1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * AMD ALSA SoC PDM Driver 4 * 5 * Copyright (C) 2021 Advanced Micro Devices, Inc. All rights reserved. 6 */ 7 8 #include "acp6x_chip_offset_byte.h" 9 10 #define ACP_DEVICE_ID 0x15E2 11 #define ACP6x_PHY_BASE_ADDRESS 0x1240000 12 #define ACP6x_REG_START 0x1240000 13 #define ACP6x_REG_END 0x1250200 14 #define ACP6x_DEVS 3 15 #define ACP6x_PDM_MODE 1 16 17 #define ACP_SOFT_RESET_SOFTRESET_AUDDONE_MASK 0x00010001 18 #define ACP_PGFSM_CNTL_POWER_ON_MASK 1 19 #define ACP_PGFSM_CNTL_POWER_OFF_MASK 0 20 #define ACP_PGFSM_STATUS_MASK 3 21 #define ACP_POWERED_ON 0 22 #define ACP_POWER_ON_IN_PROGRESS 1 23 #define ACP_POWERED_OFF 2 24 #define ACP_POWER_OFF_IN_PROGRESS 3 25 26 #define ACP_ERROR_MASK 0x20000000 27 #define ACP_EXT_INTR_STAT_CLEAR_MASK 0xFFFFFFFF 28 #define PDM_DMA_STAT 0x10 29 30 #define PDM_DMA_INTR_MASK 0x10000 31 #define ACP_ERROR_STAT 29 32 #define PDM_DECIMATION_FACTOR 2 33 #define ACP_PDM_CLK_FREQ_MASK 7 34 #define ACP_WOV_GAIN_CONTROL GENMASK(4, 3) 35 #define ACP_PDM_ENABLE 1 36 #define ACP_PDM_DISABLE 0 37 #define ACP_PDM_DMA_EN_STATUS 2 38 #define TWO_CH 2 39 #define DELAY_US 5 40 #define ACP_COUNTER 20000 41 42 #define ACP_SRAM_PTE_OFFSET 0x03800000 43 #define PAGE_SIZE_4K_ENABLE 2 44 #define PDM_PTE_OFFSET 0 45 #define PDM_MEM_WINDOW_START 0x4000000 46 47 #define CAPTURE_MIN_NUM_PERIODS 4 48 #define CAPTURE_MAX_NUM_PERIODS 4 49 #define CAPTURE_MAX_PERIOD_SIZE 8192 50 #define CAPTURE_MIN_PERIOD_SIZE 4096 51 52 #define MAX_BUFFER (CAPTURE_MAX_PERIOD_SIZE * CAPTURE_MAX_NUM_PERIODS) 53 #define MIN_BUFFER MAX_BUFFER 54 55 /* time in ms for runtime suspend delay */ 56 #define ACP_SUSPEND_DELAY_MS 2000 57 58 enum acp_config { 59 ACP_CONFIG_0 = 0, 60 ACP_CONFIG_1, 61 ACP_CONFIG_2, 62 ACP_CONFIG_3, 63 ACP_CONFIG_4, 64 ACP_CONFIG_5, 65 ACP_CONFIG_6, 66 ACP_CONFIG_7, 67 ACP_CONFIG_8, 68 ACP_CONFIG_9, 69 ACP_CONFIG_10, 70 ACP_CONFIG_11, 71 ACP_CONFIG_12, 72 ACP_CONFIG_13, 73 ACP_CONFIG_14, 74 ACP_CONFIG_15, 75 }; 76 77 struct pdm_dev_data { 78 u32 pdm_irq; 79 void __iomem *acp6x_base; 80 struct snd_pcm_substream *capture_stream; 81 }; 82 83 struct pdm_stream_instance { 84 u16 num_pages; 85 u16 channels; 86 dma_addr_t dma_addr; 87 u64 bytescount; 88 void __iomem *acp6x_base; 89 }; 90 91 union acp_pdm_dma_count { 92 struct { 93 u32 low; 94 u32 high; 95 } bcount; 96 u64 bytescount; 97 }; 98 99 static inline u32 acp6x_readl(void __iomem *base_addr) 100 { 101 return readl(base_addr - ACP6x_PHY_BASE_ADDRESS); 102 } 103 104 static inline void acp6x_writel(u32 val, void __iomem *base_addr) 105 { 106 writel(val, base_addr - ACP6x_PHY_BASE_ADDRESS); 107 } 108 109 int snd_amd_acp_find_config(struct pci_dev *pci); 110 111