1*d6a2cc9aSSyed Saba Kareem /* SPDX-License-Identifier: GPL-2.0+ */ 2*d6a2cc9aSSyed Saba Kareem /* 3*d6a2cc9aSSyed Saba Kareem * AMD ACP 6.2 Register Documentation 4*d6a2cc9aSSyed Saba Kareem * 5*d6a2cc9aSSyed Saba Kareem * Copyright 2022 Advanced Micro Devices, Inc. 6*d6a2cc9aSSyed Saba Kareem */ 7*d6a2cc9aSSyed Saba Kareem 8*d6a2cc9aSSyed Saba Kareem #ifndef _rpl_acp6x_OFFSET_HEADER 9*d6a2cc9aSSyed Saba Kareem #define _rpl_acp6x_OFFSET_HEADER 10*d6a2cc9aSSyed Saba Kareem 11*d6a2cc9aSSyed Saba Kareem /* Registers from ACP_CLKRST block */ 12*d6a2cc9aSSyed Saba Kareem #define ACP_SOFT_RESET 0x1241000 13*d6a2cc9aSSyed Saba Kareem #define ACP_CONTROL 0x1241004 14*d6a2cc9aSSyed Saba Kareem #define ACP_STATUS 0x1241008 15*d6a2cc9aSSyed Saba Kareem #define ACP_DYNAMIC_CG_MASTER_CONTROL 0x1241010 16*d6a2cc9aSSyed Saba Kareem #define ACP_PGFSM_CONTROL 0x124101C 17*d6a2cc9aSSyed Saba Kareem #define ACP_PGFSM_STATUS 0x1241020 18*d6a2cc9aSSyed Saba Kareem #define ACP_CLKMUX_SEL 0x1241024 19*d6a2cc9aSSyed Saba Kareem 20*d6a2cc9aSSyed Saba Kareem /* Registers from ACP_AON block */ 21*d6a2cc9aSSyed Saba Kareem #define ACP_PME_EN 0x1241400 22*d6a2cc9aSSyed Saba Kareem #define ACP_DEVICE_STATE 0x1241404 23*d6a2cc9aSSyed Saba Kareem #define AZ_DEVICE_STATE 0x1241408 24*d6a2cc9aSSyed Saba Kareem #define ACP_PIN_CONFIG 0x1241440 25*d6a2cc9aSSyed Saba Kareem #define ACP_PAD_PULLUP_CTRL 0x1241444 26*d6a2cc9aSSyed Saba Kareem #define ACP_PAD_PULLDOWN_CTRL 0x1241448 27*d6a2cc9aSSyed Saba Kareem #define ACP_PAD_DRIVE_STRENGTH_CTRL 0x124144C 28*d6a2cc9aSSyed Saba Kareem #define ACP_PAD_SCHMEN_CTRL 0x1241450 29*d6a2cc9aSSyed Saba Kareem 30*d6a2cc9aSSyed Saba Kareem #endif 31