1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * AMD ALSA SoC PCM Driver 4 * 5 * Copyright 2016 Advanced Micro Devices, Inc. 6 */ 7 8 #include "chip_offset_byte.h" 9 10 #define ACP3x_PHY_BASE_ADDRESS 0x1240000 11 #define ACP3x_I2S_MODE 0 12 #define ACP3x_REG_START 0x1240000 13 #define ACP3x_REG_END 0x1250200 14 #define I2S_MODE 0x04 15 #define BT_TX_THRESHOLD 26 16 #define BT_RX_THRESHOLD 25 17 #define ACP3x_POWER_ON 0x00 18 #define ACP3x_POWER_ON_IN_PROGRESS 0x01 19 #define ACP3x_POWER_OFF 0x02 20 #define ACP3x_POWER_OFF_IN_PROGRESS 0x03 21 #define ACP3x_SOFT_RESET__SoftResetAudDone_MASK 0x00010001 22 23 #define ACP_SRAM_PTE_OFFSET 0x02050000 24 #define PAGE_SIZE_4K_ENABLE 0x2 25 #define MEM_WINDOW_START 0x4000000 26 #define PLAYBACK_FIFO_ADDR_OFFSET 0x400 27 #define CAPTURE_FIFO_ADDR_OFFSET 0x500 28 29 #define PLAYBACK_MIN_NUM_PERIODS 2 30 #define PLAYBACK_MAX_NUM_PERIODS 8 31 #define PLAYBACK_MAX_PERIOD_SIZE 16384 32 #define PLAYBACK_MIN_PERIOD_SIZE 4096 33 #define CAPTURE_MIN_NUM_PERIODS 2 34 #define CAPTURE_MAX_NUM_PERIODS 8 35 #define CAPTURE_MAX_PERIOD_SIZE 16384 36 #define CAPTURE_MIN_PERIOD_SIZE 4096 37 38 #define MAX_BUFFER (PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS) 39 #define MIN_BUFFER MAX_BUFFER 40 #define FIFO_SIZE 0x100 41 #define DMA_SIZE 0x40 42 #define FRM_LEN 0x100 43 44 #define SLOT_WIDTH_8 0x08 45 #define SLOT_WIDTH_16 0x10 46 #define SLOT_WIDTH_24 0x18 47 #define SLOT_WIDTH_32 0x20 48 49 50 static inline u32 rv_readl(void __iomem *base_addr) 51 { 52 return readl(base_addr - ACP3x_PHY_BASE_ADDRESS); 53 } 54 55 static inline void rv_writel(u32 val, void __iomem *base_addr) 56 { 57 writel(val, base_addr - ACP3x_PHY_BASE_ADDRESS); 58 } 59