1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * AMD ALSA SoC PDM Driver 4 * 5 * Copyright (C) 2022, 2023 Advanced Micro Devices, Inc. All rights reserved. 6 */ 7 8 #include <sound/acp63_chip_offset_byte.h> 9 10 #define ACP_DEVICE_ID 0x15E2 11 #define ACP63_REG_START 0x1240000 12 #define ACP63_REG_END 0x1250200 13 #define ACP63_DEVS 5 14 15 #define ACP_SOFT_RESET_SOFTRESET_AUDDONE_MASK 0x00010001 16 #define ACP_PGFSM_CNTL_POWER_ON_MASK 1 17 #define ACP_PGFSM_CNTL_POWER_OFF_MASK 0 18 #define ACP_PGFSM_STATUS_MASK 3 19 #define ACP_POWERED_ON 0 20 #define ACP_POWER_ON_IN_PROGRESS 1 21 #define ACP_POWERED_OFF 2 22 #define ACP_POWER_OFF_IN_PROGRESS 3 23 24 #define ACP_ERROR_MASK 0x20000000 25 #define ACP_EXT_INTR_STAT_CLEAR_MASK 0xFFFFFFFF 26 #define PDM_DMA_STAT 0x10 27 28 #define PDM_DMA_INTR_MASK 0x10000 29 #define ACP_ERROR_STAT 29 30 #define PDM_DECIMATION_FACTOR 2 31 #define ACP_PDM_CLK_FREQ_MASK 7 32 #define ACP_WOV_GAIN_CONTROL GENMASK(4, 3) 33 #define ACP_PDM_ENABLE 1 34 #define ACP_PDM_DISABLE 0 35 #define ACP_PDM_DMA_EN_STATUS 2 36 #define TWO_CH 2 37 #define DELAY_US 5 38 #define ACP_COUNTER 20000 39 40 #define ACP_SRAM_PTE_OFFSET 0x03800000 41 #define PAGE_SIZE_4K_ENABLE 2 42 #define PDM_PTE_OFFSET 0 43 #define PDM_MEM_WINDOW_START 0x4000000 44 45 #define CAPTURE_MIN_NUM_PERIODS 4 46 #define CAPTURE_MAX_NUM_PERIODS 4 47 #define CAPTURE_MAX_PERIOD_SIZE 8192 48 #define CAPTURE_MIN_PERIOD_SIZE 4096 49 50 #define MAX_BUFFER (CAPTURE_MAX_PERIOD_SIZE * CAPTURE_MAX_NUM_PERIODS) 51 #define MIN_BUFFER MAX_BUFFER 52 53 /* time in ms for runtime suspend delay */ 54 #define ACP_SUSPEND_DELAY_MS 2000 55 56 #define ACP_DMIC_DEV 2 57 58 /* ACP63_PDM_MODE_DEVS corresponds to platform devices count for ACP PDM configuration */ 59 #define ACP63_PDM_MODE_DEVS 3 60 61 /* 62 * ACP63_SDW0_MODE_DEVS corresponds to platform devices count for 63 * SW0 SoundWire manager instance configuration 64 */ 65 #define ACP63_SDW0_MODE_DEVS 2 66 67 /* 68 * ACP63_SDW0_SDW1_MODE_DEVS corresponds to platform devices count for SW0 + SW1 SoundWire manager 69 * instances configuration 70 */ 71 #define ACP63_SDW0_SDW1_MODE_DEVS 3 72 73 /* 74 * ACP63_SDW0_PDM_MODE_DEVS corresponds to platform devices count for SW0 manager 75 * instance + ACP PDM controller configuration 76 */ 77 #define ACP63_SDW0_PDM_MODE_DEVS 4 78 79 /* 80 * ACP63_SDW0_SDW1_PDM_MODE_DEVS corresponds to platform devices count for 81 * SW0 + SW1 SoundWire manager instances + ACP PDM controller configuration 82 */ 83 #define ACP63_SDW0_SDW1_PDM_MODE_DEVS 5 84 #define ACP63_DMIC_ADDR 2 85 #define ACP63_SDW_ADDR 5 86 #define AMD_SDW_MAX_MANAGERS 2 87 88 /* time in ms for acp timeout */ 89 #define ACP_TIMEOUT 500 90 91 /* ACP63_PDM_DEV_CONFIG corresponds to platform device configuration for ACP PDM controller */ 92 #define ACP63_PDM_DEV_CONFIG BIT(0) 93 94 /* ACP63_SDW_DEV_CONFIG corresponds to platform device configuration for SDW manager instances */ 95 #define ACP63_SDW_DEV_CONFIG BIT(1) 96 97 /* 98 * ACP63_SDW_PDM_DEV_CONFIG corresponds to platform device configuration for ACP PDM + SoundWire 99 * manager instance combination. 100 */ 101 #define ACP63_SDW_PDM_DEV_CONFIG GENMASK(1, 0) 102 #define ACP_SDW0_STAT BIT(21) 103 #define ACP_SDW1_STAT BIT(2) 104 #define ACP_ERROR_IRQ BIT(29) 105 106 #define ACP_AUDIO0_TX_THRESHOLD 0x1c 107 #define ACP_AUDIO1_TX_THRESHOLD 0x1a 108 #define ACP_AUDIO2_TX_THRESHOLD 0x18 109 #define ACP_AUDIO0_RX_THRESHOLD 0x1b 110 #define ACP_AUDIO1_RX_THRESHOLD 0x19 111 #define ACP_AUDIO2_RX_THRESHOLD 0x17 112 #define ACP_P1_AUDIO1_TX_THRESHOLD BIT(6) 113 #define ACP_P1_AUDIO1_RX_THRESHOLD BIT(5) 114 #define ACP_SDW_DMA_IRQ_MASK 0x1F800000 115 #define ACP_P1_SDW_DMA_IRQ_MASK 0x60 116 #define ACP63_SDW0_DMA_MAX_STREAMS 6 117 #define ACP63_SDW1_DMA_MAX_STREAMS 2 118 #define ACP_P1_AUDIO_TX_THRESHOLD 6 119 #define SDW0_DMA_TX_IRQ_MASK(i) (ACP_AUDIO0_TX_THRESHOLD - (2 * (i))) 120 #define SDW0_DMA_RX_IRQ_MASK(i) (ACP_AUDIO0_RX_THRESHOLD - (2 * (i))) 121 #define SDW1_DMA_IRQ_MASK(i) (ACP_P1_AUDIO_TX_THRESHOLD - (i)) 122 123 #define ACP_DELAY_US 5 124 #define ACP_SDW_RING_BUFF_ADDR_OFFSET (128 * 1024) 125 #define SDW0_MEM_WINDOW_START 0x4800000 126 #define ACP_SDW_SRAM_PTE_OFFSET 0x03800400 127 #define SDW0_PTE_OFFSET 0x400 128 #define SDW_FIFO_SIZE 0x100 129 #define SDW_DMA_SIZE 0x40 130 #define ACP_SDW0_FIFO_OFFSET 0x100 131 #define ACP_SDW_PTE_OFFSET 0x100 132 #define SDW_FIFO_OFFSET 0x100 133 #define SDW_PTE_OFFSET(i) (SDW0_PTE_OFFSET + ((i) * 0x600)) 134 #define ACP_SDW_FIFO_OFFSET(i) (ACP_SDW0_FIFO_OFFSET + ((i) * 0x500)) 135 #define SDW_MEM_WINDOW_START(i) (SDW0_MEM_WINDOW_START + ((i) * 0xC0000)) 136 137 #define SDW_PLAYBACK_MIN_NUM_PERIODS 2 138 #define SDW_PLAYBACK_MAX_NUM_PERIODS 8 139 #define SDW_PLAYBACK_MAX_PERIOD_SIZE 8192 140 #define SDW_PLAYBACK_MIN_PERIOD_SIZE 1024 141 #define SDW_CAPTURE_MIN_NUM_PERIODS 2 142 #define SDW_CAPTURE_MAX_NUM_PERIODS 8 143 #define SDW_CAPTURE_MAX_PERIOD_SIZE 8192 144 #define SDW_CAPTURE_MIN_PERIOD_SIZE 1024 145 146 #define SDW_MAX_BUFFER (SDW_PLAYBACK_MAX_PERIOD_SIZE * SDW_PLAYBACK_MAX_NUM_PERIODS) 147 #define SDW_MIN_BUFFER SDW_MAX_BUFFER 148 149 enum acp_config { 150 ACP_CONFIG_0 = 0, 151 ACP_CONFIG_1, 152 ACP_CONFIG_2, 153 ACP_CONFIG_3, 154 ACP_CONFIG_4, 155 ACP_CONFIG_5, 156 ACP_CONFIG_6, 157 ACP_CONFIG_7, 158 ACP_CONFIG_8, 159 ACP_CONFIG_9, 160 ACP_CONFIG_10, 161 ACP_CONFIG_11, 162 ACP_CONFIG_12, 163 ACP_CONFIG_13, 164 ACP_CONFIG_14, 165 ACP_CONFIG_15, 166 }; 167 168 enum amd_sdw0_channel { 169 ACP_SDW0_AUDIO0_TX = 0, 170 ACP_SDW0_AUDIO1_TX, 171 ACP_SDW0_AUDIO2_TX, 172 ACP_SDW0_AUDIO0_RX, 173 ACP_SDW0_AUDIO1_RX, 174 ACP_SDW0_AUDIO2_RX, 175 }; 176 177 enum amd_sdw1_channel { 178 ACP_SDW1_AUDIO1_TX, 179 ACP_SDW1_AUDIO1_RX, 180 }; 181 182 struct pdm_stream_instance { 183 u16 num_pages; 184 u16 channels; 185 dma_addr_t dma_addr; 186 u64 bytescount; 187 void __iomem *acp63_base; 188 }; 189 190 struct pdm_dev_data { 191 u32 pdm_irq; 192 void __iomem *acp63_base; 193 struct mutex *acp_lock; 194 struct snd_pcm_substream *capture_stream; 195 }; 196 197 struct sdw_dma_dev_data { 198 void __iomem *acp_base; 199 struct mutex *acp_lock; /* used to protect acp common register access */ 200 struct snd_pcm_substream *sdw0_dma_stream[ACP63_SDW0_DMA_MAX_STREAMS]; 201 struct snd_pcm_substream *sdw1_dma_stream[ACP63_SDW1_DMA_MAX_STREAMS]; 202 }; 203 204 struct acp_sdw_dma_stream { 205 u16 num_pages; 206 u16 channels; 207 u32 stream_id; 208 u32 instance; 209 dma_addr_t dma_addr; 210 u64 bytescount; 211 }; 212 213 union acp_sdw_dma_count { 214 struct { 215 u32 low; 216 u32 high; 217 } bcount; 218 u64 bytescount; 219 }; 220 221 struct sdw_dma_ring_buf_reg { 222 u32 reg_dma_size; 223 u32 reg_fifo_addr; 224 u32 reg_fifo_size; 225 u32 reg_ring_buf_size; 226 u32 reg_ring_buf_addr; 227 u32 water_mark_size_reg; 228 u32 pos_low_reg; 229 u32 pos_high_reg; 230 }; 231 232 /** 233 * struct acp63_dev_data - acp pci driver context 234 * @acp63_base: acp mmio base 235 * @res: resource 236 * @pdev: array of child platform device node structures 237 * @acp_lock: used to protect acp common registers 238 * @sdw_fw_node: SoundWire controller fw node handle 239 * @pdev_config: platform device configuration 240 * @pdev_count: platform devices count 241 * @pdm_dev_index: pdm platform device index 242 * @sdw_manager_count: SoundWire manager instance count 243 * @sdw0_dev_index: SoundWire Manager-0 platform device index 244 * @sdw1_dev_index: SoundWire Manager-1 platform device index 245 * @sdw_dma_dev_index: SoundWire DMA controller platform device index 246 * @sdw0-dma_intr_stat: DMA interrupt status array for SoundWire manager-SW0 instance 247 * @sdw_dma_intr_stat: DMA interrupt status array for SoundWire manager-SW1 instance 248 * @acp_reset: flag set to true when bus reset is applied across all 249 * the active SoundWire manager instances 250 */ 251 252 struct acp63_dev_data { 253 void __iomem *acp63_base; 254 struct resource *res; 255 struct platform_device *pdev[ACP63_DEVS]; 256 struct mutex acp_lock; /* protect shared registers */ 257 struct fwnode_handle *sdw_fw_node; 258 u16 pdev_config; 259 u16 pdev_count; 260 u16 pdm_dev_index; 261 u8 sdw_manager_count; 262 u16 sdw0_dev_index; 263 u16 sdw1_dev_index; 264 u16 sdw_dma_dev_index; 265 u16 sdw0_dma_intr_stat[ACP63_SDW0_DMA_MAX_STREAMS]; 266 u16 sdw1_dma_intr_stat[ACP63_SDW1_DMA_MAX_STREAMS]; 267 bool acp_reset; 268 }; 269 270 int snd_amd_acp_find_config(struct pci_dev *pci); 271