1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * ACP_2_2 Register documentation 4 * 5 * Copyright (C) 2014 Advanced Micro Devices, Inc. 6 */ 7 8 #ifndef ACP_2_2_ENUM_H 9 #define ACP_2_2_ENUM_H 10 11 typedef enum DebugBlockId { 12 DBG_BLOCK_ID_RESERVED = 0x0, 13 DBG_BLOCK_ID_DBG = 0x1, 14 DBG_BLOCK_ID_VMC = 0x2, 15 DBG_BLOCK_ID_PDMA = 0x3, 16 DBG_BLOCK_ID_CG = 0x4, 17 DBG_BLOCK_ID_SRBM = 0x5, 18 DBG_BLOCK_ID_GRBM = 0x6, 19 DBG_BLOCK_ID_RLC = 0x7, 20 DBG_BLOCK_ID_CSC = 0x8, 21 DBG_BLOCK_ID_SEM = 0x9, 22 DBG_BLOCK_ID_IH = 0xa, 23 DBG_BLOCK_ID_SC = 0xb, 24 DBG_BLOCK_ID_SQ = 0xc, 25 DBG_BLOCK_ID_UVDU = 0xd, 26 DBG_BLOCK_ID_SQA = 0xe, 27 DBG_BLOCK_ID_SDMA0 = 0xf, 28 DBG_BLOCK_ID_SDMA1 = 0x10, 29 DBG_BLOCK_ID_SPIM = 0x11, 30 DBG_BLOCK_ID_GDS = 0x12, 31 DBG_BLOCK_ID_VC0 = 0x13, 32 DBG_BLOCK_ID_VC1 = 0x14, 33 DBG_BLOCK_ID_PA0 = 0x15, 34 DBG_BLOCK_ID_PA1 = 0x16, 35 DBG_BLOCK_ID_CP0 = 0x17, 36 DBG_BLOCK_ID_CP1 = 0x18, 37 DBG_BLOCK_ID_CP2 = 0x19, 38 DBG_BLOCK_ID_XBR = 0x1a, 39 DBG_BLOCK_ID_UVDM = 0x1b, 40 DBG_BLOCK_ID_VGT0 = 0x1c, 41 DBG_BLOCK_ID_VGT1 = 0x1d, 42 DBG_BLOCK_ID_IA = 0x1e, 43 DBG_BLOCK_ID_SXM0 = 0x1f, 44 DBG_BLOCK_ID_SXM1 = 0x20, 45 DBG_BLOCK_ID_SCT0 = 0x21, 46 DBG_BLOCK_ID_SCT1 = 0x22, 47 DBG_BLOCK_ID_SPM0 = 0x23, 48 DBG_BLOCK_ID_SPM1 = 0x24, 49 DBG_BLOCK_ID_UNUSED0 = 0x25, 50 DBG_BLOCK_ID_UNUSED1 = 0x26, 51 DBG_BLOCK_ID_TCAA = 0x27, 52 DBG_BLOCK_ID_TCAB = 0x28, 53 DBG_BLOCK_ID_TCCA = 0x29, 54 DBG_BLOCK_ID_TCCB = 0x2a, 55 DBG_BLOCK_ID_MCC0 = 0x2b, 56 DBG_BLOCK_ID_MCC1 = 0x2c, 57 DBG_BLOCK_ID_MCC2 = 0x2d, 58 DBG_BLOCK_ID_MCC3 = 0x2e, 59 DBG_BLOCK_ID_SXS0 = 0x2f, 60 DBG_BLOCK_ID_SXS1 = 0x30, 61 DBG_BLOCK_ID_SXS2 = 0x31, 62 DBG_BLOCK_ID_SXS3 = 0x32, 63 DBG_BLOCK_ID_SXS4 = 0x33, 64 DBG_BLOCK_ID_SXS5 = 0x34, 65 DBG_BLOCK_ID_SXS6 = 0x35, 66 DBG_BLOCK_ID_SXS7 = 0x36, 67 DBG_BLOCK_ID_SXS8 = 0x37, 68 DBG_BLOCK_ID_SXS9 = 0x38, 69 DBG_BLOCK_ID_BCI0 = 0x39, 70 DBG_BLOCK_ID_BCI1 = 0x3a, 71 DBG_BLOCK_ID_BCI2 = 0x3b, 72 DBG_BLOCK_ID_BCI3 = 0x3c, 73 DBG_BLOCK_ID_MCB = 0x3d, 74 DBG_BLOCK_ID_UNUSED6 = 0x3e, 75 DBG_BLOCK_ID_SQA00 = 0x3f, 76 DBG_BLOCK_ID_SQA01 = 0x40, 77 DBG_BLOCK_ID_SQA02 = 0x41, 78 DBG_BLOCK_ID_SQA10 = 0x42, 79 DBG_BLOCK_ID_SQA11 = 0x43, 80 DBG_BLOCK_ID_SQA12 = 0x44, 81 DBG_BLOCK_ID_UNUSED7 = 0x45, 82 DBG_BLOCK_ID_UNUSED8 = 0x46, 83 DBG_BLOCK_ID_SQB00 = 0x47, 84 DBG_BLOCK_ID_SQB01 = 0x48, 85 DBG_BLOCK_ID_SQB10 = 0x49, 86 DBG_BLOCK_ID_SQB11 = 0x4a, 87 DBG_BLOCK_ID_SQ00 = 0x4b, 88 DBG_BLOCK_ID_SQ01 = 0x4c, 89 DBG_BLOCK_ID_SQ10 = 0x4d, 90 DBG_BLOCK_ID_SQ11 = 0x4e, 91 DBG_BLOCK_ID_CB00 = 0x4f, 92 DBG_BLOCK_ID_CB01 = 0x50, 93 DBG_BLOCK_ID_CB02 = 0x51, 94 DBG_BLOCK_ID_CB03 = 0x52, 95 DBG_BLOCK_ID_CB04 = 0x53, 96 DBG_BLOCK_ID_UNUSED9 = 0x54, 97 DBG_BLOCK_ID_UNUSED10 = 0x55, 98 DBG_BLOCK_ID_UNUSED11 = 0x56, 99 DBG_BLOCK_ID_CB10 = 0x57, 100 DBG_BLOCK_ID_CB11 = 0x58, 101 DBG_BLOCK_ID_CB12 = 0x59, 102 DBG_BLOCK_ID_CB13 = 0x5a, 103 DBG_BLOCK_ID_CB14 = 0x5b, 104 DBG_BLOCK_ID_UNUSED12 = 0x5c, 105 DBG_BLOCK_ID_UNUSED13 = 0x5d, 106 DBG_BLOCK_ID_UNUSED14 = 0x5e, 107 DBG_BLOCK_ID_TCP0 = 0x5f, 108 DBG_BLOCK_ID_TCP1 = 0x60, 109 DBG_BLOCK_ID_TCP2 = 0x61, 110 DBG_BLOCK_ID_TCP3 = 0x62, 111 DBG_BLOCK_ID_TCP4 = 0x63, 112 DBG_BLOCK_ID_TCP5 = 0x64, 113 DBG_BLOCK_ID_TCP6 = 0x65, 114 DBG_BLOCK_ID_TCP7 = 0x66, 115 DBG_BLOCK_ID_TCP8 = 0x67, 116 DBG_BLOCK_ID_TCP9 = 0x68, 117 DBG_BLOCK_ID_TCP10 = 0x69, 118 DBG_BLOCK_ID_TCP11 = 0x6a, 119 DBG_BLOCK_ID_TCP12 = 0x6b, 120 DBG_BLOCK_ID_TCP13 = 0x6c, 121 DBG_BLOCK_ID_TCP14 = 0x6d, 122 DBG_BLOCK_ID_TCP15 = 0x6e, 123 DBG_BLOCK_ID_TCP16 = 0x6f, 124 DBG_BLOCK_ID_TCP17 = 0x70, 125 DBG_BLOCK_ID_TCP18 = 0x71, 126 DBG_BLOCK_ID_TCP19 = 0x72, 127 DBG_BLOCK_ID_TCP20 = 0x73, 128 DBG_BLOCK_ID_TCP21 = 0x74, 129 DBG_BLOCK_ID_TCP22 = 0x75, 130 DBG_BLOCK_ID_TCP23 = 0x76, 131 DBG_BLOCK_ID_TCP_RESERVED0 = 0x77, 132 DBG_BLOCK_ID_TCP_RESERVED1 = 0x78, 133 DBG_BLOCK_ID_TCP_RESERVED2 = 0x79, 134 DBG_BLOCK_ID_TCP_RESERVED3 = 0x7a, 135 DBG_BLOCK_ID_TCP_RESERVED4 = 0x7b, 136 DBG_BLOCK_ID_TCP_RESERVED5 = 0x7c, 137 DBG_BLOCK_ID_TCP_RESERVED6 = 0x7d, 138 DBG_BLOCK_ID_TCP_RESERVED7 = 0x7e, 139 DBG_BLOCK_ID_DB00 = 0x7f, 140 DBG_BLOCK_ID_DB01 = 0x80, 141 DBG_BLOCK_ID_DB02 = 0x81, 142 DBG_BLOCK_ID_DB03 = 0x82, 143 DBG_BLOCK_ID_DB04 = 0x83, 144 DBG_BLOCK_ID_UNUSED15 = 0x84, 145 DBG_BLOCK_ID_UNUSED16 = 0x85, 146 DBG_BLOCK_ID_UNUSED17 = 0x86, 147 DBG_BLOCK_ID_DB10 = 0x87, 148 DBG_BLOCK_ID_DB11 = 0x88, 149 DBG_BLOCK_ID_DB12 = 0x89, 150 DBG_BLOCK_ID_DB13 = 0x8a, 151 DBG_BLOCK_ID_DB14 = 0x8b, 152 DBG_BLOCK_ID_UNUSED18 = 0x8c, 153 DBG_BLOCK_ID_UNUSED19 = 0x8d, 154 DBG_BLOCK_ID_UNUSED20 = 0x8e, 155 DBG_BLOCK_ID_TCC0 = 0x8f, 156 DBG_BLOCK_ID_TCC1 = 0x90, 157 DBG_BLOCK_ID_TCC2 = 0x91, 158 DBG_BLOCK_ID_TCC3 = 0x92, 159 DBG_BLOCK_ID_TCC4 = 0x93, 160 DBG_BLOCK_ID_TCC5 = 0x94, 161 DBG_BLOCK_ID_TCC6 = 0x95, 162 DBG_BLOCK_ID_TCC7 = 0x96, 163 DBG_BLOCK_ID_SPS00 = 0x97, 164 DBG_BLOCK_ID_SPS01 = 0x98, 165 DBG_BLOCK_ID_SPS02 = 0x99, 166 DBG_BLOCK_ID_SPS10 = 0x9a, 167 DBG_BLOCK_ID_SPS11 = 0x9b, 168 DBG_BLOCK_ID_SPS12 = 0x9c, 169 DBG_BLOCK_ID_UNUSED21 = 0x9d, 170 DBG_BLOCK_ID_UNUSED22 = 0x9e, 171 DBG_BLOCK_ID_TA00 = 0x9f, 172 DBG_BLOCK_ID_TA01 = 0xa0, 173 DBG_BLOCK_ID_TA02 = 0xa1, 174 DBG_BLOCK_ID_TA03 = 0xa2, 175 DBG_BLOCK_ID_TA04 = 0xa3, 176 DBG_BLOCK_ID_TA05 = 0xa4, 177 DBG_BLOCK_ID_TA06 = 0xa5, 178 DBG_BLOCK_ID_TA07 = 0xa6, 179 DBG_BLOCK_ID_TA08 = 0xa7, 180 DBG_BLOCK_ID_TA09 = 0xa8, 181 DBG_BLOCK_ID_TA0A = 0xa9, 182 DBG_BLOCK_ID_TA0B = 0xaa, 183 DBG_BLOCK_ID_UNUSED23 = 0xab, 184 DBG_BLOCK_ID_UNUSED24 = 0xac, 185 DBG_BLOCK_ID_UNUSED25 = 0xad, 186 DBG_BLOCK_ID_UNUSED26 = 0xae, 187 DBG_BLOCK_ID_TA10 = 0xaf, 188 DBG_BLOCK_ID_TA11 = 0xb0, 189 DBG_BLOCK_ID_TA12 = 0xb1, 190 DBG_BLOCK_ID_TA13 = 0xb2, 191 DBG_BLOCK_ID_TA14 = 0xb3, 192 DBG_BLOCK_ID_TA15 = 0xb4, 193 DBG_BLOCK_ID_TA16 = 0xb5, 194 DBG_BLOCK_ID_TA17 = 0xb6, 195 DBG_BLOCK_ID_TA18 = 0xb7, 196 DBG_BLOCK_ID_TA19 = 0xb8, 197 DBG_BLOCK_ID_TA1A = 0xb9, 198 DBG_BLOCK_ID_TA1B = 0xba, 199 DBG_BLOCK_ID_UNUSED27 = 0xbb, 200 DBG_BLOCK_ID_UNUSED28 = 0xbc, 201 DBG_BLOCK_ID_UNUSED29 = 0xbd, 202 DBG_BLOCK_ID_UNUSED30 = 0xbe, 203 DBG_BLOCK_ID_TD00 = 0xbf, 204 DBG_BLOCK_ID_TD01 = 0xc0, 205 DBG_BLOCK_ID_TD02 = 0xc1, 206 DBG_BLOCK_ID_TD03 = 0xc2, 207 DBG_BLOCK_ID_TD04 = 0xc3, 208 DBG_BLOCK_ID_TD05 = 0xc4, 209 DBG_BLOCK_ID_TD06 = 0xc5, 210 DBG_BLOCK_ID_TD07 = 0xc6, 211 DBG_BLOCK_ID_TD08 = 0xc7, 212 DBG_BLOCK_ID_TD09 = 0xc8, 213 DBG_BLOCK_ID_TD0A = 0xc9, 214 DBG_BLOCK_ID_TD0B = 0xca, 215 DBG_BLOCK_ID_UNUSED31 = 0xcb, 216 DBG_BLOCK_ID_UNUSED32 = 0xcc, 217 DBG_BLOCK_ID_UNUSED33 = 0xcd, 218 DBG_BLOCK_ID_UNUSED34 = 0xce, 219 DBG_BLOCK_ID_TD10 = 0xcf, 220 DBG_BLOCK_ID_TD11 = 0xd0, 221 DBG_BLOCK_ID_TD12 = 0xd1, 222 DBG_BLOCK_ID_TD13 = 0xd2, 223 DBG_BLOCK_ID_TD14 = 0xd3, 224 DBG_BLOCK_ID_TD15 = 0xd4, 225 DBG_BLOCK_ID_TD16 = 0xd5, 226 DBG_BLOCK_ID_TD17 = 0xd6, 227 DBG_BLOCK_ID_TD18 = 0xd7, 228 DBG_BLOCK_ID_TD19 = 0xd8, 229 DBG_BLOCK_ID_TD1A = 0xd9, 230 DBG_BLOCK_ID_TD1B = 0xda, 231 DBG_BLOCK_ID_UNUSED35 = 0xdb, 232 DBG_BLOCK_ID_UNUSED36 = 0xdc, 233 DBG_BLOCK_ID_UNUSED37 = 0xdd, 234 DBG_BLOCK_ID_UNUSED38 = 0xde, 235 DBG_BLOCK_ID_LDS00 = 0xdf, 236 DBG_BLOCK_ID_LDS01 = 0xe0, 237 DBG_BLOCK_ID_LDS02 = 0xe1, 238 DBG_BLOCK_ID_LDS03 = 0xe2, 239 DBG_BLOCK_ID_LDS04 = 0xe3, 240 DBG_BLOCK_ID_LDS05 = 0xe4, 241 DBG_BLOCK_ID_LDS06 = 0xe5, 242 DBG_BLOCK_ID_LDS07 = 0xe6, 243 DBG_BLOCK_ID_LDS08 = 0xe7, 244 DBG_BLOCK_ID_LDS09 = 0xe8, 245 DBG_BLOCK_ID_LDS0A = 0xe9, 246 DBG_BLOCK_ID_LDS0B = 0xea, 247 DBG_BLOCK_ID_UNUSED39 = 0xeb, 248 DBG_BLOCK_ID_UNUSED40 = 0xec, 249 DBG_BLOCK_ID_UNUSED41 = 0xed, 250 DBG_BLOCK_ID_UNUSED42 = 0xee, 251 DBG_BLOCK_ID_LDS10 = 0xef, 252 DBG_BLOCK_ID_LDS11 = 0xf0, 253 DBG_BLOCK_ID_LDS12 = 0xf1, 254 DBG_BLOCK_ID_LDS13 = 0xf2, 255 DBG_BLOCK_ID_LDS14 = 0xf3, 256 DBG_BLOCK_ID_LDS15 = 0xf4, 257 DBG_BLOCK_ID_LDS16 = 0xf5, 258 DBG_BLOCK_ID_LDS17 = 0xf6, 259 DBG_BLOCK_ID_LDS18 = 0xf7, 260 DBG_BLOCK_ID_LDS19 = 0xf8, 261 DBG_BLOCK_ID_LDS1A = 0xf9, 262 DBG_BLOCK_ID_LDS1B = 0xfa, 263 DBG_BLOCK_ID_UNUSED43 = 0xfb, 264 DBG_BLOCK_ID_UNUSED44 = 0xfc, 265 DBG_BLOCK_ID_UNUSED45 = 0xfd, 266 DBG_BLOCK_ID_UNUSED46 = 0xfe, 267 } DebugBlockId; 268 typedef enum DebugBlockId_BY2 { 269 DBG_BLOCK_ID_RESERVED_BY2 = 0x0, 270 DBG_BLOCK_ID_VMC_BY2 = 0x1, 271 DBG_BLOCK_ID_UNUSED0_BY2 = 0x2, 272 DBG_BLOCK_ID_GRBM_BY2 = 0x3, 273 DBG_BLOCK_ID_CSC_BY2 = 0x4, 274 DBG_BLOCK_ID_IH_BY2 = 0x5, 275 DBG_BLOCK_ID_SQ_BY2 = 0x6, 276 DBG_BLOCK_ID_UVD_BY2 = 0x7, 277 DBG_BLOCK_ID_SDMA0_BY2 = 0x8, 278 DBG_BLOCK_ID_SPIM_BY2 = 0x9, 279 DBG_BLOCK_ID_VC0_BY2 = 0xa, 280 DBG_BLOCK_ID_PA_BY2 = 0xb, 281 DBG_BLOCK_ID_CP0_BY2 = 0xc, 282 DBG_BLOCK_ID_CP2_BY2 = 0xd, 283 DBG_BLOCK_ID_PC0_BY2 = 0xe, 284 DBG_BLOCK_ID_BCI0_BY2 = 0xf, 285 DBG_BLOCK_ID_SXM0_BY2 = 0x10, 286 DBG_BLOCK_ID_SCT0_BY2 = 0x11, 287 DBG_BLOCK_ID_SPM0_BY2 = 0x12, 288 DBG_BLOCK_ID_BCI2_BY2 = 0x13, 289 DBG_BLOCK_ID_TCA_BY2 = 0x14, 290 DBG_BLOCK_ID_TCCA_BY2 = 0x15, 291 DBG_BLOCK_ID_MCC_BY2 = 0x16, 292 DBG_BLOCK_ID_MCC2_BY2 = 0x17, 293 DBG_BLOCK_ID_MCD_BY2 = 0x18, 294 DBG_BLOCK_ID_MCD2_BY2 = 0x19, 295 DBG_BLOCK_ID_MCD4_BY2 = 0x1a, 296 DBG_BLOCK_ID_MCB_BY2 = 0x1b, 297 DBG_BLOCK_ID_SQA_BY2 = 0x1c, 298 DBG_BLOCK_ID_SQA02_BY2 = 0x1d, 299 DBG_BLOCK_ID_SQA11_BY2 = 0x1e, 300 DBG_BLOCK_ID_UNUSED8_BY2 = 0x1f, 301 DBG_BLOCK_ID_SQB_BY2 = 0x20, 302 DBG_BLOCK_ID_SQB10_BY2 = 0x21, 303 DBG_BLOCK_ID_UNUSED10_BY2 = 0x22, 304 DBG_BLOCK_ID_UNUSED12_BY2 = 0x23, 305 DBG_BLOCK_ID_CB_BY2 = 0x24, 306 DBG_BLOCK_ID_CB02_BY2 = 0x25, 307 DBG_BLOCK_ID_CB10_BY2 = 0x26, 308 DBG_BLOCK_ID_CB12_BY2 = 0x27, 309 DBG_BLOCK_ID_SXS_BY2 = 0x28, 310 DBG_BLOCK_ID_SXS2_BY2 = 0x29, 311 DBG_BLOCK_ID_SXS4_BY2 = 0x2a, 312 DBG_BLOCK_ID_SXS6_BY2 = 0x2b, 313 DBG_BLOCK_ID_DB_BY2 = 0x2c, 314 DBG_BLOCK_ID_DB02_BY2 = 0x2d, 315 DBG_BLOCK_ID_DB10_BY2 = 0x2e, 316 DBG_BLOCK_ID_DB12_BY2 = 0x2f, 317 DBG_BLOCK_ID_TCP_BY2 = 0x30, 318 DBG_BLOCK_ID_TCP2_BY2 = 0x31, 319 DBG_BLOCK_ID_TCP4_BY2 = 0x32, 320 DBG_BLOCK_ID_TCP6_BY2 = 0x33, 321 DBG_BLOCK_ID_TCP8_BY2 = 0x34, 322 DBG_BLOCK_ID_TCP10_BY2 = 0x35, 323 DBG_BLOCK_ID_TCP12_BY2 = 0x36, 324 DBG_BLOCK_ID_TCP14_BY2 = 0x37, 325 DBG_BLOCK_ID_TCP16_BY2 = 0x38, 326 DBG_BLOCK_ID_TCP18_BY2 = 0x39, 327 DBG_BLOCK_ID_TCP20_BY2 = 0x3a, 328 DBG_BLOCK_ID_TCP22_BY2 = 0x3b, 329 DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c, 330 DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d, 331 DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e, 332 DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f, 333 DBG_BLOCK_ID_TCC_BY2 = 0x40, 334 DBG_BLOCK_ID_TCC2_BY2 = 0x41, 335 DBG_BLOCK_ID_TCC4_BY2 = 0x42, 336 DBG_BLOCK_ID_TCC6_BY2 = 0x43, 337 DBG_BLOCK_ID_SPS_BY2 = 0x44, 338 DBG_BLOCK_ID_SPS02_BY2 = 0x45, 339 DBG_BLOCK_ID_SPS11_BY2 = 0x46, 340 DBG_BLOCK_ID_UNUSED14_BY2 = 0x47, 341 DBG_BLOCK_ID_TA_BY2 = 0x48, 342 DBG_BLOCK_ID_TA02_BY2 = 0x49, 343 DBG_BLOCK_ID_TA04_BY2 = 0x4a, 344 DBG_BLOCK_ID_TA06_BY2 = 0x4b, 345 DBG_BLOCK_ID_TA08_BY2 = 0x4c, 346 DBG_BLOCK_ID_TA0A_BY2 = 0x4d, 347 DBG_BLOCK_ID_UNUSED20_BY2 = 0x4e, 348 DBG_BLOCK_ID_UNUSED22_BY2 = 0x4f, 349 DBG_BLOCK_ID_TA10_BY2 = 0x50, 350 DBG_BLOCK_ID_TA12_BY2 = 0x51, 351 DBG_BLOCK_ID_TA14_BY2 = 0x52, 352 DBG_BLOCK_ID_TA16_BY2 = 0x53, 353 DBG_BLOCK_ID_TA18_BY2 = 0x54, 354 DBG_BLOCK_ID_TA1A_BY2 = 0x55, 355 DBG_BLOCK_ID_UNUSED24_BY2 = 0x56, 356 DBG_BLOCK_ID_UNUSED26_BY2 = 0x57, 357 DBG_BLOCK_ID_TD_BY2 = 0x58, 358 DBG_BLOCK_ID_TD02_BY2 = 0x59, 359 DBG_BLOCK_ID_TD04_BY2 = 0x5a, 360 DBG_BLOCK_ID_TD06_BY2 = 0x5b, 361 DBG_BLOCK_ID_TD08_BY2 = 0x5c, 362 DBG_BLOCK_ID_TD0A_BY2 = 0x5d, 363 DBG_BLOCK_ID_UNUSED28_BY2 = 0x5e, 364 DBG_BLOCK_ID_UNUSED30_BY2 = 0x5f, 365 DBG_BLOCK_ID_TD10_BY2 = 0x60, 366 DBG_BLOCK_ID_TD12_BY2 = 0x61, 367 DBG_BLOCK_ID_TD14_BY2 = 0x62, 368 DBG_BLOCK_ID_TD16_BY2 = 0x63, 369 DBG_BLOCK_ID_TD18_BY2 = 0x64, 370 DBG_BLOCK_ID_TD1A_BY2 = 0x65, 371 DBG_BLOCK_ID_UNUSED32_BY2 = 0x66, 372 DBG_BLOCK_ID_UNUSED34_BY2 = 0x67, 373 DBG_BLOCK_ID_LDS_BY2 = 0x68, 374 DBG_BLOCK_ID_LDS02_BY2 = 0x69, 375 DBG_BLOCK_ID_LDS04_BY2 = 0x6a, 376 DBG_BLOCK_ID_LDS06_BY2 = 0x6b, 377 DBG_BLOCK_ID_LDS08_BY2 = 0x6c, 378 DBG_BLOCK_ID_LDS0A_BY2 = 0x6d, 379 DBG_BLOCK_ID_UNUSED36_BY2 = 0x6e, 380 DBG_BLOCK_ID_UNUSED38_BY2 = 0x6f, 381 DBG_BLOCK_ID_LDS10_BY2 = 0x70, 382 DBG_BLOCK_ID_LDS12_BY2 = 0x71, 383 DBG_BLOCK_ID_LDS14_BY2 = 0x72, 384 DBG_BLOCK_ID_LDS16_BY2 = 0x73, 385 DBG_BLOCK_ID_LDS18_BY2 = 0x74, 386 DBG_BLOCK_ID_LDS1A_BY2 = 0x75, 387 DBG_BLOCK_ID_UNUSED40_BY2 = 0x76, 388 DBG_BLOCK_ID_UNUSED42_BY2 = 0x77, 389 } DebugBlockId_BY2; 390 typedef enum DebugBlockId_BY4 { 391 DBG_BLOCK_ID_RESERVED_BY4 = 0x0, 392 DBG_BLOCK_ID_UNUSED0_BY4 = 0x1, 393 DBG_BLOCK_ID_CSC_BY4 = 0x2, 394 DBG_BLOCK_ID_SQ_BY4 = 0x3, 395 DBG_BLOCK_ID_SDMA0_BY4 = 0x4, 396 DBG_BLOCK_ID_VC0_BY4 = 0x5, 397 DBG_BLOCK_ID_CP0_BY4 = 0x6, 398 DBG_BLOCK_ID_UNUSED1_BY4 = 0x7, 399 DBG_BLOCK_ID_SXM0_BY4 = 0x8, 400 DBG_BLOCK_ID_SPM0_BY4 = 0x9, 401 DBG_BLOCK_ID_TCAA_BY4 = 0xa, 402 DBG_BLOCK_ID_MCC_BY4 = 0xb, 403 DBG_BLOCK_ID_MCD_BY4 = 0xc, 404 DBG_BLOCK_ID_MCD4_BY4 = 0xd, 405 DBG_BLOCK_ID_SQA_BY4 = 0xe, 406 DBG_BLOCK_ID_SQA11_BY4 = 0xf, 407 DBG_BLOCK_ID_SQB_BY4 = 0x10, 408 DBG_BLOCK_ID_UNUSED10_BY4 = 0x11, 409 DBG_BLOCK_ID_CB_BY4 = 0x12, 410 DBG_BLOCK_ID_CB10_BY4 = 0x13, 411 DBG_BLOCK_ID_SXS_BY4 = 0x14, 412 DBG_BLOCK_ID_SXS4_BY4 = 0x15, 413 DBG_BLOCK_ID_DB_BY4 = 0x16, 414 DBG_BLOCK_ID_DB10_BY4 = 0x17, 415 DBG_BLOCK_ID_TCP_BY4 = 0x18, 416 DBG_BLOCK_ID_TCP4_BY4 = 0x19, 417 DBG_BLOCK_ID_TCP8_BY4 = 0x1a, 418 DBG_BLOCK_ID_TCP12_BY4 = 0x1b, 419 DBG_BLOCK_ID_TCP16_BY4 = 0x1c, 420 DBG_BLOCK_ID_TCP20_BY4 = 0x1d, 421 DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e, 422 DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f, 423 DBG_BLOCK_ID_TCC_BY4 = 0x20, 424 DBG_BLOCK_ID_TCC4_BY4 = 0x21, 425 DBG_BLOCK_ID_SPS_BY4 = 0x22, 426 DBG_BLOCK_ID_SPS11_BY4 = 0x23, 427 DBG_BLOCK_ID_TA_BY4 = 0x24, 428 DBG_BLOCK_ID_TA04_BY4 = 0x25, 429 DBG_BLOCK_ID_TA08_BY4 = 0x26, 430 DBG_BLOCK_ID_UNUSED20_BY4 = 0x27, 431 DBG_BLOCK_ID_TA10_BY4 = 0x28, 432 DBG_BLOCK_ID_TA14_BY4 = 0x29, 433 DBG_BLOCK_ID_TA18_BY4 = 0x2a, 434 DBG_BLOCK_ID_UNUSED24_BY4 = 0x2b, 435 DBG_BLOCK_ID_TD_BY4 = 0x2c, 436 DBG_BLOCK_ID_TD04_BY4 = 0x2d, 437 DBG_BLOCK_ID_TD08_BY4 = 0x2e, 438 DBG_BLOCK_ID_UNUSED28_BY4 = 0x2f, 439 DBG_BLOCK_ID_TD10_BY4 = 0x30, 440 DBG_BLOCK_ID_TD14_BY4 = 0x31, 441 DBG_BLOCK_ID_TD18_BY4 = 0x32, 442 DBG_BLOCK_ID_UNUSED32_BY4 = 0x33, 443 DBG_BLOCK_ID_LDS_BY4 = 0x34, 444 DBG_BLOCK_ID_LDS04_BY4 = 0x35, 445 DBG_BLOCK_ID_LDS08_BY4 = 0x36, 446 DBG_BLOCK_ID_UNUSED36_BY4 = 0x37, 447 DBG_BLOCK_ID_LDS10_BY4 = 0x38, 448 DBG_BLOCK_ID_LDS14_BY4 = 0x39, 449 DBG_BLOCK_ID_LDS18_BY4 = 0x3a, 450 DBG_BLOCK_ID_UNUSED40_BY4 = 0x3b, 451 } DebugBlockId_BY4; 452 typedef enum DebugBlockId_BY8 { 453 DBG_BLOCK_ID_RESERVED_BY8 = 0x0, 454 DBG_BLOCK_ID_CSC_BY8 = 0x1, 455 DBG_BLOCK_ID_SDMA0_BY8 = 0x2, 456 DBG_BLOCK_ID_CP0_BY8 = 0x3, 457 DBG_BLOCK_ID_SXM0_BY8 = 0x4, 458 DBG_BLOCK_ID_TCA_BY8 = 0x5, 459 DBG_BLOCK_ID_MCD_BY8 = 0x6, 460 DBG_BLOCK_ID_SQA_BY8 = 0x7, 461 DBG_BLOCK_ID_SQB_BY8 = 0x8, 462 DBG_BLOCK_ID_CB_BY8 = 0x9, 463 DBG_BLOCK_ID_SXS_BY8 = 0xa, 464 DBG_BLOCK_ID_DB_BY8 = 0xb, 465 DBG_BLOCK_ID_TCP_BY8 = 0xc, 466 DBG_BLOCK_ID_TCP8_BY8 = 0xd, 467 DBG_BLOCK_ID_TCP16_BY8 = 0xe, 468 DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf, 469 DBG_BLOCK_ID_TCC_BY8 = 0x10, 470 DBG_BLOCK_ID_SPS_BY8 = 0x11, 471 DBG_BLOCK_ID_TA_BY8 = 0x12, 472 DBG_BLOCK_ID_TA08_BY8 = 0x13, 473 DBG_BLOCK_ID_TA10_BY8 = 0x14, 474 DBG_BLOCK_ID_TA18_BY8 = 0x15, 475 DBG_BLOCK_ID_TD_BY8 = 0x16, 476 DBG_BLOCK_ID_TD08_BY8 = 0x17, 477 DBG_BLOCK_ID_TD10_BY8 = 0x18, 478 DBG_BLOCK_ID_TD18_BY8 = 0x19, 479 DBG_BLOCK_ID_LDS_BY8 = 0x1a, 480 DBG_BLOCK_ID_LDS08_BY8 = 0x1b, 481 DBG_BLOCK_ID_LDS10_BY8 = 0x1c, 482 DBG_BLOCK_ID_LDS18_BY8 = 0x1d, 483 } DebugBlockId_BY8; 484 typedef enum DebugBlockId_BY16 { 485 DBG_BLOCK_ID_RESERVED_BY16 = 0x0, 486 DBG_BLOCK_ID_SDMA0_BY16 = 0x1, 487 DBG_BLOCK_ID_SXM_BY16 = 0x2, 488 DBG_BLOCK_ID_MCD_BY16 = 0x3, 489 DBG_BLOCK_ID_SQB_BY16 = 0x4, 490 DBG_BLOCK_ID_SXS_BY16 = 0x5, 491 DBG_BLOCK_ID_TCP_BY16 = 0x6, 492 DBG_BLOCK_ID_TCP16_BY16 = 0x7, 493 DBG_BLOCK_ID_TCC_BY16 = 0x8, 494 DBG_BLOCK_ID_TA_BY16 = 0x9, 495 DBG_BLOCK_ID_TA10_BY16 = 0xa, 496 DBG_BLOCK_ID_TD_BY16 = 0xb, 497 DBG_BLOCK_ID_TD10_BY16 = 0xc, 498 DBG_BLOCK_ID_LDS_BY16 = 0xd, 499 DBG_BLOCK_ID_LDS10_BY16 = 0xe, 500 } DebugBlockId_BY16; 501 typedef enum SurfaceEndian { 502 ENDIAN_NONE = 0x0, 503 ENDIAN_8IN16 = 0x1, 504 ENDIAN_8IN32 = 0x2, 505 ENDIAN_8IN64 = 0x3, 506 } SurfaceEndian; 507 typedef enum ArrayMode { 508 ARRAY_LINEAR_GENERAL = 0x0, 509 ARRAY_LINEAR_ALIGNED = 0x1, 510 ARRAY_1D_TILED_THIN1 = 0x2, 511 ARRAY_1D_TILED_THICK = 0x3, 512 ARRAY_2D_TILED_THIN1 = 0x4, 513 ARRAY_PRT_TILED_THIN1 = 0x5, 514 ARRAY_PRT_2D_TILED_THIN1 = 0x6, 515 ARRAY_2D_TILED_THICK = 0x7, 516 ARRAY_2D_TILED_XTHICK = 0x8, 517 ARRAY_PRT_TILED_THICK = 0x9, 518 ARRAY_PRT_2D_TILED_THICK = 0xa, 519 ARRAY_PRT_3D_TILED_THIN1 = 0xb, 520 ARRAY_3D_TILED_THIN1 = 0xc, 521 ARRAY_3D_TILED_THICK = 0xd, 522 ARRAY_3D_TILED_XTHICK = 0xe, 523 ARRAY_PRT_3D_TILED_THICK = 0xf, 524 } ArrayMode; 525 typedef enum PipeTiling { 526 CONFIG_1_PIPE = 0x0, 527 CONFIG_2_PIPE = 0x1, 528 CONFIG_4_PIPE = 0x2, 529 CONFIG_8_PIPE = 0x3, 530 } PipeTiling; 531 typedef enum BankTiling { 532 CONFIG_4_BANK = 0x0, 533 CONFIG_8_BANK = 0x1, 534 } BankTiling; 535 typedef enum GroupInterleave { 536 CONFIG_256B_GROUP = 0x0, 537 CONFIG_512B_GROUP = 0x1, 538 } GroupInterleave; 539 typedef enum RowTiling { 540 CONFIG_1KB_ROW = 0x0, 541 CONFIG_2KB_ROW = 0x1, 542 CONFIG_4KB_ROW = 0x2, 543 CONFIG_8KB_ROW = 0x3, 544 CONFIG_1KB_ROW_OPT = 0x4, 545 CONFIG_2KB_ROW_OPT = 0x5, 546 CONFIG_4KB_ROW_OPT = 0x6, 547 CONFIG_8KB_ROW_OPT = 0x7, 548 } RowTiling; 549 typedef enum BankSwapBytes { 550 CONFIG_128B_SWAPS = 0x0, 551 CONFIG_256B_SWAPS = 0x1, 552 CONFIG_512B_SWAPS = 0x2, 553 CONFIG_1KB_SWAPS = 0x3, 554 } BankSwapBytes; 555 typedef enum SampleSplitBytes { 556 CONFIG_1KB_SPLIT = 0x0, 557 CONFIG_2KB_SPLIT = 0x1, 558 CONFIG_4KB_SPLIT = 0x2, 559 CONFIG_8KB_SPLIT = 0x3, 560 } SampleSplitBytes; 561 typedef enum NumPipes { 562 ADDR_CONFIG_1_PIPE = 0x0, 563 ADDR_CONFIG_2_PIPE = 0x1, 564 ADDR_CONFIG_4_PIPE = 0x2, 565 ADDR_CONFIG_8_PIPE = 0x3, 566 } NumPipes; 567 typedef enum PipeInterleaveSize { 568 ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0, 569 ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1, 570 } PipeInterleaveSize; 571 typedef enum BankInterleaveSize { 572 ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0, 573 ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1, 574 ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2, 575 ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3, 576 } BankInterleaveSize; 577 typedef enum NumShaderEngines { 578 ADDR_CONFIG_1_SHADER_ENGINE = 0x0, 579 ADDR_CONFIG_2_SHADER_ENGINE = 0x1, 580 } NumShaderEngines; 581 typedef enum ShaderEngineTileSize { 582 ADDR_CONFIG_SE_TILE_16 = 0x0, 583 ADDR_CONFIG_SE_TILE_32 = 0x1, 584 } ShaderEngineTileSize; 585 typedef enum NumGPUs { 586 ADDR_CONFIG_1_GPU = 0x0, 587 ADDR_CONFIG_2_GPU = 0x1, 588 ADDR_CONFIG_4_GPU = 0x2, 589 } NumGPUs; 590 typedef enum MultiGPUTileSize { 591 ADDR_CONFIG_GPU_TILE_16 = 0x0, 592 ADDR_CONFIG_GPU_TILE_32 = 0x1, 593 ADDR_CONFIG_GPU_TILE_64 = 0x2, 594 ADDR_CONFIG_GPU_TILE_128 = 0x3, 595 } MultiGPUTileSize; 596 typedef enum RowSize { 597 ADDR_CONFIG_1KB_ROW = 0x0, 598 ADDR_CONFIG_2KB_ROW = 0x1, 599 ADDR_CONFIG_4KB_ROW = 0x2, 600 } RowSize; 601 typedef enum NumLowerPipes { 602 ADDR_CONFIG_1_LOWER_PIPES = 0x0, 603 ADDR_CONFIG_2_LOWER_PIPES = 0x1, 604 } NumLowerPipes; 605 typedef enum ColorTransform { 606 DCC_CT_AUTO = 0x0, 607 DCC_CT_NONE = 0x1, 608 ABGR_TO_A_BG_G_RB = 0x2, 609 BGRA_TO_BG_G_RB_A = 0x3, 610 } ColorTransform; 611 typedef enum CompareRef { 612 REF_NEVER = 0x0, 613 REF_LESS = 0x1, 614 REF_EQUAL = 0x2, 615 REF_LEQUAL = 0x3, 616 REF_GREATER = 0x4, 617 REF_NOTEQUAL = 0x5, 618 REF_GEQUAL = 0x6, 619 REF_ALWAYS = 0x7, 620 } CompareRef; 621 typedef enum ReadSize { 622 READ_256_BITS = 0x0, 623 READ_512_BITS = 0x1, 624 } ReadSize; 625 typedef enum DepthFormat { 626 DEPTH_INVALID = 0x0, 627 DEPTH_16 = 0x1, 628 DEPTH_X8_24 = 0x2, 629 DEPTH_8_24 = 0x3, 630 DEPTH_X8_24_FLOAT = 0x4, 631 DEPTH_8_24_FLOAT = 0x5, 632 DEPTH_32_FLOAT = 0x6, 633 DEPTH_X24_8_32_FLOAT = 0x7, 634 } DepthFormat; 635 typedef enum ZFormat { 636 Z_INVALID = 0x0, 637 Z_16 = 0x1, 638 Z_24 = 0x2, 639 Z_32_FLOAT = 0x3, 640 } ZFormat; 641 typedef enum StencilFormat { 642 STENCIL_INVALID = 0x0, 643 STENCIL_8 = 0x1, 644 } StencilFormat; 645 typedef enum CmaskMode { 646 CMASK_CLEAR_NONE = 0x0, 647 CMASK_CLEAR_ONE = 0x1, 648 CMASK_CLEAR_ALL = 0x2, 649 CMASK_ANY_EXPANDED = 0x3, 650 CMASK_ALPHA0_FRAG1 = 0x4, 651 CMASK_ALPHA0_FRAG2 = 0x5, 652 CMASK_ALPHA0_FRAG4 = 0x6, 653 CMASK_ALPHA0_FRAGS = 0x7, 654 CMASK_ALPHA1_FRAG1 = 0x8, 655 CMASK_ALPHA1_FRAG2 = 0x9, 656 CMASK_ALPHA1_FRAG4 = 0xa, 657 CMASK_ALPHA1_FRAGS = 0xb, 658 CMASK_ALPHAX_FRAG1 = 0xc, 659 CMASK_ALPHAX_FRAG2 = 0xd, 660 CMASK_ALPHAX_FRAG4 = 0xe, 661 CMASK_ALPHAX_FRAGS = 0xf, 662 } CmaskMode; 663 typedef enum QuadExportFormat { 664 EXPORT_UNUSED = 0x0, 665 EXPORT_32_R = 0x1, 666 EXPORT_32_GR = 0x2, 667 EXPORT_32_AR = 0x3, 668 EXPORT_FP16_ABGR = 0x4, 669 EXPORT_UNSIGNED16_ABGR = 0x5, 670 EXPORT_SIGNED16_ABGR = 0x6, 671 EXPORT_32_ABGR = 0x7, 672 } QuadExportFormat; 673 typedef enum QuadExportFormatOld { 674 EXPORT_4P_32BPC_ABGR = 0x0, 675 EXPORT_4P_16BPC_ABGR = 0x1, 676 EXPORT_4P_32BPC_GR = 0x2, 677 EXPORT_4P_32BPC_AR = 0x3, 678 EXPORT_2P_32BPC_ABGR = 0x4, 679 EXPORT_8P_32BPC_R = 0x5, 680 } QuadExportFormatOld; 681 typedef enum ColorFormat { 682 COLOR_INVALID = 0x0, 683 COLOR_8 = 0x1, 684 COLOR_16 = 0x2, 685 COLOR_8_8 = 0x3, 686 COLOR_32 = 0x4, 687 COLOR_16_16 = 0x5, 688 COLOR_10_11_11 = 0x6, 689 COLOR_11_11_10 = 0x7, 690 COLOR_10_10_10_2 = 0x8, 691 COLOR_2_10_10_10 = 0x9, 692 COLOR_8_8_8_8 = 0xa, 693 COLOR_32_32 = 0xb, 694 COLOR_16_16_16_16 = 0xc, 695 COLOR_RESERVED_13 = 0xd, 696 COLOR_32_32_32_32 = 0xe, 697 COLOR_RESERVED_15 = 0xf, 698 COLOR_5_6_5 = 0x10, 699 COLOR_1_5_5_5 = 0x11, 700 COLOR_5_5_5_1 = 0x12, 701 COLOR_4_4_4_4 = 0x13, 702 COLOR_8_24 = 0x14, 703 COLOR_24_8 = 0x15, 704 COLOR_X24_8_32_FLOAT = 0x16, 705 COLOR_RESERVED_23 = 0x17, 706 } ColorFormat; 707 typedef enum SurfaceFormat { 708 FMT_INVALID = 0x0, 709 FMT_8 = 0x1, 710 FMT_16 = 0x2, 711 FMT_8_8 = 0x3, 712 FMT_32 = 0x4, 713 FMT_16_16 = 0x5, 714 FMT_10_11_11 = 0x6, 715 FMT_11_11_10 = 0x7, 716 FMT_10_10_10_2 = 0x8, 717 FMT_2_10_10_10 = 0x9, 718 FMT_8_8_8_8 = 0xa, 719 FMT_32_32 = 0xb, 720 FMT_16_16_16_16 = 0xc, 721 FMT_32_32_32 = 0xd, 722 FMT_32_32_32_32 = 0xe, 723 FMT_RESERVED_4 = 0xf, 724 FMT_5_6_5 = 0x10, 725 FMT_1_5_5_5 = 0x11, 726 FMT_5_5_5_1 = 0x12, 727 FMT_4_4_4_4 = 0x13, 728 FMT_8_24 = 0x14, 729 FMT_24_8 = 0x15, 730 FMT_X24_8_32_FLOAT = 0x16, 731 FMT_RESERVED_33 = 0x17, 732 FMT_11_11_10_FLOAT = 0x18, 733 FMT_16_FLOAT = 0x19, 734 FMT_32_FLOAT = 0x1a, 735 FMT_16_16_FLOAT = 0x1b, 736 FMT_8_24_FLOAT = 0x1c, 737 FMT_24_8_FLOAT = 0x1d, 738 FMT_32_32_FLOAT = 0x1e, 739 FMT_10_11_11_FLOAT = 0x1f, 740 FMT_16_16_16_16_FLOAT = 0x20, 741 FMT_3_3_2 = 0x21, 742 FMT_6_5_5 = 0x22, 743 FMT_32_32_32_32_FLOAT = 0x23, 744 FMT_RESERVED_36 = 0x24, 745 FMT_1 = 0x25, 746 FMT_1_REVERSED = 0x26, 747 FMT_GB_GR = 0x27, 748 FMT_BG_RG = 0x28, 749 FMT_32_AS_8 = 0x29, 750 FMT_32_AS_8_8 = 0x2a, 751 FMT_5_9_9_9_SHAREDEXP = 0x2b, 752 FMT_8_8_8 = 0x2c, 753 FMT_16_16_16 = 0x2d, 754 FMT_16_16_16_FLOAT = 0x2e, 755 FMT_4_4 = 0x2f, 756 FMT_32_32_32_FLOAT = 0x30, 757 FMT_BC1 = 0x31, 758 FMT_BC2 = 0x32, 759 FMT_BC3 = 0x33, 760 FMT_BC4 = 0x34, 761 FMT_BC5 = 0x35, 762 FMT_BC6 = 0x36, 763 FMT_BC7 = 0x37, 764 FMT_32_AS_32_32_32_32 = 0x38, 765 FMT_APC3 = 0x39, 766 FMT_APC4 = 0x3a, 767 FMT_APC5 = 0x3b, 768 FMT_APC6 = 0x3c, 769 FMT_APC7 = 0x3d, 770 FMT_CTX1 = 0x3e, 771 FMT_RESERVED_63 = 0x3f, 772 } SurfaceFormat; 773 typedef enum BUF_DATA_FORMAT { 774 BUF_DATA_FORMAT_INVALID = 0x0, 775 BUF_DATA_FORMAT_8 = 0x1, 776 BUF_DATA_FORMAT_16 = 0x2, 777 BUF_DATA_FORMAT_8_8 = 0x3, 778 BUF_DATA_FORMAT_32 = 0x4, 779 BUF_DATA_FORMAT_16_16 = 0x5, 780 BUF_DATA_FORMAT_10_11_11 = 0x6, 781 BUF_DATA_FORMAT_11_11_10 = 0x7, 782 BUF_DATA_FORMAT_10_10_10_2 = 0x8, 783 BUF_DATA_FORMAT_2_10_10_10 = 0x9, 784 BUF_DATA_FORMAT_8_8_8_8 = 0xa, 785 BUF_DATA_FORMAT_32_32 = 0xb, 786 BUF_DATA_FORMAT_16_16_16_16 = 0xc, 787 BUF_DATA_FORMAT_32_32_32 = 0xd, 788 BUF_DATA_FORMAT_32_32_32_32 = 0xe, 789 BUF_DATA_FORMAT_RESERVED_15 = 0xf, 790 } BUF_DATA_FORMAT; 791 typedef enum IMG_DATA_FORMAT { 792 IMG_DATA_FORMAT_INVALID = 0x0, 793 IMG_DATA_FORMAT_8 = 0x1, 794 IMG_DATA_FORMAT_16 = 0x2, 795 IMG_DATA_FORMAT_8_8 = 0x3, 796 IMG_DATA_FORMAT_32 = 0x4, 797 IMG_DATA_FORMAT_16_16 = 0x5, 798 IMG_DATA_FORMAT_10_11_11 = 0x6, 799 IMG_DATA_FORMAT_11_11_10 = 0x7, 800 IMG_DATA_FORMAT_10_10_10_2 = 0x8, 801 IMG_DATA_FORMAT_2_10_10_10 = 0x9, 802 IMG_DATA_FORMAT_8_8_8_8 = 0xa, 803 IMG_DATA_FORMAT_32_32 = 0xb, 804 IMG_DATA_FORMAT_16_16_16_16 = 0xc, 805 IMG_DATA_FORMAT_32_32_32 = 0xd, 806 IMG_DATA_FORMAT_32_32_32_32 = 0xe, 807 IMG_DATA_FORMAT_RESERVED_15 = 0xf, 808 IMG_DATA_FORMAT_5_6_5 = 0x10, 809 IMG_DATA_FORMAT_1_5_5_5 = 0x11, 810 IMG_DATA_FORMAT_5_5_5_1 = 0x12, 811 IMG_DATA_FORMAT_4_4_4_4 = 0x13, 812 IMG_DATA_FORMAT_8_24 = 0x14, 813 IMG_DATA_FORMAT_24_8 = 0x15, 814 IMG_DATA_FORMAT_X24_8_32 = 0x16, 815 IMG_DATA_FORMAT_RESERVED_23 = 0x17, 816 IMG_DATA_FORMAT_RESERVED_24 = 0x18, 817 IMG_DATA_FORMAT_RESERVED_25 = 0x19, 818 IMG_DATA_FORMAT_RESERVED_26 = 0x1a, 819 IMG_DATA_FORMAT_RESERVED_27 = 0x1b, 820 IMG_DATA_FORMAT_RESERVED_28 = 0x1c, 821 IMG_DATA_FORMAT_RESERVED_29 = 0x1d, 822 IMG_DATA_FORMAT_RESERVED_30 = 0x1e, 823 IMG_DATA_FORMAT_RESERVED_31 = 0x1f, 824 IMG_DATA_FORMAT_GB_GR = 0x20, 825 IMG_DATA_FORMAT_BG_RG = 0x21, 826 IMG_DATA_FORMAT_5_9_9_9 = 0x22, 827 IMG_DATA_FORMAT_BC1 = 0x23, 828 IMG_DATA_FORMAT_BC2 = 0x24, 829 IMG_DATA_FORMAT_BC3 = 0x25, 830 IMG_DATA_FORMAT_BC4 = 0x26, 831 IMG_DATA_FORMAT_BC5 = 0x27, 832 IMG_DATA_FORMAT_BC6 = 0x28, 833 IMG_DATA_FORMAT_BC7 = 0x29, 834 IMG_DATA_FORMAT_RESERVED_42 = 0x2a, 835 IMG_DATA_FORMAT_RESERVED_43 = 0x2b, 836 IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c, 837 IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d, 838 IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e, 839 IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f, 840 IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30, 841 IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31, 842 IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32, 843 IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33, 844 IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34, 845 IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35, 846 IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36, 847 IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37, 848 IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38, 849 IMG_DATA_FORMAT_4_4 = 0x39, 850 IMG_DATA_FORMAT_6_5_5 = 0x3a, 851 IMG_DATA_FORMAT_1 = 0x3b, 852 IMG_DATA_FORMAT_1_REVERSED = 0x3c, 853 IMG_DATA_FORMAT_32_AS_8 = 0x3d, 854 IMG_DATA_FORMAT_32_AS_8_8 = 0x3e, 855 IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f, 856 } IMG_DATA_FORMAT; 857 typedef enum BUF_NUM_FORMAT { 858 BUF_NUM_FORMAT_UNORM = 0x0, 859 BUF_NUM_FORMAT_SNORM = 0x1, 860 BUF_NUM_FORMAT_USCALED = 0x2, 861 BUF_NUM_FORMAT_SSCALED = 0x3, 862 BUF_NUM_FORMAT_UINT = 0x4, 863 BUF_NUM_FORMAT_SINT = 0x5, 864 BUF_NUM_FORMAT_RESERVED_6 = 0x6, 865 BUF_NUM_FORMAT_FLOAT = 0x7, 866 } BUF_NUM_FORMAT; 867 typedef enum IMG_NUM_FORMAT { 868 IMG_NUM_FORMAT_UNORM = 0x0, 869 IMG_NUM_FORMAT_SNORM = 0x1, 870 IMG_NUM_FORMAT_USCALED = 0x2, 871 IMG_NUM_FORMAT_SSCALED = 0x3, 872 IMG_NUM_FORMAT_UINT = 0x4, 873 IMG_NUM_FORMAT_SINT = 0x5, 874 IMG_NUM_FORMAT_RESERVED_6 = 0x6, 875 IMG_NUM_FORMAT_FLOAT = 0x7, 876 IMG_NUM_FORMAT_RESERVED_8 = 0x8, 877 IMG_NUM_FORMAT_SRGB = 0x9, 878 IMG_NUM_FORMAT_RESERVED_10 = 0xa, 879 IMG_NUM_FORMAT_RESERVED_11 = 0xb, 880 IMG_NUM_FORMAT_RESERVED_12 = 0xc, 881 IMG_NUM_FORMAT_RESERVED_13 = 0xd, 882 IMG_NUM_FORMAT_RESERVED_14 = 0xe, 883 IMG_NUM_FORMAT_RESERVED_15 = 0xf, 884 } IMG_NUM_FORMAT; 885 typedef enum TileType { 886 ARRAY_COLOR_TILE = 0x0, 887 ARRAY_DEPTH_TILE = 0x1, 888 } TileType; 889 typedef enum NonDispTilingOrder { 890 ADDR_SURF_MICRO_TILING_DISPLAY = 0x0, 891 ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1, 892 } NonDispTilingOrder; 893 typedef enum MicroTileMode { 894 ADDR_SURF_DISPLAY_MICRO_TILING = 0x0, 895 ADDR_SURF_THIN_MICRO_TILING = 0x1, 896 ADDR_SURF_DEPTH_MICRO_TILING = 0x2, 897 ADDR_SURF_ROTATED_MICRO_TILING = 0x3, 898 ADDR_SURF_THICK_MICRO_TILING = 0x4, 899 } MicroTileMode; 900 typedef enum TileSplit { 901 ADDR_SURF_TILE_SPLIT_64B = 0x0, 902 ADDR_SURF_TILE_SPLIT_128B = 0x1, 903 ADDR_SURF_TILE_SPLIT_256B = 0x2, 904 ADDR_SURF_TILE_SPLIT_512B = 0x3, 905 ADDR_SURF_TILE_SPLIT_1KB = 0x4, 906 ADDR_SURF_TILE_SPLIT_2KB = 0x5, 907 ADDR_SURF_TILE_SPLIT_4KB = 0x6, 908 } TileSplit; 909 typedef enum SampleSplit { 910 ADDR_SURF_SAMPLE_SPLIT_1 = 0x0, 911 ADDR_SURF_SAMPLE_SPLIT_2 = 0x1, 912 ADDR_SURF_SAMPLE_SPLIT_4 = 0x2, 913 ADDR_SURF_SAMPLE_SPLIT_8 = 0x3, 914 } SampleSplit; 915 typedef enum PipeConfig { 916 ADDR_SURF_P2 = 0x0, 917 ADDR_SURF_P2_RESERVED0 = 0x1, 918 ADDR_SURF_P2_RESERVED1 = 0x2, 919 ADDR_SURF_P2_RESERVED2 = 0x3, 920 ADDR_SURF_P4_8x16 = 0x4, 921 ADDR_SURF_P4_16x16 = 0x5, 922 ADDR_SURF_P4_16x32 = 0x6, 923 ADDR_SURF_P4_32x32 = 0x7, 924 ADDR_SURF_P8_16x16_8x16 = 0x8, 925 ADDR_SURF_P8_16x32_8x16 = 0x9, 926 ADDR_SURF_P8_32x32_8x16 = 0xa, 927 ADDR_SURF_P8_16x32_16x16 = 0xb, 928 ADDR_SURF_P8_32x32_16x16 = 0xc, 929 ADDR_SURF_P8_32x32_16x32 = 0xd, 930 ADDR_SURF_P8_32x64_32x32 = 0xe, 931 ADDR_SURF_P8_RESERVED0 = 0xf, 932 ADDR_SURF_P16_32x32_8x16 = 0x10, 933 ADDR_SURF_P16_32x32_16x16 = 0x11, 934 } PipeConfig; 935 typedef enum NumBanks { 936 ADDR_SURF_2_BANK = 0x0, 937 ADDR_SURF_4_BANK = 0x1, 938 ADDR_SURF_8_BANK = 0x2, 939 ADDR_SURF_16_BANK = 0x3, 940 } NumBanks; 941 typedef enum BankWidth { 942 ADDR_SURF_BANK_WIDTH_1 = 0x0, 943 ADDR_SURF_BANK_WIDTH_2 = 0x1, 944 ADDR_SURF_BANK_WIDTH_4 = 0x2, 945 ADDR_SURF_BANK_WIDTH_8 = 0x3, 946 } BankWidth; 947 typedef enum BankHeight { 948 ADDR_SURF_BANK_HEIGHT_1 = 0x0, 949 ADDR_SURF_BANK_HEIGHT_2 = 0x1, 950 ADDR_SURF_BANK_HEIGHT_4 = 0x2, 951 ADDR_SURF_BANK_HEIGHT_8 = 0x3, 952 } BankHeight; 953 typedef enum BankWidthHeight { 954 ADDR_SURF_BANK_WH_1 = 0x0, 955 ADDR_SURF_BANK_WH_2 = 0x1, 956 ADDR_SURF_BANK_WH_4 = 0x2, 957 ADDR_SURF_BANK_WH_8 = 0x3, 958 } BankWidthHeight; 959 typedef enum MacroTileAspect { 960 ADDR_SURF_MACRO_ASPECT_1 = 0x0, 961 ADDR_SURF_MACRO_ASPECT_2 = 0x1, 962 ADDR_SURF_MACRO_ASPECT_4 = 0x2, 963 ADDR_SURF_MACRO_ASPECT_8 = 0x3, 964 } MacroTileAspect; 965 typedef enum GATCL1RequestType { 966 GATCL1_TYPE_NORMAL = 0x0, 967 GATCL1_TYPE_SHOOTDOWN = 0x1, 968 GATCL1_TYPE_BYPASS = 0x2, 969 } GATCL1RequestType; 970 typedef enum TCC_CACHE_POLICIES { 971 TCC_CACHE_POLICY_LRU = 0x0, 972 TCC_CACHE_POLICY_STREAM = 0x1, 973 } TCC_CACHE_POLICIES; 974 typedef enum MTYPE { 975 MTYPE_NC_NV = 0x0, 976 MTYPE_NC = 0x1, 977 MTYPE_CC = 0x2, 978 MTYPE_UC = 0x3, 979 } MTYPE; 980 typedef enum PERFMON_COUNTER_MODE { 981 PERFMON_COUNTER_MODE_ACCUM = 0x0, 982 PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1, 983 PERFMON_COUNTER_MODE_MAX = 0x2, 984 PERFMON_COUNTER_MODE_DIRTY = 0x3, 985 PERFMON_COUNTER_MODE_SAMPLE = 0x4, 986 PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5, 987 PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6, 988 PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7, 989 PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8, 990 PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9, 991 PERFMON_COUNTER_MODE_RESERVED = 0xf, 992 } PERFMON_COUNTER_MODE; 993 typedef enum PERFMON_SPM_MODE { 994 PERFMON_SPM_MODE_OFF = 0x0, 995 PERFMON_SPM_MODE_16BIT_CLAMP = 0x1, 996 PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2, 997 PERFMON_SPM_MODE_32BIT_CLAMP = 0x3, 998 PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4, 999 PERFMON_SPM_MODE_RESERVED_5 = 0x5, 1000 PERFMON_SPM_MODE_RESERVED_6 = 0x6, 1001 PERFMON_SPM_MODE_RESERVED_7 = 0x7, 1002 PERFMON_SPM_MODE_TEST_MODE_0 = 0x8, 1003 PERFMON_SPM_MODE_TEST_MODE_1 = 0x9, 1004 PERFMON_SPM_MODE_TEST_MODE_2 = 0xa, 1005 } PERFMON_SPM_MODE; 1006 typedef enum SurfaceTiling { 1007 ARRAY_LINEAR = 0x0, 1008 ARRAY_TILED = 0x1, 1009 } SurfaceTiling; 1010 typedef enum SurfaceArray { 1011 ARRAY_1D = 0x0, 1012 ARRAY_2D = 0x1, 1013 ARRAY_3D = 0x2, 1014 ARRAY_3D_SLICE = 0x3, 1015 } SurfaceArray; 1016 typedef enum ColorArray { 1017 ARRAY_2D_ALT_COLOR = 0x0, 1018 ARRAY_2D_COLOR = 0x1, 1019 ARRAY_3D_SLICE_COLOR = 0x3, 1020 } ColorArray; 1021 typedef enum DepthArray { 1022 ARRAY_2D_ALT_DEPTH = 0x0, 1023 ARRAY_2D_DEPTH = 0x1, 1024 } DepthArray; 1025 typedef enum ENUM_NUM_SIMD_PER_CU { 1026 NUM_SIMD_PER_CU = 0x4, 1027 } ENUM_NUM_SIMD_PER_CU; 1028 typedef enum MEM_PWR_FORCE_CTRL { 1029 NO_FORCE_REQUEST = 0x0, 1030 FORCE_LIGHT_SLEEP_REQUEST = 0x1, 1031 FORCE_DEEP_SLEEP_REQUEST = 0x2, 1032 FORCE_SHUT_DOWN_REQUEST = 0x3, 1033 } MEM_PWR_FORCE_CTRL; 1034 typedef enum MEM_PWR_FORCE_CTRL2 { 1035 NO_FORCE_REQ = 0x0, 1036 FORCE_LIGHT_SLEEP_REQ = 0x1, 1037 } MEM_PWR_FORCE_CTRL2; 1038 typedef enum MEM_PWR_DIS_CTRL { 1039 ENABLE_MEM_PWR_CTRL = 0x0, 1040 DISABLE_MEM_PWR_CTRL = 0x1, 1041 } MEM_PWR_DIS_CTRL; 1042 typedef enum MEM_PWR_SEL_CTRL { 1043 DYNAMIC_SHUT_DOWN_ENABLE = 0x0, 1044 DYNAMIC_DEEP_SLEEP_ENABLE = 0x1, 1045 DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2, 1046 } MEM_PWR_SEL_CTRL; 1047 typedef enum MEM_PWR_SEL_CTRL2 { 1048 DYNAMIC_DEEP_SLEEP_EN = 0x0, 1049 DYNAMIC_LIGHT_SLEEP_EN = 0x1, 1050 } MEM_PWR_SEL_CTRL2; 1051 1052 #endif /* ACP_2_2_ENUM_H */ 1053