1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ 2 /* 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * Copyright(c) 2021 Advanced Micro Devices, Inc. All rights reserved. 7 * 8 * Author: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com> 9 */ 10 11 #ifndef _ACP_IP_OFFSET_HEADER 12 #define _ACP_IP_OFFSET_HEADER 13 14 #define ACPAXI2AXI_ATU_CTRL 0xC40 15 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_5 0xC20 16 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_5 0xC24 17 18 #define ACP_PGFSM_CONTROL 0x141C 19 #define ACP_PGFSM_STATUS 0x1420 20 #define ACP_SOFT_RESET 0x1000 21 #define ACP_CONTROL 0x1004 22 23 #define ACP_EXTERNAL_INTR_ENB 0x1800 24 #define ACP_EXTERNAL_INTR_CNTL 0x1804 25 #define ACP_EXTERNAL_INTR_STAT 0x1808 26 #define ACP_I2S_PIN_CONFIG 0x1400 27 #define ACP_SCRATCH_REG_0 0x12800 28 29 /* Registers from ACP_AUDIO_BUFFERS block */ 30 31 #define ACP_I2S_RX_RINGBUFADDR 0x2000 32 #define ACP_I2S_RX_RINGBUFSIZE 0x2004 33 #define ACP_I2S_RX_LINKPOSITIONCNTR 0x2008 34 #define ACP_I2S_RX_FIFOADDR 0x200C 35 #define ACP_I2S_RX_FIFOSIZE 0x2010 36 #define ACP_I2S_RX_DMA_SIZE 0x2014 37 #define ACP_I2S_RX_LINEARPOSITIONCNTR_HIGH 0x2018 38 #define ACP_I2S_RX_LINEARPOSITIONCNTR_LOW 0x201C 39 #define ACP_I2S_RX_INTR_WATERMARK_SIZE 0x2020 40 #define ACP_I2S_TX_RINGBUFADDR 0x2024 41 #define ACP_I2S_TX_RINGBUFSIZE 0x2028 42 #define ACP_I2S_TX_LINKPOSITIONCNTR 0x202C 43 #define ACP_I2S_TX_FIFOADDR 0x2030 44 #define ACP_I2S_TX_FIFOSIZE 0x2034 45 #define ACP_I2S_TX_DMA_SIZE 0x2038 46 #define ACP_I2S_TX_LINEARPOSITIONCNTR_HIGH 0x203C 47 #define ACP_I2S_TX_LINEARPOSITIONCNTR_LOW 0x2040 48 #define ACP_I2S_TX_INTR_WATERMARK_SIZE 0x2044 49 #define ACP_BT_RX_RINGBUFADDR 0x2048 50 #define ACP_BT_RX_RINGBUFSIZE 0x204C 51 #define ACP_BT_RX_LINKPOSITIONCNTR 0x2050 52 #define ACP_BT_RX_FIFOADDR 0x2054 53 #define ACP_BT_RX_FIFOSIZE 0x2058 54 #define ACP_BT_RX_DMA_SIZE 0x205C 55 #define ACP_BT_RX_LINEARPOSITIONCNTR_HIGH 0x2060 56 #define ACP_BT_RX_LINEARPOSITIONCNTR_LOW 0x2064 57 #define ACP_BT_RX_INTR_WATERMARK_SIZE 0x2068 58 #define ACP_BT_TX_RINGBUFADDR 0x206C 59 #define ACP_BT_TX_RINGBUFSIZE 0x2070 60 #define ACP_BT_TX_LINKPOSITIONCNTR 0x2074 61 #define ACP_BT_TX_FIFOADDR 0x2078 62 #define ACP_BT_TX_FIFOSIZE 0x207C 63 #define ACP_BT_TX_DMA_SIZE 0x2080 64 #define ACP_BT_TX_LINEARPOSITIONCNTR_HIGH 0x2084 65 #define ACP_BT_TX_LINEARPOSITIONCNTR_LOW 0x2088 66 #define ACP_BT_TX_INTR_WATERMARK_SIZE 0x208C 67 68 #define ACP_I2STDM_IER 0x2400 69 #define ACP_I2STDM_IRER 0x2404 70 #define ACP_I2STDM_RXFRMT 0x2408 71 #define ACP_I2STDM_ITER 0x240C 72 #define ACP_I2STDM_TXFRMT 0x2410 73 74 /* Registers from ACP_BT_TDM block */ 75 76 #define ACP_BTTDM_IER 0x2800 77 #define ACP_BTTDM_IRER 0x2804 78 #define ACP_BTTDM_RXFRMT 0x2808 79 #define ACP_BTTDM_ITER 0x280C 80 #define ACP_BTTDM_TXFRMT 0x2810 81 82 /* Registers from ACP_WOV_PDM block */ 83 84 #define ACP_WOV_PDM_ENABLE 0x2C04 85 #define ACP_WOV_PDM_DMA_ENABLE 0x2C08 86 #define ACP_WOV_RX_RINGBUFADDR 0x2C0C 87 #define ACP_WOV_RX_RINGBUFSIZE 0x2C10 88 #define ACP_WOV_RX_LINKPOSITIONCNTR 0x2C14 89 #define ACP_WOV_RX_LINEARPOSITIONCNTR_HIGH 0x2C18 90 #define ACP_WOV_RX_LINEARPOSITIONCNTR_LOW 0x2C1C 91 #define ACP_WOV_RX_INTR_WATERMARK_SIZE 0x2C20 92 #define ACP_WOV_PDM_FIFO_FLUSH 0x2C24 93 #define ACP_WOV_PDM_NO_OF_CHANNELS 0x2C28 94 #define ACP_WOV_PDM_DECIMATION_FACTOR 0x2C2C 95 #define ACP_WOV_PDM_VAD_CTRL 0x2C30 96 #define ACP_WOV_BUFFER_STATUS 0x2C58 97 #define ACP_WOV_MISC_CTRL 0x2C5C 98 #define ACP_WOV_CLK_CTRL 0x2C60 99 #define ACP_PDM_VAD_DYNAMIC_CLK_GATING_EN 0x2C64 100 #define ACP_WOV_ERROR_STATUS_REGISTER 0x2C68 101 102 #endif 103