1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ 2 /* 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * Copyright(c) 2021 Advanced Micro Devices, Inc. All rights reserved. 7 * 8 * Author: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com> 9 */ 10 11 #ifndef _ACP_IP_OFFSET_HEADER 12 #define _ACP_IP_OFFSET_HEADER 13 14 #define ACPAXI2AXI_ATU_CTRL 0xC40 15 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_5 0xC20 16 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_5 0xC24 17 18 #define ACP_PGFSM_CONTROL 0x141C 19 #define ACP_PGFSM_STATUS 0x1420 20 #define ACP_SOFT_RESET 0x1000 21 #define ACP_CONTROL 0x1004 22 #define ACP_PIN_CONFIG 0x1440 23 #define ACP3X_PIN_CONFIG 0x1400 24 25 #define ACP_EXTERNAL_INTR_REG_ADDR(adata, offset, ctrl) \ 26 (adata->acp_base + adata->rsrc->irq_reg_offset + offset + (ctrl * 0x04)) 27 28 #define ACP_EXTERNAL_INTR_ENB(adata) ACP_EXTERNAL_INTR_REG_ADDR(adata, 0x0, 0x0) 29 #define ACP_EXTERNAL_INTR_CNTL(adata, ctrl) ACP_EXTERNAL_INTR_REG_ADDR(adata, 0x4, ctrl) 30 #define ACP_EXTERNAL_INTR_STAT(adata, ctrl) ACP_EXTERNAL_INTR_REG_ADDR(adata, \ 31 (0x4 + (adata->rsrc->no_of_ctrls * 0x04)), ctrl) 32 33 /* Registers from ACP_AUDIO_BUFFERS block */ 34 35 #define ACP_I2S_RX_RINGBUFADDR 0x2000 36 #define ACP_I2S_RX_RINGBUFSIZE 0x2004 37 #define ACP_I2S_RX_LINKPOSITIONCNTR 0x2008 38 #define ACP_I2S_RX_FIFOADDR 0x200C 39 #define ACP_I2S_RX_FIFOSIZE 0x2010 40 #define ACP_I2S_RX_DMA_SIZE 0x2014 41 #define ACP_I2S_RX_LINEARPOSITIONCNTR_HIGH 0x2018 42 #define ACP_I2S_RX_LINEARPOSITIONCNTR_LOW 0x201C 43 #define ACP_I2S_RX_INTR_WATERMARK_SIZE 0x2020 44 #define ACP_I2S_TX_RINGBUFADDR 0x2024 45 #define ACP_I2S_TX_RINGBUFSIZE 0x2028 46 #define ACP_I2S_TX_LINKPOSITIONCNTR 0x202C 47 #define ACP_I2S_TX_FIFOADDR 0x2030 48 #define ACP_I2S_TX_FIFOSIZE 0x2034 49 #define ACP_I2S_TX_DMA_SIZE 0x2038 50 #define ACP_I2S_TX_LINEARPOSITIONCNTR_HIGH 0x203C 51 #define ACP_I2S_TX_LINEARPOSITIONCNTR_LOW 0x2040 52 #define ACP_I2S_TX_INTR_WATERMARK_SIZE 0x2044 53 #define ACP_BT_RX_RINGBUFADDR 0x2048 54 #define ACP_BT_RX_RINGBUFSIZE 0x204C 55 #define ACP_BT_RX_LINKPOSITIONCNTR 0x2050 56 #define ACP_BT_RX_FIFOADDR 0x2054 57 #define ACP_BT_RX_FIFOSIZE 0x2058 58 #define ACP_BT_RX_DMA_SIZE 0x205C 59 #define ACP_BT_RX_LINEARPOSITIONCNTR_HIGH 0x2060 60 #define ACP_BT_RX_LINEARPOSITIONCNTR_LOW 0x2064 61 #define ACP_BT_RX_INTR_WATERMARK_SIZE 0x2068 62 #define ACP_BT_TX_RINGBUFADDR 0x206C 63 #define ACP_BT_TX_RINGBUFSIZE 0x2070 64 #define ACP_BT_TX_LINKPOSITIONCNTR 0x2074 65 #define ACP_BT_TX_FIFOADDR 0x2078 66 #define ACP_BT_TX_FIFOSIZE 0x207C 67 #define ACP_BT_TX_DMA_SIZE 0x2080 68 #define ACP_BT_TX_LINEARPOSITIONCNTR_HIGH 0x2084 69 #define ACP_BT_TX_LINEARPOSITIONCNTR_LOW 0x2088 70 #define ACP_BT_TX_INTR_WATERMARK_SIZE 0x208C 71 #define ACP_HS_RX_RINGBUFADDR 0x3A90 72 #define ACP_HS_RX_RINGBUFSIZE 0x3A94 73 #define ACP_HS_RX_LINKPOSITIONCNTR 0x3A98 74 #define ACP_HS_RX_FIFOADDR 0x3A9C 75 #define ACP_HS_RX_FIFOSIZE 0x3AA0 76 #define ACP_HS_RX_DMA_SIZE 0x3AA4 77 #define ACP_HS_RX_LINEARPOSITIONCNTR_HIGH 0x3AA8 78 #define ACP_HS_RX_LINEARPOSITIONCNTR_LOW 0x3AAC 79 #define ACP_HS_RX_INTR_WATERMARK_SIZE 0x3AB0 80 #define ACP_HS_TX_RINGBUFADDR 0x3AB4 81 #define ACP_HS_TX_RINGBUFSIZE 0x3AB8 82 #define ACP_HS_TX_LINKPOSITIONCNTR 0x3ABC 83 #define ACP_HS_TX_FIFOADDR 0x3AC0 84 #define ACP_HS_TX_FIFOSIZE 0x3AC4 85 #define ACP_HS_TX_DMA_SIZE 0x3AC8 86 #define ACP_HS_TX_LINEARPOSITIONCNTR_HIGH 0x3ACC 87 #define ACP_HS_TX_LINEARPOSITIONCNTR_LOW 0x3AD0 88 #define ACP_HS_TX_INTR_WATERMARK_SIZE 0x3AD4 89 90 #define ACP_I2STDM_IER 0x2400 91 #define ACP_I2STDM_IRER 0x2404 92 #define ACP_I2STDM_RXFRMT 0x2408 93 #define ACP_I2STDM_ITER 0x240C 94 #define ACP_I2STDM_TXFRMT 0x2410 95 96 /* Registers from ACP_BT_TDM block */ 97 98 #define ACP_BTTDM_IER 0x2800 99 #define ACP_BTTDM_IRER 0x2804 100 #define ACP_BTTDM_RXFRMT 0x2808 101 #define ACP_BTTDM_ITER 0x280C 102 #define ACP_BTTDM_TXFRMT 0x2810 103 104 /* Registers from ACP_HS_TDM block */ 105 #define ACP_HSTDM_IER 0x2814 106 #define ACP_HSTDM_IRER 0x2818 107 #define ACP_HSTDM_RXFRMT 0x281C 108 #define ACP_HSTDM_ITER 0x2820 109 #define ACP_HSTDM_TXFRMT 0x2824 110 111 /* Registers from ACP_WOV_PDM block */ 112 113 #define ACP_WOV_PDM_ENABLE 0x2C04 114 #define ACP_WOV_PDM_DMA_ENABLE 0x2C08 115 #define ACP_WOV_RX_RINGBUFADDR 0x2C0C 116 #define ACP_WOV_RX_RINGBUFSIZE 0x2C10 117 #define ACP_WOV_RX_LINKPOSITIONCNTR 0x2C14 118 #define ACP_WOV_RX_LINEARPOSITIONCNTR_HIGH 0x2C18 119 #define ACP_WOV_RX_LINEARPOSITIONCNTR_LOW 0x2C1C 120 #define ACP_WOV_RX_INTR_WATERMARK_SIZE 0x2C20 121 #define ACP_WOV_PDM_FIFO_FLUSH 0x2C24 122 #define ACP_WOV_PDM_NO_OF_CHANNELS 0x2C28 123 #define ACP_WOV_PDM_DECIMATION_FACTOR 0x2C2C 124 #define ACP_WOV_PDM_VAD_CTRL 0x2C30 125 #define ACP_WOV_BUFFER_STATUS 0x2C58 126 #define ACP_WOV_MISC_CTRL 0x2C5C 127 #define ACP_WOV_CLK_CTRL 0x2C60 128 #define ACP_PDM_VAD_DYNAMIC_CLK_GATING_EN 0x2C64 129 #define ACP_WOV_ERROR_STATUS_REGISTER 0x2C68 130 131 #define ACP_I2STDM0_MSTRCLKGEN 0x2414 132 #define ACP_I2STDM1_MSTRCLKGEN 0x2418 133 #define ACP_I2STDM2_MSTRCLKGEN 0x241C 134 #endif 135