xref: /linux/sound/soc/amd/acp/amd.h (revision 8e1bb4a41aa78d6105e59186af3dcd545fc66e70)
1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
2 /*
3  * This file is provided under a dual BSD/GPLv2 license. When using or
4  * redistributing this file, you may do so under either license.
5  *
6  * Copyright(c) 2021 Advanced Micro Devices, Inc. All rights reserved.
7  *
8  * Author: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com>
9  */
10 
11 #ifndef __AMD_ACP_H
12 #define __AMD_ACP_H
13 
14 #include <sound/pcm.h>
15 #include <sound/soc.h>
16 #include <sound/soc-acpi.h>
17 #include <sound/soc-dai.h>
18 
19 #include "chip_offset_byte.h"
20 
21 #define ACP3X_DEV			3
22 #define ACP6X_DEV			6
23 #define ACP63_DEV			0x63
24 #define ACP70_DEV			0x70
25 
26 #define DMIC_INSTANCE			0x00
27 #define I2S_SP_INSTANCE			0x01
28 #define I2S_BT_INSTANCE			0x02
29 #define I2S_HS_INSTANCE			0x03
30 
31 #define MEM_WINDOW_START		0x4080000
32 
33 #define ACP_I2S_REG_START		0x1242400
34 #define ACP_I2S_REG_END			0x1242810
35 #define ACP3x_I2STDM_REG_START		0x1242400
36 #define ACP3x_I2STDM_REG_END		0x1242410
37 #define ACP3x_BT_TDM_REG_START		0x1242800
38 #define ACP3x_BT_TDM_REG_END		0x1242810
39 
40 #define THRESHOLD(bit, base)	((bit) + (base))
41 #define I2S_RX_THRESHOLD(base)	THRESHOLD(7, base)
42 #define I2S_TX_THRESHOLD(base)	THRESHOLD(8, base)
43 #define BT_TX_THRESHOLD(base)	THRESHOLD(6, base)
44 #define BT_RX_THRESHOLD(base)	THRESHOLD(5, base)
45 #define HS_TX_THRESHOLD(base)	THRESHOLD(4, base)
46 #define HS_RX_THRESHOLD(base)	THRESHOLD(3, base)
47 
48 #define ACP_SRAM_SP_PB_PTE_OFFSET	0x0
49 #define ACP_SRAM_SP_CP_PTE_OFFSET	0x100
50 #define ACP_SRAM_BT_PB_PTE_OFFSET	0x200
51 #define ACP_SRAM_BT_CP_PTE_OFFSET	0x300
52 #define ACP_SRAM_PDM_PTE_OFFSET		0x400
53 #define ACP_SRAM_HS_PB_PTE_OFFSET       0x500
54 #define ACP_SRAM_HS_CP_PTE_OFFSET       0x600
55 #define PAGE_SIZE_4K_ENABLE		0x2
56 
57 #define I2S_SP_TX_MEM_WINDOW_START	0x4000000
58 #define I2S_SP_RX_MEM_WINDOW_START	0x4020000
59 #define I2S_BT_TX_MEM_WINDOW_START	0x4040000
60 #define I2S_BT_RX_MEM_WINDOW_START	0x4060000
61 #define I2S_HS_TX_MEM_WINDOW_START      0x40A0000
62 #define I2S_HS_RX_MEM_WINDOW_START      0x40C0000
63 
64 #define SP_PB_FIFO_ADDR_OFFSET		0x500
65 #define SP_CAPT_FIFO_ADDR_OFFSET	0x700
66 #define BT_PB_FIFO_ADDR_OFFSET		0x900
67 #define BT_CAPT_FIFO_ADDR_OFFSET	0xB00
68 #define HS_PB_FIFO_ADDR_OFFSET		0xD00
69 #define HS_CAPT_FIFO_ADDR_OFFSET	0xF00
70 #define PLAYBACK_MIN_NUM_PERIODS	2
71 #define PLAYBACK_MAX_NUM_PERIODS	8
72 #define PLAYBACK_MAX_PERIOD_SIZE	8192
73 #define PLAYBACK_MIN_PERIOD_SIZE	1024
74 #define CAPTURE_MIN_NUM_PERIODS		2
75 #define CAPTURE_MAX_NUM_PERIODS		8
76 #define CAPTURE_MAX_PERIOD_SIZE		8192
77 #define CAPTURE_MIN_PERIOD_SIZE		1024
78 
79 #define MAX_BUFFER			65536
80 #define MIN_BUFFER			MAX_BUFFER
81 #define FIFO_SIZE			0x100
82 #define DMA_SIZE			0x40
83 #define FRM_LEN				0x100
84 
85 #define ACP3x_ITER_IRER_SAMP_LEN_MASK	0x38
86 
87 #define ACP_MAX_STREAM			8
88 
89 #define TDM_ENABLE	1
90 #define TDM_DISABLE	0
91 
92 #define SLOT_WIDTH_8	0x8
93 #define SLOT_WIDTH_16	0x10
94 #define SLOT_WIDTH_24	0x18
95 #define SLOT_WIDTH_32	0x20
96 
97 #define ACP6X_PGFSM_CONTROL                     0x1024
98 #define ACP6X_PGFSM_STATUS                      0x1028
99 
100 #define ACP63_PGFSM_CONTROL			ACP6X_PGFSM_CONTROL
101 #define ACP63_PGFSM_STATUS			ACP6X_PGFSM_STATUS
102 
103 #define ACP70_PGFSM_CONTROL			ACP6X_PGFSM_CONTROL
104 #define ACP70_PGFSM_STATUS			ACP6X_PGFSM_STATUS
105 
106 #define ACP_SOFT_RST_DONE_MASK	0x00010001
107 
108 #define ACP_PGFSM_CNTL_POWER_ON_MASK            0xffffffff
109 #define ACP_PGFSM_CNTL_POWER_OFF_MASK           0x00
110 #define ACP_PGFSM_STATUS_MASK                   0x03
111 #define ACP_POWERED_ON                          0x00
112 #define ACP_POWER_ON_IN_PROGRESS                0x01
113 #define ACP_POWERED_OFF                         0x02
114 #define ACP_POWER_OFF_IN_PROGRESS               0x03
115 
116 #define ACP_ERROR_MASK                          0x20000000
117 #define ACP_EXT_INTR_STAT_CLEAR_MASK            0xffffffff
118 
119 #define ACP_TIMEOUT		500
120 #define DELAY_US		5
121 #define ACP_SUSPEND_DELAY_MS   2000
122 
123 #define PDM_DMA_STAT            0x10
124 #define PDM_DMA_INTR_MASK       0x10000
125 #define PDM_DEC_64              0x2
126 #define PDM_CLK_FREQ_MASK       0x07
127 #define PDM_MISC_CTRL_MASK      0x10
128 #define PDM_ENABLE              0x01
129 #define PDM_DISABLE             0x00
130 #define DMA_EN_MASK             0x02
131 #define DELAY_US                5
132 #define PDM_TIMEOUT             1000
133 #define ACP_REGION2_OFFSET      0x02000000
134 
135 struct acp_chip_info {
136 	char *name;		/* Platform name */
137 	unsigned int acp_rev;	/* ACP Revision id */
138 	void __iomem *base;	/* ACP memory PCI base */
139 	struct platform_device *chip_pdev;
140 	unsigned int flag;	/* Distinguish b/w Legacy or Only PDM */
141 	bool is_pdm_dev;	/* flag set to true when ACP PDM controller exists */
142 	bool is_pdm_config;	/* flag set to true when PDM configuration is selected from BIOS */
143 	bool is_i2s_config;	/* flag set to true when I2S configuration is selected from BIOS */
144 };
145 
146 struct acp_stream {
147 	struct list_head list;
148 	struct snd_pcm_substream *substream;
149 	int irq_bit;
150 	int dai_id;
151 	int id;
152 	int dir;
153 	u64 bytescount;
154 	u32 reg_offset;
155 	u32 pte_offset;
156 	u32 fifo_offset;
157 };
158 
159 struct acp_resource {
160 	int offset;
161 	int no_of_ctrls;
162 	int irqp_used;
163 	bool soc_mclk;
164 	u32 irq_reg_offset;
165 	u64 scratch_reg_offset;
166 	u64 sram_pte_offset;
167 };
168 
169 struct acp_dev_data {
170 	char *name;
171 	struct device *dev;
172 	void __iomem *acp_base;
173 	unsigned int i2s_irq;
174 
175 	bool tdm_mode;
176 	bool is_i2s_config;
177 	/* SOC specific dais */
178 	struct snd_soc_dai_driver *dai_driver;
179 	int num_dai;
180 
181 	struct list_head stream_list;
182 	spinlock_t acp_lock;
183 
184 	struct snd_soc_acpi_mach *machines;
185 	struct platform_device *mach_dev;
186 
187 	u32 bclk_div;
188 	u32 lrclk_div;
189 
190 	struct acp_resource *rsrc;
191 	u32 ch_mask;
192 	u32 tdm_tx_fmt[3];
193 	u32 tdm_rx_fmt[3];
194 	u32 xfer_tx_resolution[3];
195 	u32 xfer_rx_resolution[3];
196 	unsigned int flag;
197 	unsigned int platform;
198 };
199 
200 enum acp_config {
201 	ACP_CONFIG_0 = 0,
202 	ACP_CONFIG_1,
203 	ACP_CONFIG_2,
204 	ACP_CONFIG_3,
205 	ACP_CONFIG_4,
206 	ACP_CONFIG_5,
207 	ACP_CONFIG_6,
208 	ACP_CONFIG_7,
209 	ACP_CONFIG_8,
210 	ACP_CONFIG_9,
211 	ACP_CONFIG_10,
212 	ACP_CONFIG_11,
213 	ACP_CONFIG_12,
214 	ACP_CONFIG_13,
215 	ACP_CONFIG_14,
216 	ACP_CONFIG_15,
217 	ACP_CONFIG_16,
218 	ACP_CONFIG_17,
219 	ACP_CONFIG_18,
220 	ACP_CONFIG_19,
221 	ACP_CONFIG_20,
222 };
223 
224 extern const struct snd_soc_dai_ops asoc_acp_cpu_dai_ops;
225 extern const struct snd_soc_dai_ops acp_dmic_dai_ops;
226 
227 int acp_platform_register(struct device *dev);
228 int acp_platform_unregister(struct device *dev);
229 
230 int acp_machine_select(struct acp_dev_data *adata);
231 
232 int smn_read(struct pci_dev *dev, u32 smn_addr);
233 int smn_write(struct pci_dev *dev, u32 smn_addr, u32 data);
234 
235 int acp_init(struct acp_chip_info *chip);
236 int acp_deinit(struct acp_chip_info *chip);
237 void acp_enable_interrupts(struct acp_dev_data *adata);
238 void acp_disable_interrupts(struct acp_dev_data *adata);
239 /* Machine configuration */
240 int snd_amd_acp_find_config(struct pci_dev *pci);
241 
242 void config_pte_for_stream(struct acp_dev_data *adata, struct acp_stream *stream);
243 void config_acp_dma(struct acp_dev_data *adata, struct acp_stream *stream, int size);
244 void restore_acp_pdm_params(struct snd_pcm_substream *substream,
245 			    struct acp_dev_data *adata);
246 
247 int restore_acp_i2s_params(struct snd_pcm_substream *substream,
248 			   struct acp_dev_data *adata, struct acp_stream *stream);
249 
250 void check_acp_config(struct pci_dev *pci, struct acp_chip_info *chip);
251 
252 static inline u64 acp_get_byte_count(struct acp_dev_data *adata, int dai_id, int direction)
253 {
254 	u64 byte_count = 0, low = 0, high = 0;
255 
256 	if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
257 		switch (dai_id) {
258 		case I2S_BT_INSTANCE:
259 			high = readl(adata->acp_base + ACP_BT_TX_LINEARPOSITIONCNTR_HIGH);
260 			low = readl(adata->acp_base + ACP_BT_TX_LINEARPOSITIONCNTR_LOW);
261 			break;
262 		case I2S_SP_INSTANCE:
263 			high = readl(adata->acp_base + ACP_I2S_TX_LINEARPOSITIONCNTR_HIGH);
264 			low = readl(adata->acp_base + ACP_I2S_TX_LINEARPOSITIONCNTR_LOW);
265 			break;
266 		case I2S_HS_INSTANCE:
267 			high = readl(adata->acp_base + ACP_HS_TX_LINEARPOSITIONCNTR_HIGH);
268 			low = readl(adata->acp_base + ACP_HS_TX_LINEARPOSITIONCNTR_LOW);
269 			break;
270 		default:
271 			dev_err(adata->dev, "Invalid dai id %x\n", dai_id);
272 			goto POINTER_RETURN_BYTES;
273 		}
274 	} else {
275 		switch (dai_id) {
276 		case I2S_BT_INSTANCE:
277 			high = readl(adata->acp_base + ACP_BT_RX_LINEARPOSITIONCNTR_HIGH);
278 			low = readl(adata->acp_base + ACP_BT_RX_LINEARPOSITIONCNTR_LOW);
279 			break;
280 		case I2S_SP_INSTANCE:
281 			high = readl(adata->acp_base + ACP_I2S_RX_LINEARPOSITIONCNTR_HIGH);
282 			low = readl(adata->acp_base + ACP_I2S_RX_LINEARPOSITIONCNTR_LOW);
283 			break;
284 		case I2S_HS_INSTANCE:
285 			high = readl(adata->acp_base + ACP_HS_RX_LINEARPOSITIONCNTR_HIGH);
286 			low = readl(adata->acp_base + ACP_HS_RX_LINEARPOSITIONCNTR_LOW);
287 			break;
288 		case DMIC_INSTANCE:
289 			high = readl(adata->acp_base + ACP_WOV_RX_LINEARPOSITIONCNTR_HIGH);
290 			low = readl(adata->acp_base + ACP_WOV_RX_LINEARPOSITIONCNTR_LOW);
291 			break;
292 		default:
293 			dev_err(adata->dev, "Invalid dai id %x\n", dai_id);
294 			goto POINTER_RETURN_BYTES;
295 		}
296 	}
297 	/* Get 64 bit value from two 32 bit registers */
298 	byte_count = (high << 32) | low;
299 
300 POINTER_RETURN_BYTES:
301 	return byte_count;
302 }
303 #endif
304