1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 // 3 // This file is provided under a dual BSD/GPLv2 license. When using or 4 // redistributing this file, you may do so under either license. 5 // 6 // Copyright(c) 2021 Advanced Micro Devices, Inc. 7 // 8 // Authors: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com> 9 // 10 11 /* 12 * Generic Hardware interface for ACP Audio I2S controller 13 */ 14 15 #include <linux/platform_device.h> 16 #include <linux/module.h> 17 #include <linux/err.h> 18 #include <linux/io.h> 19 #include <sound/pcm_params.h> 20 #include <sound/soc.h> 21 #include <sound/soc-dai.h> 22 #include <linux/dma-mapping.h> 23 #include <linux/bitfield.h> 24 25 #include "amd.h" 26 27 #define DRV_NAME "acp_i2s_playcap" 28 #define I2S_MASTER_MODE_ENABLE 1 29 #define LRCLK_DIV_FIELD GENMASK(10, 2) 30 #define BCLK_DIV_FIELD GENMASK(23, 11) 31 #define ACP63_LRCLK_DIV_FIELD GENMASK(12, 2) 32 #define ACP63_BCLK_DIV_FIELD GENMASK(23, 13) 33 34 static inline void acp_set_i2s_clk(struct acp_chip_info *chip, int dai_id) 35 { 36 u32 i2s_clk_reg, val; 37 38 switch (dai_id) { 39 case I2S_SP_INSTANCE: 40 i2s_clk_reg = ACP_I2STDM0_MSTRCLKGEN; 41 break; 42 case I2S_BT_INSTANCE: 43 i2s_clk_reg = ACP_I2STDM1_MSTRCLKGEN; 44 break; 45 case I2S_HS_INSTANCE: 46 i2s_clk_reg = ACP_I2STDM2_MSTRCLKGEN; 47 break; 48 default: 49 i2s_clk_reg = ACP_I2STDM0_MSTRCLKGEN; 50 break; 51 } 52 53 val = I2S_MASTER_MODE_ENABLE; 54 if (chip->tdm_mode) 55 val |= BIT(1); 56 57 switch (chip->acp_rev) { 58 case ACP63_PCI_ID: 59 case ACP70_PCI_ID: 60 case ACP71_PCI_ID: 61 case ACP72_PCI_ID: 62 val |= FIELD_PREP(ACP63_LRCLK_DIV_FIELD, chip->lrclk_div); 63 val |= FIELD_PREP(ACP63_BCLK_DIV_FIELD, chip->bclk_div); 64 break; 65 default: 66 val |= FIELD_PREP(LRCLK_DIV_FIELD, chip->lrclk_div); 67 val |= FIELD_PREP(BCLK_DIV_FIELD, chip->bclk_div); 68 } 69 writel(val, chip->base + i2s_clk_reg); 70 } 71 72 static int acp_i2s_set_fmt(struct snd_soc_dai *cpu_dai, 73 unsigned int fmt) 74 { 75 struct device *dev = cpu_dai->component->dev; 76 struct acp_chip_info *chip = dev_get_platdata(dev); 77 int mode; 78 79 mode = fmt & SND_SOC_DAIFMT_FORMAT_MASK; 80 switch (mode) { 81 case SND_SOC_DAIFMT_I2S: 82 chip->tdm_mode = TDM_DISABLE; 83 break; 84 case SND_SOC_DAIFMT_DSP_A: 85 chip->tdm_mode = TDM_ENABLE; 86 break; 87 default: 88 return -EINVAL; 89 } 90 return 0; 91 } 92 93 static int acp_i2s_set_tdm_slot(struct snd_soc_dai *dai, u32 tx_mask, u32 rx_mask, 94 int slots, int slot_width) 95 { 96 struct device *dev = dai->component->dev; 97 struct acp_chip_info *chip; 98 struct acp_stream *stream; 99 int slot_len, no_of_slots; 100 101 chip = dev_get_drvdata(dev->parent); 102 switch (slot_width) { 103 case SLOT_WIDTH_8: 104 slot_len = 8; 105 break; 106 case SLOT_WIDTH_16: 107 slot_len = 16; 108 break; 109 case SLOT_WIDTH_24: 110 slot_len = 24; 111 break; 112 case SLOT_WIDTH_32: 113 slot_len = 0; 114 break; 115 default: 116 dev_err(dev, "Unsupported bitdepth %d\n", slot_width); 117 return -EINVAL; 118 } 119 120 switch (chip->acp_rev) { 121 case ACP_RN_PCI_ID: 122 case ACP_RMB_PCI_ID: 123 switch (slots) { 124 case 1 ... 7: 125 no_of_slots = slots; 126 break; 127 case 8: 128 no_of_slots = 0; 129 break; 130 default: 131 dev_err(dev, "Unsupported slots %d\n", slots); 132 return -EINVAL; 133 } 134 break; 135 case ACP63_PCI_ID: 136 case ACP70_PCI_ID: 137 case ACP71_PCI_ID: 138 case ACP72_PCI_ID: 139 switch (slots) { 140 case 1 ... 31: 141 no_of_slots = slots; 142 break; 143 case 32: 144 no_of_slots = 0; 145 break; 146 default: 147 dev_err(dev, "Unsupported slots %d\n", slots); 148 return -EINVAL; 149 } 150 break; 151 default: 152 dev_err(dev, "Unknown chip revision %d\n", chip->acp_rev); 153 return -EINVAL; 154 } 155 156 slots = no_of_slots; 157 158 spin_lock_irq(&chip->acp_lock); 159 list_for_each_entry(stream, &chip->stream_list, list) { 160 switch (chip->acp_rev) { 161 case ACP_RN_PCI_ID: 162 case ACP_RMB_PCI_ID: 163 if (tx_mask && stream->dir == SNDRV_PCM_STREAM_PLAYBACK) 164 chip->tdm_tx_fmt[stream->dai_id - 1] = 165 FRM_LEN | (slots << 15) | (slot_len << 18); 166 else if (rx_mask && stream->dir == SNDRV_PCM_STREAM_CAPTURE) 167 chip->tdm_rx_fmt[stream->dai_id - 1] = 168 FRM_LEN | (slots << 15) | (slot_len << 18); 169 break; 170 case ACP63_PCI_ID: 171 case ACP70_PCI_ID: 172 case ACP71_PCI_ID: 173 case ACP72_PCI_ID: 174 if (tx_mask && stream->dir == SNDRV_PCM_STREAM_PLAYBACK) 175 chip->tdm_tx_fmt[stream->dai_id - 1] = 176 FRM_LEN | (slots << 13) | (slot_len << 18); 177 else if (rx_mask && stream->dir == SNDRV_PCM_STREAM_CAPTURE) 178 chip->tdm_rx_fmt[stream->dai_id - 1] = 179 FRM_LEN | (slots << 13) | (slot_len << 18); 180 break; 181 default: 182 dev_err(dev, "Unknown chip revision %d\n", chip->acp_rev); 183 spin_unlock_irq(&chip->acp_lock); 184 return -EINVAL; 185 } 186 } 187 spin_unlock_irq(&chip->acp_lock); 188 return 0; 189 } 190 191 static int acp_i2s_hwparams(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params, 192 struct snd_soc_dai *dai) 193 { 194 struct device *dev = dai->component->dev; 195 struct acp_chip_info *chip; 196 struct acp_resource *rsrc; 197 u32 val; 198 u32 xfer_resolution; 199 u32 reg_val, fmt_reg, tdm_fmt; 200 u32 lrclk_div_val, bclk_div_val; 201 202 chip = dev_get_platdata(dev); 203 rsrc = chip->rsrc; 204 205 /* These values are as per Hardware Spec */ 206 switch (params_format(params)) { 207 case SNDRV_PCM_FORMAT_U8: 208 case SNDRV_PCM_FORMAT_S8: 209 xfer_resolution = 0x0; 210 break; 211 case SNDRV_PCM_FORMAT_S16_LE: 212 xfer_resolution = 0x02; 213 break; 214 case SNDRV_PCM_FORMAT_S24_LE: 215 xfer_resolution = 0x04; 216 break; 217 case SNDRV_PCM_FORMAT_S32_LE: 218 xfer_resolution = 0x05; 219 break; 220 default: 221 return -EINVAL; 222 } 223 224 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 225 switch (dai->driver->id) { 226 case I2S_BT_INSTANCE: 227 reg_val = ACP_BTTDM_ITER; 228 fmt_reg = ACP_BTTDM_TXFRMT; 229 break; 230 case I2S_SP_INSTANCE: 231 reg_val = ACP_I2STDM_ITER; 232 fmt_reg = ACP_I2STDM_TXFRMT; 233 break; 234 case I2S_HS_INSTANCE: 235 reg_val = ACP_HSTDM_ITER; 236 fmt_reg = ACP_HSTDM_TXFRMT; 237 break; 238 default: 239 dev_err(dev, "Invalid dai id %x\n", dai->driver->id); 240 return -EINVAL; 241 } 242 chip->xfer_tx_resolution[dai->driver->id - 1] = xfer_resolution; 243 } else { 244 switch (dai->driver->id) { 245 case I2S_BT_INSTANCE: 246 reg_val = ACP_BTTDM_IRER; 247 fmt_reg = ACP_BTTDM_RXFRMT; 248 break; 249 case I2S_SP_INSTANCE: 250 reg_val = ACP_I2STDM_IRER; 251 fmt_reg = ACP_I2STDM_RXFRMT; 252 break; 253 case I2S_HS_INSTANCE: 254 reg_val = ACP_HSTDM_IRER; 255 fmt_reg = ACP_HSTDM_RXFRMT; 256 break; 257 default: 258 dev_err(dev, "Invalid dai id %x\n", dai->driver->id); 259 return -EINVAL; 260 } 261 chip->xfer_rx_resolution[dai->driver->id - 1] = xfer_resolution; 262 } 263 264 val = readl(chip->base + reg_val); 265 val &= ~ACP3x_ITER_IRER_SAMP_LEN_MASK; 266 val = val | (xfer_resolution << 3); 267 writel(val, chip->base + reg_val); 268 269 if (chip->tdm_mode) { 270 val = readl(chip->base + reg_val); 271 writel(val | BIT(1), chip->base + reg_val); 272 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 273 tdm_fmt = chip->tdm_tx_fmt[dai->driver->id - 1]; 274 else 275 tdm_fmt = chip->tdm_rx_fmt[dai->driver->id - 1]; 276 writel(tdm_fmt, chip->base + fmt_reg); 277 } 278 279 if (rsrc->soc_mclk) { 280 switch (params_format(params)) { 281 case SNDRV_PCM_FORMAT_S16_LE: 282 switch (params_rate(params)) { 283 case 8000: 284 bclk_div_val = 768; 285 break; 286 case 16000: 287 bclk_div_val = 384; 288 break; 289 case 24000: 290 bclk_div_val = 256; 291 break; 292 case 32000: 293 bclk_div_val = 192; 294 break; 295 case 44100: 296 case 48000: 297 bclk_div_val = 128; 298 break; 299 case 88200: 300 case 96000: 301 bclk_div_val = 64; 302 break; 303 case 192000: 304 bclk_div_val = 32; 305 break; 306 default: 307 return -EINVAL; 308 } 309 lrclk_div_val = 32; 310 break; 311 case SNDRV_PCM_FORMAT_S32_LE: 312 switch (params_rate(params)) { 313 case 8000: 314 bclk_div_val = 384; 315 break; 316 case 16000: 317 bclk_div_val = 192; 318 break; 319 case 24000: 320 bclk_div_val = 128; 321 break; 322 case 32000: 323 bclk_div_val = 96; 324 break; 325 case 44100: 326 case 48000: 327 bclk_div_val = 64; 328 break; 329 case 88200: 330 case 96000: 331 bclk_div_val = 32; 332 break; 333 case 192000: 334 bclk_div_val = 16; 335 break; 336 default: 337 return -EINVAL; 338 } 339 lrclk_div_val = 64; 340 break; 341 default: 342 return -EINVAL; 343 } 344 345 switch (params_rate(params)) { 346 case 8000: 347 case 16000: 348 case 24000: 349 case 48000: 350 case 96000: 351 case 192000: 352 switch (params_channels(params)) { 353 case 2: 354 break; 355 case 4: 356 bclk_div_val = bclk_div_val >> 1; 357 lrclk_div_val = lrclk_div_val << 1; 358 break; 359 case 8: 360 bclk_div_val = bclk_div_val >> 2; 361 lrclk_div_val = lrclk_div_val << 2; 362 break; 363 case 16: 364 bclk_div_val = bclk_div_val >> 3; 365 lrclk_div_val = lrclk_div_val << 3; 366 break; 367 case 32: 368 bclk_div_val = bclk_div_val >> 4; 369 lrclk_div_val = lrclk_div_val << 4; 370 break; 371 default: 372 dev_err(dev, "Unsupported channels %#x\n", 373 params_channels(params)); 374 } 375 break; 376 default: 377 break; 378 } 379 chip->lrclk_div = lrclk_div_val; 380 chip->bclk_div = bclk_div_val; 381 } 382 return 0; 383 } 384 385 static int acp_i2s_trigger(struct snd_pcm_substream *substream, int cmd, struct snd_soc_dai *dai) 386 { 387 struct acp_stream *stream = substream->runtime->private_data; 388 struct device *dev = dai->component->dev; 389 struct acp_chip_info *chip = dev_get_platdata(dev); 390 struct acp_resource *rsrc = chip->rsrc; 391 u32 val, period_bytes, reg_val, ier_val, water_val, buf_size, buf_reg; 392 393 period_bytes = frames_to_bytes(substream->runtime, substream->runtime->period_size); 394 buf_size = frames_to_bytes(substream->runtime, substream->runtime->buffer_size); 395 396 switch (cmd) { 397 case SNDRV_PCM_TRIGGER_START: 398 case SNDRV_PCM_TRIGGER_RESUME: 399 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 400 stream->bytescount = acp_get_byte_count(chip, stream->dai_id, substream->stream); 401 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 402 switch (dai->driver->id) { 403 case I2S_BT_INSTANCE: 404 water_val = ACP_BT_TX_INTR_WATERMARK_SIZE(chip); 405 reg_val = ACP_BTTDM_ITER; 406 ier_val = ACP_BTTDM_IER; 407 buf_reg = ACP_BT_TX_RINGBUFSIZE(chip); 408 break; 409 case I2S_SP_INSTANCE: 410 water_val = ACP_I2S_TX_INTR_WATERMARK_SIZE(chip); 411 reg_val = ACP_I2STDM_ITER; 412 ier_val = ACP_I2STDM_IER; 413 buf_reg = ACP_I2S_TX_RINGBUFSIZE(chip); 414 break; 415 case I2S_HS_INSTANCE: 416 water_val = ACP_HS_TX_INTR_WATERMARK_SIZE; 417 reg_val = ACP_HSTDM_ITER; 418 ier_val = ACP_HSTDM_IER; 419 buf_reg = ACP_HS_TX_RINGBUFSIZE; 420 break; 421 default: 422 dev_err(dev, "Invalid dai id %x\n", dai->driver->id); 423 return -EINVAL; 424 } 425 } else { 426 switch (dai->driver->id) { 427 case I2S_BT_INSTANCE: 428 water_val = ACP_BT_RX_INTR_WATERMARK_SIZE(chip); 429 reg_val = ACP_BTTDM_IRER; 430 ier_val = ACP_BTTDM_IER; 431 buf_reg = ACP_BT_RX_RINGBUFSIZE(chip); 432 break; 433 case I2S_SP_INSTANCE: 434 water_val = ACP_I2S_RX_INTR_WATERMARK_SIZE(chip); 435 reg_val = ACP_I2STDM_IRER; 436 ier_val = ACP_I2STDM_IER; 437 buf_reg = ACP_I2S_RX_RINGBUFSIZE(chip); 438 break; 439 case I2S_HS_INSTANCE: 440 water_val = ACP_HS_RX_INTR_WATERMARK_SIZE; 441 reg_val = ACP_HSTDM_IRER; 442 ier_val = ACP_HSTDM_IER; 443 buf_reg = ACP_HS_RX_RINGBUFSIZE; 444 break; 445 default: 446 dev_err(dev, "Invalid dai id %x\n", dai->driver->id); 447 return -EINVAL; 448 } 449 } 450 451 writel(period_bytes, chip->base + water_val); 452 writel(buf_size, chip->base + buf_reg); 453 if (rsrc->soc_mclk) 454 acp_set_i2s_clk(chip, dai->driver->id); 455 val = readl(chip->base + reg_val); 456 val = val | BIT(0); 457 writel(val, chip->base + reg_val); 458 writel(1, chip->base + ier_val); 459 return 0; 460 case SNDRV_PCM_TRIGGER_STOP: 461 case SNDRV_PCM_TRIGGER_SUSPEND: 462 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 463 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 464 switch (dai->driver->id) { 465 case I2S_BT_INSTANCE: 466 reg_val = ACP_BTTDM_ITER; 467 break; 468 case I2S_SP_INSTANCE: 469 reg_val = ACP_I2STDM_ITER; 470 break; 471 case I2S_HS_INSTANCE: 472 reg_val = ACP_HSTDM_ITER; 473 break; 474 default: 475 dev_err(dev, "Invalid dai id %x\n", dai->driver->id); 476 return -EINVAL; 477 } 478 479 } else { 480 switch (dai->driver->id) { 481 case I2S_BT_INSTANCE: 482 reg_val = ACP_BTTDM_IRER; 483 break; 484 case I2S_SP_INSTANCE: 485 reg_val = ACP_I2STDM_IRER; 486 break; 487 case I2S_HS_INSTANCE: 488 reg_val = ACP_HSTDM_IRER; 489 break; 490 default: 491 dev_err(dev, "Invalid dai id %x\n", dai->driver->id); 492 return -EINVAL; 493 } 494 } 495 val = readl(chip->base + reg_val); 496 val = val & ~BIT(0); 497 writel(val, chip->base + reg_val); 498 499 if (!(readl(chip->base + ACP_BTTDM_ITER) & BIT(0)) && 500 !(readl(chip->base + ACP_BTTDM_IRER) & BIT(0))) 501 writel(0, chip->base + ACP_BTTDM_IER); 502 if (!(readl(chip->base + ACP_I2STDM_ITER) & BIT(0)) && 503 !(readl(chip->base + ACP_I2STDM_IRER) & BIT(0))) 504 writel(0, chip->base + ACP_I2STDM_IER); 505 if (!(readl(chip->base + ACP_HSTDM_ITER) & BIT(0)) && 506 !(readl(chip->base + ACP_HSTDM_IRER) & BIT(0))) 507 writel(0, chip->base + ACP_HSTDM_IER); 508 return 0; 509 default: 510 return -EINVAL; 511 } 512 513 return 0; 514 } 515 516 static int acp_i2s_prepare(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) 517 { 518 struct device *dev = dai->component->dev; 519 struct acp_chip_info *chip = dev_get_platdata(dev); 520 struct acp_resource *rsrc = chip->rsrc; 521 struct acp_stream *stream = substream->runtime->private_data; 522 u32 reg_dma_size = 0, reg_fifo_size = 0, reg_fifo_addr = 0; 523 u32 phy_addr = 0, acp_fifo_addr = 0, ext_int_ctrl; 524 unsigned int dir = substream->stream; 525 526 chip = dev_get_platdata(dev); 527 switch (dai->driver->id) { 528 case I2S_SP_INSTANCE: 529 if (dir == SNDRV_PCM_STREAM_PLAYBACK) { 530 reg_dma_size = ACP_I2S_TX_DMA_SIZE(chip); 531 acp_fifo_addr = rsrc->sram_pte_offset + 532 SP_PB_FIFO_ADDR_OFFSET; 533 reg_fifo_addr = ACP_I2S_TX_FIFOADDR(chip); 534 reg_fifo_size = ACP_I2S_TX_FIFOSIZE(chip); 535 536 if (chip->acp_rev >= ACP70_PCI_ID) 537 phy_addr = ACP7x_I2S_SP_TX_MEM_WINDOW_START; 538 else 539 phy_addr = I2S_SP_TX_MEM_WINDOW_START + stream->reg_offset; 540 writel(phy_addr, chip->base + ACP_I2S_TX_RINGBUFADDR(chip)); 541 } else { 542 reg_dma_size = ACP_I2S_RX_DMA_SIZE(chip); 543 acp_fifo_addr = rsrc->sram_pte_offset + 544 SP_CAPT_FIFO_ADDR_OFFSET; 545 reg_fifo_addr = ACP_I2S_RX_FIFOADDR(chip); 546 reg_fifo_size = ACP_I2S_RX_FIFOSIZE(chip); 547 548 if (chip->acp_rev >= ACP70_PCI_ID) 549 phy_addr = ACP7x_I2S_SP_RX_MEM_WINDOW_START; 550 else 551 phy_addr = I2S_SP_RX_MEM_WINDOW_START + stream->reg_offset; 552 writel(phy_addr, chip->base + ACP_I2S_RX_RINGBUFADDR(chip)); 553 } 554 break; 555 case I2S_BT_INSTANCE: 556 if (dir == SNDRV_PCM_STREAM_PLAYBACK) { 557 reg_dma_size = ACP_BT_TX_DMA_SIZE(chip); 558 acp_fifo_addr = rsrc->sram_pte_offset + 559 BT_PB_FIFO_ADDR_OFFSET; 560 reg_fifo_addr = ACP_BT_TX_FIFOADDR(chip); 561 reg_fifo_size = ACP_BT_TX_FIFOSIZE(chip); 562 563 if (chip->acp_rev >= ACP70_PCI_ID) 564 phy_addr = ACP7x_I2S_BT_TX_MEM_WINDOW_START; 565 else 566 phy_addr = I2S_BT_TX_MEM_WINDOW_START + stream->reg_offset; 567 writel(phy_addr, chip->base + ACP_BT_TX_RINGBUFADDR(chip)); 568 } else { 569 reg_dma_size = ACP_BT_RX_DMA_SIZE(chip); 570 acp_fifo_addr = rsrc->sram_pte_offset + 571 BT_CAPT_FIFO_ADDR_OFFSET; 572 reg_fifo_addr = ACP_BT_RX_FIFOADDR(chip); 573 reg_fifo_size = ACP_BT_RX_FIFOSIZE(chip); 574 575 if (chip->acp_rev >= ACP70_PCI_ID) 576 phy_addr = ACP7x_I2S_BT_RX_MEM_WINDOW_START; 577 else 578 phy_addr = I2S_BT_TX_MEM_WINDOW_START + stream->reg_offset; 579 writel(phy_addr, chip->base + ACP_BT_RX_RINGBUFADDR(chip)); 580 } 581 break; 582 case I2S_HS_INSTANCE: 583 if (dir == SNDRV_PCM_STREAM_PLAYBACK) { 584 reg_dma_size = ACP_HS_TX_DMA_SIZE; 585 acp_fifo_addr = rsrc->sram_pte_offset + 586 HS_PB_FIFO_ADDR_OFFSET; 587 reg_fifo_addr = ACP_HS_TX_FIFOADDR; 588 reg_fifo_size = ACP_HS_TX_FIFOSIZE; 589 590 if (chip->acp_rev >= ACP70_PCI_ID) 591 phy_addr = ACP7x_I2S_HS_TX_MEM_WINDOW_START; 592 else 593 phy_addr = I2S_HS_TX_MEM_WINDOW_START + stream->reg_offset; 594 writel(phy_addr, chip->base + ACP_HS_TX_RINGBUFADDR); 595 } else { 596 reg_dma_size = ACP_HS_RX_DMA_SIZE; 597 acp_fifo_addr = rsrc->sram_pte_offset + 598 HS_CAPT_FIFO_ADDR_OFFSET; 599 reg_fifo_addr = ACP_HS_RX_FIFOADDR; 600 reg_fifo_size = ACP_HS_RX_FIFOSIZE; 601 602 if (chip->acp_rev >= ACP70_PCI_ID) 603 phy_addr = ACP7x_I2S_HS_RX_MEM_WINDOW_START; 604 else 605 phy_addr = I2S_HS_RX_MEM_WINDOW_START + stream->reg_offset; 606 writel(phy_addr, chip->base + ACP_HS_RX_RINGBUFADDR); 607 } 608 break; 609 default: 610 dev_err(dev, "Invalid dai id %x\n", dai->driver->id); 611 return -EINVAL; 612 } 613 614 writel(DMA_SIZE, chip->base + reg_dma_size); 615 writel(acp_fifo_addr, chip->base + reg_fifo_addr); 616 writel(FIFO_SIZE, chip->base + reg_fifo_size); 617 618 ext_int_ctrl = readl(ACP_EXTERNAL_INTR_CNTL(chip, rsrc->irqp_used)); 619 ext_int_ctrl |= BIT(I2S_RX_THRESHOLD(rsrc->offset)) | 620 BIT(BT_RX_THRESHOLD(rsrc->offset)) | 621 BIT(I2S_TX_THRESHOLD(rsrc->offset)) | 622 BIT(BT_TX_THRESHOLD(rsrc->offset)) | 623 BIT(HS_RX_THRESHOLD(rsrc->offset)) | 624 BIT(HS_TX_THRESHOLD(rsrc->offset)); 625 626 writel(ext_int_ctrl, ACP_EXTERNAL_INTR_CNTL(chip, rsrc->irqp_used)); 627 628 return 0; 629 } 630 631 static int acp_i2s_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) 632 { 633 struct acp_stream *stream = substream->runtime->private_data; 634 struct device *dev = dai->component->dev; 635 struct acp_chip_info *chip = dev_get_platdata(dev); 636 struct acp_resource *rsrc = chip->rsrc; 637 unsigned int dir = substream->stream; 638 unsigned int irq_bit = 0; 639 640 switch (dai->driver->id) { 641 case I2S_SP_INSTANCE: 642 if (dir == SNDRV_PCM_STREAM_PLAYBACK) { 643 irq_bit = BIT(I2S_TX_THRESHOLD(rsrc->offset)); 644 stream->pte_offset = ACP_SRAM_SP_PB_PTE_OFFSET; 645 stream->fifo_offset = SP_PB_FIFO_ADDR_OFFSET; 646 } else { 647 irq_bit = BIT(I2S_RX_THRESHOLD(rsrc->offset)); 648 stream->pte_offset = ACP_SRAM_SP_CP_PTE_OFFSET; 649 stream->fifo_offset = SP_CAPT_FIFO_ADDR_OFFSET; 650 } 651 break; 652 case I2S_BT_INSTANCE: 653 if (dir == SNDRV_PCM_STREAM_PLAYBACK) { 654 irq_bit = BIT(BT_TX_THRESHOLD(rsrc->offset)); 655 stream->pte_offset = ACP_SRAM_BT_PB_PTE_OFFSET; 656 stream->fifo_offset = BT_PB_FIFO_ADDR_OFFSET; 657 } else { 658 irq_bit = BIT(BT_RX_THRESHOLD(rsrc->offset)); 659 stream->pte_offset = ACP_SRAM_BT_CP_PTE_OFFSET; 660 stream->fifo_offset = BT_CAPT_FIFO_ADDR_OFFSET; 661 } 662 break; 663 case I2S_HS_INSTANCE: 664 if (dir == SNDRV_PCM_STREAM_PLAYBACK) { 665 irq_bit = BIT(HS_TX_THRESHOLD(rsrc->offset)); 666 stream->pte_offset = ACP_SRAM_HS_PB_PTE_OFFSET; 667 stream->fifo_offset = HS_PB_FIFO_ADDR_OFFSET; 668 } else { 669 irq_bit = BIT(HS_RX_THRESHOLD(rsrc->offset)); 670 stream->pte_offset = ACP_SRAM_HS_CP_PTE_OFFSET; 671 stream->fifo_offset = HS_CAPT_FIFO_ADDR_OFFSET; 672 } 673 break; 674 default: 675 dev_err(dev, "Invalid dai id %x\n", dai->driver->id); 676 return -EINVAL; 677 } 678 679 /* Save runtime dai configuration in stream */ 680 stream->id = dai->driver->id + dir; 681 stream->dai_id = dai->driver->id; 682 stream->irq_bit = irq_bit; 683 stream->dir = substream->stream; 684 685 return 0; 686 } 687 688 const struct snd_soc_dai_ops asoc_acp_cpu_dai_ops = { 689 .startup = acp_i2s_startup, 690 .hw_params = acp_i2s_hwparams, 691 .prepare = acp_i2s_prepare, 692 .trigger = acp_i2s_trigger, 693 .set_fmt = acp_i2s_set_fmt, 694 .set_tdm_slot = acp_i2s_set_tdm_slot, 695 }; 696 EXPORT_SYMBOL_NS_GPL(asoc_acp_cpu_dai_ops, "SND_SOC_ACP_COMMON"); 697 698 MODULE_DESCRIPTION("AMD ACP Audio I2S controller"); 699 MODULE_LICENSE("Dual BSD/GPL"); 700 MODULE_ALIAS(DRV_NAME); 701