1 /* 2 * AMD ALSA SoC PCM Driver for ACP 2.x 3 * 4 * Copyright 2014-2015 Advanced Micro Devices, Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 */ 15 16 #include <linux/module.h> 17 #include <linux/delay.h> 18 #include <linux/io.h> 19 #include <linux/iopoll.h> 20 #include <linux/sizes.h> 21 #include <linux/pm_runtime.h> 22 23 #include <sound/soc.h> 24 #include <drm/amd_asic_type.h> 25 #include "acp.h" 26 27 #define DRV_NAME "acp_audio_dma" 28 29 #define PLAYBACK_MIN_NUM_PERIODS 2 30 #define PLAYBACK_MAX_NUM_PERIODS 2 31 #define PLAYBACK_MAX_PERIOD_SIZE 16384 32 #define PLAYBACK_MIN_PERIOD_SIZE 1024 33 #define CAPTURE_MIN_NUM_PERIODS 2 34 #define CAPTURE_MAX_NUM_PERIODS 2 35 #define CAPTURE_MAX_PERIOD_SIZE 16384 36 #define CAPTURE_MIN_PERIOD_SIZE 1024 37 38 #define MAX_BUFFER (PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS) 39 #define MIN_BUFFER MAX_BUFFER 40 41 #define ST_PLAYBACK_MAX_PERIOD_SIZE 4096 42 #define ST_CAPTURE_MAX_PERIOD_SIZE ST_PLAYBACK_MAX_PERIOD_SIZE 43 #define ST_MAX_BUFFER (ST_PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS) 44 #define ST_MIN_BUFFER ST_MAX_BUFFER 45 46 #define DRV_NAME "acp_audio_dma" 47 bool bt_uart_enable = true; 48 EXPORT_SYMBOL(bt_uart_enable); 49 50 static const struct snd_pcm_hardware acp_pcm_hardware_playback = { 51 .info = SNDRV_PCM_INFO_INTERLEAVED | 52 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP | 53 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH | 54 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME, 55 .formats = SNDRV_PCM_FMTBIT_S16_LE | 56 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, 57 .channels_min = 1, 58 .channels_max = 8, 59 .rates = SNDRV_PCM_RATE_8000_96000, 60 .rate_min = 8000, 61 .rate_max = 96000, 62 .buffer_bytes_max = PLAYBACK_MAX_NUM_PERIODS * PLAYBACK_MAX_PERIOD_SIZE, 63 .period_bytes_min = PLAYBACK_MIN_PERIOD_SIZE, 64 .period_bytes_max = PLAYBACK_MAX_PERIOD_SIZE, 65 .periods_min = PLAYBACK_MIN_NUM_PERIODS, 66 .periods_max = PLAYBACK_MAX_NUM_PERIODS, 67 }; 68 69 static const struct snd_pcm_hardware acp_pcm_hardware_capture = { 70 .info = SNDRV_PCM_INFO_INTERLEAVED | 71 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP | 72 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH | 73 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME, 74 .formats = SNDRV_PCM_FMTBIT_S16_LE | 75 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, 76 .channels_min = 1, 77 .channels_max = 2, 78 .rates = SNDRV_PCM_RATE_8000_48000, 79 .rate_min = 8000, 80 .rate_max = 48000, 81 .buffer_bytes_max = CAPTURE_MAX_NUM_PERIODS * CAPTURE_MAX_PERIOD_SIZE, 82 .period_bytes_min = CAPTURE_MIN_PERIOD_SIZE, 83 .period_bytes_max = CAPTURE_MAX_PERIOD_SIZE, 84 .periods_min = CAPTURE_MIN_NUM_PERIODS, 85 .periods_max = CAPTURE_MAX_NUM_PERIODS, 86 }; 87 88 static const struct snd_pcm_hardware acp_st_pcm_hardware_playback = { 89 .info = SNDRV_PCM_INFO_INTERLEAVED | 90 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP | 91 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH | 92 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME, 93 .formats = SNDRV_PCM_FMTBIT_S16_LE | 94 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, 95 .channels_min = 1, 96 .channels_max = 8, 97 .rates = SNDRV_PCM_RATE_8000_96000, 98 .rate_min = 8000, 99 .rate_max = 96000, 100 .buffer_bytes_max = ST_MAX_BUFFER, 101 .period_bytes_min = PLAYBACK_MIN_PERIOD_SIZE, 102 .period_bytes_max = ST_PLAYBACK_MAX_PERIOD_SIZE, 103 .periods_min = PLAYBACK_MIN_NUM_PERIODS, 104 .periods_max = PLAYBACK_MAX_NUM_PERIODS, 105 }; 106 107 static const struct snd_pcm_hardware acp_st_pcm_hardware_capture = { 108 .info = SNDRV_PCM_INFO_INTERLEAVED | 109 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP | 110 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH | 111 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME, 112 .formats = SNDRV_PCM_FMTBIT_S16_LE | 113 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, 114 .channels_min = 1, 115 .channels_max = 2, 116 .rates = SNDRV_PCM_RATE_8000_48000, 117 .rate_min = 8000, 118 .rate_max = 48000, 119 .buffer_bytes_max = ST_MAX_BUFFER, 120 .period_bytes_min = CAPTURE_MIN_PERIOD_SIZE, 121 .period_bytes_max = ST_CAPTURE_MAX_PERIOD_SIZE, 122 .periods_min = CAPTURE_MIN_NUM_PERIODS, 123 .periods_max = CAPTURE_MAX_NUM_PERIODS, 124 }; 125 126 static u32 acp_reg_read(void __iomem *acp_mmio, u32 reg) 127 { 128 return readl(acp_mmio + (reg * 4)); 129 } 130 131 static void acp_reg_write(u32 val, void __iomem *acp_mmio, u32 reg) 132 { 133 writel(val, acp_mmio + (reg * 4)); 134 } 135 136 /* 137 * Configure a given dma channel parameters - enable/disable, 138 * number of descriptors, priority 139 */ 140 static void config_acp_dma_channel(void __iomem *acp_mmio, u8 ch_num, 141 u16 dscr_strt_idx, u16 num_dscrs, 142 enum acp_dma_priority_level priority_level) 143 { 144 u32 dma_ctrl; 145 146 /* disable the channel run field */ 147 dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 148 dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRun_MASK; 149 acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 150 151 /* program a DMA channel with first descriptor to be processed. */ 152 acp_reg_write((ACP_DMA_DSCR_STRT_IDX_0__DMAChDscrStrtIdx_MASK 153 & dscr_strt_idx), 154 acp_mmio, mmACP_DMA_DSCR_STRT_IDX_0 + ch_num); 155 156 /* 157 * program a DMA channel with the number of descriptors to be 158 * processed in the transfer 159 */ 160 acp_reg_write(ACP_DMA_DSCR_CNT_0__DMAChDscrCnt_MASK & num_dscrs, 161 acp_mmio, mmACP_DMA_DSCR_CNT_0 + ch_num); 162 163 /* set DMA channel priority */ 164 acp_reg_write(priority_level, acp_mmio, mmACP_DMA_PRIO_0 + ch_num); 165 } 166 167 /* Initialize a dma descriptor in SRAM based on descritor information passed */ 168 static void config_dma_descriptor_in_sram(void __iomem *acp_mmio, 169 u16 descr_idx, 170 acp_dma_dscr_transfer_t *descr_info) 171 { 172 u32 sram_offset; 173 174 sram_offset = (descr_idx * sizeof(acp_dma_dscr_transfer_t)); 175 176 /* program the source base address. */ 177 acp_reg_write(sram_offset, acp_mmio, mmACP_SRBM_Targ_Idx_Addr); 178 acp_reg_write(descr_info->src, acp_mmio, mmACP_SRBM_Targ_Idx_Data); 179 /* program the destination base address. */ 180 acp_reg_write(sram_offset + 4, acp_mmio, mmACP_SRBM_Targ_Idx_Addr); 181 acp_reg_write(descr_info->dest, acp_mmio, mmACP_SRBM_Targ_Idx_Data); 182 183 /* program the number of bytes to be transferred for this descriptor. */ 184 acp_reg_write(sram_offset + 8, acp_mmio, mmACP_SRBM_Targ_Idx_Addr); 185 acp_reg_write(descr_info->xfer_val, acp_mmio, mmACP_SRBM_Targ_Idx_Data); 186 } 187 188 static void pre_config_reset(void __iomem *acp_mmio, u16 ch_num) 189 { 190 u32 dma_ctrl; 191 int ret; 192 193 /* clear the reset bit */ 194 dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 195 dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRst_MASK; 196 acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 197 /* check the reset bit before programming configuration registers */ 198 ret = readl_poll_timeout(acp_mmio + ((mmACP_DMA_CNTL_0 + ch_num) * 4), 199 dma_ctrl, 200 !(dma_ctrl & ACP_DMA_CNTL_0__DMAChRst_MASK), 201 100, ACP_DMA_RESET_TIME); 202 if (ret < 0) 203 pr_err("Failed to clear reset of channel : %d\n", ch_num); 204 } 205 206 /* 207 * Initialize the DMA descriptor information for transfer between 208 * system memory <-> ACP SRAM 209 */ 210 static void set_acp_sysmem_dma_descriptors(void __iomem *acp_mmio, 211 u32 size, int direction, 212 u32 pte_offset, u16 ch, 213 u32 sram_bank, u16 dma_dscr_idx, 214 u32 asic_type) 215 { 216 u16 i; 217 acp_dma_dscr_transfer_t dmadscr[NUM_DSCRS_PER_CHANNEL]; 218 219 for (i = 0; i < NUM_DSCRS_PER_CHANNEL; i++) { 220 dmadscr[i].xfer_val = 0; 221 if (direction == SNDRV_PCM_STREAM_PLAYBACK) { 222 dma_dscr_idx = dma_dscr_idx + i; 223 dmadscr[i].dest = sram_bank + (i * (size / 2)); 224 dmadscr[i].src = ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS 225 + (pte_offset * SZ_4K) + (i * (size / 2)); 226 switch (asic_type) { 227 case CHIP_STONEY: 228 dmadscr[i].xfer_val |= 229 (ACP_DMA_ATTR_DAGB_GARLIC_TO_SHAREDMEM << 16) | 230 (size / 2); 231 break; 232 default: 233 dmadscr[i].xfer_val |= 234 (ACP_DMA_ATTR_DAGB_ONION_TO_SHAREDMEM << 16) | 235 (size / 2); 236 } 237 } else { 238 dma_dscr_idx = dma_dscr_idx + i; 239 dmadscr[i].src = sram_bank + (i * (size / 2)); 240 dmadscr[i].dest = 241 ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS + 242 (pte_offset * SZ_4K) + (i * (size / 2)); 243 switch (asic_type) { 244 case CHIP_STONEY: 245 dmadscr[i].xfer_val |= 246 (ACP_DMA_ATTR_SHARED_MEM_TO_DAGB_GARLIC << 16) | 247 (size / 2); 248 break; 249 default: 250 dmadscr[i].xfer_val |= 251 (ACP_DMA_ATTR_SHAREDMEM_TO_DAGB_ONION << 16) | 252 (size / 2); 253 } 254 } 255 config_dma_descriptor_in_sram(acp_mmio, dma_dscr_idx, 256 &dmadscr[i]); 257 } 258 pre_config_reset(acp_mmio, ch); 259 config_acp_dma_channel(acp_mmio, ch, 260 dma_dscr_idx - 1, 261 NUM_DSCRS_PER_CHANNEL, 262 ACP_DMA_PRIORITY_LEVEL_NORMAL); 263 } 264 265 /* 266 * Initialize the DMA descriptor information for transfer between 267 * ACP SRAM <-> I2S 268 */ 269 static void set_acp_to_i2s_dma_descriptors(void __iomem *acp_mmio, u32 size, 270 int direction, u32 sram_bank, 271 u16 destination, u16 ch, 272 u16 dma_dscr_idx, u32 asic_type) 273 { 274 u16 i; 275 acp_dma_dscr_transfer_t dmadscr[NUM_DSCRS_PER_CHANNEL]; 276 277 for (i = 0; i < NUM_DSCRS_PER_CHANNEL; i++) { 278 dmadscr[i].xfer_val = 0; 279 if (direction == SNDRV_PCM_STREAM_PLAYBACK) { 280 dma_dscr_idx = dma_dscr_idx + i; 281 dmadscr[i].src = sram_bank + (i * (size / 2)); 282 /* dmadscr[i].dest is unused by hardware. */ 283 dmadscr[i].dest = 0; 284 dmadscr[i].xfer_val |= BIT(22) | (destination << 16) | 285 (size / 2); 286 } else { 287 dma_dscr_idx = dma_dscr_idx + i; 288 /* dmadscr[i].src is unused by hardware. */ 289 dmadscr[i].src = 0; 290 dmadscr[i].dest = 291 sram_bank + (i * (size / 2)); 292 dmadscr[i].xfer_val |= BIT(22) | 293 (destination << 16) | (size / 2); 294 } 295 config_dma_descriptor_in_sram(acp_mmio, dma_dscr_idx, 296 &dmadscr[i]); 297 } 298 pre_config_reset(acp_mmio, ch); 299 /* Configure the DMA channel with the above descriptore */ 300 config_acp_dma_channel(acp_mmio, ch, dma_dscr_idx - 1, 301 NUM_DSCRS_PER_CHANNEL, 302 ACP_DMA_PRIORITY_LEVEL_NORMAL); 303 } 304 305 /* Create page table entries in ACP SRAM for the allocated memory */ 306 static void acp_pte_config(void __iomem *acp_mmio, struct page *pg, 307 u16 num_of_pages, u32 pte_offset) 308 { 309 u16 page_idx; 310 u64 addr; 311 u32 low; 312 u32 high; 313 u32 offset; 314 315 offset = ACP_DAGB_GRP_SRBM_SRAM_BASE_OFFSET + (pte_offset * 8); 316 for (page_idx = 0; page_idx < (num_of_pages); page_idx++) { 317 /* Load the low address of page int ACP SRAM through SRBM */ 318 acp_reg_write((offset + (page_idx * 8)), 319 acp_mmio, mmACP_SRBM_Targ_Idx_Addr); 320 addr = page_to_phys(pg); 321 322 low = lower_32_bits(addr); 323 high = upper_32_bits(addr); 324 325 acp_reg_write(low, acp_mmio, mmACP_SRBM_Targ_Idx_Data); 326 327 /* Load the High address of page int ACP SRAM through SRBM */ 328 acp_reg_write((offset + (page_idx * 8) + 4), 329 acp_mmio, mmACP_SRBM_Targ_Idx_Addr); 330 331 /* page enable in ACP */ 332 high |= BIT(31); 333 acp_reg_write(high, acp_mmio, mmACP_SRBM_Targ_Idx_Data); 334 335 /* Move to next physically contiguos page */ 336 pg++; 337 } 338 } 339 340 static void config_acp_dma(void __iomem *acp_mmio, 341 struct audio_substream_data *rtd, 342 u32 asic_type) 343 { 344 u16 ch_acp_sysmem, ch_acp_i2s; 345 346 acp_pte_config(acp_mmio, rtd->pg, rtd->num_of_pages, 347 rtd->pte_offset); 348 349 if (rtd->direction == SNDRV_PCM_STREAM_PLAYBACK) { 350 ch_acp_sysmem = rtd->ch1; 351 ch_acp_i2s = rtd->ch2; 352 } else { 353 ch_acp_i2s = rtd->ch1; 354 ch_acp_sysmem = rtd->ch2; 355 } 356 /* Configure System memory <-> ACP SRAM DMA descriptors */ 357 set_acp_sysmem_dma_descriptors(acp_mmio, rtd->size, 358 rtd->direction, rtd->pte_offset, 359 ch_acp_sysmem, rtd->sram_bank, 360 rtd->dma_dscr_idx_1, asic_type); 361 /* Configure ACP SRAM <-> I2S DMA descriptors */ 362 set_acp_to_i2s_dma_descriptors(acp_mmio, rtd->size, 363 rtd->direction, rtd->sram_bank, 364 rtd->destination, ch_acp_i2s, 365 rtd->dma_dscr_idx_2, asic_type); 366 } 367 368 static void acp_dma_cap_channel_enable(void __iomem *acp_mmio, 369 u16 cap_channel) 370 { 371 u32 val, ch_reg, imr_reg, res_reg; 372 373 switch (cap_channel) { 374 case CAP_CHANNEL1: 375 ch_reg = mmACP_I2SMICSP_RER1; 376 res_reg = mmACP_I2SMICSP_RCR1; 377 imr_reg = mmACP_I2SMICSP_IMR1; 378 break; 379 case CAP_CHANNEL0: 380 default: 381 ch_reg = mmACP_I2SMICSP_RER0; 382 res_reg = mmACP_I2SMICSP_RCR0; 383 imr_reg = mmACP_I2SMICSP_IMR0; 384 break; 385 } 386 val = acp_reg_read(acp_mmio, 387 mmACP_I2S_16BIT_RESOLUTION_EN); 388 if (val & ACP_I2S_MIC_16BIT_RESOLUTION_EN) { 389 acp_reg_write(0x0, acp_mmio, ch_reg); 390 /* Set 16bit resolution on capture */ 391 acp_reg_write(0x2, acp_mmio, res_reg); 392 } 393 val = acp_reg_read(acp_mmio, imr_reg); 394 val &= ~ACP_I2SMICSP_IMR1__I2SMICSP_RXDAM_MASK; 395 val &= ~ACP_I2SMICSP_IMR1__I2SMICSP_RXFOM_MASK; 396 acp_reg_write(val, acp_mmio, imr_reg); 397 acp_reg_write(0x1, acp_mmio, ch_reg); 398 } 399 400 static void acp_dma_cap_channel_disable(void __iomem *acp_mmio, 401 u16 cap_channel) 402 { 403 u32 val, ch_reg, imr_reg; 404 405 switch (cap_channel) { 406 case CAP_CHANNEL1: 407 imr_reg = mmACP_I2SMICSP_IMR1; 408 ch_reg = mmACP_I2SMICSP_RER1; 409 break; 410 case CAP_CHANNEL0: 411 default: 412 imr_reg = mmACP_I2SMICSP_IMR0; 413 ch_reg = mmACP_I2SMICSP_RER0; 414 break; 415 } 416 val = acp_reg_read(acp_mmio, imr_reg); 417 val |= ACP_I2SMICSP_IMR1__I2SMICSP_RXDAM_MASK; 418 val |= ACP_I2SMICSP_IMR1__I2SMICSP_RXFOM_MASK; 419 acp_reg_write(val, acp_mmio, imr_reg); 420 acp_reg_write(0x0, acp_mmio, ch_reg); 421 } 422 423 /* Start a given DMA channel transfer */ 424 static void acp_dma_start(void __iomem *acp_mmio, u16 ch_num, bool is_circular) 425 { 426 u32 dma_ctrl; 427 428 /* read the dma control register and disable the channel run field */ 429 dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 430 431 /* Invalidating the DAGB cache */ 432 acp_reg_write(1, acp_mmio, mmACP_DAGB_ATU_CTRL); 433 434 /* 435 * configure the DMA channel and start the DMA transfer 436 * set dmachrun bit to start the transfer and enable the 437 * interrupt on completion of the dma transfer 438 */ 439 dma_ctrl |= ACP_DMA_CNTL_0__DMAChRun_MASK; 440 441 switch (ch_num) { 442 case ACP_TO_I2S_DMA_CH_NUM: 443 case I2S_TO_ACP_DMA_CH_NUM: 444 case ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM: 445 case I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM: 446 dma_ctrl |= ACP_DMA_CNTL_0__DMAChIOCEn_MASK; 447 break; 448 default: 449 dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChIOCEn_MASK; 450 break; 451 } 452 453 /* enable for ACP to SRAM DMA channel */ 454 if (is_circular == true) 455 dma_ctrl |= ACP_DMA_CNTL_0__Circular_DMA_En_MASK; 456 else 457 dma_ctrl &= ~ACP_DMA_CNTL_0__Circular_DMA_En_MASK; 458 459 acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 460 } 461 462 /* Stop a given DMA channel transfer */ 463 static int acp_dma_stop(void __iomem *acp_mmio, u8 ch_num) 464 { 465 u32 dma_ctrl; 466 u32 dma_ch_sts; 467 u32 count = ACP_DMA_RESET_TIME; 468 469 dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 470 471 /* 472 * clear the dma control register fields before writing zero 473 * in reset bit 474 */ 475 dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRun_MASK; 476 dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChIOCEn_MASK; 477 478 acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 479 dma_ch_sts = acp_reg_read(acp_mmio, mmACP_DMA_CH_STS); 480 481 if (dma_ch_sts & BIT(ch_num)) { 482 /* 483 * set the reset bit for this channel to stop the dma 484 * transfer 485 */ 486 dma_ctrl |= ACP_DMA_CNTL_0__DMAChRst_MASK; 487 acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 488 } 489 490 /* check the channel status bit for some time and return the status */ 491 while (true) { 492 dma_ch_sts = acp_reg_read(acp_mmio, mmACP_DMA_CH_STS); 493 if (!(dma_ch_sts & BIT(ch_num))) { 494 /* 495 * clear the reset flag after successfully stopping 496 * the dma transfer and break from the loop 497 */ 498 dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRst_MASK; 499 500 acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 501 + ch_num); 502 break; 503 } 504 if (--count == 0) { 505 pr_err("Failed to stop ACP DMA channel : %d\n", ch_num); 506 return -ETIMEDOUT; 507 } 508 udelay(100); 509 } 510 return 0; 511 } 512 513 static void acp_set_sram_bank_state(void __iomem *acp_mmio, u16 bank, 514 bool power_on) 515 { 516 u32 val, req_reg, sts_reg, sts_reg_mask; 517 u32 loops = 1000; 518 519 if (bank < 32) { 520 req_reg = mmACP_MEM_SHUT_DOWN_REQ_LO; 521 sts_reg = mmACP_MEM_SHUT_DOWN_STS_LO; 522 sts_reg_mask = 0xFFFFFFFF; 523 524 } else { 525 bank -= 32; 526 req_reg = mmACP_MEM_SHUT_DOWN_REQ_HI; 527 sts_reg = mmACP_MEM_SHUT_DOWN_STS_HI; 528 sts_reg_mask = 0x0000FFFF; 529 } 530 531 val = acp_reg_read(acp_mmio, req_reg); 532 if (val & (1 << bank)) { 533 /* bank is in off state */ 534 if (power_on == true) 535 /* request to on */ 536 val &= ~(1 << bank); 537 else 538 /* request to off */ 539 return; 540 } else { 541 /* bank is in on state */ 542 if (power_on == false) 543 /* request to off */ 544 val |= 1 << bank; 545 else 546 /* request to on */ 547 return; 548 } 549 acp_reg_write(val, acp_mmio, req_reg); 550 551 while (acp_reg_read(acp_mmio, sts_reg) != sts_reg_mask) { 552 if (!loops--) { 553 pr_err("ACP SRAM bank %d state change failed\n", bank); 554 break; 555 } 556 cpu_relax(); 557 } 558 } 559 560 /* Initialize and bring ACP hardware to default state. */ 561 static int acp_init(void __iomem *acp_mmio, u32 asic_type) 562 { 563 u16 bank; 564 u32 val, count, sram_pte_offset; 565 566 /* Assert Soft reset of ACP */ 567 val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET); 568 569 val |= ACP_SOFT_RESET__SoftResetAud_MASK; 570 acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET); 571 572 count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE; 573 while (true) { 574 val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET); 575 if (ACP_SOFT_RESET__SoftResetAudDone_MASK == 576 (val & ACP_SOFT_RESET__SoftResetAudDone_MASK)) 577 break; 578 if (--count == 0) { 579 pr_err("Failed to reset ACP\n"); 580 return -ETIMEDOUT; 581 } 582 udelay(100); 583 } 584 585 /* Enable clock to ACP and wait until the clock is enabled */ 586 val = acp_reg_read(acp_mmio, mmACP_CONTROL); 587 val = val | ACP_CONTROL__ClkEn_MASK; 588 acp_reg_write(val, acp_mmio, mmACP_CONTROL); 589 590 count = ACP_CLOCK_EN_TIME_OUT_VALUE; 591 592 while (true) { 593 val = acp_reg_read(acp_mmio, mmACP_STATUS); 594 if (val & (u32)0x1) 595 break; 596 if (--count == 0) { 597 pr_err("Failed to reset ACP\n"); 598 return -ETIMEDOUT; 599 } 600 udelay(100); 601 } 602 603 /* Deassert the SOFT RESET flags */ 604 val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET); 605 val &= ~ACP_SOFT_RESET__SoftResetAud_MASK; 606 acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET); 607 608 /* For BT instance change pins from UART to BT */ 609 if (!bt_uart_enable) { 610 val = acp_reg_read(acp_mmio, mmACP_BT_UART_PAD_SEL); 611 val |= ACP_BT_UART_PAD_SELECT_MASK; 612 acp_reg_write(val, acp_mmio, mmACP_BT_UART_PAD_SEL); 613 } 614 615 /* initiailize Onion control DAGB register */ 616 acp_reg_write(ACP_ONION_CNTL_DEFAULT, acp_mmio, 617 mmACP_AXI2DAGB_ONION_CNTL); 618 619 /* initiailize Garlic control DAGB registers */ 620 acp_reg_write(ACP_GARLIC_CNTL_DEFAULT, acp_mmio, 621 mmACP_AXI2DAGB_GARLIC_CNTL); 622 623 sram_pte_offset = ACP_DAGB_GRP_SRAM_BASE_ADDRESS | 624 ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBSnoopSel_MASK | 625 ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBTargetMemSel_MASK | 626 ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBGrpEnable_MASK; 627 acp_reg_write(sram_pte_offset, acp_mmio, mmACP_DAGB_BASE_ADDR_GRP_1); 628 acp_reg_write(ACP_PAGE_SIZE_4K_ENABLE, acp_mmio, 629 mmACP_DAGB_PAGE_SIZE_GRP_1); 630 631 acp_reg_write(ACP_SRAM_BASE_ADDRESS, acp_mmio, 632 mmACP_DMA_DESC_BASE_ADDR); 633 634 /* Num of descriptiors in SRAM 0x4, means 256 descriptors;(64 * 4) */ 635 acp_reg_write(0x4, acp_mmio, mmACP_DMA_DESC_MAX_NUM_DSCR); 636 acp_reg_write(ACP_EXTERNAL_INTR_CNTL__DMAIOCMask_MASK, 637 acp_mmio, mmACP_EXTERNAL_INTR_CNTL); 638 639 /* 640 * When ACP_TILE_P1 is turned on, all SRAM banks get turned on. 641 * Now, turn off all of them. This can't be done in 'poweron' of 642 * ACP pm domain, as this requires ACP to be initialized. 643 * For Stoney, Memory gating is disabled,i.e SRAM Banks 644 * won't be turned off. The default state for SRAM banks is ON. 645 * Setting SRAM bank state code skipped for STONEY platform. 646 */ 647 if (asic_type != CHIP_STONEY) { 648 for (bank = 1; bank < 48; bank++) 649 acp_set_sram_bank_state(acp_mmio, bank, false); 650 } 651 return 0; 652 } 653 654 /* Deinitialize ACP */ 655 static int acp_deinit(void __iomem *acp_mmio) 656 { 657 u32 val; 658 u32 count; 659 660 /* Assert Soft reset of ACP */ 661 val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET); 662 663 val |= ACP_SOFT_RESET__SoftResetAud_MASK; 664 acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET); 665 666 count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE; 667 while (true) { 668 val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET); 669 if (ACP_SOFT_RESET__SoftResetAudDone_MASK == 670 (val & ACP_SOFT_RESET__SoftResetAudDone_MASK)) 671 break; 672 if (--count == 0) { 673 pr_err("Failed to reset ACP\n"); 674 return -ETIMEDOUT; 675 } 676 udelay(100); 677 } 678 /* Disable ACP clock */ 679 val = acp_reg_read(acp_mmio, mmACP_CONTROL); 680 val &= ~ACP_CONTROL__ClkEn_MASK; 681 acp_reg_write(val, acp_mmio, mmACP_CONTROL); 682 683 count = ACP_CLOCK_EN_TIME_OUT_VALUE; 684 685 while (true) { 686 val = acp_reg_read(acp_mmio, mmACP_STATUS); 687 if (!(val & (u32)0x1)) 688 break; 689 if (--count == 0) { 690 pr_err("Failed to reset ACP\n"); 691 return -ETIMEDOUT; 692 } 693 udelay(100); 694 } 695 return 0; 696 } 697 698 /* ACP DMA irq handler routine for playback, capture usecases */ 699 static irqreturn_t dma_irq_handler(int irq, void *arg) 700 { 701 u16 dscr_idx; 702 u32 intr_flag, ext_intr_status; 703 struct audio_drv_data *irq_data; 704 void __iomem *acp_mmio; 705 struct device *dev = arg; 706 bool valid_irq = false; 707 708 irq_data = dev_get_drvdata(dev); 709 acp_mmio = irq_data->acp_mmio; 710 711 ext_intr_status = acp_reg_read(acp_mmio, mmACP_EXTERNAL_INTR_STAT); 712 intr_flag = (((ext_intr_status & 713 ACP_EXTERNAL_INTR_STAT__DMAIOCStat_MASK) >> 714 ACP_EXTERNAL_INTR_STAT__DMAIOCStat__SHIFT)); 715 716 if ((intr_flag & BIT(ACP_TO_I2S_DMA_CH_NUM)) != 0) { 717 valid_irq = true; 718 snd_pcm_period_elapsed(irq_data->play_i2ssp_stream); 719 acp_reg_write((intr_flag & BIT(ACP_TO_I2S_DMA_CH_NUM)) << 16, 720 acp_mmio, mmACP_EXTERNAL_INTR_STAT); 721 } 722 723 if ((intr_flag & BIT(ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM)) != 0) { 724 valid_irq = true; 725 snd_pcm_period_elapsed(irq_data->play_i2sbt_stream); 726 acp_reg_write((intr_flag & 727 BIT(ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM)) << 16, 728 acp_mmio, mmACP_EXTERNAL_INTR_STAT); 729 } 730 731 if ((intr_flag & BIT(I2S_TO_ACP_DMA_CH_NUM)) != 0) { 732 valid_irq = true; 733 if (acp_reg_read(acp_mmio, mmACP_DMA_CUR_DSCR_14) == 734 CAPTURE_START_DMA_DESCR_CH15) 735 dscr_idx = CAPTURE_END_DMA_DESCR_CH14; 736 else 737 dscr_idx = CAPTURE_START_DMA_DESCR_CH14; 738 config_acp_dma_channel(acp_mmio, ACP_TO_SYSRAM_CH_NUM, dscr_idx, 739 1, 0); 740 acp_dma_start(acp_mmio, ACP_TO_SYSRAM_CH_NUM, false); 741 742 snd_pcm_period_elapsed(irq_data->capture_i2ssp_stream); 743 acp_reg_write((intr_flag & BIT(I2S_TO_ACP_DMA_CH_NUM)) << 16, 744 acp_mmio, mmACP_EXTERNAL_INTR_STAT); 745 } 746 747 if ((intr_flag & BIT(I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM)) != 0) { 748 valid_irq = true; 749 if (acp_reg_read(acp_mmio, mmACP_DMA_CUR_DSCR_10) == 750 CAPTURE_START_DMA_DESCR_CH11) 751 dscr_idx = CAPTURE_END_DMA_DESCR_CH10; 752 else 753 dscr_idx = CAPTURE_START_DMA_DESCR_CH10; 754 config_acp_dma_channel(acp_mmio, 755 ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM, 756 dscr_idx, 1, 0); 757 acp_dma_start(acp_mmio, ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM, 758 false); 759 760 snd_pcm_period_elapsed(irq_data->capture_i2sbt_stream); 761 acp_reg_write((intr_flag & 762 BIT(I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM)) << 16, 763 acp_mmio, mmACP_EXTERNAL_INTR_STAT); 764 } 765 766 if (valid_irq) 767 return IRQ_HANDLED; 768 else 769 return IRQ_NONE; 770 } 771 772 static int acp_dma_open(struct snd_pcm_substream *substream) 773 { 774 u16 bank; 775 int ret = 0; 776 struct snd_pcm_runtime *runtime = substream->runtime; 777 struct snd_soc_pcm_runtime *prtd = substream->private_data; 778 struct snd_soc_component *component = snd_soc_rtdcom_lookup(prtd, 779 DRV_NAME); 780 struct audio_drv_data *intr_data = dev_get_drvdata(component->dev); 781 struct audio_substream_data *adata = 782 kzalloc(sizeof(struct audio_substream_data), GFP_KERNEL); 783 if (!adata) 784 return -ENOMEM; 785 786 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 787 switch (intr_data->asic_type) { 788 case CHIP_STONEY: 789 runtime->hw = acp_st_pcm_hardware_playback; 790 break; 791 default: 792 runtime->hw = acp_pcm_hardware_playback; 793 } 794 } else { 795 switch (intr_data->asic_type) { 796 case CHIP_STONEY: 797 runtime->hw = acp_st_pcm_hardware_capture; 798 break; 799 default: 800 runtime->hw = acp_pcm_hardware_capture; 801 } 802 } 803 804 ret = snd_pcm_hw_constraint_integer(runtime, 805 SNDRV_PCM_HW_PARAM_PERIODS); 806 if (ret < 0) { 807 dev_err(component->dev, "set integer constraint failed\n"); 808 kfree(adata); 809 return ret; 810 } 811 812 adata->acp_mmio = intr_data->acp_mmio; 813 runtime->private_data = adata; 814 815 /* 816 * Enable ACP irq, when neither playback or capture streams are 817 * active by the time when a new stream is being opened. 818 * This enablement is not required for another stream, if current 819 * stream is not closed 820 */ 821 if (!intr_data->play_i2ssp_stream && !intr_data->capture_i2ssp_stream && 822 !intr_data->play_i2sbt_stream && !intr_data->capture_i2sbt_stream) 823 acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB); 824 825 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 826 /* 827 * For Stoney, Memory gating is disabled,i.e SRAM Banks 828 * won't be turned off. The default state for SRAM banks is ON. 829 * Setting SRAM bank state code skipped for STONEY platform. 830 */ 831 if (intr_data->asic_type != CHIP_STONEY) { 832 for (bank = 1; bank <= 4; bank++) 833 acp_set_sram_bank_state(intr_data->acp_mmio, 834 bank, true); 835 } 836 } else { 837 if (intr_data->asic_type != CHIP_STONEY) { 838 for (bank = 5; bank <= 8; bank++) 839 acp_set_sram_bank_state(intr_data->acp_mmio, 840 bank, true); 841 } 842 } 843 844 return 0; 845 } 846 847 static int acp_dma_hw_params(struct snd_pcm_substream *substream, 848 struct snd_pcm_hw_params *params) 849 { 850 int status; 851 uint64_t size; 852 u32 val = 0; 853 struct page *pg; 854 struct snd_pcm_runtime *runtime; 855 struct audio_substream_data *rtd; 856 struct snd_soc_pcm_runtime *prtd = substream->private_data; 857 struct snd_soc_component *component = snd_soc_rtdcom_lookup(prtd, 858 DRV_NAME); 859 struct audio_drv_data *adata = dev_get_drvdata(component->dev); 860 struct snd_soc_card *card = prtd->card; 861 struct acp_platform_info *pinfo = snd_soc_card_get_drvdata(card); 862 863 runtime = substream->runtime; 864 rtd = runtime->private_data; 865 866 if (WARN_ON(!rtd)) 867 return -EINVAL; 868 869 if (pinfo) { 870 rtd->i2s_instance = pinfo->i2s_instance; 871 rtd->capture_channel = pinfo->capture_channel; 872 } 873 if (adata->asic_type == CHIP_STONEY) { 874 val = acp_reg_read(adata->acp_mmio, 875 mmACP_I2S_16BIT_RESOLUTION_EN); 876 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 877 switch (rtd->i2s_instance) { 878 case I2S_BT_INSTANCE: 879 val |= ACP_I2S_BT_16BIT_RESOLUTION_EN; 880 break; 881 case I2S_SP_INSTANCE: 882 default: 883 val |= ACP_I2S_SP_16BIT_RESOLUTION_EN; 884 } 885 } else { 886 switch (rtd->i2s_instance) { 887 case I2S_BT_INSTANCE: 888 val |= ACP_I2S_BT_16BIT_RESOLUTION_EN; 889 break; 890 case I2S_SP_INSTANCE: 891 default: 892 val |= ACP_I2S_MIC_16BIT_RESOLUTION_EN; 893 } 894 } 895 acp_reg_write(val, adata->acp_mmio, 896 mmACP_I2S_16BIT_RESOLUTION_EN); 897 } 898 899 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 900 switch (rtd->i2s_instance) { 901 case I2S_BT_INSTANCE: 902 rtd->pte_offset = ACP_ST_BT_PLAYBACK_PTE_OFFSET; 903 rtd->ch1 = SYSRAM_TO_ACP_BT_INSTANCE_CH_NUM; 904 rtd->ch2 = ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM; 905 rtd->sram_bank = ACP_SRAM_BANK_3_ADDRESS; 906 rtd->destination = TO_BLUETOOTH; 907 rtd->dma_dscr_idx_1 = PLAYBACK_START_DMA_DESCR_CH8; 908 rtd->dma_dscr_idx_2 = PLAYBACK_START_DMA_DESCR_CH9; 909 rtd->byte_cnt_high_reg_offset = 910 mmACP_I2S_BT_TRANSMIT_BYTE_CNT_HIGH; 911 rtd->byte_cnt_low_reg_offset = 912 mmACP_I2S_BT_TRANSMIT_BYTE_CNT_LOW; 913 adata->play_i2sbt_stream = substream; 914 break; 915 case I2S_SP_INSTANCE: 916 default: 917 switch (adata->asic_type) { 918 case CHIP_STONEY: 919 rtd->pte_offset = ACP_ST_PLAYBACK_PTE_OFFSET; 920 break; 921 default: 922 rtd->pte_offset = ACP_PLAYBACK_PTE_OFFSET; 923 } 924 rtd->ch1 = SYSRAM_TO_ACP_CH_NUM; 925 rtd->ch2 = ACP_TO_I2S_DMA_CH_NUM; 926 rtd->sram_bank = ACP_SRAM_BANK_1_ADDRESS; 927 rtd->destination = TO_ACP_I2S_1; 928 rtd->dma_dscr_idx_1 = PLAYBACK_START_DMA_DESCR_CH12; 929 rtd->dma_dscr_idx_2 = PLAYBACK_START_DMA_DESCR_CH13; 930 rtd->byte_cnt_high_reg_offset = 931 mmACP_I2S_TRANSMIT_BYTE_CNT_HIGH; 932 rtd->byte_cnt_low_reg_offset = 933 mmACP_I2S_TRANSMIT_BYTE_CNT_LOW; 934 adata->play_i2ssp_stream = substream; 935 } 936 } else { 937 switch (rtd->i2s_instance) { 938 case I2S_BT_INSTANCE: 939 rtd->pte_offset = ACP_ST_BT_CAPTURE_PTE_OFFSET; 940 rtd->ch1 = I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM; 941 rtd->ch2 = ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM; 942 rtd->sram_bank = ACP_SRAM_BANK_4_ADDRESS; 943 rtd->destination = FROM_BLUETOOTH; 944 rtd->dma_dscr_idx_1 = CAPTURE_START_DMA_DESCR_CH10; 945 rtd->dma_dscr_idx_2 = CAPTURE_START_DMA_DESCR_CH11; 946 rtd->byte_cnt_high_reg_offset = 947 mmACP_I2S_BT_RECEIVE_BYTE_CNT_HIGH; 948 rtd->byte_cnt_low_reg_offset = 949 mmACP_I2S_BT_RECEIVE_BYTE_CNT_LOW; 950 rtd->dma_curr_dscr = mmACP_DMA_CUR_DSCR_11; 951 adata->capture_i2sbt_stream = substream; 952 break; 953 case I2S_SP_INSTANCE: 954 default: 955 rtd->pte_offset = ACP_CAPTURE_PTE_OFFSET; 956 rtd->ch1 = I2S_TO_ACP_DMA_CH_NUM; 957 rtd->ch2 = ACP_TO_SYSRAM_CH_NUM; 958 switch (adata->asic_type) { 959 case CHIP_STONEY: 960 rtd->pte_offset = ACP_ST_CAPTURE_PTE_OFFSET; 961 rtd->sram_bank = ACP_SRAM_BANK_2_ADDRESS; 962 break; 963 default: 964 rtd->pte_offset = ACP_CAPTURE_PTE_OFFSET; 965 rtd->sram_bank = ACP_SRAM_BANK_5_ADDRESS; 966 } 967 rtd->destination = FROM_ACP_I2S_1; 968 rtd->dma_dscr_idx_1 = CAPTURE_START_DMA_DESCR_CH14; 969 rtd->dma_dscr_idx_2 = CAPTURE_START_DMA_DESCR_CH15; 970 rtd->byte_cnt_high_reg_offset = 971 mmACP_I2S_RECEIVED_BYTE_CNT_HIGH; 972 rtd->byte_cnt_low_reg_offset = 973 mmACP_I2S_RECEIVED_BYTE_CNT_LOW; 974 rtd->dma_curr_dscr = mmACP_DMA_CUR_DSCR_15; 975 adata->capture_i2ssp_stream = substream; 976 } 977 } 978 979 size = params_buffer_bytes(params); 980 status = snd_pcm_lib_malloc_pages(substream, size); 981 if (status < 0) 982 return status; 983 984 memset(substream->runtime->dma_area, 0, params_buffer_bytes(params)); 985 pg = virt_to_page(substream->dma_buffer.area); 986 987 if (pg) { 988 acp_set_sram_bank_state(rtd->acp_mmio, 0, true); 989 /* Save for runtime private data */ 990 rtd->pg = pg; 991 rtd->order = get_order(size); 992 993 /* Fill the page table entries in ACP SRAM */ 994 rtd->pg = pg; 995 rtd->size = size; 996 rtd->num_of_pages = PAGE_ALIGN(size) >> PAGE_SHIFT; 997 rtd->direction = substream->stream; 998 999 config_acp_dma(rtd->acp_mmio, rtd, adata->asic_type); 1000 status = 0; 1001 } else { 1002 status = -ENOMEM; 1003 } 1004 return status; 1005 } 1006 1007 static int acp_dma_hw_free(struct snd_pcm_substream *substream) 1008 { 1009 return snd_pcm_lib_free_pages(substream); 1010 } 1011 1012 static u64 acp_get_byte_count(struct audio_substream_data *rtd) 1013 { 1014 union acp_dma_count byte_count; 1015 1016 byte_count.bcount.high = acp_reg_read(rtd->acp_mmio, 1017 rtd->byte_cnt_high_reg_offset); 1018 byte_count.bcount.low = acp_reg_read(rtd->acp_mmio, 1019 rtd->byte_cnt_low_reg_offset); 1020 return byte_count.bytescount; 1021 } 1022 1023 static snd_pcm_uframes_t acp_dma_pointer(struct snd_pcm_substream *substream) 1024 { 1025 u32 buffersize; 1026 u32 pos = 0; 1027 u64 bytescount = 0; 1028 u16 dscr; 1029 u32 period_bytes, delay; 1030 1031 struct snd_pcm_runtime *runtime = substream->runtime; 1032 struct audio_substream_data *rtd = runtime->private_data; 1033 1034 if (!rtd) 1035 return -EINVAL; 1036 1037 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { 1038 period_bytes = frames_to_bytes(runtime, runtime->period_size); 1039 dscr = acp_reg_read(rtd->acp_mmio, rtd->dma_curr_dscr); 1040 if (dscr == rtd->dma_dscr_idx_1) 1041 pos = period_bytes; 1042 else 1043 pos = 0; 1044 bytescount = acp_get_byte_count(rtd); 1045 if (bytescount > rtd->bytescount) 1046 bytescount -= rtd->bytescount; 1047 delay = do_div(bytescount, period_bytes); 1048 runtime->delay = bytes_to_frames(runtime, delay); 1049 } else { 1050 buffersize = frames_to_bytes(runtime, runtime->buffer_size); 1051 bytescount = acp_get_byte_count(rtd); 1052 if (bytescount > rtd->bytescount) 1053 bytescount -= rtd->bytescount; 1054 pos = do_div(bytescount, buffersize); 1055 } 1056 return bytes_to_frames(runtime, pos); 1057 } 1058 1059 static int acp_dma_mmap(struct snd_pcm_substream *substream, 1060 struct vm_area_struct *vma) 1061 { 1062 return snd_pcm_lib_default_mmap(substream, vma); 1063 } 1064 1065 static int acp_dma_prepare(struct snd_pcm_substream *substream) 1066 { 1067 struct snd_pcm_runtime *runtime = substream->runtime; 1068 struct audio_substream_data *rtd = runtime->private_data; 1069 u16 ch_acp_sysmem, ch_acp_i2s; 1070 1071 if (!rtd) 1072 return -EINVAL; 1073 1074 if (rtd->direction == SNDRV_PCM_STREAM_PLAYBACK) { 1075 ch_acp_sysmem = rtd->ch1; 1076 ch_acp_i2s = rtd->ch2; 1077 } else { 1078 ch_acp_i2s = rtd->ch1; 1079 ch_acp_sysmem = rtd->ch2; 1080 } 1081 config_acp_dma_channel(rtd->acp_mmio, 1082 ch_acp_sysmem, 1083 rtd->dma_dscr_idx_1, 1084 NUM_DSCRS_PER_CHANNEL, 0); 1085 config_acp_dma_channel(rtd->acp_mmio, 1086 ch_acp_i2s, 1087 rtd->dma_dscr_idx_2, 1088 NUM_DSCRS_PER_CHANNEL, 0); 1089 return 0; 1090 } 1091 1092 static int acp_dma_trigger(struct snd_pcm_substream *substream, int cmd) 1093 { 1094 int ret; 1095 1096 struct snd_pcm_runtime *runtime = substream->runtime; 1097 struct audio_substream_data *rtd = runtime->private_data; 1098 1099 if (!rtd) 1100 return -EINVAL; 1101 switch (cmd) { 1102 case SNDRV_PCM_TRIGGER_START: 1103 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1104 case SNDRV_PCM_TRIGGER_RESUME: 1105 rtd->bytescount = acp_get_byte_count(rtd); 1106 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { 1107 if (rtd->capture_channel == CAP_CHANNEL0) { 1108 acp_dma_cap_channel_disable(rtd->acp_mmio, 1109 CAP_CHANNEL1); 1110 acp_dma_cap_channel_enable(rtd->acp_mmio, 1111 CAP_CHANNEL0); 1112 } 1113 if (rtd->capture_channel == CAP_CHANNEL1) { 1114 acp_dma_cap_channel_disable(rtd->acp_mmio, 1115 CAP_CHANNEL0); 1116 acp_dma_cap_channel_enable(rtd->acp_mmio, 1117 CAP_CHANNEL1); 1118 } 1119 acp_dma_start(rtd->acp_mmio, rtd->ch1, true); 1120 } else { 1121 acp_dma_start(rtd->acp_mmio, rtd->ch1, true); 1122 acp_dma_start(rtd->acp_mmio, rtd->ch2, true); 1123 } 1124 ret = 0; 1125 break; 1126 case SNDRV_PCM_TRIGGER_STOP: 1127 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1128 case SNDRV_PCM_TRIGGER_SUSPEND: 1129 acp_dma_stop(rtd->acp_mmio, rtd->ch2); 1130 ret = acp_dma_stop(rtd->acp_mmio, rtd->ch1); 1131 break; 1132 default: 1133 ret = -EINVAL; 1134 } 1135 return ret; 1136 } 1137 1138 static int acp_dma_new(struct snd_soc_pcm_runtime *rtd) 1139 { 1140 int ret; 1141 struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, 1142 DRV_NAME); 1143 struct audio_drv_data *adata = dev_get_drvdata(component->dev); 1144 1145 switch (adata->asic_type) { 1146 case CHIP_STONEY: 1147 ret = snd_pcm_lib_preallocate_pages_for_all(rtd->pcm, 1148 SNDRV_DMA_TYPE_DEV, 1149 NULL, ST_MIN_BUFFER, 1150 ST_MAX_BUFFER); 1151 break; 1152 default: 1153 ret = snd_pcm_lib_preallocate_pages_for_all(rtd->pcm, 1154 SNDRV_DMA_TYPE_DEV, 1155 NULL, MIN_BUFFER, 1156 MAX_BUFFER); 1157 break; 1158 } 1159 if (ret < 0) 1160 dev_err(component->dev, 1161 "buffer preallocation failure error:%d\n", ret); 1162 return ret; 1163 } 1164 1165 static int acp_dma_close(struct snd_pcm_substream *substream) 1166 { 1167 u16 bank; 1168 struct snd_pcm_runtime *runtime = substream->runtime; 1169 struct audio_substream_data *rtd = runtime->private_data; 1170 struct snd_soc_pcm_runtime *prtd = substream->private_data; 1171 struct snd_soc_component *component = snd_soc_rtdcom_lookup(prtd, 1172 DRV_NAME); 1173 struct audio_drv_data *adata = dev_get_drvdata(component->dev); 1174 1175 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 1176 switch (rtd->i2s_instance) { 1177 case I2S_BT_INSTANCE: 1178 adata->play_i2sbt_stream = NULL; 1179 break; 1180 case I2S_SP_INSTANCE: 1181 default: 1182 adata->play_i2ssp_stream = NULL; 1183 /* 1184 * For Stoney, Memory gating is disabled,i.e SRAM Banks 1185 * won't be turned off. The default state for SRAM banks 1186 * is ON.Setting SRAM bank state code skipped for STONEY 1187 * platform. Added condition checks for Carrizo platform 1188 * only. 1189 */ 1190 if (adata->asic_type != CHIP_STONEY) { 1191 for (bank = 1; bank <= 4; bank++) 1192 acp_set_sram_bank_state(adata->acp_mmio, 1193 bank, false); 1194 } 1195 } 1196 } else { 1197 switch (rtd->i2s_instance) { 1198 case I2S_BT_INSTANCE: 1199 adata->capture_i2sbt_stream = NULL; 1200 break; 1201 case I2S_SP_INSTANCE: 1202 default: 1203 adata->capture_i2ssp_stream = NULL; 1204 if (adata->asic_type != CHIP_STONEY) { 1205 for (bank = 5; bank <= 8; bank++) 1206 acp_set_sram_bank_state(adata->acp_mmio, 1207 bank, false); 1208 } 1209 } 1210 } 1211 1212 /* 1213 * Disable ACP irq, when the current stream is being closed and 1214 * another stream is also not active. 1215 */ 1216 if (!adata->play_i2ssp_stream && !adata->capture_i2ssp_stream && 1217 !adata->play_i2sbt_stream && !adata->capture_i2sbt_stream) 1218 acp_reg_write(0, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB); 1219 kfree(rtd); 1220 return 0; 1221 } 1222 1223 static const struct snd_pcm_ops acp_dma_ops = { 1224 .open = acp_dma_open, 1225 .close = acp_dma_close, 1226 .ioctl = snd_pcm_lib_ioctl, 1227 .hw_params = acp_dma_hw_params, 1228 .hw_free = acp_dma_hw_free, 1229 .trigger = acp_dma_trigger, 1230 .pointer = acp_dma_pointer, 1231 .mmap = acp_dma_mmap, 1232 .prepare = acp_dma_prepare, 1233 }; 1234 1235 static const struct snd_soc_component_driver acp_asoc_platform = { 1236 .name = DRV_NAME, 1237 .ops = &acp_dma_ops, 1238 .pcm_new = acp_dma_new, 1239 }; 1240 1241 static int acp_audio_probe(struct platform_device *pdev) 1242 { 1243 int status; 1244 struct audio_drv_data *audio_drv_data; 1245 struct resource *res; 1246 const u32 *pdata = pdev->dev.platform_data; 1247 1248 if (!pdata) { 1249 dev_err(&pdev->dev, "Missing platform data\n"); 1250 return -ENODEV; 1251 } 1252 1253 audio_drv_data = devm_kzalloc(&pdev->dev, sizeof(struct audio_drv_data), 1254 GFP_KERNEL); 1255 if (!audio_drv_data) 1256 return -ENOMEM; 1257 1258 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1259 audio_drv_data->acp_mmio = devm_ioremap_resource(&pdev->dev, res); 1260 if (IS_ERR(audio_drv_data->acp_mmio)) 1261 return PTR_ERR(audio_drv_data->acp_mmio); 1262 1263 /* 1264 * The following members gets populated in device 'open' 1265 * function. Till then interrupts are disabled in 'acp_init' 1266 * and device doesn't generate any interrupts. 1267 */ 1268 1269 audio_drv_data->play_i2ssp_stream = NULL; 1270 audio_drv_data->capture_i2ssp_stream = NULL; 1271 audio_drv_data->play_i2sbt_stream = NULL; 1272 audio_drv_data->capture_i2sbt_stream = NULL; 1273 1274 audio_drv_data->asic_type = *pdata; 1275 1276 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 1277 if (!res) { 1278 dev_err(&pdev->dev, "IORESOURCE_IRQ FAILED\n"); 1279 return -ENODEV; 1280 } 1281 1282 status = devm_request_irq(&pdev->dev, res->start, dma_irq_handler, 1283 0, "ACP_IRQ", &pdev->dev); 1284 if (status) { 1285 dev_err(&pdev->dev, "ACP IRQ request failed\n"); 1286 return status; 1287 } 1288 1289 dev_set_drvdata(&pdev->dev, audio_drv_data); 1290 1291 /* Initialize the ACP */ 1292 status = acp_init(audio_drv_data->acp_mmio, audio_drv_data->asic_type); 1293 if (status) { 1294 dev_err(&pdev->dev, "ACP Init failed status:%d\n", status); 1295 return status; 1296 } 1297 1298 status = devm_snd_soc_register_component(&pdev->dev, 1299 &acp_asoc_platform, NULL, 0); 1300 if (status != 0) { 1301 dev_err(&pdev->dev, "Fail to register ALSA platform device\n"); 1302 return status; 1303 } 1304 1305 pm_runtime_set_autosuspend_delay(&pdev->dev, 10000); 1306 pm_runtime_use_autosuspend(&pdev->dev); 1307 pm_runtime_enable(&pdev->dev); 1308 1309 return status; 1310 } 1311 1312 static int acp_audio_remove(struct platform_device *pdev) 1313 { 1314 int status; 1315 struct audio_drv_data *adata = dev_get_drvdata(&pdev->dev); 1316 1317 status = acp_deinit(adata->acp_mmio); 1318 if (status) 1319 dev_err(&pdev->dev, "ACP Deinit failed status:%d\n", status); 1320 pm_runtime_disable(&pdev->dev); 1321 1322 return 0; 1323 } 1324 1325 static int acp_pcm_resume(struct device *dev) 1326 { 1327 u16 bank; 1328 int status; 1329 struct audio_substream_data *rtd; 1330 struct audio_drv_data *adata = dev_get_drvdata(dev); 1331 1332 status = acp_init(adata->acp_mmio, adata->asic_type); 1333 if (status) { 1334 dev_err(dev, "ACP Init failed status:%d\n", status); 1335 return status; 1336 } 1337 1338 if (adata->play_i2ssp_stream && adata->play_i2ssp_stream->runtime) { 1339 /* 1340 * For Stoney, Memory gating is disabled,i.e SRAM Banks 1341 * won't be turned off. The default state for SRAM banks is ON. 1342 * Setting SRAM bank state code skipped for STONEY platform. 1343 */ 1344 if (adata->asic_type != CHIP_STONEY) { 1345 for (bank = 1; bank <= 4; bank++) 1346 acp_set_sram_bank_state(adata->acp_mmio, bank, 1347 true); 1348 } 1349 rtd = adata->play_i2ssp_stream->runtime->private_data; 1350 config_acp_dma(adata->acp_mmio, rtd, adata->asic_type); 1351 } 1352 if (adata->capture_i2ssp_stream && 1353 adata->capture_i2ssp_stream->runtime) { 1354 if (adata->asic_type != CHIP_STONEY) { 1355 for (bank = 5; bank <= 8; bank++) 1356 acp_set_sram_bank_state(adata->acp_mmio, bank, 1357 true); 1358 } 1359 rtd = adata->capture_i2ssp_stream->runtime->private_data; 1360 config_acp_dma(adata->acp_mmio, rtd, adata->asic_type); 1361 } 1362 if (adata->asic_type != CHIP_CARRIZO) { 1363 if (adata->play_i2sbt_stream && 1364 adata->play_i2sbt_stream->runtime) { 1365 rtd = adata->play_i2sbt_stream->runtime->private_data; 1366 config_acp_dma(adata->acp_mmio, rtd, adata->asic_type); 1367 } 1368 if (adata->capture_i2sbt_stream && 1369 adata->capture_i2sbt_stream->runtime) { 1370 rtd = adata->capture_i2sbt_stream->runtime->private_data; 1371 config_acp_dma(adata->acp_mmio, rtd, adata->asic_type); 1372 } 1373 } 1374 acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB); 1375 return 0; 1376 } 1377 1378 static int acp_pcm_runtime_suspend(struct device *dev) 1379 { 1380 int status; 1381 struct audio_drv_data *adata = dev_get_drvdata(dev); 1382 1383 status = acp_deinit(adata->acp_mmio); 1384 if (status) 1385 dev_err(dev, "ACP Deinit failed status:%d\n", status); 1386 acp_reg_write(0, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB); 1387 return 0; 1388 } 1389 1390 static int acp_pcm_runtime_resume(struct device *dev) 1391 { 1392 int status; 1393 struct audio_drv_data *adata = dev_get_drvdata(dev); 1394 1395 status = acp_init(adata->acp_mmio, adata->asic_type); 1396 if (status) { 1397 dev_err(dev, "ACP Init failed status:%d\n", status); 1398 return status; 1399 } 1400 acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB); 1401 return 0; 1402 } 1403 1404 static const struct dev_pm_ops acp_pm_ops = { 1405 .resume = acp_pcm_resume, 1406 .runtime_suspend = acp_pcm_runtime_suspend, 1407 .runtime_resume = acp_pcm_runtime_resume, 1408 }; 1409 1410 static struct platform_driver acp_dma_driver = { 1411 .probe = acp_audio_probe, 1412 .remove = acp_audio_remove, 1413 .driver = { 1414 .name = DRV_NAME, 1415 .pm = &acp_pm_ops, 1416 }, 1417 }; 1418 1419 module_platform_driver(acp_dma_driver); 1420 1421 MODULE_AUTHOR("Vijendar.Mukunda@amd.com"); 1422 MODULE_AUTHOR("Maruthi.Bayyavarapu@amd.com"); 1423 MODULE_DESCRIPTION("AMD ACP PCM Driver"); 1424 MODULE_LICENSE("GPL v2"); 1425 MODULE_ALIAS("platform:"DRV_NAME); 1426