12025cf9eSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 27c31335aSMaruthi Srinivas Bayyavarapu /* 37c31335aSMaruthi Srinivas Bayyavarapu * AMD ALSA SoC PCM Driver for ACP 2.x 47c31335aSMaruthi Srinivas Bayyavarapu * 57c31335aSMaruthi Srinivas Bayyavarapu * Copyright 2014-2015 Advanced Micro Devices, Inc. 67c31335aSMaruthi Srinivas Bayyavarapu */ 77c31335aSMaruthi Srinivas Bayyavarapu 87c31335aSMaruthi Srinivas Bayyavarapu #include <linux/module.h> 97c31335aSMaruthi Srinivas Bayyavarapu #include <linux/delay.h> 107cb1dc81SGuenter Roeck #include <linux/io.h> 112a665dbaSAkshu Agrawal #include <linux/iopoll.h> 127c31335aSMaruthi Srinivas Bayyavarapu #include <linux/sizes.h> 131927da93SMaruthi Srinivas Bayyavarapu #include <linux/pm_runtime.h> 147c31335aSMaruthi Srinivas Bayyavarapu 157c31335aSMaruthi Srinivas Bayyavarapu #include <sound/soc.h> 16607b39efSVijendar Mukunda #include <drm/amd_asic_type.h> 177c31335aSMaruthi Srinivas Bayyavarapu #include "acp.h" 187c31335aSMaruthi Srinivas Bayyavarapu 19a1042a42SKuninori Morimoto #define DRV_NAME "acp_audio_dma" 20a1042a42SKuninori Morimoto 217c31335aSMaruthi Srinivas Bayyavarapu #define PLAYBACK_MIN_NUM_PERIODS 2 227c31335aSMaruthi Srinivas Bayyavarapu #define PLAYBACK_MAX_NUM_PERIODS 2 237c31335aSMaruthi Srinivas Bayyavarapu #define PLAYBACK_MAX_PERIOD_SIZE 16384 247c31335aSMaruthi Srinivas Bayyavarapu #define PLAYBACK_MIN_PERIOD_SIZE 1024 257c31335aSMaruthi Srinivas Bayyavarapu #define CAPTURE_MIN_NUM_PERIODS 2 267c31335aSMaruthi Srinivas Bayyavarapu #define CAPTURE_MAX_NUM_PERIODS 2 277c31335aSMaruthi Srinivas Bayyavarapu #define CAPTURE_MAX_PERIOD_SIZE 16384 287c31335aSMaruthi Srinivas Bayyavarapu #define CAPTURE_MIN_PERIOD_SIZE 1024 297c31335aSMaruthi Srinivas Bayyavarapu 307c31335aSMaruthi Srinivas Bayyavarapu #define MAX_BUFFER (PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS) 317c31335aSMaruthi Srinivas Bayyavarapu #define MIN_BUFFER MAX_BUFFER 327c31335aSMaruthi Srinivas Bayyavarapu 33ccfbb4f5SMukunda, Vijendar #define ST_PLAYBACK_MAX_PERIOD_SIZE 4096 349c7d6fabSVijendar Mukunda #define ST_CAPTURE_MAX_PERIOD_SIZE ST_PLAYBACK_MAX_PERIOD_SIZE 359c7d6fabSVijendar Mukunda #define ST_MAX_BUFFER (ST_PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS) 369c7d6fabSVijendar Mukunda #define ST_MIN_BUFFER ST_MAX_BUFFER 379c7d6fabSVijendar Mukunda 38bdd2a858SAkshu Agrawal #define DRV_NAME "acp_audio_dma" 3919843302SPierre-Louis Bossart bool acp_bt_uart_enable = true; 4019843302SPierre-Louis Bossart EXPORT_SYMBOL(acp_bt_uart_enable); 41bdd2a858SAkshu Agrawal 427c31335aSMaruthi Srinivas Bayyavarapu static const struct snd_pcm_hardware acp_pcm_hardware_playback = { 437c31335aSMaruthi Srinivas Bayyavarapu .info = SNDRV_PCM_INFO_INTERLEAVED | 447c31335aSMaruthi Srinivas Bayyavarapu SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP | 457c31335aSMaruthi Srinivas Bayyavarapu SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH | 467c31335aSMaruthi Srinivas Bayyavarapu SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME, 477c31335aSMaruthi Srinivas Bayyavarapu .formats = SNDRV_PCM_FMTBIT_S16_LE | 487c31335aSMaruthi Srinivas Bayyavarapu SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, 497c31335aSMaruthi Srinivas Bayyavarapu .channels_min = 1, 507c31335aSMaruthi Srinivas Bayyavarapu .channels_max = 8, 517c31335aSMaruthi Srinivas Bayyavarapu .rates = SNDRV_PCM_RATE_8000_96000, 527c31335aSMaruthi Srinivas Bayyavarapu .rate_min = 8000, 537c31335aSMaruthi Srinivas Bayyavarapu .rate_max = 96000, 547c31335aSMaruthi Srinivas Bayyavarapu .buffer_bytes_max = PLAYBACK_MAX_NUM_PERIODS * PLAYBACK_MAX_PERIOD_SIZE, 557c31335aSMaruthi Srinivas Bayyavarapu .period_bytes_min = PLAYBACK_MIN_PERIOD_SIZE, 567c31335aSMaruthi Srinivas Bayyavarapu .period_bytes_max = PLAYBACK_MAX_PERIOD_SIZE, 577c31335aSMaruthi Srinivas Bayyavarapu .periods_min = PLAYBACK_MIN_NUM_PERIODS, 587c31335aSMaruthi Srinivas Bayyavarapu .periods_max = PLAYBACK_MAX_NUM_PERIODS, 597c31335aSMaruthi Srinivas Bayyavarapu }; 607c31335aSMaruthi Srinivas Bayyavarapu 617c31335aSMaruthi Srinivas Bayyavarapu static const struct snd_pcm_hardware acp_pcm_hardware_capture = { 627c31335aSMaruthi Srinivas Bayyavarapu .info = SNDRV_PCM_INFO_INTERLEAVED | 637c31335aSMaruthi Srinivas Bayyavarapu SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP | 647c31335aSMaruthi Srinivas Bayyavarapu SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH | 657c31335aSMaruthi Srinivas Bayyavarapu SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME, 667c31335aSMaruthi Srinivas Bayyavarapu .formats = SNDRV_PCM_FMTBIT_S16_LE | 677c31335aSMaruthi Srinivas Bayyavarapu SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, 687c31335aSMaruthi Srinivas Bayyavarapu .channels_min = 1, 697c31335aSMaruthi Srinivas Bayyavarapu .channels_max = 2, 707c31335aSMaruthi Srinivas Bayyavarapu .rates = SNDRV_PCM_RATE_8000_48000, 717c31335aSMaruthi Srinivas Bayyavarapu .rate_min = 8000, 727c31335aSMaruthi Srinivas Bayyavarapu .rate_max = 48000, 737c31335aSMaruthi Srinivas Bayyavarapu .buffer_bytes_max = CAPTURE_MAX_NUM_PERIODS * CAPTURE_MAX_PERIOD_SIZE, 747c31335aSMaruthi Srinivas Bayyavarapu .period_bytes_min = CAPTURE_MIN_PERIOD_SIZE, 757c31335aSMaruthi Srinivas Bayyavarapu .period_bytes_max = CAPTURE_MAX_PERIOD_SIZE, 767c31335aSMaruthi Srinivas Bayyavarapu .periods_min = CAPTURE_MIN_NUM_PERIODS, 777c31335aSMaruthi Srinivas Bayyavarapu .periods_max = CAPTURE_MAX_NUM_PERIODS, 787c31335aSMaruthi Srinivas Bayyavarapu }; 797c31335aSMaruthi Srinivas Bayyavarapu 809c7d6fabSVijendar Mukunda static const struct snd_pcm_hardware acp_st_pcm_hardware_playback = { 819c7d6fabSVijendar Mukunda .info = SNDRV_PCM_INFO_INTERLEAVED | 829c7d6fabSVijendar Mukunda SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP | 839c7d6fabSVijendar Mukunda SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH | 849c7d6fabSVijendar Mukunda SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME, 859c7d6fabSVijendar Mukunda .formats = SNDRV_PCM_FMTBIT_S16_LE | 869c7d6fabSVijendar Mukunda SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, 879c7d6fabSVijendar Mukunda .channels_min = 1, 889c7d6fabSVijendar Mukunda .channels_max = 8, 899c7d6fabSVijendar Mukunda .rates = SNDRV_PCM_RATE_8000_96000, 909c7d6fabSVijendar Mukunda .rate_min = 8000, 919c7d6fabSVijendar Mukunda .rate_max = 96000, 929c7d6fabSVijendar Mukunda .buffer_bytes_max = ST_MAX_BUFFER, 939c7d6fabSVijendar Mukunda .period_bytes_min = PLAYBACK_MIN_PERIOD_SIZE, 949c7d6fabSVijendar Mukunda .period_bytes_max = ST_PLAYBACK_MAX_PERIOD_SIZE, 959c7d6fabSVijendar Mukunda .periods_min = PLAYBACK_MIN_NUM_PERIODS, 969c7d6fabSVijendar Mukunda .periods_max = PLAYBACK_MAX_NUM_PERIODS, 979c7d6fabSVijendar Mukunda }; 989c7d6fabSVijendar Mukunda 999c7d6fabSVijendar Mukunda static const struct snd_pcm_hardware acp_st_pcm_hardware_capture = { 1009c7d6fabSVijendar Mukunda .info = SNDRV_PCM_INFO_INTERLEAVED | 1019c7d6fabSVijendar Mukunda SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP | 1029c7d6fabSVijendar Mukunda SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH | 1039c7d6fabSVijendar Mukunda SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME, 1049c7d6fabSVijendar Mukunda .formats = SNDRV_PCM_FMTBIT_S16_LE | 1059c7d6fabSVijendar Mukunda SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, 1069c7d6fabSVijendar Mukunda .channels_min = 1, 1079c7d6fabSVijendar Mukunda .channels_max = 2, 1089c7d6fabSVijendar Mukunda .rates = SNDRV_PCM_RATE_8000_48000, 1099c7d6fabSVijendar Mukunda .rate_min = 8000, 1109c7d6fabSVijendar Mukunda .rate_max = 48000, 1119c7d6fabSVijendar Mukunda .buffer_bytes_max = ST_MAX_BUFFER, 1129c7d6fabSVijendar Mukunda .period_bytes_min = CAPTURE_MIN_PERIOD_SIZE, 1139c7d6fabSVijendar Mukunda .period_bytes_max = ST_CAPTURE_MAX_PERIOD_SIZE, 1149c7d6fabSVijendar Mukunda .periods_min = CAPTURE_MIN_NUM_PERIODS, 1159c7d6fabSVijendar Mukunda .periods_max = CAPTURE_MAX_NUM_PERIODS, 1169c7d6fabSVijendar Mukunda }; 1179c7d6fabSVijendar Mukunda 1187c31335aSMaruthi Srinivas Bayyavarapu static u32 acp_reg_read(void __iomem *acp_mmio, u32 reg) 1197c31335aSMaruthi Srinivas Bayyavarapu { 1207c31335aSMaruthi Srinivas Bayyavarapu return readl(acp_mmio + (reg * 4)); 1217c31335aSMaruthi Srinivas Bayyavarapu } 1227c31335aSMaruthi Srinivas Bayyavarapu 1237c31335aSMaruthi Srinivas Bayyavarapu static void acp_reg_write(u32 val, void __iomem *acp_mmio, u32 reg) 1247c31335aSMaruthi Srinivas Bayyavarapu { 1257c31335aSMaruthi Srinivas Bayyavarapu writel(val, acp_mmio + (reg * 4)); 1267c31335aSMaruthi Srinivas Bayyavarapu } 1277c31335aSMaruthi Srinivas Bayyavarapu 12813838c11SMukunda, Vijendar /* 12913838c11SMukunda, Vijendar * Configure a given dma channel parameters - enable/disable, 1307c31335aSMaruthi Srinivas Bayyavarapu * number of descriptors, priority 1317c31335aSMaruthi Srinivas Bayyavarapu */ 1327c31335aSMaruthi Srinivas Bayyavarapu static void config_acp_dma_channel(void __iomem *acp_mmio, u8 ch_num, 1337c31335aSMaruthi Srinivas Bayyavarapu u16 dscr_strt_idx, u16 num_dscrs, 1347c31335aSMaruthi Srinivas Bayyavarapu enum acp_dma_priority_level priority_level) 1357c31335aSMaruthi Srinivas Bayyavarapu { 1367c31335aSMaruthi Srinivas Bayyavarapu u32 dma_ctrl; 1377c31335aSMaruthi Srinivas Bayyavarapu 1387c31335aSMaruthi Srinivas Bayyavarapu /* disable the channel run field */ 1397c31335aSMaruthi Srinivas Bayyavarapu dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 1407c31335aSMaruthi Srinivas Bayyavarapu dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRun_MASK; 1417c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 1427c31335aSMaruthi Srinivas Bayyavarapu 1437c31335aSMaruthi Srinivas Bayyavarapu /* program a DMA channel with first descriptor to be processed. */ 1447c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write((ACP_DMA_DSCR_STRT_IDX_0__DMAChDscrStrtIdx_MASK 1457c31335aSMaruthi Srinivas Bayyavarapu & dscr_strt_idx), 1467c31335aSMaruthi Srinivas Bayyavarapu acp_mmio, mmACP_DMA_DSCR_STRT_IDX_0 + ch_num); 1477c31335aSMaruthi Srinivas Bayyavarapu 14813838c11SMukunda, Vijendar /* 14913838c11SMukunda, Vijendar * program a DMA channel with the number of descriptors to be 1507c31335aSMaruthi Srinivas Bayyavarapu * processed in the transfer 1517c31335aSMaruthi Srinivas Bayyavarapu */ 1527c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(ACP_DMA_DSCR_CNT_0__DMAChDscrCnt_MASK & num_dscrs, 1537c31335aSMaruthi Srinivas Bayyavarapu acp_mmio, mmACP_DMA_DSCR_CNT_0 + ch_num); 1547c31335aSMaruthi Srinivas Bayyavarapu 1557c31335aSMaruthi Srinivas Bayyavarapu /* set DMA channel priority */ 1567c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(priority_level, acp_mmio, mmACP_DMA_PRIO_0 + ch_num); 1577c31335aSMaruthi Srinivas Bayyavarapu } 1587c31335aSMaruthi Srinivas Bayyavarapu 159f7c4fe9cSGu Shengxian /* Initialize a dma descriptor in SRAM based on descriptor information passed */ 1607c31335aSMaruthi Srinivas Bayyavarapu static void config_dma_descriptor_in_sram(void __iomem *acp_mmio, 1617c31335aSMaruthi Srinivas Bayyavarapu u16 descr_idx, 1627c31335aSMaruthi Srinivas Bayyavarapu acp_dma_dscr_transfer_t *descr_info) 1637c31335aSMaruthi Srinivas Bayyavarapu { 1647c31335aSMaruthi Srinivas Bayyavarapu u32 sram_offset; 1657c31335aSMaruthi Srinivas Bayyavarapu 1667c31335aSMaruthi Srinivas Bayyavarapu sram_offset = (descr_idx * sizeof(acp_dma_dscr_transfer_t)); 1677c31335aSMaruthi Srinivas Bayyavarapu 1687c31335aSMaruthi Srinivas Bayyavarapu /* program the source base address. */ 1697c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(sram_offset, acp_mmio, mmACP_SRBM_Targ_Idx_Addr); 1707c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(descr_info->src, acp_mmio, mmACP_SRBM_Targ_Idx_Data); 1717c31335aSMaruthi Srinivas Bayyavarapu /* program the destination base address. */ 1727c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(sram_offset + 4, acp_mmio, mmACP_SRBM_Targ_Idx_Addr); 1737c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(descr_info->dest, acp_mmio, mmACP_SRBM_Targ_Idx_Data); 1747c31335aSMaruthi Srinivas Bayyavarapu 1757c31335aSMaruthi Srinivas Bayyavarapu /* program the number of bytes to be transferred for this descriptor. */ 1767c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(sram_offset + 8, acp_mmio, mmACP_SRBM_Targ_Idx_Addr); 1777c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(descr_info->xfer_val, acp_mmio, mmACP_SRBM_Targ_Idx_Data); 1787c31335aSMaruthi Srinivas Bayyavarapu } 1797c31335aSMaruthi Srinivas Bayyavarapu 1802a665dbaSAkshu Agrawal static void pre_config_reset(void __iomem *acp_mmio, u16 ch_num) 1812a665dbaSAkshu Agrawal { 1822a665dbaSAkshu Agrawal u32 dma_ctrl; 1832a665dbaSAkshu Agrawal int ret; 1842a665dbaSAkshu Agrawal 1852a665dbaSAkshu Agrawal /* clear the reset bit */ 1862a665dbaSAkshu Agrawal dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 1872a665dbaSAkshu Agrawal dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRst_MASK; 1882a665dbaSAkshu Agrawal acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 1892a665dbaSAkshu Agrawal /* check the reset bit before programming configuration registers */ 1902a665dbaSAkshu Agrawal ret = readl_poll_timeout(acp_mmio + ((mmACP_DMA_CNTL_0 + ch_num) * 4), 1912a665dbaSAkshu Agrawal dma_ctrl, 1922a665dbaSAkshu Agrawal !(dma_ctrl & ACP_DMA_CNTL_0__DMAChRst_MASK), 1932a665dbaSAkshu Agrawal 100, ACP_DMA_RESET_TIME); 1942a665dbaSAkshu Agrawal if (ret < 0) 1952a665dbaSAkshu Agrawal pr_err("Failed to clear reset of channel : %d\n", ch_num); 1962a665dbaSAkshu Agrawal } 1972a665dbaSAkshu Agrawal 19813838c11SMukunda, Vijendar /* 19913838c11SMukunda, Vijendar * Initialize the DMA descriptor information for transfer between 2007c31335aSMaruthi Srinivas Bayyavarapu * system memory <-> ACP SRAM 2017c31335aSMaruthi Srinivas Bayyavarapu */ 2027c31335aSMaruthi Srinivas Bayyavarapu static void set_acp_sysmem_dma_descriptors(void __iomem *acp_mmio, 20313838c11SMukunda, Vijendar u32 size, int direction, 20413838c11SMukunda, Vijendar u32 pte_offset, u16 ch, 20513838c11SMukunda, Vijendar u32 sram_bank, u16 dma_dscr_idx, 20613838c11SMukunda, Vijendar u32 asic_type) 2077c31335aSMaruthi Srinivas Bayyavarapu { 2087c31335aSMaruthi Srinivas Bayyavarapu u16 i; 2097c31335aSMaruthi Srinivas Bayyavarapu acp_dma_dscr_transfer_t dmadscr[NUM_DSCRS_PER_CHANNEL]; 2107c31335aSMaruthi Srinivas Bayyavarapu 2117c31335aSMaruthi Srinivas Bayyavarapu for (i = 0; i < NUM_DSCRS_PER_CHANNEL; i++) { 2127c31335aSMaruthi Srinivas Bayyavarapu dmadscr[i].xfer_val = 0; 2137c31335aSMaruthi Srinivas Bayyavarapu if (direction == SNDRV_PCM_STREAM_PLAYBACK) { 2144376a86cSMukunda, Vijendar dma_dscr_idx = dma_dscr_idx + i; 2154376a86cSMukunda, Vijendar dmadscr[i].dest = sram_bank + (i * (size / 2)); 2167c31335aSMaruthi Srinivas Bayyavarapu dmadscr[i].src = ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS 2177c31335aSMaruthi Srinivas Bayyavarapu + (pte_offset * SZ_4K) + (i * (size / 2)); 218aac89748SVijendar Mukunda switch (asic_type) { 219aac89748SVijendar Mukunda case CHIP_STONEY: 220aac89748SVijendar Mukunda dmadscr[i].xfer_val |= 22113838c11SMukunda, Vijendar (ACP_DMA_ATTR_DAGB_GARLIC_TO_SHAREDMEM << 16) | 222aac89748SVijendar Mukunda (size / 2); 223aac89748SVijendar Mukunda break; 224aac89748SVijendar Mukunda default: 2257c31335aSMaruthi Srinivas Bayyavarapu dmadscr[i].xfer_val |= 22613838c11SMukunda, Vijendar (ACP_DMA_ATTR_DAGB_ONION_TO_SHAREDMEM << 16) | 2277c31335aSMaruthi Srinivas Bayyavarapu (size / 2); 228aac89748SVijendar Mukunda } 2297c31335aSMaruthi Srinivas Bayyavarapu } else { 2304376a86cSMukunda, Vijendar dma_dscr_idx = dma_dscr_idx + i; 2314376a86cSMukunda, Vijendar dmadscr[i].src = sram_bank + (i * (size / 2)); 232aac89748SVijendar Mukunda dmadscr[i].dest = 233aac89748SVijendar Mukunda ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS + 234aac89748SVijendar Mukunda (pte_offset * SZ_4K) + (i * (size / 2)); 2354376a86cSMukunda, Vijendar switch (asic_type) { 2364376a86cSMukunda, Vijendar case CHIP_STONEY: 237aac89748SVijendar Mukunda dmadscr[i].xfer_val |= 23813838c11SMukunda, Vijendar (ACP_DMA_ATTR_SHARED_MEM_TO_DAGB_GARLIC << 16) | 239aac89748SVijendar Mukunda (size / 2); 240aac89748SVijendar Mukunda break; 241aac89748SVijendar Mukunda default: 2427c31335aSMaruthi Srinivas Bayyavarapu dmadscr[i].xfer_val |= 24313838c11SMukunda, Vijendar (ACP_DMA_ATTR_SHAREDMEM_TO_DAGB_ONION << 16) | 2447c31335aSMaruthi Srinivas Bayyavarapu (size / 2); 2457c31335aSMaruthi Srinivas Bayyavarapu } 246aac89748SVijendar Mukunda } 2477c31335aSMaruthi Srinivas Bayyavarapu config_dma_descriptor_in_sram(acp_mmio, dma_dscr_idx, 2487c31335aSMaruthi Srinivas Bayyavarapu &dmadscr[i]); 2497c31335aSMaruthi Srinivas Bayyavarapu } 2502a665dbaSAkshu Agrawal pre_config_reset(acp_mmio, ch); 2514376a86cSMukunda, Vijendar config_acp_dma_channel(acp_mmio, ch, 2524376a86cSMukunda, Vijendar dma_dscr_idx - 1, 2537c31335aSMaruthi Srinivas Bayyavarapu NUM_DSCRS_PER_CHANNEL, 2547c31335aSMaruthi Srinivas Bayyavarapu ACP_DMA_PRIORITY_LEVEL_NORMAL); 2557c31335aSMaruthi Srinivas Bayyavarapu } 2567c31335aSMaruthi Srinivas Bayyavarapu 25713838c11SMukunda, Vijendar /* 25813838c11SMukunda, Vijendar * Initialize the DMA descriptor information for transfer between 2597c31335aSMaruthi Srinivas Bayyavarapu * ACP SRAM <-> I2S 2607c31335aSMaruthi Srinivas Bayyavarapu */ 2614376a86cSMukunda, Vijendar static void set_acp_to_i2s_dma_descriptors(void __iomem *acp_mmio, u32 size, 2624376a86cSMukunda, Vijendar int direction, u32 sram_bank, 2634376a86cSMukunda, Vijendar u16 destination, u16 ch, 2644376a86cSMukunda, Vijendar u16 dma_dscr_idx, u32 asic_type) 2657c31335aSMaruthi Srinivas Bayyavarapu { 2667c31335aSMaruthi Srinivas Bayyavarapu u16 i; 2677c31335aSMaruthi Srinivas Bayyavarapu acp_dma_dscr_transfer_t dmadscr[NUM_DSCRS_PER_CHANNEL]; 2687c31335aSMaruthi Srinivas Bayyavarapu 2697c31335aSMaruthi Srinivas Bayyavarapu for (i = 0; i < NUM_DSCRS_PER_CHANNEL; i++) { 2707c31335aSMaruthi Srinivas Bayyavarapu dmadscr[i].xfer_val = 0; 2717c31335aSMaruthi Srinivas Bayyavarapu if (direction == SNDRV_PCM_STREAM_PLAYBACK) { 2724376a86cSMukunda, Vijendar dma_dscr_idx = dma_dscr_idx + i; 2734376a86cSMukunda, Vijendar dmadscr[i].src = sram_bank + (i * (size / 2)); 2747c31335aSMaruthi Srinivas Bayyavarapu /* dmadscr[i].dest is unused by hardware. */ 2757c31335aSMaruthi Srinivas Bayyavarapu dmadscr[i].dest = 0; 2764376a86cSMukunda, Vijendar dmadscr[i].xfer_val |= BIT(22) | (destination << 16) | 2777c31335aSMaruthi Srinivas Bayyavarapu (size / 2); 2787c31335aSMaruthi Srinivas Bayyavarapu } else { 2794376a86cSMukunda, Vijendar dma_dscr_idx = dma_dscr_idx + i; 2807c31335aSMaruthi Srinivas Bayyavarapu /* dmadscr[i].src is unused by hardware. */ 2817c31335aSMaruthi Srinivas Bayyavarapu dmadscr[i].src = 0; 282aac89748SVijendar Mukunda dmadscr[i].dest = 2834376a86cSMukunda, Vijendar sram_bank + (i * (size / 2)); 2847c31335aSMaruthi Srinivas Bayyavarapu dmadscr[i].xfer_val |= BIT(22) | 2854376a86cSMukunda, Vijendar (destination << 16) | (size / 2); 2867c31335aSMaruthi Srinivas Bayyavarapu } 2877c31335aSMaruthi Srinivas Bayyavarapu config_dma_descriptor_in_sram(acp_mmio, dma_dscr_idx, 2887c31335aSMaruthi Srinivas Bayyavarapu &dmadscr[i]); 2897c31335aSMaruthi Srinivas Bayyavarapu } 2902a665dbaSAkshu Agrawal pre_config_reset(acp_mmio, ch); 291f7c4fe9cSGu Shengxian /* Configure the DMA channel with the above descriptor */ 2924376a86cSMukunda, Vijendar config_acp_dma_channel(acp_mmio, ch, dma_dscr_idx - 1, 2937c31335aSMaruthi Srinivas Bayyavarapu NUM_DSCRS_PER_CHANNEL, 2947c31335aSMaruthi Srinivas Bayyavarapu ACP_DMA_PRIORITY_LEVEL_NORMAL); 2957c31335aSMaruthi Srinivas Bayyavarapu } 2967c31335aSMaruthi Srinivas Bayyavarapu 2977c31335aSMaruthi Srinivas Bayyavarapu /* Create page table entries in ACP SRAM for the allocated memory */ 298d6d08273SYu Zhao static void acp_pte_config(void __iomem *acp_mmio, dma_addr_t addr, 2997c31335aSMaruthi Srinivas Bayyavarapu u16 num_of_pages, u32 pte_offset) 3007c31335aSMaruthi Srinivas Bayyavarapu { 3017c31335aSMaruthi Srinivas Bayyavarapu u16 page_idx; 3027c31335aSMaruthi Srinivas Bayyavarapu u32 low; 3037c31335aSMaruthi Srinivas Bayyavarapu u32 high; 3047c31335aSMaruthi Srinivas Bayyavarapu u32 offset; 3057c31335aSMaruthi Srinivas Bayyavarapu 3067c31335aSMaruthi Srinivas Bayyavarapu offset = ACP_DAGB_GRP_SRBM_SRAM_BASE_OFFSET + (pte_offset * 8); 3077c31335aSMaruthi Srinivas Bayyavarapu for (page_idx = 0; page_idx < (num_of_pages); page_idx++) { 3087c31335aSMaruthi Srinivas Bayyavarapu /* Load the low address of page int ACP SRAM through SRBM */ 3097c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write((offset + (page_idx * 8)), 3107c31335aSMaruthi Srinivas Bayyavarapu acp_mmio, mmACP_SRBM_Targ_Idx_Addr); 3117c31335aSMaruthi Srinivas Bayyavarapu 3127c31335aSMaruthi Srinivas Bayyavarapu low = lower_32_bits(addr); 3137c31335aSMaruthi Srinivas Bayyavarapu high = upper_32_bits(addr); 3147c31335aSMaruthi Srinivas Bayyavarapu 3157c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(low, acp_mmio, mmACP_SRBM_Targ_Idx_Data); 3167c31335aSMaruthi Srinivas Bayyavarapu 3177c31335aSMaruthi Srinivas Bayyavarapu /* Load the High address of page int ACP SRAM through SRBM */ 3187c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write((offset + (page_idx * 8) + 4), 3197c31335aSMaruthi Srinivas Bayyavarapu acp_mmio, mmACP_SRBM_Targ_Idx_Addr); 3207c31335aSMaruthi Srinivas Bayyavarapu 3217c31335aSMaruthi Srinivas Bayyavarapu /* page enable in ACP */ 3227c31335aSMaruthi Srinivas Bayyavarapu high |= BIT(31); 3237c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(high, acp_mmio, mmACP_SRBM_Targ_Idx_Data); 3247c31335aSMaruthi Srinivas Bayyavarapu 325f7c4fe9cSGu Shengxian /* Move to next physically contiguous page */ 326d6d08273SYu Zhao addr += PAGE_SIZE; 3277c31335aSMaruthi Srinivas Bayyavarapu } 3287c31335aSMaruthi Srinivas Bayyavarapu } 3297c31335aSMaruthi Srinivas Bayyavarapu 3307c31335aSMaruthi Srinivas Bayyavarapu static void config_acp_dma(void __iomem *acp_mmio, 3318349b7f5SMukunda, Vijendar struct audio_substream_data *rtd, 332aac89748SVijendar Mukunda u32 asic_type) 3337c31335aSMaruthi Srinivas Bayyavarapu { 334fa9d2f17SAgrawal, Akshu u16 ch_acp_sysmem, ch_acp_i2s; 335fa9d2f17SAgrawal, Akshu 336d6d08273SYu Zhao acp_pte_config(acp_mmio, rtd->dma_addr, rtd->num_of_pages, 337e188c525SMukunda, Vijendar rtd->pte_offset); 338fa9d2f17SAgrawal, Akshu 339fa9d2f17SAgrawal, Akshu if (rtd->direction == SNDRV_PCM_STREAM_PLAYBACK) { 340fa9d2f17SAgrawal, Akshu ch_acp_sysmem = rtd->ch1; 341fa9d2f17SAgrawal, Akshu ch_acp_i2s = rtd->ch2; 342fa9d2f17SAgrawal, Akshu } else { 343fa9d2f17SAgrawal, Akshu ch_acp_i2s = rtd->ch1; 344fa9d2f17SAgrawal, Akshu ch_acp_sysmem = rtd->ch2; 345fa9d2f17SAgrawal, Akshu } 3467c31335aSMaruthi Srinivas Bayyavarapu /* Configure System memory <-> ACP SRAM DMA descriptors */ 3478349b7f5SMukunda, Vijendar set_acp_sysmem_dma_descriptors(acp_mmio, rtd->size, 348e188c525SMukunda, Vijendar rtd->direction, rtd->pte_offset, 349fa9d2f17SAgrawal, Akshu ch_acp_sysmem, rtd->sram_bank, 3508769bb55SVijendar Mukunda rtd->dma_dscr_idx_1, asic_type); 3517c31335aSMaruthi Srinivas Bayyavarapu /* Configure ACP SRAM <-> I2S DMA descriptors */ 3528349b7f5SMukunda, Vijendar set_acp_to_i2s_dma_descriptors(acp_mmio, rtd->size, 35318e8a40dSMukunda, Vijendar rtd->direction, rtd->sram_bank, 354fa9d2f17SAgrawal, Akshu rtd->destination, ch_acp_i2s, 3558769bb55SVijendar Mukunda rtd->dma_dscr_idx_2, asic_type); 3567c31335aSMaruthi Srinivas Bayyavarapu } 3577c31335aSMaruthi Srinivas Bayyavarapu 3582718c89aSAkshu Agrawal static void acp_dma_cap_channel_enable(void __iomem *acp_mmio, 3592718c89aSAkshu Agrawal u16 cap_channel) 3602718c89aSAkshu Agrawal { 3612718c89aSAkshu Agrawal u32 val, ch_reg, imr_reg, res_reg; 3622718c89aSAkshu Agrawal 3632718c89aSAkshu Agrawal switch (cap_channel) { 3642718c89aSAkshu Agrawal case CAP_CHANNEL1: 3652718c89aSAkshu Agrawal ch_reg = mmACP_I2SMICSP_RER1; 3662718c89aSAkshu Agrawal res_reg = mmACP_I2SMICSP_RCR1; 3672718c89aSAkshu Agrawal imr_reg = mmACP_I2SMICSP_IMR1; 3682718c89aSAkshu Agrawal break; 3692718c89aSAkshu Agrawal case CAP_CHANNEL0: 3702718c89aSAkshu Agrawal default: 3712718c89aSAkshu Agrawal ch_reg = mmACP_I2SMICSP_RER0; 3722718c89aSAkshu Agrawal res_reg = mmACP_I2SMICSP_RCR0; 3732718c89aSAkshu Agrawal imr_reg = mmACP_I2SMICSP_IMR0; 3742718c89aSAkshu Agrawal break; 3752718c89aSAkshu Agrawal } 3762718c89aSAkshu Agrawal val = acp_reg_read(acp_mmio, 3772718c89aSAkshu Agrawal mmACP_I2S_16BIT_RESOLUTION_EN); 3782718c89aSAkshu Agrawal if (val & ACP_I2S_MIC_16BIT_RESOLUTION_EN) { 3792718c89aSAkshu Agrawal acp_reg_write(0x0, acp_mmio, ch_reg); 3802718c89aSAkshu Agrawal /* Set 16bit resolution on capture */ 3812718c89aSAkshu Agrawal acp_reg_write(0x2, acp_mmio, res_reg); 3822718c89aSAkshu Agrawal } 3832718c89aSAkshu Agrawal val = acp_reg_read(acp_mmio, imr_reg); 3842718c89aSAkshu Agrawal val &= ~ACP_I2SMICSP_IMR1__I2SMICSP_RXDAM_MASK; 3852718c89aSAkshu Agrawal val &= ~ACP_I2SMICSP_IMR1__I2SMICSP_RXFOM_MASK; 3862718c89aSAkshu Agrawal acp_reg_write(val, acp_mmio, imr_reg); 3872718c89aSAkshu Agrawal acp_reg_write(0x1, acp_mmio, ch_reg); 3882718c89aSAkshu Agrawal } 3892718c89aSAkshu Agrawal 3902718c89aSAkshu Agrawal static void acp_dma_cap_channel_disable(void __iomem *acp_mmio, 3912718c89aSAkshu Agrawal u16 cap_channel) 3922718c89aSAkshu Agrawal { 3932718c89aSAkshu Agrawal u32 val, ch_reg, imr_reg; 3942718c89aSAkshu Agrawal 3952718c89aSAkshu Agrawal switch (cap_channel) { 3962718c89aSAkshu Agrawal case CAP_CHANNEL1: 3972718c89aSAkshu Agrawal imr_reg = mmACP_I2SMICSP_IMR1; 3982718c89aSAkshu Agrawal ch_reg = mmACP_I2SMICSP_RER1; 3992718c89aSAkshu Agrawal break; 4002718c89aSAkshu Agrawal case CAP_CHANNEL0: 4012718c89aSAkshu Agrawal default: 4022718c89aSAkshu Agrawal imr_reg = mmACP_I2SMICSP_IMR0; 4032718c89aSAkshu Agrawal ch_reg = mmACP_I2SMICSP_RER0; 4042718c89aSAkshu Agrawal break; 4052718c89aSAkshu Agrawal } 4062718c89aSAkshu Agrawal val = acp_reg_read(acp_mmio, imr_reg); 4072718c89aSAkshu Agrawal val |= ACP_I2SMICSP_IMR1__I2SMICSP_RXDAM_MASK; 4082718c89aSAkshu Agrawal val |= ACP_I2SMICSP_IMR1__I2SMICSP_RXFOM_MASK; 4092718c89aSAkshu Agrawal acp_reg_write(val, acp_mmio, imr_reg); 4102718c89aSAkshu Agrawal acp_reg_write(0x0, acp_mmio, ch_reg); 4112718c89aSAkshu Agrawal } 4122718c89aSAkshu Agrawal 4137c31335aSMaruthi Srinivas Bayyavarapu /* Start a given DMA channel transfer */ 414bbdb7012SAkshu Agrawal static void acp_dma_start(void __iomem *acp_mmio, u16 ch_num, bool is_circular) 4157c31335aSMaruthi Srinivas Bayyavarapu { 4167c31335aSMaruthi Srinivas Bayyavarapu u32 dma_ctrl; 4177c31335aSMaruthi Srinivas Bayyavarapu 4187c31335aSMaruthi Srinivas Bayyavarapu /* read the dma control register and disable the channel run field */ 4197c31335aSMaruthi Srinivas Bayyavarapu dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 4207c31335aSMaruthi Srinivas Bayyavarapu 4217c31335aSMaruthi Srinivas Bayyavarapu /* Invalidating the DAGB cache */ 4227c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(1, acp_mmio, mmACP_DAGB_ATU_CTRL); 4237c31335aSMaruthi Srinivas Bayyavarapu 42413838c11SMukunda, Vijendar /* 42513838c11SMukunda, Vijendar * configure the DMA channel and start the DMA transfer 4267c31335aSMaruthi Srinivas Bayyavarapu * set dmachrun bit to start the transfer and enable the 4277c31335aSMaruthi Srinivas Bayyavarapu * interrupt on completion of the dma transfer 4287c31335aSMaruthi Srinivas Bayyavarapu */ 4297c31335aSMaruthi Srinivas Bayyavarapu dma_ctrl |= ACP_DMA_CNTL_0__DMAChRun_MASK; 4307c31335aSMaruthi Srinivas Bayyavarapu 4317c31335aSMaruthi Srinivas Bayyavarapu switch (ch_num) { 4327c31335aSMaruthi Srinivas Bayyavarapu case ACP_TO_I2S_DMA_CH_NUM: 43319e023e3SAgrawal, Akshu case I2S_TO_ACP_DMA_CH_NUM: 434ccfbb4f5SMukunda, Vijendar case ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM: 43519e023e3SAgrawal, Akshu case I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM: 4367c31335aSMaruthi Srinivas Bayyavarapu dma_ctrl |= ACP_DMA_CNTL_0__DMAChIOCEn_MASK; 4377c31335aSMaruthi Srinivas Bayyavarapu break; 4387c31335aSMaruthi Srinivas Bayyavarapu default: 4397c31335aSMaruthi Srinivas Bayyavarapu dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChIOCEn_MASK; 4407c31335aSMaruthi Srinivas Bayyavarapu break; 4417c31335aSMaruthi Srinivas Bayyavarapu } 4427c31335aSMaruthi Srinivas Bayyavarapu 443bbdb7012SAkshu Agrawal /* enable for ACP to SRAM DMA channel */ 444bbdb7012SAkshu Agrawal if (is_circular == true) 4457c31335aSMaruthi Srinivas Bayyavarapu dma_ctrl |= ACP_DMA_CNTL_0__Circular_DMA_En_MASK; 446bbdb7012SAkshu Agrawal else 447bbdb7012SAkshu Agrawal dma_ctrl &= ~ACP_DMA_CNTL_0__Circular_DMA_En_MASK; 4487c31335aSMaruthi Srinivas Bayyavarapu 4497c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 4507c31335aSMaruthi Srinivas Bayyavarapu } 4517c31335aSMaruthi Srinivas Bayyavarapu 4527c31335aSMaruthi Srinivas Bayyavarapu /* Stop a given DMA channel transfer */ 4537c31335aSMaruthi Srinivas Bayyavarapu static int acp_dma_stop(void __iomem *acp_mmio, u8 ch_num) 4547c31335aSMaruthi Srinivas Bayyavarapu { 4557c31335aSMaruthi Srinivas Bayyavarapu u32 dma_ctrl; 4567c31335aSMaruthi Srinivas Bayyavarapu u32 dma_ch_sts; 4577c31335aSMaruthi Srinivas Bayyavarapu u32 count = ACP_DMA_RESET_TIME; 4587c31335aSMaruthi Srinivas Bayyavarapu 4597c31335aSMaruthi Srinivas Bayyavarapu dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 4607c31335aSMaruthi Srinivas Bayyavarapu 46113838c11SMukunda, Vijendar /* 46213838c11SMukunda, Vijendar * clear the dma control register fields before writing zero 4637c31335aSMaruthi Srinivas Bayyavarapu * in reset bit 4647c31335aSMaruthi Srinivas Bayyavarapu */ 4657c31335aSMaruthi Srinivas Bayyavarapu dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRun_MASK; 4667c31335aSMaruthi Srinivas Bayyavarapu dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChIOCEn_MASK; 4677c31335aSMaruthi Srinivas Bayyavarapu 4687c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 4697c31335aSMaruthi Srinivas Bayyavarapu dma_ch_sts = acp_reg_read(acp_mmio, mmACP_DMA_CH_STS); 4707c31335aSMaruthi Srinivas Bayyavarapu 4717c31335aSMaruthi Srinivas Bayyavarapu if (dma_ch_sts & BIT(ch_num)) { 47213838c11SMukunda, Vijendar /* 47313838c11SMukunda, Vijendar * set the reset bit for this channel to stop the dma 4747c31335aSMaruthi Srinivas Bayyavarapu * transfer 4757c31335aSMaruthi Srinivas Bayyavarapu */ 4767c31335aSMaruthi Srinivas Bayyavarapu dma_ctrl |= ACP_DMA_CNTL_0__DMAChRst_MASK; 4777c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 4787c31335aSMaruthi Srinivas Bayyavarapu } 4797c31335aSMaruthi Srinivas Bayyavarapu 4807c31335aSMaruthi Srinivas Bayyavarapu /* check the channel status bit for some time and return the status */ 4817c31335aSMaruthi Srinivas Bayyavarapu while (true) { 4827c31335aSMaruthi Srinivas Bayyavarapu dma_ch_sts = acp_reg_read(acp_mmio, mmACP_DMA_CH_STS); 4837c31335aSMaruthi Srinivas Bayyavarapu if (!(dma_ch_sts & BIT(ch_num))) { 48413838c11SMukunda, Vijendar /* 48513838c11SMukunda, Vijendar * clear the reset flag after successfully stopping 4867c31335aSMaruthi Srinivas Bayyavarapu * the dma transfer and break from the loop 4877c31335aSMaruthi Srinivas Bayyavarapu */ 4887c31335aSMaruthi Srinivas Bayyavarapu dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRst_MASK; 4897c31335aSMaruthi Srinivas Bayyavarapu 4907c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 4917c31335aSMaruthi Srinivas Bayyavarapu + ch_num); 4927c31335aSMaruthi Srinivas Bayyavarapu break; 4937c31335aSMaruthi Srinivas Bayyavarapu } 4947c31335aSMaruthi Srinivas Bayyavarapu if (--count == 0) { 4957c31335aSMaruthi Srinivas Bayyavarapu pr_err("Failed to stop ACP DMA channel : %d\n", ch_num); 4967c31335aSMaruthi Srinivas Bayyavarapu return -ETIMEDOUT; 4977c31335aSMaruthi Srinivas Bayyavarapu } 4987c31335aSMaruthi Srinivas Bayyavarapu udelay(100); 4997c31335aSMaruthi Srinivas Bayyavarapu } 5007c31335aSMaruthi Srinivas Bayyavarapu return 0; 5017c31335aSMaruthi Srinivas Bayyavarapu } 5027c31335aSMaruthi Srinivas Bayyavarapu 503c36d9b3fSMaruthi Srinivas Bayyavarapu static void acp_set_sram_bank_state(void __iomem *acp_mmio, u16 bank, 504c36d9b3fSMaruthi Srinivas Bayyavarapu bool power_on) 505c36d9b3fSMaruthi Srinivas Bayyavarapu { 506c36d9b3fSMaruthi Srinivas Bayyavarapu u32 val, req_reg, sts_reg, sts_reg_mask; 507c36d9b3fSMaruthi Srinivas Bayyavarapu u32 loops = 1000; 508c36d9b3fSMaruthi Srinivas Bayyavarapu 509c36d9b3fSMaruthi Srinivas Bayyavarapu if (bank < 32) { 510c36d9b3fSMaruthi Srinivas Bayyavarapu req_reg = mmACP_MEM_SHUT_DOWN_REQ_LO; 511c36d9b3fSMaruthi Srinivas Bayyavarapu sts_reg = mmACP_MEM_SHUT_DOWN_STS_LO; 512c36d9b3fSMaruthi Srinivas Bayyavarapu sts_reg_mask = 0xFFFFFFFF; 513c36d9b3fSMaruthi Srinivas Bayyavarapu 514c36d9b3fSMaruthi Srinivas Bayyavarapu } else { 515c36d9b3fSMaruthi Srinivas Bayyavarapu bank -= 32; 516c36d9b3fSMaruthi Srinivas Bayyavarapu req_reg = mmACP_MEM_SHUT_DOWN_REQ_HI; 517c36d9b3fSMaruthi Srinivas Bayyavarapu sts_reg = mmACP_MEM_SHUT_DOWN_STS_HI; 518c36d9b3fSMaruthi Srinivas Bayyavarapu sts_reg_mask = 0x0000FFFF; 519c36d9b3fSMaruthi Srinivas Bayyavarapu } 520c36d9b3fSMaruthi Srinivas Bayyavarapu 521c36d9b3fSMaruthi Srinivas Bayyavarapu val = acp_reg_read(acp_mmio, req_reg); 522c36d9b3fSMaruthi Srinivas Bayyavarapu if (val & (1 << bank)) { 523c36d9b3fSMaruthi Srinivas Bayyavarapu /* bank is in off state */ 524c36d9b3fSMaruthi Srinivas Bayyavarapu if (power_on == true) 525c36d9b3fSMaruthi Srinivas Bayyavarapu /* request to on */ 526c36d9b3fSMaruthi Srinivas Bayyavarapu val &= ~(1 << bank); 527c36d9b3fSMaruthi Srinivas Bayyavarapu else 528c36d9b3fSMaruthi Srinivas Bayyavarapu /* request to off */ 529c36d9b3fSMaruthi Srinivas Bayyavarapu return; 530c36d9b3fSMaruthi Srinivas Bayyavarapu } else { 531c36d9b3fSMaruthi Srinivas Bayyavarapu /* bank is in on state */ 532c36d9b3fSMaruthi Srinivas Bayyavarapu if (power_on == false) 533c36d9b3fSMaruthi Srinivas Bayyavarapu /* request to off */ 534c36d9b3fSMaruthi Srinivas Bayyavarapu val |= 1 << bank; 535c36d9b3fSMaruthi Srinivas Bayyavarapu else 536c36d9b3fSMaruthi Srinivas Bayyavarapu /* request to on */ 537c36d9b3fSMaruthi Srinivas Bayyavarapu return; 538c36d9b3fSMaruthi Srinivas Bayyavarapu } 539c36d9b3fSMaruthi Srinivas Bayyavarapu acp_reg_write(val, acp_mmio, req_reg); 540c36d9b3fSMaruthi Srinivas Bayyavarapu 541c36d9b3fSMaruthi Srinivas Bayyavarapu while (acp_reg_read(acp_mmio, sts_reg) != sts_reg_mask) { 542c36d9b3fSMaruthi Srinivas Bayyavarapu if (!loops--) { 543c36d9b3fSMaruthi Srinivas Bayyavarapu pr_err("ACP SRAM bank %d state change failed\n", bank); 544c36d9b3fSMaruthi Srinivas Bayyavarapu break; 545c36d9b3fSMaruthi Srinivas Bayyavarapu } 546c36d9b3fSMaruthi Srinivas Bayyavarapu cpu_relax(); 547c36d9b3fSMaruthi Srinivas Bayyavarapu } 548c36d9b3fSMaruthi Srinivas Bayyavarapu } 549c36d9b3fSMaruthi Srinivas Bayyavarapu 5507c31335aSMaruthi Srinivas Bayyavarapu /* Initialize and bring ACP hardware to default state. */ 551607b39efSVijendar Mukunda static int acp_init(void __iomem *acp_mmio, u32 asic_type) 5527c31335aSMaruthi Srinivas Bayyavarapu { 553c36d9b3fSMaruthi Srinivas Bayyavarapu u16 bank; 5547c31335aSMaruthi Srinivas Bayyavarapu u32 val, count, sram_pte_offset; 5557c31335aSMaruthi Srinivas Bayyavarapu 5567c31335aSMaruthi Srinivas Bayyavarapu /* Assert Soft reset of ACP */ 5577c31335aSMaruthi Srinivas Bayyavarapu val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET); 5587c31335aSMaruthi Srinivas Bayyavarapu 5597c31335aSMaruthi Srinivas Bayyavarapu val |= ACP_SOFT_RESET__SoftResetAud_MASK; 5607c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET); 5617c31335aSMaruthi Srinivas Bayyavarapu 5627c31335aSMaruthi Srinivas Bayyavarapu count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE; 5637c31335aSMaruthi Srinivas Bayyavarapu while (true) { 5647c31335aSMaruthi Srinivas Bayyavarapu val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET); 5657c31335aSMaruthi Srinivas Bayyavarapu if (ACP_SOFT_RESET__SoftResetAudDone_MASK == 5667c31335aSMaruthi Srinivas Bayyavarapu (val & ACP_SOFT_RESET__SoftResetAudDone_MASK)) 5677c31335aSMaruthi Srinivas Bayyavarapu break; 5687c31335aSMaruthi Srinivas Bayyavarapu if (--count == 0) { 5697c31335aSMaruthi Srinivas Bayyavarapu pr_err("Failed to reset ACP\n"); 5707c31335aSMaruthi Srinivas Bayyavarapu return -ETIMEDOUT; 5717c31335aSMaruthi Srinivas Bayyavarapu } 5727c31335aSMaruthi Srinivas Bayyavarapu udelay(100); 5737c31335aSMaruthi Srinivas Bayyavarapu } 5747c31335aSMaruthi Srinivas Bayyavarapu 5757c31335aSMaruthi Srinivas Bayyavarapu /* Enable clock to ACP and wait until the clock is enabled */ 5767c31335aSMaruthi Srinivas Bayyavarapu val = acp_reg_read(acp_mmio, mmACP_CONTROL); 5777c31335aSMaruthi Srinivas Bayyavarapu val = val | ACP_CONTROL__ClkEn_MASK; 5787c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(val, acp_mmio, mmACP_CONTROL); 5797c31335aSMaruthi Srinivas Bayyavarapu 5807c31335aSMaruthi Srinivas Bayyavarapu count = ACP_CLOCK_EN_TIME_OUT_VALUE; 5817c31335aSMaruthi Srinivas Bayyavarapu 5827c31335aSMaruthi Srinivas Bayyavarapu while (true) { 5837c31335aSMaruthi Srinivas Bayyavarapu val = acp_reg_read(acp_mmio, mmACP_STATUS); 5847c31335aSMaruthi Srinivas Bayyavarapu if (val & (u32)0x1) 5857c31335aSMaruthi Srinivas Bayyavarapu break; 5867c31335aSMaruthi Srinivas Bayyavarapu if (--count == 0) { 5877c31335aSMaruthi Srinivas Bayyavarapu pr_err("Failed to reset ACP\n"); 5887c31335aSMaruthi Srinivas Bayyavarapu return -ETIMEDOUT; 5897c31335aSMaruthi Srinivas Bayyavarapu } 5907c31335aSMaruthi Srinivas Bayyavarapu udelay(100); 5917c31335aSMaruthi Srinivas Bayyavarapu } 5927c31335aSMaruthi Srinivas Bayyavarapu 5937c31335aSMaruthi Srinivas Bayyavarapu /* Deassert the SOFT RESET flags */ 5947c31335aSMaruthi Srinivas Bayyavarapu val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET); 5957c31335aSMaruthi Srinivas Bayyavarapu val &= ~ACP_SOFT_RESET__SoftResetAud_MASK; 5967c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET); 5977c31335aSMaruthi Srinivas Bayyavarapu 598ccfbb4f5SMukunda, Vijendar /* For BT instance change pins from UART to BT */ 59919843302SPierre-Louis Bossart if (!acp_bt_uart_enable) { 600ccfbb4f5SMukunda, Vijendar val = acp_reg_read(acp_mmio, mmACP_BT_UART_PAD_SEL); 601ccfbb4f5SMukunda, Vijendar val |= ACP_BT_UART_PAD_SELECT_MASK; 602ccfbb4f5SMukunda, Vijendar acp_reg_write(val, acp_mmio, mmACP_BT_UART_PAD_SEL); 603ccfbb4f5SMukunda, Vijendar } 604ccfbb4f5SMukunda, Vijendar 605f7c4fe9cSGu Shengxian /* initialize Onion control DAGB register */ 6067c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(ACP_ONION_CNTL_DEFAULT, acp_mmio, 6077c31335aSMaruthi Srinivas Bayyavarapu mmACP_AXI2DAGB_ONION_CNTL); 6087c31335aSMaruthi Srinivas Bayyavarapu 609f7c4fe9cSGu Shengxian /* initialize Garlic control DAGB registers */ 6107c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(ACP_GARLIC_CNTL_DEFAULT, acp_mmio, 6117c31335aSMaruthi Srinivas Bayyavarapu mmACP_AXI2DAGB_GARLIC_CNTL); 6127c31335aSMaruthi Srinivas Bayyavarapu 6137c31335aSMaruthi Srinivas Bayyavarapu sram_pte_offset = ACP_DAGB_GRP_SRAM_BASE_ADDRESS | 6147c31335aSMaruthi Srinivas Bayyavarapu ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBSnoopSel_MASK | 6157c31335aSMaruthi Srinivas Bayyavarapu ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBTargetMemSel_MASK | 6167c31335aSMaruthi Srinivas Bayyavarapu ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBGrpEnable_MASK; 6177c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(sram_pte_offset, acp_mmio, mmACP_DAGB_BASE_ADDR_GRP_1); 6187c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(ACP_PAGE_SIZE_4K_ENABLE, acp_mmio, 6197c31335aSMaruthi Srinivas Bayyavarapu mmACP_DAGB_PAGE_SIZE_GRP_1); 6207c31335aSMaruthi Srinivas Bayyavarapu 6217c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(ACP_SRAM_BASE_ADDRESS, acp_mmio, 6227c31335aSMaruthi Srinivas Bayyavarapu mmACP_DMA_DESC_BASE_ADDR); 6237c31335aSMaruthi Srinivas Bayyavarapu 624f7c4fe9cSGu Shengxian /* Num of descriptors in SRAM 0x4, means 256 descriptors;(64 * 4) */ 6257c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(0x4, acp_mmio, mmACP_DMA_DESC_MAX_NUM_DSCR); 6267c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(ACP_EXTERNAL_INTR_CNTL__DMAIOCMask_MASK, 6277c31335aSMaruthi Srinivas Bayyavarapu acp_mmio, mmACP_EXTERNAL_INTR_CNTL); 6287c31335aSMaruthi Srinivas Bayyavarapu 62913838c11SMukunda, Vijendar /* 63013838c11SMukunda, Vijendar * When ACP_TILE_P1 is turned on, all SRAM banks get turned on. 631c36d9b3fSMaruthi Srinivas Bayyavarapu * Now, turn off all of them. This can't be done in 'poweron' of 632c36d9b3fSMaruthi Srinivas Bayyavarapu * ACP pm domain, as this requires ACP to be initialized. 633607b39efSVijendar Mukunda * For Stoney, Memory gating is disabled,i.e SRAM Banks 634607b39efSVijendar Mukunda * won't be turned off. The default state for SRAM banks is ON. 635607b39efSVijendar Mukunda * Setting SRAM bank state code skipped for STONEY platform. 636c36d9b3fSMaruthi Srinivas Bayyavarapu */ 637607b39efSVijendar Mukunda if (asic_type != CHIP_STONEY) { 638c36d9b3fSMaruthi Srinivas Bayyavarapu for (bank = 1; bank < 48; bank++) 639c36d9b3fSMaruthi Srinivas Bayyavarapu acp_set_sram_bank_state(acp_mmio, bank, false); 640607b39efSVijendar Mukunda } 6417c31335aSMaruthi Srinivas Bayyavarapu return 0; 6427c31335aSMaruthi Srinivas Bayyavarapu } 6437c31335aSMaruthi Srinivas Bayyavarapu 6441cce2000SMasahiro Yamada /* Deinitialize ACP */ 6457c31335aSMaruthi Srinivas Bayyavarapu static int acp_deinit(void __iomem *acp_mmio) 6467c31335aSMaruthi Srinivas Bayyavarapu { 6477c31335aSMaruthi Srinivas Bayyavarapu u32 val; 6487c31335aSMaruthi Srinivas Bayyavarapu u32 count; 6497c31335aSMaruthi Srinivas Bayyavarapu 6507c31335aSMaruthi Srinivas Bayyavarapu /* Assert Soft reset of ACP */ 6517c31335aSMaruthi Srinivas Bayyavarapu val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET); 6527c31335aSMaruthi Srinivas Bayyavarapu 6537c31335aSMaruthi Srinivas Bayyavarapu val |= ACP_SOFT_RESET__SoftResetAud_MASK; 6547c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET); 6557c31335aSMaruthi Srinivas Bayyavarapu 6567c31335aSMaruthi Srinivas Bayyavarapu count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE; 6577c31335aSMaruthi Srinivas Bayyavarapu while (true) { 6587c31335aSMaruthi Srinivas Bayyavarapu val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET); 6597c31335aSMaruthi Srinivas Bayyavarapu if (ACP_SOFT_RESET__SoftResetAudDone_MASK == 6607c31335aSMaruthi Srinivas Bayyavarapu (val & ACP_SOFT_RESET__SoftResetAudDone_MASK)) 6617c31335aSMaruthi Srinivas Bayyavarapu break; 6627c31335aSMaruthi Srinivas Bayyavarapu if (--count == 0) { 6637c31335aSMaruthi Srinivas Bayyavarapu pr_err("Failed to reset ACP\n"); 6647c31335aSMaruthi Srinivas Bayyavarapu return -ETIMEDOUT; 6657c31335aSMaruthi Srinivas Bayyavarapu } 6667c31335aSMaruthi Srinivas Bayyavarapu udelay(100); 6677c31335aSMaruthi Srinivas Bayyavarapu } 66813838c11SMukunda, Vijendar /* Disable ACP clock */ 6697c31335aSMaruthi Srinivas Bayyavarapu val = acp_reg_read(acp_mmio, mmACP_CONTROL); 6707c31335aSMaruthi Srinivas Bayyavarapu val &= ~ACP_CONTROL__ClkEn_MASK; 6717c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(val, acp_mmio, mmACP_CONTROL); 6727c31335aSMaruthi Srinivas Bayyavarapu 6737c31335aSMaruthi Srinivas Bayyavarapu count = ACP_CLOCK_EN_TIME_OUT_VALUE; 6747c31335aSMaruthi Srinivas Bayyavarapu 6757c31335aSMaruthi Srinivas Bayyavarapu while (true) { 6767c31335aSMaruthi Srinivas Bayyavarapu val = acp_reg_read(acp_mmio, mmACP_STATUS); 6777c31335aSMaruthi Srinivas Bayyavarapu if (!(val & (u32)0x1)) 6787c31335aSMaruthi Srinivas Bayyavarapu break; 6797c31335aSMaruthi Srinivas Bayyavarapu if (--count == 0) { 6807c31335aSMaruthi Srinivas Bayyavarapu pr_err("Failed to reset ACP\n"); 6817c31335aSMaruthi Srinivas Bayyavarapu return -ETIMEDOUT; 6827c31335aSMaruthi Srinivas Bayyavarapu } 6837c31335aSMaruthi Srinivas Bayyavarapu udelay(100); 6847c31335aSMaruthi Srinivas Bayyavarapu } 6857c31335aSMaruthi Srinivas Bayyavarapu return 0; 6867c31335aSMaruthi Srinivas Bayyavarapu } 6877c31335aSMaruthi Srinivas Bayyavarapu 6887c31335aSMaruthi Srinivas Bayyavarapu /* ACP DMA irq handler routine for playback, capture usecases */ 6897c31335aSMaruthi Srinivas Bayyavarapu static irqreturn_t dma_irq_handler(int irq, void *arg) 6907c31335aSMaruthi Srinivas Bayyavarapu { 691bbdb7012SAkshu Agrawal u16 dscr_idx; 6927c31335aSMaruthi Srinivas Bayyavarapu u32 intr_flag, ext_intr_status; 6937c31335aSMaruthi Srinivas Bayyavarapu struct audio_drv_data *irq_data; 6947c31335aSMaruthi Srinivas Bayyavarapu void __iomem *acp_mmio; 6957c31335aSMaruthi Srinivas Bayyavarapu struct device *dev = arg; 6967c31335aSMaruthi Srinivas Bayyavarapu bool valid_irq = false; 6977c31335aSMaruthi Srinivas Bayyavarapu 6987c31335aSMaruthi Srinivas Bayyavarapu irq_data = dev_get_drvdata(dev); 6997c31335aSMaruthi Srinivas Bayyavarapu acp_mmio = irq_data->acp_mmio; 7007c31335aSMaruthi Srinivas Bayyavarapu 7017c31335aSMaruthi Srinivas Bayyavarapu ext_intr_status = acp_reg_read(acp_mmio, mmACP_EXTERNAL_INTR_STAT); 7027c31335aSMaruthi Srinivas Bayyavarapu intr_flag = (((ext_intr_status & 7037c31335aSMaruthi Srinivas Bayyavarapu ACP_EXTERNAL_INTR_STAT__DMAIOCStat_MASK) >> 7047c31335aSMaruthi Srinivas Bayyavarapu ACP_EXTERNAL_INTR_STAT__DMAIOCStat__SHIFT)); 7057c31335aSMaruthi Srinivas Bayyavarapu 7067c31335aSMaruthi Srinivas Bayyavarapu if ((intr_flag & BIT(ACP_TO_I2S_DMA_CH_NUM)) != 0) { 7077c31335aSMaruthi Srinivas Bayyavarapu valid_irq = true; 708e21358c4SMukunda, Vijendar snd_pcm_period_elapsed(irq_data->play_i2ssp_stream); 7097c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write((intr_flag & BIT(ACP_TO_I2S_DMA_CH_NUM)) << 16, 7107c31335aSMaruthi Srinivas Bayyavarapu acp_mmio, mmACP_EXTERNAL_INTR_STAT); 7117c31335aSMaruthi Srinivas Bayyavarapu } 7127c31335aSMaruthi Srinivas Bayyavarapu 713ccfbb4f5SMukunda, Vijendar if ((intr_flag & BIT(ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM)) != 0) { 714ccfbb4f5SMukunda, Vijendar valid_irq = true; 715ccfbb4f5SMukunda, Vijendar snd_pcm_period_elapsed(irq_data->play_i2sbt_stream); 716ccfbb4f5SMukunda, Vijendar acp_reg_write((intr_flag & 717ccfbb4f5SMukunda, Vijendar BIT(ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM)) << 16, 718ccfbb4f5SMukunda, Vijendar acp_mmio, mmACP_EXTERNAL_INTR_STAT); 719ccfbb4f5SMukunda, Vijendar } 720ccfbb4f5SMukunda, Vijendar 72119e023e3SAgrawal, Akshu if ((intr_flag & BIT(I2S_TO_ACP_DMA_CH_NUM)) != 0) { 7227c31335aSMaruthi Srinivas Bayyavarapu valid_irq = true; 723bbdb7012SAkshu Agrawal if (acp_reg_read(acp_mmio, mmACP_DMA_CUR_DSCR_14) == 724bbdb7012SAkshu Agrawal CAPTURE_START_DMA_DESCR_CH15) 725bbdb7012SAkshu Agrawal dscr_idx = CAPTURE_END_DMA_DESCR_CH14; 726bbdb7012SAkshu Agrawal else 727bbdb7012SAkshu Agrawal dscr_idx = CAPTURE_START_DMA_DESCR_CH14; 728bbdb7012SAkshu Agrawal config_acp_dma_channel(acp_mmio, ACP_TO_SYSRAM_CH_NUM, dscr_idx, 729bbdb7012SAkshu Agrawal 1, 0); 730bbdb7012SAkshu Agrawal acp_dma_start(acp_mmio, ACP_TO_SYSRAM_CH_NUM, false); 731bbdb7012SAkshu Agrawal 73255af49acSDaniel Kurtz snd_pcm_period_elapsed(irq_data->capture_i2ssp_stream); 73319e023e3SAgrawal, Akshu acp_reg_write((intr_flag & BIT(I2S_TO_ACP_DMA_CH_NUM)) << 16, 7347c31335aSMaruthi Srinivas Bayyavarapu acp_mmio, mmACP_EXTERNAL_INTR_STAT); 7357c31335aSMaruthi Srinivas Bayyavarapu } 7367c31335aSMaruthi Srinivas Bayyavarapu 73719e023e3SAgrawal, Akshu if ((intr_flag & BIT(I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM)) != 0) { 738ccfbb4f5SMukunda, Vijendar valid_irq = true; 739bbdb7012SAkshu Agrawal if (acp_reg_read(acp_mmio, mmACP_DMA_CUR_DSCR_10) == 740bbdb7012SAkshu Agrawal CAPTURE_START_DMA_DESCR_CH11) 741bbdb7012SAkshu Agrawal dscr_idx = CAPTURE_END_DMA_DESCR_CH10; 742bbdb7012SAkshu Agrawal else 743bbdb7012SAkshu Agrawal dscr_idx = CAPTURE_START_DMA_DESCR_CH10; 744bbdb7012SAkshu Agrawal config_acp_dma_channel(acp_mmio, 745bbdb7012SAkshu Agrawal ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM, 746bbdb7012SAkshu Agrawal dscr_idx, 1, 0); 747bbdb7012SAkshu Agrawal acp_dma_start(acp_mmio, ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM, 748bbdb7012SAkshu Agrawal false); 749bbdb7012SAkshu Agrawal 75055af49acSDaniel Kurtz snd_pcm_period_elapsed(irq_data->capture_i2sbt_stream); 751ccfbb4f5SMukunda, Vijendar acp_reg_write((intr_flag & 75219e023e3SAgrawal, Akshu BIT(I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM)) << 16, 753ccfbb4f5SMukunda, Vijendar acp_mmio, mmACP_EXTERNAL_INTR_STAT); 754ccfbb4f5SMukunda, Vijendar } 755ccfbb4f5SMukunda, Vijendar 7567c31335aSMaruthi Srinivas Bayyavarapu if (valid_irq) 7577c31335aSMaruthi Srinivas Bayyavarapu return IRQ_HANDLED; 7587c31335aSMaruthi Srinivas Bayyavarapu else 7597c31335aSMaruthi Srinivas Bayyavarapu return IRQ_NONE; 7607c31335aSMaruthi Srinivas Bayyavarapu } 7617c31335aSMaruthi Srinivas Bayyavarapu 7628c028a40SKuninori Morimoto static int acp_dma_open(struct snd_soc_component *component, 7638c028a40SKuninori Morimoto struct snd_pcm_substream *substream) 7647c31335aSMaruthi Srinivas Bayyavarapu { 765c36d9b3fSMaruthi Srinivas Bayyavarapu u16 bank; 7667c31335aSMaruthi Srinivas Bayyavarapu int ret = 0; 7677c31335aSMaruthi Srinivas Bayyavarapu struct snd_pcm_runtime *runtime = substream->runtime; 768a1042a42SKuninori Morimoto struct audio_drv_data *intr_data = dev_get_drvdata(component->dev); 7697c31335aSMaruthi Srinivas Bayyavarapu struct audio_substream_data *adata = 7707c31335aSMaruthi Srinivas Bayyavarapu kzalloc(sizeof(struct audio_substream_data), GFP_KERNEL); 77113838c11SMukunda, Vijendar if (!adata) 7727c31335aSMaruthi Srinivas Bayyavarapu return -ENOMEM; 7737c31335aSMaruthi Srinivas Bayyavarapu 7749c7d6fabSVijendar Mukunda if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 7759c7d6fabSVijendar Mukunda switch (intr_data->asic_type) { 7769c7d6fabSVijendar Mukunda case CHIP_STONEY: 7779c7d6fabSVijendar Mukunda runtime->hw = acp_st_pcm_hardware_playback; 7789c7d6fabSVijendar Mukunda break; 7799c7d6fabSVijendar Mukunda default: 7807c31335aSMaruthi Srinivas Bayyavarapu runtime->hw = acp_pcm_hardware_playback; 7819c7d6fabSVijendar Mukunda } 7829c7d6fabSVijendar Mukunda } else { 7839c7d6fabSVijendar Mukunda switch (intr_data->asic_type) { 7849c7d6fabSVijendar Mukunda case CHIP_STONEY: 7859c7d6fabSVijendar Mukunda runtime->hw = acp_st_pcm_hardware_capture; 7869c7d6fabSVijendar Mukunda break; 7879c7d6fabSVijendar Mukunda default: 7887c31335aSMaruthi Srinivas Bayyavarapu runtime->hw = acp_pcm_hardware_capture; 7899c7d6fabSVijendar Mukunda } 7909c7d6fabSVijendar Mukunda } 7917c31335aSMaruthi Srinivas Bayyavarapu 7927c31335aSMaruthi Srinivas Bayyavarapu ret = snd_pcm_hw_constraint_integer(runtime, 7937c31335aSMaruthi Srinivas Bayyavarapu SNDRV_PCM_HW_PARAM_PERIODS); 7947c31335aSMaruthi Srinivas Bayyavarapu if (ret < 0) { 795a1042a42SKuninori Morimoto dev_err(component->dev, "set integer constraint failed\n"); 796cde6bcd5SDan Carpenter kfree(adata); 7977c31335aSMaruthi Srinivas Bayyavarapu return ret; 7987c31335aSMaruthi Srinivas Bayyavarapu } 7997c31335aSMaruthi Srinivas Bayyavarapu 8007c31335aSMaruthi Srinivas Bayyavarapu adata->acp_mmio = intr_data->acp_mmio; 8017c31335aSMaruthi Srinivas Bayyavarapu runtime->private_data = adata; 8027c31335aSMaruthi Srinivas Bayyavarapu 80313838c11SMukunda, Vijendar /* 80413838c11SMukunda, Vijendar * Enable ACP irq, when neither playback or capture streams are 8057c31335aSMaruthi Srinivas Bayyavarapu * active by the time when a new stream is being opened. 8067c31335aSMaruthi Srinivas Bayyavarapu * This enablement is not required for another stream, if current 8077c31335aSMaruthi Srinivas Bayyavarapu * stream is not closed 8087c31335aSMaruthi Srinivas Bayyavarapu */ 809ccfbb4f5SMukunda, Vijendar if (!intr_data->play_i2ssp_stream && !intr_data->capture_i2ssp_stream && 810ccfbb4f5SMukunda, Vijendar !intr_data->play_i2sbt_stream && !intr_data->capture_i2sbt_stream) 8117c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB); 8127c31335aSMaruthi Srinivas Bayyavarapu 813c36d9b3fSMaruthi Srinivas Bayyavarapu if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 81413838c11SMukunda, Vijendar /* 81513838c11SMukunda, Vijendar * For Stoney, Memory gating is disabled,i.e SRAM Banks 816607b39efSVijendar Mukunda * won't be turned off. The default state for SRAM banks is ON. 817607b39efSVijendar Mukunda * Setting SRAM bank state code skipped for STONEY platform. 818607b39efSVijendar Mukunda */ 819607b39efSVijendar Mukunda if (intr_data->asic_type != CHIP_STONEY) { 820c36d9b3fSMaruthi Srinivas Bayyavarapu for (bank = 1; bank <= 4; bank++) 821607b39efSVijendar Mukunda acp_set_sram_bank_state(intr_data->acp_mmio, 822607b39efSVijendar Mukunda bank, true); 823607b39efSVijendar Mukunda } 824c36d9b3fSMaruthi Srinivas Bayyavarapu } else { 825607b39efSVijendar Mukunda if (intr_data->asic_type != CHIP_STONEY) { 826c36d9b3fSMaruthi Srinivas Bayyavarapu for (bank = 5; bank <= 8; bank++) 827607b39efSVijendar Mukunda acp_set_sram_bank_state(intr_data->acp_mmio, 828607b39efSVijendar Mukunda bank, true); 829607b39efSVijendar Mukunda } 830c36d9b3fSMaruthi Srinivas Bayyavarapu } 8317c31335aSMaruthi Srinivas Bayyavarapu 8327c31335aSMaruthi Srinivas Bayyavarapu return 0; 8337c31335aSMaruthi Srinivas Bayyavarapu } 8347c31335aSMaruthi Srinivas Bayyavarapu 8358c028a40SKuninori Morimoto static int acp_dma_hw_params(struct snd_soc_component *component, 8368c028a40SKuninori Morimoto struct snd_pcm_substream *substream, 8377c31335aSMaruthi Srinivas Bayyavarapu struct snd_pcm_hw_params *params) 8387c31335aSMaruthi Srinivas Bayyavarapu { 8397c31335aSMaruthi Srinivas Bayyavarapu uint64_t size; 840a37d48e3SVijendar Mukunda u32 val = 0; 8417c31335aSMaruthi Srinivas Bayyavarapu struct snd_pcm_runtime *runtime; 8427c31335aSMaruthi Srinivas Bayyavarapu struct audio_substream_data *rtd; 843ded00543SKuninori Morimoto struct snd_soc_pcm_runtime *prtd = asoc_substream_to_rtd(substream); 844a1042a42SKuninori Morimoto struct audio_drv_data *adata = dev_get_drvdata(component->dev); 845ccfbb4f5SMukunda, Vijendar struct snd_soc_card *card = prtd->card; 846ccfbb4f5SMukunda, Vijendar struct acp_platform_info *pinfo = snd_soc_card_get_drvdata(card); 8477c31335aSMaruthi Srinivas Bayyavarapu 8487c31335aSMaruthi Srinivas Bayyavarapu runtime = substream->runtime; 8497c31335aSMaruthi Srinivas Bayyavarapu rtd = runtime->private_data; 8507c31335aSMaruthi Srinivas Bayyavarapu 8517c31335aSMaruthi Srinivas Bayyavarapu if (WARN_ON(!rtd)) 8527c31335aSMaruthi Srinivas Bayyavarapu return -EINVAL; 8537c31335aSMaruthi Srinivas Bayyavarapu 8542718c89aSAkshu Agrawal if (pinfo) { 8558dcb0c90SAkshu Agrawal if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 8568dcb0c90SAkshu Agrawal rtd->i2s_instance = pinfo->play_i2s_instance; 8578dcb0c90SAkshu Agrawal } else { 8588dcb0c90SAkshu Agrawal rtd->i2s_instance = pinfo->cap_i2s_instance; 8592718c89aSAkshu Agrawal rtd->capture_channel = pinfo->capture_channel; 8602718c89aSAkshu Agrawal } 8618dcb0c90SAkshu Agrawal } 862a37d48e3SVijendar Mukunda if (adata->asic_type == CHIP_STONEY) { 86313838c11SMukunda, Vijendar val = acp_reg_read(adata->acp_mmio, 86413838c11SMukunda, Vijendar mmACP_I2S_16BIT_RESOLUTION_EN); 865ccfbb4f5SMukunda, Vijendar if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 866ccfbb4f5SMukunda, Vijendar switch (rtd->i2s_instance) { 867ccfbb4f5SMukunda, Vijendar case I2S_BT_INSTANCE: 868ccfbb4f5SMukunda, Vijendar val |= ACP_I2S_BT_16BIT_RESOLUTION_EN; 869ccfbb4f5SMukunda, Vijendar break; 870ccfbb4f5SMukunda, Vijendar case I2S_SP_INSTANCE: 871ccfbb4f5SMukunda, Vijendar default: 872a37d48e3SVijendar Mukunda val |= ACP_I2S_SP_16BIT_RESOLUTION_EN; 873ccfbb4f5SMukunda, Vijendar } 874ccfbb4f5SMukunda, Vijendar } else { 875ccfbb4f5SMukunda, Vijendar switch (rtd->i2s_instance) { 876ccfbb4f5SMukunda, Vijendar case I2S_BT_INSTANCE: 877ccfbb4f5SMukunda, Vijendar val |= ACP_I2S_BT_16BIT_RESOLUTION_EN; 878ccfbb4f5SMukunda, Vijendar break; 879ccfbb4f5SMukunda, Vijendar case I2S_SP_INSTANCE: 880ccfbb4f5SMukunda, Vijendar default: 881a37d48e3SVijendar Mukunda val |= ACP_I2S_MIC_16BIT_RESOLUTION_EN; 882ccfbb4f5SMukunda, Vijendar } 883ccfbb4f5SMukunda, Vijendar } 88413838c11SMukunda, Vijendar acp_reg_write(val, adata->acp_mmio, 88513838c11SMukunda, Vijendar mmACP_I2S_16BIT_RESOLUTION_EN); 886a37d48e3SVijendar Mukunda } 8878769bb55SVijendar Mukunda 8888769bb55SVijendar Mukunda if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 889ccfbb4f5SMukunda, Vijendar switch (rtd->i2s_instance) { 890ccfbb4f5SMukunda, Vijendar case I2S_BT_INSTANCE: 891ccfbb4f5SMukunda, Vijendar rtd->pte_offset = ACP_ST_BT_PLAYBACK_PTE_OFFSET; 892ccfbb4f5SMukunda, Vijendar rtd->ch1 = SYSRAM_TO_ACP_BT_INSTANCE_CH_NUM; 893ccfbb4f5SMukunda, Vijendar rtd->ch2 = ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM; 894ccfbb4f5SMukunda, Vijendar rtd->sram_bank = ACP_SRAM_BANK_3_ADDRESS; 895ccfbb4f5SMukunda, Vijendar rtd->destination = TO_BLUETOOTH; 896ccfbb4f5SMukunda, Vijendar rtd->dma_dscr_idx_1 = PLAYBACK_START_DMA_DESCR_CH8; 897ccfbb4f5SMukunda, Vijendar rtd->dma_dscr_idx_2 = PLAYBACK_START_DMA_DESCR_CH9; 898ccfbb4f5SMukunda, Vijendar rtd->byte_cnt_high_reg_offset = 899ccfbb4f5SMukunda, Vijendar mmACP_I2S_BT_TRANSMIT_BYTE_CNT_HIGH; 900ccfbb4f5SMukunda, Vijendar rtd->byte_cnt_low_reg_offset = 901ccfbb4f5SMukunda, Vijendar mmACP_I2S_BT_TRANSMIT_BYTE_CNT_LOW; 902ccfbb4f5SMukunda, Vijendar adata->play_i2sbt_stream = substream; 903ccfbb4f5SMukunda, Vijendar break; 904ccfbb4f5SMukunda, Vijendar case I2S_SP_INSTANCE: 905ccfbb4f5SMukunda, Vijendar default: 906e188c525SMukunda, Vijendar switch (adata->asic_type) { 907e188c525SMukunda, Vijendar case CHIP_STONEY: 908e188c525SMukunda, Vijendar rtd->pte_offset = ACP_ST_PLAYBACK_PTE_OFFSET; 909e188c525SMukunda, Vijendar break; 910e188c525SMukunda, Vijendar default: 911e188c525SMukunda, Vijendar rtd->pte_offset = ACP_PLAYBACK_PTE_OFFSET; 912e188c525SMukunda, Vijendar } 9138769bb55SVijendar Mukunda rtd->ch1 = SYSRAM_TO_ACP_CH_NUM; 9148769bb55SVijendar Mukunda rtd->ch2 = ACP_TO_I2S_DMA_CH_NUM; 91518e8a40dSMukunda, Vijendar rtd->sram_bank = ACP_SRAM_BANK_1_ADDRESS; 9168769bb55SVijendar Mukunda rtd->destination = TO_ACP_I2S_1; 9178769bb55SVijendar Mukunda rtd->dma_dscr_idx_1 = PLAYBACK_START_DMA_DESCR_CH12; 9188769bb55SVijendar Mukunda rtd->dma_dscr_idx_2 = PLAYBACK_START_DMA_DESCR_CH13; 9197f004847SVijendar Mukunda rtd->byte_cnt_high_reg_offset = 9207f004847SVijendar Mukunda mmACP_I2S_TRANSMIT_BYTE_CNT_HIGH; 921ccfbb4f5SMukunda, Vijendar rtd->byte_cnt_low_reg_offset = 922ccfbb4f5SMukunda, Vijendar mmACP_I2S_TRANSMIT_BYTE_CNT_LOW; 923ccfbb4f5SMukunda, Vijendar adata->play_i2ssp_stream = substream; 924ccfbb4f5SMukunda, Vijendar } 9258769bb55SVijendar Mukunda } else { 926ccfbb4f5SMukunda, Vijendar switch (rtd->i2s_instance) { 927ccfbb4f5SMukunda, Vijendar case I2S_BT_INSTANCE: 928ccfbb4f5SMukunda, Vijendar rtd->pte_offset = ACP_ST_BT_CAPTURE_PTE_OFFSET; 92955af49acSDaniel Kurtz rtd->ch1 = I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM; 93055af49acSDaniel Kurtz rtd->ch2 = ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM; 931ccfbb4f5SMukunda, Vijendar rtd->sram_bank = ACP_SRAM_BANK_4_ADDRESS; 932ccfbb4f5SMukunda, Vijendar rtd->destination = FROM_BLUETOOTH; 933ccfbb4f5SMukunda, Vijendar rtd->dma_dscr_idx_1 = CAPTURE_START_DMA_DESCR_CH10; 934ccfbb4f5SMukunda, Vijendar rtd->dma_dscr_idx_2 = CAPTURE_START_DMA_DESCR_CH11; 935c21c834aSAkshu Agrawal rtd->byte_cnt_high_reg_offset = 936c21c834aSAkshu Agrawal mmACP_I2S_BT_RECEIVE_BYTE_CNT_HIGH; 937c21c834aSAkshu Agrawal rtd->byte_cnt_low_reg_offset = 938c21c834aSAkshu Agrawal mmACP_I2S_BT_RECEIVE_BYTE_CNT_LOW; 939662fb3efSMukunda, Vijendar rtd->dma_curr_dscr = mmACP_DMA_CUR_DSCR_11; 940ccfbb4f5SMukunda, Vijendar adata->capture_i2sbt_stream = substream; 941ccfbb4f5SMukunda, Vijendar break; 942ccfbb4f5SMukunda, Vijendar case I2S_SP_INSTANCE: 943ccfbb4f5SMukunda, Vijendar default: 944ccfbb4f5SMukunda, Vijendar rtd->pte_offset = ACP_CAPTURE_PTE_OFFSET; 94555af49acSDaniel Kurtz rtd->ch1 = I2S_TO_ACP_DMA_CH_NUM; 94655af49acSDaniel Kurtz rtd->ch2 = ACP_TO_SYSRAM_CH_NUM; 947e188c525SMukunda, Vijendar switch (adata->asic_type) { 948e188c525SMukunda, Vijendar case CHIP_STONEY: 949e188c525SMukunda, Vijendar rtd->pte_offset = ACP_ST_CAPTURE_PTE_OFFSET; 95018e8a40dSMukunda, Vijendar rtd->sram_bank = ACP_SRAM_BANK_2_ADDRESS; 951e188c525SMukunda, Vijendar break; 952e188c525SMukunda, Vijendar default: 953e188c525SMukunda, Vijendar rtd->pte_offset = ACP_CAPTURE_PTE_OFFSET; 95418e8a40dSMukunda, Vijendar rtd->sram_bank = ACP_SRAM_BANK_5_ADDRESS; 955e188c525SMukunda, Vijendar } 9568769bb55SVijendar Mukunda rtd->destination = FROM_ACP_I2S_1; 9578769bb55SVijendar Mukunda rtd->dma_dscr_idx_1 = CAPTURE_START_DMA_DESCR_CH14; 9588769bb55SVijendar Mukunda rtd->dma_dscr_idx_2 = CAPTURE_START_DMA_DESCR_CH15; 959c21c834aSAkshu Agrawal rtd->byte_cnt_high_reg_offset = 960c21c834aSAkshu Agrawal mmACP_I2S_RECEIVED_BYTE_CNT_HIGH; 961c21c834aSAkshu Agrawal rtd->byte_cnt_low_reg_offset = 962c21c834aSAkshu Agrawal mmACP_I2S_RECEIVED_BYTE_CNT_LOW; 963662fb3efSMukunda, Vijendar rtd->dma_curr_dscr = mmACP_DMA_CUR_DSCR_15; 964ccfbb4f5SMukunda, Vijendar adata->capture_i2ssp_stream = substream; 965ccfbb4f5SMukunda, Vijendar } 9668769bb55SVijendar Mukunda } 9678769bb55SVijendar Mukunda 9687c31335aSMaruthi Srinivas Bayyavarapu size = params_buffer_bytes(params); 9697c31335aSMaruthi Srinivas Bayyavarapu 970c36d9b3fSMaruthi Srinivas Bayyavarapu acp_set_sram_bank_state(rtd->acp_mmio, 0, true); 9717c31335aSMaruthi Srinivas Bayyavarapu /* Save for runtime private data */ 9728b5d9531STakashi Iwai rtd->dma_addr = runtime->dma_addr; 9737c31335aSMaruthi Srinivas Bayyavarapu rtd->order = get_order(size); 9747c31335aSMaruthi Srinivas Bayyavarapu 9757c31335aSMaruthi Srinivas Bayyavarapu /* Fill the page table entries in ACP SRAM */ 9767c31335aSMaruthi Srinivas Bayyavarapu rtd->size = size; 9777c31335aSMaruthi Srinivas Bayyavarapu rtd->num_of_pages = PAGE_ALIGN(size) >> PAGE_SHIFT; 9787c31335aSMaruthi Srinivas Bayyavarapu rtd->direction = substream->stream; 9797c31335aSMaruthi Srinivas Bayyavarapu 980aac89748SVijendar Mukunda config_acp_dma(rtd->acp_mmio, rtd, adata->asic_type); 9817f4aee8fSTakashi Iwai return 0; 9827c31335aSMaruthi Srinivas Bayyavarapu } 9837c31335aSMaruthi Srinivas Bayyavarapu 9847f004847SVijendar Mukunda static u64 acp_get_byte_count(struct audio_substream_data *rtd) 98561add814SVijendar Mukunda { 9867f004847SVijendar Mukunda union acp_dma_count byte_count; 98761add814SVijendar Mukunda 9887f004847SVijendar Mukunda byte_count.bcount.high = acp_reg_read(rtd->acp_mmio, 9897f004847SVijendar Mukunda rtd->byte_cnt_high_reg_offset); 9907f004847SVijendar Mukunda byte_count.bcount.low = acp_reg_read(rtd->acp_mmio, 9917f004847SVijendar Mukunda rtd->byte_cnt_low_reg_offset); 9927f004847SVijendar Mukunda return byte_count.bytescount; 99361add814SVijendar Mukunda } 99461add814SVijendar Mukunda 9958c028a40SKuninori Morimoto static snd_pcm_uframes_t acp_dma_pointer(struct snd_soc_component *component, 9968c028a40SKuninori Morimoto struct snd_pcm_substream *substream) 9977c31335aSMaruthi Srinivas Bayyavarapu { 99861add814SVijendar Mukunda u32 buffersize; 9997c31335aSMaruthi Srinivas Bayyavarapu u32 pos = 0; 100061add814SVijendar Mukunda u64 bytescount = 0; 1001662fb3efSMukunda, Vijendar u16 dscr; 1002c21c834aSAkshu Agrawal u32 period_bytes, delay; 10037c31335aSMaruthi Srinivas Bayyavarapu 10047c31335aSMaruthi Srinivas Bayyavarapu struct snd_pcm_runtime *runtime = substream->runtime; 10057c31335aSMaruthi Srinivas Bayyavarapu struct audio_substream_data *rtd = runtime->private_data; 1006*feea640aSKuninori Morimoto struct audio_drv_data *adata = dev_get_drvdata(component->dev); 10077c31335aSMaruthi Srinivas Bayyavarapu 10087afa535eSMukunda, Vijendar if (!rtd) 10097afa535eSMukunda, Vijendar return -EINVAL; 10107afa535eSMukunda, Vijendar 1011662fb3efSMukunda, Vijendar if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { 1012662fb3efSMukunda, Vijendar period_bytes = frames_to_bytes(runtime, runtime->period_size); 1013c50535edSAkshu Agrawal bytescount = acp_get_byte_count(rtd); 1014c50535edSAkshu Agrawal if (bytescount >= rtd->bytescount) 1015c50535edSAkshu Agrawal bytescount -= rtd->bytescount; 1016c50535edSAkshu Agrawal if (bytescount < period_bytes) { 1017c50535edSAkshu Agrawal pos = 0; 1018c50535edSAkshu Agrawal } else { 1019662fb3efSMukunda, Vijendar dscr = acp_reg_read(rtd->acp_mmio, rtd->dma_curr_dscr); 1020662fb3efSMukunda, Vijendar if (dscr == rtd->dma_dscr_idx_1) 1021662fb3efSMukunda, Vijendar pos = period_bytes; 1022662fb3efSMukunda, Vijendar else 1023662fb3efSMukunda, Vijendar pos = 0; 1024c50535edSAkshu Agrawal } 1025c50535edSAkshu Agrawal if (bytescount > 0) { 1026c21c834aSAkshu Agrawal delay = do_div(bytescount, period_bytes); 1027*feea640aSKuninori Morimoto adata->delay += bytes_to_frames(runtime, delay); 1028c50535edSAkshu Agrawal } 1029662fb3efSMukunda, Vijendar } else { 103061add814SVijendar Mukunda buffersize = frames_to_bytes(runtime, runtime->buffer_size); 10317f004847SVijendar Mukunda bytescount = acp_get_byte_count(rtd); 1032662fb3efSMukunda, Vijendar if (bytescount > rtd->bytescount) 10339af8937eSVijendar Mukunda bytescount -= rtd->bytescount; 10347db08b2cSGuenter Roeck pos = do_div(bytescount, buffersize); 1035662fb3efSMukunda, Vijendar } 10367c31335aSMaruthi Srinivas Bayyavarapu return bytes_to_frames(runtime, pos); 10377c31335aSMaruthi Srinivas Bayyavarapu } 10387c31335aSMaruthi Srinivas Bayyavarapu 1039*feea640aSKuninori Morimoto static snd_pcm_sframes_t acp_dma_delay(struct snd_soc_component *component, 1040*feea640aSKuninori Morimoto struct snd_pcm_substream *substream) 1041*feea640aSKuninori Morimoto { 1042*feea640aSKuninori Morimoto struct audio_drv_data *adata = dev_get_drvdata(component->dev); 1043*feea640aSKuninori Morimoto snd_pcm_sframes_t delay = adata->delay; 1044*feea640aSKuninori Morimoto 1045*feea640aSKuninori Morimoto adata->delay = 0; 1046*feea640aSKuninori Morimoto 1047*feea640aSKuninori Morimoto return delay; 1048*feea640aSKuninori Morimoto } 1049*feea640aSKuninori Morimoto 10508c028a40SKuninori Morimoto static int acp_dma_prepare(struct snd_soc_component *component, 10518c028a40SKuninori Morimoto struct snd_pcm_substream *substream) 10527c31335aSMaruthi Srinivas Bayyavarapu { 10537c31335aSMaruthi Srinivas Bayyavarapu struct snd_pcm_runtime *runtime = substream->runtime; 10547c31335aSMaruthi Srinivas Bayyavarapu struct audio_substream_data *rtd = runtime->private_data; 1055fa9d2f17SAgrawal, Akshu u16 ch_acp_sysmem, ch_acp_i2s; 10567c31335aSMaruthi Srinivas Bayyavarapu 10577afa535eSMukunda, Vijendar if (!rtd) 10587afa535eSMukunda, Vijendar return -EINVAL; 10598769bb55SVijendar Mukunda 1060fa9d2f17SAgrawal, Akshu if (rtd->direction == SNDRV_PCM_STREAM_PLAYBACK) { 1061fa9d2f17SAgrawal, Akshu ch_acp_sysmem = rtd->ch1; 1062fa9d2f17SAgrawal, Akshu ch_acp_i2s = rtd->ch2; 1063fa9d2f17SAgrawal, Akshu } else { 1064fa9d2f17SAgrawal, Akshu ch_acp_i2s = rtd->ch1; 1065fa9d2f17SAgrawal, Akshu ch_acp_sysmem = rtd->ch2; 1066fa9d2f17SAgrawal, Akshu } 10678769bb55SVijendar Mukunda config_acp_dma_channel(rtd->acp_mmio, 1068fa9d2f17SAgrawal, Akshu ch_acp_sysmem, 10698769bb55SVijendar Mukunda rtd->dma_dscr_idx_1, 10707c31335aSMaruthi Srinivas Bayyavarapu NUM_DSCRS_PER_CHANNEL, 0); 10718769bb55SVijendar Mukunda config_acp_dma_channel(rtd->acp_mmio, 1072fa9d2f17SAgrawal, Akshu ch_acp_i2s, 10738769bb55SVijendar Mukunda rtd->dma_dscr_idx_2, 10747c31335aSMaruthi Srinivas Bayyavarapu NUM_DSCRS_PER_CHANNEL, 0); 10757c31335aSMaruthi Srinivas Bayyavarapu return 0; 10767c31335aSMaruthi Srinivas Bayyavarapu } 10777c31335aSMaruthi Srinivas Bayyavarapu 10788c028a40SKuninori Morimoto static int acp_dma_trigger(struct snd_soc_component *component, 10798c028a40SKuninori Morimoto struct snd_pcm_substream *substream, int cmd) 10807c31335aSMaruthi Srinivas Bayyavarapu { 10817c31335aSMaruthi Srinivas Bayyavarapu int ret; 10827c31335aSMaruthi Srinivas Bayyavarapu 10837c31335aSMaruthi Srinivas Bayyavarapu struct snd_pcm_runtime *runtime = substream->runtime; 10847c31335aSMaruthi Srinivas Bayyavarapu struct audio_substream_data *rtd = runtime->private_data; 10857c31335aSMaruthi Srinivas Bayyavarapu 10867c31335aSMaruthi Srinivas Bayyavarapu if (!rtd) 10877c31335aSMaruthi Srinivas Bayyavarapu return -EINVAL; 10887c31335aSMaruthi Srinivas Bayyavarapu switch (cmd) { 10897c31335aSMaruthi Srinivas Bayyavarapu case SNDRV_PCM_TRIGGER_START: 10907c31335aSMaruthi Srinivas Bayyavarapu case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 10917c31335aSMaruthi Srinivas Bayyavarapu case SNDRV_PCM_TRIGGER_RESUME: 10921a337a1eSDaniel Kurtz rtd->bytescount = acp_get_byte_count(rtd); 1093df61f9f7SDaniel Kurtz if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { 10942718c89aSAkshu Agrawal if (rtd->capture_channel == CAP_CHANNEL0) { 10952718c89aSAkshu Agrawal acp_dma_cap_channel_disable(rtd->acp_mmio, 10962718c89aSAkshu Agrawal CAP_CHANNEL1); 10972718c89aSAkshu Agrawal acp_dma_cap_channel_enable(rtd->acp_mmio, 10982718c89aSAkshu Agrawal CAP_CHANNEL0); 10992718c89aSAkshu Agrawal } 11002718c89aSAkshu Agrawal if (rtd->capture_channel == CAP_CHANNEL1) { 11012718c89aSAkshu Agrawal acp_dma_cap_channel_disable(rtd->acp_mmio, 11022718c89aSAkshu Agrawal CAP_CHANNEL0); 11032718c89aSAkshu Agrawal acp_dma_cap_channel_enable(rtd->acp_mmio, 11042718c89aSAkshu Agrawal CAP_CHANNEL1); 11052718c89aSAkshu Agrawal } 1106bbdb7012SAkshu Agrawal acp_dma_start(rtd->acp_mmio, rtd->ch1, true); 1107bbdb7012SAkshu Agrawal } else { 1108bbdb7012SAkshu Agrawal acp_dma_start(rtd->acp_mmio, rtd->ch1, true); 1109bbdb7012SAkshu Agrawal acp_dma_start(rtd->acp_mmio, rtd->ch2, true); 11107c31335aSMaruthi Srinivas Bayyavarapu } 11117c31335aSMaruthi Srinivas Bayyavarapu ret = 0; 11127c31335aSMaruthi Srinivas Bayyavarapu break; 11137c31335aSMaruthi Srinivas Bayyavarapu case SNDRV_PCM_TRIGGER_STOP: 11147c31335aSMaruthi Srinivas Bayyavarapu case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 11157c31335aSMaruthi Srinivas Bayyavarapu case SNDRV_PCM_TRIGGER_SUSPEND: 11168769bb55SVijendar Mukunda acp_dma_stop(rtd->acp_mmio, rtd->ch2); 11178769bb55SVijendar Mukunda ret = acp_dma_stop(rtd->acp_mmio, rtd->ch1); 11187c31335aSMaruthi Srinivas Bayyavarapu break; 11197c31335aSMaruthi Srinivas Bayyavarapu default: 11207c31335aSMaruthi Srinivas Bayyavarapu ret = -EINVAL; 11217c31335aSMaruthi Srinivas Bayyavarapu } 11227c31335aSMaruthi Srinivas Bayyavarapu return ret; 11237c31335aSMaruthi Srinivas Bayyavarapu } 11247c31335aSMaruthi Srinivas Bayyavarapu 11258c028a40SKuninori Morimoto static int acp_dma_new(struct snd_soc_component *component, 11268c028a40SKuninori Morimoto struct snd_soc_pcm_runtime *rtd) 11277c31335aSMaruthi Srinivas Bayyavarapu { 1128a1042a42SKuninori Morimoto struct audio_drv_data *adata = dev_get_drvdata(component->dev); 112923aa128bSYu Zhao struct device *parent = component->dev->parent; 11309c7d6fabSVijendar Mukunda 11319c7d6fabSVijendar Mukunda switch (adata->asic_type) { 11329c7d6fabSVijendar Mukunda case CHIP_STONEY: 11337f4aee8fSTakashi Iwai snd_pcm_set_managed_buffer_all(rtd->pcm, 11349c7d6fabSVijendar Mukunda SNDRV_DMA_TYPE_DEV, 113523aa128bSYu Zhao parent, 113623aa128bSYu Zhao ST_MIN_BUFFER, 11379c7d6fabSVijendar Mukunda ST_MAX_BUFFER); 11389c7d6fabSVijendar Mukunda break; 11399c7d6fabSVijendar Mukunda default: 11407f4aee8fSTakashi Iwai snd_pcm_set_managed_buffer_all(rtd->pcm, 11417c31335aSMaruthi Srinivas Bayyavarapu SNDRV_DMA_TYPE_DEV, 114223aa128bSYu Zhao parent, 114323aa128bSYu Zhao MIN_BUFFER, 11447c31335aSMaruthi Srinivas Bayyavarapu MAX_BUFFER); 11459c7d6fabSVijendar Mukunda break; 11469c7d6fabSVijendar Mukunda } 1147f6aa470fSTakashi Iwai return 0; 11487c31335aSMaruthi Srinivas Bayyavarapu } 11497c31335aSMaruthi Srinivas Bayyavarapu 11508c028a40SKuninori Morimoto static int acp_dma_close(struct snd_soc_component *component, 11518c028a40SKuninori Morimoto struct snd_pcm_substream *substream) 11527c31335aSMaruthi Srinivas Bayyavarapu { 1153c36d9b3fSMaruthi Srinivas Bayyavarapu u16 bank; 11547c31335aSMaruthi Srinivas Bayyavarapu struct snd_pcm_runtime *runtime = substream->runtime; 11557c31335aSMaruthi Srinivas Bayyavarapu struct audio_substream_data *rtd = runtime->private_data; 1156a1042a42SKuninori Morimoto struct audio_drv_data *adata = dev_get_drvdata(component->dev); 11577c31335aSMaruthi Srinivas Bayyavarapu 1158c36d9b3fSMaruthi Srinivas Bayyavarapu if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 1159ccfbb4f5SMukunda, Vijendar switch (rtd->i2s_instance) { 1160ccfbb4f5SMukunda, Vijendar case I2S_BT_INSTANCE: 1161ccfbb4f5SMukunda, Vijendar adata->play_i2sbt_stream = NULL; 1162ccfbb4f5SMukunda, Vijendar break; 1163ccfbb4f5SMukunda, Vijendar case I2S_SP_INSTANCE: 1164ccfbb4f5SMukunda, Vijendar default: 1165e21358c4SMukunda, Vijendar adata->play_i2ssp_stream = NULL; 116613838c11SMukunda, Vijendar /* 116713838c11SMukunda, Vijendar * For Stoney, Memory gating is disabled,i.e SRAM Banks 1168ccfbb4f5SMukunda, Vijendar * won't be turned off. The default state for SRAM banks 1169ccfbb4f5SMukunda, Vijendar * is ON.Setting SRAM bank state code skipped for STONEY 1170ccfbb4f5SMukunda, Vijendar * platform. Added condition checks for Carrizo platform 1171ccfbb4f5SMukunda, Vijendar * only. 1172607b39efSVijendar Mukunda */ 1173607b39efSVijendar Mukunda if (adata->asic_type != CHIP_STONEY) { 1174c36d9b3fSMaruthi Srinivas Bayyavarapu for (bank = 1; bank <= 4; bank++) 1175ccfbb4f5SMukunda, Vijendar acp_set_sram_bank_state(adata->acp_mmio, 1176ccfbb4f5SMukunda, Vijendar bank, false); 1177ccfbb4f5SMukunda, Vijendar } 1178607b39efSVijendar Mukunda } 1179c36d9b3fSMaruthi Srinivas Bayyavarapu } else { 1180ccfbb4f5SMukunda, Vijendar switch (rtd->i2s_instance) { 1181ccfbb4f5SMukunda, Vijendar case I2S_BT_INSTANCE: 1182ccfbb4f5SMukunda, Vijendar adata->capture_i2sbt_stream = NULL; 1183ccfbb4f5SMukunda, Vijendar break; 1184ccfbb4f5SMukunda, Vijendar case I2S_SP_INSTANCE: 1185ccfbb4f5SMukunda, Vijendar default: 1186e21358c4SMukunda, Vijendar adata->capture_i2ssp_stream = NULL; 1187607b39efSVijendar Mukunda if (adata->asic_type != CHIP_STONEY) { 1188c36d9b3fSMaruthi Srinivas Bayyavarapu for (bank = 5; bank <= 8; bank++) 1189ccfbb4f5SMukunda, Vijendar acp_set_sram_bank_state(adata->acp_mmio, 1190ccfbb4f5SMukunda, Vijendar bank, false); 1191ccfbb4f5SMukunda, Vijendar } 1192c36d9b3fSMaruthi Srinivas Bayyavarapu } 1193607b39efSVijendar Mukunda } 11947c31335aSMaruthi Srinivas Bayyavarapu 119513838c11SMukunda, Vijendar /* 119613838c11SMukunda, Vijendar * Disable ACP irq, when the current stream is being closed and 11977c31335aSMaruthi Srinivas Bayyavarapu * another stream is also not active. 11987c31335aSMaruthi Srinivas Bayyavarapu */ 1199ccfbb4f5SMukunda, Vijendar if (!adata->play_i2ssp_stream && !adata->capture_i2ssp_stream && 1200ccfbb4f5SMukunda, Vijendar !adata->play_i2sbt_stream && !adata->capture_i2sbt_stream) 12017c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(0, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB); 1202cac6f597SMukunda, Vijendar kfree(rtd); 12037c31335aSMaruthi Srinivas Bayyavarapu return 0; 12047c31335aSMaruthi Srinivas Bayyavarapu } 12057c31335aSMaruthi Srinivas Bayyavarapu 12068c028a40SKuninori Morimoto static const struct snd_soc_component_driver acp_asoc_platform = { 12078c028a40SKuninori Morimoto .name = DRV_NAME, 12087c31335aSMaruthi Srinivas Bayyavarapu .open = acp_dma_open, 12097c31335aSMaruthi Srinivas Bayyavarapu .close = acp_dma_close, 12107c31335aSMaruthi Srinivas Bayyavarapu .hw_params = acp_dma_hw_params, 12117c31335aSMaruthi Srinivas Bayyavarapu .trigger = acp_dma_trigger, 12127c31335aSMaruthi Srinivas Bayyavarapu .pointer = acp_dma_pointer, 1213*feea640aSKuninori Morimoto .delay = acp_dma_delay, 12147c31335aSMaruthi Srinivas Bayyavarapu .prepare = acp_dma_prepare, 12158c028a40SKuninori Morimoto .pcm_construct = acp_dma_new, 12167c31335aSMaruthi Srinivas Bayyavarapu }; 12177c31335aSMaruthi Srinivas Bayyavarapu 12187c31335aSMaruthi Srinivas Bayyavarapu static int acp_audio_probe(struct platform_device *pdev) 12197c31335aSMaruthi Srinivas Bayyavarapu { 12207c31335aSMaruthi Srinivas Bayyavarapu int status; 12217c31335aSMaruthi Srinivas Bayyavarapu struct audio_drv_data *audio_drv_data; 12227c31335aSMaruthi Srinivas Bayyavarapu struct resource *res; 1223a1b16aaaSVijendar Mukunda const u32 *pdata = pdev->dev.platform_data; 12247c31335aSMaruthi Srinivas Bayyavarapu 1225fdaa4511SGuenter Roeck if (!pdata) { 1226fdaa4511SGuenter Roeck dev_err(&pdev->dev, "Missing platform data\n"); 1227fdaa4511SGuenter Roeck return -ENODEV; 1228fdaa4511SGuenter Roeck } 1229fdaa4511SGuenter Roeck 12307c31335aSMaruthi Srinivas Bayyavarapu audio_drv_data = devm_kzalloc(&pdev->dev, sizeof(struct audio_drv_data), 12317c31335aSMaruthi Srinivas Bayyavarapu GFP_KERNEL); 123213838c11SMukunda, Vijendar if (!audio_drv_data) 12337c31335aSMaruthi Srinivas Bayyavarapu return -ENOMEM; 12347c31335aSMaruthi Srinivas Bayyavarapu 1235dfafc182SYueHaibing audio_drv_data->acp_mmio = devm_platform_ioremap_resource(pdev, 0); 1236fdaa4511SGuenter Roeck if (IS_ERR(audio_drv_data->acp_mmio)) 1237fdaa4511SGuenter Roeck return PTR_ERR(audio_drv_data->acp_mmio); 12387c31335aSMaruthi Srinivas Bayyavarapu 123913838c11SMukunda, Vijendar /* 124013838c11SMukunda, Vijendar * The following members gets populated in device 'open' 12417c31335aSMaruthi Srinivas Bayyavarapu * function. Till then interrupts are disabled in 'acp_init' 12427c31335aSMaruthi Srinivas Bayyavarapu * and device doesn't generate any interrupts. 12437c31335aSMaruthi Srinivas Bayyavarapu */ 12447c31335aSMaruthi Srinivas Bayyavarapu 1245e21358c4SMukunda, Vijendar audio_drv_data->play_i2ssp_stream = NULL; 1246e21358c4SMukunda, Vijendar audio_drv_data->capture_i2ssp_stream = NULL; 1247ccfbb4f5SMukunda, Vijendar audio_drv_data->play_i2sbt_stream = NULL; 1248ccfbb4f5SMukunda, Vijendar audio_drv_data->capture_i2sbt_stream = NULL; 1249e21358c4SMukunda, Vijendar 1250a1b16aaaSVijendar Mukunda audio_drv_data->asic_type = *pdata; 12517c31335aSMaruthi Srinivas Bayyavarapu 12527c31335aSMaruthi Srinivas Bayyavarapu res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 12537c31335aSMaruthi Srinivas Bayyavarapu if (!res) { 12547c31335aSMaruthi Srinivas Bayyavarapu dev_err(&pdev->dev, "IORESOURCE_IRQ FAILED\n"); 12557c31335aSMaruthi Srinivas Bayyavarapu return -ENODEV; 12567c31335aSMaruthi Srinivas Bayyavarapu } 12577c31335aSMaruthi Srinivas Bayyavarapu 12587c31335aSMaruthi Srinivas Bayyavarapu status = devm_request_irq(&pdev->dev, res->start, dma_irq_handler, 12597c31335aSMaruthi Srinivas Bayyavarapu 0, "ACP_IRQ", &pdev->dev); 12607c31335aSMaruthi Srinivas Bayyavarapu if (status) { 12617c31335aSMaruthi Srinivas Bayyavarapu dev_err(&pdev->dev, "ACP IRQ request failed\n"); 12627c31335aSMaruthi Srinivas Bayyavarapu return status; 12637c31335aSMaruthi Srinivas Bayyavarapu } 12647c31335aSMaruthi Srinivas Bayyavarapu 12657c31335aSMaruthi Srinivas Bayyavarapu dev_set_drvdata(&pdev->dev, audio_drv_data); 12667c31335aSMaruthi Srinivas Bayyavarapu 12677c31335aSMaruthi Srinivas Bayyavarapu /* Initialize the ACP */ 12687afa535eSMukunda, Vijendar status = acp_init(audio_drv_data->acp_mmio, audio_drv_data->asic_type); 12697afa535eSMukunda, Vijendar if (status) { 12707afa535eSMukunda, Vijendar dev_err(&pdev->dev, "ACP Init failed status:%d\n", status); 12717afa535eSMukunda, Vijendar return status; 12727afa535eSMukunda, Vijendar } 12737c31335aSMaruthi Srinivas Bayyavarapu 1274a1042a42SKuninori Morimoto status = devm_snd_soc_register_component(&pdev->dev, 1275a1042a42SKuninori Morimoto &acp_asoc_platform, NULL, 0); 12767c31335aSMaruthi Srinivas Bayyavarapu if (status != 0) { 12777c31335aSMaruthi Srinivas Bayyavarapu dev_err(&pdev->dev, "Fail to register ALSA platform device\n"); 12787c31335aSMaruthi Srinivas Bayyavarapu return status; 12797c31335aSMaruthi Srinivas Bayyavarapu } 12807c31335aSMaruthi Srinivas Bayyavarapu 12811927da93SMaruthi Srinivas Bayyavarapu pm_runtime_set_autosuspend_delay(&pdev->dev, 10000); 12821927da93SMaruthi Srinivas Bayyavarapu pm_runtime_use_autosuspend(&pdev->dev); 12831927da93SMaruthi Srinivas Bayyavarapu pm_runtime_enable(&pdev->dev); 12841927da93SMaruthi Srinivas Bayyavarapu 12857c31335aSMaruthi Srinivas Bayyavarapu return status; 12867c31335aSMaruthi Srinivas Bayyavarapu } 12877c31335aSMaruthi Srinivas Bayyavarapu 12887c31335aSMaruthi Srinivas Bayyavarapu static int acp_audio_remove(struct platform_device *pdev) 12897c31335aSMaruthi Srinivas Bayyavarapu { 12907afa535eSMukunda, Vijendar int status; 12917c31335aSMaruthi Srinivas Bayyavarapu struct audio_drv_data *adata = dev_get_drvdata(&pdev->dev); 12927c31335aSMaruthi Srinivas Bayyavarapu 12937afa535eSMukunda, Vijendar status = acp_deinit(adata->acp_mmio); 12947afa535eSMukunda, Vijendar if (status) 12957afa535eSMukunda, Vijendar dev_err(&pdev->dev, "ACP Deinit failed status:%d\n", status); 12961927da93SMaruthi Srinivas Bayyavarapu pm_runtime_disable(&pdev->dev); 12977c31335aSMaruthi Srinivas Bayyavarapu 12987c31335aSMaruthi Srinivas Bayyavarapu return 0; 12997c31335aSMaruthi Srinivas Bayyavarapu } 13007c31335aSMaruthi Srinivas Bayyavarapu 13011927da93SMaruthi Srinivas Bayyavarapu static int acp_pcm_resume(struct device *dev) 13021927da93SMaruthi Srinivas Bayyavarapu { 1303c36d9b3fSMaruthi Srinivas Bayyavarapu u16 bank; 13047afa535eSMukunda, Vijendar int status; 1305ccfbb4f5SMukunda, Vijendar struct audio_substream_data *rtd; 13061927da93SMaruthi Srinivas Bayyavarapu struct audio_drv_data *adata = dev_get_drvdata(dev); 13071927da93SMaruthi Srinivas Bayyavarapu 13087afa535eSMukunda, Vijendar status = acp_init(adata->acp_mmio, adata->asic_type); 13097afa535eSMukunda, Vijendar if (status) { 13107afa535eSMukunda, Vijendar dev_err(dev, "ACP Init failed status:%d\n", status); 13117afa535eSMukunda, Vijendar return status; 13127afa535eSMukunda, Vijendar } 13131927da93SMaruthi Srinivas Bayyavarapu 1314e21358c4SMukunda, Vijendar if (adata->play_i2ssp_stream && adata->play_i2ssp_stream->runtime) { 131513838c11SMukunda, Vijendar /* 131613838c11SMukunda, Vijendar * For Stoney, Memory gating is disabled,i.e SRAM Banks 1317607b39efSVijendar Mukunda * won't be turned off. The default state for SRAM banks is ON. 1318607b39efSVijendar Mukunda * Setting SRAM bank state code skipped for STONEY platform. 1319607b39efSVijendar Mukunda */ 1320607b39efSVijendar Mukunda if (adata->asic_type != CHIP_STONEY) { 1321c36d9b3fSMaruthi Srinivas Bayyavarapu for (bank = 1; bank <= 4; bank++) 1322c36d9b3fSMaruthi Srinivas Bayyavarapu acp_set_sram_bank_state(adata->acp_mmio, bank, 1323c36d9b3fSMaruthi Srinivas Bayyavarapu true); 1324607b39efSVijendar Mukunda } 1325ccfbb4f5SMukunda, Vijendar rtd = adata->play_i2ssp_stream->runtime->private_data; 1326ccfbb4f5SMukunda, Vijendar config_acp_dma(adata->acp_mmio, rtd, adata->asic_type); 1327c36d9b3fSMaruthi Srinivas Bayyavarapu } 132813838c11SMukunda, Vijendar if (adata->capture_i2ssp_stream && 132913838c11SMukunda, Vijendar adata->capture_i2ssp_stream->runtime) { 1330607b39efSVijendar Mukunda if (adata->asic_type != CHIP_STONEY) { 1331c36d9b3fSMaruthi Srinivas Bayyavarapu for (bank = 5; bank <= 8; bank++) 1332c36d9b3fSMaruthi Srinivas Bayyavarapu acp_set_sram_bank_state(adata->acp_mmio, bank, 1333c36d9b3fSMaruthi Srinivas Bayyavarapu true); 1334607b39efSVijendar Mukunda } 1335ccfbb4f5SMukunda, Vijendar rtd = adata->capture_i2ssp_stream->runtime->private_data; 1336ccfbb4f5SMukunda, Vijendar config_acp_dma(adata->acp_mmio, rtd, adata->asic_type); 1337ccfbb4f5SMukunda, Vijendar } 1338ccfbb4f5SMukunda, Vijendar if (adata->asic_type != CHIP_CARRIZO) { 1339ccfbb4f5SMukunda, Vijendar if (adata->play_i2sbt_stream && 1340ccfbb4f5SMukunda, Vijendar adata->play_i2sbt_stream->runtime) { 1341ccfbb4f5SMukunda, Vijendar rtd = adata->play_i2sbt_stream->runtime->private_data; 1342ccfbb4f5SMukunda, Vijendar config_acp_dma(adata->acp_mmio, rtd, adata->asic_type); 1343ccfbb4f5SMukunda, Vijendar } 1344ccfbb4f5SMukunda, Vijendar if (adata->capture_i2sbt_stream && 1345ccfbb4f5SMukunda, Vijendar adata->capture_i2sbt_stream->runtime) { 1346ccfbb4f5SMukunda, Vijendar rtd = adata->capture_i2sbt_stream->runtime->private_data; 1347ccfbb4f5SMukunda, Vijendar config_acp_dma(adata->acp_mmio, rtd, adata->asic_type); 1348ccfbb4f5SMukunda, Vijendar } 1349c36d9b3fSMaruthi Srinivas Bayyavarapu } 13501927da93SMaruthi Srinivas Bayyavarapu acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB); 13511927da93SMaruthi Srinivas Bayyavarapu return 0; 13521927da93SMaruthi Srinivas Bayyavarapu } 13531927da93SMaruthi Srinivas Bayyavarapu 13541927da93SMaruthi Srinivas Bayyavarapu static int acp_pcm_runtime_suspend(struct device *dev) 13551927da93SMaruthi Srinivas Bayyavarapu { 13567afa535eSMukunda, Vijendar int status; 13571927da93SMaruthi Srinivas Bayyavarapu struct audio_drv_data *adata = dev_get_drvdata(dev); 13581927da93SMaruthi Srinivas Bayyavarapu 13597afa535eSMukunda, Vijendar status = acp_deinit(adata->acp_mmio); 13607afa535eSMukunda, Vijendar if (status) 13617afa535eSMukunda, Vijendar dev_err(dev, "ACP Deinit failed status:%d\n", status); 13621927da93SMaruthi Srinivas Bayyavarapu acp_reg_write(0, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB); 13631927da93SMaruthi Srinivas Bayyavarapu return 0; 13641927da93SMaruthi Srinivas Bayyavarapu } 13651927da93SMaruthi Srinivas Bayyavarapu 13661927da93SMaruthi Srinivas Bayyavarapu static int acp_pcm_runtime_resume(struct device *dev) 13671927da93SMaruthi Srinivas Bayyavarapu { 13687afa535eSMukunda, Vijendar int status; 13691927da93SMaruthi Srinivas Bayyavarapu struct audio_drv_data *adata = dev_get_drvdata(dev); 13701927da93SMaruthi Srinivas Bayyavarapu 13717afa535eSMukunda, Vijendar status = acp_init(adata->acp_mmio, adata->asic_type); 13727afa535eSMukunda, Vijendar if (status) { 13737afa535eSMukunda, Vijendar dev_err(dev, "ACP Init failed status:%d\n", status); 13747afa535eSMukunda, Vijendar return status; 13757afa535eSMukunda, Vijendar } 13761927da93SMaruthi Srinivas Bayyavarapu acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB); 13771927da93SMaruthi Srinivas Bayyavarapu return 0; 13781927da93SMaruthi Srinivas Bayyavarapu } 13791927da93SMaruthi Srinivas Bayyavarapu 13801927da93SMaruthi Srinivas Bayyavarapu static const struct dev_pm_ops acp_pm_ops = { 13811927da93SMaruthi Srinivas Bayyavarapu .resume = acp_pcm_resume, 13821927da93SMaruthi Srinivas Bayyavarapu .runtime_suspend = acp_pcm_runtime_suspend, 13831927da93SMaruthi Srinivas Bayyavarapu .runtime_resume = acp_pcm_runtime_resume, 13841927da93SMaruthi Srinivas Bayyavarapu }; 13851927da93SMaruthi Srinivas Bayyavarapu 13867c31335aSMaruthi Srinivas Bayyavarapu static struct platform_driver acp_dma_driver = { 13877c31335aSMaruthi Srinivas Bayyavarapu .probe = acp_audio_probe, 13887c31335aSMaruthi Srinivas Bayyavarapu .remove = acp_audio_remove, 13897c31335aSMaruthi Srinivas Bayyavarapu .driver = { 1390bdd2a858SAkshu Agrawal .name = DRV_NAME, 13911927da93SMaruthi Srinivas Bayyavarapu .pm = &acp_pm_ops, 13927c31335aSMaruthi Srinivas Bayyavarapu }, 13937c31335aSMaruthi Srinivas Bayyavarapu }; 13947c31335aSMaruthi Srinivas Bayyavarapu 13957c31335aSMaruthi Srinivas Bayyavarapu module_platform_driver(acp_dma_driver); 13967c31335aSMaruthi Srinivas Bayyavarapu 1397607b39efSVijendar Mukunda MODULE_AUTHOR("Vijendar.Mukunda@amd.com"); 13987c31335aSMaruthi Srinivas Bayyavarapu MODULE_AUTHOR("Maruthi.Bayyavarapu@amd.com"); 13997c31335aSMaruthi Srinivas Bayyavarapu MODULE_DESCRIPTION("AMD ACP PCM Driver"); 14007c31335aSMaruthi Srinivas Bayyavarapu MODULE_LICENSE("GPL v2"); 1401bdd2a858SAkshu Agrawal MODULE_ALIAS("platform:"DRV_NAME); 1402