17c31335aSMaruthi Srinivas Bayyavarapu /* 27c31335aSMaruthi Srinivas Bayyavarapu * AMD ALSA SoC PCM Driver for ACP 2.x 37c31335aSMaruthi Srinivas Bayyavarapu * 47c31335aSMaruthi Srinivas Bayyavarapu * Copyright 2014-2015 Advanced Micro Devices, Inc. 57c31335aSMaruthi Srinivas Bayyavarapu * 67c31335aSMaruthi Srinivas Bayyavarapu * This program is free software; you can redistribute it and/or modify it 77c31335aSMaruthi Srinivas Bayyavarapu * under the terms and conditions of the GNU General Public License, 87c31335aSMaruthi Srinivas Bayyavarapu * version 2, as published by the Free Software Foundation. 97c31335aSMaruthi Srinivas Bayyavarapu * 107c31335aSMaruthi Srinivas Bayyavarapu * This program is distributed in the hope it will be useful, but WITHOUT 117c31335aSMaruthi Srinivas Bayyavarapu * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 127c31335aSMaruthi Srinivas Bayyavarapu * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 137c31335aSMaruthi Srinivas Bayyavarapu * more details. 147c31335aSMaruthi Srinivas Bayyavarapu */ 157c31335aSMaruthi Srinivas Bayyavarapu 167c31335aSMaruthi Srinivas Bayyavarapu #include <linux/module.h> 177c31335aSMaruthi Srinivas Bayyavarapu #include <linux/delay.h> 187cb1dc81SGuenter Roeck #include <linux/io.h> 197c31335aSMaruthi Srinivas Bayyavarapu #include <linux/sizes.h> 201927da93SMaruthi Srinivas Bayyavarapu #include <linux/pm_runtime.h> 217c31335aSMaruthi Srinivas Bayyavarapu 227c31335aSMaruthi Srinivas Bayyavarapu #include <sound/soc.h> 23607b39efSVijendar Mukunda #include <drm/amd_asic_type.h> 247c31335aSMaruthi Srinivas Bayyavarapu #include "acp.h" 257c31335aSMaruthi Srinivas Bayyavarapu 267c31335aSMaruthi Srinivas Bayyavarapu #define PLAYBACK_MIN_NUM_PERIODS 2 277c31335aSMaruthi Srinivas Bayyavarapu #define PLAYBACK_MAX_NUM_PERIODS 2 287c31335aSMaruthi Srinivas Bayyavarapu #define PLAYBACK_MAX_PERIOD_SIZE 16384 297c31335aSMaruthi Srinivas Bayyavarapu #define PLAYBACK_MIN_PERIOD_SIZE 1024 307c31335aSMaruthi Srinivas Bayyavarapu #define CAPTURE_MIN_NUM_PERIODS 2 317c31335aSMaruthi Srinivas Bayyavarapu #define CAPTURE_MAX_NUM_PERIODS 2 327c31335aSMaruthi Srinivas Bayyavarapu #define CAPTURE_MAX_PERIOD_SIZE 16384 337c31335aSMaruthi Srinivas Bayyavarapu #define CAPTURE_MIN_PERIOD_SIZE 1024 347c31335aSMaruthi Srinivas Bayyavarapu 357c31335aSMaruthi Srinivas Bayyavarapu #define MAX_BUFFER (PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS) 367c31335aSMaruthi Srinivas Bayyavarapu #define MIN_BUFFER MAX_BUFFER 377c31335aSMaruthi Srinivas Bayyavarapu 389c7d6fabSVijendar Mukunda #define ST_PLAYBACK_MAX_PERIOD_SIZE 8192 399c7d6fabSVijendar Mukunda #define ST_CAPTURE_MAX_PERIOD_SIZE ST_PLAYBACK_MAX_PERIOD_SIZE 409c7d6fabSVijendar Mukunda #define ST_MAX_BUFFER (ST_PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS) 419c7d6fabSVijendar Mukunda #define ST_MIN_BUFFER ST_MAX_BUFFER 429c7d6fabSVijendar Mukunda 43bdd2a858SAkshu Agrawal #define DRV_NAME "acp_audio_dma" 44bdd2a858SAkshu Agrawal 457c31335aSMaruthi Srinivas Bayyavarapu static const struct snd_pcm_hardware acp_pcm_hardware_playback = { 467c31335aSMaruthi Srinivas Bayyavarapu .info = SNDRV_PCM_INFO_INTERLEAVED | 477c31335aSMaruthi Srinivas Bayyavarapu SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP | 487c31335aSMaruthi Srinivas Bayyavarapu SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH | 497c31335aSMaruthi Srinivas Bayyavarapu SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME, 507c31335aSMaruthi Srinivas Bayyavarapu .formats = SNDRV_PCM_FMTBIT_S16_LE | 517c31335aSMaruthi Srinivas Bayyavarapu SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, 527c31335aSMaruthi Srinivas Bayyavarapu .channels_min = 1, 537c31335aSMaruthi Srinivas Bayyavarapu .channels_max = 8, 547c31335aSMaruthi Srinivas Bayyavarapu .rates = SNDRV_PCM_RATE_8000_96000, 557c31335aSMaruthi Srinivas Bayyavarapu .rate_min = 8000, 567c31335aSMaruthi Srinivas Bayyavarapu .rate_max = 96000, 577c31335aSMaruthi Srinivas Bayyavarapu .buffer_bytes_max = PLAYBACK_MAX_NUM_PERIODS * PLAYBACK_MAX_PERIOD_SIZE, 587c31335aSMaruthi Srinivas Bayyavarapu .period_bytes_min = PLAYBACK_MIN_PERIOD_SIZE, 597c31335aSMaruthi Srinivas Bayyavarapu .period_bytes_max = PLAYBACK_MAX_PERIOD_SIZE, 607c31335aSMaruthi Srinivas Bayyavarapu .periods_min = PLAYBACK_MIN_NUM_PERIODS, 617c31335aSMaruthi Srinivas Bayyavarapu .periods_max = PLAYBACK_MAX_NUM_PERIODS, 627c31335aSMaruthi Srinivas Bayyavarapu }; 637c31335aSMaruthi Srinivas Bayyavarapu 647c31335aSMaruthi Srinivas Bayyavarapu static const struct snd_pcm_hardware acp_pcm_hardware_capture = { 657c31335aSMaruthi Srinivas Bayyavarapu .info = SNDRV_PCM_INFO_INTERLEAVED | 667c31335aSMaruthi Srinivas Bayyavarapu SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP | 677c31335aSMaruthi Srinivas Bayyavarapu SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH | 687c31335aSMaruthi Srinivas Bayyavarapu SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME, 697c31335aSMaruthi Srinivas Bayyavarapu .formats = SNDRV_PCM_FMTBIT_S16_LE | 707c31335aSMaruthi Srinivas Bayyavarapu SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, 717c31335aSMaruthi Srinivas Bayyavarapu .channels_min = 1, 727c31335aSMaruthi Srinivas Bayyavarapu .channels_max = 2, 737c31335aSMaruthi Srinivas Bayyavarapu .rates = SNDRV_PCM_RATE_8000_48000, 747c31335aSMaruthi Srinivas Bayyavarapu .rate_min = 8000, 757c31335aSMaruthi Srinivas Bayyavarapu .rate_max = 48000, 767c31335aSMaruthi Srinivas Bayyavarapu .buffer_bytes_max = CAPTURE_MAX_NUM_PERIODS * CAPTURE_MAX_PERIOD_SIZE, 777c31335aSMaruthi Srinivas Bayyavarapu .period_bytes_min = CAPTURE_MIN_PERIOD_SIZE, 787c31335aSMaruthi Srinivas Bayyavarapu .period_bytes_max = CAPTURE_MAX_PERIOD_SIZE, 797c31335aSMaruthi Srinivas Bayyavarapu .periods_min = CAPTURE_MIN_NUM_PERIODS, 807c31335aSMaruthi Srinivas Bayyavarapu .periods_max = CAPTURE_MAX_NUM_PERIODS, 817c31335aSMaruthi Srinivas Bayyavarapu }; 827c31335aSMaruthi Srinivas Bayyavarapu 839c7d6fabSVijendar Mukunda static const struct snd_pcm_hardware acp_st_pcm_hardware_playback = { 849c7d6fabSVijendar Mukunda .info = SNDRV_PCM_INFO_INTERLEAVED | 859c7d6fabSVijendar Mukunda SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP | 869c7d6fabSVijendar Mukunda SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH | 879c7d6fabSVijendar Mukunda SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME, 889c7d6fabSVijendar Mukunda .formats = SNDRV_PCM_FMTBIT_S16_LE | 899c7d6fabSVijendar Mukunda SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, 909c7d6fabSVijendar Mukunda .channels_min = 1, 919c7d6fabSVijendar Mukunda .channels_max = 8, 929c7d6fabSVijendar Mukunda .rates = SNDRV_PCM_RATE_8000_96000, 939c7d6fabSVijendar Mukunda .rate_min = 8000, 949c7d6fabSVijendar Mukunda .rate_max = 96000, 959c7d6fabSVijendar Mukunda .buffer_bytes_max = ST_MAX_BUFFER, 969c7d6fabSVijendar Mukunda .period_bytes_min = PLAYBACK_MIN_PERIOD_SIZE, 979c7d6fabSVijendar Mukunda .period_bytes_max = ST_PLAYBACK_MAX_PERIOD_SIZE, 989c7d6fabSVijendar Mukunda .periods_min = PLAYBACK_MIN_NUM_PERIODS, 999c7d6fabSVijendar Mukunda .periods_max = PLAYBACK_MAX_NUM_PERIODS, 1009c7d6fabSVijendar Mukunda }; 1019c7d6fabSVijendar Mukunda 1029c7d6fabSVijendar Mukunda static const struct snd_pcm_hardware acp_st_pcm_hardware_capture = { 1039c7d6fabSVijendar Mukunda .info = SNDRV_PCM_INFO_INTERLEAVED | 1049c7d6fabSVijendar Mukunda SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP | 1059c7d6fabSVijendar Mukunda SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH | 1069c7d6fabSVijendar Mukunda SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME, 1079c7d6fabSVijendar Mukunda .formats = SNDRV_PCM_FMTBIT_S16_LE | 1089c7d6fabSVijendar Mukunda SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, 1099c7d6fabSVijendar Mukunda .channels_min = 1, 1109c7d6fabSVijendar Mukunda .channels_max = 2, 1119c7d6fabSVijendar Mukunda .rates = SNDRV_PCM_RATE_8000_48000, 1129c7d6fabSVijendar Mukunda .rate_min = 8000, 1139c7d6fabSVijendar Mukunda .rate_max = 48000, 1149c7d6fabSVijendar Mukunda .buffer_bytes_max = ST_MAX_BUFFER, 1159c7d6fabSVijendar Mukunda .period_bytes_min = CAPTURE_MIN_PERIOD_SIZE, 1169c7d6fabSVijendar Mukunda .period_bytes_max = ST_CAPTURE_MAX_PERIOD_SIZE, 1179c7d6fabSVijendar Mukunda .periods_min = CAPTURE_MIN_NUM_PERIODS, 1189c7d6fabSVijendar Mukunda .periods_max = CAPTURE_MAX_NUM_PERIODS, 1199c7d6fabSVijendar Mukunda }; 1209c7d6fabSVijendar Mukunda 1217c31335aSMaruthi Srinivas Bayyavarapu static u32 acp_reg_read(void __iomem *acp_mmio, u32 reg) 1227c31335aSMaruthi Srinivas Bayyavarapu { 1237c31335aSMaruthi Srinivas Bayyavarapu return readl(acp_mmio + (reg * 4)); 1247c31335aSMaruthi Srinivas Bayyavarapu } 1257c31335aSMaruthi Srinivas Bayyavarapu 1267c31335aSMaruthi Srinivas Bayyavarapu static void acp_reg_write(u32 val, void __iomem *acp_mmio, u32 reg) 1277c31335aSMaruthi Srinivas Bayyavarapu { 1287c31335aSMaruthi Srinivas Bayyavarapu writel(val, acp_mmio + (reg * 4)); 1297c31335aSMaruthi Srinivas Bayyavarapu } 1307c31335aSMaruthi Srinivas Bayyavarapu 1318a1115ffSMasahiro Yamada /* Configure a given dma channel parameters - enable/disable, 1327c31335aSMaruthi Srinivas Bayyavarapu * number of descriptors, priority 1337c31335aSMaruthi Srinivas Bayyavarapu */ 1347c31335aSMaruthi Srinivas Bayyavarapu static void config_acp_dma_channel(void __iomem *acp_mmio, u8 ch_num, 1357c31335aSMaruthi Srinivas Bayyavarapu u16 dscr_strt_idx, u16 num_dscrs, 1367c31335aSMaruthi Srinivas Bayyavarapu enum acp_dma_priority_level priority_level) 1377c31335aSMaruthi Srinivas Bayyavarapu { 1387c31335aSMaruthi Srinivas Bayyavarapu u32 dma_ctrl; 1397c31335aSMaruthi Srinivas Bayyavarapu 1407c31335aSMaruthi Srinivas Bayyavarapu /* disable the channel run field */ 1417c31335aSMaruthi Srinivas Bayyavarapu dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 1427c31335aSMaruthi Srinivas Bayyavarapu dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRun_MASK; 1437c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 1447c31335aSMaruthi Srinivas Bayyavarapu 1457c31335aSMaruthi Srinivas Bayyavarapu /* program a DMA channel with first descriptor to be processed. */ 1467c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write((ACP_DMA_DSCR_STRT_IDX_0__DMAChDscrStrtIdx_MASK 1477c31335aSMaruthi Srinivas Bayyavarapu & dscr_strt_idx), 1487c31335aSMaruthi Srinivas Bayyavarapu acp_mmio, mmACP_DMA_DSCR_STRT_IDX_0 + ch_num); 1497c31335aSMaruthi Srinivas Bayyavarapu 1507c31335aSMaruthi Srinivas Bayyavarapu /* program a DMA channel with the number of descriptors to be 1517c31335aSMaruthi Srinivas Bayyavarapu * processed in the transfer 1527c31335aSMaruthi Srinivas Bayyavarapu */ 1537c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(ACP_DMA_DSCR_CNT_0__DMAChDscrCnt_MASK & num_dscrs, 1547c31335aSMaruthi Srinivas Bayyavarapu acp_mmio, mmACP_DMA_DSCR_CNT_0 + ch_num); 1557c31335aSMaruthi Srinivas Bayyavarapu 1567c31335aSMaruthi Srinivas Bayyavarapu /* set DMA channel priority */ 1577c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(priority_level, acp_mmio, mmACP_DMA_PRIO_0 + ch_num); 1587c31335aSMaruthi Srinivas Bayyavarapu } 1597c31335aSMaruthi Srinivas Bayyavarapu 1607c31335aSMaruthi Srinivas Bayyavarapu /* Initialize a dma descriptor in SRAM based on descritor information passed */ 1617c31335aSMaruthi Srinivas Bayyavarapu static void config_dma_descriptor_in_sram(void __iomem *acp_mmio, 1627c31335aSMaruthi Srinivas Bayyavarapu u16 descr_idx, 1637c31335aSMaruthi Srinivas Bayyavarapu acp_dma_dscr_transfer_t *descr_info) 1647c31335aSMaruthi Srinivas Bayyavarapu { 1657c31335aSMaruthi Srinivas Bayyavarapu u32 sram_offset; 1667c31335aSMaruthi Srinivas Bayyavarapu 1677c31335aSMaruthi Srinivas Bayyavarapu sram_offset = (descr_idx * sizeof(acp_dma_dscr_transfer_t)); 1687c31335aSMaruthi Srinivas Bayyavarapu 1697c31335aSMaruthi Srinivas Bayyavarapu /* program the source base address. */ 1707c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(sram_offset, acp_mmio, mmACP_SRBM_Targ_Idx_Addr); 1717c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(descr_info->src, acp_mmio, mmACP_SRBM_Targ_Idx_Data); 1727c31335aSMaruthi Srinivas Bayyavarapu /* program the destination base address. */ 1737c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(sram_offset + 4, acp_mmio, mmACP_SRBM_Targ_Idx_Addr); 1747c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(descr_info->dest, acp_mmio, mmACP_SRBM_Targ_Idx_Data); 1757c31335aSMaruthi Srinivas Bayyavarapu 1767c31335aSMaruthi Srinivas Bayyavarapu /* program the number of bytes to be transferred for this descriptor. */ 1777c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(sram_offset + 8, acp_mmio, mmACP_SRBM_Targ_Idx_Addr); 1787c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(descr_info->xfer_val, acp_mmio, mmACP_SRBM_Targ_Idx_Data); 1797c31335aSMaruthi Srinivas Bayyavarapu } 1807c31335aSMaruthi Srinivas Bayyavarapu 1817c31335aSMaruthi Srinivas Bayyavarapu /* Initialize the DMA descriptor information for transfer between 1827c31335aSMaruthi Srinivas Bayyavarapu * system memory <-> ACP SRAM 1837c31335aSMaruthi Srinivas Bayyavarapu */ 1847c31335aSMaruthi Srinivas Bayyavarapu static void set_acp_sysmem_dma_descriptors(void __iomem *acp_mmio, 1857c31335aSMaruthi Srinivas Bayyavarapu u32 size, int direction, 186aac89748SVijendar Mukunda u32 pte_offset, u32 asic_type) 1877c31335aSMaruthi Srinivas Bayyavarapu { 1887c31335aSMaruthi Srinivas Bayyavarapu u16 i; 1897c31335aSMaruthi Srinivas Bayyavarapu u16 dma_dscr_idx = PLAYBACK_START_DMA_DESCR_CH12; 1907c31335aSMaruthi Srinivas Bayyavarapu acp_dma_dscr_transfer_t dmadscr[NUM_DSCRS_PER_CHANNEL]; 1917c31335aSMaruthi Srinivas Bayyavarapu 1927c31335aSMaruthi Srinivas Bayyavarapu for (i = 0; i < NUM_DSCRS_PER_CHANNEL; i++) { 1937c31335aSMaruthi Srinivas Bayyavarapu dmadscr[i].xfer_val = 0; 1947c31335aSMaruthi Srinivas Bayyavarapu if (direction == SNDRV_PCM_STREAM_PLAYBACK) { 1957c31335aSMaruthi Srinivas Bayyavarapu dma_dscr_idx = PLAYBACK_START_DMA_DESCR_CH12 + i; 19631c45b3eSVijendar Mukunda dmadscr[i].dest = ACP_SHARED_RAM_BANK_1_ADDRESS 19731c45b3eSVijendar Mukunda + (i * (size/2)); 1987c31335aSMaruthi Srinivas Bayyavarapu dmadscr[i].src = ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS 1997c31335aSMaruthi Srinivas Bayyavarapu + (pte_offset * SZ_4K) + (i * (size/2)); 200aac89748SVijendar Mukunda switch (asic_type) { 201aac89748SVijendar Mukunda case CHIP_STONEY: 202aac89748SVijendar Mukunda dmadscr[i].xfer_val |= 203aac89748SVijendar Mukunda (ACP_DMA_ATTRIBUTES_DAGB_GARLIC_TO_SHAREDMEM << 16) | 204aac89748SVijendar Mukunda (size / 2); 205aac89748SVijendar Mukunda break; 206aac89748SVijendar Mukunda default: 2077c31335aSMaruthi Srinivas Bayyavarapu dmadscr[i].xfer_val |= 2087c31335aSMaruthi Srinivas Bayyavarapu (ACP_DMA_ATTRIBUTES_DAGB_ONION_TO_SHAREDMEM << 16) | 2097c31335aSMaruthi Srinivas Bayyavarapu (size / 2); 210aac89748SVijendar Mukunda } 2117c31335aSMaruthi Srinivas Bayyavarapu } else { 2127c31335aSMaruthi Srinivas Bayyavarapu dma_dscr_idx = CAPTURE_START_DMA_DESCR_CH14 + i; 213aac89748SVijendar Mukunda switch (asic_type) { 214aac89748SVijendar Mukunda case CHIP_STONEY: 215aac89748SVijendar Mukunda dmadscr[i].src = ACP_SHARED_RAM_BANK_3_ADDRESS + 216aac89748SVijendar Mukunda (i * (size/2)); 217aac89748SVijendar Mukunda dmadscr[i].dest = 218aac89748SVijendar Mukunda ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS + 219aac89748SVijendar Mukunda (pte_offset * SZ_4K) + (i * (size/2)); 220aac89748SVijendar Mukunda dmadscr[i].xfer_val |= 221aac89748SVijendar Mukunda BIT(22) | 222aac89748SVijendar Mukunda (ACP_DMA_ATTRIBUTES_SHARED_MEM_TO_DAGB_GARLIC << 16) | 223aac89748SVijendar Mukunda (size / 2); 224aac89748SVijendar Mukunda break; 225aac89748SVijendar Mukunda default: 2267c31335aSMaruthi Srinivas Bayyavarapu dmadscr[i].src = ACP_SHARED_RAM_BANK_5_ADDRESS + 2277c31335aSMaruthi Srinivas Bayyavarapu (i * (size/2)); 228aac89748SVijendar Mukunda dmadscr[i].dest = 229aac89748SVijendar Mukunda ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS + 230aac89748SVijendar Mukunda (pte_offset * SZ_4K) + (i * (size/2)); 2317c31335aSMaruthi Srinivas Bayyavarapu dmadscr[i].xfer_val |= 2327c31335aSMaruthi Srinivas Bayyavarapu BIT(22) | 2337c31335aSMaruthi Srinivas Bayyavarapu (ACP_DMA_ATTRIBUTES_SHAREDMEM_TO_DAGB_ONION << 16) | 2347c31335aSMaruthi Srinivas Bayyavarapu (size / 2); 2357c31335aSMaruthi Srinivas Bayyavarapu } 236aac89748SVijendar Mukunda } 2377c31335aSMaruthi Srinivas Bayyavarapu config_dma_descriptor_in_sram(acp_mmio, dma_dscr_idx, 2387c31335aSMaruthi Srinivas Bayyavarapu &dmadscr[i]); 2397c31335aSMaruthi Srinivas Bayyavarapu } 2407c31335aSMaruthi Srinivas Bayyavarapu if (direction == SNDRV_PCM_STREAM_PLAYBACK) 2417c31335aSMaruthi Srinivas Bayyavarapu config_acp_dma_channel(acp_mmio, SYSRAM_TO_ACP_CH_NUM, 2427c31335aSMaruthi Srinivas Bayyavarapu PLAYBACK_START_DMA_DESCR_CH12, 2437c31335aSMaruthi Srinivas Bayyavarapu NUM_DSCRS_PER_CHANNEL, 2447c31335aSMaruthi Srinivas Bayyavarapu ACP_DMA_PRIORITY_LEVEL_NORMAL); 2457c31335aSMaruthi Srinivas Bayyavarapu else 2467c31335aSMaruthi Srinivas Bayyavarapu config_acp_dma_channel(acp_mmio, ACP_TO_SYSRAM_CH_NUM, 2477c31335aSMaruthi Srinivas Bayyavarapu CAPTURE_START_DMA_DESCR_CH14, 2487c31335aSMaruthi Srinivas Bayyavarapu NUM_DSCRS_PER_CHANNEL, 2497c31335aSMaruthi Srinivas Bayyavarapu ACP_DMA_PRIORITY_LEVEL_NORMAL); 2507c31335aSMaruthi Srinivas Bayyavarapu } 2517c31335aSMaruthi Srinivas Bayyavarapu 2527c31335aSMaruthi Srinivas Bayyavarapu /* Initialize the DMA descriptor information for transfer between 2537c31335aSMaruthi Srinivas Bayyavarapu * ACP SRAM <-> I2S 2547c31335aSMaruthi Srinivas Bayyavarapu */ 2557c31335aSMaruthi Srinivas Bayyavarapu static void set_acp_to_i2s_dma_descriptors(void __iomem *acp_mmio, 256aac89748SVijendar Mukunda u32 size, int direction, 257aac89748SVijendar Mukunda u32 asic_type) 2587c31335aSMaruthi Srinivas Bayyavarapu { 2597c31335aSMaruthi Srinivas Bayyavarapu 2607c31335aSMaruthi Srinivas Bayyavarapu u16 i; 2617c31335aSMaruthi Srinivas Bayyavarapu u16 dma_dscr_idx = PLAYBACK_START_DMA_DESCR_CH13; 2627c31335aSMaruthi Srinivas Bayyavarapu acp_dma_dscr_transfer_t dmadscr[NUM_DSCRS_PER_CHANNEL]; 2637c31335aSMaruthi Srinivas Bayyavarapu 2647c31335aSMaruthi Srinivas Bayyavarapu for (i = 0; i < NUM_DSCRS_PER_CHANNEL; i++) { 2657c31335aSMaruthi Srinivas Bayyavarapu dmadscr[i].xfer_val = 0; 2667c31335aSMaruthi Srinivas Bayyavarapu if (direction == SNDRV_PCM_STREAM_PLAYBACK) { 2677c31335aSMaruthi Srinivas Bayyavarapu dma_dscr_idx = PLAYBACK_START_DMA_DESCR_CH13 + i; 2687c31335aSMaruthi Srinivas Bayyavarapu dmadscr[i].src = ACP_SHARED_RAM_BANK_1_ADDRESS + 2697c31335aSMaruthi Srinivas Bayyavarapu (i * (size/2)); 2707c31335aSMaruthi Srinivas Bayyavarapu /* dmadscr[i].dest is unused by hardware. */ 2717c31335aSMaruthi Srinivas Bayyavarapu dmadscr[i].dest = 0; 2727c31335aSMaruthi Srinivas Bayyavarapu dmadscr[i].xfer_val |= BIT(22) | (TO_ACP_I2S_1 << 16) | 2737c31335aSMaruthi Srinivas Bayyavarapu (size / 2); 2747c31335aSMaruthi Srinivas Bayyavarapu } else { 2757c31335aSMaruthi Srinivas Bayyavarapu dma_dscr_idx = CAPTURE_START_DMA_DESCR_CH15 + i; 2767c31335aSMaruthi Srinivas Bayyavarapu /* dmadscr[i].src is unused by hardware. */ 2777c31335aSMaruthi Srinivas Bayyavarapu dmadscr[i].src = 0; 278aac89748SVijendar Mukunda switch (asic_type) { 279aac89748SVijendar Mukunda case CHIP_STONEY: 280aac89748SVijendar Mukunda dmadscr[i].dest = 281aac89748SVijendar Mukunda ACP_SHARED_RAM_BANK_3_ADDRESS + 2827c31335aSMaruthi Srinivas Bayyavarapu (i * (size / 2)); 283aac89748SVijendar Mukunda break; 284aac89748SVijendar Mukunda default: 285aac89748SVijendar Mukunda dmadscr[i].dest = 286aac89748SVijendar Mukunda ACP_SHARED_RAM_BANK_5_ADDRESS + 287aac89748SVijendar Mukunda (i * (size / 2)); 288aac89748SVijendar Mukunda } 2897c31335aSMaruthi Srinivas Bayyavarapu dmadscr[i].xfer_val |= BIT(22) | 2907c31335aSMaruthi Srinivas Bayyavarapu (FROM_ACP_I2S_1 << 16) | (size / 2); 2917c31335aSMaruthi Srinivas Bayyavarapu } 2927c31335aSMaruthi Srinivas Bayyavarapu config_dma_descriptor_in_sram(acp_mmio, dma_dscr_idx, 2937c31335aSMaruthi Srinivas Bayyavarapu &dmadscr[i]); 2947c31335aSMaruthi Srinivas Bayyavarapu } 2957c31335aSMaruthi Srinivas Bayyavarapu /* Configure the DMA channel with the above descriptore */ 2967c31335aSMaruthi Srinivas Bayyavarapu if (direction == SNDRV_PCM_STREAM_PLAYBACK) 2977c31335aSMaruthi Srinivas Bayyavarapu config_acp_dma_channel(acp_mmio, ACP_TO_I2S_DMA_CH_NUM, 2987c31335aSMaruthi Srinivas Bayyavarapu PLAYBACK_START_DMA_DESCR_CH13, 2997c31335aSMaruthi Srinivas Bayyavarapu NUM_DSCRS_PER_CHANNEL, 3007c31335aSMaruthi Srinivas Bayyavarapu ACP_DMA_PRIORITY_LEVEL_NORMAL); 3017c31335aSMaruthi Srinivas Bayyavarapu else 3027c31335aSMaruthi Srinivas Bayyavarapu config_acp_dma_channel(acp_mmio, I2S_TO_ACP_DMA_CH_NUM, 3037c31335aSMaruthi Srinivas Bayyavarapu CAPTURE_START_DMA_DESCR_CH15, 3047c31335aSMaruthi Srinivas Bayyavarapu NUM_DSCRS_PER_CHANNEL, 3057c31335aSMaruthi Srinivas Bayyavarapu ACP_DMA_PRIORITY_LEVEL_NORMAL); 3067c31335aSMaruthi Srinivas Bayyavarapu } 3077c31335aSMaruthi Srinivas Bayyavarapu 3087c31335aSMaruthi Srinivas Bayyavarapu /* Create page table entries in ACP SRAM for the allocated memory */ 3097c31335aSMaruthi Srinivas Bayyavarapu static void acp_pte_config(void __iomem *acp_mmio, struct page *pg, 3107c31335aSMaruthi Srinivas Bayyavarapu u16 num_of_pages, u32 pte_offset) 3117c31335aSMaruthi Srinivas Bayyavarapu { 3127c31335aSMaruthi Srinivas Bayyavarapu u16 page_idx; 3137c31335aSMaruthi Srinivas Bayyavarapu u64 addr; 3147c31335aSMaruthi Srinivas Bayyavarapu u32 low; 3157c31335aSMaruthi Srinivas Bayyavarapu u32 high; 3167c31335aSMaruthi Srinivas Bayyavarapu u32 offset; 3177c31335aSMaruthi Srinivas Bayyavarapu 3187c31335aSMaruthi Srinivas Bayyavarapu offset = ACP_DAGB_GRP_SRBM_SRAM_BASE_OFFSET + (pte_offset * 8); 3197c31335aSMaruthi Srinivas Bayyavarapu for (page_idx = 0; page_idx < (num_of_pages); page_idx++) { 3207c31335aSMaruthi Srinivas Bayyavarapu /* Load the low address of page int ACP SRAM through SRBM */ 3217c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write((offset + (page_idx * 8)), 3227c31335aSMaruthi Srinivas Bayyavarapu acp_mmio, mmACP_SRBM_Targ_Idx_Addr); 3237c31335aSMaruthi Srinivas Bayyavarapu addr = page_to_phys(pg); 3247c31335aSMaruthi Srinivas Bayyavarapu 3257c31335aSMaruthi Srinivas Bayyavarapu low = lower_32_bits(addr); 3267c31335aSMaruthi Srinivas Bayyavarapu high = upper_32_bits(addr); 3277c31335aSMaruthi Srinivas Bayyavarapu 3287c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(low, acp_mmio, mmACP_SRBM_Targ_Idx_Data); 3297c31335aSMaruthi Srinivas Bayyavarapu 3307c31335aSMaruthi Srinivas Bayyavarapu /* Load the High address of page int ACP SRAM through SRBM */ 3317c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write((offset + (page_idx * 8) + 4), 3327c31335aSMaruthi Srinivas Bayyavarapu acp_mmio, mmACP_SRBM_Targ_Idx_Addr); 3337c31335aSMaruthi Srinivas Bayyavarapu 3347c31335aSMaruthi Srinivas Bayyavarapu /* page enable in ACP */ 3357c31335aSMaruthi Srinivas Bayyavarapu high |= BIT(31); 3367c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(high, acp_mmio, mmACP_SRBM_Targ_Idx_Data); 3377c31335aSMaruthi Srinivas Bayyavarapu 3387c31335aSMaruthi Srinivas Bayyavarapu /* Move to next physically contiguos page */ 3397c31335aSMaruthi Srinivas Bayyavarapu pg++; 3407c31335aSMaruthi Srinivas Bayyavarapu } 3417c31335aSMaruthi Srinivas Bayyavarapu } 3427c31335aSMaruthi Srinivas Bayyavarapu 3437c31335aSMaruthi Srinivas Bayyavarapu static void config_acp_dma(void __iomem *acp_mmio, 344aac89748SVijendar Mukunda struct audio_substream_data *audio_config, 345aac89748SVijendar Mukunda u32 asic_type) 3467c31335aSMaruthi Srinivas Bayyavarapu { 3477c31335aSMaruthi Srinivas Bayyavarapu u32 pte_offset; 3487c31335aSMaruthi Srinivas Bayyavarapu 3497c31335aSMaruthi Srinivas Bayyavarapu if (audio_config->direction == SNDRV_PCM_STREAM_PLAYBACK) 3507c31335aSMaruthi Srinivas Bayyavarapu pte_offset = ACP_PLAYBACK_PTE_OFFSET; 3517c31335aSMaruthi Srinivas Bayyavarapu else 3527c31335aSMaruthi Srinivas Bayyavarapu pte_offset = ACP_CAPTURE_PTE_OFFSET; 3537c31335aSMaruthi Srinivas Bayyavarapu 3547c31335aSMaruthi Srinivas Bayyavarapu acp_pte_config(acp_mmio, audio_config->pg, audio_config->num_of_pages, 3557c31335aSMaruthi Srinivas Bayyavarapu pte_offset); 3567c31335aSMaruthi Srinivas Bayyavarapu 3577c31335aSMaruthi Srinivas Bayyavarapu /* Configure System memory <-> ACP SRAM DMA descriptors */ 3587c31335aSMaruthi Srinivas Bayyavarapu set_acp_sysmem_dma_descriptors(acp_mmio, audio_config->size, 359aac89748SVijendar Mukunda audio_config->direction, pte_offset, asic_type); 3607c31335aSMaruthi Srinivas Bayyavarapu 3617c31335aSMaruthi Srinivas Bayyavarapu /* Configure ACP SRAM <-> I2S DMA descriptors */ 3627c31335aSMaruthi Srinivas Bayyavarapu set_acp_to_i2s_dma_descriptors(acp_mmio, audio_config->size, 363aac89748SVijendar Mukunda audio_config->direction, asic_type); 3647c31335aSMaruthi Srinivas Bayyavarapu } 3657c31335aSMaruthi Srinivas Bayyavarapu 3667c31335aSMaruthi Srinivas Bayyavarapu /* Start a given DMA channel transfer */ 3677c31335aSMaruthi Srinivas Bayyavarapu static void acp_dma_start(void __iomem *acp_mmio, 3687c31335aSMaruthi Srinivas Bayyavarapu u16 ch_num, bool is_circular) 3697c31335aSMaruthi Srinivas Bayyavarapu { 3707c31335aSMaruthi Srinivas Bayyavarapu u32 dma_ctrl; 3717c31335aSMaruthi Srinivas Bayyavarapu 3727c31335aSMaruthi Srinivas Bayyavarapu /* read the dma control register and disable the channel run field */ 3737c31335aSMaruthi Srinivas Bayyavarapu dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 3747c31335aSMaruthi Srinivas Bayyavarapu 3757c31335aSMaruthi Srinivas Bayyavarapu /* Invalidating the DAGB cache */ 3767c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(1, acp_mmio, mmACP_DAGB_ATU_CTRL); 3777c31335aSMaruthi Srinivas Bayyavarapu 3787c31335aSMaruthi Srinivas Bayyavarapu /* configure the DMA channel and start the DMA transfer 3797c31335aSMaruthi Srinivas Bayyavarapu * set dmachrun bit to start the transfer and enable the 3807c31335aSMaruthi Srinivas Bayyavarapu * interrupt on completion of the dma transfer 3817c31335aSMaruthi Srinivas Bayyavarapu */ 3827c31335aSMaruthi Srinivas Bayyavarapu dma_ctrl |= ACP_DMA_CNTL_0__DMAChRun_MASK; 3837c31335aSMaruthi Srinivas Bayyavarapu 3847c31335aSMaruthi Srinivas Bayyavarapu switch (ch_num) { 3857c31335aSMaruthi Srinivas Bayyavarapu case ACP_TO_I2S_DMA_CH_NUM: 3867c31335aSMaruthi Srinivas Bayyavarapu case ACP_TO_SYSRAM_CH_NUM: 3877c31335aSMaruthi Srinivas Bayyavarapu case I2S_TO_ACP_DMA_CH_NUM: 3887c31335aSMaruthi Srinivas Bayyavarapu dma_ctrl |= ACP_DMA_CNTL_0__DMAChIOCEn_MASK; 3897c31335aSMaruthi Srinivas Bayyavarapu break; 3907c31335aSMaruthi Srinivas Bayyavarapu default: 3917c31335aSMaruthi Srinivas Bayyavarapu dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChIOCEn_MASK; 3927c31335aSMaruthi Srinivas Bayyavarapu break; 3937c31335aSMaruthi Srinivas Bayyavarapu } 3947c31335aSMaruthi Srinivas Bayyavarapu 3957c31335aSMaruthi Srinivas Bayyavarapu /* enable for ACP SRAM to/from I2S DMA channel */ 3967c31335aSMaruthi Srinivas Bayyavarapu if (is_circular == true) 3977c31335aSMaruthi Srinivas Bayyavarapu dma_ctrl |= ACP_DMA_CNTL_0__Circular_DMA_En_MASK; 3987c31335aSMaruthi Srinivas Bayyavarapu else 3997c31335aSMaruthi Srinivas Bayyavarapu dma_ctrl &= ~ACP_DMA_CNTL_0__Circular_DMA_En_MASK; 4007c31335aSMaruthi Srinivas Bayyavarapu 4017c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 4027c31335aSMaruthi Srinivas Bayyavarapu } 4037c31335aSMaruthi Srinivas Bayyavarapu 4047c31335aSMaruthi Srinivas Bayyavarapu /* Stop a given DMA channel transfer */ 4057c31335aSMaruthi Srinivas Bayyavarapu static int acp_dma_stop(void __iomem *acp_mmio, u8 ch_num) 4067c31335aSMaruthi Srinivas Bayyavarapu { 4077c31335aSMaruthi Srinivas Bayyavarapu u32 dma_ctrl; 4087c31335aSMaruthi Srinivas Bayyavarapu u32 dma_ch_sts; 4097c31335aSMaruthi Srinivas Bayyavarapu u32 count = ACP_DMA_RESET_TIME; 4107c31335aSMaruthi Srinivas Bayyavarapu 4117c31335aSMaruthi Srinivas Bayyavarapu dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 4127c31335aSMaruthi Srinivas Bayyavarapu 4137c31335aSMaruthi Srinivas Bayyavarapu /* clear the dma control register fields before writing zero 4147c31335aSMaruthi Srinivas Bayyavarapu * in reset bit 4157c31335aSMaruthi Srinivas Bayyavarapu */ 4167c31335aSMaruthi Srinivas Bayyavarapu dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRun_MASK; 4177c31335aSMaruthi Srinivas Bayyavarapu dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChIOCEn_MASK; 4187c31335aSMaruthi Srinivas Bayyavarapu 4197c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 4207c31335aSMaruthi Srinivas Bayyavarapu dma_ch_sts = acp_reg_read(acp_mmio, mmACP_DMA_CH_STS); 4217c31335aSMaruthi Srinivas Bayyavarapu 4227c31335aSMaruthi Srinivas Bayyavarapu if (dma_ch_sts & BIT(ch_num)) { 4237c31335aSMaruthi Srinivas Bayyavarapu /* set the reset bit for this channel to stop the dma 4247c31335aSMaruthi Srinivas Bayyavarapu * transfer 4257c31335aSMaruthi Srinivas Bayyavarapu */ 4267c31335aSMaruthi Srinivas Bayyavarapu dma_ctrl |= ACP_DMA_CNTL_0__DMAChRst_MASK; 4277c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 4287c31335aSMaruthi Srinivas Bayyavarapu } 4297c31335aSMaruthi Srinivas Bayyavarapu 4307c31335aSMaruthi Srinivas Bayyavarapu /* check the channel status bit for some time and return the status */ 4317c31335aSMaruthi Srinivas Bayyavarapu while (true) { 4327c31335aSMaruthi Srinivas Bayyavarapu dma_ch_sts = acp_reg_read(acp_mmio, mmACP_DMA_CH_STS); 4337c31335aSMaruthi Srinivas Bayyavarapu if (!(dma_ch_sts & BIT(ch_num))) { 4347c31335aSMaruthi Srinivas Bayyavarapu /* clear the reset flag after successfully stopping 4357c31335aSMaruthi Srinivas Bayyavarapu * the dma transfer and break from the loop 4367c31335aSMaruthi Srinivas Bayyavarapu */ 4377c31335aSMaruthi Srinivas Bayyavarapu dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRst_MASK; 4387c31335aSMaruthi Srinivas Bayyavarapu 4397c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 4407c31335aSMaruthi Srinivas Bayyavarapu + ch_num); 4417c31335aSMaruthi Srinivas Bayyavarapu break; 4427c31335aSMaruthi Srinivas Bayyavarapu } 4437c31335aSMaruthi Srinivas Bayyavarapu if (--count == 0) { 4447c31335aSMaruthi Srinivas Bayyavarapu pr_err("Failed to stop ACP DMA channel : %d\n", ch_num); 4457c31335aSMaruthi Srinivas Bayyavarapu return -ETIMEDOUT; 4467c31335aSMaruthi Srinivas Bayyavarapu } 4477c31335aSMaruthi Srinivas Bayyavarapu udelay(100); 4487c31335aSMaruthi Srinivas Bayyavarapu } 4497c31335aSMaruthi Srinivas Bayyavarapu return 0; 4507c31335aSMaruthi Srinivas Bayyavarapu } 4517c31335aSMaruthi Srinivas Bayyavarapu 452c36d9b3fSMaruthi Srinivas Bayyavarapu static void acp_set_sram_bank_state(void __iomem *acp_mmio, u16 bank, 453c36d9b3fSMaruthi Srinivas Bayyavarapu bool power_on) 454c36d9b3fSMaruthi Srinivas Bayyavarapu { 455c36d9b3fSMaruthi Srinivas Bayyavarapu u32 val, req_reg, sts_reg, sts_reg_mask; 456c36d9b3fSMaruthi Srinivas Bayyavarapu u32 loops = 1000; 457c36d9b3fSMaruthi Srinivas Bayyavarapu 458c36d9b3fSMaruthi Srinivas Bayyavarapu if (bank < 32) { 459c36d9b3fSMaruthi Srinivas Bayyavarapu req_reg = mmACP_MEM_SHUT_DOWN_REQ_LO; 460c36d9b3fSMaruthi Srinivas Bayyavarapu sts_reg = mmACP_MEM_SHUT_DOWN_STS_LO; 461c36d9b3fSMaruthi Srinivas Bayyavarapu sts_reg_mask = 0xFFFFFFFF; 462c36d9b3fSMaruthi Srinivas Bayyavarapu 463c36d9b3fSMaruthi Srinivas Bayyavarapu } else { 464c36d9b3fSMaruthi Srinivas Bayyavarapu bank -= 32; 465c36d9b3fSMaruthi Srinivas Bayyavarapu req_reg = mmACP_MEM_SHUT_DOWN_REQ_HI; 466c36d9b3fSMaruthi Srinivas Bayyavarapu sts_reg = mmACP_MEM_SHUT_DOWN_STS_HI; 467c36d9b3fSMaruthi Srinivas Bayyavarapu sts_reg_mask = 0x0000FFFF; 468c36d9b3fSMaruthi Srinivas Bayyavarapu } 469c36d9b3fSMaruthi Srinivas Bayyavarapu 470c36d9b3fSMaruthi Srinivas Bayyavarapu val = acp_reg_read(acp_mmio, req_reg); 471c36d9b3fSMaruthi Srinivas Bayyavarapu if (val & (1 << bank)) { 472c36d9b3fSMaruthi Srinivas Bayyavarapu /* bank is in off state */ 473c36d9b3fSMaruthi Srinivas Bayyavarapu if (power_on == true) 474c36d9b3fSMaruthi Srinivas Bayyavarapu /* request to on */ 475c36d9b3fSMaruthi Srinivas Bayyavarapu val &= ~(1 << bank); 476c36d9b3fSMaruthi Srinivas Bayyavarapu else 477c36d9b3fSMaruthi Srinivas Bayyavarapu /* request to off */ 478c36d9b3fSMaruthi Srinivas Bayyavarapu return; 479c36d9b3fSMaruthi Srinivas Bayyavarapu } else { 480c36d9b3fSMaruthi Srinivas Bayyavarapu /* bank is in on state */ 481c36d9b3fSMaruthi Srinivas Bayyavarapu if (power_on == false) 482c36d9b3fSMaruthi Srinivas Bayyavarapu /* request to off */ 483c36d9b3fSMaruthi Srinivas Bayyavarapu val |= 1 << bank; 484c36d9b3fSMaruthi Srinivas Bayyavarapu else 485c36d9b3fSMaruthi Srinivas Bayyavarapu /* request to on */ 486c36d9b3fSMaruthi Srinivas Bayyavarapu return; 487c36d9b3fSMaruthi Srinivas Bayyavarapu } 488c36d9b3fSMaruthi Srinivas Bayyavarapu acp_reg_write(val, acp_mmio, req_reg); 489c36d9b3fSMaruthi Srinivas Bayyavarapu 490c36d9b3fSMaruthi Srinivas Bayyavarapu while (acp_reg_read(acp_mmio, sts_reg) != sts_reg_mask) { 491c36d9b3fSMaruthi Srinivas Bayyavarapu if (!loops--) { 492c36d9b3fSMaruthi Srinivas Bayyavarapu pr_err("ACP SRAM bank %d state change failed\n", bank); 493c36d9b3fSMaruthi Srinivas Bayyavarapu break; 494c36d9b3fSMaruthi Srinivas Bayyavarapu } 495c36d9b3fSMaruthi Srinivas Bayyavarapu cpu_relax(); 496c36d9b3fSMaruthi Srinivas Bayyavarapu } 497c36d9b3fSMaruthi Srinivas Bayyavarapu } 498c36d9b3fSMaruthi Srinivas Bayyavarapu 4997c31335aSMaruthi Srinivas Bayyavarapu /* Initialize and bring ACP hardware to default state. */ 500607b39efSVijendar Mukunda static int acp_init(void __iomem *acp_mmio, u32 asic_type) 5017c31335aSMaruthi Srinivas Bayyavarapu { 502c36d9b3fSMaruthi Srinivas Bayyavarapu u16 bank; 5037c31335aSMaruthi Srinivas Bayyavarapu u32 val, count, sram_pte_offset; 5047c31335aSMaruthi Srinivas Bayyavarapu 5057c31335aSMaruthi Srinivas Bayyavarapu /* Assert Soft reset of ACP */ 5067c31335aSMaruthi Srinivas Bayyavarapu val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET); 5077c31335aSMaruthi Srinivas Bayyavarapu 5087c31335aSMaruthi Srinivas Bayyavarapu val |= ACP_SOFT_RESET__SoftResetAud_MASK; 5097c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET); 5107c31335aSMaruthi Srinivas Bayyavarapu 5117c31335aSMaruthi Srinivas Bayyavarapu count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE; 5127c31335aSMaruthi Srinivas Bayyavarapu while (true) { 5137c31335aSMaruthi Srinivas Bayyavarapu val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET); 5147c31335aSMaruthi Srinivas Bayyavarapu if (ACP_SOFT_RESET__SoftResetAudDone_MASK == 5157c31335aSMaruthi Srinivas Bayyavarapu (val & ACP_SOFT_RESET__SoftResetAudDone_MASK)) 5167c31335aSMaruthi Srinivas Bayyavarapu break; 5177c31335aSMaruthi Srinivas Bayyavarapu if (--count == 0) { 5187c31335aSMaruthi Srinivas Bayyavarapu pr_err("Failed to reset ACP\n"); 5197c31335aSMaruthi Srinivas Bayyavarapu return -ETIMEDOUT; 5207c31335aSMaruthi Srinivas Bayyavarapu } 5217c31335aSMaruthi Srinivas Bayyavarapu udelay(100); 5227c31335aSMaruthi Srinivas Bayyavarapu } 5237c31335aSMaruthi Srinivas Bayyavarapu 5247c31335aSMaruthi Srinivas Bayyavarapu /* Enable clock to ACP and wait until the clock is enabled */ 5257c31335aSMaruthi Srinivas Bayyavarapu val = acp_reg_read(acp_mmio, mmACP_CONTROL); 5267c31335aSMaruthi Srinivas Bayyavarapu val = val | ACP_CONTROL__ClkEn_MASK; 5277c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(val, acp_mmio, mmACP_CONTROL); 5287c31335aSMaruthi Srinivas Bayyavarapu 5297c31335aSMaruthi Srinivas Bayyavarapu count = ACP_CLOCK_EN_TIME_OUT_VALUE; 5307c31335aSMaruthi Srinivas Bayyavarapu 5317c31335aSMaruthi Srinivas Bayyavarapu while (true) { 5327c31335aSMaruthi Srinivas Bayyavarapu val = acp_reg_read(acp_mmio, mmACP_STATUS); 5337c31335aSMaruthi Srinivas Bayyavarapu if (val & (u32) 0x1) 5347c31335aSMaruthi Srinivas Bayyavarapu break; 5357c31335aSMaruthi Srinivas Bayyavarapu if (--count == 0) { 5367c31335aSMaruthi Srinivas Bayyavarapu pr_err("Failed to reset ACP\n"); 5377c31335aSMaruthi Srinivas Bayyavarapu return -ETIMEDOUT; 5387c31335aSMaruthi Srinivas Bayyavarapu } 5397c31335aSMaruthi Srinivas Bayyavarapu udelay(100); 5407c31335aSMaruthi Srinivas Bayyavarapu } 5417c31335aSMaruthi Srinivas Bayyavarapu 5427c31335aSMaruthi Srinivas Bayyavarapu /* Deassert the SOFT RESET flags */ 5437c31335aSMaruthi Srinivas Bayyavarapu val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET); 5447c31335aSMaruthi Srinivas Bayyavarapu val &= ~ACP_SOFT_RESET__SoftResetAud_MASK; 5457c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET); 5467c31335aSMaruthi Srinivas Bayyavarapu 5477c31335aSMaruthi Srinivas Bayyavarapu /* initiailize Onion control DAGB register */ 5487c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(ACP_ONION_CNTL_DEFAULT, acp_mmio, 5497c31335aSMaruthi Srinivas Bayyavarapu mmACP_AXI2DAGB_ONION_CNTL); 5507c31335aSMaruthi Srinivas Bayyavarapu 5517c31335aSMaruthi Srinivas Bayyavarapu /* initiailize Garlic control DAGB registers */ 5527c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(ACP_GARLIC_CNTL_DEFAULT, acp_mmio, 5537c31335aSMaruthi Srinivas Bayyavarapu mmACP_AXI2DAGB_GARLIC_CNTL); 5547c31335aSMaruthi Srinivas Bayyavarapu 5557c31335aSMaruthi Srinivas Bayyavarapu sram_pte_offset = ACP_DAGB_GRP_SRAM_BASE_ADDRESS | 5567c31335aSMaruthi Srinivas Bayyavarapu ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBSnoopSel_MASK | 5577c31335aSMaruthi Srinivas Bayyavarapu ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBTargetMemSel_MASK | 5587c31335aSMaruthi Srinivas Bayyavarapu ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBGrpEnable_MASK; 5597c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(sram_pte_offset, acp_mmio, mmACP_DAGB_BASE_ADDR_GRP_1); 5607c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(ACP_PAGE_SIZE_4K_ENABLE, acp_mmio, 5617c31335aSMaruthi Srinivas Bayyavarapu mmACP_DAGB_PAGE_SIZE_GRP_1); 5627c31335aSMaruthi Srinivas Bayyavarapu 5637c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(ACP_SRAM_BASE_ADDRESS, acp_mmio, 5647c31335aSMaruthi Srinivas Bayyavarapu mmACP_DMA_DESC_BASE_ADDR); 5657c31335aSMaruthi Srinivas Bayyavarapu 5667c31335aSMaruthi Srinivas Bayyavarapu /* Num of descriptiors in SRAM 0x4, means 256 descriptors;(64 * 4) */ 5677c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(0x4, acp_mmio, mmACP_DMA_DESC_MAX_NUM_DSCR); 5687c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(ACP_EXTERNAL_INTR_CNTL__DMAIOCMask_MASK, 5697c31335aSMaruthi Srinivas Bayyavarapu acp_mmio, mmACP_EXTERNAL_INTR_CNTL); 5707c31335aSMaruthi Srinivas Bayyavarapu 571c36d9b3fSMaruthi Srinivas Bayyavarapu /* When ACP_TILE_P1 is turned on, all SRAM banks get turned on. 572c36d9b3fSMaruthi Srinivas Bayyavarapu * Now, turn off all of them. This can't be done in 'poweron' of 573c36d9b3fSMaruthi Srinivas Bayyavarapu * ACP pm domain, as this requires ACP to be initialized. 574607b39efSVijendar Mukunda * For Stoney, Memory gating is disabled,i.e SRAM Banks 575607b39efSVijendar Mukunda * won't be turned off. The default state for SRAM banks is ON. 576607b39efSVijendar Mukunda * Setting SRAM bank state code skipped for STONEY platform. 577c36d9b3fSMaruthi Srinivas Bayyavarapu */ 578607b39efSVijendar Mukunda if (asic_type != CHIP_STONEY) { 579c36d9b3fSMaruthi Srinivas Bayyavarapu for (bank = 1; bank < 48; bank++) 580c36d9b3fSMaruthi Srinivas Bayyavarapu acp_set_sram_bank_state(acp_mmio, bank, false); 581607b39efSVijendar Mukunda } 582c36d9b3fSMaruthi Srinivas Bayyavarapu 583aac89748SVijendar Mukunda /* Stoney supports 16bit resolution */ 584aac89748SVijendar Mukunda if (asic_type == CHIP_STONEY) { 585aac89748SVijendar Mukunda val = acp_reg_read(acp_mmio, mmACP_I2S_16BIT_RESOLUTION_EN); 586aac89748SVijendar Mukunda val |= 0x03; 587aac89748SVijendar Mukunda acp_reg_write(val, acp_mmio, mmACP_I2S_16BIT_RESOLUTION_EN); 588aac89748SVijendar Mukunda } 5897c31335aSMaruthi Srinivas Bayyavarapu return 0; 5907c31335aSMaruthi Srinivas Bayyavarapu } 5917c31335aSMaruthi Srinivas Bayyavarapu 5921cce2000SMasahiro Yamada /* Deinitialize ACP */ 5937c31335aSMaruthi Srinivas Bayyavarapu static int acp_deinit(void __iomem *acp_mmio) 5947c31335aSMaruthi Srinivas Bayyavarapu { 5957c31335aSMaruthi Srinivas Bayyavarapu u32 val; 5967c31335aSMaruthi Srinivas Bayyavarapu u32 count; 5977c31335aSMaruthi Srinivas Bayyavarapu 5987c31335aSMaruthi Srinivas Bayyavarapu /* Assert Soft reset of ACP */ 5997c31335aSMaruthi Srinivas Bayyavarapu val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET); 6007c31335aSMaruthi Srinivas Bayyavarapu 6017c31335aSMaruthi Srinivas Bayyavarapu val |= ACP_SOFT_RESET__SoftResetAud_MASK; 6027c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET); 6037c31335aSMaruthi Srinivas Bayyavarapu 6047c31335aSMaruthi Srinivas Bayyavarapu count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE; 6057c31335aSMaruthi Srinivas Bayyavarapu while (true) { 6067c31335aSMaruthi Srinivas Bayyavarapu val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET); 6077c31335aSMaruthi Srinivas Bayyavarapu if (ACP_SOFT_RESET__SoftResetAudDone_MASK == 6087c31335aSMaruthi Srinivas Bayyavarapu (val & ACP_SOFT_RESET__SoftResetAudDone_MASK)) 6097c31335aSMaruthi Srinivas Bayyavarapu break; 6107c31335aSMaruthi Srinivas Bayyavarapu if (--count == 0) { 6117c31335aSMaruthi Srinivas Bayyavarapu pr_err("Failed to reset ACP\n"); 6127c31335aSMaruthi Srinivas Bayyavarapu return -ETIMEDOUT; 6137c31335aSMaruthi Srinivas Bayyavarapu } 6147c31335aSMaruthi Srinivas Bayyavarapu udelay(100); 6157c31335aSMaruthi Srinivas Bayyavarapu } 6167c31335aSMaruthi Srinivas Bayyavarapu /** Disable ACP clock */ 6177c31335aSMaruthi Srinivas Bayyavarapu val = acp_reg_read(acp_mmio, mmACP_CONTROL); 6187c31335aSMaruthi Srinivas Bayyavarapu val &= ~ACP_CONTROL__ClkEn_MASK; 6197c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(val, acp_mmio, mmACP_CONTROL); 6207c31335aSMaruthi Srinivas Bayyavarapu 6217c31335aSMaruthi Srinivas Bayyavarapu count = ACP_CLOCK_EN_TIME_OUT_VALUE; 6227c31335aSMaruthi Srinivas Bayyavarapu 6237c31335aSMaruthi Srinivas Bayyavarapu while (true) { 6247c31335aSMaruthi Srinivas Bayyavarapu val = acp_reg_read(acp_mmio, mmACP_STATUS); 6257c31335aSMaruthi Srinivas Bayyavarapu if (!(val & (u32) 0x1)) 6267c31335aSMaruthi Srinivas Bayyavarapu break; 6277c31335aSMaruthi Srinivas Bayyavarapu if (--count == 0) { 6287c31335aSMaruthi Srinivas Bayyavarapu pr_err("Failed to reset ACP\n"); 6297c31335aSMaruthi Srinivas Bayyavarapu return -ETIMEDOUT; 6307c31335aSMaruthi Srinivas Bayyavarapu } 6317c31335aSMaruthi Srinivas Bayyavarapu udelay(100); 6327c31335aSMaruthi Srinivas Bayyavarapu } 6337c31335aSMaruthi Srinivas Bayyavarapu return 0; 6347c31335aSMaruthi Srinivas Bayyavarapu } 6357c31335aSMaruthi Srinivas Bayyavarapu 6367c31335aSMaruthi Srinivas Bayyavarapu /* ACP DMA irq handler routine for playback, capture usecases */ 6377c31335aSMaruthi Srinivas Bayyavarapu static irqreturn_t dma_irq_handler(int irq, void *arg) 6387c31335aSMaruthi Srinivas Bayyavarapu { 6397c31335aSMaruthi Srinivas Bayyavarapu u16 dscr_idx; 6407c31335aSMaruthi Srinivas Bayyavarapu u32 intr_flag, ext_intr_status; 6417c31335aSMaruthi Srinivas Bayyavarapu struct audio_drv_data *irq_data; 6427c31335aSMaruthi Srinivas Bayyavarapu void __iomem *acp_mmio; 6437c31335aSMaruthi Srinivas Bayyavarapu struct device *dev = arg; 6447c31335aSMaruthi Srinivas Bayyavarapu bool valid_irq = false; 6457c31335aSMaruthi Srinivas Bayyavarapu 6467c31335aSMaruthi Srinivas Bayyavarapu irq_data = dev_get_drvdata(dev); 6477c31335aSMaruthi Srinivas Bayyavarapu acp_mmio = irq_data->acp_mmio; 6487c31335aSMaruthi Srinivas Bayyavarapu 6497c31335aSMaruthi Srinivas Bayyavarapu ext_intr_status = acp_reg_read(acp_mmio, mmACP_EXTERNAL_INTR_STAT); 6507c31335aSMaruthi Srinivas Bayyavarapu intr_flag = (((ext_intr_status & 6517c31335aSMaruthi Srinivas Bayyavarapu ACP_EXTERNAL_INTR_STAT__DMAIOCStat_MASK) >> 6527c31335aSMaruthi Srinivas Bayyavarapu ACP_EXTERNAL_INTR_STAT__DMAIOCStat__SHIFT)); 6537c31335aSMaruthi Srinivas Bayyavarapu 6547c31335aSMaruthi Srinivas Bayyavarapu if ((intr_flag & BIT(ACP_TO_I2S_DMA_CH_NUM)) != 0) { 6557c31335aSMaruthi Srinivas Bayyavarapu valid_irq = true; 6567c31335aSMaruthi Srinivas Bayyavarapu if (acp_reg_read(acp_mmio, mmACP_DMA_CUR_DSCR_13) == 6577c31335aSMaruthi Srinivas Bayyavarapu PLAYBACK_START_DMA_DESCR_CH13) 6587c31335aSMaruthi Srinivas Bayyavarapu dscr_idx = PLAYBACK_END_DMA_DESCR_CH12; 65931c45b3eSVijendar Mukunda else 66031c45b3eSVijendar Mukunda dscr_idx = PLAYBACK_START_DMA_DESCR_CH12; 6617c31335aSMaruthi Srinivas Bayyavarapu config_acp_dma_channel(acp_mmio, SYSRAM_TO_ACP_CH_NUM, dscr_idx, 6627c31335aSMaruthi Srinivas Bayyavarapu 1, 0); 6637c31335aSMaruthi Srinivas Bayyavarapu acp_dma_start(acp_mmio, SYSRAM_TO_ACP_CH_NUM, false); 6647c31335aSMaruthi Srinivas Bayyavarapu 665*e21358c4SMukunda, Vijendar snd_pcm_period_elapsed(irq_data->play_i2ssp_stream); 6667c31335aSMaruthi Srinivas Bayyavarapu 6677c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write((intr_flag & BIT(ACP_TO_I2S_DMA_CH_NUM)) << 16, 6687c31335aSMaruthi Srinivas Bayyavarapu acp_mmio, mmACP_EXTERNAL_INTR_STAT); 6697c31335aSMaruthi Srinivas Bayyavarapu } 6707c31335aSMaruthi Srinivas Bayyavarapu 6717c31335aSMaruthi Srinivas Bayyavarapu if ((intr_flag & BIT(I2S_TO_ACP_DMA_CH_NUM)) != 0) { 6727c31335aSMaruthi Srinivas Bayyavarapu valid_irq = true; 6737c31335aSMaruthi Srinivas Bayyavarapu if (acp_reg_read(acp_mmio, mmACP_DMA_CUR_DSCR_15) == 6747c31335aSMaruthi Srinivas Bayyavarapu CAPTURE_START_DMA_DESCR_CH15) 6757c31335aSMaruthi Srinivas Bayyavarapu dscr_idx = CAPTURE_END_DMA_DESCR_CH14; 6767c31335aSMaruthi Srinivas Bayyavarapu else 6777c31335aSMaruthi Srinivas Bayyavarapu dscr_idx = CAPTURE_START_DMA_DESCR_CH14; 6787c31335aSMaruthi Srinivas Bayyavarapu config_acp_dma_channel(acp_mmio, ACP_TO_SYSRAM_CH_NUM, dscr_idx, 6797c31335aSMaruthi Srinivas Bayyavarapu 1, 0); 6807c31335aSMaruthi Srinivas Bayyavarapu acp_dma_start(acp_mmio, ACP_TO_SYSRAM_CH_NUM, false); 6817c31335aSMaruthi Srinivas Bayyavarapu 6827c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write((intr_flag & BIT(I2S_TO_ACP_DMA_CH_NUM)) << 16, 6837c31335aSMaruthi Srinivas Bayyavarapu acp_mmio, mmACP_EXTERNAL_INTR_STAT); 6847c31335aSMaruthi Srinivas Bayyavarapu } 6857c31335aSMaruthi Srinivas Bayyavarapu 6867c31335aSMaruthi Srinivas Bayyavarapu if ((intr_flag & BIT(ACP_TO_SYSRAM_CH_NUM)) != 0) { 6877c31335aSMaruthi Srinivas Bayyavarapu valid_irq = true; 688*e21358c4SMukunda, Vijendar snd_pcm_period_elapsed(irq_data->capture_i2ssp_stream); 6897c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write((intr_flag & BIT(ACP_TO_SYSRAM_CH_NUM)) << 16, 6907c31335aSMaruthi Srinivas Bayyavarapu acp_mmio, mmACP_EXTERNAL_INTR_STAT); 6917c31335aSMaruthi Srinivas Bayyavarapu } 6927c31335aSMaruthi Srinivas Bayyavarapu 6937c31335aSMaruthi Srinivas Bayyavarapu if (valid_irq) 6947c31335aSMaruthi Srinivas Bayyavarapu return IRQ_HANDLED; 6957c31335aSMaruthi Srinivas Bayyavarapu else 6967c31335aSMaruthi Srinivas Bayyavarapu return IRQ_NONE; 6977c31335aSMaruthi Srinivas Bayyavarapu } 6987c31335aSMaruthi Srinivas Bayyavarapu 6997c31335aSMaruthi Srinivas Bayyavarapu static int acp_dma_open(struct snd_pcm_substream *substream) 7007c31335aSMaruthi Srinivas Bayyavarapu { 701c36d9b3fSMaruthi Srinivas Bayyavarapu u16 bank; 7027c31335aSMaruthi Srinivas Bayyavarapu int ret = 0; 7037c31335aSMaruthi Srinivas Bayyavarapu struct snd_pcm_runtime *runtime = substream->runtime; 7047c31335aSMaruthi Srinivas Bayyavarapu struct snd_soc_pcm_runtime *prtd = substream->private_data; 7057c31335aSMaruthi Srinivas Bayyavarapu struct audio_drv_data *intr_data = dev_get_drvdata(prtd->platform->dev); 7067c31335aSMaruthi Srinivas Bayyavarapu 7077c31335aSMaruthi Srinivas Bayyavarapu struct audio_substream_data *adata = 7087c31335aSMaruthi Srinivas Bayyavarapu kzalloc(sizeof(struct audio_substream_data), GFP_KERNEL); 7097c31335aSMaruthi Srinivas Bayyavarapu if (adata == NULL) 7107c31335aSMaruthi Srinivas Bayyavarapu return -ENOMEM; 7117c31335aSMaruthi Srinivas Bayyavarapu 7129c7d6fabSVijendar Mukunda if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 7139c7d6fabSVijendar Mukunda switch (intr_data->asic_type) { 7149c7d6fabSVijendar Mukunda case CHIP_STONEY: 7159c7d6fabSVijendar Mukunda runtime->hw = acp_st_pcm_hardware_playback; 7169c7d6fabSVijendar Mukunda break; 7179c7d6fabSVijendar Mukunda default: 7187c31335aSMaruthi Srinivas Bayyavarapu runtime->hw = acp_pcm_hardware_playback; 7199c7d6fabSVijendar Mukunda } 7209c7d6fabSVijendar Mukunda } else { 7219c7d6fabSVijendar Mukunda switch (intr_data->asic_type) { 7229c7d6fabSVijendar Mukunda case CHIP_STONEY: 7239c7d6fabSVijendar Mukunda runtime->hw = acp_st_pcm_hardware_capture; 7249c7d6fabSVijendar Mukunda break; 7259c7d6fabSVijendar Mukunda default: 7267c31335aSMaruthi Srinivas Bayyavarapu runtime->hw = acp_pcm_hardware_capture; 7279c7d6fabSVijendar Mukunda } 7289c7d6fabSVijendar Mukunda } 7297c31335aSMaruthi Srinivas Bayyavarapu 7307c31335aSMaruthi Srinivas Bayyavarapu ret = snd_pcm_hw_constraint_integer(runtime, 7317c31335aSMaruthi Srinivas Bayyavarapu SNDRV_PCM_HW_PARAM_PERIODS); 7327c31335aSMaruthi Srinivas Bayyavarapu if (ret < 0) { 7337c31335aSMaruthi Srinivas Bayyavarapu dev_err(prtd->platform->dev, "set integer constraint failed\n"); 734cde6bcd5SDan Carpenter kfree(adata); 7357c31335aSMaruthi Srinivas Bayyavarapu return ret; 7367c31335aSMaruthi Srinivas Bayyavarapu } 7377c31335aSMaruthi Srinivas Bayyavarapu 7387c31335aSMaruthi Srinivas Bayyavarapu adata->acp_mmio = intr_data->acp_mmio; 7397c31335aSMaruthi Srinivas Bayyavarapu runtime->private_data = adata; 7407c31335aSMaruthi Srinivas Bayyavarapu 7417c31335aSMaruthi Srinivas Bayyavarapu /* Enable ACP irq, when neither playback or capture streams are 7427c31335aSMaruthi Srinivas Bayyavarapu * active by the time when a new stream is being opened. 7437c31335aSMaruthi Srinivas Bayyavarapu * This enablement is not required for another stream, if current 7447c31335aSMaruthi Srinivas Bayyavarapu * stream is not closed 7457c31335aSMaruthi Srinivas Bayyavarapu */ 746*e21358c4SMukunda, Vijendar if (!intr_data->play_i2ssp_stream && !intr_data->capture_i2ssp_stream) 7477c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB); 7487c31335aSMaruthi Srinivas Bayyavarapu 749c36d9b3fSMaruthi Srinivas Bayyavarapu if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 750*e21358c4SMukunda, Vijendar intr_data->play_i2ssp_stream = substream; 751607b39efSVijendar Mukunda /* For Stoney, Memory gating is disabled,i.e SRAM Banks 752607b39efSVijendar Mukunda * won't be turned off. The default state for SRAM banks is ON. 753607b39efSVijendar Mukunda * Setting SRAM bank state code skipped for STONEY platform. 754607b39efSVijendar Mukunda */ 755607b39efSVijendar Mukunda if (intr_data->asic_type != CHIP_STONEY) { 756c36d9b3fSMaruthi Srinivas Bayyavarapu for (bank = 1; bank <= 4; bank++) 757607b39efSVijendar Mukunda acp_set_sram_bank_state(intr_data->acp_mmio, 758607b39efSVijendar Mukunda bank, true); 759607b39efSVijendar Mukunda } 760c36d9b3fSMaruthi Srinivas Bayyavarapu } else { 761*e21358c4SMukunda, Vijendar intr_data->capture_i2ssp_stream = substream; 762607b39efSVijendar Mukunda if (intr_data->asic_type != CHIP_STONEY) { 763c36d9b3fSMaruthi Srinivas Bayyavarapu for (bank = 5; bank <= 8; bank++) 764607b39efSVijendar Mukunda acp_set_sram_bank_state(intr_data->acp_mmio, 765607b39efSVijendar Mukunda bank, true); 766607b39efSVijendar Mukunda } 767c36d9b3fSMaruthi Srinivas Bayyavarapu } 7687c31335aSMaruthi Srinivas Bayyavarapu 7697c31335aSMaruthi Srinivas Bayyavarapu return 0; 7707c31335aSMaruthi Srinivas Bayyavarapu } 7717c31335aSMaruthi Srinivas Bayyavarapu 7727c31335aSMaruthi Srinivas Bayyavarapu static int acp_dma_hw_params(struct snd_pcm_substream *substream, 7737c31335aSMaruthi Srinivas Bayyavarapu struct snd_pcm_hw_params *params) 7747c31335aSMaruthi Srinivas Bayyavarapu { 7757c31335aSMaruthi Srinivas Bayyavarapu int status; 7767c31335aSMaruthi Srinivas Bayyavarapu uint64_t size; 7777c31335aSMaruthi Srinivas Bayyavarapu struct page *pg; 7787c31335aSMaruthi Srinivas Bayyavarapu struct snd_pcm_runtime *runtime; 7797c31335aSMaruthi Srinivas Bayyavarapu struct audio_substream_data *rtd; 780aac89748SVijendar Mukunda struct snd_soc_pcm_runtime *prtd = substream->private_data; 781aac89748SVijendar Mukunda struct audio_drv_data *adata = dev_get_drvdata(prtd->platform->dev); 7827c31335aSMaruthi Srinivas Bayyavarapu 7837c31335aSMaruthi Srinivas Bayyavarapu runtime = substream->runtime; 7847c31335aSMaruthi Srinivas Bayyavarapu rtd = runtime->private_data; 7857c31335aSMaruthi Srinivas Bayyavarapu 7867c31335aSMaruthi Srinivas Bayyavarapu if (WARN_ON(!rtd)) 7877c31335aSMaruthi Srinivas Bayyavarapu return -EINVAL; 7887c31335aSMaruthi Srinivas Bayyavarapu 7897c31335aSMaruthi Srinivas Bayyavarapu size = params_buffer_bytes(params); 7907c31335aSMaruthi Srinivas Bayyavarapu status = snd_pcm_lib_malloc_pages(substream, size); 7917c31335aSMaruthi Srinivas Bayyavarapu if (status < 0) 7927c31335aSMaruthi Srinivas Bayyavarapu return status; 7937c31335aSMaruthi Srinivas Bayyavarapu 7947c31335aSMaruthi Srinivas Bayyavarapu memset(substream->runtime->dma_area, 0, params_buffer_bytes(params)); 7957c31335aSMaruthi Srinivas Bayyavarapu pg = virt_to_page(substream->dma_buffer.area); 7967c31335aSMaruthi Srinivas Bayyavarapu 7977c31335aSMaruthi Srinivas Bayyavarapu if (pg != NULL) { 798c36d9b3fSMaruthi Srinivas Bayyavarapu acp_set_sram_bank_state(rtd->acp_mmio, 0, true); 7997c31335aSMaruthi Srinivas Bayyavarapu /* Save for runtime private data */ 8007c31335aSMaruthi Srinivas Bayyavarapu rtd->pg = pg; 8017c31335aSMaruthi Srinivas Bayyavarapu rtd->order = get_order(size); 8027c31335aSMaruthi Srinivas Bayyavarapu 8037c31335aSMaruthi Srinivas Bayyavarapu /* Fill the page table entries in ACP SRAM */ 8047c31335aSMaruthi Srinivas Bayyavarapu rtd->pg = pg; 8057c31335aSMaruthi Srinivas Bayyavarapu rtd->size = size; 8067c31335aSMaruthi Srinivas Bayyavarapu rtd->num_of_pages = PAGE_ALIGN(size) >> PAGE_SHIFT; 8077c31335aSMaruthi Srinivas Bayyavarapu rtd->direction = substream->stream; 8087c31335aSMaruthi Srinivas Bayyavarapu 809aac89748SVijendar Mukunda config_acp_dma(rtd->acp_mmio, rtd, adata->asic_type); 8107c31335aSMaruthi Srinivas Bayyavarapu status = 0; 8117c31335aSMaruthi Srinivas Bayyavarapu } else { 8127c31335aSMaruthi Srinivas Bayyavarapu status = -ENOMEM; 8137c31335aSMaruthi Srinivas Bayyavarapu } 8147c31335aSMaruthi Srinivas Bayyavarapu return status; 8157c31335aSMaruthi Srinivas Bayyavarapu } 8167c31335aSMaruthi Srinivas Bayyavarapu 8177c31335aSMaruthi Srinivas Bayyavarapu static int acp_dma_hw_free(struct snd_pcm_substream *substream) 8187c31335aSMaruthi Srinivas Bayyavarapu { 8197c31335aSMaruthi Srinivas Bayyavarapu return snd_pcm_lib_free_pages(substream); 8207c31335aSMaruthi Srinivas Bayyavarapu } 8217c31335aSMaruthi Srinivas Bayyavarapu 82261add814SVijendar Mukunda static u64 acp_get_byte_count(void __iomem *acp_mmio, int stream) 82361add814SVijendar Mukunda { 82461add814SVijendar Mukunda union acp_dma_count playback_dma_count; 82561add814SVijendar Mukunda union acp_dma_count capture_dma_count; 82661add814SVijendar Mukunda u64 bytescount = 0; 82761add814SVijendar Mukunda 82861add814SVijendar Mukunda if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 82961add814SVijendar Mukunda playback_dma_count.bcount.high = acp_reg_read(acp_mmio, 83061add814SVijendar Mukunda mmACP_I2S_TRANSMIT_BYTE_CNT_HIGH); 83161add814SVijendar Mukunda playback_dma_count.bcount.low = acp_reg_read(acp_mmio, 83261add814SVijendar Mukunda mmACP_I2S_TRANSMIT_BYTE_CNT_LOW); 83361add814SVijendar Mukunda bytescount = playback_dma_count.bytescount; 83461add814SVijendar Mukunda } else { 83561add814SVijendar Mukunda capture_dma_count.bcount.high = acp_reg_read(acp_mmio, 83661add814SVijendar Mukunda mmACP_I2S_RECEIVED_BYTE_CNT_HIGH); 83761add814SVijendar Mukunda capture_dma_count.bcount.low = acp_reg_read(acp_mmio, 83861add814SVijendar Mukunda mmACP_I2S_RECEIVED_BYTE_CNT_LOW); 83961add814SVijendar Mukunda bytescount = capture_dma_count.bytescount; 84061add814SVijendar Mukunda } 84161add814SVijendar Mukunda return bytescount; 84261add814SVijendar Mukunda } 84361add814SVijendar Mukunda 8447c31335aSMaruthi Srinivas Bayyavarapu static snd_pcm_uframes_t acp_dma_pointer(struct snd_pcm_substream *substream) 8457c31335aSMaruthi Srinivas Bayyavarapu { 84661add814SVijendar Mukunda u32 buffersize; 8477c31335aSMaruthi Srinivas Bayyavarapu u32 pos = 0; 84861add814SVijendar Mukunda u64 bytescount = 0; 8497c31335aSMaruthi Srinivas Bayyavarapu 8507c31335aSMaruthi Srinivas Bayyavarapu struct snd_pcm_runtime *runtime = substream->runtime; 8517c31335aSMaruthi Srinivas Bayyavarapu struct audio_substream_data *rtd = runtime->private_data; 8527c31335aSMaruthi Srinivas Bayyavarapu 8537afa535eSMukunda, Vijendar if (!rtd) 8547afa535eSMukunda, Vijendar return -EINVAL; 8557afa535eSMukunda, Vijendar 85661add814SVijendar Mukunda buffersize = frames_to_bytes(runtime, runtime->buffer_size); 85761add814SVijendar Mukunda bytescount = acp_get_byte_count(rtd->acp_mmio, substream->stream); 85861add814SVijendar Mukunda 8597c31335aSMaruthi Srinivas Bayyavarapu if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 860*e21358c4SMukunda, Vijendar if (bytescount > rtd->i2ssp_renderbytescount) 861*e21358c4SMukunda, Vijendar bytescount = bytescount - rtd->i2ssp_renderbytescount; 8627c31335aSMaruthi Srinivas Bayyavarapu } else { 863*e21358c4SMukunda, Vijendar if (bytescount > rtd->i2ssp_capturebytescount) 864*e21358c4SMukunda, Vijendar bytescount = bytescount - rtd->i2ssp_capturebytescount; 8657c31335aSMaruthi Srinivas Bayyavarapu } 8667db08b2cSGuenter Roeck pos = do_div(bytescount, buffersize); 8677c31335aSMaruthi Srinivas Bayyavarapu return bytes_to_frames(runtime, pos); 8687c31335aSMaruthi Srinivas Bayyavarapu } 8697c31335aSMaruthi Srinivas Bayyavarapu 8707c31335aSMaruthi Srinivas Bayyavarapu static int acp_dma_mmap(struct snd_pcm_substream *substream, 8717c31335aSMaruthi Srinivas Bayyavarapu struct vm_area_struct *vma) 8727c31335aSMaruthi Srinivas Bayyavarapu { 8737c31335aSMaruthi Srinivas Bayyavarapu return snd_pcm_lib_default_mmap(substream, vma); 8747c31335aSMaruthi Srinivas Bayyavarapu } 8757c31335aSMaruthi Srinivas Bayyavarapu 8767c31335aSMaruthi Srinivas Bayyavarapu static int acp_dma_prepare(struct snd_pcm_substream *substream) 8777c31335aSMaruthi Srinivas Bayyavarapu { 8787c31335aSMaruthi Srinivas Bayyavarapu struct snd_pcm_runtime *runtime = substream->runtime; 8797c31335aSMaruthi Srinivas Bayyavarapu struct audio_substream_data *rtd = runtime->private_data; 8807c31335aSMaruthi Srinivas Bayyavarapu 8817afa535eSMukunda, Vijendar if (!rtd) 8827afa535eSMukunda, Vijendar return -EINVAL; 8837c31335aSMaruthi Srinivas Bayyavarapu if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 8847c31335aSMaruthi Srinivas Bayyavarapu config_acp_dma_channel(rtd->acp_mmio, SYSRAM_TO_ACP_CH_NUM, 8857c31335aSMaruthi Srinivas Bayyavarapu PLAYBACK_START_DMA_DESCR_CH12, 8867c31335aSMaruthi Srinivas Bayyavarapu NUM_DSCRS_PER_CHANNEL, 0); 8877c31335aSMaruthi Srinivas Bayyavarapu config_acp_dma_channel(rtd->acp_mmio, ACP_TO_I2S_DMA_CH_NUM, 8887c31335aSMaruthi Srinivas Bayyavarapu PLAYBACK_START_DMA_DESCR_CH13, 8897c31335aSMaruthi Srinivas Bayyavarapu NUM_DSCRS_PER_CHANNEL, 0); 8907c31335aSMaruthi Srinivas Bayyavarapu } else { 8917c31335aSMaruthi Srinivas Bayyavarapu config_acp_dma_channel(rtd->acp_mmio, ACP_TO_SYSRAM_CH_NUM, 8927c31335aSMaruthi Srinivas Bayyavarapu CAPTURE_START_DMA_DESCR_CH14, 8937c31335aSMaruthi Srinivas Bayyavarapu NUM_DSCRS_PER_CHANNEL, 0); 8947c31335aSMaruthi Srinivas Bayyavarapu config_acp_dma_channel(rtd->acp_mmio, I2S_TO_ACP_DMA_CH_NUM, 8957c31335aSMaruthi Srinivas Bayyavarapu CAPTURE_START_DMA_DESCR_CH15, 8967c31335aSMaruthi Srinivas Bayyavarapu NUM_DSCRS_PER_CHANNEL, 0); 8977c31335aSMaruthi Srinivas Bayyavarapu } 8987c31335aSMaruthi Srinivas Bayyavarapu return 0; 8997c31335aSMaruthi Srinivas Bayyavarapu } 9007c31335aSMaruthi Srinivas Bayyavarapu 9017c31335aSMaruthi Srinivas Bayyavarapu static int acp_dma_trigger(struct snd_pcm_substream *substream, int cmd) 9027c31335aSMaruthi Srinivas Bayyavarapu { 9037c31335aSMaruthi Srinivas Bayyavarapu int ret; 90431c45b3eSVijendar Mukunda u32 loops = 4000; 90561add814SVijendar Mukunda u64 bytescount = 0; 9067c31335aSMaruthi Srinivas Bayyavarapu 9077c31335aSMaruthi Srinivas Bayyavarapu struct snd_pcm_runtime *runtime = substream->runtime; 9087c31335aSMaruthi Srinivas Bayyavarapu struct snd_soc_pcm_runtime *prtd = substream->private_data; 9097c31335aSMaruthi Srinivas Bayyavarapu struct audio_substream_data *rtd = runtime->private_data; 9107c31335aSMaruthi Srinivas Bayyavarapu 9117c31335aSMaruthi Srinivas Bayyavarapu if (!rtd) 9127c31335aSMaruthi Srinivas Bayyavarapu return -EINVAL; 9137c31335aSMaruthi Srinivas Bayyavarapu switch (cmd) { 9147c31335aSMaruthi Srinivas Bayyavarapu case SNDRV_PCM_TRIGGER_START: 9157c31335aSMaruthi Srinivas Bayyavarapu case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 9167c31335aSMaruthi Srinivas Bayyavarapu case SNDRV_PCM_TRIGGER_RESUME: 91761add814SVijendar Mukunda bytescount = acp_get_byte_count(rtd->acp_mmio, 91861add814SVijendar Mukunda substream->stream); 9197c31335aSMaruthi Srinivas Bayyavarapu if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 920*e21358c4SMukunda, Vijendar if (rtd->i2ssp_renderbytescount == 0) 921*e21358c4SMukunda, Vijendar rtd->i2ssp_renderbytescount = bytescount; 9227c31335aSMaruthi Srinivas Bayyavarapu acp_dma_start(rtd->acp_mmio, 9237c31335aSMaruthi Srinivas Bayyavarapu SYSRAM_TO_ACP_CH_NUM, false); 9247c31335aSMaruthi Srinivas Bayyavarapu while (acp_reg_read(rtd->acp_mmio, mmACP_DMA_CH_STS) & 9257c31335aSMaruthi Srinivas Bayyavarapu BIT(SYSRAM_TO_ACP_CH_NUM)) { 9267c31335aSMaruthi Srinivas Bayyavarapu if (!loops--) { 9277c31335aSMaruthi Srinivas Bayyavarapu dev_err(prtd->platform->dev, 9287c31335aSMaruthi Srinivas Bayyavarapu "acp dma start timeout\n"); 9297c31335aSMaruthi Srinivas Bayyavarapu return -ETIMEDOUT; 9307c31335aSMaruthi Srinivas Bayyavarapu } 9317c31335aSMaruthi Srinivas Bayyavarapu cpu_relax(); 9327c31335aSMaruthi Srinivas Bayyavarapu } 9337c31335aSMaruthi Srinivas Bayyavarapu 9347c31335aSMaruthi Srinivas Bayyavarapu acp_dma_start(rtd->acp_mmio, 9357c31335aSMaruthi Srinivas Bayyavarapu ACP_TO_I2S_DMA_CH_NUM, true); 9367c31335aSMaruthi Srinivas Bayyavarapu 9377c31335aSMaruthi Srinivas Bayyavarapu } else { 938*e21358c4SMukunda, Vijendar if (rtd->i2ssp_capturebytescount == 0) 939*e21358c4SMukunda, Vijendar rtd->i2ssp_capturebytescount = bytescount; 9407c31335aSMaruthi Srinivas Bayyavarapu acp_dma_start(rtd->acp_mmio, 9417c31335aSMaruthi Srinivas Bayyavarapu I2S_TO_ACP_DMA_CH_NUM, true); 9427c31335aSMaruthi Srinivas Bayyavarapu } 9437c31335aSMaruthi Srinivas Bayyavarapu ret = 0; 9447c31335aSMaruthi Srinivas Bayyavarapu break; 9457c31335aSMaruthi Srinivas Bayyavarapu case SNDRV_PCM_TRIGGER_STOP: 9467c31335aSMaruthi Srinivas Bayyavarapu case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 9477c31335aSMaruthi Srinivas Bayyavarapu case SNDRV_PCM_TRIGGER_SUSPEND: 9487c31335aSMaruthi Srinivas Bayyavarapu /* Need to stop only circular DMA channels : 9497c31335aSMaruthi Srinivas Bayyavarapu * ACP_TO_I2S_DMA_CH_NUM / I2S_TO_ACP_DMA_CH_NUM. Non-circular 9507c31335aSMaruthi Srinivas Bayyavarapu * channels will stopped automatically after its transfer 9517c31335aSMaruthi Srinivas Bayyavarapu * completes : SYSRAM_TO_ACP_CH_NUM / ACP_TO_SYSRAM_CH_NUM 9527c31335aSMaruthi Srinivas Bayyavarapu */ 95361add814SVijendar Mukunda if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 9547c31335aSMaruthi Srinivas Bayyavarapu ret = acp_dma_stop(rtd->acp_mmio, 9557c31335aSMaruthi Srinivas Bayyavarapu ACP_TO_I2S_DMA_CH_NUM); 956*e21358c4SMukunda, Vijendar rtd->i2ssp_renderbytescount = 0; 95761add814SVijendar Mukunda } else { 9587c31335aSMaruthi Srinivas Bayyavarapu ret = acp_dma_stop(rtd->acp_mmio, 9597c31335aSMaruthi Srinivas Bayyavarapu I2S_TO_ACP_DMA_CH_NUM); 960*e21358c4SMukunda, Vijendar rtd->i2ssp_capturebytescount = 0; 96161add814SVijendar Mukunda } 9627c31335aSMaruthi Srinivas Bayyavarapu break; 9637c31335aSMaruthi Srinivas Bayyavarapu default: 9647c31335aSMaruthi Srinivas Bayyavarapu ret = -EINVAL; 9657c31335aSMaruthi Srinivas Bayyavarapu 9667c31335aSMaruthi Srinivas Bayyavarapu } 9677c31335aSMaruthi Srinivas Bayyavarapu return ret; 9687c31335aSMaruthi Srinivas Bayyavarapu } 9697c31335aSMaruthi Srinivas Bayyavarapu 9707c31335aSMaruthi Srinivas Bayyavarapu static int acp_dma_new(struct snd_soc_pcm_runtime *rtd) 9717c31335aSMaruthi Srinivas Bayyavarapu { 9729c7d6fabSVijendar Mukunda int ret; 9739c7d6fabSVijendar Mukunda struct audio_drv_data *adata = dev_get_drvdata(rtd->platform->dev); 9749c7d6fabSVijendar Mukunda 9759c7d6fabSVijendar Mukunda switch (adata->asic_type) { 9769c7d6fabSVijendar Mukunda case CHIP_STONEY: 9779c7d6fabSVijendar Mukunda ret = snd_pcm_lib_preallocate_pages_for_all(rtd->pcm, 9789c7d6fabSVijendar Mukunda SNDRV_DMA_TYPE_DEV, 9799c7d6fabSVijendar Mukunda NULL, ST_MIN_BUFFER, 9809c7d6fabSVijendar Mukunda ST_MAX_BUFFER); 9819c7d6fabSVijendar Mukunda break; 9829c7d6fabSVijendar Mukunda default: 9839c7d6fabSVijendar Mukunda ret = snd_pcm_lib_preallocate_pages_for_all(rtd->pcm, 9847c31335aSMaruthi Srinivas Bayyavarapu SNDRV_DMA_TYPE_DEV, 9857c31335aSMaruthi Srinivas Bayyavarapu NULL, MIN_BUFFER, 9867c31335aSMaruthi Srinivas Bayyavarapu MAX_BUFFER); 9879c7d6fabSVijendar Mukunda break; 9889c7d6fabSVijendar Mukunda } 9899c7d6fabSVijendar Mukunda if (ret < 0) 9909c7d6fabSVijendar Mukunda dev_err(rtd->platform->dev, 9919c7d6fabSVijendar Mukunda "buffer preallocation failer error:%d\n", ret); 9929c7d6fabSVijendar Mukunda return ret; 9937c31335aSMaruthi Srinivas Bayyavarapu } 9947c31335aSMaruthi Srinivas Bayyavarapu 9957c31335aSMaruthi Srinivas Bayyavarapu static int acp_dma_close(struct snd_pcm_substream *substream) 9967c31335aSMaruthi Srinivas Bayyavarapu { 997c36d9b3fSMaruthi Srinivas Bayyavarapu u16 bank; 9987c31335aSMaruthi Srinivas Bayyavarapu struct snd_pcm_runtime *runtime = substream->runtime; 9997c31335aSMaruthi Srinivas Bayyavarapu struct audio_substream_data *rtd = runtime->private_data; 10007c31335aSMaruthi Srinivas Bayyavarapu struct snd_soc_pcm_runtime *prtd = substream->private_data; 10017c31335aSMaruthi Srinivas Bayyavarapu struct audio_drv_data *adata = dev_get_drvdata(prtd->platform->dev); 10027c31335aSMaruthi Srinivas Bayyavarapu 10037c31335aSMaruthi Srinivas Bayyavarapu kfree(rtd); 10047c31335aSMaruthi Srinivas Bayyavarapu 1005c36d9b3fSMaruthi Srinivas Bayyavarapu if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 1006*e21358c4SMukunda, Vijendar adata->play_i2ssp_stream = NULL; 1007607b39efSVijendar Mukunda /* For Stoney, Memory gating is disabled,i.e SRAM Banks 1008607b39efSVijendar Mukunda * won't be turned off. The default state for SRAM banks is ON. 1009607b39efSVijendar Mukunda * Setting SRAM bank state code skipped for STONEY platform. 1010607b39efSVijendar Mukunda * added condition checks for Carrizo platform only 1011607b39efSVijendar Mukunda */ 1012607b39efSVijendar Mukunda if (adata->asic_type != CHIP_STONEY) { 1013c36d9b3fSMaruthi Srinivas Bayyavarapu for (bank = 1; bank <= 4; bank++) 1014c36d9b3fSMaruthi Srinivas Bayyavarapu acp_set_sram_bank_state(adata->acp_mmio, bank, 1015c36d9b3fSMaruthi Srinivas Bayyavarapu false); 1016607b39efSVijendar Mukunda } 1017c36d9b3fSMaruthi Srinivas Bayyavarapu } else { 1018*e21358c4SMukunda, Vijendar adata->capture_i2ssp_stream = NULL; 1019607b39efSVijendar Mukunda if (adata->asic_type != CHIP_STONEY) { 1020c36d9b3fSMaruthi Srinivas Bayyavarapu for (bank = 5; bank <= 8; bank++) 1021c36d9b3fSMaruthi Srinivas Bayyavarapu acp_set_sram_bank_state(adata->acp_mmio, bank, 1022c36d9b3fSMaruthi Srinivas Bayyavarapu false); 1023c36d9b3fSMaruthi Srinivas Bayyavarapu } 1024607b39efSVijendar Mukunda } 10257c31335aSMaruthi Srinivas Bayyavarapu 10267c31335aSMaruthi Srinivas Bayyavarapu /* Disable ACP irq, when the current stream is being closed and 10277c31335aSMaruthi Srinivas Bayyavarapu * another stream is also not active. 10287c31335aSMaruthi Srinivas Bayyavarapu */ 1029*e21358c4SMukunda, Vijendar if (!adata->play_i2ssp_stream && !adata->capture_i2ssp_stream) 10307c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(0, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB); 10317c31335aSMaruthi Srinivas Bayyavarapu 10327c31335aSMaruthi Srinivas Bayyavarapu return 0; 10337c31335aSMaruthi Srinivas Bayyavarapu } 10347c31335aSMaruthi Srinivas Bayyavarapu 1035115c7254SJulia Lawall static const struct snd_pcm_ops acp_dma_ops = { 10367c31335aSMaruthi Srinivas Bayyavarapu .open = acp_dma_open, 10377c31335aSMaruthi Srinivas Bayyavarapu .close = acp_dma_close, 10387c31335aSMaruthi Srinivas Bayyavarapu .ioctl = snd_pcm_lib_ioctl, 10397c31335aSMaruthi Srinivas Bayyavarapu .hw_params = acp_dma_hw_params, 10407c31335aSMaruthi Srinivas Bayyavarapu .hw_free = acp_dma_hw_free, 10417c31335aSMaruthi Srinivas Bayyavarapu .trigger = acp_dma_trigger, 10427c31335aSMaruthi Srinivas Bayyavarapu .pointer = acp_dma_pointer, 10437c31335aSMaruthi Srinivas Bayyavarapu .mmap = acp_dma_mmap, 10447c31335aSMaruthi Srinivas Bayyavarapu .prepare = acp_dma_prepare, 10457c31335aSMaruthi Srinivas Bayyavarapu }; 10467c31335aSMaruthi Srinivas Bayyavarapu 10477c31335aSMaruthi Srinivas Bayyavarapu static struct snd_soc_platform_driver acp_asoc_platform = { 10487c31335aSMaruthi Srinivas Bayyavarapu .ops = &acp_dma_ops, 10497c31335aSMaruthi Srinivas Bayyavarapu .pcm_new = acp_dma_new, 10507c31335aSMaruthi Srinivas Bayyavarapu }; 10517c31335aSMaruthi Srinivas Bayyavarapu 10527c31335aSMaruthi Srinivas Bayyavarapu static int acp_audio_probe(struct platform_device *pdev) 10537c31335aSMaruthi Srinivas Bayyavarapu { 10547c31335aSMaruthi Srinivas Bayyavarapu int status; 10557c31335aSMaruthi Srinivas Bayyavarapu struct audio_drv_data *audio_drv_data; 10567c31335aSMaruthi Srinivas Bayyavarapu struct resource *res; 1057a1b16aaaSVijendar Mukunda const u32 *pdata = pdev->dev.platform_data; 10587c31335aSMaruthi Srinivas Bayyavarapu 1059fdaa4511SGuenter Roeck if (!pdata) { 1060fdaa4511SGuenter Roeck dev_err(&pdev->dev, "Missing platform data\n"); 1061fdaa4511SGuenter Roeck return -ENODEV; 1062fdaa4511SGuenter Roeck } 1063fdaa4511SGuenter Roeck 10647c31335aSMaruthi Srinivas Bayyavarapu audio_drv_data = devm_kzalloc(&pdev->dev, sizeof(struct audio_drv_data), 10657c31335aSMaruthi Srinivas Bayyavarapu GFP_KERNEL); 10667c31335aSMaruthi Srinivas Bayyavarapu if (audio_drv_data == NULL) 10677c31335aSMaruthi Srinivas Bayyavarapu return -ENOMEM; 10687c31335aSMaruthi Srinivas Bayyavarapu 10697c31335aSMaruthi Srinivas Bayyavarapu res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 10707c31335aSMaruthi Srinivas Bayyavarapu audio_drv_data->acp_mmio = devm_ioremap_resource(&pdev->dev, res); 1071fdaa4511SGuenter Roeck if (IS_ERR(audio_drv_data->acp_mmio)) 1072fdaa4511SGuenter Roeck return PTR_ERR(audio_drv_data->acp_mmio); 10737c31335aSMaruthi Srinivas Bayyavarapu 10747c31335aSMaruthi Srinivas Bayyavarapu /* The following members gets populated in device 'open' 10757c31335aSMaruthi Srinivas Bayyavarapu * function. Till then interrupts are disabled in 'acp_init' 10767c31335aSMaruthi Srinivas Bayyavarapu * and device doesn't generate any interrupts. 10777c31335aSMaruthi Srinivas Bayyavarapu */ 10787c31335aSMaruthi Srinivas Bayyavarapu 1079*e21358c4SMukunda, Vijendar audio_drv_data->play_i2ssp_stream = NULL; 1080*e21358c4SMukunda, Vijendar audio_drv_data->capture_i2ssp_stream = NULL; 1081*e21358c4SMukunda, Vijendar 1082a1b16aaaSVijendar Mukunda audio_drv_data->asic_type = *pdata; 10837c31335aSMaruthi Srinivas Bayyavarapu 10847c31335aSMaruthi Srinivas Bayyavarapu res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 10857c31335aSMaruthi Srinivas Bayyavarapu if (!res) { 10867c31335aSMaruthi Srinivas Bayyavarapu dev_err(&pdev->dev, "IORESOURCE_IRQ FAILED\n"); 10877c31335aSMaruthi Srinivas Bayyavarapu return -ENODEV; 10887c31335aSMaruthi Srinivas Bayyavarapu } 10897c31335aSMaruthi Srinivas Bayyavarapu 10907c31335aSMaruthi Srinivas Bayyavarapu status = devm_request_irq(&pdev->dev, res->start, dma_irq_handler, 10917c31335aSMaruthi Srinivas Bayyavarapu 0, "ACP_IRQ", &pdev->dev); 10927c31335aSMaruthi Srinivas Bayyavarapu if (status) { 10937c31335aSMaruthi Srinivas Bayyavarapu dev_err(&pdev->dev, "ACP IRQ request failed\n"); 10947c31335aSMaruthi Srinivas Bayyavarapu return status; 10957c31335aSMaruthi Srinivas Bayyavarapu } 10967c31335aSMaruthi Srinivas Bayyavarapu 10977c31335aSMaruthi Srinivas Bayyavarapu dev_set_drvdata(&pdev->dev, audio_drv_data); 10987c31335aSMaruthi Srinivas Bayyavarapu 10997c31335aSMaruthi Srinivas Bayyavarapu /* Initialize the ACP */ 11007afa535eSMukunda, Vijendar status = acp_init(audio_drv_data->acp_mmio, audio_drv_data->asic_type); 11017afa535eSMukunda, Vijendar if (status) { 11027afa535eSMukunda, Vijendar dev_err(&pdev->dev, "ACP Init failed status:%d\n", status); 11037afa535eSMukunda, Vijendar return status; 11047afa535eSMukunda, Vijendar } 11057c31335aSMaruthi Srinivas Bayyavarapu 11067c31335aSMaruthi Srinivas Bayyavarapu status = snd_soc_register_platform(&pdev->dev, &acp_asoc_platform); 11077c31335aSMaruthi Srinivas Bayyavarapu if (status != 0) { 11087c31335aSMaruthi Srinivas Bayyavarapu dev_err(&pdev->dev, "Fail to register ALSA platform device\n"); 11097c31335aSMaruthi Srinivas Bayyavarapu return status; 11107c31335aSMaruthi Srinivas Bayyavarapu } 11117c31335aSMaruthi Srinivas Bayyavarapu 11121927da93SMaruthi Srinivas Bayyavarapu pm_runtime_set_autosuspend_delay(&pdev->dev, 10000); 11131927da93SMaruthi Srinivas Bayyavarapu pm_runtime_use_autosuspend(&pdev->dev); 11141927da93SMaruthi Srinivas Bayyavarapu pm_runtime_enable(&pdev->dev); 11151927da93SMaruthi Srinivas Bayyavarapu 11167c31335aSMaruthi Srinivas Bayyavarapu return status; 11177c31335aSMaruthi Srinivas Bayyavarapu } 11187c31335aSMaruthi Srinivas Bayyavarapu 11197c31335aSMaruthi Srinivas Bayyavarapu static int acp_audio_remove(struct platform_device *pdev) 11207c31335aSMaruthi Srinivas Bayyavarapu { 11217afa535eSMukunda, Vijendar int status; 11227c31335aSMaruthi Srinivas Bayyavarapu struct audio_drv_data *adata = dev_get_drvdata(&pdev->dev); 11237c31335aSMaruthi Srinivas Bayyavarapu 11247afa535eSMukunda, Vijendar status = acp_deinit(adata->acp_mmio); 11257afa535eSMukunda, Vijendar if (status) 11267afa535eSMukunda, Vijendar dev_err(&pdev->dev, "ACP Deinit failed status:%d\n", status); 11277c31335aSMaruthi Srinivas Bayyavarapu snd_soc_unregister_platform(&pdev->dev); 11281927da93SMaruthi Srinivas Bayyavarapu pm_runtime_disable(&pdev->dev); 11297c31335aSMaruthi Srinivas Bayyavarapu 11307c31335aSMaruthi Srinivas Bayyavarapu return 0; 11317c31335aSMaruthi Srinivas Bayyavarapu } 11327c31335aSMaruthi Srinivas Bayyavarapu 11331927da93SMaruthi Srinivas Bayyavarapu static int acp_pcm_resume(struct device *dev) 11341927da93SMaruthi Srinivas Bayyavarapu { 1135c36d9b3fSMaruthi Srinivas Bayyavarapu u16 bank; 11367afa535eSMukunda, Vijendar int status; 11371927da93SMaruthi Srinivas Bayyavarapu struct audio_drv_data *adata = dev_get_drvdata(dev); 11381927da93SMaruthi Srinivas Bayyavarapu 11397afa535eSMukunda, Vijendar status = acp_init(adata->acp_mmio, adata->asic_type); 11407afa535eSMukunda, Vijendar if (status) { 11417afa535eSMukunda, Vijendar dev_err(dev, "ACP Init failed status:%d\n", status); 11427afa535eSMukunda, Vijendar return status; 11437afa535eSMukunda, Vijendar } 11441927da93SMaruthi Srinivas Bayyavarapu 1145*e21358c4SMukunda, Vijendar if (adata->play_i2ssp_stream && adata->play_i2ssp_stream->runtime) { 1146607b39efSVijendar Mukunda /* For Stoney, Memory gating is disabled,i.e SRAM Banks 1147607b39efSVijendar Mukunda * won't be turned off. The default state for SRAM banks is ON. 1148607b39efSVijendar Mukunda * Setting SRAM bank state code skipped for STONEY platform. 1149607b39efSVijendar Mukunda */ 1150607b39efSVijendar Mukunda if (adata->asic_type != CHIP_STONEY) { 1151c36d9b3fSMaruthi Srinivas Bayyavarapu for (bank = 1; bank <= 4; bank++) 1152c36d9b3fSMaruthi Srinivas Bayyavarapu acp_set_sram_bank_state(adata->acp_mmio, bank, 1153c36d9b3fSMaruthi Srinivas Bayyavarapu true); 1154607b39efSVijendar Mukunda } 11551927da93SMaruthi Srinivas Bayyavarapu config_acp_dma(adata->acp_mmio, 1156*e21358c4SMukunda, Vijendar adata->play_i2ssp_stream->runtime->private_data, 1157aac89748SVijendar Mukunda adata->asic_type); 1158c36d9b3fSMaruthi Srinivas Bayyavarapu } 1159*e21358c4SMukunda, Vijendar if (adata->capture_i2ssp_stream && adata->capture_i2ssp_stream->runtime) { 1160607b39efSVijendar Mukunda if (adata->asic_type != CHIP_STONEY) { 1161c36d9b3fSMaruthi Srinivas Bayyavarapu for (bank = 5; bank <= 8; bank++) 1162c36d9b3fSMaruthi Srinivas Bayyavarapu acp_set_sram_bank_state(adata->acp_mmio, bank, 1163c36d9b3fSMaruthi Srinivas Bayyavarapu true); 1164607b39efSVijendar Mukunda } 11651927da93SMaruthi Srinivas Bayyavarapu config_acp_dma(adata->acp_mmio, 1166*e21358c4SMukunda, Vijendar adata->capture_i2ssp_stream->runtime->private_data, 1167aac89748SVijendar Mukunda adata->asic_type); 1168c36d9b3fSMaruthi Srinivas Bayyavarapu } 11691927da93SMaruthi Srinivas Bayyavarapu acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB); 11701927da93SMaruthi Srinivas Bayyavarapu return 0; 11711927da93SMaruthi Srinivas Bayyavarapu } 11721927da93SMaruthi Srinivas Bayyavarapu 11731927da93SMaruthi Srinivas Bayyavarapu static int acp_pcm_runtime_suspend(struct device *dev) 11741927da93SMaruthi Srinivas Bayyavarapu { 11757afa535eSMukunda, Vijendar int status; 11761927da93SMaruthi Srinivas Bayyavarapu struct audio_drv_data *adata = dev_get_drvdata(dev); 11771927da93SMaruthi Srinivas Bayyavarapu 11787afa535eSMukunda, Vijendar status = acp_deinit(adata->acp_mmio); 11797afa535eSMukunda, Vijendar if (status) 11807afa535eSMukunda, Vijendar dev_err(dev, "ACP Deinit failed status:%d\n", status); 11811927da93SMaruthi Srinivas Bayyavarapu acp_reg_write(0, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB); 11821927da93SMaruthi Srinivas Bayyavarapu return 0; 11831927da93SMaruthi Srinivas Bayyavarapu } 11841927da93SMaruthi Srinivas Bayyavarapu 11851927da93SMaruthi Srinivas Bayyavarapu static int acp_pcm_runtime_resume(struct device *dev) 11861927da93SMaruthi Srinivas Bayyavarapu { 11877afa535eSMukunda, Vijendar int status; 11881927da93SMaruthi Srinivas Bayyavarapu struct audio_drv_data *adata = dev_get_drvdata(dev); 11891927da93SMaruthi Srinivas Bayyavarapu 11907afa535eSMukunda, Vijendar status = acp_init(adata->acp_mmio, adata->asic_type); 11917afa535eSMukunda, Vijendar if (status) { 11927afa535eSMukunda, Vijendar dev_err(dev, "ACP Init failed status:%d\n", status); 11937afa535eSMukunda, Vijendar return status; 11947afa535eSMukunda, Vijendar } 11951927da93SMaruthi Srinivas Bayyavarapu acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB); 11961927da93SMaruthi Srinivas Bayyavarapu return 0; 11971927da93SMaruthi Srinivas Bayyavarapu } 11981927da93SMaruthi Srinivas Bayyavarapu 11991927da93SMaruthi Srinivas Bayyavarapu static const struct dev_pm_ops acp_pm_ops = { 12001927da93SMaruthi Srinivas Bayyavarapu .resume = acp_pcm_resume, 12011927da93SMaruthi Srinivas Bayyavarapu .runtime_suspend = acp_pcm_runtime_suspend, 12021927da93SMaruthi Srinivas Bayyavarapu .runtime_resume = acp_pcm_runtime_resume, 12031927da93SMaruthi Srinivas Bayyavarapu }; 12041927da93SMaruthi Srinivas Bayyavarapu 12057c31335aSMaruthi Srinivas Bayyavarapu static struct platform_driver acp_dma_driver = { 12067c31335aSMaruthi Srinivas Bayyavarapu .probe = acp_audio_probe, 12077c31335aSMaruthi Srinivas Bayyavarapu .remove = acp_audio_remove, 12087c31335aSMaruthi Srinivas Bayyavarapu .driver = { 1209bdd2a858SAkshu Agrawal .name = DRV_NAME, 12101927da93SMaruthi Srinivas Bayyavarapu .pm = &acp_pm_ops, 12117c31335aSMaruthi Srinivas Bayyavarapu }, 12127c31335aSMaruthi Srinivas Bayyavarapu }; 12137c31335aSMaruthi Srinivas Bayyavarapu 12147c31335aSMaruthi Srinivas Bayyavarapu module_platform_driver(acp_dma_driver); 12157c31335aSMaruthi Srinivas Bayyavarapu 1216607b39efSVijendar Mukunda MODULE_AUTHOR("Vijendar.Mukunda@amd.com"); 12177c31335aSMaruthi Srinivas Bayyavarapu MODULE_AUTHOR("Maruthi.Bayyavarapu@amd.com"); 12187c31335aSMaruthi Srinivas Bayyavarapu MODULE_DESCRIPTION("AMD ACP PCM Driver"); 12197c31335aSMaruthi Srinivas Bayyavarapu MODULE_LICENSE("GPL v2"); 1220bdd2a858SAkshu Agrawal MODULE_ALIAS("platform:"DRV_NAME); 1221