17c31335aSMaruthi Srinivas Bayyavarapu /* 27c31335aSMaruthi Srinivas Bayyavarapu * AMD ALSA SoC PCM Driver for ACP 2.x 37c31335aSMaruthi Srinivas Bayyavarapu * 47c31335aSMaruthi Srinivas Bayyavarapu * Copyright 2014-2015 Advanced Micro Devices, Inc. 57c31335aSMaruthi Srinivas Bayyavarapu * 67c31335aSMaruthi Srinivas Bayyavarapu * This program is free software; you can redistribute it and/or modify it 77c31335aSMaruthi Srinivas Bayyavarapu * under the terms and conditions of the GNU General Public License, 87c31335aSMaruthi Srinivas Bayyavarapu * version 2, as published by the Free Software Foundation. 97c31335aSMaruthi Srinivas Bayyavarapu * 107c31335aSMaruthi Srinivas Bayyavarapu * This program is distributed in the hope it will be useful, but WITHOUT 117c31335aSMaruthi Srinivas Bayyavarapu * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 127c31335aSMaruthi Srinivas Bayyavarapu * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 137c31335aSMaruthi Srinivas Bayyavarapu * more details. 147c31335aSMaruthi Srinivas Bayyavarapu */ 157c31335aSMaruthi Srinivas Bayyavarapu 167c31335aSMaruthi Srinivas Bayyavarapu #include <linux/module.h> 177c31335aSMaruthi Srinivas Bayyavarapu #include <linux/delay.h> 187cb1dc81SGuenter Roeck #include <linux/io.h> 197c31335aSMaruthi Srinivas Bayyavarapu #include <linux/sizes.h> 201927da93SMaruthi Srinivas Bayyavarapu #include <linux/pm_runtime.h> 217c31335aSMaruthi Srinivas Bayyavarapu 227c31335aSMaruthi Srinivas Bayyavarapu #include <sound/soc.h> 23607b39efSVijendar Mukunda #include <drm/amd_asic_type.h> 247c31335aSMaruthi Srinivas Bayyavarapu #include "acp.h" 257c31335aSMaruthi Srinivas Bayyavarapu 26a1042a42SKuninori Morimoto #define DRV_NAME "acp_audio_dma" 27a1042a42SKuninori Morimoto 287c31335aSMaruthi Srinivas Bayyavarapu #define PLAYBACK_MIN_NUM_PERIODS 2 297c31335aSMaruthi Srinivas Bayyavarapu #define PLAYBACK_MAX_NUM_PERIODS 2 307c31335aSMaruthi Srinivas Bayyavarapu #define PLAYBACK_MAX_PERIOD_SIZE 16384 317c31335aSMaruthi Srinivas Bayyavarapu #define PLAYBACK_MIN_PERIOD_SIZE 1024 327c31335aSMaruthi Srinivas Bayyavarapu #define CAPTURE_MIN_NUM_PERIODS 2 337c31335aSMaruthi Srinivas Bayyavarapu #define CAPTURE_MAX_NUM_PERIODS 2 347c31335aSMaruthi Srinivas Bayyavarapu #define CAPTURE_MAX_PERIOD_SIZE 16384 357c31335aSMaruthi Srinivas Bayyavarapu #define CAPTURE_MIN_PERIOD_SIZE 1024 367c31335aSMaruthi Srinivas Bayyavarapu 377c31335aSMaruthi Srinivas Bayyavarapu #define MAX_BUFFER (PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS) 387c31335aSMaruthi Srinivas Bayyavarapu #define MIN_BUFFER MAX_BUFFER 397c31335aSMaruthi Srinivas Bayyavarapu 409c7d6fabSVijendar Mukunda #define ST_PLAYBACK_MAX_PERIOD_SIZE 8192 419c7d6fabSVijendar Mukunda #define ST_CAPTURE_MAX_PERIOD_SIZE ST_PLAYBACK_MAX_PERIOD_SIZE 429c7d6fabSVijendar Mukunda #define ST_MAX_BUFFER (ST_PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS) 439c7d6fabSVijendar Mukunda #define ST_MIN_BUFFER ST_MAX_BUFFER 449c7d6fabSVijendar Mukunda 45bdd2a858SAkshu Agrawal #define DRV_NAME "acp_audio_dma" 46bdd2a858SAkshu Agrawal 477c31335aSMaruthi Srinivas Bayyavarapu static const struct snd_pcm_hardware acp_pcm_hardware_playback = { 487c31335aSMaruthi Srinivas Bayyavarapu .info = SNDRV_PCM_INFO_INTERLEAVED | 497c31335aSMaruthi Srinivas Bayyavarapu SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP | 507c31335aSMaruthi Srinivas Bayyavarapu SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH | 517c31335aSMaruthi Srinivas Bayyavarapu SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME, 527c31335aSMaruthi Srinivas Bayyavarapu .formats = SNDRV_PCM_FMTBIT_S16_LE | 537c31335aSMaruthi Srinivas Bayyavarapu SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, 547c31335aSMaruthi Srinivas Bayyavarapu .channels_min = 1, 557c31335aSMaruthi Srinivas Bayyavarapu .channels_max = 8, 567c31335aSMaruthi Srinivas Bayyavarapu .rates = SNDRV_PCM_RATE_8000_96000, 577c31335aSMaruthi Srinivas Bayyavarapu .rate_min = 8000, 587c31335aSMaruthi Srinivas Bayyavarapu .rate_max = 96000, 597c31335aSMaruthi Srinivas Bayyavarapu .buffer_bytes_max = PLAYBACK_MAX_NUM_PERIODS * PLAYBACK_MAX_PERIOD_SIZE, 607c31335aSMaruthi Srinivas Bayyavarapu .period_bytes_min = PLAYBACK_MIN_PERIOD_SIZE, 617c31335aSMaruthi Srinivas Bayyavarapu .period_bytes_max = PLAYBACK_MAX_PERIOD_SIZE, 627c31335aSMaruthi Srinivas Bayyavarapu .periods_min = PLAYBACK_MIN_NUM_PERIODS, 637c31335aSMaruthi Srinivas Bayyavarapu .periods_max = PLAYBACK_MAX_NUM_PERIODS, 647c31335aSMaruthi Srinivas Bayyavarapu }; 657c31335aSMaruthi Srinivas Bayyavarapu 667c31335aSMaruthi Srinivas Bayyavarapu static const struct snd_pcm_hardware acp_pcm_hardware_capture = { 677c31335aSMaruthi Srinivas Bayyavarapu .info = SNDRV_PCM_INFO_INTERLEAVED | 687c31335aSMaruthi Srinivas Bayyavarapu SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP | 697c31335aSMaruthi Srinivas Bayyavarapu SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH | 707c31335aSMaruthi Srinivas Bayyavarapu SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME, 717c31335aSMaruthi Srinivas Bayyavarapu .formats = SNDRV_PCM_FMTBIT_S16_LE | 727c31335aSMaruthi Srinivas Bayyavarapu SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, 737c31335aSMaruthi Srinivas Bayyavarapu .channels_min = 1, 747c31335aSMaruthi Srinivas Bayyavarapu .channels_max = 2, 757c31335aSMaruthi Srinivas Bayyavarapu .rates = SNDRV_PCM_RATE_8000_48000, 767c31335aSMaruthi Srinivas Bayyavarapu .rate_min = 8000, 777c31335aSMaruthi Srinivas Bayyavarapu .rate_max = 48000, 787c31335aSMaruthi Srinivas Bayyavarapu .buffer_bytes_max = CAPTURE_MAX_NUM_PERIODS * CAPTURE_MAX_PERIOD_SIZE, 797c31335aSMaruthi Srinivas Bayyavarapu .period_bytes_min = CAPTURE_MIN_PERIOD_SIZE, 807c31335aSMaruthi Srinivas Bayyavarapu .period_bytes_max = CAPTURE_MAX_PERIOD_SIZE, 817c31335aSMaruthi Srinivas Bayyavarapu .periods_min = CAPTURE_MIN_NUM_PERIODS, 827c31335aSMaruthi Srinivas Bayyavarapu .periods_max = CAPTURE_MAX_NUM_PERIODS, 837c31335aSMaruthi Srinivas Bayyavarapu }; 847c31335aSMaruthi Srinivas Bayyavarapu 859c7d6fabSVijendar Mukunda static const struct snd_pcm_hardware acp_st_pcm_hardware_playback = { 869c7d6fabSVijendar Mukunda .info = SNDRV_PCM_INFO_INTERLEAVED | 879c7d6fabSVijendar Mukunda SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP | 889c7d6fabSVijendar Mukunda SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH | 899c7d6fabSVijendar Mukunda SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME, 909c7d6fabSVijendar Mukunda .formats = SNDRV_PCM_FMTBIT_S16_LE | 919c7d6fabSVijendar Mukunda SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, 929c7d6fabSVijendar Mukunda .channels_min = 1, 939c7d6fabSVijendar Mukunda .channels_max = 8, 949c7d6fabSVijendar Mukunda .rates = SNDRV_PCM_RATE_8000_96000, 959c7d6fabSVijendar Mukunda .rate_min = 8000, 969c7d6fabSVijendar Mukunda .rate_max = 96000, 979c7d6fabSVijendar Mukunda .buffer_bytes_max = ST_MAX_BUFFER, 989c7d6fabSVijendar Mukunda .period_bytes_min = PLAYBACK_MIN_PERIOD_SIZE, 999c7d6fabSVijendar Mukunda .period_bytes_max = ST_PLAYBACK_MAX_PERIOD_SIZE, 1009c7d6fabSVijendar Mukunda .periods_min = PLAYBACK_MIN_NUM_PERIODS, 1019c7d6fabSVijendar Mukunda .periods_max = PLAYBACK_MAX_NUM_PERIODS, 1029c7d6fabSVijendar Mukunda }; 1039c7d6fabSVijendar Mukunda 1049c7d6fabSVijendar Mukunda static const struct snd_pcm_hardware acp_st_pcm_hardware_capture = { 1059c7d6fabSVijendar Mukunda .info = SNDRV_PCM_INFO_INTERLEAVED | 1069c7d6fabSVijendar Mukunda SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP | 1079c7d6fabSVijendar Mukunda SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH | 1089c7d6fabSVijendar Mukunda SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME, 1099c7d6fabSVijendar Mukunda .formats = SNDRV_PCM_FMTBIT_S16_LE | 1109c7d6fabSVijendar Mukunda SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, 1119c7d6fabSVijendar Mukunda .channels_min = 1, 1129c7d6fabSVijendar Mukunda .channels_max = 2, 1139c7d6fabSVijendar Mukunda .rates = SNDRV_PCM_RATE_8000_48000, 1149c7d6fabSVijendar Mukunda .rate_min = 8000, 1159c7d6fabSVijendar Mukunda .rate_max = 48000, 1169c7d6fabSVijendar Mukunda .buffer_bytes_max = ST_MAX_BUFFER, 1179c7d6fabSVijendar Mukunda .period_bytes_min = CAPTURE_MIN_PERIOD_SIZE, 1189c7d6fabSVijendar Mukunda .period_bytes_max = ST_CAPTURE_MAX_PERIOD_SIZE, 1199c7d6fabSVijendar Mukunda .periods_min = CAPTURE_MIN_NUM_PERIODS, 1209c7d6fabSVijendar Mukunda .periods_max = CAPTURE_MAX_NUM_PERIODS, 1219c7d6fabSVijendar Mukunda }; 1229c7d6fabSVijendar Mukunda 1237c31335aSMaruthi Srinivas Bayyavarapu static u32 acp_reg_read(void __iomem *acp_mmio, u32 reg) 1247c31335aSMaruthi Srinivas Bayyavarapu { 1257c31335aSMaruthi Srinivas Bayyavarapu return readl(acp_mmio + (reg * 4)); 1267c31335aSMaruthi Srinivas Bayyavarapu } 1277c31335aSMaruthi Srinivas Bayyavarapu 1287c31335aSMaruthi Srinivas Bayyavarapu static void acp_reg_write(u32 val, void __iomem *acp_mmio, u32 reg) 1297c31335aSMaruthi Srinivas Bayyavarapu { 1307c31335aSMaruthi Srinivas Bayyavarapu writel(val, acp_mmio + (reg * 4)); 1317c31335aSMaruthi Srinivas Bayyavarapu } 1327c31335aSMaruthi Srinivas Bayyavarapu 13313838c11SMukunda, Vijendar /* 13413838c11SMukunda, Vijendar * Configure a given dma channel parameters - enable/disable, 1357c31335aSMaruthi Srinivas Bayyavarapu * number of descriptors, priority 1367c31335aSMaruthi Srinivas Bayyavarapu */ 1377c31335aSMaruthi Srinivas Bayyavarapu static void config_acp_dma_channel(void __iomem *acp_mmio, u8 ch_num, 1387c31335aSMaruthi Srinivas Bayyavarapu u16 dscr_strt_idx, u16 num_dscrs, 1397c31335aSMaruthi Srinivas Bayyavarapu enum acp_dma_priority_level priority_level) 1407c31335aSMaruthi Srinivas Bayyavarapu { 1417c31335aSMaruthi Srinivas Bayyavarapu u32 dma_ctrl; 1427c31335aSMaruthi Srinivas Bayyavarapu 1437c31335aSMaruthi Srinivas Bayyavarapu /* disable the channel run field */ 1447c31335aSMaruthi Srinivas Bayyavarapu dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 1457c31335aSMaruthi Srinivas Bayyavarapu dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRun_MASK; 1467c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 1477c31335aSMaruthi Srinivas Bayyavarapu 1487c31335aSMaruthi Srinivas Bayyavarapu /* program a DMA channel with first descriptor to be processed. */ 1497c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write((ACP_DMA_DSCR_STRT_IDX_0__DMAChDscrStrtIdx_MASK 1507c31335aSMaruthi Srinivas Bayyavarapu & dscr_strt_idx), 1517c31335aSMaruthi Srinivas Bayyavarapu acp_mmio, mmACP_DMA_DSCR_STRT_IDX_0 + ch_num); 1527c31335aSMaruthi Srinivas Bayyavarapu 15313838c11SMukunda, Vijendar /* 15413838c11SMukunda, Vijendar * program a DMA channel with the number of descriptors to be 1557c31335aSMaruthi Srinivas Bayyavarapu * processed in the transfer 1567c31335aSMaruthi Srinivas Bayyavarapu */ 1577c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(ACP_DMA_DSCR_CNT_0__DMAChDscrCnt_MASK & num_dscrs, 1587c31335aSMaruthi Srinivas Bayyavarapu acp_mmio, mmACP_DMA_DSCR_CNT_0 + ch_num); 1597c31335aSMaruthi Srinivas Bayyavarapu 1607c31335aSMaruthi Srinivas Bayyavarapu /* set DMA channel priority */ 1617c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(priority_level, acp_mmio, mmACP_DMA_PRIO_0 + ch_num); 1627c31335aSMaruthi Srinivas Bayyavarapu } 1637c31335aSMaruthi Srinivas Bayyavarapu 1647c31335aSMaruthi Srinivas Bayyavarapu /* Initialize a dma descriptor in SRAM based on descritor information passed */ 1657c31335aSMaruthi Srinivas Bayyavarapu static void config_dma_descriptor_in_sram(void __iomem *acp_mmio, 1667c31335aSMaruthi Srinivas Bayyavarapu u16 descr_idx, 1677c31335aSMaruthi Srinivas Bayyavarapu acp_dma_dscr_transfer_t *descr_info) 1687c31335aSMaruthi Srinivas Bayyavarapu { 1697c31335aSMaruthi Srinivas Bayyavarapu u32 sram_offset; 1707c31335aSMaruthi Srinivas Bayyavarapu 1717c31335aSMaruthi Srinivas Bayyavarapu sram_offset = (descr_idx * sizeof(acp_dma_dscr_transfer_t)); 1727c31335aSMaruthi Srinivas Bayyavarapu 1737c31335aSMaruthi Srinivas Bayyavarapu /* program the source base address. */ 1747c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(sram_offset, acp_mmio, mmACP_SRBM_Targ_Idx_Addr); 1757c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(descr_info->src, acp_mmio, mmACP_SRBM_Targ_Idx_Data); 1767c31335aSMaruthi Srinivas Bayyavarapu /* program the destination base address. */ 1777c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(sram_offset + 4, acp_mmio, mmACP_SRBM_Targ_Idx_Addr); 1787c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(descr_info->dest, acp_mmio, mmACP_SRBM_Targ_Idx_Data); 1797c31335aSMaruthi Srinivas Bayyavarapu 1807c31335aSMaruthi Srinivas Bayyavarapu /* program the number of bytes to be transferred for this descriptor. */ 1817c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(sram_offset + 8, acp_mmio, mmACP_SRBM_Targ_Idx_Addr); 1827c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(descr_info->xfer_val, acp_mmio, mmACP_SRBM_Targ_Idx_Data); 1837c31335aSMaruthi Srinivas Bayyavarapu } 1847c31335aSMaruthi Srinivas Bayyavarapu 18513838c11SMukunda, Vijendar /* 18613838c11SMukunda, Vijendar * Initialize the DMA descriptor information for transfer between 1877c31335aSMaruthi Srinivas Bayyavarapu * system memory <-> ACP SRAM 1887c31335aSMaruthi Srinivas Bayyavarapu */ 1897c31335aSMaruthi Srinivas Bayyavarapu static void set_acp_sysmem_dma_descriptors(void __iomem *acp_mmio, 19013838c11SMukunda, Vijendar u32 size, int direction, 19113838c11SMukunda, Vijendar u32 pte_offset, u16 ch, 19213838c11SMukunda, Vijendar u32 sram_bank, u16 dma_dscr_idx, 19313838c11SMukunda, Vijendar u32 asic_type) 1947c31335aSMaruthi Srinivas Bayyavarapu { 1957c31335aSMaruthi Srinivas Bayyavarapu u16 i; 1967c31335aSMaruthi Srinivas Bayyavarapu acp_dma_dscr_transfer_t dmadscr[NUM_DSCRS_PER_CHANNEL]; 1977c31335aSMaruthi Srinivas Bayyavarapu 1987c31335aSMaruthi Srinivas Bayyavarapu for (i = 0; i < NUM_DSCRS_PER_CHANNEL; i++) { 1997c31335aSMaruthi Srinivas Bayyavarapu dmadscr[i].xfer_val = 0; 2007c31335aSMaruthi Srinivas Bayyavarapu if (direction == SNDRV_PCM_STREAM_PLAYBACK) { 2014376a86cSMukunda, Vijendar dma_dscr_idx = dma_dscr_idx + i; 2024376a86cSMukunda, Vijendar dmadscr[i].dest = sram_bank + (i * (size / 2)); 2037c31335aSMaruthi Srinivas Bayyavarapu dmadscr[i].src = ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS 2047c31335aSMaruthi Srinivas Bayyavarapu + (pte_offset * SZ_4K) + (i * (size / 2)); 205aac89748SVijendar Mukunda switch (asic_type) { 206aac89748SVijendar Mukunda case CHIP_STONEY: 207aac89748SVijendar Mukunda dmadscr[i].xfer_val |= 20813838c11SMukunda, Vijendar (ACP_DMA_ATTR_DAGB_GARLIC_TO_SHAREDMEM << 16) | 209aac89748SVijendar Mukunda (size / 2); 210aac89748SVijendar Mukunda break; 211aac89748SVijendar Mukunda default: 2127c31335aSMaruthi Srinivas Bayyavarapu dmadscr[i].xfer_val |= 21313838c11SMukunda, Vijendar (ACP_DMA_ATTR_DAGB_ONION_TO_SHAREDMEM << 16) | 2147c31335aSMaruthi Srinivas Bayyavarapu (size / 2); 215aac89748SVijendar Mukunda } 2167c31335aSMaruthi Srinivas Bayyavarapu } else { 2174376a86cSMukunda, Vijendar dma_dscr_idx = dma_dscr_idx + i; 2184376a86cSMukunda, Vijendar dmadscr[i].src = sram_bank + (i * (size / 2)); 219aac89748SVijendar Mukunda dmadscr[i].dest = 220aac89748SVijendar Mukunda ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS + 221aac89748SVijendar Mukunda (pte_offset * SZ_4K) + (i * (size / 2)); 2224376a86cSMukunda, Vijendar switch (asic_type) { 2234376a86cSMukunda, Vijendar case CHIP_STONEY: 224aac89748SVijendar Mukunda dmadscr[i].xfer_val |= 225aac89748SVijendar Mukunda BIT(22) | 22613838c11SMukunda, Vijendar (ACP_DMA_ATTR_SHARED_MEM_TO_DAGB_GARLIC << 16) | 227aac89748SVijendar Mukunda (size / 2); 228aac89748SVijendar Mukunda break; 229aac89748SVijendar Mukunda default: 2307c31335aSMaruthi Srinivas Bayyavarapu dmadscr[i].xfer_val |= 2317c31335aSMaruthi Srinivas Bayyavarapu BIT(22) | 23213838c11SMukunda, Vijendar (ACP_DMA_ATTR_SHAREDMEM_TO_DAGB_ONION << 16) | 2337c31335aSMaruthi Srinivas Bayyavarapu (size / 2); 2347c31335aSMaruthi Srinivas Bayyavarapu } 235aac89748SVijendar Mukunda } 2367c31335aSMaruthi Srinivas Bayyavarapu config_dma_descriptor_in_sram(acp_mmio, dma_dscr_idx, 2377c31335aSMaruthi Srinivas Bayyavarapu &dmadscr[i]); 2387c31335aSMaruthi Srinivas Bayyavarapu } 2394376a86cSMukunda, Vijendar config_acp_dma_channel(acp_mmio, ch, 2404376a86cSMukunda, Vijendar dma_dscr_idx - 1, 2417c31335aSMaruthi Srinivas Bayyavarapu NUM_DSCRS_PER_CHANNEL, 2427c31335aSMaruthi Srinivas Bayyavarapu ACP_DMA_PRIORITY_LEVEL_NORMAL); 2437c31335aSMaruthi Srinivas Bayyavarapu } 2447c31335aSMaruthi Srinivas Bayyavarapu 24513838c11SMukunda, Vijendar /* 24613838c11SMukunda, Vijendar * Initialize the DMA descriptor information for transfer between 2477c31335aSMaruthi Srinivas Bayyavarapu * ACP SRAM <-> I2S 2487c31335aSMaruthi Srinivas Bayyavarapu */ 2494376a86cSMukunda, Vijendar static void set_acp_to_i2s_dma_descriptors(void __iomem *acp_mmio, u32 size, 2504376a86cSMukunda, Vijendar int direction, u32 sram_bank, 2514376a86cSMukunda, Vijendar u16 destination, u16 ch, 2524376a86cSMukunda, Vijendar u16 dma_dscr_idx, u32 asic_type) 2537c31335aSMaruthi Srinivas Bayyavarapu { 2547c31335aSMaruthi Srinivas Bayyavarapu u16 i; 2557c31335aSMaruthi Srinivas Bayyavarapu acp_dma_dscr_transfer_t dmadscr[NUM_DSCRS_PER_CHANNEL]; 2567c31335aSMaruthi Srinivas Bayyavarapu 2577c31335aSMaruthi Srinivas Bayyavarapu for (i = 0; i < NUM_DSCRS_PER_CHANNEL; i++) { 2587c31335aSMaruthi Srinivas Bayyavarapu dmadscr[i].xfer_val = 0; 2597c31335aSMaruthi Srinivas Bayyavarapu if (direction == SNDRV_PCM_STREAM_PLAYBACK) { 2604376a86cSMukunda, Vijendar dma_dscr_idx = dma_dscr_idx + i; 2614376a86cSMukunda, Vijendar dmadscr[i].src = sram_bank + (i * (size / 2)); 2627c31335aSMaruthi Srinivas Bayyavarapu /* dmadscr[i].dest is unused by hardware. */ 2637c31335aSMaruthi Srinivas Bayyavarapu dmadscr[i].dest = 0; 2644376a86cSMukunda, Vijendar dmadscr[i].xfer_val |= BIT(22) | (destination << 16) | 2657c31335aSMaruthi Srinivas Bayyavarapu (size / 2); 2667c31335aSMaruthi Srinivas Bayyavarapu } else { 2674376a86cSMukunda, Vijendar dma_dscr_idx = dma_dscr_idx + i; 2687c31335aSMaruthi Srinivas Bayyavarapu /* dmadscr[i].src is unused by hardware. */ 2697c31335aSMaruthi Srinivas Bayyavarapu dmadscr[i].src = 0; 270aac89748SVijendar Mukunda dmadscr[i].dest = 2714376a86cSMukunda, Vijendar sram_bank + (i * (size / 2)); 2727c31335aSMaruthi Srinivas Bayyavarapu dmadscr[i].xfer_val |= BIT(22) | 2734376a86cSMukunda, Vijendar (destination << 16) | (size / 2); 2747c31335aSMaruthi Srinivas Bayyavarapu } 2757c31335aSMaruthi Srinivas Bayyavarapu config_dma_descriptor_in_sram(acp_mmio, dma_dscr_idx, 2767c31335aSMaruthi Srinivas Bayyavarapu &dmadscr[i]); 2777c31335aSMaruthi Srinivas Bayyavarapu } 2787c31335aSMaruthi Srinivas Bayyavarapu /* Configure the DMA channel with the above descriptore */ 2794376a86cSMukunda, Vijendar config_acp_dma_channel(acp_mmio, ch, dma_dscr_idx - 1, 2807c31335aSMaruthi Srinivas Bayyavarapu NUM_DSCRS_PER_CHANNEL, 2817c31335aSMaruthi Srinivas Bayyavarapu ACP_DMA_PRIORITY_LEVEL_NORMAL); 2827c31335aSMaruthi Srinivas Bayyavarapu } 2837c31335aSMaruthi Srinivas Bayyavarapu 2847c31335aSMaruthi Srinivas Bayyavarapu /* Create page table entries in ACP SRAM for the allocated memory */ 2857c31335aSMaruthi Srinivas Bayyavarapu static void acp_pte_config(void __iomem *acp_mmio, struct page *pg, 2867c31335aSMaruthi Srinivas Bayyavarapu u16 num_of_pages, u32 pte_offset) 2877c31335aSMaruthi Srinivas Bayyavarapu { 2887c31335aSMaruthi Srinivas Bayyavarapu u16 page_idx; 2897c31335aSMaruthi Srinivas Bayyavarapu u64 addr; 2907c31335aSMaruthi Srinivas Bayyavarapu u32 low; 2917c31335aSMaruthi Srinivas Bayyavarapu u32 high; 2927c31335aSMaruthi Srinivas Bayyavarapu u32 offset; 2937c31335aSMaruthi Srinivas Bayyavarapu 2947c31335aSMaruthi Srinivas Bayyavarapu offset = ACP_DAGB_GRP_SRBM_SRAM_BASE_OFFSET + (pte_offset * 8); 2957c31335aSMaruthi Srinivas Bayyavarapu for (page_idx = 0; page_idx < (num_of_pages); page_idx++) { 2967c31335aSMaruthi Srinivas Bayyavarapu /* Load the low address of page int ACP SRAM through SRBM */ 2977c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write((offset + (page_idx * 8)), 2987c31335aSMaruthi Srinivas Bayyavarapu acp_mmio, mmACP_SRBM_Targ_Idx_Addr); 2997c31335aSMaruthi Srinivas Bayyavarapu addr = page_to_phys(pg); 3007c31335aSMaruthi Srinivas Bayyavarapu 3017c31335aSMaruthi Srinivas Bayyavarapu low = lower_32_bits(addr); 3027c31335aSMaruthi Srinivas Bayyavarapu high = upper_32_bits(addr); 3037c31335aSMaruthi Srinivas Bayyavarapu 3047c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(low, acp_mmio, mmACP_SRBM_Targ_Idx_Data); 3057c31335aSMaruthi Srinivas Bayyavarapu 3067c31335aSMaruthi Srinivas Bayyavarapu /* Load the High address of page int ACP SRAM through SRBM */ 3077c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write((offset + (page_idx * 8) + 4), 3087c31335aSMaruthi Srinivas Bayyavarapu acp_mmio, mmACP_SRBM_Targ_Idx_Addr); 3097c31335aSMaruthi Srinivas Bayyavarapu 3107c31335aSMaruthi Srinivas Bayyavarapu /* page enable in ACP */ 3117c31335aSMaruthi Srinivas Bayyavarapu high |= BIT(31); 3127c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(high, acp_mmio, mmACP_SRBM_Targ_Idx_Data); 3137c31335aSMaruthi Srinivas Bayyavarapu 3147c31335aSMaruthi Srinivas Bayyavarapu /* Move to next physically contiguos page */ 3157c31335aSMaruthi Srinivas Bayyavarapu pg++; 3167c31335aSMaruthi Srinivas Bayyavarapu } 3177c31335aSMaruthi Srinivas Bayyavarapu } 3187c31335aSMaruthi Srinivas Bayyavarapu 3197c31335aSMaruthi Srinivas Bayyavarapu static void config_acp_dma(void __iomem *acp_mmio, 3208349b7f5SMukunda, Vijendar struct audio_substream_data *rtd, 321aac89748SVijendar Mukunda u32 asic_type) 3227c31335aSMaruthi Srinivas Bayyavarapu { 3238349b7f5SMukunda, Vijendar acp_pte_config(acp_mmio, rtd->pg, rtd->num_of_pages, 324e188c525SMukunda, Vijendar rtd->pte_offset); 3257c31335aSMaruthi Srinivas Bayyavarapu /* Configure System memory <-> ACP SRAM DMA descriptors */ 3268349b7f5SMukunda, Vijendar set_acp_sysmem_dma_descriptors(acp_mmio, rtd->size, 327e188c525SMukunda, Vijendar rtd->direction, rtd->pte_offset, 32818e8a40dSMukunda, Vijendar rtd->ch1, rtd->sram_bank, 3298769bb55SVijendar Mukunda rtd->dma_dscr_idx_1, asic_type); 3307c31335aSMaruthi Srinivas Bayyavarapu /* Configure ACP SRAM <-> I2S DMA descriptors */ 3318349b7f5SMukunda, Vijendar set_acp_to_i2s_dma_descriptors(acp_mmio, rtd->size, 33218e8a40dSMukunda, Vijendar rtd->direction, rtd->sram_bank, 3338769bb55SVijendar Mukunda rtd->destination, rtd->ch2, 3348769bb55SVijendar Mukunda rtd->dma_dscr_idx_2, asic_type); 3357c31335aSMaruthi Srinivas Bayyavarapu } 3367c31335aSMaruthi Srinivas Bayyavarapu 3377c31335aSMaruthi Srinivas Bayyavarapu /* Start a given DMA channel transfer */ 3387c31335aSMaruthi Srinivas Bayyavarapu static void acp_dma_start(void __iomem *acp_mmio, 3397c31335aSMaruthi Srinivas Bayyavarapu u16 ch_num, bool is_circular) 3407c31335aSMaruthi Srinivas Bayyavarapu { 3417c31335aSMaruthi Srinivas Bayyavarapu u32 dma_ctrl; 3427c31335aSMaruthi Srinivas Bayyavarapu 3437c31335aSMaruthi Srinivas Bayyavarapu /* read the dma control register and disable the channel run field */ 3447c31335aSMaruthi Srinivas Bayyavarapu dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 3457c31335aSMaruthi Srinivas Bayyavarapu 3467c31335aSMaruthi Srinivas Bayyavarapu /* Invalidating the DAGB cache */ 3477c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(1, acp_mmio, mmACP_DAGB_ATU_CTRL); 3487c31335aSMaruthi Srinivas Bayyavarapu 34913838c11SMukunda, Vijendar /* 35013838c11SMukunda, Vijendar * configure the DMA channel and start the DMA transfer 3517c31335aSMaruthi Srinivas Bayyavarapu * set dmachrun bit to start the transfer and enable the 3527c31335aSMaruthi Srinivas Bayyavarapu * interrupt on completion of the dma transfer 3537c31335aSMaruthi Srinivas Bayyavarapu */ 3547c31335aSMaruthi Srinivas Bayyavarapu dma_ctrl |= ACP_DMA_CNTL_0__DMAChRun_MASK; 3557c31335aSMaruthi Srinivas Bayyavarapu 3567c31335aSMaruthi Srinivas Bayyavarapu switch (ch_num) { 3577c31335aSMaruthi Srinivas Bayyavarapu case ACP_TO_I2S_DMA_CH_NUM: 3587c31335aSMaruthi Srinivas Bayyavarapu case ACP_TO_SYSRAM_CH_NUM: 3597c31335aSMaruthi Srinivas Bayyavarapu case I2S_TO_ACP_DMA_CH_NUM: 3607c31335aSMaruthi Srinivas Bayyavarapu dma_ctrl |= ACP_DMA_CNTL_0__DMAChIOCEn_MASK; 3617c31335aSMaruthi Srinivas Bayyavarapu break; 3627c31335aSMaruthi Srinivas Bayyavarapu default: 3637c31335aSMaruthi Srinivas Bayyavarapu dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChIOCEn_MASK; 3647c31335aSMaruthi Srinivas Bayyavarapu break; 3657c31335aSMaruthi Srinivas Bayyavarapu } 3667c31335aSMaruthi Srinivas Bayyavarapu 3677c31335aSMaruthi Srinivas Bayyavarapu /* enable for ACP SRAM to/from I2S DMA channel */ 3687c31335aSMaruthi Srinivas Bayyavarapu if (is_circular == true) 3697c31335aSMaruthi Srinivas Bayyavarapu dma_ctrl |= ACP_DMA_CNTL_0__Circular_DMA_En_MASK; 3707c31335aSMaruthi Srinivas Bayyavarapu else 3717c31335aSMaruthi Srinivas Bayyavarapu dma_ctrl &= ~ACP_DMA_CNTL_0__Circular_DMA_En_MASK; 3727c31335aSMaruthi Srinivas Bayyavarapu 3737c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 3747c31335aSMaruthi Srinivas Bayyavarapu } 3757c31335aSMaruthi Srinivas Bayyavarapu 3767c31335aSMaruthi Srinivas Bayyavarapu /* Stop a given DMA channel transfer */ 3777c31335aSMaruthi Srinivas Bayyavarapu static int acp_dma_stop(void __iomem *acp_mmio, u8 ch_num) 3787c31335aSMaruthi Srinivas Bayyavarapu { 3797c31335aSMaruthi Srinivas Bayyavarapu u32 dma_ctrl; 3807c31335aSMaruthi Srinivas Bayyavarapu u32 dma_ch_sts; 3817c31335aSMaruthi Srinivas Bayyavarapu u32 count = ACP_DMA_RESET_TIME; 3827c31335aSMaruthi Srinivas Bayyavarapu 3837c31335aSMaruthi Srinivas Bayyavarapu dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 3847c31335aSMaruthi Srinivas Bayyavarapu 38513838c11SMukunda, Vijendar /* 38613838c11SMukunda, Vijendar * clear the dma control register fields before writing zero 3877c31335aSMaruthi Srinivas Bayyavarapu * in reset bit 3887c31335aSMaruthi Srinivas Bayyavarapu */ 3897c31335aSMaruthi Srinivas Bayyavarapu dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRun_MASK; 3907c31335aSMaruthi Srinivas Bayyavarapu dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChIOCEn_MASK; 3917c31335aSMaruthi Srinivas Bayyavarapu 3927c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 3937c31335aSMaruthi Srinivas Bayyavarapu dma_ch_sts = acp_reg_read(acp_mmio, mmACP_DMA_CH_STS); 3947c31335aSMaruthi Srinivas Bayyavarapu 3957c31335aSMaruthi Srinivas Bayyavarapu if (dma_ch_sts & BIT(ch_num)) { 39613838c11SMukunda, Vijendar /* 39713838c11SMukunda, Vijendar * set the reset bit for this channel to stop the dma 3987c31335aSMaruthi Srinivas Bayyavarapu * transfer 3997c31335aSMaruthi Srinivas Bayyavarapu */ 4007c31335aSMaruthi Srinivas Bayyavarapu dma_ctrl |= ACP_DMA_CNTL_0__DMAChRst_MASK; 4017c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 4027c31335aSMaruthi Srinivas Bayyavarapu } 4037c31335aSMaruthi Srinivas Bayyavarapu 4047c31335aSMaruthi Srinivas Bayyavarapu /* check the channel status bit for some time and return the status */ 4057c31335aSMaruthi Srinivas Bayyavarapu while (true) { 4067c31335aSMaruthi Srinivas Bayyavarapu dma_ch_sts = acp_reg_read(acp_mmio, mmACP_DMA_CH_STS); 4077c31335aSMaruthi Srinivas Bayyavarapu if (!(dma_ch_sts & BIT(ch_num))) { 40813838c11SMukunda, Vijendar /* 40913838c11SMukunda, Vijendar * clear the reset flag after successfully stopping 4107c31335aSMaruthi Srinivas Bayyavarapu * the dma transfer and break from the loop 4117c31335aSMaruthi Srinivas Bayyavarapu */ 4127c31335aSMaruthi Srinivas Bayyavarapu dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRst_MASK; 4137c31335aSMaruthi Srinivas Bayyavarapu 4147c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 4157c31335aSMaruthi Srinivas Bayyavarapu + ch_num); 4167c31335aSMaruthi Srinivas Bayyavarapu break; 4177c31335aSMaruthi Srinivas Bayyavarapu } 4187c31335aSMaruthi Srinivas Bayyavarapu if (--count == 0) { 4197c31335aSMaruthi Srinivas Bayyavarapu pr_err("Failed to stop ACP DMA channel : %d\n", ch_num); 4207c31335aSMaruthi Srinivas Bayyavarapu return -ETIMEDOUT; 4217c31335aSMaruthi Srinivas Bayyavarapu } 4227c31335aSMaruthi Srinivas Bayyavarapu udelay(100); 4237c31335aSMaruthi Srinivas Bayyavarapu } 4247c31335aSMaruthi Srinivas Bayyavarapu return 0; 4257c31335aSMaruthi Srinivas Bayyavarapu } 4267c31335aSMaruthi Srinivas Bayyavarapu 427c36d9b3fSMaruthi Srinivas Bayyavarapu static void acp_set_sram_bank_state(void __iomem *acp_mmio, u16 bank, 428c36d9b3fSMaruthi Srinivas Bayyavarapu bool power_on) 429c36d9b3fSMaruthi Srinivas Bayyavarapu { 430c36d9b3fSMaruthi Srinivas Bayyavarapu u32 val, req_reg, sts_reg, sts_reg_mask; 431c36d9b3fSMaruthi Srinivas Bayyavarapu u32 loops = 1000; 432c36d9b3fSMaruthi Srinivas Bayyavarapu 433c36d9b3fSMaruthi Srinivas Bayyavarapu if (bank < 32) { 434c36d9b3fSMaruthi Srinivas Bayyavarapu req_reg = mmACP_MEM_SHUT_DOWN_REQ_LO; 435c36d9b3fSMaruthi Srinivas Bayyavarapu sts_reg = mmACP_MEM_SHUT_DOWN_STS_LO; 436c36d9b3fSMaruthi Srinivas Bayyavarapu sts_reg_mask = 0xFFFFFFFF; 437c36d9b3fSMaruthi Srinivas Bayyavarapu 438c36d9b3fSMaruthi Srinivas Bayyavarapu } else { 439c36d9b3fSMaruthi Srinivas Bayyavarapu bank -= 32; 440c36d9b3fSMaruthi Srinivas Bayyavarapu req_reg = mmACP_MEM_SHUT_DOWN_REQ_HI; 441c36d9b3fSMaruthi Srinivas Bayyavarapu sts_reg = mmACP_MEM_SHUT_DOWN_STS_HI; 442c36d9b3fSMaruthi Srinivas Bayyavarapu sts_reg_mask = 0x0000FFFF; 443c36d9b3fSMaruthi Srinivas Bayyavarapu } 444c36d9b3fSMaruthi Srinivas Bayyavarapu 445c36d9b3fSMaruthi Srinivas Bayyavarapu val = acp_reg_read(acp_mmio, req_reg); 446c36d9b3fSMaruthi Srinivas Bayyavarapu if (val & (1 << bank)) { 447c36d9b3fSMaruthi Srinivas Bayyavarapu /* bank is in off state */ 448c36d9b3fSMaruthi Srinivas Bayyavarapu if (power_on == true) 449c36d9b3fSMaruthi Srinivas Bayyavarapu /* request to on */ 450c36d9b3fSMaruthi Srinivas Bayyavarapu val &= ~(1 << bank); 451c36d9b3fSMaruthi Srinivas Bayyavarapu else 452c36d9b3fSMaruthi Srinivas Bayyavarapu /* request to off */ 453c36d9b3fSMaruthi Srinivas Bayyavarapu return; 454c36d9b3fSMaruthi Srinivas Bayyavarapu } else { 455c36d9b3fSMaruthi Srinivas Bayyavarapu /* bank is in on state */ 456c36d9b3fSMaruthi Srinivas Bayyavarapu if (power_on == false) 457c36d9b3fSMaruthi Srinivas Bayyavarapu /* request to off */ 458c36d9b3fSMaruthi Srinivas Bayyavarapu val |= 1 << bank; 459c36d9b3fSMaruthi Srinivas Bayyavarapu else 460c36d9b3fSMaruthi Srinivas Bayyavarapu /* request to on */ 461c36d9b3fSMaruthi Srinivas Bayyavarapu return; 462c36d9b3fSMaruthi Srinivas Bayyavarapu } 463c36d9b3fSMaruthi Srinivas Bayyavarapu acp_reg_write(val, acp_mmio, req_reg); 464c36d9b3fSMaruthi Srinivas Bayyavarapu 465c36d9b3fSMaruthi Srinivas Bayyavarapu while (acp_reg_read(acp_mmio, sts_reg) != sts_reg_mask) { 466c36d9b3fSMaruthi Srinivas Bayyavarapu if (!loops--) { 467c36d9b3fSMaruthi Srinivas Bayyavarapu pr_err("ACP SRAM bank %d state change failed\n", bank); 468c36d9b3fSMaruthi Srinivas Bayyavarapu break; 469c36d9b3fSMaruthi Srinivas Bayyavarapu } 470c36d9b3fSMaruthi Srinivas Bayyavarapu cpu_relax(); 471c36d9b3fSMaruthi Srinivas Bayyavarapu } 472c36d9b3fSMaruthi Srinivas Bayyavarapu } 473c36d9b3fSMaruthi Srinivas Bayyavarapu 4747c31335aSMaruthi Srinivas Bayyavarapu /* Initialize and bring ACP hardware to default state. */ 475607b39efSVijendar Mukunda static int acp_init(void __iomem *acp_mmio, u32 asic_type) 4767c31335aSMaruthi Srinivas Bayyavarapu { 477c36d9b3fSMaruthi Srinivas Bayyavarapu u16 bank; 4787c31335aSMaruthi Srinivas Bayyavarapu u32 val, count, sram_pte_offset; 4797c31335aSMaruthi Srinivas Bayyavarapu 4807c31335aSMaruthi Srinivas Bayyavarapu /* Assert Soft reset of ACP */ 4817c31335aSMaruthi Srinivas Bayyavarapu val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET); 4827c31335aSMaruthi Srinivas Bayyavarapu 4837c31335aSMaruthi Srinivas Bayyavarapu val |= ACP_SOFT_RESET__SoftResetAud_MASK; 4847c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET); 4857c31335aSMaruthi Srinivas Bayyavarapu 4867c31335aSMaruthi Srinivas Bayyavarapu count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE; 4877c31335aSMaruthi Srinivas Bayyavarapu while (true) { 4887c31335aSMaruthi Srinivas Bayyavarapu val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET); 4897c31335aSMaruthi Srinivas Bayyavarapu if (ACP_SOFT_RESET__SoftResetAudDone_MASK == 4907c31335aSMaruthi Srinivas Bayyavarapu (val & ACP_SOFT_RESET__SoftResetAudDone_MASK)) 4917c31335aSMaruthi Srinivas Bayyavarapu break; 4927c31335aSMaruthi Srinivas Bayyavarapu if (--count == 0) { 4937c31335aSMaruthi Srinivas Bayyavarapu pr_err("Failed to reset ACP\n"); 4947c31335aSMaruthi Srinivas Bayyavarapu return -ETIMEDOUT; 4957c31335aSMaruthi Srinivas Bayyavarapu } 4967c31335aSMaruthi Srinivas Bayyavarapu udelay(100); 4977c31335aSMaruthi Srinivas Bayyavarapu } 4987c31335aSMaruthi Srinivas Bayyavarapu 4997c31335aSMaruthi Srinivas Bayyavarapu /* Enable clock to ACP and wait until the clock is enabled */ 5007c31335aSMaruthi Srinivas Bayyavarapu val = acp_reg_read(acp_mmio, mmACP_CONTROL); 5017c31335aSMaruthi Srinivas Bayyavarapu val = val | ACP_CONTROL__ClkEn_MASK; 5027c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(val, acp_mmio, mmACP_CONTROL); 5037c31335aSMaruthi Srinivas Bayyavarapu 5047c31335aSMaruthi Srinivas Bayyavarapu count = ACP_CLOCK_EN_TIME_OUT_VALUE; 5057c31335aSMaruthi Srinivas Bayyavarapu 5067c31335aSMaruthi Srinivas Bayyavarapu while (true) { 5077c31335aSMaruthi Srinivas Bayyavarapu val = acp_reg_read(acp_mmio, mmACP_STATUS); 5087c31335aSMaruthi Srinivas Bayyavarapu if (val & (u32)0x1) 5097c31335aSMaruthi Srinivas Bayyavarapu break; 5107c31335aSMaruthi Srinivas Bayyavarapu if (--count == 0) { 5117c31335aSMaruthi Srinivas Bayyavarapu pr_err("Failed to reset ACP\n"); 5127c31335aSMaruthi Srinivas Bayyavarapu return -ETIMEDOUT; 5137c31335aSMaruthi Srinivas Bayyavarapu } 5147c31335aSMaruthi Srinivas Bayyavarapu udelay(100); 5157c31335aSMaruthi Srinivas Bayyavarapu } 5167c31335aSMaruthi Srinivas Bayyavarapu 5177c31335aSMaruthi Srinivas Bayyavarapu /* Deassert the SOFT RESET flags */ 5187c31335aSMaruthi Srinivas Bayyavarapu val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET); 5197c31335aSMaruthi Srinivas Bayyavarapu val &= ~ACP_SOFT_RESET__SoftResetAud_MASK; 5207c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET); 5217c31335aSMaruthi Srinivas Bayyavarapu 5227c31335aSMaruthi Srinivas Bayyavarapu /* initiailize Onion control DAGB register */ 5237c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(ACP_ONION_CNTL_DEFAULT, acp_mmio, 5247c31335aSMaruthi Srinivas Bayyavarapu mmACP_AXI2DAGB_ONION_CNTL); 5257c31335aSMaruthi Srinivas Bayyavarapu 5267c31335aSMaruthi Srinivas Bayyavarapu /* initiailize Garlic control DAGB registers */ 5277c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(ACP_GARLIC_CNTL_DEFAULT, acp_mmio, 5287c31335aSMaruthi Srinivas Bayyavarapu mmACP_AXI2DAGB_GARLIC_CNTL); 5297c31335aSMaruthi Srinivas Bayyavarapu 5307c31335aSMaruthi Srinivas Bayyavarapu sram_pte_offset = ACP_DAGB_GRP_SRAM_BASE_ADDRESS | 5317c31335aSMaruthi Srinivas Bayyavarapu ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBSnoopSel_MASK | 5327c31335aSMaruthi Srinivas Bayyavarapu ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBTargetMemSel_MASK | 5337c31335aSMaruthi Srinivas Bayyavarapu ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBGrpEnable_MASK; 5347c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(sram_pte_offset, acp_mmio, mmACP_DAGB_BASE_ADDR_GRP_1); 5357c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(ACP_PAGE_SIZE_4K_ENABLE, acp_mmio, 5367c31335aSMaruthi Srinivas Bayyavarapu mmACP_DAGB_PAGE_SIZE_GRP_1); 5377c31335aSMaruthi Srinivas Bayyavarapu 5387c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(ACP_SRAM_BASE_ADDRESS, acp_mmio, 5397c31335aSMaruthi Srinivas Bayyavarapu mmACP_DMA_DESC_BASE_ADDR); 5407c31335aSMaruthi Srinivas Bayyavarapu 5417c31335aSMaruthi Srinivas Bayyavarapu /* Num of descriptiors in SRAM 0x4, means 256 descriptors;(64 * 4) */ 5427c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(0x4, acp_mmio, mmACP_DMA_DESC_MAX_NUM_DSCR); 5437c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(ACP_EXTERNAL_INTR_CNTL__DMAIOCMask_MASK, 5447c31335aSMaruthi Srinivas Bayyavarapu acp_mmio, mmACP_EXTERNAL_INTR_CNTL); 5457c31335aSMaruthi Srinivas Bayyavarapu 54613838c11SMukunda, Vijendar /* 54713838c11SMukunda, Vijendar * When ACP_TILE_P1 is turned on, all SRAM banks get turned on. 548c36d9b3fSMaruthi Srinivas Bayyavarapu * Now, turn off all of them. This can't be done in 'poweron' of 549c36d9b3fSMaruthi Srinivas Bayyavarapu * ACP pm domain, as this requires ACP to be initialized. 550607b39efSVijendar Mukunda * For Stoney, Memory gating is disabled,i.e SRAM Banks 551607b39efSVijendar Mukunda * won't be turned off. The default state for SRAM banks is ON. 552607b39efSVijendar Mukunda * Setting SRAM bank state code skipped for STONEY platform. 553c36d9b3fSMaruthi Srinivas Bayyavarapu */ 554607b39efSVijendar Mukunda if (asic_type != CHIP_STONEY) { 555c36d9b3fSMaruthi Srinivas Bayyavarapu for (bank = 1; bank < 48; bank++) 556c36d9b3fSMaruthi Srinivas Bayyavarapu acp_set_sram_bank_state(acp_mmio, bank, false); 557607b39efSVijendar Mukunda } 5587c31335aSMaruthi Srinivas Bayyavarapu return 0; 5597c31335aSMaruthi Srinivas Bayyavarapu } 5607c31335aSMaruthi Srinivas Bayyavarapu 5611cce2000SMasahiro Yamada /* Deinitialize ACP */ 5627c31335aSMaruthi Srinivas Bayyavarapu static int acp_deinit(void __iomem *acp_mmio) 5637c31335aSMaruthi Srinivas Bayyavarapu { 5647c31335aSMaruthi Srinivas Bayyavarapu u32 val; 5657c31335aSMaruthi Srinivas Bayyavarapu u32 count; 5667c31335aSMaruthi Srinivas Bayyavarapu 5677c31335aSMaruthi Srinivas Bayyavarapu /* Assert Soft reset of ACP */ 5687c31335aSMaruthi Srinivas Bayyavarapu val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET); 5697c31335aSMaruthi Srinivas Bayyavarapu 5707c31335aSMaruthi Srinivas Bayyavarapu val |= ACP_SOFT_RESET__SoftResetAud_MASK; 5717c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET); 5727c31335aSMaruthi Srinivas Bayyavarapu 5737c31335aSMaruthi Srinivas Bayyavarapu count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE; 5747c31335aSMaruthi Srinivas Bayyavarapu while (true) { 5757c31335aSMaruthi Srinivas Bayyavarapu val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET); 5767c31335aSMaruthi Srinivas Bayyavarapu if (ACP_SOFT_RESET__SoftResetAudDone_MASK == 5777c31335aSMaruthi Srinivas Bayyavarapu (val & ACP_SOFT_RESET__SoftResetAudDone_MASK)) 5787c31335aSMaruthi Srinivas Bayyavarapu break; 5797c31335aSMaruthi Srinivas Bayyavarapu if (--count == 0) { 5807c31335aSMaruthi Srinivas Bayyavarapu pr_err("Failed to reset ACP\n"); 5817c31335aSMaruthi Srinivas Bayyavarapu return -ETIMEDOUT; 5827c31335aSMaruthi Srinivas Bayyavarapu } 5837c31335aSMaruthi Srinivas Bayyavarapu udelay(100); 5847c31335aSMaruthi Srinivas Bayyavarapu } 58513838c11SMukunda, Vijendar /* Disable ACP clock */ 5867c31335aSMaruthi Srinivas Bayyavarapu val = acp_reg_read(acp_mmio, mmACP_CONTROL); 5877c31335aSMaruthi Srinivas Bayyavarapu val &= ~ACP_CONTROL__ClkEn_MASK; 5887c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(val, acp_mmio, mmACP_CONTROL); 5897c31335aSMaruthi Srinivas Bayyavarapu 5907c31335aSMaruthi Srinivas Bayyavarapu count = ACP_CLOCK_EN_TIME_OUT_VALUE; 5917c31335aSMaruthi Srinivas Bayyavarapu 5927c31335aSMaruthi Srinivas Bayyavarapu while (true) { 5937c31335aSMaruthi Srinivas Bayyavarapu val = acp_reg_read(acp_mmio, mmACP_STATUS); 5947c31335aSMaruthi Srinivas Bayyavarapu if (!(val & (u32)0x1)) 5957c31335aSMaruthi Srinivas Bayyavarapu break; 5967c31335aSMaruthi Srinivas Bayyavarapu if (--count == 0) { 5977c31335aSMaruthi Srinivas Bayyavarapu pr_err("Failed to reset ACP\n"); 5987c31335aSMaruthi Srinivas Bayyavarapu return -ETIMEDOUT; 5997c31335aSMaruthi Srinivas Bayyavarapu } 6007c31335aSMaruthi Srinivas Bayyavarapu udelay(100); 6017c31335aSMaruthi Srinivas Bayyavarapu } 6027c31335aSMaruthi Srinivas Bayyavarapu return 0; 6037c31335aSMaruthi Srinivas Bayyavarapu } 6047c31335aSMaruthi Srinivas Bayyavarapu 6057c31335aSMaruthi Srinivas Bayyavarapu /* ACP DMA irq handler routine for playback, capture usecases */ 6067c31335aSMaruthi Srinivas Bayyavarapu static irqreturn_t dma_irq_handler(int irq, void *arg) 6077c31335aSMaruthi Srinivas Bayyavarapu { 6087c31335aSMaruthi Srinivas Bayyavarapu u16 dscr_idx; 6097c31335aSMaruthi Srinivas Bayyavarapu u32 intr_flag, ext_intr_status; 6107c31335aSMaruthi Srinivas Bayyavarapu struct audio_drv_data *irq_data; 6117c31335aSMaruthi Srinivas Bayyavarapu void __iomem *acp_mmio; 6127c31335aSMaruthi Srinivas Bayyavarapu struct device *dev = arg; 6137c31335aSMaruthi Srinivas Bayyavarapu bool valid_irq = false; 6147c31335aSMaruthi Srinivas Bayyavarapu 6157c31335aSMaruthi Srinivas Bayyavarapu irq_data = dev_get_drvdata(dev); 6167c31335aSMaruthi Srinivas Bayyavarapu acp_mmio = irq_data->acp_mmio; 6177c31335aSMaruthi Srinivas Bayyavarapu 6187c31335aSMaruthi Srinivas Bayyavarapu ext_intr_status = acp_reg_read(acp_mmio, mmACP_EXTERNAL_INTR_STAT); 6197c31335aSMaruthi Srinivas Bayyavarapu intr_flag = (((ext_intr_status & 6207c31335aSMaruthi Srinivas Bayyavarapu ACP_EXTERNAL_INTR_STAT__DMAIOCStat_MASK) >> 6217c31335aSMaruthi Srinivas Bayyavarapu ACP_EXTERNAL_INTR_STAT__DMAIOCStat__SHIFT)); 6227c31335aSMaruthi Srinivas Bayyavarapu 6237c31335aSMaruthi Srinivas Bayyavarapu if ((intr_flag & BIT(ACP_TO_I2S_DMA_CH_NUM)) != 0) { 6247c31335aSMaruthi Srinivas Bayyavarapu valid_irq = true; 6257c31335aSMaruthi Srinivas Bayyavarapu if (acp_reg_read(acp_mmio, mmACP_DMA_CUR_DSCR_13) == 6267c31335aSMaruthi Srinivas Bayyavarapu PLAYBACK_START_DMA_DESCR_CH13) 6277c31335aSMaruthi Srinivas Bayyavarapu dscr_idx = PLAYBACK_END_DMA_DESCR_CH12; 62831c45b3eSVijendar Mukunda else 62931c45b3eSVijendar Mukunda dscr_idx = PLAYBACK_START_DMA_DESCR_CH12; 6307c31335aSMaruthi Srinivas Bayyavarapu config_acp_dma_channel(acp_mmio, SYSRAM_TO_ACP_CH_NUM, dscr_idx, 6317c31335aSMaruthi Srinivas Bayyavarapu 1, 0); 6327c31335aSMaruthi Srinivas Bayyavarapu acp_dma_start(acp_mmio, SYSRAM_TO_ACP_CH_NUM, false); 6337c31335aSMaruthi Srinivas Bayyavarapu 634e21358c4SMukunda, Vijendar snd_pcm_period_elapsed(irq_data->play_i2ssp_stream); 6357c31335aSMaruthi Srinivas Bayyavarapu 6367c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write((intr_flag & BIT(ACP_TO_I2S_DMA_CH_NUM)) << 16, 6377c31335aSMaruthi Srinivas Bayyavarapu acp_mmio, mmACP_EXTERNAL_INTR_STAT); 6387c31335aSMaruthi Srinivas Bayyavarapu } 6397c31335aSMaruthi Srinivas Bayyavarapu 6407c31335aSMaruthi Srinivas Bayyavarapu if ((intr_flag & BIT(I2S_TO_ACP_DMA_CH_NUM)) != 0) { 6417c31335aSMaruthi Srinivas Bayyavarapu valid_irq = true; 6427c31335aSMaruthi Srinivas Bayyavarapu if (acp_reg_read(acp_mmio, mmACP_DMA_CUR_DSCR_15) == 6437c31335aSMaruthi Srinivas Bayyavarapu CAPTURE_START_DMA_DESCR_CH15) 6447c31335aSMaruthi Srinivas Bayyavarapu dscr_idx = CAPTURE_END_DMA_DESCR_CH14; 6457c31335aSMaruthi Srinivas Bayyavarapu else 6467c31335aSMaruthi Srinivas Bayyavarapu dscr_idx = CAPTURE_START_DMA_DESCR_CH14; 6477c31335aSMaruthi Srinivas Bayyavarapu config_acp_dma_channel(acp_mmio, ACP_TO_SYSRAM_CH_NUM, dscr_idx, 6487c31335aSMaruthi Srinivas Bayyavarapu 1, 0); 6497c31335aSMaruthi Srinivas Bayyavarapu acp_dma_start(acp_mmio, ACP_TO_SYSRAM_CH_NUM, false); 6507c31335aSMaruthi Srinivas Bayyavarapu 6517c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write((intr_flag & BIT(I2S_TO_ACP_DMA_CH_NUM)) << 16, 6527c31335aSMaruthi Srinivas Bayyavarapu acp_mmio, mmACP_EXTERNAL_INTR_STAT); 6537c31335aSMaruthi Srinivas Bayyavarapu } 6547c31335aSMaruthi Srinivas Bayyavarapu 6557c31335aSMaruthi Srinivas Bayyavarapu if ((intr_flag & BIT(ACP_TO_SYSRAM_CH_NUM)) != 0) { 6567c31335aSMaruthi Srinivas Bayyavarapu valid_irq = true; 657e21358c4SMukunda, Vijendar snd_pcm_period_elapsed(irq_data->capture_i2ssp_stream); 6587c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write((intr_flag & BIT(ACP_TO_SYSRAM_CH_NUM)) << 16, 6597c31335aSMaruthi Srinivas Bayyavarapu acp_mmio, mmACP_EXTERNAL_INTR_STAT); 6607c31335aSMaruthi Srinivas Bayyavarapu } 6617c31335aSMaruthi Srinivas Bayyavarapu 6627c31335aSMaruthi Srinivas Bayyavarapu if (valid_irq) 6637c31335aSMaruthi Srinivas Bayyavarapu return IRQ_HANDLED; 6647c31335aSMaruthi Srinivas Bayyavarapu else 6657c31335aSMaruthi Srinivas Bayyavarapu return IRQ_NONE; 6667c31335aSMaruthi Srinivas Bayyavarapu } 6677c31335aSMaruthi Srinivas Bayyavarapu 6687c31335aSMaruthi Srinivas Bayyavarapu static int acp_dma_open(struct snd_pcm_substream *substream) 6697c31335aSMaruthi Srinivas Bayyavarapu { 670c36d9b3fSMaruthi Srinivas Bayyavarapu u16 bank; 6717c31335aSMaruthi Srinivas Bayyavarapu int ret = 0; 6727c31335aSMaruthi Srinivas Bayyavarapu struct snd_pcm_runtime *runtime = substream->runtime; 6737c31335aSMaruthi Srinivas Bayyavarapu struct snd_soc_pcm_runtime *prtd = substream->private_data; 67413838c11SMukunda, Vijendar struct snd_soc_component *component = snd_soc_rtdcom_lookup(prtd, 67513838c11SMukunda, Vijendar DRV_NAME); 676a1042a42SKuninori Morimoto struct audio_drv_data *intr_data = dev_get_drvdata(component->dev); 6777c31335aSMaruthi Srinivas Bayyavarapu struct audio_substream_data *adata = 6787c31335aSMaruthi Srinivas Bayyavarapu kzalloc(sizeof(struct audio_substream_data), GFP_KERNEL); 67913838c11SMukunda, Vijendar if (!adata) 6807c31335aSMaruthi Srinivas Bayyavarapu return -ENOMEM; 6817c31335aSMaruthi Srinivas Bayyavarapu 6829c7d6fabSVijendar Mukunda if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 6839c7d6fabSVijendar Mukunda switch (intr_data->asic_type) { 6849c7d6fabSVijendar Mukunda case CHIP_STONEY: 6859c7d6fabSVijendar Mukunda runtime->hw = acp_st_pcm_hardware_playback; 6869c7d6fabSVijendar Mukunda break; 6879c7d6fabSVijendar Mukunda default: 6887c31335aSMaruthi Srinivas Bayyavarapu runtime->hw = acp_pcm_hardware_playback; 6899c7d6fabSVijendar Mukunda } 6909c7d6fabSVijendar Mukunda } else { 6919c7d6fabSVijendar Mukunda switch (intr_data->asic_type) { 6929c7d6fabSVijendar Mukunda case CHIP_STONEY: 6939c7d6fabSVijendar Mukunda runtime->hw = acp_st_pcm_hardware_capture; 6949c7d6fabSVijendar Mukunda break; 6959c7d6fabSVijendar Mukunda default: 6967c31335aSMaruthi Srinivas Bayyavarapu runtime->hw = acp_pcm_hardware_capture; 6979c7d6fabSVijendar Mukunda } 6989c7d6fabSVijendar Mukunda } 6997c31335aSMaruthi Srinivas Bayyavarapu 7007c31335aSMaruthi Srinivas Bayyavarapu ret = snd_pcm_hw_constraint_integer(runtime, 7017c31335aSMaruthi Srinivas Bayyavarapu SNDRV_PCM_HW_PARAM_PERIODS); 7027c31335aSMaruthi Srinivas Bayyavarapu if (ret < 0) { 703a1042a42SKuninori Morimoto dev_err(component->dev, "set integer constraint failed\n"); 704cde6bcd5SDan Carpenter kfree(adata); 7057c31335aSMaruthi Srinivas Bayyavarapu return ret; 7067c31335aSMaruthi Srinivas Bayyavarapu } 7077c31335aSMaruthi Srinivas Bayyavarapu 7087c31335aSMaruthi Srinivas Bayyavarapu adata->acp_mmio = intr_data->acp_mmio; 7097c31335aSMaruthi Srinivas Bayyavarapu runtime->private_data = adata; 7107c31335aSMaruthi Srinivas Bayyavarapu 71113838c11SMukunda, Vijendar /* 71213838c11SMukunda, Vijendar * Enable ACP irq, when neither playback or capture streams are 7137c31335aSMaruthi Srinivas Bayyavarapu * active by the time when a new stream is being opened. 7147c31335aSMaruthi Srinivas Bayyavarapu * This enablement is not required for another stream, if current 7157c31335aSMaruthi Srinivas Bayyavarapu * stream is not closed 7167c31335aSMaruthi Srinivas Bayyavarapu */ 717e21358c4SMukunda, Vijendar if (!intr_data->play_i2ssp_stream && !intr_data->capture_i2ssp_stream) 7187c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB); 7197c31335aSMaruthi Srinivas Bayyavarapu 720c36d9b3fSMaruthi Srinivas Bayyavarapu if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 721e21358c4SMukunda, Vijendar intr_data->play_i2ssp_stream = substream; 72213838c11SMukunda, Vijendar /* 72313838c11SMukunda, Vijendar * For Stoney, Memory gating is disabled,i.e SRAM Banks 724607b39efSVijendar Mukunda * won't be turned off. The default state for SRAM banks is ON. 725607b39efSVijendar Mukunda * Setting SRAM bank state code skipped for STONEY platform. 726607b39efSVijendar Mukunda */ 727607b39efSVijendar Mukunda if (intr_data->asic_type != CHIP_STONEY) { 728c36d9b3fSMaruthi Srinivas Bayyavarapu for (bank = 1; bank <= 4; bank++) 729607b39efSVijendar Mukunda acp_set_sram_bank_state(intr_data->acp_mmio, 730607b39efSVijendar Mukunda bank, true); 731607b39efSVijendar Mukunda } 732c36d9b3fSMaruthi Srinivas Bayyavarapu } else { 733e21358c4SMukunda, Vijendar intr_data->capture_i2ssp_stream = substream; 734607b39efSVijendar Mukunda if (intr_data->asic_type != CHIP_STONEY) { 735c36d9b3fSMaruthi Srinivas Bayyavarapu for (bank = 5; bank <= 8; bank++) 736607b39efSVijendar Mukunda acp_set_sram_bank_state(intr_data->acp_mmio, 737607b39efSVijendar Mukunda bank, true); 738607b39efSVijendar Mukunda } 739c36d9b3fSMaruthi Srinivas Bayyavarapu } 7407c31335aSMaruthi Srinivas Bayyavarapu 7417c31335aSMaruthi Srinivas Bayyavarapu return 0; 7427c31335aSMaruthi Srinivas Bayyavarapu } 7437c31335aSMaruthi Srinivas Bayyavarapu 7447c31335aSMaruthi Srinivas Bayyavarapu static int acp_dma_hw_params(struct snd_pcm_substream *substream, 7457c31335aSMaruthi Srinivas Bayyavarapu struct snd_pcm_hw_params *params) 7467c31335aSMaruthi Srinivas Bayyavarapu { 7477c31335aSMaruthi Srinivas Bayyavarapu int status; 7487c31335aSMaruthi Srinivas Bayyavarapu uint64_t size; 749a37d48e3SVijendar Mukunda u32 val = 0; 7507c31335aSMaruthi Srinivas Bayyavarapu struct page *pg; 7517c31335aSMaruthi Srinivas Bayyavarapu struct snd_pcm_runtime *runtime; 7527c31335aSMaruthi Srinivas Bayyavarapu struct audio_substream_data *rtd; 753aac89748SVijendar Mukunda struct snd_soc_pcm_runtime *prtd = substream->private_data; 75413838c11SMukunda, Vijendar struct snd_soc_component *component = snd_soc_rtdcom_lookup(prtd, 75513838c11SMukunda, Vijendar DRV_NAME); 756a1042a42SKuninori Morimoto struct audio_drv_data *adata = dev_get_drvdata(component->dev); 7577c31335aSMaruthi Srinivas Bayyavarapu 7587c31335aSMaruthi Srinivas Bayyavarapu runtime = substream->runtime; 7597c31335aSMaruthi Srinivas Bayyavarapu rtd = runtime->private_data; 7607c31335aSMaruthi Srinivas Bayyavarapu 7617c31335aSMaruthi Srinivas Bayyavarapu if (WARN_ON(!rtd)) 7627c31335aSMaruthi Srinivas Bayyavarapu return -EINVAL; 7637c31335aSMaruthi Srinivas Bayyavarapu 764a37d48e3SVijendar Mukunda if (adata->asic_type == CHIP_STONEY) { 76513838c11SMukunda, Vijendar val = acp_reg_read(adata->acp_mmio, 76613838c11SMukunda, Vijendar mmACP_I2S_16BIT_RESOLUTION_EN); 767a37d48e3SVijendar Mukunda if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 768a37d48e3SVijendar Mukunda val |= ACP_I2S_SP_16BIT_RESOLUTION_EN; 769a37d48e3SVijendar Mukunda else 770a37d48e3SVijendar Mukunda val |= ACP_I2S_MIC_16BIT_RESOLUTION_EN; 77113838c11SMukunda, Vijendar acp_reg_write(val, adata->acp_mmio, 77213838c11SMukunda, Vijendar mmACP_I2S_16BIT_RESOLUTION_EN); 773a37d48e3SVijendar Mukunda } 7748769bb55SVijendar Mukunda 7758769bb55SVijendar Mukunda if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 776e188c525SMukunda, Vijendar switch (adata->asic_type) { 777e188c525SMukunda, Vijendar case CHIP_STONEY: 778e188c525SMukunda, Vijendar rtd->pte_offset = ACP_ST_PLAYBACK_PTE_OFFSET; 779e188c525SMukunda, Vijendar break; 780e188c525SMukunda, Vijendar default: 781e188c525SMukunda, Vijendar rtd->pte_offset = ACP_PLAYBACK_PTE_OFFSET; 782e188c525SMukunda, Vijendar } 7838769bb55SVijendar Mukunda rtd->ch1 = SYSRAM_TO_ACP_CH_NUM; 7848769bb55SVijendar Mukunda rtd->ch2 = ACP_TO_I2S_DMA_CH_NUM; 78518e8a40dSMukunda, Vijendar rtd->sram_bank = ACP_SRAM_BANK_1_ADDRESS; 7868769bb55SVijendar Mukunda rtd->destination = TO_ACP_I2S_1; 7878769bb55SVijendar Mukunda rtd->dma_dscr_idx_1 = PLAYBACK_START_DMA_DESCR_CH12; 7888769bb55SVijendar Mukunda rtd->dma_dscr_idx_2 = PLAYBACK_START_DMA_DESCR_CH13; 7897f004847SVijendar Mukunda rtd->byte_cnt_high_reg_offset = 7907f004847SVijendar Mukunda mmACP_I2S_TRANSMIT_BYTE_CNT_HIGH; 7917f004847SVijendar Mukunda rtd->byte_cnt_low_reg_offset = mmACP_I2S_TRANSMIT_BYTE_CNT_LOW; 7928769bb55SVijendar Mukunda } else { 793e188c525SMukunda, Vijendar switch (adata->asic_type) { 794e188c525SMukunda, Vijendar case CHIP_STONEY: 795e188c525SMukunda, Vijendar rtd->pte_offset = ACP_ST_CAPTURE_PTE_OFFSET; 79618e8a40dSMukunda, Vijendar rtd->sram_bank = ACP_SRAM_BANK_2_ADDRESS; 797e188c525SMukunda, Vijendar break; 798e188c525SMukunda, Vijendar default: 799e188c525SMukunda, Vijendar rtd->pte_offset = ACP_CAPTURE_PTE_OFFSET; 80018e8a40dSMukunda, Vijendar rtd->sram_bank = ACP_SRAM_BANK_5_ADDRESS; 801e188c525SMukunda, Vijendar } 8028769bb55SVijendar Mukunda rtd->ch1 = ACP_TO_SYSRAM_CH_NUM; 8038769bb55SVijendar Mukunda rtd->ch2 = I2S_TO_ACP_DMA_CH_NUM; 8048769bb55SVijendar Mukunda rtd->destination = FROM_ACP_I2S_1; 8058769bb55SVijendar Mukunda rtd->dma_dscr_idx_1 = CAPTURE_START_DMA_DESCR_CH14; 8068769bb55SVijendar Mukunda rtd->dma_dscr_idx_2 = CAPTURE_START_DMA_DESCR_CH15; 8077f004847SVijendar Mukunda rtd->byte_cnt_high_reg_offset = 8087f004847SVijendar Mukunda mmACP_I2S_RECEIVED_BYTE_CNT_HIGH; 8097f004847SVijendar Mukunda rtd->byte_cnt_low_reg_offset = mmACP_I2S_RECEIVED_BYTE_CNT_LOW; 8108769bb55SVijendar Mukunda } 8118769bb55SVijendar Mukunda 8127c31335aSMaruthi Srinivas Bayyavarapu size = params_buffer_bytes(params); 8137c31335aSMaruthi Srinivas Bayyavarapu status = snd_pcm_lib_malloc_pages(substream, size); 8147c31335aSMaruthi Srinivas Bayyavarapu if (status < 0) 8157c31335aSMaruthi Srinivas Bayyavarapu return status; 8167c31335aSMaruthi Srinivas Bayyavarapu 8177c31335aSMaruthi Srinivas Bayyavarapu memset(substream->runtime->dma_area, 0, params_buffer_bytes(params)); 8187c31335aSMaruthi Srinivas Bayyavarapu pg = virt_to_page(substream->dma_buffer.area); 8197c31335aSMaruthi Srinivas Bayyavarapu 82013838c11SMukunda, Vijendar if (pg) { 821c36d9b3fSMaruthi Srinivas Bayyavarapu acp_set_sram_bank_state(rtd->acp_mmio, 0, true); 8227c31335aSMaruthi Srinivas Bayyavarapu /* Save for runtime private data */ 8237c31335aSMaruthi Srinivas Bayyavarapu rtd->pg = pg; 8247c31335aSMaruthi Srinivas Bayyavarapu rtd->order = get_order(size); 8257c31335aSMaruthi Srinivas Bayyavarapu 8267c31335aSMaruthi Srinivas Bayyavarapu /* Fill the page table entries in ACP SRAM */ 8277c31335aSMaruthi Srinivas Bayyavarapu rtd->pg = pg; 8287c31335aSMaruthi Srinivas Bayyavarapu rtd->size = size; 8297c31335aSMaruthi Srinivas Bayyavarapu rtd->num_of_pages = PAGE_ALIGN(size) >> PAGE_SHIFT; 8307c31335aSMaruthi Srinivas Bayyavarapu rtd->direction = substream->stream; 8317c31335aSMaruthi Srinivas Bayyavarapu 832aac89748SVijendar Mukunda config_acp_dma(rtd->acp_mmio, rtd, adata->asic_type); 8337c31335aSMaruthi Srinivas Bayyavarapu status = 0; 8347c31335aSMaruthi Srinivas Bayyavarapu } else { 8357c31335aSMaruthi Srinivas Bayyavarapu status = -ENOMEM; 8367c31335aSMaruthi Srinivas Bayyavarapu } 8377c31335aSMaruthi Srinivas Bayyavarapu return status; 8387c31335aSMaruthi Srinivas Bayyavarapu } 8397c31335aSMaruthi Srinivas Bayyavarapu 8407c31335aSMaruthi Srinivas Bayyavarapu static int acp_dma_hw_free(struct snd_pcm_substream *substream) 8417c31335aSMaruthi Srinivas Bayyavarapu { 8427c31335aSMaruthi Srinivas Bayyavarapu return snd_pcm_lib_free_pages(substream); 8437c31335aSMaruthi Srinivas Bayyavarapu } 8447c31335aSMaruthi Srinivas Bayyavarapu 8457f004847SVijendar Mukunda static u64 acp_get_byte_count(struct audio_substream_data *rtd) 84661add814SVijendar Mukunda { 8477f004847SVijendar Mukunda union acp_dma_count byte_count; 84861add814SVijendar Mukunda 8497f004847SVijendar Mukunda byte_count.bcount.high = acp_reg_read(rtd->acp_mmio, 8507f004847SVijendar Mukunda rtd->byte_cnt_high_reg_offset); 8517f004847SVijendar Mukunda byte_count.bcount.low = acp_reg_read(rtd->acp_mmio, 8527f004847SVijendar Mukunda rtd->byte_cnt_low_reg_offset); 8537f004847SVijendar Mukunda return byte_count.bytescount; 85461add814SVijendar Mukunda } 85561add814SVijendar Mukunda 8567c31335aSMaruthi Srinivas Bayyavarapu static snd_pcm_uframes_t acp_dma_pointer(struct snd_pcm_substream *substream) 8577c31335aSMaruthi Srinivas Bayyavarapu { 85861add814SVijendar Mukunda u32 buffersize; 8597c31335aSMaruthi Srinivas Bayyavarapu u32 pos = 0; 86061add814SVijendar Mukunda u64 bytescount = 0; 8617c31335aSMaruthi Srinivas Bayyavarapu 8627c31335aSMaruthi Srinivas Bayyavarapu struct snd_pcm_runtime *runtime = substream->runtime; 8637c31335aSMaruthi Srinivas Bayyavarapu struct audio_substream_data *rtd = runtime->private_data; 8647c31335aSMaruthi Srinivas Bayyavarapu 8657afa535eSMukunda, Vijendar if (!rtd) 8667afa535eSMukunda, Vijendar return -EINVAL; 8677afa535eSMukunda, Vijendar 86861add814SVijendar Mukunda buffersize = frames_to_bytes(runtime, runtime->buffer_size); 8697f004847SVijendar Mukunda bytescount = acp_get_byte_count(rtd); 87061add814SVijendar Mukunda 8719af8937eSVijendar Mukunda if (bytescount > rtd->bytescount) 8729af8937eSVijendar Mukunda bytescount -= rtd->bytescount; 8737db08b2cSGuenter Roeck pos = do_div(bytescount, buffersize); 8747c31335aSMaruthi Srinivas Bayyavarapu return bytes_to_frames(runtime, pos); 8757c31335aSMaruthi Srinivas Bayyavarapu } 8767c31335aSMaruthi Srinivas Bayyavarapu 8777c31335aSMaruthi Srinivas Bayyavarapu static int acp_dma_mmap(struct snd_pcm_substream *substream, 8787c31335aSMaruthi Srinivas Bayyavarapu struct vm_area_struct *vma) 8797c31335aSMaruthi Srinivas Bayyavarapu { 8807c31335aSMaruthi Srinivas Bayyavarapu return snd_pcm_lib_default_mmap(substream, vma); 8817c31335aSMaruthi Srinivas Bayyavarapu } 8827c31335aSMaruthi Srinivas Bayyavarapu 8837c31335aSMaruthi Srinivas Bayyavarapu static int acp_dma_prepare(struct snd_pcm_substream *substream) 8847c31335aSMaruthi Srinivas Bayyavarapu { 8857c31335aSMaruthi Srinivas Bayyavarapu struct snd_pcm_runtime *runtime = substream->runtime; 8867c31335aSMaruthi Srinivas Bayyavarapu struct audio_substream_data *rtd = runtime->private_data; 8877c31335aSMaruthi Srinivas Bayyavarapu 8887afa535eSMukunda, Vijendar if (!rtd) 8897afa535eSMukunda, Vijendar return -EINVAL; 8908769bb55SVijendar Mukunda 8918769bb55SVijendar Mukunda config_acp_dma_channel(rtd->acp_mmio, 8928769bb55SVijendar Mukunda rtd->ch1, 8938769bb55SVijendar Mukunda rtd->dma_dscr_idx_1, 8947c31335aSMaruthi Srinivas Bayyavarapu NUM_DSCRS_PER_CHANNEL, 0); 8958769bb55SVijendar Mukunda config_acp_dma_channel(rtd->acp_mmio, 8968769bb55SVijendar Mukunda rtd->ch2, 8978769bb55SVijendar Mukunda rtd->dma_dscr_idx_2, 8987c31335aSMaruthi Srinivas Bayyavarapu NUM_DSCRS_PER_CHANNEL, 0); 8997c31335aSMaruthi Srinivas Bayyavarapu return 0; 9007c31335aSMaruthi Srinivas Bayyavarapu } 9017c31335aSMaruthi Srinivas Bayyavarapu 9027c31335aSMaruthi Srinivas Bayyavarapu static int acp_dma_trigger(struct snd_pcm_substream *substream, int cmd) 9037c31335aSMaruthi Srinivas Bayyavarapu { 9047c31335aSMaruthi Srinivas Bayyavarapu int ret; 90531c45b3eSVijendar Mukunda u32 loops = 4000; 90661add814SVijendar Mukunda u64 bytescount = 0; 9077c31335aSMaruthi Srinivas Bayyavarapu 9087c31335aSMaruthi Srinivas Bayyavarapu struct snd_pcm_runtime *runtime = substream->runtime; 9097c31335aSMaruthi Srinivas Bayyavarapu struct snd_soc_pcm_runtime *prtd = substream->private_data; 9107c31335aSMaruthi Srinivas Bayyavarapu struct audio_substream_data *rtd = runtime->private_data; 91113838c11SMukunda, Vijendar struct snd_soc_component *component = snd_soc_rtdcom_lookup(prtd, 91213838c11SMukunda, Vijendar DRV_NAME); 9137c31335aSMaruthi Srinivas Bayyavarapu 9147c31335aSMaruthi Srinivas Bayyavarapu if (!rtd) 9157c31335aSMaruthi Srinivas Bayyavarapu return -EINVAL; 9167c31335aSMaruthi Srinivas Bayyavarapu switch (cmd) { 9177c31335aSMaruthi Srinivas Bayyavarapu case SNDRV_PCM_TRIGGER_START: 9187c31335aSMaruthi Srinivas Bayyavarapu case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 9197c31335aSMaruthi Srinivas Bayyavarapu case SNDRV_PCM_TRIGGER_RESUME: 9207f004847SVijendar Mukunda bytescount = acp_get_byte_count(rtd); 9219af8937eSVijendar Mukunda if (rtd->bytescount == 0) 9229af8937eSVijendar Mukunda rtd->bytescount = bytescount; 9237c31335aSMaruthi Srinivas Bayyavarapu if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 9248769bb55SVijendar Mukunda acp_dma_start(rtd->acp_mmio, rtd->ch1, false); 9257c31335aSMaruthi Srinivas Bayyavarapu while (acp_reg_read(rtd->acp_mmio, mmACP_DMA_CH_STS) & 9268769bb55SVijendar Mukunda BIT(rtd->ch1)) { 9277c31335aSMaruthi Srinivas Bayyavarapu if (!loops--) { 928a1042a42SKuninori Morimoto dev_err(component->dev, 9297c31335aSMaruthi Srinivas Bayyavarapu "acp dma start timeout\n"); 9307c31335aSMaruthi Srinivas Bayyavarapu return -ETIMEDOUT; 9317c31335aSMaruthi Srinivas Bayyavarapu } 9327c31335aSMaruthi Srinivas Bayyavarapu cpu_relax(); 9337c31335aSMaruthi Srinivas Bayyavarapu } 9347c31335aSMaruthi Srinivas Bayyavarapu } 9358769bb55SVijendar Mukunda acp_dma_start(rtd->acp_mmio, rtd->ch2, true); 9367c31335aSMaruthi Srinivas Bayyavarapu ret = 0; 9377c31335aSMaruthi Srinivas Bayyavarapu break; 9387c31335aSMaruthi Srinivas Bayyavarapu case SNDRV_PCM_TRIGGER_STOP: 9397c31335aSMaruthi Srinivas Bayyavarapu case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 9407c31335aSMaruthi Srinivas Bayyavarapu case SNDRV_PCM_TRIGGER_SUSPEND: 9418769bb55SVijendar Mukunda /* For playback, non circular dma should be stopped first 9428769bb55SVijendar Mukunda * i.e Sysram to acp dma transfer channel(rtd->ch1) should be 9438769bb55SVijendar Mukunda * stopped before stopping cirular dma which is acp sram to i2s 9448769bb55SVijendar Mukunda * fifo dma transfer channel(rtd->ch2). Where as in Capture 9458769bb55SVijendar Mukunda * scenario, i2s fifo to acp sram dma channel(rtd->ch2) stopped 9468769bb55SVijendar Mukunda * first before stopping acp sram to sysram which is circular 9478769bb55SVijendar Mukunda * dma(rtd->ch1). 9487c31335aSMaruthi Srinivas Bayyavarapu */ 94961add814SVijendar Mukunda if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 9508769bb55SVijendar Mukunda acp_dma_stop(rtd->acp_mmio, rtd->ch1); 9518769bb55SVijendar Mukunda ret = acp_dma_stop(rtd->acp_mmio, rtd->ch2); 95261add814SVijendar Mukunda } else { 9538769bb55SVijendar Mukunda acp_dma_stop(rtd->acp_mmio, rtd->ch2); 9548769bb55SVijendar Mukunda ret = acp_dma_stop(rtd->acp_mmio, rtd->ch1); 95561add814SVijendar Mukunda } 9569af8937eSVijendar Mukunda rtd->bytescount = 0; 9577c31335aSMaruthi Srinivas Bayyavarapu break; 9587c31335aSMaruthi Srinivas Bayyavarapu default: 9597c31335aSMaruthi Srinivas Bayyavarapu ret = -EINVAL; 9607c31335aSMaruthi Srinivas Bayyavarapu } 9617c31335aSMaruthi Srinivas Bayyavarapu return ret; 9627c31335aSMaruthi Srinivas Bayyavarapu } 9637c31335aSMaruthi Srinivas Bayyavarapu 9647c31335aSMaruthi Srinivas Bayyavarapu static int acp_dma_new(struct snd_soc_pcm_runtime *rtd) 9657c31335aSMaruthi Srinivas Bayyavarapu { 9669c7d6fabSVijendar Mukunda int ret; 96713838c11SMukunda, Vijendar struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, 96813838c11SMukunda, Vijendar DRV_NAME); 969a1042a42SKuninori Morimoto struct audio_drv_data *adata = dev_get_drvdata(component->dev); 9709c7d6fabSVijendar Mukunda 9719c7d6fabSVijendar Mukunda switch (adata->asic_type) { 9729c7d6fabSVijendar Mukunda case CHIP_STONEY: 9739c7d6fabSVijendar Mukunda ret = snd_pcm_lib_preallocate_pages_for_all(rtd->pcm, 9749c7d6fabSVijendar Mukunda SNDRV_DMA_TYPE_DEV, 9759c7d6fabSVijendar Mukunda NULL, ST_MIN_BUFFER, 9769c7d6fabSVijendar Mukunda ST_MAX_BUFFER); 9779c7d6fabSVijendar Mukunda break; 9789c7d6fabSVijendar Mukunda default: 9799c7d6fabSVijendar Mukunda ret = snd_pcm_lib_preallocate_pages_for_all(rtd->pcm, 9807c31335aSMaruthi Srinivas Bayyavarapu SNDRV_DMA_TYPE_DEV, 9817c31335aSMaruthi Srinivas Bayyavarapu NULL, MIN_BUFFER, 9827c31335aSMaruthi Srinivas Bayyavarapu MAX_BUFFER); 9839c7d6fabSVijendar Mukunda break; 9849c7d6fabSVijendar Mukunda } 9859c7d6fabSVijendar Mukunda if (ret < 0) 986a1042a42SKuninori Morimoto dev_err(component->dev, 9879e6a469eSColin Ian King "buffer preallocation failure error:%d\n", ret); 9889c7d6fabSVijendar Mukunda return ret; 9897c31335aSMaruthi Srinivas Bayyavarapu } 9907c31335aSMaruthi Srinivas Bayyavarapu 9917c31335aSMaruthi Srinivas Bayyavarapu static int acp_dma_close(struct snd_pcm_substream *substream) 9927c31335aSMaruthi Srinivas Bayyavarapu { 993c36d9b3fSMaruthi Srinivas Bayyavarapu u16 bank; 9947c31335aSMaruthi Srinivas Bayyavarapu struct snd_pcm_runtime *runtime = substream->runtime; 9957c31335aSMaruthi Srinivas Bayyavarapu struct audio_substream_data *rtd = runtime->private_data; 9967c31335aSMaruthi Srinivas Bayyavarapu struct snd_soc_pcm_runtime *prtd = substream->private_data; 99713838c11SMukunda, Vijendar struct snd_soc_component *component = snd_soc_rtdcom_lookup(prtd, 99813838c11SMukunda, Vijendar DRV_NAME); 999a1042a42SKuninori Morimoto struct audio_drv_data *adata = dev_get_drvdata(component->dev); 10007c31335aSMaruthi Srinivas Bayyavarapu 1001c36d9b3fSMaruthi Srinivas Bayyavarapu if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 1002e21358c4SMukunda, Vijendar adata->play_i2ssp_stream = NULL; 100313838c11SMukunda, Vijendar /* 100413838c11SMukunda, Vijendar * For Stoney, Memory gating is disabled,i.e SRAM Banks 1005607b39efSVijendar Mukunda * won't be turned off. The default state for SRAM banks is ON. 1006607b39efSVijendar Mukunda * Setting SRAM bank state code skipped for STONEY platform. 1007607b39efSVijendar Mukunda * added condition checks for Carrizo platform only 1008607b39efSVijendar Mukunda */ 1009607b39efSVijendar Mukunda if (adata->asic_type != CHIP_STONEY) { 1010c36d9b3fSMaruthi Srinivas Bayyavarapu for (bank = 1; bank <= 4; bank++) 1011c36d9b3fSMaruthi Srinivas Bayyavarapu acp_set_sram_bank_state(adata->acp_mmio, bank, 1012c36d9b3fSMaruthi Srinivas Bayyavarapu false); 1013607b39efSVijendar Mukunda } 1014c36d9b3fSMaruthi Srinivas Bayyavarapu } else { 1015e21358c4SMukunda, Vijendar adata->capture_i2ssp_stream = NULL; 1016607b39efSVijendar Mukunda if (adata->asic_type != CHIP_STONEY) { 1017c36d9b3fSMaruthi Srinivas Bayyavarapu for (bank = 5; bank <= 8; bank++) 1018c36d9b3fSMaruthi Srinivas Bayyavarapu acp_set_sram_bank_state(adata->acp_mmio, bank, 1019c36d9b3fSMaruthi Srinivas Bayyavarapu false); 1020c36d9b3fSMaruthi Srinivas Bayyavarapu } 1021607b39efSVijendar Mukunda } 10227c31335aSMaruthi Srinivas Bayyavarapu 102313838c11SMukunda, Vijendar /* 102413838c11SMukunda, Vijendar * Disable ACP irq, when the current stream is being closed and 10257c31335aSMaruthi Srinivas Bayyavarapu * another stream is also not active. 10267c31335aSMaruthi Srinivas Bayyavarapu */ 1027e21358c4SMukunda, Vijendar if (!adata->play_i2ssp_stream && !adata->capture_i2ssp_stream) 10287c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(0, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB); 1029*cac6f597SMukunda, Vijendar kfree(rtd); 10307c31335aSMaruthi Srinivas Bayyavarapu return 0; 10317c31335aSMaruthi Srinivas Bayyavarapu } 10327c31335aSMaruthi Srinivas Bayyavarapu 1033115c7254SJulia Lawall static const struct snd_pcm_ops acp_dma_ops = { 10347c31335aSMaruthi Srinivas Bayyavarapu .open = acp_dma_open, 10357c31335aSMaruthi Srinivas Bayyavarapu .close = acp_dma_close, 10367c31335aSMaruthi Srinivas Bayyavarapu .ioctl = snd_pcm_lib_ioctl, 10377c31335aSMaruthi Srinivas Bayyavarapu .hw_params = acp_dma_hw_params, 10387c31335aSMaruthi Srinivas Bayyavarapu .hw_free = acp_dma_hw_free, 10397c31335aSMaruthi Srinivas Bayyavarapu .trigger = acp_dma_trigger, 10407c31335aSMaruthi Srinivas Bayyavarapu .pointer = acp_dma_pointer, 10417c31335aSMaruthi Srinivas Bayyavarapu .mmap = acp_dma_mmap, 10427c31335aSMaruthi Srinivas Bayyavarapu .prepare = acp_dma_prepare, 10437c31335aSMaruthi Srinivas Bayyavarapu }; 10447c31335aSMaruthi Srinivas Bayyavarapu 104513838c11SMukunda, Vijendar static const struct snd_soc_component_driver acp_asoc_platform = { 1046a1042a42SKuninori Morimoto .name = DRV_NAME, 10477c31335aSMaruthi Srinivas Bayyavarapu .ops = &acp_dma_ops, 10487c31335aSMaruthi Srinivas Bayyavarapu .pcm_new = acp_dma_new, 10497c31335aSMaruthi Srinivas Bayyavarapu }; 10507c31335aSMaruthi Srinivas Bayyavarapu 10517c31335aSMaruthi Srinivas Bayyavarapu static int acp_audio_probe(struct platform_device *pdev) 10527c31335aSMaruthi Srinivas Bayyavarapu { 10537c31335aSMaruthi Srinivas Bayyavarapu int status; 10547c31335aSMaruthi Srinivas Bayyavarapu struct audio_drv_data *audio_drv_data; 10557c31335aSMaruthi Srinivas Bayyavarapu struct resource *res; 1056a1b16aaaSVijendar Mukunda const u32 *pdata = pdev->dev.platform_data; 10577c31335aSMaruthi Srinivas Bayyavarapu 1058fdaa4511SGuenter Roeck if (!pdata) { 1059fdaa4511SGuenter Roeck dev_err(&pdev->dev, "Missing platform data\n"); 1060fdaa4511SGuenter Roeck return -ENODEV; 1061fdaa4511SGuenter Roeck } 1062fdaa4511SGuenter Roeck 10637c31335aSMaruthi Srinivas Bayyavarapu audio_drv_data = devm_kzalloc(&pdev->dev, sizeof(struct audio_drv_data), 10647c31335aSMaruthi Srinivas Bayyavarapu GFP_KERNEL); 106513838c11SMukunda, Vijendar if (!audio_drv_data) 10667c31335aSMaruthi Srinivas Bayyavarapu return -ENOMEM; 10677c31335aSMaruthi Srinivas Bayyavarapu 10687c31335aSMaruthi Srinivas Bayyavarapu res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 10697c31335aSMaruthi Srinivas Bayyavarapu audio_drv_data->acp_mmio = devm_ioremap_resource(&pdev->dev, res); 1070fdaa4511SGuenter Roeck if (IS_ERR(audio_drv_data->acp_mmio)) 1071fdaa4511SGuenter Roeck return PTR_ERR(audio_drv_data->acp_mmio); 10727c31335aSMaruthi Srinivas Bayyavarapu 107313838c11SMukunda, Vijendar /* 107413838c11SMukunda, Vijendar * The following members gets populated in device 'open' 10757c31335aSMaruthi Srinivas Bayyavarapu * function. Till then interrupts are disabled in 'acp_init' 10767c31335aSMaruthi Srinivas Bayyavarapu * and device doesn't generate any interrupts. 10777c31335aSMaruthi Srinivas Bayyavarapu */ 10787c31335aSMaruthi Srinivas Bayyavarapu 1079e21358c4SMukunda, Vijendar audio_drv_data->play_i2ssp_stream = NULL; 1080e21358c4SMukunda, Vijendar audio_drv_data->capture_i2ssp_stream = NULL; 1081e21358c4SMukunda, Vijendar 1082a1b16aaaSVijendar Mukunda audio_drv_data->asic_type = *pdata; 10837c31335aSMaruthi Srinivas Bayyavarapu 10847c31335aSMaruthi Srinivas Bayyavarapu res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 10857c31335aSMaruthi Srinivas Bayyavarapu if (!res) { 10867c31335aSMaruthi Srinivas Bayyavarapu dev_err(&pdev->dev, "IORESOURCE_IRQ FAILED\n"); 10877c31335aSMaruthi Srinivas Bayyavarapu return -ENODEV; 10887c31335aSMaruthi Srinivas Bayyavarapu } 10897c31335aSMaruthi Srinivas Bayyavarapu 10907c31335aSMaruthi Srinivas Bayyavarapu status = devm_request_irq(&pdev->dev, res->start, dma_irq_handler, 10917c31335aSMaruthi Srinivas Bayyavarapu 0, "ACP_IRQ", &pdev->dev); 10927c31335aSMaruthi Srinivas Bayyavarapu if (status) { 10937c31335aSMaruthi Srinivas Bayyavarapu dev_err(&pdev->dev, "ACP IRQ request failed\n"); 10947c31335aSMaruthi Srinivas Bayyavarapu return status; 10957c31335aSMaruthi Srinivas Bayyavarapu } 10967c31335aSMaruthi Srinivas Bayyavarapu 10977c31335aSMaruthi Srinivas Bayyavarapu dev_set_drvdata(&pdev->dev, audio_drv_data); 10987c31335aSMaruthi Srinivas Bayyavarapu 10997c31335aSMaruthi Srinivas Bayyavarapu /* Initialize the ACP */ 11007afa535eSMukunda, Vijendar status = acp_init(audio_drv_data->acp_mmio, audio_drv_data->asic_type); 11017afa535eSMukunda, Vijendar if (status) { 11027afa535eSMukunda, Vijendar dev_err(&pdev->dev, "ACP Init failed status:%d\n", status); 11037afa535eSMukunda, Vijendar return status; 11047afa535eSMukunda, Vijendar } 11057c31335aSMaruthi Srinivas Bayyavarapu 1106a1042a42SKuninori Morimoto status = devm_snd_soc_register_component(&pdev->dev, 1107a1042a42SKuninori Morimoto &acp_asoc_platform, NULL, 0); 11087c31335aSMaruthi Srinivas Bayyavarapu if (status != 0) { 11097c31335aSMaruthi Srinivas Bayyavarapu dev_err(&pdev->dev, "Fail to register ALSA platform device\n"); 11107c31335aSMaruthi Srinivas Bayyavarapu return status; 11117c31335aSMaruthi Srinivas Bayyavarapu } 11127c31335aSMaruthi Srinivas Bayyavarapu 11131927da93SMaruthi Srinivas Bayyavarapu pm_runtime_set_autosuspend_delay(&pdev->dev, 10000); 11141927da93SMaruthi Srinivas Bayyavarapu pm_runtime_use_autosuspend(&pdev->dev); 11151927da93SMaruthi Srinivas Bayyavarapu pm_runtime_enable(&pdev->dev); 11161927da93SMaruthi Srinivas Bayyavarapu 11177c31335aSMaruthi Srinivas Bayyavarapu return status; 11187c31335aSMaruthi Srinivas Bayyavarapu } 11197c31335aSMaruthi Srinivas Bayyavarapu 11207c31335aSMaruthi Srinivas Bayyavarapu static int acp_audio_remove(struct platform_device *pdev) 11217c31335aSMaruthi Srinivas Bayyavarapu { 11227afa535eSMukunda, Vijendar int status; 11237c31335aSMaruthi Srinivas Bayyavarapu struct audio_drv_data *adata = dev_get_drvdata(&pdev->dev); 11247c31335aSMaruthi Srinivas Bayyavarapu 11257afa535eSMukunda, Vijendar status = acp_deinit(adata->acp_mmio); 11267afa535eSMukunda, Vijendar if (status) 11277afa535eSMukunda, Vijendar dev_err(&pdev->dev, "ACP Deinit failed status:%d\n", status); 11281927da93SMaruthi Srinivas Bayyavarapu pm_runtime_disable(&pdev->dev); 11297c31335aSMaruthi Srinivas Bayyavarapu 11307c31335aSMaruthi Srinivas Bayyavarapu return 0; 11317c31335aSMaruthi Srinivas Bayyavarapu } 11327c31335aSMaruthi Srinivas Bayyavarapu 11331927da93SMaruthi Srinivas Bayyavarapu static int acp_pcm_resume(struct device *dev) 11341927da93SMaruthi Srinivas Bayyavarapu { 1135c36d9b3fSMaruthi Srinivas Bayyavarapu u16 bank; 11367afa535eSMukunda, Vijendar int status; 11371927da93SMaruthi Srinivas Bayyavarapu struct audio_drv_data *adata = dev_get_drvdata(dev); 11381927da93SMaruthi Srinivas Bayyavarapu 11397afa535eSMukunda, Vijendar status = acp_init(adata->acp_mmio, adata->asic_type); 11407afa535eSMukunda, Vijendar if (status) { 11417afa535eSMukunda, Vijendar dev_err(dev, "ACP Init failed status:%d\n", status); 11427afa535eSMukunda, Vijendar return status; 11437afa535eSMukunda, Vijendar } 11441927da93SMaruthi Srinivas Bayyavarapu 1145e21358c4SMukunda, Vijendar if (adata->play_i2ssp_stream && adata->play_i2ssp_stream->runtime) { 114613838c11SMukunda, Vijendar /* 114713838c11SMukunda, Vijendar * For Stoney, Memory gating is disabled,i.e SRAM Banks 1148607b39efSVijendar Mukunda * won't be turned off. The default state for SRAM banks is ON. 1149607b39efSVijendar Mukunda * Setting SRAM bank state code skipped for STONEY platform. 1150607b39efSVijendar Mukunda */ 1151607b39efSVijendar Mukunda if (adata->asic_type != CHIP_STONEY) { 1152c36d9b3fSMaruthi Srinivas Bayyavarapu for (bank = 1; bank <= 4; bank++) 1153c36d9b3fSMaruthi Srinivas Bayyavarapu acp_set_sram_bank_state(adata->acp_mmio, bank, 1154c36d9b3fSMaruthi Srinivas Bayyavarapu true); 1155607b39efSVijendar Mukunda } 11561927da93SMaruthi Srinivas Bayyavarapu config_acp_dma(adata->acp_mmio, 1157e21358c4SMukunda, Vijendar adata->play_i2ssp_stream->runtime->private_data, 1158aac89748SVijendar Mukunda adata->asic_type); 1159c36d9b3fSMaruthi Srinivas Bayyavarapu } 116013838c11SMukunda, Vijendar if (adata->capture_i2ssp_stream && 116113838c11SMukunda, Vijendar adata->capture_i2ssp_stream->runtime) { 1162607b39efSVijendar Mukunda if (adata->asic_type != CHIP_STONEY) { 1163c36d9b3fSMaruthi Srinivas Bayyavarapu for (bank = 5; bank <= 8; bank++) 1164c36d9b3fSMaruthi Srinivas Bayyavarapu acp_set_sram_bank_state(adata->acp_mmio, bank, 1165c36d9b3fSMaruthi Srinivas Bayyavarapu true); 1166607b39efSVijendar Mukunda } 11671927da93SMaruthi Srinivas Bayyavarapu config_acp_dma(adata->acp_mmio, 1168e21358c4SMukunda, Vijendar adata->capture_i2ssp_stream->runtime->private_data, 1169aac89748SVijendar Mukunda adata->asic_type); 1170c36d9b3fSMaruthi Srinivas Bayyavarapu } 11711927da93SMaruthi Srinivas Bayyavarapu acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB); 11721927da93SMaruthi Srinivas Bayyavarapu return 0; 11731927da93SMaruthi Srinivas Bayyavarapu } 11741927da93SMaruthi Srinivas Bayyavarapu 11751927da93SMaruthi Srinivas Bayyavarapu static int acp_pcm_runtime_suspend(struct device *dev) 11761927da93SMaruthi Srinivas Bayyavarapu { 11777afa535eSMukunda, Vijendar int status; 11781927da93SMaruthi Srinivas Bayyavarapu struct audio_drv_data *adata = dev_get_drvdata(dev); 11791927da93SMaruthi Srinivas Bayyavarapu 11807afa535eSMukunda, Vijendar status = acp_deinit(adata->acp_mmio); 11817afa535eSMukunda, Vijendar if (status) 11827afa535eSMukunda, Vijendar dev_err(dev, "ACP Deinit failed status:%d\n", status); 11831927da93SMaruthi Srinivas Bayyavarapu acp_reg_write(0, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB); 11841927da93SMaruthi Srinivas Bayyavarapu return 0; 11851927da93SMaruthi Srinivas Bayyavarapu } 11861927da93SMaruthi Srinivas Bayyavarapu 11871927da93SMaruthi Srinivas Bayyavarapu static int acp_pcm_runtime_resume(struct device *dev) 11881927da93SMaruthi Srinivas Bayyavarapu { 11897afa535eSMukunda, Vijendar int status; 11901927da93SMaruthi Srinivas Bayyavarapu struct audio_drv_data *adata = dev_get_drvdata(dev); 11911927da93SMaruthi Srinivas Bayyavarapu 11927afa535eSMukunda, Vijendar status = acp_init(adata->acp_mmio, adata->asic_type); 11937afa535eSMukunda, Vijendar if (status) { 11947afa535eSMukunda, Vijendar dev_err(dev, "ACP Init failed status:%d\n", status); 11957afa535eSMukunda, Vijendar return status; 11967afa535eSMukunda, Vijendar } 11971927da93SMaruthi Srinivas Bayyavarapu acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB); 11981927da93SMaruthi Srinivas Bayyavarapu return 0; 11991927da93SMaruthi Srinivas Bayyavarapu } 12001927da93SMaruthi Srinivas Bayyavarapu 12011927da93SMaruthi Srinivas Bayyavarapu static const struct dev_pm_ops acp_pm_ops = { 12021927da93SMaruthi Srinivas Bayyavarapu .resume = acp_pcm_resume, 12031927da93SMaruthi Srinivas Bayyavarapu .runtime_suspend = acp_pcm_runtime_suspend, 12041927da93SMaruthi Srinivas Bayyavarapu .runtime_resume = acp_pcm_runtime_resume, 12051927da93SMaruthi Srinivas Bayyavarapu }; 12061927da93SMaruthi Srinivas Bayyavarapu 12077c31335aSMaruthi Srinivas Bayyavarapu static struct platform_driver acp_dma_driver = { 12087c31335aSMaruthi Srinivas Bayyavarapu .probe = acp_audio_probe, 12097c31335aSMaruthi Srinivas Bayyavarapu .remove = acp_audio_remove, 12107c31335aSMaruthi Srinivas Bayyavarapu .driver = { 1211bdd2a858SAkshu Agrawal .name = DRV_NAME, 12121927da93SMaruthi Srinivas Bayyavarapu .pm = &acp_pm_ops, 12137c31335aSMaruthi Srinivas Bayyavarapu }, 12147c31335aSMaruthi Srinivas Bayyavarapu }; 12157c31335aSMaruthi Srinivas Bayyavarapu 12167c31335aSMaruthi Srinivas Bayyavarapu module_platform_driver(acp_dma_driver); 12177c31335aSMaruthi Srinivas Bayyavarapu 1218607b39efSVijendar Mukunda MODULE_AUTHOR("Vijendar.Mukunda@amd.com"); 12197c31335aSMaruthi Srinivas Bayyavarapu MODULE_AUTHOR("Maruthi.Bayyavarapu@amd.com"); 12207c31335aSMaruthi Srinivas Bayyavarapu MODULE_DESCRIPTION("AMD ACP PCM Driver"); 12217c31335aSMaruthi Srinivas Bayyavarapu MODULE_LICENSE("GPL v2"); 1222bdd2a858SAkshu Agrawal MODULE_ALIAS("platform:"DRV_NAME); 1223