17c31335aSMaruthi Srinivas Bayyavarapu /* 27c31335aSMaruthi Srinivas Bayyavarapu * AMD ALSA SoC PCM Driver for ACP 2.x 37c31335aSMaruthi Srinivas Bayyavarapu * 47c31335aSMaruthi Srinivas Bayyavarapu * Copyright 2014-2015 Advanced Micro Devices, Inc. 57c31335aSMaruthi Srinivas Bayyavarapu * 67c31335aSMaruthi Srinivas Bayyavarapu * This program is free software; you can redistribute it and/or modify it 77c31335aSMaruthi Srinivas Bayyavarapu * under the terms and conditions of the GNU General Public License, 87c31335aSMaruthi Srinivas Bayyavarapu * version 2, as published by the Free Software Foundation. 97c31335aSMaruthi Srinivas Bayyavarapu * 107c31335aSMaruthi Srinivas Bayyavarapu * This program is distributed in the hope it will be useful, but WITHOUT 117c31335aSMaruthi Srinivas Bayyavarapu * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 127c31335aSMaruthi Srinivas Bayyavarapu * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 137c31335aSMaruthi Srinivas Bayyavarapu * more details. 147c31335aSMaruthi Srinivas Bayyavarapu */ 157c31335aSMaruthi Srinivas Bayyavarapu 167c31335aSMaruthi Srinivas Bayyavarapu #include <linux/module.h> 177c31335aSMaruthi Srinivas Bayyavarapu #include <linux/delay.h> 187cb1dc81SGuenter Roeck #include <linux/io.h> 197c31335aSMaruthi Srinivas Bayyavarapu #include <linux/sizes.h> 201927da93SMaruthi Srinivas Bayyavarapu #include <linux/pm_runtime.h> 217c31335aSMaruthi Srinivas Bayyavarapu 227c31335aSMaruthi Srinivas Bayyavarapu #include <sound/soc.h> 23607b39efSVijendar Mukunda #include <drm/amd_asic_type.h> 247c31335aSMaruthi Srinivas Bayyavarapu #include "acp.h" 257c31335aSMaruthi Srinivas Bayyavarapu 26a1042a42SKuninori Morimoto #define DRV_NAME "acp_audio_dma" 27a1042a42SKuninori Morimoto 287c31335aSMaruthi Srinivas Bayyavarapu #define PLAYBACK_MIN_NUM_PERIODS 2 297c31335aSMaruthi Srinivas Bayyavarapu #define PLAYBACK_MAX_NUM_PERIODS 2 307c31335aSMaruthi Srinivas Bayyavarapu #define PLAYBACK_MAX_PERIOD_SIZE 16384 317c31335aSMaruthi Srinivas Bayyavarapu #define PLAYBACK_MIN_PERIOD_SIZE 1024 327c31335aSMaruthi Srinivas Bayyavarapu #define CAPTURE_MIN_NUM_PERIODS 2 337c31335aSMaruthi Srinivas Bayyavarapu #define CAPTURE_MAX_NUM_PERIODS 2 347c31335aSMaruthi Srinivas Bayyavarapu #define CAPTURE_MAX_PERIOD_SIZE 16384 357c31335aSMaruthi Srinivas Bayyavarapu #define CAPTURE_MIN_PERIOD_SIZE 1024 367c31335aSMaruthi Srinivas Bayyavarapu 377c31335aSMaruthi Srinivas Bayyavarapu #define MAX_BUFFER (PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS) 387c31335aSMaruthi Srinivas Bayyavarapu #define MIN_BUFFER MAX_BUFFER 397c31335aSMaruthi Srinivas Bayyavarapu 40ccfbb4f5SMukunda, Vijendar #define ST_PLAYBACK_MAX_PERIOD_SIZE 4096 419c7d6fabSVijendar Mukunda #define ST_CAPTURE_MAX_PERIOD_SIZE ST_PLAYBACK_MAX_PERIOD_SIZE 429c7d6fabSVijendar Mukunda #define ST_MAX_BUFFER (ST_PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS) 439c7d6fabSVijendar Mukunda #define ST_MIN_BUFFER ST_MAX_BUFFER 449c7d6fabSVijendar Mukunda 45bdd2a858SAkshu Agrawal #define DRV_NAME "acp_audio_dma" 46ccfbb4f5SMukunda, Vijendar bool bt_uart_enable = true; 47ccfbb4f5SMukunda, Vijendar EXPORT_SYMBOL(bt_uart_enable); 48bdd2a858SAkshu Agrawal 497c31335aSMaruthi Srinivas Bayyavarapu static const struct snd_pcm_hardware acp_pcm_hardware_playback = { 507c31335aSMaruthi Srinivas Bayyavarapu .info = SNDRV_PCM_INFO_INTERLEAVED | 517c31335aSMaruthi Srinivas Bayyavarapu SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP | 527c31335aSMaruthi Srinivas Bayyavarapu SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH | 537c31335aSMaruthi Srinivas Bayyavarapu SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME, 547c31335aSMaruthi Srinivas Bayyavarapu .formats = SNDRV_PCM_FMTBIT_S16_LE | 557c31335aSMaruthi Srinivas Bayyavarapu SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, 567c31335aSMaruthi Srinivas Bayyavarapu .channels_min = 1, 577c31335aSMaruthi Srinivas Bayyavarapu .channels_max = 8, 587c31335aSMaruthi Srinivas Bayyavarapu .rates = SNDRV_PCM_RATE_8000_96000, 597c31335aSMaruthi Srinivas Bayyavarapu .rate_min = 8000, 607c31335aSMaruthi Srinivas Bayyavarapu .rate_max = 96000, 617c31335aSMaruthi Srinivas Bayyavarapu .buffer_bytes_max = PLAYBACK_MAX_NUM_PERIODS * PLAYBACK_MAX_PERIOD_SIZE, 627c31335aSMaruthi Srinivas Bayyavarapu .period_bytes_min = PLAYBACK_MIN_PERIOD_SIZE, 637c31335aSMaruthi Srinivas Bayyavarapu .period_bytes_max = PLAYBACK_MAX_PERIOD_SIZE, 647c31335aSMaruthi Srinivas Bayyavarapu .periods_min = PLAYBACK_MIN_NUM_PERIODS, 657c31335aSMaruthi Srinivas Bayyavarapu .periods_max = PLAYBACK_MAX_NUM_PERIODS, 667c31335aSMaruthi Srinivas Bayyavarapu }; 677c31335aSMaruthi Srinivas Bayyavarapu 687c31335aSMaruthi Srinivas Bayyavarapu static const struct snd_pcm_hardware acp_pcm_hardware_capture = { 697c31335aSMaruthi Srinivas Bayyavarapu .info = SNDRV_PCM_INFO_INTERLEAVED | 707c31335aSMaruthi Srinivas Bayyavarapu SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP | 717c31335aSMaruthi Srinivas Bayyavarapu SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH | 727c31335aSMaruthi Srinivas Bayyavarapu SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME, 737c31335aSMaruthi Srinivas Bayyavarapu .formats = SNDRV_PCM_FMTBIT_S16_LE | 747c31335aSMaruthi Srinivas Bayyavarapu SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, 757c31335aSMaruthi Srinivas Bayyavarapu .channels_min = 1, 767c31335aSMaruthi Srinivas Bayyavarapu .channels_max = 2, 777c31335aSMaruthi Srinivas Bayyavarapu .rates = SNDRV_PCM_RATE_8000_48000, 787c31335aSMaruthi Srinivas Bayyavarapu .rate_min = 8000, 797c31335aSMaruthi Srinivas Bayyavarapu .rate_max = 48000, 807c31335aSMaruthi Srinivas Bayyavarapu .buffer_bytes_max = CAPTURE_MAX_NUM_PERIODS * CAPTURE_MAX_PERIOD_SIZE, 817c31335aSMaruthi Srinivas Bayyavarapu .period_bytes_min = CAPTURE_MIN_PERIOD_SIZE, 827c31335aSMaruthi Srinivas Bayyavarapu .period_bytes_max = CAPTURE_MAX_PERIOD_SIZE, 837c31335aSMaruthi Srinivas Bayyavarapu .periods_min = CAPTURE_MIN_NUM_PERIODS, 847c31335aSMaruthi Srinivas Bayyavarapu .periods_max = CAPTURE_MAX_NUM_PERIODS, 857c31335aSMaruthi Srinivas Bayyavarapu }; 867c31335aSMaruthi Srinivas Bayyavarapu 879c7d6fabSVijendar Mukunda static const struct snd_pcm_hardware acp_st_pcm_hardware_playback = { 889c7d6fabSVijendar Mukunda .info = SNDRV_PCM_INFO_INTERLEAVED | 899c7d6fabSVijendar Mukunda SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP | 909c7d6fabSVijendar Mukunda SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH | 919c7d6fabSVijendar Mukunda SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME, 929c7d6fabSVijendar Mukunda .formats = SNDRV_PCM_FMTBIT_S16_LE | 939c7d6fabSVijendar Mukunda SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, 949c7d6fabSVijendar Mukunda .channels_min = 1, 959c7d6fabSVijendar Mukunda .channels_max = 8, 969c7d6fabSVijendar Mukunda .rates = SNDRV_PCM_RATE_8000_96000, 979c7d6fabSVijendar Mukunda .rate_min = 8000, 989c7d6fabSVijendar Mukunda .rate_max = 96000, 999c7d6fabSVijendar Mukunda .buffer_bytes_max = ST_MAX_BUFFER, 1009c7d6fabSVijendar Mukunda .period_bytes_min = PLAYBACK_MIN_PERIOD_SIZE, 1019c7d6fabSVijendar Mukunda .period_bytes_max = ST_PLAYBACK_MAX_PERIOD_SIZE, 1029c7d6fabSVijendar Mukunda .periods_min = PLAYBACK_MIN_NUM_PERIODS, 1039c7d6fabSVijendar Mukunda .periods_max = PLAYBACK_MAX_NUM_PERIODS, 1049c7d6fabSVijendar Mukunda }; 1059c7d6fabSVijendar Mukunda 1069c7d6fabSVijendar Mukunda static const struct snd_pcm_hardware acp_st_pcm_hardware_capture = { 1079c7d6fabSVijendar Mukunda .info = SNDRV_PCM_INFO_INTERLEAVED | 1089c7d6fabSVijendar Mukunda SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP | 1099c7d6fabSVijendar Mukunda SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH | 1109c7d6fabSVijendar Mukunda SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME, 1119c7d6fabSVijendar Mukunda .formats = SNDRV_PCM_FMTBIT_S16_LE | 1129c7d6fabSVijendar Mukunda SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, 1139c7d6fabSVijendar Mukunda .channels_min = 1, 1149c7d6fabSVijendar Mukunda .channels_max = 2, 1159c7d6fabSVijendar Mukunda .rates = SNDRV_PCM_RATE_8000_48000, 1169c7d6fabSVijendar Mukunda .rate_min = 8000, 1179c7d6fabSVijendar Mukunda .rate_max = 48000, 1189c7d6fabSVijendar Mukunda .buffer_bytes_max = ST_MAX_BUFFER, 1199c7d6fabSVijendar Mukunda .period_bytes_min = CAPTURE_MIN_PERIOD_SIZE, 1209c7d6fabSVijendar Mukunda .period_bytes_max = ST_CAPTURE_MAX_PERIOD_SIZE, 1219c7d6fabSVijendar Mukunda .periods_min = CAPTURE_MIN_NUM_PERIODS, 1229c7d6fabSVijendar Mukunda .periods_max = CAPTURE_MAX_NUM_PERIODS, 1239c7d6fabSVijendar Mukunda }; 1249c7d6fabSVijendar Mukunda 1257c31335aSMaruthi Srinivas Bayyavarapu static u32 acp_reg_read(void __iomem *acp_mmio, u32 reg) 1267c31335aSMaruthi Srinivas Bayyavarapu { 1277c31335aSMaruthi Srinivas Bayyavarapu return readl(acp_mmio + (reg * 4)); 1287c31335aSMaruthi Srinivas Bayyavarapu } 1297c31335aSMaruthi Srinivas Bayyavarapu 1307c31335aSMaruthi Srinivas Bayyavarapu static void acp_reg_write(u32 val, void __iomem *acp_mmio, u32 reg) 1317c31335aSMaruthi Srinivas Bayyavarapu { 1327c31335aSMaruthi Srinivas Bayyavarapu writel(val, acp_mmio + (reg * 4)); 1337c31335aSMaruthi Srinivas Bayyavarapu } 1347c31335aSMaruthi Srinivas Bayyavarapu 13513838c11SMukunda, Vijendar /* 13613838c11SMukunda, Vijendar * Configure a given dma channel parameters - enable/disable, 1377c31335aSMaruthi Srinivas Bayyavarapu * number of descriptors, priority 1387c31335aSMaruthi Srinivas Bayyavarapu */ 1397c31335aSMaruthi Srinivas Bayyavarapu static void config_acp_dma_channel(void __iomem *acp_mmio, u8 ch_num, 1407c31335aSMaruthi Srinivas Bayyavarapu u16 dscr_strt_idx, u16 num_dscrs, 1417c31335aSMaruthi Srinivas Bayyavarapu enum acp_dma_priority_level priority_level) 1427c31335aSMaruthi Srinivas Bayyavarapu { 1437c31335aSMaruthi Srinivas Bayyavarapu u32 dma_ctrl; 1447c31335aSMaruthi Srinivas Bayyavarapu 1457c31335aSMaruthi Srinivas Bayyavarapu /* disable the channel run field */ 1467c31335aSMaruthi Srinivas Bayyavarapu dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 1477c31335aSMaruthi Srinivas Bayyavarapu dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRun_MASK; 1487c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 1497c31335aSMaruthi Srinivas Bayyavarapu 1507c31335aSMaruthi Srinivas Bayyavarapu /* program a DMA channel with first descriptor to be processed. */ 1517c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write((ACP_DMA_DSCR_STRT_IDX_0__DMAChDscrStrtIdx_MASK 1527c31335aSMaruthi Srinivas Bayyavarapu & dscr_strt_idx), 1537c31335aSMaruthi Srinivas Bayyavarapu acp_mmio, mmACP_DMA_DSCR_STRT_IDX_0 + ch_num); 1547c31335aSMaruthi Srinivas Bayyavarapu 15513838c11SMukunda, Vijendar /* 15613838c11SMukunda, Vijendar * program a DMA channel with the number of descriptors to be 1577c31335aSMaruthi Srinivas Bayyavarapu * processed in the transfer 1587c31335aSMaruthi Srinivas Bayyavarapu */ 1597c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(ACP_DMA_DSCR_CNT_0__DMAChDscrCnt_MASK & num_dscrs, 1607c31335aSMaruthi Srinivas Bayyavarapu acp_mmio, mmACP_DMA_DSCR_CNT_0 + ch_num); 1617c31335aSMaruthi Srinivas Bayyavarapu 1627c31335aSMaruthi Srinivas Bayyavarapu /* set DMA channel priority */ 1637c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(priority_level, acp_mmio, mmACP_DMA_PRIO_0 + ch_num); 1647c31335aSMaruthi Srinivas Bayyavarapu } 1657c31335aSMaruthi Srinivas Bayyavarapu 1667c31335aSMaruthi Srinivas Bayyavarapu /* Initialize a dma descriptor in SRAM based on descritor information passed */ 1677c31335aSMaruthi Srinivas Bayyavarapu static void config_dma_descriptor_in_sram(void __iomem *acp_mmio, 1687c31335aSMaruthi Srinivas Bayyavarapu u16 descr_idx, 1697c31335aSMaruthi Srinivas Bayyavarapu acp_dma_dscr_transfer_t *descr_info) 1707c31335aSMaruthi Srinivas Bayyavarapu { 1717c31335aSMaruthi Srinivas Bayyavarapu u32 sram_offset; 1727c31335aSMaruthi Srinivas Bayyavarapu 1737c31335aSMaruthi Srinivas Bayyavarapu sram_offset = (descr_idx * sizeof(acp_dma_dscr_transfer_t)); 1747c31335aSMaruthi Srinivas Bayyavarapu 1757c31335aSMaruthi Srinivas Bayyavarapu /* program the source base address. */ 1767c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(sram_offset, acp_mmio, mmACP_SRBM_Targ_Idx_Addr); 1777c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(descr_info->src, acp_mmio, mmACP_SRBM_Targ_Idx_Data); 1787c31335aSMaruthi Srinivas Bayyavarapu /* program the destination base address. */ 1797c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(sram_offset + 4, acp_mmio, mmACP_SRBM_Targ_Idx_Addr); 1807c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(descr_info->dest, acp_mmio, mmACP_SRBM_Targ_Idx_Data); 1817c31335aSMaruthi Srinivas Bayyavarapu 1827c31335aSMaruthi Srinivas Bayyavarapu /* program the number of bytes to be transferred for this descriptor. */ 1837c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(sram_offset + 8, acp_mmio, mmACP_SRBM_Targ_Idx_Addr); 1847c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(descr_info->xfer_val, acp_mmio, mmACP_SRBM_Targ_Idx_Data); 1857c31335aSMaruthi Srinivas Bayyavarapu } 1867c31335aSMaruthi Srinivas Bayyavarapu 18713838c11SMukunda, Vijendar /* 18813838c11SMukunda, Vijendar * Initialize the DMA descriptor information for transfer between 1897c31335aSMaruthi Srinivas Bayyavarapu * system memory <-> ACP SRAM 1907c31335aSMaruthi Srinivas Bayyavarapu */ 1917c31335aSMaruthi Srinivas Bayyavarapu static void set_acp_sysmem_dma_descriptors(void __iomem *acp_mmio, 19213838c11SMukunda, Vijendar u32 size, int direction, 19313838c11SMukunda, Vijendar u32 pte_offset, u16 ch, 19413838c11SMukunda, Vijendar u32 sram_bank, u16 dma_dscr_idx, 19513838c11SMukunda, Vijendar u32 asic_type) 1967c31335aSMaruthi Srinivas Bayyavarapu { 1977c31335aSMaruthi Srinivas Bayyavarapu u16 i; 1987c31335aSMaruthi Srinivas Bayyavarapu acp_dma_dscr_transfer_t dmadscr[NUM_DSCRS_PER_CHANNEL]; 1997c31335aSMaruthi Srinivas Bayyavarapu 2007c31335aSMaruthi Srinivas Bayyavarapu for (i = 0; i < NUM_DSCRS_PER_CHANNEL; i++) { 2017c31335aSMaruthi Srinivas Bayyavarapu dmadscr[i].xfer_val = 0; 2027c31335aSMaruthi Srinivas Bayyavarapu if (direction == SNDRV_PCM_STREAM_PLAYBACK) { 2034376a86cSMukunda, Vijendar dma_dscr_idx = dma_dscr_idx + i; 2044376a86cSMukunda, Vijendar dmadscr[i].dest = sram_bank + (i * (size / 2)); 2057c31335aSMaruthi Srinivas Bayyavarapu dmadscr[i].src = ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS 2067c31335aSMaruthi Srinivas Bayyavarapu + (pte_offset * SZ_4K) + (i * (size / 2)); 207aac89748SVijendar Mukunda switch (asic_type) { 208aac89748SVijendar Mukunda case CHIP_STONEY: 209aac89748SVijendar Mukunda dmadscr[i].xfer_val |= 21013838c11SMukunda, Vijendar (ACP_DMA_ATTR_DAGB_GARLIC_TO_SHAREDMEM << 16) | 211aac89748SVijendar Mukunda (size / 2); 212aac89748SVijendar Mukunda break; 213aac89748SVijendar Mukunda default: 2147c31335aSMaruthi Srinivas Bayyavarapu dmadscr[i].xfer_val |= 21513838c11SMukunda, Vijendar (ACP_DMA_ATTR_DAGB_ONION_TO_SHAREDMEM << 16) | 2167c31335aSMaruthi Srinivas Bayyavarapu (size / 2); 217aac89748SVijendar Mukunda } 2187c31335aSMaruthi Srinivas Bayyavarapu } else { 2194376a86cSMukunda, Vijendar dma_dscr_idx = dma_dscr_idx + i; 2204376a86cSMukunda, Vijendar dmadscr[i].src = sram_bank + (i * (size / 2)); 221aac89748SVijendar Mukunda dmadscr[i].dest = 222aac89748SVijendar Mukunda ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS + 223aac89748SVijendar Mukunda (pte_offset * SZ_4K) + (i * (size / 2)); 2244376a86cSMukunda, Vijendar switch (asic_type) { 2254376a86cSMukunda, Vijendar case CHIP_STONEY: 226aac89748SVijendar Mukunda dmadscr[i].xfer_val |= 227aac89748SVijendar Mukunda BIT(22) | 22813838c11SMukunda, Vijendar (ACP_DMA_ATTR_SHARED_MEM_TO_DAGB_GARLIC << 16) | 229aac89748SVijendar Mukunda (size / 2); 230aac89748SVijendar Mukunda break; 231aac89748SVijendar Mukunda default: 2327c31335aSMaruthi Srinivas Bayyavarapu dmadscr[i].xfer_val |= 2337c31335aSMaruthi Srinivas Bayyavarapu BIT(22) | 23413838c11SMukunda, Vijendar (ACP_DMA_ATTR_SHAREDMEM_TO_DAGB_ONION << 16) | 2357c31335aSMaruthi Srinivas Bayyavarapu (size / 2); 2367c31335aSMaruthi Srinivas Bayyavarapu } 237aac89748SVijendar Mukunda } 2387c31335aSMaruthi Srinivas Bayyavarapu config_dma_descriptor_in_sram(acp_mmio, dma_dscr_idx, 2397c31335aSMaruthi Srinivas Bayyavarapu &dmadscr[i]); 2407c31335aSMaruthi Srinivas Bayyavarapu } 2414376a86cSMukunda, Vijendar config_acp_dma_channel(acp_mmio, ch, 2424376a86cSMukunda, Vijendar dma_dscr_idx - 1, 2437c31335aSMaruthi Srinivas Bayyavarapu NUM_DSCRS_PER_CHANNEL, 2447c31335aSMaruthi Srinivas Bayyavarapu ACP_DMA_PRIORITY_LEVEL_NORMAL); 2457c31335aSMaruthi Srinivas Bayyavarapu } 2467c31335aSMaruthi Srinivas Bayyavarapu 24713838c11SMukunda, Vijendar /* 24813838c11SMukunda, Vijendar * Initialize the DMA descriptor information for transfer between 2497c31335aSMaruthi Srinivas Bayyavarapu * ACP SRAM <-> I2S 2507c31335aSMaruthi Srinivas Bayyavarapu */ 2514376a86cSMukunda, Vijendar static void set_acp_to_i2s_dma_descriptors(void __iomem *acp_mmio, u32 size, 2524376a86cSMukunda, Vijendar int direction, u32 sram_bank, 2534376a86cSMukunda, Vijendar u16 destination, u16 ch, 2544376a86cSMukunda, Vijendar u16 dma_dscr_idx, u32 asic_type) 2557c31335aSMaruthi Srinivas Bayyavarapu { 2567c31335aSMaruthi Srinivas Bayyavarapu u16 i; 2577c31335aSMaruthi Srinivas Bayyavarapu acp_dma_dscr_transfer_t dmadscr[NUM_DSCRS_PER_CHANNEL]; 2587c31335aSMaruthi Srinivas Bayyavarapu 2597c31335aSMaruthi Srinivas Bayyavarapu for (i = 0; i < NUM_DSCRS_PER_CHANNEL; i++) { 2607c31335aSMaruthi Srinivas Bayyavarapu dmadscr[i].xfer_val = 0; 2617c31335aSMaruthi Srinivas Bayyavarapu if (direction == SNDRV_PCM_STREAM_PLAYBACK) { 2624376a86cSMukunda, Vijendar dma_dscr_idx = dma_dscr_idx + i; 2634376a86cSMukunda, Vijendar dmadscr[i].src = sram_bank + (i * (size / 2)); 2647c31335aSMaruthi Srinivas Bayyavarapu /* dmadscr[i].dest is unused by hardware. */ 2657c31335aSMaruthi Srinivas Bayyavarapu dmadscr[i].dest = 0; 2664376a86cSMukunda, Vijendar dmadscr[i].xfer_val |= BIT(22) | (destination << 16) | 2677c31335aSMaruthi Srinivas Bayyavarapu (size / 2); 2687c31335aSMaruthi Srinivas Bayyavarapu } else { 2694376a86cSMukunda, Vijendar dma_dscr_idx = dma_dscr_idx + i; 2707c31335aSMaruthi Srinivas Bayyavarapu /* dmadscr[i].src is unused by hardware. */ 2717c31335aSMaruthi Srinivas Bayyavarapu dmadscr[i].src = 0; 272aac89748SVijendar Mukunda dmadscr[i].dest = 2734376a86cSMukunda, Vijendar sram_bank + (i * (size / 2)); 2747c31335aSMaruthi Srinivas Bayyavarapu dmadscr[i].xfer_val |= BIT(22) | 2754376a86cSMukunda, Vijendar (destination << 16) | (size / 2); 2767c31335aSMaruthi Srinivas Bayyavarapu } 2777c31335aSMaruthi Srinivas Bayyavarapu config_dma_descriptor_in_sram(acp_mmio, dma_dscr_idx, 2787c31335aSMaruthi Srinivas Bayyavarapu &dmadscr[i]); 2797c31335aSMaruthi Srinivas Bayyavarapu } 2807c31335aSMaruthi Srinivas Bayyavarapu /* Configure the DMA channel with the above descriptore */ 2814376a86cSMukunda, Vijendar config_acp_dma_channel(acp_mmio, ch, dma_dscr_idx - 1, 2827c31335aSMaruthi Srinivas Bayyavarapu NUM_DSCRS_PER_CHANNEL, 2837c31335aSMaruthi Srinivas Bayyavarapu ACP_DMA_PRIORITY_LEVEL_NORMAL); 2847c31335aSMaruthi Srinivas Bayyavarapu } 2857c31335aSMaruthi Srinivas Bayyavarapu 2867c31335aSMaruthi Srinivas Bayyavarapu /* Create page table entries in ACP SRAM for the allocated memory */ 2877c31335aSMaruthi Srinivas Bayyavarapu static void acp_pte_config(void __iomem *acp_mmio, struct page *pg, 2887c31335aSMaruthi Srinivas Bayyavarapu u16 num_of_pages, u32 pte_offset) 2897c31335aSMaruthi Srinivas Bayyavarapu { 2907c31335aSMaruthi Srinivas Bayyavarapu u16 page_idx; 2917c31335aSMaruthi Srinivas Bayyavarapu u64 addr; 2927c31335aSMaruthi Srinivas Bayyavarapu u32 low; 2937c31335aSMaruthi Srinivas Bayyavarapu u32 high; 2947c31335aSMaruthi Srinivas Bayyavarapu u32 offset; 2957c31335aSMaruthi Srinivas Bayyavarapu 2967c31335aSMaruthi Srinivas Bayyavarapu offset = ACP_DAGB_GRP_SRBM_SRAM_BASE_OFFSET + (pte_offset * 8); 2977c31335aSMaruthi Srinivas Bayyavarapu for (page_idx = 0; page_idx < (num_of_pages); page_idx++) { 2987c31335aSMaruthi Srinivas Bayyavarapu /* Load the low address of page int ACP SRAM through SRBM */ 2997c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write((offset + (page_idx * 8)), 3007c31335aSMaruthi Srinivas Bayyavarapu acp_mmio, mmACP_SRBM_Targ_Idx_Addr); 3017c31335aSMaruthi Srinivas Bayyavarapu addr = page_to_phys(pg); 3027c31335aSMaruthi Srinivas Bayyavarapu 3037c31335aSMaruthi Srinivas Bayyavarapu low = lower_32_bits(addr); 3047c31335aSMaruthi Srinivas Bayyavarapu high = upper_32_bits(addr); 3057c31335aSMaruthi Srinivas Bayyavarapu 3067c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(low, acp_mmio, mmACP_SRBM_Targ_Idx_Data); 3077c31335aSMaruthi Srinivas Bayyavarapu 3087c31335aSMaruthi Srinivas Bayyavarapu /* Load the High address of page int ACP SRAM through SRBM */ 3097c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write((offset + (page_idx * 8) + 4), 3107c31335aSMaruthi Srinivas Bayyavarapu acp_mmio, mmACP_SRBM_Targ_Idx_Addr); 3117c31335aSMaruthi Srinivas Bayyavarapu 3127c31335aSMaruthi Srinivas Bayyavarapu /* page enable in ACP */ 3137c31335aSMaruthi Srinivas Bayyavarapu high |= BIT(31); 3147c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(high, acp_mmio, mmACP_SRBM_Targ_Idx_Data); 3157c31335aSMaruthi Srinivas Bayyavarapu 3167c31335aSMaruthi Srinivas Bayyavarapu /* Move to next physically contiguos page */ 3177c31335aSMaruthi Srinivas Bayyavarapu pg++; 3187c31335aSMaruthi Srinivas Bayyavarapu } 3197c31335aSMaruthi Srinivas Bayyavarapu } 3207c31335aSMaruthi Srinivas Bayyavarapu 3217c31335aSMaruthi Srinivas Bayyavarapu static void config_acp_dma(void __iomem *acp_mmio, 3228349b7f5SMukunda, Vijendar struct audio_substream_data *rtd, 323aac89748SVijendar Mukunda u32 asic_type) 3247c31335aSMaruthi Srinivas Bayyavarapu { 3258349b7f5SMukunda, Vijendar acp_pte_config(acp_mmio, rtd->pg, rtd->num_of_pages, 326e188c525SMukunda, Vijendar rtd->pte_offset); 3277c31335aSMaruthi Srinivas Bayyavarapu /* Configure System memory <-> ACP SRAM DMA descriptors */ 3288349b7f5SMukunda, Vijendar set_acp_sysmem_dma_descriptors(acp_mmio, rtd->size, 329e188c525SMukunda, Vijendar rtd->direction, rtd->pte_offset, 33018e8a40dSMukunda, Vijendar rtd->ch1, rtd->sram_bank, 3318769bb55SVijendar Mukunda rtd->dma_dscr_idx_1, asic_type); 3327c31335aSMaruthi Srinivas Bayyavarapu /* Configure ACP SRAM <-> I2S DMA descriptors */ 3338349b7f5SMukunda, Vijendar set_acp_to_i2s_dma_descriptors(acp_mmio, rtd->size, 33418e8a40dSMukunda, Vijendar rtd->direction, rtd->sram_bank, 3358769bb55SVijendar Mukunda rtd->destination, rtd->ch2, 3368769bb55SVijendar Mukunda rtd->dma_dscr_idx_2, asic_type); 3377c31335aSMaruthi Srinivas Bayyavarapu } 3387c31335aSMaruthi Srinivas Bayyavarapu 3392718c89aSAkshu Agrawal static void acp_dma_cap_channel_enable(void __iomem *acp_mmio, 3402718c89aSAkshu Agrawal u16 cap_channel) 3412718c89aSAkshu Agrawal { 3422718c89aSAkshu Agrawal u32 val, ch_reg, imr_reg, res_reg; 3432718c89aSAkshu Agrawal 3442718c89aSAkshu Agrawal switch (cap_channel) { 3452718c89aSAkshu Agrawal case CAP_CHANNEL1: 3462718c89aSAkshu Agrawal ch_reg = mmACP_I2SMICSP_RER1; 3472718c89aSAkshu Agrawal res_reg = mmACP_I2SMICSP_RCR1; 3482718c89aSAkshu Agrawal imr_reg = mmACP_I2SMICSP_IMR1; 3492718c89aSAkshu Agrawal break; 3502718c89aSAkshu Agrawal case CAP_CHANNEL0: 3512718c89aSAkshu Agrawal default: 3522718c89aSAkshu Agrawal ch_reg = mmACP_I2SMICSP_RER0; 3532718c89aSAkshu Agrawal res_reg = mmACP_I2SMICSP_RCR0; 3542718c89aSAkshu Agrawal imr_reg = mmACP_I2SMICSP_IMR0; 3552718c89aSAkshu Agrawal break; 3562718c89aSAkshu Agrawal } 3572718c89aSAkshu Agrawal val = acp_reg_read(acp_mmio, 3582718c89aSAkshu Agrawal mmACP_I2S_16BIT_RESOLUTION_EN); 3592718c89aSAkshu Agrawal if (val & ACP_I2S_MIC_16BIT_RESOLUTION_EN) { 3602718c89aSAkshu Agrawal acp_reg_write(0x0, acp_mmio, ch_reg); 3612718c89aSAkshu Agrawal /* Set 16bit resolution on capture */ 3622718c89aSAkshu Agrawal acp_reg_write(0x2, acp_mmio, res_reg); 3632718c89aSAkshu Agrawal } 3642718c89aSAkshu Agrawal val = acp_reg_read(acp_mmio, imr_reg); 3652718c89aSAkshu Agrawal val &= ~ACP_I2SMICSP_IMR1__I2SMICSP_RXDAM_MASK; 3662718c89aSAkshu Agrawal val &= ~ACP_I2SMICSP_IMR1__I2SMICSP_RXFOM_MASK; 3672718c89aSAkshu Agrawal acp_reg_write(val, acp_mmio, imr_reg); 3682718c89aSAkshu Agrawal acp_reg_write(0x1, acp_mmio, ch_reg); 3692718c89aSAkshu Agrawal } 3702718c89aSAkshu Agrawal 3712718c89aSAkshu Agrawal static void acp_dma_cap_channel_disable(void __iomem *acp_mmio, 3722718c89aSAkshu Agrawal u16 cap_channel) 3732718c89aSAkshu Agrawal { 3742718c89aSAkshu Agrawal u32 val, ch_reg, imr_reg; 3752718c89aSAkshu Agrawal 3762718c89aSAkshu Agrawal switch (cap_channel) { 3772718c89aSAkshu Agrawal case CAP_CHANNEL1: 3782718c89aSAkshu Agrawal imr_reg = mmACP_I2SMICSP_IMR1; 3792718c89aSAkshu Agrawal ch_reg = mmACP_I2SMICSP_RER1; 3802718c89aSAkshu Agrawal break; 3812718c89aSAkshu Agrawal case CAP_CHANNEL0: 3822718c89aSAkshu Agrawal default: 3832718c89aSAkshu Agrawal imr_reg = mmACP_I2SMICSP_IMR0; 3842718c89aSAkshu Agrawal ch_reg = mmACP_I2SMICSP_RER0; 3852718c89aSAkshu Agrawal break; 3862718c89aSAkshu Agrawal } 3872718c89aSAkshu Agrawal val = acp_reg_read(acp_mmio, imr_reg); 3882718c89aSAkshu Agrawal val |= ACP_I2SMICSP_IMR1__I2SMICSP_RXDAM_MASK; 3892718c89aSAkshu Agrawal val |= ACP_I2SMICSP_IMR1__I2SMICSP_RXFOM_MASK; 3902718c89aSAkshu Agrawal acp_reg_write(val, acp_mmio, imr_reg); 3912718c89aSAkshu Agrawal acp_reg_write(0x0, acp_mmio, ch_reg); 3922718c89aSAkshu Agrawal } 3932718c89aSAkshu Agrawal 3947c31335aSMaruthi Srinivas Bayyavarapu /* Start a given DMA channel transfer */ 3956b116dfbSAgrawal, Akshu static void acp_dma_start(void __iomem *acp_mmio, u16 ch_num) 3967c31335aSMaruthi Srinivas Bayyavarapu { 3977c31335aSMaruthi Srinivas Bayyavarapu u32 dma_ctrl; 3987c31335aSMaruthi Srinivas Bayyavarapu 3997c31335aSMaruthi Srinivas Bayyavarapu /* read the dma control register and disable the channel run field */ 4007c31335aSMaruthi Srinivas Bayyavarapu dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 4017c31335aSMaruthi Srinivas Bayyavarapu 4027c31335aSMaruthi Srinivas Bayyavarapu /* Invalidating the DAGB cache */ 4037c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(1, acp_mmio, mmACP_DAGB_ATU_CTRL); 4047c31335aSMaruthi Srinivas Bayyavarapu 40513838c11SMukunda, Vijendar /* 40613838c11SMukunda, Vijendar * configure the DMA channel and start the DMA transfer 4077c31335aSMaruthi Srinivas Bayyavarapu * set dmachrun bit to start the transfer and enable the 4087c31335aSMaruthi Srinivas Bayyavarapu * interrupt on completion of the dma transfer 4097c31335aSMaruthi Srinivas Bayyavarapu */ 4107c31335aSMaruthi Srinivas Bayyavarapu dma_ctrl |= ACP_DMA_CNTL_0__DMAChRun_MASK; 4117c31335aSMaruthi Srinivas Bayyavarapu 4127c31335aSMaruthi Srinivas Bayyavarapu switch (ch_num) { 4137c31335aSMaruthi Srinivas Bayyavarapu case ACP_TO_I2S_DMA_CH_NUM: 4147c31335aSMaruthi Srinivas Bayyavarapu case ACP_TO_SYSRAM_CH_NUM: 415ccfbb4f5SMukunda, Vijendar case ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM: 416ccfbb4f5SMukunda, Vijendar case ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM: 4177c31335aSMaruthi Srinivas Bayyavarapu dma_ctrl |= ACP_DMA_CNTL_0__DMAChIOCEn_MASK; 4187c31335aSMaruthi Srinivas Bayyavarapu break; 4197c31335aSMaruthi Srinivas Bayyavarapu default: 4207c31335aSMaruthi Srinivas Bayyavarapu dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChIOCEn_MASK; 4217c31335aSMaruthi Srinivas Bayyavarapu break; 4227c31335aSMaruthi Srinivas Bayyavarapu } 4237c31335aSMaruthi Srinivas Bayyavarapu 4246b116dfbSAgrawal, Akshu /* circular for both DMA channel */ 4257c31335aSMaruthi Srinivas Bayyavarapu dma_ctrl |= ACP_DMA_CNTL_0__Circular_DMA_En_MASK; 4267c31335aSMaruthi Srinivas Bayyavarapu 4277c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 4287c31335aSMaruthi Srinivas Bayyavarapu } 4297c31335aSMaruthi Srinivas Bayyavarapu 4307c31335aSMaruthi Srinivas Bayyavarapu /* Stop a given DMA channel transfer */ 4317c31335aSMaruthi Srinivas Bayyavarapu static int acp_dma_stop(void __iomem *acp_mmio, u8 ch_num) 4327c31335aSMaruthi Srinivas Bayyavarapu { 4337c31335aSMaruthi Srinivas Bayyavarapu u32 dma_ctrl; 4347c31335aSMaruthi Srinivas Bayyavarapu u32 dma_ch_sts; 4357c31335aSMaruthi Srinivas Bayyavarapu u32 count = ACP_DMA_RESET_TIME; 4367c31335aSMaruthi Srinivas Bayyavarapu 4377c31335aSMaruthi Srinivas Bayyavarapu dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 4387c31335aSMaruthi Srinivas Bayyavarapu 43913838c11SMukunda, Vijendar /* 44013838c11SMukunda, Vijendar * clear the dma control register fields before writing zero 4417c31335aSMaruthi Srinivas Bayyavarapu * in reset bit 4427c31335aSMaruthi Srinivas Bayyavarapu */ 4437c31335aSMaruthi Srinivas Bayyavarapu dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRun_MASK; 4447c31335aSMaruthi Srinivas Bayyavarapu dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChIOCEn_MASK; 4457c31335aSMaruthi Srinivas Bayyavarapu 4467c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 4477c31335aSMaruthi Srinivas Bayyavarapu dma_ch_sts = acp_reg_read(acp_mmio, mmACP_DMA_CH_STS); 4487c31335aSMaruthi Srinivas Bayyavarapu 4497c31335aSMaruthi Srinivas Bayyavarapu if (dma_ch_sts & BIT(ch_num)) { 45013838c11SMukunda, Vijendar /* 45113838c11SMukunda, Vijendar * set the reset bit for this channel to stop the dma 4527c31335aSMaruthi Srinivas Bayyavarapu * transfer 4537c31335aSMaruthi Srinivas Bayyavarapu */ 4547c31335aSMaruthi Srinivas Bayyavarapu dma_ctrl |= ACP_DMA_CNTL_0__DMAChRst_MASK; 4557c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 4567c31335aSMaruthi Srinivas Bayyavarapu } 4577c31335aSMaruthi Srinivas Bayyavarapu 4587c31335aSMaruthi Srinivas Bayyavarapu /* check the channel status bit for some time and return the status */ 4597c31335aSMaruthi Srinivas Bayyavarapu while (true) { 4607c31335aSMaruthi Srinivas Bayyavarapu dma_ch_sts = acp_reg_read(acp_mmio, mmACP_DMA_CH_STS); 4617c31335aSMaruthi Srinivas Bayyavarapu if (!(dma_ch_sts & BIT(ch_num))) { 46213838c11SMukunda, Vijendar /* 46313838c11SMukunda, Vijendar * clear the reset flag after successfully stopping 4647c31335aSMaruthi Srinivas Bayyavarapu * the dma transfer and break from the loop 4657c31335aSMaruthi Srinivas Bayyavarapu */ 4667c31335aSMaruthi Srinivas Bayyavarapu dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRst_MASK; 4677c31335aSMaruthi Srinivas Bayyavarapu 4687c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 4697c31335aSMaruthi Srinivas Bayyavarapu + ch_num); 4707c31335aSMaruthi Srinivas Bayyavarapu break; 4717c31335aSMaruthi Srinivas Bayyavarapu } 4727c31335aSMaruthi Srinivas Bayyavarapu if (--count == 0) { 4737c31335aSMaruthi Srinivas Bayyavarapu pr_err("Failed to stop ACP DMA channel : %d\n", ch_num); 4747c31335aSMaruthi Srinivas Bayyavarapu return -ETIMEDOUT; 4757c31335aSMaruthi Srinivas Bayyavarapu } 4767c31335aSMaruthi Srinivas Bayyavarapu udelay(100); 4777c31335aSMaruthi Srinivas Bayyavarapu } 4787c31335aSMaruthi Srinivas Bayyavarapu return 0; 4797c31335aSMaruthi Srinivas Bayyavarapu } 4807c31335aSMaruthi Srinivas Bayyavarapu 481c36d9b3fSMaruthi Srinivas Bayyavarapu static void acp_set_sram_bank_state(void __iomem *acp_mmio, u16 bank, 482c36d9b3fSMaruthi Srinivas Bayyavarapu bool power_on) 483c36d9b3fSMaruthi Srinivas Bayyavarapu { 484c36d9b3fSMaruthi Srinivas Bayyavarapu u32 val, req_reg, sts_reg, sts_reg_mask; 485c36d9b3fSMaruthi Srinivas Bayyavarapu u32 loops = 1000; 486c36d9b3fSMaruthi Srinivas Bayyavarapu 487c36d9b3fSMaruthi Srinivas Bayyavarapu if (bank < 32) { 488c36d9b3fSMaruthi Srinivas Bayyavarapu req_reg = mmACP_MEM_SHUT_DOWN_REQ_LO; 489c36d9b3fSMaruthi Srinivas Bayyavarapu sts_reg = mmACP_MEM_SHUT_DOWN_STS_LO; 490c36d9b3fSMaruthi Srinivas Bayyavarapu sts_reg_mask = 0xFFFFFFFF; 491c36d9b3fSMaruthi Srinivas Bayyavarapu 492c36d9b3fSMaruthi Srinivas Bayyavarapu } else { 493c36d9b3fSMaruthi Srinivas Bayyavarapu bank -= 32; 494c36d9b3fSMaruthi Srinivas Bayyavarapu req_reg = mmACP_MEM_SHUT_DOWN_REQ_HI; 495c36d9b3fSMaruthi Srinivas Bayyavarapu sts_reg = mmACP_MEM_SHUT_DOWN_STS_HI; 496c36d9b3fSMaruthi Srinivas Bayyavarapu sts_reg_mask = 0x0000FFFF; 497c36d9b3fSMaruthi Srinivas Bayyavarapu } 498c36d9b3fSMaruthi Srinivas Bayyavarapu 499c36d9b3fSMaruthi Srinivas Bayyavarapu val = acp_reg_read(acp_mmio, req_reg); 500c36d9b3fSMaruthi Srinivas Bayyavarapu if (val & (1 << bank)) { 501c36d9b3fSMaruthi Srinivas Bayyavarapu /* bank is in off state */ 502c36d9b3fSMaruthi Srinivas Bayyavarapu if (power_on == true) 503c36d9b3fSMaruthi Srinivas Bayyavarapu /* request to on */ 504c36d9b3fSMaruthi Srinivas Bayyavarapu val &= ~(1 << bank); 505c36d9b3fSMaruthi Srinivas Bayyavarapu else 506c36d9b3fSMaruthi Srinivas Bayyavarapu /* request to off */ 507c36d9b3fSMaruthi Srinivas Bayyavarapu return; 508c36d9b3fSMaruthi Srinivas Bayyavarapu } else { 509c36d9b3fSMaruthi Srinivas Bayyavarapu /* bank is in on state */ 510c36d9b3fSMaruthi Srinivas Bayyavarapu if (power_on == false) 511c36d9b3fSMaruthi Srinivas Bayyavarapu /* request to off */ 512c36d9b3fSMaruthi Srinivas Bayyavarapu val |= 1 << bank; 513c36d9b3fSMaruthi Srinivas Bayyavarapu else 514c36d9b3fSMaruthi Srinivas Bayyavarapu /* request to on */ 515c36d9b3fSMaruthi Srinivas Bayyavarapu return; 516c36d9b3fSMaruthi Srinivas Bayyavarapu } 517c36d9b3fSMaruthi Srinivas Bayyavarapu acp_reg_write(val, acp_mmio, req_reg); 518c36d9b3fSMaruthi Srinivas Bayyavarapu 519c36d9b3fSMaruthi Srinivas Bayyavarapu while (acp_reg_read(acp_mmio, sts_reg) != sts_reg_mask) { 520c36d9b3fSMaruthi Srinivas Bayyavarapu if (!loops--) { 521c36d9b3fSMaruthi Srinivas Bayyavarapu pr_err("ACP SRAM bank %d state change failed\n", bank); 522c36d9b3fSMaruthi Srinivas Bayyavarapu break; 523c36d9b3fSMaruthi Srinivas Bayyavarapu } 524c36d9b3fSMaruthi Srinivas Bayyavarapu cpu_relax(); 525c36d9b3fSMaruthi Srinivas Bayyavarapu } 526c36d9b3fSMaruthi Srinivas Bayyavarapu } 527c36d9b3fSMaruthi Srinivas Bayyavarapu 5287c31335aSMaruthi Srinivas Bayyavarapu /* Initialize and bring ACP hardware to default state. */ 529607b39efSVijendar Mukunda static int acp_init(void __iomem *acp_mmio, u32 asic_type) 5307c31335aSMaruthi Srinivas Bayyavarapu { 531c36d9b3fSMaruthi Srinivas Bayyavarapu u16 bank; 5327c31335aSMaruthi Srinivas Bayyavarapu u32 val, count, sram_pte_offset; 5337c31335aSMaruthi Srinivas Bayyavarapu 5347c31335aSMaruthi Srinivas Bayyavarapu /* Assert Soft reset of ACP */ 5357c31335aSMaruthi Srinivas Bayyavarapu val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET); 5367c31335aSMaruthi Srinivas Bayyavarapu 5377c31335aSMaruthi Srinivas Bayyavarapu val |= ACP_SOFT_RESET__SoftResetAud_MASK; 5387c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET); 5397c31335aSMaruthi Srinivas Bayyavarapu 5407c31335aSMaruthi Srinivas Bayyavarapu count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE; 5417c31335aSMaruthi Srinivas Bayyavarapu while (true) { 5427c31335aSMaruthi Srinivas Bayyavarapu val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET); 5437c31335aSMaruthi Srinivas Bayyavarapu if (ACP_SOFT_RESET__SoftResetAudDone_MASK == 5447c31335aSMaruthi Srinivas Bayyavarapu (val & ACP_SOFT_RESET__SoftResetAudDone_MASK)) 5457c31335aSMaruthi Srinivas Bayyavarapu break; 5467c31335aSMaruthi Srinivas Bayyavarapu if (--count == 0) { 5477c31335aSMaruthi Srinivas Bayyavarapu pr_err("Failed to reset ACP\n"); 5487c31335aSMaruthi Srinivas Bayyavarapu return -ETIMEDOUT; 5497c31335aSMaruthi Srinivas Bayyavarapu } 5507c31335aSMaruthi Srinivas Bayyavarapu udelay(100); 5517c31335aSMaruthi Srinivas Bayyavarapu } 5527c31335aSMaruthi Srinivas Bayyavarapu 5537c31335aSMaruthi Srinivas Bayyavarapu /* Enable clock to ACP and wait until the clock is enabled */ 5547c31335aSMaruthi Srinivas Bayyavarapu val = acp_reg_read(acp_mmio, mmACP_CONTROL); 5557c31335aSMaruthi Srinivas Bayyavarapu val = val | ACP_CONTROL__ClkEn_MASK; 5567c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(val, acp_mmio, mmACP_CONTROL); 5577c31335aSMaruthi Srinivas Bayyavarapu 5587c31335aSMaruthi Srinivas Bayyavarapu count = ACP_CLOCK_EN_TIME_OUT_VALUE; 5597c31335aSMaruthi Srinivas Bayyavarapu 5607c31335aSMaruthi Srinivas Bayyavarapu while (true) { 5617c31335aSMaruthi Srinivas Bayyavarapu val = acp_reg_read(acp_mmio, mmACP_STATUS); 5627c31335aSMaruthi Srinivas Bayyavarapu if (val & (u32)0x1) 5637c31335aSMaruthi Srinivas Bayyavarapu break; 5647c31335aSMaruthi Srinivas Bayyavarapu if (--count == 0) { 5657c31335aSMaruthi Srinivas Bayyavarapu pr_err("Failed to reset ACP\n"); 5667c31335aSMaruthi Srinivas Bayyavarapu return -ETIMEDOUT; 5677c31335aSMaruthi Srinivas Bayyavarapu } 5687c31335aSMaruthi Srinivas Bayyavarapu udelay(100); 5697c31335aSMaruthi Srinivas Bayyavarapu } 5707c31335aSMaruthi Srinivas Bayyavarapu 5717c31335aSMaruthi Srinivas Bayyavarapu /* Deassert the SOFT RESET flags */ 5727c31335aSMaruthi Srinivas Bayyavarapu val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET); 5737c31335aSMaruthi Srinivas Bayyavarapu val &= ~ACP_SOFT_RESET__SoftResetAud_MASK; 5747c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET); 5757c31335aSMaruthi Srinivas Bayyavarapu 576ccfbb4f5SMukunda, Vijendar /* For BT instance change pins from UART to BT */ 577ccfbb4f5SMukunda, Vijendar if (!bt_uart_enable) { 578ccfbb4f5SMukunda, Vijendar val = acp_reg_read(acp_mmio, mmACP_BT_UART_PAD_SEL); 579ccfbb4f5SMukunda, Vijendar val |= ACP_BT_UART_PAD_SELECT_MASK; 580ccfbb4f5SMukunda, Vijendar acp_reg_write(val, acp_mmio, mmACP_BT_UART_PAD_SEL); 581ccfbb4f5SMukunda, Vijendar } 582ccfbb4f5SMukunda, Vijendar 5837c31335aSMaruthi Srinivas Bayyavarapu /* initiailize Onion control DAGB register */ 5847c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(ACP_ONION_CNTL_DEFAULT, acp_mmio, 5857c31335aSMaruthi Srinivas Bayyavarapu mmACP_AXI2DAGB_ONION_CNTL); 5867c31335aSMaruthi Srinivas Bayyavarapu 5877c31335aSMaruthi Srinivas Bayyavarapu /* initiailize Garlic control DAGB registers */ 5887c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(ACP_GARLIC_CNTL_DEFAULT, acp_mmio, 5897c31335aSMaruthi Srinivas Bayyavarapu mmACP_AXI2DAGB_GARLIC_CNTL); 5907c31335aSMaruthi Srinivas Bayyavarapu 5917c31335aSMaruthi Srinivas Bayyavarapu sram_pte_offset = ACP_DAGB_GRP_SRAM_BASE_ADDRESS | 5927c31335aSMaruthi Srinivas Bayyavarapu ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBSnoopSel_MASK | 5937c31335aSMaruthi Srinivas Bayyavarapu ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBTargetMemSel_MASK | 5947c31335aSMaruthi Srinivas Bayyavarapu ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBGrpEnable_MASK; 5957c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(sram_pte_offset, acp_mmio, mmACP_DAGB_BASE_ADDR_GRP_1); 5967c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(ACP_PAGE_SIZE_4K_ENABLE, acp_mmio, 5977c31335aSMaruthi Srinivas Bayyavarapu mmACP_DAGB_PAGE_SIZE_GRP_1); 5987c31335aSMaruthi Srinivas Bayyavarapu 5997c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(ACP_SRAM_BASE_ADDRESS, acp_mmio, 6007c31335aSMaruthi Srinivas Bayyavarapu mmACP_DMA_DESC_BASE_ADDR); 6017c31335aSMaruthi Srinivas Bayyavarapu 6027c31335aSMaruthi Srinivas Bayyavarapu /* Num of descriptiors in SRAM 0x4, means 256 descriptors;(64 * 4) */ 6037c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(0x4, acp_mmio, mmACP_DMA_DESC_MAX_NUM_DSCR); 6047c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(ACP_EXTERNAL_INTR_CNTL__DMAIOCMask_MASK, 6057c31335aSMaruthi Srinivas Bayyavarapu acp_mmio, mmACP_EXTERNAL_INTR_CNTL); 6067c31335aSMaruthi Srinivas Bayyavarapu 60713838c11SMukunda, Vijendar /* 60813838c11SMukunda, Vijendar * When ACP_TILE_P1 is turned on, all SRAM banks get turned on. 609c36d9b3fSMaruthi Srinivas Bayyavarapu * Now, turn off all of them. This can't be done in 'poweron' of 610c36d9b3fSMaruthi Srinivas Bayyavarapu * ACP pm domain, as this requires ACP to be initialized. 611607b39efSVijendar Mukunda * For Stoney, Memory gating is disabled,i.e SRAM Banks 612607b39efSVijendar Mukunda * won't be turned off. The default state for SRAM banks is ON. 613607b39efSVijendar Mukunda * Setting SRAM bank state code skipped for STONEY platform. 614c36d9b3fSMaruthi Srinivas Bayyavarapu */ 615607b39efSVijendar Mukunda if (asic_type != CHIP_STONEY) { 616c36d9b3fSMaruthi Srinivas Bayyavarapu for (bank = 1; bank < 48; bank++) 617c36d9b3fSMaruthi Srinivas Bayyavarapu acp_set_sram_bank_state(acp_mmio, bank, false); 618607b39efSVijendar Mukunda } 6197c31335aSMaruthi Srinivas Bayyavarapu return 0; 6207c31335aSMaruthi Srinivas Bayyavarapu } 6217c31335aSMaruthi Srinivas Bayyavarapu 6221cce2000SMasahiro Yamada /* Deinitialize ACP */ 6237c31335aSMaruthi Srinivas Bayyavarapu static int acp_deinit(void __iomem *acp_mmio) 6247c31335aSMaruthi Srinivas Bayyavarapu { 6257c31335aSMaruthi Srinivas Bayyavarapu u32 val; 6267c31335aSMaruthi Srinivas Bayyavarapu u32 count; 6277c31335aSMaruthi Srinivas Bayyavarapu 6287c31335aSMaruthi Srinivas Bayyavarapu /* Assert Soft reset of ACP */ 6297c31335aSMaruthi Srinivas Bayyavarapu val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET); 6307c31335aSMaruthi Srinivas Bayyavarapu 6317c31335aSMaruthi Srinivas Bayyavarapu val |= ACP_SOFT_RESET__SoftResetAud_MASK; 6327c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET); 6337c31335aSMaruthi Srinivas Bayyavarapu 6347c31335aSMaruthi Srinivas Bayyavarapu count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE; 6357c31335aSMaruthi Srinivas Bayyavarapu while (true) { 6367c31335aSMaruthi Srinivas Bayyavarapu val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET); 6377c31335aSMaruthi Srinivas Bayyavarapu if (ACP_SOFT_RESET__SoftResetAudDone_MASK == 6387c31335aSMaruthi Srinivas Bayyavarapu (val & ACP_SOFT_RESET__SoftResetAudDone_MASK)) 6397c31335aSMaruthi Srinivas Bayyavarapu break; 6407c31335aSMaruthi Srinivas Bayyavarapu if (--count == 0) { 6417c31335aSMaruthi Srinivas Bayyavarapu pr_err("Failed to reset ACP\n"); 6427c31335aSMaruthi Srinivas Bayyavarapu return -ETIMEDOUT; 6437c31335aSMaruthi Srinivas Bayyavarapu } 6447c31335aSMaruthi Srinivas Bayyavarapu udelay(100); 6457c31335aSMaruthi Srinivas Bayyavarapu } 64613838c11SMukunda, Vijendar /* Disable ACP clock */ 6477c31335aSMaruthi Srinivas Bayyavarapu val = acp_reg_read(acp_mmio, mmACP_CONTROL); 6487c31335aSMaruthi Srinivas Bayyavarapu val &= ~ACP_CONTROL__ClkEn_MASK; 6497c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(val, acp_mmio, mmACP_CONTROL); 6507c31335aSMaruthi Srinivas Bayyavarapu 6517c31335aSMaruthi Srinivas Bayyavarapu count = ACP_CLOCK_EN_TIME_OUT_VALUE; 6527c31335aSMaruthi Srinivas Bayyavarapu 6537c31335aSMaruthi Srinivas Bayyavarapu while (true) { 6547c31335aSMaruthi Srinivas Bayyavarapu val = acp_reg_read(acp_mmio, mmACP_STATUS); 6557c31335aSMaruthi Srinivas Bayyavarapu if (!(val & (u32)0x1)) 6567c31335aSMaruthi Srinivas Bayyavarapu break; 6577c31335aSMaruthi Srinivas Bayyavarapu if (--count == 0) { 6587c31335aSMaruthi Srinivas Bayyavarapu pr_err("Failed to reset ACP\n"); 6597c31335aSMaruthi Srinivas Bayyavarapu return -ETIMEDOUT; 6607c31335aSMaruthi Srinivas Bayyavarapu } 6617c31335aSMaruthi Srinivas Bayyavarapu udelay(100); 6627c31335aSMaruthi Srinivas Bayyavarapu } 6637c31335aSMaruthi Srinivas Bayyavarapu return 0; 6647c31335aSMaruthi Srinivas Bayyavarapu } 6657c31335aSMaruthi Srinivas Bayyavarapu 6667c31335aSMaruthi Srinivas Bayyavarapu /* ACP DMA irq handler routine for playback, capture usecases */ 6677c31335aSMaruthi Srinivas Bayyavarapu static irqreturn_t dma_irq_handler(int irq, void *arg) 6687c31335aSMaruthi Srinivas Bayyavarapu { 6697c31335aSMaruthi Srinivas Bayyavarapu u32 intr_flag, ext_intr_status; 6707c31335aSMaruthi Srinivas Bayyavarapu struct audio_drv_data *irq_data; 6717c31335aSMaruthi Srinivas Bayyavarapu void __iomem *acp_mmio; 6727c31335aSMaruthi Srinivas Bayyavarapu struct device *dev = arg; 6737c31335aSMaruthi Srinivas Bayyavarapu bool valid_irq = false; 6747c31335aSMaruthi Srinivas Bayyavarapu 6757c31335aSMaruthi Srinivas Bayyavarapu irq_data = dev_get_drvdata(dev); 6767c31335aSMaruthi Srinivas Bayyavarapu acp_mmio = irq_data->acp_mmio; 6777c31335aSMaruthi Srinivas Bayyavarapu 6787c31335aSMaruthi Srinivas Bayyavarapu ext_intr_status = acp_reg_read(acp_mmio, mmACP_EXTERNAL_INTR_STAT); 6797c31335aSMaruthi Srinivas Bayyavarapu intr_flag = (((ext_intr_status & 6807c31335aSMaruthi Srinivas Bayyavarapu ACP_EXTERNAL_INTR_STAT__DMAIOCStat_MASK) >> 6817c31335aSMaruthi Srinivas Bayyavarapu ACP_EXTERNAL_INTR_STAT__DMAIOCStat__SHIFT)); 6827c31335aSMaruthi Srinivas Bayyavarapu 6837c31335aSMaruthi Srinivas Bayyavarapu if ((intr_flag & BIT(ACP_TO_I2S_DMA_CH_NUM)) != 0) { 6847c31335aSMaruthi Srinivas Bayyavarapu valid_irq = true; 685e21358c4SMukunda, Vijendar snd_pcm_period_elapsed(irq_data->play_i2ssp_stream); 6867c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write((intr_flag & BIT(ACP_TO_I2S_DMA_CH_NUM)) << 16, 6877c31335aSMaruthi Srinivas Bayyavarapu acp_mmio, mmACP_EXTERNAL_INTR_STAT); 6887c31335aSMaruthi Srinivas Bayyavarapu } 6897c31335aSMaruthi Srinivas Bayyavarapu 690ccfbb4f5SMukunda, Vijendar if ((intr_flag & BIT(ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM)) != 0) { 691ccfbb4f5SMukunda, Vijendar valid_irq = true; 692ccfbb4f5SMukunda, Vijendar snd_pcm_period_elapsed(irq_data->play_i2sbt_stream); 693ccfbb4f5SMukunda, Vijendar acp_reg_write((intr_flag & 694ccfbb4f5SMukunda, Vijendar BIT(ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM)) << 16, 695ccfbb4f5SMukunda, Vijendar acp_mmio, mmACP_EXTERNAL_INTR_STAT); 696ccfbb4f5SMukunda, Vijendar } 697ccfbb4f5SMukunda, Vijendar 6987c31335aSMaruthi Srinivas Bayyavarapu if ((intr_flag & BIT(ACP_TO_SYSRAM_CH_NUM)) != 0) { 6997c31335aSMaruthi Srinivas Bayyavarapu valid_irq = true; 70055af49acSDaniel Kurtz snd_pcm_period_elapsed(irq_data->capture_i2ssp_stream); 7017c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write((intr_flag & BIT(ACP_TO_SYSRAM_CH_NUM)) << 16, 7027c31335aSMaruthi Srinivas Bayyavarapu acp_mmio, mmACP_EXTERNAL_INTR_STAT); 7037c31335aSMaruthi Srinivas Bayyavarapu } 7047c31335aSMaruthi Srinivas Bayyavarapu 705ccfbb4f5SMukunda, Vijendar if ((intr_flag & BIT(ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM)) != 0) { 706ccfbb4f5SMukunda, Vijendar valid_irq = true; 70755af49acSDaniel Kurtz snd_pcm_period_elapsed(irq_data->capture_i2sbt_stream); 708ccfbb4f5SMukunda, Vijendar acp_reg_write((intr_flag & 709ccfbb4f5SMukunda, Vijendar BIT(ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM)) << 16, 710ccfbb4f5SMukunda, Vijendar acp_mmio, mmACP_EXTERNAL_INTR_STAT); 711ccfbb4f5SMukunda, Vijendar } 712ccfbb4f5SMukunda, Vijendar 7137c31335aSMaruthi Srinivas Bayyavarapu if (valid_irq) 7147c31335aSMaruthi Srinivas Bayyavarapu return IRQ_HANDLED; 7157c31335aSMaruthi Srinivas Bayyavarapu else 7167c31335aSMaruthi Srinivas Bayyavarapu return IRQ_NONE; 7177c31335aSMaruthi Srinivas Bayyavarapu } 7187c31335aSMaruthi Srinivas Bayyavarapu 7197c31335aSMaruthi Srinivas Bayyavarapu static int acp_dma_open(struct snd_pcm_substream *substream) 7207c31335aSMaruthi Srinivas Bayyavarapu { 721c36d9b3fSMaruthi Srinivas Bayyavarapu u16 bank; 7227c31335aSMaruthi Srinivas Bayyavarapu int ret = 0; 7237c31335aSMaruthi Srinivas Bayyavarapu struct snd_pcm_runtime *runtime = substream->runtime; 7247c31335aSMaruthi Srinivas Bayyavarapu struct snd_soc_pcm_runtime *prtd = substream->private_data; 72513838c11SMukunda, Vijendar struct snd_soc_component *component = snd_soc_rtdcom_lookup(prtd, 72613838c11SMukunda, Vijendar DRV_NAME); 727a1042a42SKuninori Morimoto struct audio_drv_data *intr_data = dev_get_drvdata(component->dev); 7287c31335aSMaruthi Srinivas Bayyavarapu struct audio_substream_data *adata = 7297c31335aSMaruthi Srinivas Bayyavarapu kzalloc(sizeof(struct audio_substream_data), GFP_KERNEL); 73013838c11SMukunda, Vijendar if (!adata) 7317c31335aSMaruthi Srinivas Bayyavarapu return -ENOMEM; 7327c31335aSMaruthi Srinivas Bayyavarapu 7339c7d6fabSVijendar Mukunda if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 7349c7d6fabSVijendar Mukunda switch (intr_data->asic_type) { 7359c7d6fabSVijendar Mukunda case CHIP_STONEY: 7369c7d6fabSVijendar Mukunda runtime->hw = acp_st_pcm_hardware_playback; 7379c7d6fabSVijendar Mukunda break; 7389c7d6fabSVijendar Mukunda default: 7397c31335aSMaruthi Srinivas Bayyavarapu runtime->hw = acp_pcm_hardware_playback; 7409c7d6fabSVijendar Mukunda } 7419c7d6fabSVijendar Mukunda } else { 7429c7d6fabSVijendar Mukunda switch (intr_data->asic_type) { 7439c7d6fabSVijendar Mukunda case CHIP_STONEY: 7449c7d6fabSVijendar Mukunda runtime->hw = acp_st_pcm_hardware_capture; 7459c7d6fabSVijendar Mukunda break; 7469c7d6fabSVijendar Mukunda default: 7477c31335aSMaruthi Srinivas Bayyavarapu runtime->hw = acp_pcm_hardware_capture; 7489c7d6fabSVijendar Mukunda } 7499c7d6fabSVijendar Mukunda } 7507c31335aSMaruthi Srinivas Bayyavarapu 7517c31335aSMaruthi Srinivas Bayyavarapu ret = snd_pcm_hw_constraint_integer(runtime, 7527c31335aSMaruthi Srinivas Bayyavarapu SNDRV_PCM_HW_PARAM_PERIODS); 7537c31335aSMaruthi Srinivas Bayyavarapu if (ret < 0) { 754a1042a42SKuninori Morimoto dev_err(component->dev, "set integer constraint failed\n"); 755cde6bcd5SDan Carpenter kfree(adata); 7567c31335aSMaruthi Srinivas Bayyavarapu return ret; 7577c31335aSMaruthi Srinivas Bayyavarapu } 7587c31335aSMaruthi Srinivas Bayyavarapu 7597c31335aSMaruthi Srinivas Bayyavarapu adata->acp_mmio = intr_data->acp_mmio; 7607c31335aSMaruthi Srinivas Bayyavarapu runtime->private_data = adata; 7617c31335aSMaruthi Srinivas Bayyavarapu 76213838c11SMukunda, Vijendar /* 76313838c11SMukunda, Vijendar * Enable ACP irq, when neither playback or capture streams are 7647c31335aSMaruthi Srinivas Bayyavarapu * active by the time when a new stream is being opened. 7657c31335aSMaruthi Srinivas Bayyavarapu * This enablement is not required for another stream, if current 7667c31335aSMaruthi Srinivas Bayyavarapu * stream is not closed 7677c31335aSMaruthi Srinivas Bayyavarapu */ 768ccfbb4f5SMukunda, Vijendar if (!intr_data->play_i2ssp_stream && !intr_data->capture_i2ssp_stream && 769ccfbb4f5SMukunda, Vijendar !intr_data->play_i2sbt_stream && !intr_data->capture_i2sbt_stream) 7707c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB); 7717c31335aSMaruthi Srinivas Bayyavarapu 772c36d9b3fSMaruthi Srinivas Bayyavarapu if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 77313838c11SMukunda, Vijendar /* 77413838c11SMukunda, Vijendar * For Stoney, Memory gating is disabled,i.e SRAM Banks 775607b39efSVijendar Mukunda * won't be turned off. The default state for SRAM banks is ON. 776607b39efSVijendar Mukunda * Setting SRAM bank state code skipped for STONEY platform. 777607b39efSVijendar Mukunda */ 778607b39efSVijendar Mukunda if (intr_data->asic_type != CHIP_STONEY) { 779c36d9b3fSMaruthi Srinivas Bayyavarapu for (bank = 1; bank <= 4; bank++) 780607b39efSVijendar Mukunda acp_set_sram_bank_state(intr_data->acp_mmio, 781607b39efSVijendar Mukunda bank, true); 782607b39efSVijendar Mukunda } 783c36d9b3fSMaruthi Srinivas Bayyavarapu } else { 784607b39efSVijendar Mukunda if (intr_data->asic_type != CHIP_STONEY) { 785c36d9b3fSMaruthi Srinivas Bayyavarapu for (bank = 5; bank <= 8; bank++) 786607b39efSVijendar Mukunda acp_set_sram_bank_state(intr_data->acp_mmio, 787607b39efSVijendar Mukunda bank, true); 788607b39efSVijendar Mukunda } 789c36d9b3fSMaruthi Srinivas Bayyavarapu } 7907c31335aSMaruthi Srinivas Bayyavarapu 7917c31335aSMaruthi Srinivas Bayyavarapu return 0; 7927c31335aSMaruthi Srinivas Bayyavarapu } 7937c31335aSMaruthi Srinivas Bayyavarapu 7947c31335aSMaruthi Srinivas Bayyavarapu static int acp_dma_hw_params(struct snd_pcm_substream *substream, 7957c31335aSMaruthi Srinivas Bayyavarapu struct snd_pcm_hw_params *params) 7967c31335aSMaruthi Srinivas Bayyavarapu { 7977c31335aSMaruthi Srinivas Bayyavarapu int status; 7987c31335aSMaruthi Srinivas Bayyavarapu uint64_t size; 799a37d48e3SVijendar Mukunda u32 val = 0; 8007c31335aSMaruthi Srinivas Bayyavarapu struct page *pg; 8017c31335aSMaruthi Srinivas Bayyavarapu struct snd_pcm_runtime *runtime; 8027c31335aSMaruthi Srinivas Bayyavarapu struct audio_substream_data *rtd; 803aac89748SVijendar Mukunda struct snd_soc_pcm_runtime *prtd = substream->private_data; 80413838c11SMukunda, Vijendar struct snd_soc_component *component = snd_soc_rtdcom_lookup(prtd, 80513838c11SMukunda, Vijendar DRV_NAME); 806a1042a42SKuninori Morimoto struct audio_drv_data *adata = dev_get_drvdata(component->dev); 807ccfbb4f5SMukunda, Vijendar struct snd_soc_card *card = prtd->card; 808ccfbb4f5SMukunda, Vijendar struct acp_platform_info *pinfo = snd_soc_card_get_drvdata(card); 8097c31335aSMaruthi Srinivas Bayyavarapu 8107c31335aSMaruthi Srinivas Bayyavarapu runtime = substream->runtime; 8117c31335aSMaruthi Srinivas Bayyavarapu rtd = runtime->private_data; 8127c31335aSMaruthi Srinivas Bayyavarapu 8137c31335aSMaruthi Srinivas Bayyavarapu if (WARN_ON(!rtd)) 8147c31335aSMaruthi Srinivas Bayyavarapu return -EINVAL; 8157c31335aSMaruthi Srinivas Bayyavarapu 8162718c89aSAkshu Agrawal if (pinfo) { 817ccfbb4f5SMukunda, Vijendar rtd->i2s_instance = pinfo->i2s_instance; 8182718c89aSAkshu Agrawal rtd->capture_channel = pinfo->capture_channel; 8192718c89aSAkshu Agrawal } 820a37d48e3SVijendar Mukunda if (adata->asic_type == CHIP_STONEY) { 82113838c11SMukunda, Vijendar val = acp_reg_read(adata->acp_mmio, 82213838c11SMukunda, Vijendar mmACP_I2S_16BIT_RESOLUTION_EN); 823ccfbb4f5SMukunda, Vijendar if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 824ccfbb4f5SMukunda, Vijendar switch (rtd->i2s_instance) { 825ccfbb4f5SMukunda, Vijendar case I2S_BT_INSTANCE: 826ccfbb4f5SMukunda, Vijendar val |= ACP_I2S_BT_16BIT_RESOLUTION_EN; 827ccfbb4f5SMukunda, Vijendar break; 828ccfbb4f5SMukunda, Vijendar case I2S_SP_INSTANCE: 829ccfbb4f5SMukunda, Vijendar default: 830a37d48e3SVijendar Mukunda val |= ACP_I2S_SP_16BIT_RESOLUTION_EN; 831ccfbb4f5SMukunda, Vijendar } 832ccfbb4f5SMukunda, Vijendar } else { 833ccfbb4f5SMukunda, Vijendar switch (rtd->i2s_instance) { 834ccfbb4f5SMukunda, Vijendar case I2S_BT_INSTANCE: 835ccfbb4f5SMukunda, Vijendar val |= ACP_I2S_BT_16BIT_RESOLUTION_EN; 836ccfbb4f5SMukunda, Vijendar break; 837ccfbb4f5SMukunda, Vijendar case I2S_SP_INSTANCE: 838ccfbb4f5SMukunda, Vijendar default: 839a37d48e3SVijendar Mukunda val |= ACP_I2S_MIC_16BIT_RESOLUTION_EN; 840ccfbb4f5SMukunda, Vijendar } 841ccfbb4f5SMukunda, Vijendar } 84213838c11SMukunda, Vijendar acp_reg_write(val, adata->acp_mmio, 84313838c11SMukunda, Vijendar mmACP_I2S_16BIT_RESOLUTION_EN); 844a37d48e3SVijendar Mukunda } 8458769bb55SVijendar Mukunda 8468769bb55SVijendar Mukunda if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 847ccfbb4f5SMukunda, Vijendar switch (rtd->i2s_instance) { 848ccfbb4f5SMukunda, Vijendar case I2S_BT_INSTANCE: 849ccfbb4f5SMukunda, Vijendar rtd->pte_offset = ACP_ST_BT_PLAYBACK_PTE_OFFSET; 850ccfbb4f5SMukunda, Vijendar rtd->ch1 = SYSRAM_TO_ACP_BT_INSTANCE_CH_NUM; 851ccfbb4f5SMukunda, Vijendar rtd->ch2 = ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM; 852ccfbb4f5SMukunda, Vijendar rtd->sram_bank = ACP_SRAM_BANK_3_ADDRESS; 853ccfbb4f5SMukunda, Vijendar rtd->destination = TO_BLUETOOTH; 854ccfbb4f5SMukunda, Vijendar rtd->dma_dscr_idx_1 = PLAYBACK_START_DMA_DESCR_CH8; 855ccfbb4f5SMukunda, Vijendar rtd->dma_dscr_idx_2 = PLAYBACK_START_DMA_DESCR_CH9; 856ccfbb4f5SMukunda, Vijendar rtd->byte_cnt_high_reg_offset = 857ccfbb4f5SMukunda, Vijendar mmACP_I2S_BT_TRANSMIT_BYTE_CNT_HIGH; 858ccfbb4f5SMukunda, Vijendar rtd->byte_cnt_low_reg_offset = 859ccfbb4f5SMukunda, Vijendar mmACP_I2S_BT_TRANSMIT_BYTE_CNT_LOW; 860ccfbb4f5SMukunda, Vijendar adata->play_i2sbt_stream = substream; 861ccfbb4f5SMukunda, Vijendar break; 862ccfbb4f5SMukunda, Vijendar case I2S_SP_INSTANCE: 863ccfbb4f5SMukunda, Vijendar default: 864e188c525SMukunda, Vijendar switch (adata->asic_type) { 865e188c525SMukunda, Vijendar case CHIP_STONEY: 866e188c525SMukunda, Vijendar rtd->pte_offset = ACP_ST_PLAYBACK_PTE_OFFSET; 867e188c525SMukunda, Vijendar break; 868e188c525SMukunda, Vijendar default: 869e188c525SMukunda, Vijendar rtd->pte_offset = ACP_PLAYBACK_PTE_OFFSET; 870e188c525SMukunda, Vijendar } 8718769bb55SVijendar Mukunda rtd->ch1 = SYSRAM_TO_ACP_CH_NUM; 8728769bb55SVijendar Mukunda rtd->ch2 = ACP_TO_I2S_DMA_CH_NUM; 87318e8a40dSMukunda, Vijendar rtd->sram_bank = ACP_SRAM_BANK_1_ADDRESS; 8748769bb55SVijendar Mukunda rtd->destination = TO_ACP_I2S_1; 8758769bb55SVijendar Mukunda rtd->dma_dscr_idx_1 = PLAYBACK_START_DMA_DESCR_CH12; 8768769bb55SVijendar Mukunda rtd->dma_dscr_idx_2 = PLAYBACK_START_DMA_DESCR_CH13; 8777f004847SVijendar Mukunda rtd->byte_cnt_high_reg_offset = 8787f004847SVijendar Mukunda mmACP_I2S_TRANSMIT_BYTE_CNT_HIGH; 879ccfbb4f5SMukunda, Vijendar rtd->byte_cnt_low_reg_offset = 880ccfbb4f5SMukunda, Vijendar mmACP_I2S_TRANSMIT_BYTE_CNT_LOW; 881ccfbb4f5SMukunda, Vijendar adata->play_i2ssp_stream = substream; 882ccfbb4f5SMukunda, Vijendar } 8838769bb55SVijendar Mukunda } else { 884ccfbb4f5SMukunda, Vijendar switch (rtd->i2s_instance) { 885ccfbb4f5SMukunda, Vijendar case I2S_BT_INSTANCE: 886ccfbb4f5SMukunda, Vijendar rtd->pte_offset = ACP_ST_BT_CAPTURE_PTE_OFFSET; 88755af49acSDaniel Kurtz rtd->ch1 = I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM; 88855af49acSDaniel Kurtz rtd->ch2 = ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM; 889ccfbb4f5SMukunda, Vijendar rtd->sram_bank = ACP_SRAM_BANK_4_ADDRESS; 890ccfbb4f5SMukunda, Vijendar rtd->destination = FROM_BLUETOOTH; 891ccfbb4f5SMukunda, Vijendar rtd->dma_dscr_idx_1 = CAPTURE_START_DMA_DESCR_CH10; 892ccfbb4f5SMukunda, Vijendar rtd->dma_dscr_idx_2 = CAPTURE_START_DMA_DESCR_CH11; 893ccfbb4f5SMukunda, Vijendar rtd->byte_cnt_high_reg_offset = 894ccfbb4f5SMukunda, Vijendar mmACP_I2S_BT_RECEIVE_BYTE_CNT_HIGH; 895ccfbb4f5SMukunda, Vijendar rtd->byte_cnt_low_reg_offset = 896ccfbb4f5SMukunda, Vijendar mmACP_I2S_BT_RECEIVE_BYTE_CNT_LOW; 897ccfbb4f5SMukunda, Vijendar adata->capture_i2sbt_stream = substream; 898ccfbb4f5SMukunda, Vijendar break; 899ccfbb4f5SMukunda, Vijendar case I2S_SP_INSTANCE: 900ccfbb4f5SMukunda, Vijendar default: 901ccfbb4f5SMukunda, Vijendar rtd->pte_offset = ACP_CAPTURE_PTE_OFFSET; 90255af49acSDaniel Kurtz rtd->ch1 = I2S_TO_ACP_DMA_CH_NUM; 90355af49acSDaniel Kurtz rtd->ch2 = ACP_TO_SYSRAM_CH_NUM; 904e188c525SMukunda, Vijendar switch (adata->asic_type) { 905e188c525SMukunda, Vijendar case CHIP_STONEY: 906e188c525SMukunda, Vijendar rtd->pte_offset = ACP_ST_CAPTURE_PTE_OFFSET; 90718e8a40dSMukunda, Vijendar rtd->sram_bank = ACP_SRAM_BANK_2_ADDRESS; 908e188c525SMukunda, Vijendar break; 909e188c525SMukunda, Vijendar default: 910e188c525SMukunda, Vijendar rtd->pte_offset = ACP_CAPTURE_PTE_OFFSET; 91118e8a40dSMukunda, Vijendar rtd->sram_bank = ACP_SRAM_BANK_5_ADDRESS; 912e188c525SMukunda, Vijendar } 9138769bb55SVijendar Mukunda rtd->destination = FROM_ACP_I2S_1; 9148769bb55SVijendar Mukunda rtd->dma_dscr_idx_1 = CAPTURE_START_DMA_DESCR_CH14; 9158769bb55SVijendar Mukunda rtd->dma_dscr_idx_2 = CAPTURE_START_DMA_DESCR_CH15; 9167f004847SVijendar Mukunda rtd->byte_cnt_high_reg_offset = 9177f004847SVijendar Mukunda mmACP_I2S_RECEIVED_BYTE_CNT_HIGH; 918ccfbb4f5SMukunda, Vijendar rtd->byte_cnt_low_reg_offset = 919ccfbb4f5SMukunda, Vijendar mmACP_I2S_RECEIVED_BYTE_CNT_LOW; 920ccfbb4f5SMukunda, Vijendar adata->capture_i2ssp_stream = substream; 921ccfbb4f5SMukunda, Vijendar } 9228769bb55SVijendar Mukunda } 9238769bb55SVijendar Mukunda 9247c31335aSMaruthi Srinivas Bayyavarapu size = params_buffer_bytes(params); 9257c31335aSMaruthi Srinivas Bayyavarapu status = snd_pcm_lib_malloc_pages(substream, size); 9267c31335aSMaruthi Srinivas Bayyavarapu if (status < 0) 9277c31335aSMaruthi Srinivas Bayyavarapu return status; 9287c31335aSMaruthi Srinivas Bayyavarapu 9297c31335aSMaruthi Srinivas Bayyavarapu memset(substream->runtime->dma_area, 0, params_buffer_bytes(params)); 9307c31335aSMaruthi Srinivas Bayyavarapu pg = virt_to_page(substream->dma_buffer.area); 9317c31335aSMaruthi Srinivas Bayyavarapu 93213838c11SMukunda, Vijendar if (pg) { 933c36d9b3fSMaruthi Srinivas Bayyavarapu acp_set_sram_bank_state(rtd->acp_mmio, 0, true); 9347c31335aSMaruthi Srinivas Bayyavarapu /* Save for runtime private data */ 9357c31335aSMaruthi Srinivas Bayyavarapu rtd->pg = pg; 9367c31335aSMaruthi Srinivas Bayyavarapu rtd->order = get_order(size); 9377c31335aSMaruthi Srinivas Bayyavarapu 9387c31335aSMaruthi Srinivas Bayyavarapu /* Fill the page table entries in ACP SRAM */ 9397c31335aSMaruthi Srinivas Bayyavarapu rtd->pg = pg; 9407c31335aSMaruthi Srinivas Bayyavarapu rtd->size = size; 9417c31335aSMaruthi Srinivas Bayyavarapu rtd->num_of_pages = PAGE_ALIGN(size) >> PAGE_SHIFT; 9427c31335aSMaruthi Srinivas Bayyavarapu rtd->direction = substream->stream; 9437c31335aSMaruthi Srinivas Bayyavarapu 944aac89748SVijendar Mukunda config_acp_dma(rtd->acp_mmio, rtd, adata->asic_type); 9457c31335aSMaruthi Srinivas Bayyavarapu status = 0; 9467c31335aSMaruthi Srinivas Bayyavarapu } else { 9477c31335aSMaruthi Srinivas Bayyavarapu status = -ENOMEM; 9487c31335aSMaruthi Srinivas Bayyavarapu } 9497c31335aSMaruthi Srinivas Bayyavarapu return status; 9507c31335aSMaruthi Srinivas Bayyavarapu } 9517c31335aSMaruthi Srinivas Bayyavarapu 9527c31335aSMaruthi Srinivas Bayyavarapu static int acp_dma_hw_free(struct snd_pcm_substream *substream) 9537c31335aSMaruthi Srinivas Bayyavarapu { 9547c31335aSMaruthi Srinivas Bayyavarapu return snd_pcm_lib_free_pages(substream); 9557c31335aSMaruthi Srinivas Bayyavarapu } 9567c31335aSMaruthi Srinivas Bayyavarapu 9577f004847SVijendar Mukunda static u64 acp_get_byte_count(struct audio_substream_data *rtd) 95861add814SVijendar Mukunda { 9597f004847SVijendar Mukunda union acp_dma_count byte_count; 96061add814SVijendar Mukunda 9617f004847SVijendar Mukunda byte_count.bcount.high = acp_reg_read(rtd->acp_mmio, 9627f004847SVijendar Mukunda rtd->byte_cnt_high_reg_offset); 9637f004847SVijendar Mukunda byte_count.bcount.low = acp_reg_read(rtd->acp_mmio, 9647f004847SVijendar Mukunda rtd->byte_cnt_low_reg_offset); 9657f004847SVijendar Mukunda return byte_count.bytescount; 96661add814SVijendar Mukunda } 96761add814SVijendar Mukunda 9687c31335aSMaruthi Srinivas Bayyavarapu static snd_pcm_uframes_t acp_dma_pointer(struct snd_pcm_substream *substream) 9697c31335aSMaruthi Srinivas Bayyavarapu { 97061add814SVijendar Mukunda u32 buffersize; 9717c31335aSMaruthi Srinivas Bayyavarapu u32 pos = 0; 97261add814SVijendar Mukunda u64 bytescount = 0; 9737c31335aSMaruthi Srinivas Bayyavarapu 9747c31335aSMaruthi Srinivas Bayyavarapu struct snd_pcm_runtime *runtime = substream->runtime; 9757c31335aSMaruthi Srinivas Bayyavarapu struct audio_substream_data *rtd = runtime->private_data; 9767c31335aSMaruthi Srinivas Bayyavarapu 9777afa535eSMukunda, Vijendar if (!rtd) 9787afa535eSMukunda, Vijendar return -EINVAL; 9797afa535eSMukunda, Vijendar 98061add814SVijendar Mukunda buffersize = frames_to_bytes(runtime, runtime->buffer_size); 9817f004847SVijendar Mukunda bytescount = acp_get_byte_count(rtd); 98261add814SVijendar Mukunda 9839af8937eSVijendar Mukunda bytescount -= rtd->bytescount; 9847db08b2cSGuenter Roeck pos = do_div(bytescount, buffersize); 9857c31335aSMaruthi Srinivas Bayyavarapu return bytes_to_frames(runtime, pos); 9867c31335aSMaruthi Srinivas Bayyavarapu } 9877c31335aSMaruthi Srinivas Bayyavarapu 9887c31335aSMaruthi Srinivas Bayyavarapu static int acp_dma_mmap(struct snd_pcm_substream *substream, 9897c31335aSMaruthi Srinivas Bayyavarapu struct vm_area_struct *vma) 9907c31335aSMaruthi Srinivas Bayyavarapu { 9917c31335aSMaruthi Srinivas Bayyavarapu return snd_pcm_lib_default_mmap(substream, vma); 9927c31335aSMaruthi Srinivas Bayyavarapu } 9937c31335aSMaruthi Srinivas Bayyavarapu 9947c31335aSMaruthi Srinivas Bayyavarapu static int acp_dma_prepare(struct snd_pcm_substream *substream) 9957c31335aSMaruthi Srinivas Bayyavarapu { 9967c31335aSMaruthi Srinivas Bayyavarapu struct snd_pcm_runtime *runtime = substream->runtime; 9977c31335aSMaruthi Srinivas Bayyavarapu struct audio_substream_data *rtd = runtime->private_data; 9987c31335aSMaruthi Srinivas Bayyavarapu 9997afa535eSMukunda, Vijendar if (!rtd) 10007afa535eSMukunda, Vijendar return -EINVAL; 10018769bb55SVijendar Mukunda 10028769bb55SVijendar Mukunda config_acp_dma_channel(rtd->acp_mmio, 10038769bb55SVijendar Mukunda rtd->ch1, 10048769bb55SVijendar Mukunda rtd->dma_dscr_idx_1, 10057c31335aSMaruthi Srinivas Bayyavarapu NUM_DSCRS_PER_CHANNEL, 0); 10068769bb55SVijendar Mukunda config_acp_dma_channel(rtd->acp_mmio, 10078769bb55SVijendar Mukunda rtd->ch2, 10088769bb55SVijendar Mukunda rtd->dma_dscr_idx_2, 10097c31335aSMaruthi Srinivas Bayyavarapu NUM_DSCRS_PER_CHANNEL, 0); 10107c31335aSMaruthi Srinivas Bayyavarapu return 0; 10117c31335aSMaruthi Srinivas Bayyavarapu } 10127c31335aSMaruthi Srinivas Bayyavarapu 10137c31335aSMaruthi Srinivas Bayyavarapu static int acp_dma_trigger(struct snd_pcm_substream *substream, int cmd) 10147c31335aSMaruthi Srinivas Bayyavarapu { 10157c31335aSMaruthi Srinivas Bayyavarapu int ret; 10167c31335aSMaruthi Srinivas Bayyavarapu 10177c31335aSMaruthi Srinivas Bayyavarapu struct snd_pcm_runtime *runtime = substream->runtime; 10187c31335aSMaruthi Srinivas Bayyavarapu struct audio_substream_data *rtd = runtime->private_data; 10197c31335aSMaruthi Srinivas Bayyavarapu 10207c31335aSMaruthi Srinivas Bayyavarapu if (!rtd) 10217c31335aSMaruthi Srinivas Bayyavarapu return -EINVAL; 10227c31335aSMaruthi Srinivas Bayyavarapu switch (cmd) { 10237c31335aSMaruthi Srinivas Bayyavarapu case SNDRV_PCM_TRIGGER_START: 10247c31335aSMaruthi Srinivas Bayyavarapu case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 10257c31335aSMaruthi Srinivas Bayyavarapu case SNDRV_PCM_TRIGGER_RESUME: 1026*1a337a1eSDaniel Kurtz rtd->bytescount = acp_get_byte_count(rtd); 10277c31335aSMaruthi Srinivas Bayyavarapu if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 10286b116dfbSAgrawal, Akshu acp_dma_start(rtd->acp_mmio, rtd->ch1); 10296b116dfbSAgrawal, Akshu acp_dma_start(rtd->acp_mmio, rtd->ch2); 10306b116dfbSAgrawal, Akshu } else { 10312718c89aSAkshu Agrawal if (rtd->capture_channel == CAP_CHANNEL0) { 10322718c89aSAkshu Agrawal acp_dma_cap_channel_disable(rtd->acp_mmio, 10332718c89aSAkshu Agrawal CAP_CHANNEL1); 10342718c89aSAkshu Agrawal acp_dma_cap_channel_enable(rtd->acp_mmio, 10352718c89aSAkshu Agrawal CAP_CHANNEL0); 10362718c89aSAkshu Agrawal } 10372718c89aSAkshu Agrawal if (rtd->capture_channel == CAP_CHANNEL1) { 10382718c89aSAkshu Agrawal acp_dma_cap_channel_disable(rtd->acp_mmio, 10392718c89aSAkshu Agrawal CAP_CHANNEL0); 10402718c89aSAkshu Agrawal acp_dma_cap_channel_enable(rtd->acp_mmio, 10412718c89aSAkshu Agrawal CAP_CHANNEL1); 10422718c89aSAkshu Agrawal } 10436b116dfbSAgrawal, Akshu acp_dma_start(rtd->acp_mmio, rtd->ch2); 10446b116dfbSAgrawal, Akshu acp_dma_start(rtd->acp_mmio, rtd->ch1); 10457c31335aSMaruthi Srinivas Bayyavarapu } 10467c31335aSMaruthi Srinivas Bayyavarapu ret = 0; 10477c31335aSMaruthi Srinivas Bayyavarapu break; 10487c31335aSMaruthi Srinivas Bayyavarapu case SNDRV_PCM_TRIGGER_STOP: 10497c31335aSMaruthi Srinivas Bayyavarapu case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 10507c31335aSMaruthi Srinivas Bayyavarapu case SNDRV_PCM_TRIGGER_SUSPEND: 10518769bb55SVijendar Mukunda acp_dma_stop(rtd->acp_mmio, rtd->ch2); 10528769bb55SVijendar Mukunda ret = acp_dma_stop(rtd->acp_mmio, rtd->ch1); 10537c31335aSMaruthi Srinivas Bayyavarapu break; 10547c31335aSMaruthi Srinivas Bayyavarapu default: 10557c31335aSMaruthi Srinivas Bayyavarapu ret = -EINVAL; 10567c31335aSMaruthi Srinivas Bayyavarapu } 10577c31335aSMaruthi Srinivas Bayyavarapu return ret; 10587c31335aSMaruthi Srinivas Bayyavarapu } 10597c31335aSMaruthi Srinivas Bayyavarapu 10607c31335aSMaruthi Srinivas Bayyavarapu static int acp_dma_new(struct snd_soc_pcm_runtime *rtd) 10617c31335aSMaruthi Srinivas Bayyavarapu { 10629c7d6fabSVijendar Mukunda int ret; 106313838c11SMukunda, Vijendar struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, 106413838c11SMukunda, Vijendar DRV_NAME); 1065a1042a42SKuninori Morimoto struct audio_drv_data *adata = dev_get_drvdata(component->dev); 10669c7d6fabSVijendar Mukunda 10679c7d6fabSVijendar Mukunda switch (adata->asic_type) { 10689c7d6fabSVijendar Mukunda case CHIP_STONEY: 10699c7d6fabSVijendar Mukunda ret = snd_pcm_lib_preallocate_pages_for_all(rtd->pcm, 10709c7d6fabSVijendar Mukunda SNDRV_DMA_TYPE_DEV, 10719c7d6fabSVijendar Mukunda NULL, ST_MIN_BUFFER, 10729c7d6fabSVijendar Mukunda ST_MAX_BUFFER); 10739c7d6fabSVijendar Mukunda break; 10749c7d6fabSVijendar Mukunda default: 10759c7d6fabSVijendar Mukunda ret = snd_pcm_lib_preallocate_pages_for_all(rtd->pcm, 10767c31335aSMaruthi Srinivas Bayyavarapu SNDRV_DMA_TYPE_DEV, 10777c31335aSMaruthi Srinivas Bayyavarapu NULL, MIN_BUFFER, 10787c31335aSMaruthi Srinivas Bayyavarapu MAX_BUFFER); 10799c7d6fabSVijendar Mukunda break; 10809c7d6fabSVijendar Mukunda } 10819c7d6fabSVijendar Mukunda if (ret < 0) 1082a1042a42SKuninori Morimoto dev_err(component->dev, 10839e6a469eSColin Ian King "buffer preallocation failure error:%d\n", ret); 10849c7d6fabSVijendar Mukunda return ret; 10857c31335aSMaruthi Srinivas Bayyavarapu } 10867c31335aSMaruthi Srinivas Bayyavarapu 10877c31335aSMaruthi Srinivas Bayyavarapu static int acp_dma_close(struct snd_pcm_substream *substream) 10887c31335aSMaruthi Srinivas Bayyavarapu { 1089c36d9b3fSMaruthi Srinivas Bayyavarapu u16 bank; 10907c31335aSMaruthi Srinivas Bayyavarapu struct snd_pcm_runtime *runtime = substream->runtime; 10917c31335aSMaruthi Srinivas Bayyavarapu struct audio_substream_data *rtd = runtime->private_data; 10927c31335aSMaruthi Srinivas Bayyavarapu struct snd_soc_pcm_runtime *prtd = substream->private_data; 109313838c11SMukunda, Vijendar struct snd_soc_component *component = snd_soc_rtdcom_lookup(prtd, 109413838c11SMukunda, Vijendar DRV_NAME); 1095a1042a42SKuninori Morimoto struct audio_drv_data *adata = dev_get_drvdata(component->dev); 10967c31335aSMaruthi Srinivas Bayyavarapu 1097c36d9b3fSMaruthi Srinivas Bayyavarapu if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 1098ccfbb4f5SMukunda, Vijendar switch (rtd->i2s_instance) { 1099ccfbb4f5SMukunda, Vijendar case I2S_BT_INSTANCE: 1100ccfbb4f5SMukunda, Vijendar adata->play_i2sbt_stream = NULL; 1101ccfbb4f5SMukunda, Vijendar break; 1102ccfbb4f5SMukunda, Vijendar case I2S_SP_INSTANCE: 1103ccfbb4f5SMukunda, Vijendar default: 1104e21358c4SMukunda, Vijendar adata->play_i2ssp_stream = NULL; 110513838c11SMukunda, Vijendar /* 110613838c11SMukunda, Vijendar * For Stoney, Memory gating is disabled,i.e SRAM Banks 1107ccfbb4f5SMukunda, Vijendar * won't be turned off. The default state for SRAM banks 1108ccfbb4f5SMukunda, Vijendar * is ON.Setting SRAM bank state code skipped for STONEY 1109ccfbb4f5SMukunda, Vijendar * platform. Added condition checks for Carrizo platform 1110ccfbb4f5SMukunda, Vijendar * only. 1111607b39efSVijendar Mukunda */ 1112607b39efSVijendar Mukunda if (adata->asic_type != CHIP_STONEY) { 1113c36d9b3fSMaruthi Srinivas Bayyavarapu for (bank = 1; bank <= 4; bank++) 1114ccfbb4f5SMukunda, Vijendar acp_set_sram_bank_state(adata->acp_mmio, 1115ccfbb4f5SMukunda, Vijendar bank, false); 1116ccfbb4f5SMukunda, Vijendar } 1117607b39efSVijendar Mukunda } 1118c36d9b3fSMaruthi Srinivas Bayyavarapu } else { 1119ccfbb4f5SMukunda, Vijendar switch (rtd->i2s_instance) { 1120ccfbb4f5SMukunda, Vijendar case I2S_BT_INSTANCE: 1121ccfbb4f5SMukunda, Vijendar adata->capture_i2sbt_stream = NULL; 1122ccfbb4f5SMukunda, Vijendar break; 1123ccfbb4f5SMukunda, Vijendar case I2S_SP_INSTANCE: 1124ccfbb4f5SMukunda, Vijendar default: 1125e21358c4SMukunda, Vijendar adata->capture_i2ssp_stream = NULL; 1126607b39efSVijendar Mukunda if (adata->asic_type != CHIP_STONEY) { 1127c36d9b3fSMaruthi Srinivas Bayyavarapu for (bank = 5; bank <= 8; bank++) 1128ccfbb4f5SMukunda, Vijendar acp_set_sram_bank_state(adata->acp_mmio, 1129ccfbb4f5SMukunda, Vijendar bank, false); 1130ccfbb4f5SMukunda, Vijendar } 1131c36d9b3fSMaruthi Srinivas Bayyavarapu } 1132607b39efSVijendar Mukunda } 11337c31335aSMaruthi Srinivas Bayyavarapu 113413838c11SMukunda, Vijendar /* 113513838c11SMukunda, Vijendar * Disable ACP irq, when the current stream is being closed and 11367c31335aSMaruthi Srinivas Bayyavarapu * another stream is also not active. 11377c31335aSMaruthi Srinivas Bayyavarapu */ 1138ccfbb4f5SMukunda, Vijendar if (!adata->play_i2ssp_stream && !adata->capture_i2ssp_stream && 1139ccfbb4f5SMukunda, Vijendar !adata->play_i2sbt_stream && !adata->capture_i2sbt_stream) 11407c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(0, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB); 1141cac6f597SMukunda, Vijendar kfree(rtd); 11427c31335aSMaruthi Srinivas Bayyavarapu return 0; 11437c31335aSMaruthi Srinivas Bayyavarapu } 11447c31335aSMaruthi Srinivas Bayyavarapu 1145115c7254SJulia Lawall static const struct snd_pcm_ops acp_dma_ops = { 11467c31335aSMaruthi Srinivas Bayyavarapu .open = acp_dma_open, 11477c31335aSMaruthi Srinivas Bayyavarapu .close = acp_dma_close, 11487c31335aSMaruthi Srinivas Bayyavarapu .ioctl = snd_pcm_lib_ioctl, 11497c31335aSMaruthi Srinivas Bayyavarapu .hw_params = acp_dma_hw_params, 11507c31335aSMaruthi Srinivas Bayyavarapu .hw_free = acp_dma_hw_free, 11517c31335aSMaruthi Srinivas Bayyavarapu .trigger = acp_dma_trigger, 11527c31335aSMaruthi Srinivas Bayyavarapu .pointer = acp_dma_pointer, 11537c31335aSMaruthi Srinivas Bayyavarapu .mmap = acp_dma_mmap, 11547c31335aSMaruthi Srinivas Bayyavarapu .prepare = acp_dma_prepare, 11557c31335aSMaruthi Srinivas Bayyavarapu }; 11567c31335aSMaruthi Srinivas Bayyavarapu 115713838c11SMukunda, Vijendar static const struct snd_soc_component_driver acp_asoc_platform = { 1158a1042a42SKuninori Morimoto .name = DRV_NAME, 11597c31335aSMaruthi Srinivas Bayyavarapu .ops = &acp_dma_ops, 11607c31335aSMaruthi Srinivas Bayyavarapu .pcm_new = acp_dma_new, 11617c31335aSMaruthi Srinivas Bayyavarapu }; 11627c31335aSMaruthi Srinivas Bayyavarapu 11637c31335aSMaruthi Srinivas Bayyavarapu static int acp_audio_probe(struct platform_device *pdev) 11647c31335aSMaruthi Srinivas Bayyavarapu { 11657c31335aSMaruthi Srinivas Bayyavarapu int status; 11667c31335aSMaruthi Srinivas Bayyavarapu struct audio_drv_data *audio_drv_data; 11677c31335aSMaruthi Srinivas Bayyavarapu struct resource *res; 1168a1b16aaaSVijendar Mukunda const u32 *pdata = pdev->dev.platform_data; 11697c31335aSMaruthi Srinivas Bayyavarapu 1170fdaa4511SGuenter Roeck if (!pdata) { 1171fdaa4511SGuenter Roeck dev_err(&pdev->dev, "Missing platform data\n"); 1172fdaa4511SGuenter Roeck return -ENODEV; 1173fdaa4511SGuenter Roeck } 1174fdaa4511SGuenter Roeck 11757c31335aSMaruthi Srinivas Bayyavarapu audio_drv_data = devm_kzalloc(&pdev->dev, sizeof(struct audio_drv_data), 11767c31335aSMaruthi Srinivas Bayyavarapu GFP_KERNEL); 117713838c11SMukunda, Vijendar if (!audio_drv_data) 11787c31335aSMaruthi Srinivas Bayyavarapu return -ENOMEM; 11797c31335aSMaruthi Srinivas Bayyavarapu 11807c31335aSMaruthi Srinivas Bayyavarapu res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 11817c31335aSMaruthi Srinivas Bayyavarapu audio_drv_data->acp_mmio = devm_ioremap_resource(&pdev->dev, res); 1182fdaa4511SGuenter Roeck if (IS_ERR(audio_drv_data->acp_mmio)) 1183fdaa4511SGuenter Roeck return PTR_ERR(audio_drv_data->acp_mmio); 11847c31335aSMaruthi Srinivas Bayyavarapu 118513838c11SMukunda, Vijendar /* 118613838c11SMukunda, Vijendar * The following members gets populated in device 'open' 11877c31335aSMaruthi Srinivas Bayyavarapu * function. Till then interrupts are disabled in 'acp_init' 11887c31335aSMaruthi Srinivas Bayyavarapu * and device doesn't generate any interrupts. 11897c31335aSMaruthi Srinivas Bayyavarapu */ 11907c31335aSMaruthi Srinivas Bayyavarapu 1191e21358c4SMukunda, Vijendar audio_drv_data->play_i2ssp_stream = NULL; 1192e21358c4SMukunda, Vijendar audio_drv_data->capture_i2ssp_stream = NULL; 1193ccfbb4f5SMukunda, Vijendar audio_drv_data->play_i2sbt_stream = NULL; 1194ccfbb4f5SMukunda, Vijendar audio_drv_data->capture_i2sbt_stream = NULL; 1195e21358c4SMukunda, Vijendar 1196a1b16aaaSVijendar Mukunda audio_drv_data->asic_type = *pdata; 11977c31335aSMaruthi Srinivas Bayyavarapu 11987c31335aSMaruthi Srinivas Bayyavarapu res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 11997c31335aSMaruthi Srinivas Bayyavarapu if (!res) { 12007c31335aSMaruthi Srinivas Bayyavarapu dev_err(&pdev->dev, "IORESOURCE_IRQ FAILED\n"); 12017c31335aSMaruthi Srinivas Bayyavarapu return -ENODEV; 12027c31335aSMaruthi Srinivas Bayyavarapu } 12037c31335aSMaruthi Srinivas Bayyavarapu 12047c31335aSMaruthi Srinivas Bayyavarapu status = devm_request_irq(&pdev->dev, res->start, dma_irq_handler, 12057c31335aSMaruthi Srinivas Bayyavarapu 0, "ACP_IRQ", &pdev->dev); 12067c31335aSMaruthi Srinivas Bayyavarapu if (status) { 12077c31335aSMaruthi Srinivas Bayyavarapu dev_err(&pdev->dev, "ACP IRQ request failed\n"); 12087c31335aSMaruthi Srinivas Bayyavarapu return status; 12097c31335aSMaruthi Srinivas Bayyavarapu } 12107c31335aSMaruthi Srinivas Bayyavarapu 12117c31335aSMaruthi Srinivas Bayyavarapu dev_set_drvdata(&pdev->dev, audio_drv_data); 12127c31335aSMaruthi Srinivas Bayyavarapu 12137c31335aSMaruthi Srinivas Bayyavarapu /* Initialize the ACP */ 12147afa535eSMukunda, Vijendar status = acp_init(audio_drv_data->acp_mmio, audio_drv_data->asic_type); 12157afa535eSMukunda, Vijendar if (status) { 12167afa535eSMukunda, Vijendar dev_err(&pdev->dev, "ACP Init failed status:%d\n", status); 12177afa535eSMukunda, Vijendar return status; 12187afa535eSMukunda, Vijendar } 12197c31335aSMaruthi Srinivas Bayyavarapu 1220a1042a42SKuninori Morimoto status = devm_snd_soc_register_component(&pdev->dev, 1221a1042a42SKuninori Morimoto &acp_asoc_platform, NULL, 0); 12227c31335aSMaruthi Srinivas Bayyavarapu if (status != 0) { 12237c31335aSMaruthi Srinivas Bayyavarapu dev_err(&pdev->dev, "Fail to register ALSA platform device\n"); 12247c31335aSMaruthi Srinivas Bayyavarapu return status; 12257c31335aSMaruthi Srinivas Bayyavarapu } 12267c31335aSMaruthi Srinivas Bayyavarapu 12271927da93SMaruthi Srinivas Bayyavarapu pm_runtime_set_autosuspend_delay(&pdev->dev, 10000); 12281927da93SMaruthi Srinivas Bayyavarapu pm_runtime_use_autosuspend(&pdev->dev); 12291927da93SMaruthi Srinivas Bayyavarapu pm_runtime_enable(&pdev->dev); 12301927da93SMaruthi Srinivas Bayyavarapu 12317c31335aSMaruthi Srinivas Bayyavarapu return status; 12327c31335aSMaruthi Srinivas Bayyavarapu } 12337c31335aSMaruthi Srinivas Bayyavarapu 12347c31335aSMaruthi Srinivas Bayyavarapu static int acp_audio_remove(struct platform_device *pdev) 12357c31335aSMaruthi Srinivas Bayyavarapu { 12367afa535eSMukunda, Vijendar int status; 12377c31335aSMaruthi Srinivas Bayyavarapu struct audio_drv_data *adata = dev_get_drvdata(&pdev->dev); 12387c31335aSMaruthi Srinivas Bayyavarapu 12397afa535eSMukunda, Vijendar status = acp_deinit(adata->acp_mmio); 12407afa535eSMukunda, Vijendar if (status) 12417afa535eSMukunda, Vijendar dev_err(&pdev->dev, "ACP Deinit failed status:%d\n", status); 12421927da93SMaruthi Srinivas Bayyavarapu pm_runtime_disable(&pdev->dev); 12437c31335aSMaruthi Srinivas Bayyavarapu 12447c31335aSMaruthi Srinivas Bayyavarapu return 0; 12457c31335aSMaruthi Srinivas Bayyavarapu } 12467c31335aSMaruthi Srinivas Bayyavarapu 12471927da93SMaruthi Srinivas Bayyavarapu static int acp_pcm_resume(struct device *dev) 12481927da93SMaruthi Srinivas Bayyavarapu { 1249c36d9b3fSMaruthi Srinivas Bayyavarapu u16 bank; 12507afa535eSMukunda, Vijendar int status; 1251ccfbb4f5SMukunda, Vijendar struct audio_substream_data *rtd; 12521927da93SMaruthi Srinivas Bayyavarapu struct audio_drv_data *adata = dev_get_drvdata(dev); 12531927da93SMaruthi Srinivas Bayyavarapu 12547afa535eSMukunda, Vijendar status = acp_init(adata->acp_mmio, adata->asic_type); 12557afa535eSMukunda, Vijendar if (status) { 12567afa535eSMukunda, Vijendar dev_err(dev, "ACP Init failed status:%d\n", status); 12577afa535eSMukunda, Vijendar return status; 12587afa535eSMukunda, Vijendar } 12591927da93SMaruthi Srinivas Bayyavarapu 1260e21358c4SMukunda, Vijendar if (adata->play_i2ssp_stream && adata->play_i2ssp_stream->runtime) { 126113838c11SMukunda, Vijendar /* 126213838c11SMukunda, Vijendar * For Stoney, Memory gating is disabled,i.e SRAM Banks 1263607b39efSVijendar Mukunda * won't be turned off. The default state for SRAM banks is ON. 1264607b39efSVijendar Mukunda * Setting SRAM bank state code skipped for STONEY platform. 1265607b39efSVijendar Mukunda */ 1266607b39efSVijendar Mukunda if (adata->asic_type != CHIP_STONEY) { 1267c36d9b3fSMaruthi Srinivas Bayyavarapu for (bank = 1; bank <= 4; bank++) 1268c36d9b3fSMaruthi Srinivas Bayyavarapu acp_set_sram_bank_state(adata->acp_mmio, bank, 1269c36d9b3fSMaruthi Srinivas Bayyavarapu true); 1270607b39efSVijendar Mukunda } 1271ccfbb4f5SMukunda, Vijendar rtd = adata->play_i2ssp_stream->runtime->private_data; 1272ccfbb4f5SMukunda, Vijendar config_acp_dma(adata->acp_mmio, rtd, adata->asic_type); 1273c36d9b3fSMaruthi Srinivas Bayyavarapu } 127413838c11SMukunda, Vijendar if (adata->capture_i2ssp_stream && 127513838c11SMukunda, Vijendar adata->capture_i2ssp_stream->runtime) { 1276607b39efSVijendar Mukunda if (adata->asic_type != CHIP_STONEY) { 1277c36d9b3fSMaruthi Srinivas Bayyavarapu for (bank = 5; bank <= 8; bank++) 1278c36d9b3fSMaruthi Srinivas Bayyavarapu acp_set_sram_bank_state(adata->acp_mmio, bank, 1279c36d9b3fSMaruthi Srinivas Bayyavarapu true); 1280607b39efSVijendar Mukunda } 1281ccfbb4f5SMukunda, Vijendar rtd = adata->capture_i2ssp_stream->runtime->private_data; 1282ccfbb4f5SMukunda, Vijendar config_acp_dma(adata->acp_mmio, rtd, adata->asic_type); 1283ccfbb4f5SMukunda, Vijendar } 1284ccfbb4f5SMukunda, Vijendar if (adata->asic_type != CHIP_CARRIZO) { 1285ccfbb4f5SMukunda, Vijendar if (adata->play_i2sbt_stream && 1286ccfbb4f5SMukunda, Vijendar adata->play_i2sbt_stream->runtime) { 1287ccfbb4f5SMukunda, Vijendar rtd = adata->play_i2sbt_stream->runtime->private_data; 1288ccfbb4f5SMukunda, Vijendar config_acp_dma(adata->acp_mmio, rtd, adata->asic_type); 1289ccfbb4f5SMukunda, Vijendar } 1290ccfbb4f5SMukunda, Vijendar if (adata->capture_i2sbt_stream && 1291ccfbb4f5SMukunda, Vijendar adata->capture_i2sbt_stream->runtime) { 1292ccfbb4f5SMukunda, Vijendar rtd = adata->capture_i2sbt_stream->runtime->private_data; 1293ccfbb4f5SMukunda, Vijendar config_acp_dma(adata->acp_mmio, rtd, adata->asic_type); 1294ccfbb4f5SMukunda, Vijendar } 1295c36d9b3fSMaruthi Srinivas Bayyavarapu } 12961927da93SMaruthi Srinivas Bayyavarapu acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB); 12971927da93SMaruthi Srinivas Bayyavarapu return 0; 12981927da93SMaruthi Srinivas Bayyavarapu } 12991927da93SMaruthi Srinivas Bayyavarapu 13001927da93SMaruthi Srinivas Bayyavarapu static int acp_pcm_runtime_suspend(struct device *dev) 13011927da93SMaruthi Srinivas Bayyavarapu { 13027afa535eSMukunda, Vijendar int status; 13031927da93SMaruthi Srinivas Bayyavarapu struct audio_drv_data *adata = dev_get_drvdata(dev); 13041927da93SMaruthi Srinivas Bayyavarapu 13057afa535eSMukunda, Vijendar status = acp_deinit(adata->acp_mmio); 13067afa535eSMukunda, Vijendar if (status) 13077afa535eSMukunda, Vijendar dev_err(dev, "ACP Deinit failed status:%d\n", status); 13081927da93SMaruthi Srinivas Bayyavarapu acp_reg_write(0, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB); 13091927da93SMaruthi Srinivas Bayyavarapu return 0; 13101927da93SMaruthi Srinivas Bayyavarapu } 13111927da93SMaruthi Srinivas Bayyavarapu 13121927da93SMaruthi Srinivas Bayyavarapu static int acp_pcm_runtime_resume(struct device *dev) 13131927da93SMaruthi Srinivas Bayyavarapu { 13147afa535eSMukunda, Vijendar int status; 13151927da93SMaruthi Srinivas Bayyavarapu struct audio_drv_data *adata = dev_get_drvdata(dev); 13161927da93SMaruthi Srinivas Bayyavarapu 13177afa535eSMukunda, Vijendar status = acp_init(adata->acp_mmio, adata->asic_type); 13187afa535eSMukunda, Vijendar if (status) { 13197afa535eSMukunda, Vijendar dev_err(dev, "ACP Init failed status:%d\n", status); 13207afa535eSMukunda, Vijendar return status; 13217afa535eSMukunda, Vijendar } 13221927da93SMaruthi Srinivas Bayyavarapu acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB); 13231927da93SMaruthi Srinivas Bayyavarapu return 0; 13241927da93SMaruthi Srinivas Bayyavarapu } 13251927da93SMaruthi Srinivas Bayyavarapu 13261927da93SMaruthi Srinivas Bayyavarapu static const struct dev_pm_ops acp_pm_ops = { 13271927da93SMaruthi Srinivas Bayyavarapu .resume = acp_pcm_resume, 13281927da93SMaruthi Srinivas Bayyavarapu .runtime_suspend = acp_pcm_runtime_suspend, 13291927da93SMaruthi Srinivas Bayyavarapu .runtime_resume = acp_pcm_runtime_resume, 13301927da93SMaruthi Srinivas Bayyavarapu }; 13311927da93SMaruthi Srinivas Bayyavarapu 13327c31335aSMaruthi Srinivas Bayyavarapu static struct platform_driver acp_dma_driver = { 13337c31335aSMaruthi Srinivas Bayyavarapu .probe = acp_audio_probe, 13347c31335aSMaruthi Srinivas Bayyavarapu .remove = acp_audio_remove, 13357c31335aSMaruthi Srinivas Bayyavarapu .driver = { 1336bdd2a858SAkshu Agrawal .name = DRV_NAME, 13371927da93SMaruthi Srinivas Bayyavarapu .pm = &acp_pm_ops, 13387c31335aSMaruthi Srinivas Bayyavarapu }, 13397c31335aSMaruthi Srinivas Bayyavarapu }; 13407c31335aSMaruthi Srinivas Bayyavarapu 13417c31335aSMaruthi Srinivas Bayyavarapu module_platform_driver(acp_dma_driver); 13427c31335aSMaruthi Srinivas Bayyavarapu 1343607b39efSVijendar Mukunda MODULE_AUTHOR("Vijendar.Mukunda@amd.com"); 13447c31335aSMaruthi Srinivas Bayyavarapu MODULE_AUTHOR("Maruthi.Bayyavarapu@amd.com"); 13457c31335aSMaruthi Srinivas Bayyavarapu MODULE_DESCRIPTION("AMD ACP PCM Driver"); 13467c31335aSMaruthi Srinivas Bayyavarapu MODULE_LICENSE("GPL v2"); 1347bdd2a858SAkshu Agrawal MODULE_ALIAS("platform:"DRV_NAME); 1348