17c31335aSMaruthi Srinivas Bayyavarapu /* 27c31335aSMaruthi Srinivas Bayyavarapu * AMD ALSA SoC PCM Driver for ACP 2.x 37c31335aSMaruthi Srinivas Bayyavarapu * 47c31335aSMaruthi Srinivas Bayyavarapu * Copyright 2014-2015 Advanced Micro Devices, Inc. 57c31335aSMaruthi Srinivas Bayyavarapu * 67c31335aSMaruthi Srinivas Bayyavarapu * This program is free software; you can redistribute it and/or modify it 77c31335aSMaruthi Srinivas Bayyavarapu * under the terms and conditions of the GNU General Public License, 87c31335aSMaruthi Srinivas Bayyavarapu * version 2, as published by the Free Software Foundation. 97c31335aSMaruthi Srinivas Bayyavarapu * 107c31335aSMaruthi Srinivas Bayyavarapu * This program is distributed in the hope it will be useful, but WITHOUT 117c31335aSMaruthi Srinivas Bayyavarapu * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 127c31335aSMaruthi Srinivas Bayyavarapu * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 137c31335aSMaruthi Srinivas Bayyavarapu * more details. 147c31335aSMaruthi Srinivas Bayyavarapu */ 157c31335aSMaruthi Srinivas Bayyavarapu 167c31335aSMaruthi Srinivas Bayyavarapu #include <linux/module.h> 177c31335aSMaruthi Srinivas Bayyavarapu #include <linux/delay.h> 187cb1dc81SGuenter Roeck #include <linux/io.h> 197c31335aSMaruthi Srinivas Bayyavarapu #include <linux/sizes.h> 201927da93SMaruthi Srinivas Bayyavarapu #include <linux/pm_runtime.h> 217c31335aSMaruthi Srinivas Bayyavarapu 227c31335aSMaruthi Srinivas Bayyavarapu #include <sound/soc.h> 237c31335aSMaruthi Srinivas Bayyavarapu 247c31335aSMaruthi Srinivas Bayyavarapu #include "acp.h" 257c31335aSMaruthi Srinivas Bayyavarapu 267c31335aSMaruthi Srinivas Bayyavarapu #define PLAYBACK_MIN_NUM_PERIODS 2 277c31335aSMaruthi Srinivas Bayyavarapu #define PLAYBACK_MAX_NUM_PERIODS 2 287c31335aSMaruthi Srinivas Bayyavarapu #define PLAYBACK_MAX_PERIOD_SIZE 16384 297c31335aSMaruthi Srinivas Bayyavarapu #define PLAYBACK_MIN_PERIOD_SIZE 1024 307c31335aSMaruthi Srinivas Bayyavarapu #define CAPTURE_MIN_NUM_PERIODS 2 317c31335aSMaruthi Srinivas Bayyavarapu #define CAPTURE_MAX_NUM_PERIODS 2 327c31335aSMaruthi Srinivas Bayyavarapu #define CAPTURE_MAX_PERIOD_SIZE 16384 337c31335aSMaruthi Srinivas Bayyavarapu #define CAPTURE_MIN_PERIOD_SIZE 1024 347c31335aSMaruthi Srinivas Bayyavarapu 357c31335aSMaruthi Srinivas Bayyavarapu #define MAX_BUFFER (PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS) 367c31335aSMaruthi Srinivas Bayyavarapu #define MIN_BUFFER MAX_BUFFER 377c31335aSMaruthi Srinivas Bayyavarapu 387c31335aSMaruthi Srinivas Bayyavarapu static const struct snd_pcm_hardware acp_pcm_hardware_playback = { 397c31335aSMaruthi Srinivas Bayyavarapu .info = SNDRV_PCM_INFO_INTERLEAVED | 407c31335aSMaruthi Srinivas Bayyavarapu SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP | 417c31335aSMaruthi Srinivas Bayyavarapu SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH | 427c31335aSMaruthi Srinivas Bayyavarapu SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME, 437c31335aSMaruthi Srinivas Bayyavarapu .formats = SNDRV_PCM_FMTBIT_S16_LE | 447c31335aSMaruthi Srinivas Bayyavarapu SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, 457c31335aSMaruthi Srinivas Bayyavarapu .channels_min = 1, 467c31335aSMaruthi Srinivas Bayyavarapu .channels_max = 8, 477c31335aSMaruthi Srinivas Bayyavarapu .rates = SNDRV_PCM_RATE_8000_96000, 487c31335aSMaruthi Srinivas Bayyavarapu .rate_min = 8000, 497c31335aSMaruthi Srinivas Bayyavarapu .rate_max = 96000, 507c31335aSMaruthi Srinivas Bayyavarapu .buffer_bytes_max = PLAYBACK_MAX_NUM_PERIODS * PLAYBACK_MAX_PERIOD_SIZE, 517c31335aSMaruthi Srinivas Bayyavarapu .period_bytes_min = PLAYBACK_MIN_PERIOD_SIZE, 527c31335aSMaruthi Srinivas Bayyavarapu .period_bytes_max = PLAYBACK_MAX_PERIOD_SIZE, 537c31335aSMaruthi Srinivas Bayyavarapu .periods_min = PLAYBACK_MIN_NUM_PERIODS, 547c31335aSMaruthi Srinivas Bayyavarapu .periods_max = PLAYBACK_MAX_NUM_PERIODS, 557c31335aSMaruthi Srinivas Bayyavarapu }; 567c31335aSMaruthi Srinivas Bayyavarapu 577c31335aSMaruthi Srinivas Bayyavarapu static const struct snd_pcm_hardware acp_pcm_hardware_capture = { 587c31335aSMaruthi Srinivas Bayyavarapu .info = SNDRV_PCM_INFO_INTERLEAVED | 597c31335aSMaruthi Srinivas Bayyavarapu SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP | 607c31335aSMaruthi Srinivas Bayyavarapu SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH | 617c31335aSMaruthi Srinivas Bayyavarapu SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME, 627c31335aSMaruthi Srinivas Bayyavarapu .formats = SNDRV_PCM_FMTBIT_S16_LE | 637c31335aSMaruthi Srinivas Bayyavarapu SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, 647c31335aSMaruthi Srinivas Bayyavarapu .channels_min = 1, 657c31335aSMaruthi Srinivas Bayyavarapu .channels_max = 2, 667c31335aSMaruthi Srinivas Bayyavarapu .rates = SNDRV_PCM_RATE_8000_48000, 677c31335aSMaruthi Srinivas Bayyavarapu .rate_min = 8000, 687c31335aSMaruthi Srinivas Bayyavarapu .rate_max = 48000, 697c31335aSMaruthi Srinivas Bayyavarapu .buffer_bytes_max = CAPTURE_MAX_NUM_PERIODS * CAPTURE_MAX_PERIOD_SIZE, 707c31335aSMaruthi Srinivas Bayyavarapu .period_bytes_min = CAPTURE_MIN_PERIOD_SIZE, 717c31335aSMaruthi Srinivas Bayyavarapu .period_bytes_max = CAPTURE_MAX_PERIOD_SIZE, 727c31335aSMaruthi Srinivas Bayyavarapu .periods_min = CAPTURE_MIN_NUM_PERIODS, 737c31335aSMaruthi Srinivas Bayyavarapu .periods_max = CAPTURE_MAX_NUM_PERIODS, 747c31335aSMaruthi Srinivas Bayyavarapu }; 757c31335aSMaruthi Srinivas Bayyavarapu 767c31335aSMaruthi Srinivas Bayyavarapu struct audio_drv_data { 777c31335aSMaruthi Srinivas Bayyavarapu struct snd_pcm_substream *play_stream; 787c31335aSMaruthi Srinivas Bayyavarapu struct snd_pcm_substream *capture_stream; 797c31335aSMaruthi Srinivas Bayyavarapu void __iomem *acp_mmio; 807c31335aSMaruthi Srinivas Bayyavarapu }; 817c31335aSMaruthi Srinivas Bayyavarapu 827c31335aSMaruthi Srinivas Bayyavarapu static u32 acp_reg_read(void __iomem *acp_mmio, u32 reg) 837c31335aSMaruthi Srinivas Bayyavarapu { 847c31335aSMaruthi Srinivas Bayyavarapu return readl(acp_mmio + (reg * 4)); 857c31335aSMaruthi Srinivas Bayyavarapu } 867c31335aSMaruthi Srinivas Bayyavarapu 877c31335aSMaruthi Srinivas Bayyavarapu static void acp_reg_write(u32 val, void __iomem *acp_mmio, u32 reg) 887c31335aSMaruthi Srinivas Bayyavarapu { 897c31335aSMaruthi Srinivas Bayyavarapu writel(val, acp_mmio + (reg * 4)); 907c31335aSMaruthi Srinivas Bayyavarapu } 917c31335aSMaruthi Srinivas Bayyavarapu 927c31335aSMaruthi Srinivas Bayyavarapu /* Configure a given dma channel parameters - enable/disble, 937c31335aSMaruthi Srinivas Bayyavarapu * number of descriptors, priority 947c31335aSMaruthi Srinivas Bayyavarapu */ 957c31335aSMaruthi Srinivas Bayyavarapu static void config_acp_dma_channel(void __iomem *acp_mmio, u8 ch_num, 967c31335aSMaruthi Srinivas Bayyavarapu u16 dscr_strt_idx, u16 num_dscrs, 977c31335aSMaruthi Srinivas Bayyavarapu enum acp_dma_priority_level priority_level) 987c31335aSMaruthi Srinivas Bayyavarapu { 997c31335aSMaruthi Srinivas Bayyavarapu u32 dma_ctrl; 1007c31335aSMaruthi Srinivas Bayyavarapu 1017c31335aSMaruthi Srinivas Bayyavarapu /* disable the channel run field */ 1027c31335aSMaruthi Srinivas Bayyavarapu dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 1037c31335aSMaruthi Srinivas Bayyavarapu dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRun_MASK; 1047c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 1057c31335aSMaruthi Srinivas Bayyavarapu 1067c31335aSMaruthi Srinivas Bayyavarapu /* program a DMA channel with first descriptor to be processed. */ 1077c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write((ACP_DMA_DSCR_STRT_IDX_0__DMAChDscrStrtIdx_MASK 1087c31335aSMaruthi Srinivas Bayyavarapu & dscr_strt_idx), 1097c31335aSMaruthi Srinivas Bayyavarapu acp_mmio, mmACP_DMA_DSCR_STRT_IDX_0 + ch_num); 1107c31335aSMaruthi Srinivas Bayyavarapu 1117c31335aSMaruthi Srinivas Bayyavarapu /* program a DMA channel with the number of descriptors to be 1127c31335aSMaruthi Srinivas Bayyavarapu * processed in the transfer 1137c31335aSMaruthi Srinivas Bayyavarapu */ 1147c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(ACP_DMA_DSCR_CNT_0__DMAChDscrCnt_MASK & num_dscrs, 1157c31335aSMaruthi Srinivas Bayyavarapu acp_mmio, mmACP_DMA_DSCR_CNT_0 + ch_num); 1167c31335aSMaruthi Srinivas Bayyavarapu 1177c31335aSMaruthi Srinivas Bayyavarapu /* set DMA channel priority */ 1187c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(priority_level, acp_mmio, mmACP_DMA_PRIO_0 + ch_num); 1197c31335aSMaruthi Srinivas Bayyavarapu } 1207c31335aSMaruthi Srinivas Bayyavarapu 1217c31335aSMaruthi Srinivas Bayyavarapu /* Initialize a dma descriptor in SRAM based on descritor information passed */ 1227c31335aSMaruthi Srinivas Bayyavarapu static void config_dma_descriptor_in_sram(void __iomem *acp_mmio, 1237c31335aSMaruthi Srinivas Bayyavarapu u16 descr_idx, 1247c31335aSMaruthi Srinivas Bayyavarapu acp_dma_dscr_transfer_t *descr_info) 1257c31335aSMaruthi Srinivas Bayyavarapu { 1267c31335aSMaruthi Srinivas Bayyavarapu u32 sram_offset; 1277c31335aSMaruthi Srinivas Bayyavarapu 1287c31335aSMaruthi Srinivas Bayyavarapu sram_offset = (descr_idx * sizeof(acp_dma_dscr_transfer_t)); 1297c31335aSMaruthi Srinivas Bayyavarapu 1307c31335aSMaruthi Srinivas Bayyavarapu /* program the source base address. */ 1317c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(sram_offset, acp_mmio, mmACP_SRBM_Targ_Idx_Addr); 1327c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(descr_info->src, acp_mmio, mmACP_SRBM_Targ_Idx_Data); 1337c31335aSMaruthi Srinivas Bayyavarapu /* program the destination base address. */ 1347c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(sram_offset + 4, acp_mmio, mmACP_SRBM_Targ_Idx_Addr); 1357c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(descr_info->dest, acp_mmio, mmACP_SRBM_Targ_Idx_Data); 1367c31335aSMaruthi Srinivas Bayyavarapu 1377c31335aSMaruthi Srinivas Bayyavarapu /* program the number of bytes to be transferred for this descriptor. */ 1387c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(sram_offset + 8, acp_mmio, mmACP_SRBM_Targ_Idx_Addr); 1397c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(descr_info->xfer_val, acp_mmio, mmACP_SRBM_Targ_Idx_Data); 1407c31335aSMaruthi Srinivas Bayyavarapu } 1417c31335aSMaruthi Srinivas Bayyavarapu 1427c31335aSMaruthi Srinivas Bayyavarapu /* Initialize the DMA descriptor information for transfer between 1437c31335aSMaruthi Srinivas Bayyavarapu * system memory <-> ACP SRAM 1447c31335aSMaruthi Srinivas Bayyavarapu */ 1457c31335aSMaruthi Srinivas Bayyavarapu static void set_acp_sysmem_dma_descriptors(void __iomem *acp_mmio, 1467c31335aSMaruthi Srinivas Bayyavarapu u32 size, int direction, 1477c31335aSMaruthi Srinivas Bayyavarapu u32 pte_offset) 1487c31335aSMaruthi Srinivas Bayyavarapu { 1497c31335aSMaruthi Srinivas Bayyavarapu u16 i; 1507c31335aSMaruthi Srinivas Bayyavarapu u16 dma_dscr_idx = PLAYBACK_START_DMA_DESCR_CH12; 1517c31335aSMaruthi Srinivas Bayyavarapu acp_dma_dscr_transfer_t dmadscr[NUM_DSCRS_PER_CHANNEL]; 1527c31335aSMaruthi Srinivas Bayyavarapu 1537c31335aSMaruthi Srinivas Bayyavarapu for (i = 0; i < NUM_DSCRS_PER_CHANNEL; i++) { 1547c31335aSMaruthi Srinivas Bayyavarapu dmadscr[i].xfer_val = 0; 1557c31335aSMaruthi Srinivas Bayyavarapu if (direction == SNDRV_PCM_STREAM_PLAYBACK) { 1567c31335aSMaruthi Srinivas Bayyavarapu dma_dscr_idx = PLAYBACK_START_DMA_DESCR_CH12 + i; 1577c31335aSMaruthi Srinivas Bayyavarapu dmadscr[i].dest = ACP_SHARED_RAM_BANK_1_ADDRESS + 1587c31335aSMaruthi Srinivas Bayyavarapu (size / 2) - (i * (size/2)); 1597c31335aSMaruthi Srinivas Bayyavarapu dmadscr[i].src = ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS 1607c31335aSMaruthi Srinivas Bayyavarapu + (pte_offset * SZ_4K) + (i * (size/2)); 1617c31335aSMaruthi Srinivas Bayyavarapu dmadscr[i].xfer_val |= 1627c31335aSMaruthi Srinivas Bayyavarapu (ACP_DMA_ATTRIBUTES_DAGB_ONION_TO_SHAREDMEM << 16) | 1637c31335aSMaruthi Srinivas Bayyavarapu (size / 2); 1647c31335aSMaruthi Srinivas Bayyavarapu } else { 1657c31335aSMaruthi Srinivas Bayyavarapu dma_dscr_idx = CAPTURE_START_DMA_DESCR_CH14 + i; 1667c31335aSMaruthi Srinivas Bayyavarapu dmadscr[i].src = ACP_SHARED_RAM_BANK_5_ADDRESS + 1677c31335aSMaruthi Srinivas Bayyavarapu (i * (size/2)); 1687c31335aSMaruthi Srinivas Bayyavarapu dmadscr[i].dest = ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS 1697c31335aSMaruthi Srinivas Bayyavarapu + (pte_offset * SZ_4K) + 1707c31335aSMaruthi Srinivas Bayyavarapu (i * (size/2)); 1717c31335aSMaruthi Srinivas Bayyavarapu dmadscr[i].xfer_val |= 1727c31335aSMaruthi Srinivas Bayyavarapu BIT(22) | 1737c31335aSMaruthi Srinivas Bayyavarapu (ACP_DMA_ATTRIBUTES_SHAREDMEM_TO_DAGB_ONION << 16) | 1747c31335aSMaruthi Srinivas Bayyavarapu (size / 2); 1757c31335aSMaruthi Srinivas Bayyavarapu } 1767c31335aSMaruthi Srinivas Bayyavarapu config_dma_descriptor_in_sram(acp_mmio, dma_dscr_idx, 1777c31335aSMaruthi Srinivas Bayyavarapu &dmadscr[i]); 1787c31335aSMaruthi Srinivas Bayyavarapu } 1797c31335aSMaruthi Srinivas Bayyavarapu if (direction == SNDRV_PCM_STREAM_PLAYBACK) 1807c31335aSMaruthi Srinivas Bayyavarapu config_acp_dma_channel(acp_mmio, SYSRAM_TO_ACP_CH_NUM, 1817c31335aSMaruthi Srinivas Bayyavarapu PLAYBACK_START_DMA_DESCR_CH12, 1827c31335aSMaruthi Srinivas Bayyavarapu NUM_DSCRS_PER_CHANNEL, 1837c31335aSMaruthi Srinivas Bayyavarapu ACP_DMA_PRIORITY_LEVEL_NORMAL); 1847c31335aSMaruthi Srinivas Bayyavarapu else 1857c31335aSMaruthi Srinivas Bayyavarapu config_acp_dma_channel(acp_mmio, ACP_TO_SYSRAM_CH_NUM, 1867c31335aSMaruthi Srinivas Bayyavarapu CAPTURE_START_DMA_DESCR_CH14, 1877c31335aSMaruthi Srinivas Bayyavarapu NUM_DSCRS_PER_CHANNEL, 1887c31335aSMaruthi Srinivas Bayyavarapu ACP_DMA_PRIORITY_LEVEL_NORMAL); 1897c31335aSMaruthi Srinivas Bayyavarapu } 1907c31335aSMaruthi Srinivas Bayyavarapu 1917c31335aSMaruthi Srinivas Bayyavarapu /* Initialize the DMA descriptor information for transfer between 1927c31335aSMaruthi Srinivas Bayyavarapu * ACP SRAM <-> I2S 1937c31335aSMaruthi Srinivas Bayyavarapu */ 1947c31335aSMaruthi Srinivas Bayyavarapu static void set_acp_to_i2s_dma_descriptors(void __iomem *acp_mmio, 1957c31335aSMaruthi Srinivas Bayyavarapu u32 size, int direction) 1967c31335aSMaruthi Srinivas Bayyavarapu { 1977c31335aSMaruthi Srinivas Bayyavarapu 1987c31335aSMaruthi Srinivas Bayyavarapu u16 i; 1997c31335aSMaruthi Srinivas Bayyavarapu u16 dma_dscr_idx = PLAYBACK_START_DMA_DESCR_CH13; 2007c31335aSMaruthi Srinivas Bayyavarapu acp_dma_dscr_transfer_t dmadscr[NUM_DSCRS_PER_CHANNEL]; 2017c31335aSMaruthi Srinivas Bayyavarapu 2027c31335aSMaruthi Srinivas Bayyavarapu for (i = 0; i < NUM_DSCRS_PER_CHANNEL; i++) { 2037c31335aSMaruthi Srinivas Bayyavarapu dmadscr[i].xfer_val = 0; 2047c31335aSMaruthi Srinivas Bayyavarapu if (direction == SNDRV_PCM_STREAM_PLAYBACK) { 2057c31335aSMaruthi Srinivas Bayyavarapu dma_dscr_idx = PLAYBACK_START_DMA_DESCR_CH13 + i; 2067c31335aSMaruthi Srinivas Bayyavarapu dmadscr[i].src = ACP_SHARED_RAM_BANK_1_ADDRESS + 2077c31335aSMaruthi Srinivas Bayyavarapu (i * (size/2)); 2087c31335aSMaruthi Srinivas Bayyavarapu /* dmadscr[i].dest is unused by hardware. */ 2097c31335aSMaruthi Srinivas Bayyavarapu dmadscr[i].dest = 0; 2107c31335aSMaruthi Srinivas Bayyavarapu dmadscr[i].xfer_val |= BIT(22) | (TO_ACP_I2S_1 << 16) | 2117c31335aSMaruthi Srinivas Bayyavarapu (size / 2); 2127c31335aSMaruthi Srinivas Bayyavarapu } else { 2137c31335aSMaruthi Srinivas Bayyavarapu dma_dscr_idx = CAPTURE_START_DMA_DESCR_CH15 + i; 2147c31335aSMaruthi Srinivas Bayyavarapu /* dmadscr[i].src is unused by hardware. */ 2157c31335aSMaruthi Srinivas Bayyavarapu dmadscr[i].src = 0; 2167c31335aSMaruthi Srinivas Bayyavarapu dmadscr[i].dest = ACP_SHARED_RAM_BANK_5_ADDRESS + 2177c31335aSMaruthi Srinivas Bayyavarapu (i * (size / 2)); 2187c31335aSMaruthi Srinivas Bayyavarapu dmadscr[i].xfer_val |= BIT(22) | 2197c31335aSMaruthi Srinivas Bayyavarapu (FROM_ACP_I2S_1 << 16) | (size / 2); 2207c31335aSMaruthi Srinivas Bayyavarapu } 2217c31335aSMaruthi Srinivas Bayyavarapu config_dma_descriptor_in_sram(acp_mmio, dma_dscr_idx, 2227c31335aSMaruthi Srinivas Bayyavarapu &dmadscr[i]); 2237c31335aSMaruthi Srinivas Bayyavarapu } 2247c31335aSMaruthi Srinivas Bayyavarapu /* Configure the DMA channel with the above descriptore */ 2257c31335aSMaruthi Srinivas Bayyavarapu if (direction == SNDRV_PCM_STREAM_PLAYBACK) 2267c31335aSMaruthi Srinivas Bayyavarapu config_acp_dma_channel(acp_mmio, ACP_TO_I2S_DMA_CH_NUM, 2277c31335aSMaruthi Srinivas Bayyavarapu PLAYBACK_START_DMA_DESCR_CH13, 2287c31335aSMaruthi Srinivas Bayyavarapu NUM_DSCRS_PER_CHANNEL, 2297c31335aSMaruthi Srinivas Bayyavarapu ACP_DMA_PRIORITY_LEVEL_NORMAL); 2307c31335aSMaruthi Srinivas Bayyavarapu else 2317c31335aSMaruthi Srinivas Bayyavarapu config_acp_dma_channel(acp_mmio, I2S_TO_ACP_DMA_CH_NUM, 2327c31335aSMaruthi Srinivas Bayyavarapu CAPTURE_START_DMA_DESCR_CH15, 2337c31335aSMaruthi Srinivas Bayyavarapu NUM_DSCRS_PER_CHANNEL, 2347c31335aSMaruthi Srinivas Bayyavarapu ACP_DMA_PRIORITY_LEVEL_NORMAL); 2357c31335aSMaruthi Srinivas Bayyavarapu } 2367c31335aSMaruthi Srinivas Bayyavarapu 2377c31335aSMaruthi Srinivas Bayyavarapu /* Create page table entries in ACP SRAM for the allocated memory */ 2387c31335aSMaruthi Srinivas Bayyavarapu static void acp_pte_config(void __iomem *acp_mmio, struct page *pg, 2397c31335aSMaruthi Srinivas Bayyavarapu u16 num_of_pages, u32 pte_offset) 2407c31335aSMaruthi Srinivas Bayyavarapu { 2417c31335aSMaruthi Srinivas Bayyavarapu u16 page_idx; 2427c31335aSMaruthi Srinivas Bayyavarapu u64 addr; 2437c31335aSMaruthi Srinivas Bayyavarapu u32 low; 2447c31335aSMaruthi Srinivas Bayyavarapu u32 high; 2457c31335aSMaruthi Srinivas Bayyavarapu u32 offset; 2467c31335aSMaruthi Srinivas Bayyavarapu 2477c31335aSMaruthi Srinivas Bayyavarapu offset = ACP_DAGB_GRP_SRBM_SRAM_BASE_OFFSET + (pte_offset * 8); 2487c31335aSMaruthi Srinivas Bayyavarapu for (page_idx = 0; page_idx < (num_of_pages); page_idx++) { 2497c31335aSMaruthi Srinivas Bayyavarapu /* Load the low address of page int ACP SRAM through SRBM */ 2507c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write((offset + (page_idx * 8)), 2517c31335aSMaruthi Srinivas Bayyavarapu acp_mmio, mmACP_SRBM_Targ_Idx_Addr); 2527c31335aSMaruthi Srinivas Bayyavarapu addr = page_to_phys(pg); 2537c31335aSMaruthi Srinivas Bayyavarapu 2547c31335aSMaruthi Srinivas Bayyavarapu low = lower_32_bits(addr); 2557c31335aSMaruthi Srinivas Bayyavarapu high = upper_32_bits(addr); 2567c31335aSMaruthi Srinivas Bayyavarapu 2577c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(low, acp_mmio, mmACP_SRBM_Targ_Idx_Data); 2587c31335aSMaruthi Srinivas Bayyavarapu 2597c31335aSMaruthi Srinivas Bayyavarapu /* Load the High address of page int ACP SRAM through SRBM */ 2607c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write((offset + (page_idx * 8) + 4), 2617c31335aSMaruthi Srinivas Bayyavarapu acp_mmio, mmACP_SRBM_Targ_Idx_Addr); 2627c31335aSMaruthi Srinivas Bayyavarapu 2637c31335aSMaruthi Srinivas Bayyavarapu /* page enable in ACP */ 2647c31335aSMaruthi Srinivas Bayyavarapu high |= BIT(31); 2657c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(high, acp_mmio, mmACP_SRBM_Targ_Idx_Data); 2667c31335aSMaruthi Srinivas Bayyavarapu 2677c31335aSMaruthi Srinivas Bayyavarapu /* Move to next physically contiguos page */ 2687c31335aSMaruthi Srinivas Bayyavarapu pg++; 2697c31335aSMaruthi Srinivas Bayyavarapu } 2707c31335aSMaruthi Srinivas Bayyavarapu } 2717c31335aSMaruthi Srinivas Bayyavarapu 2727c31335aSMaruthi Srinivas Bayyavarapu static void config_acp_dma(void __iomem *acp_mmio, 2737c31335aSMaruthi Srinivas Bayyavarapu struct audio_substream_data *audio_config) 2747c31335aSMaruthi Srinivas Bayyavarapu { 2757c31335aSMaruthi Srinivas Bayyavarapu u32 pte_offset; 2767c31335aSMaruthi Srinivas Bayyavarapu 2777c31335aSMaruthi Srinivas Bayyavarapu if (audio_config->direction == SNDRV_PCM_STREAM_PLAYBACK) 2787c31335aSMaruthi Srinivas Bayyavarapu pte_offset = ACP_PLAYBACK_PTE_OFFSET; 2797c31335aSMaruthi Srinivas Bayyavarapu else 2807c31335aSMaruthi Srinivas Bayyavarapu pte_offset = ACP_CAPTURE_PTE_OFFSET; 2817c31335aSMaruthi Srinivas Bayyavarapu 2827c31335aSMaruthi Srinivas Bayyavarapu acp_pte_config(acp_mmio, audio_config->pg, audio_config->num_of_pages, 2837c31335aSMaruthi Srinivas Bayyavarapu pte_offset); 2847c31335aSMaruthi Srinivas Bayyavarapu 2857c31335aSMaruthi Srinivas Bayyavarapu /* Configure System memory <-> ACP SRAM DMA descriptors */ 2867c31335aSMaruthi Srinivas Bayyavarapu set_acp_sysmem_dma_descriptors(acp_mmio, audio_config->size, 2877c31335aSMaruthi Srinivas Bayyavarapu audio_config->direction, pte_offset); 2887c31335aSMaruthi Srinivas Bayyavarapu 2897c31335aSMaruthi Srinivas Bayyavarapu /* Configure ACP SRAM <-> I2S DMA descriptors */ 2907c31335aSMaruthi Srinivas Bayyavarapu set_acp_to_i2s_dma_descriptors(acp_mmio, audio_config->size, 2917c31335aSMaruthi Srinivas Bayyavarapu audio_config->direction); 2927c31335aSMaruthi Srinivas Bayyavarapu } 2937c31335aSMaruthi Srinivas Bayyavarapu 2947c31335aSMaruthi Srinivas Bayyavarapu /* Start a given DMA channel transfer */ 2957c31335aSMaruthi Srinivas Bayyavarapu static void acp_dma_start(void __iomem *acp_mmio, 2967c31335aSMaruthi Srinivas Bayyavarapu u16 ch_num, bool is_circular) 2977c31335aSMaruthi Srinivas Bayyavarapu { 2987c31335aSMaruthi Srinivas Bayyavarapu u32 dma_ctrl; 2997c31335aSMaruthi Srinivas Bayyavarapu 3007c31335aSMaruthi Srinivas Bayyavarapu /* read the dma control register and disable the channel run field */ 3017c31335aSMaruthi Srinivas Bayyavarapu dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 3027c31335aSMaruthi Srinivas Bayyavarapu 3037c31335aSMaruthi Srinivas Bayyavarapu /* Invalidating the DAGB cache */ 3047c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(1, acp_mmio, mmACP_DAGB_ATU_CTRL); 3057c31335aSMaruthi Srinivas Bayyavarapu 3067c31335aSMaruthi Srinivas Bayyavarapu /* configure the DMA channel and start the DMA transfer 3077c31335aSMaruthi Srinivas Bayyavarapu * set dmachrun bit to start the transfer and enable the 3087c31335aSMaruthi Srinivas Bayyavarapu * interrupt on completion of the dma transfer 3097c31335aSMaruthi Srinivas Bayyavarapu */ 3107c31335aSMaruthi Srinivas Bayyavarapu dma_ctrl |= ACP_DMA_CNTL_0__DMAChRun_MASK; 3117c31335aSMaruthi Srinivas Bayyavarapu 3127c31335aSMaruthi Srinivas Bayyavarapu switch (ch_num) { 3137c31335aSMaruthi Srinivas Bayyavarapu case ACP_TO_I2S_DMA_CH_NUM: 3147c31335aSMaruthi Srinivas Bayyavarapu case ACP_TO_SYSRAM_CH_NUM: 3157c31335aSMaruthi Srinivas Bayyavarapu case I2S_TO_ACP_DMA_CH_NUM: 3167c31335aSMaruthi Srinivas Bayyavarapu dma_ctrl |= ACP_DMA_CNTL_0__DMAChIOCEn_MASK; 3177c31335aSMaruthi Srinivas Bayyavarapu break; 3187c31335aSMaruthi Srinivas Bayyavarapu default: 3197c31335aSMaruthi Srinivas Bayyavarapu dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChIOCEn_MASK; 3207c31335aSMaruthi Srinivas Bayyavarapu break; 3217c31335aSMaruthi Srinivas Bayyavarapu } 3227c31335aSMaruthi Srinivas Bayyavarapu 3237c31335aSMaruthi Srinivas Bayyavarapu /* enable for ACP SRAM to/from I2S DMA channel */ 3247c31335aSMaruthi Srinivas Bayyavarapu if (is_circular == true) 3257c31335aSMaruthi Srinivas Bayyavarapu dma_ctrl |= ACP_DMA_CNTL_0__Circular_DMA_En_MASK; 3267c31335aSMaruthi Srinivas Bayyavarapu else 3277c31335aSMaruthi Srinivas Bayyavarapu dma_ctrl &= ~ACP_DMA_CNTL_0__Circular_DMA_En_MASK; 3287c31335aSMaruthi Srinivas Bayyavarapu 3297c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 3307c31335aSMaruthi Srinivas Bayyavarapu } 3317c31335aSMaruthi Srinivas Bayyavarapu 3327c31335aSMaruthi Srinivas Bayyavarapu /* Stop a given DMA channel transfer */ 3337c31335aSMaruthi Srinivas Bayyavarapu static int acp_dma_stop(void __iomem *acp_mmio, u8 ch_num) 3347c31335aSMaruthi Srinivas Bayyavarapu { 3357c31335aSMaruthi Srinivas Bayyavarapu u32 dma_ctrl; 3367c31335aSMaruthi Srinivas Bayyavarapu u32 dma_ch_sts; 3377c31335aSMaruthi Srinivas Bayyavarapu u32 count = ACP_DMA_RESET_TIME; 3387c31335aSMaruthi Srinivas Bayyavarapu 3397c31335aSMaruthi Srinivas Bayyavarapu dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 3407c31335aSMaruthi Srinivas Bayyavarapu 3417c31335aSMaruthi Srinivas Bayyavarapu /* clear the dma control register fields before writing zero 3427c31335aSMaruthi Srinivas Bayyavarapu * in reset bit 3437c31335aSMaruthi Srinivas Bayyavarapu */ 3447c31335aSMaruthi Srinivas Bayyavarapu dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRun_MASK; 3457c31335aSMaruthi Srinivas Bayyavarapu dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChIOCEn_MASK; 3467c31335aSMaruthi Srinivas Bayyavarapu 3477c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 3487c31335aSMaruthi Srinivas Bayyavarapu dma_ch_sts = acp_reg_read(acp_mmio, mmACP_DMA_CH_STS); 3497c31335aSMaruthi Srinivas Bayyavarapu 3507c31335aSMaruthi Srinivas Bayyavarapu if (dma_ch_sts & BIT(ch_num)) { 3517c31335aSMaruthi Srinivas Bayyavarapu /* set the reset bit for this channel to stop the dma 3527c31335aSMaruthi Srinivas Bayyavarapu * transfer 3537c31335aSMaruthi Srinivas Bayyavarapu */ 3547c31335aSMaruthi Srinivas Bayyavarapu dma_ctrl |= ACP_DMA_CNTL_0__DMAChRst_MASK; 3557c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 3567c31335aSMaruthi Srinivas Bayyavarapu } 3577c31335aSMaruthi Srinivas Bayyavarapu 3587c31335aSMaruthi Srinivas Bayyavarapu /* check the channel status bit for some time and return the status */ 3597c31335aSMaruthi Srinivas Bayyavarapu while (true) { 3607c31335aSMaruthi Srinivas Bayyavarapu dma_ch_sts = acp_reg_read(acp_mmio, mmACP_DMA_CH_STS); 3617c31335aSMaruthi Srinivas Bayyavarapu if (!(dma_ch_sts & BIT(ch_num))) { 3627c31335aSMaruthi Srinivas Bayyavarapu /* clear the reset flag after successfully stopping 3637c31335aSMaruthi Srinivas Bayyavarapu * the dma transfer and break from the loop 3647c31335aSMaruthi Srinivas Bayyavarapu */ 3657c31335aSMaruthi Srinivas Bayyavarapu dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRst_MASK; 3667c31335aSMaruthi Srinivas Bayyavarapu 3677c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 3687c31335aSMaruthi Srinivas Bayyavarapu + ch_num); 3697c31335aSMaruthi Srinivas Bayyavarapu break; 3707c31335aSMaruthi Srinivas Bayyavarapu } 3717c31335aSMaruthi Srinivas Bayyavarapu if (--count == 0) { 3727c31335aSMaruthi Srinivas Bayyavarapu pr_err("Failed to stop ACP DMA channel : %d\n", ch_num); 3737c31335aSMaruthi Srinivas Bayyavarapu return -ETIMEDOUT; 3747c31335aSMaruthi Srinivas Bayyavarapu } 3757c31335aSMaruthi Srinivas Bayyavarapu udelay(100); 3767c31335aSMaruthi Srinivas Bayyavarapu } 3777c31335aSMaruthi Srinivas Bayyavarapu return 0; 3787c31335aSMaruthi Srinivas Bayyavarapu } 3797c31335aSMaruthi Srinivas Bayyavarapu 380c36d9b3fSMaruthi Srinivas Bayyavarapu static void acp_set_sram_bank_state(void __iomem *acp_mmio, u16 bank, 381c36d9b3fSMaruthi Srinivas Bayyavarapu bool power_on) 382c36d9b3fSMaruthi Srinivas Bayyavarapu { 383c36d9b3fSMaruthi Srinivas Bayyavarapu u32 val, req_reg, sts_reg, sts_reg_mask; 384c36d9b3fSMaruthi Srinivas Bayyavarapu u32 loops = 1000; 385c36d9b3fSMaruthi Srinivas Bayyavarapu 386c36d9b3fSMaruthi Srinivas Bayyavarapu if (bank < 32) { 387c36d9b3fSMaruthi Srinivas Bayyavarapu req_reg = mmACP_MEM_SHUT_DOWN_REQ_LO; 388c36d9b3fSMaruthi Srinivas Bayyavarapu sts_reg = mmACP_MEM_SHUT_DOWN_STS_LO; 389c36d9b3fSMaruthi Srinivas Bayyavarapu sts_reg_mask = 0xFFFFFFFF; 390c36d9b3fSMaruthi Srinivas Bayyavarapu 391c36d9b3fSMaruthi Srinivas Bayyavarapu } else { 392c36d9b3fSMaruthi Srinivas Bayyavarapu bank -= 32; 393c36d9b3fSMaruthi Srinivas Bayyavarapu req_reg = mmACP_MEM_SHUT_DOWN_REQ_HI; 394c36d9b3fSMaruthi Srinivas Bayyavarapu sts_reg = mmACP_MEM_SHUT_DOWN_STS_HI; 395c36d9b3fSMaruthi Srinivas Bayyavarapu sts_reg_mask = 0x0000FFFF; 396c36d9b3fSMaruthi Srinivas Bayyavarapu } 397c36d9b3fSMaruthi Srinivas Bayyavarapu 398c36d9b3fSMaruthi Srinivas Bayyavarapu val = acp_reg_read(acp_mmio, req_reg); 399c36d9b3fSMaruthi Srinivas Bayyavarapu if (val & (1 << bank)) { 400c36d9b3fSMaruthi Srinivas Bayyavarapu /* bank is in off state */ 401c36d9b3fSMaruthi Srinivas Bayyavarapu if (power_on == true) 402c36d9b3fSMaruthi Srinivas Bayyavarapu /* request to on */ 403c36d9b3fSMaruthi Srinivas Bayyavarapu val &= ~(1 << bank); 404c36d9b3fSMaruthi Srinivas Bayyavarapu else 405c36d9b3fSMaruthi Srinivas Bayyavarapu /* request to off */ 406c36d9b3fSMaruthi Srinivas Bayyavarapu return; 407c36d9b3fSMaruthi Srinivas Bayyavarapu } else { 408c36d9b3fSMaruthi Srinivas Bayyavarapu /* bank is in on state */ 409c36d9b3fSMaruthi Srinivas Bayyavarapu if (power_on == false) 410c36d9b3fSMaruthi Srinivas Bayyavarapu /* request to off */ 411c36d9b3fSMaruthi Srinivas Bayyavarapu val |= 1 << bank; 412c36d9b3fSMaruthi Srinivas Bayyavarapu else 413c36d9b3fSMaruthi Srinivas Bayyavarapu /* request to on */ 414c36d9b3fSMaruthi Srinivas Bayyavarapu return; 415c36d9b3fSMaruthi Srinivas Bayyavarapu } 416c36d9b3fSMaruthi Srinivas Bayyavarapu acp_reg_write(val, acp_mmio, req_reg); 417c36d9b3fSMaruthi Srinivas Bayyavarapu 418c36d9b3fSMaruthi Srinivas Bayyavarapu while (acp_reg_read(acp_mmio, sts_reg) != sts_reg_mask) { 419c36d9b3fSMaruthi Srinivas Bayyavarapu if (!loops--) { 420c36d9b3fSMaruthi Srinivas Bayyavarapu pr_err("ACP SRAM bank %d state change failed\n", bank); 421c36d9b3fSMaruthi Srinivas Bayyavarapu break; 422c36d9b3fSMaruthi Srinivas Bayyavarapu } 423c36d9b3fSMaruthi Srinivas Bayyavarapu cpu_relax(); 424c36d9b3fSMaruthi Srinivas Bayyavarapu } 425c36d9b3fSMaruthi Srinivas Bayyavarapu } 426c36d9b3fSMaruthi Srinivas Bayyavarapu 4277c31335aSMaruthi Srinivas Bayyavarapu /* Initialize and bring ACP hardware to default state. */ 4287c31335aSMaruthi Srinivas Bayyavarapu static int acp_init(void __iomem *acp_mmio) 4297c31335aSMaruthi Srinivas Bayyavarapu { 430c36d9b3fSMaruthi Srinivas Bayyavarapu u16 bank; 4317c31335aSMaruthi Srinivas Bayyavarapu u32 val, count, sram_pte_offset; 4327c31335aSMaruthi Srinivas Bayyavarapu 4337c31335aSMaruthi Srinivas Bayyavarapu /* Assert Soft reset of ACP */ 4347c31335aSMaruthi Srinivas Bayyavarapu val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET); 4357c31335aSMaruthi Srinivas Bayyavarapu 4367c31335aSMaruthi Srinivas Bayyavarapu val |= ACP_SOFT_RESET__SoftResetAud_MASK; 4377c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET); 4387c31335aSMaruthi Srinivas Bayyavarapu 4397c31335aSMaruthi Srinivas Bayyavarapu count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE; 4407c31335aSMaruthi Srinivas Bayyavarapu while (true) { 4417c31335aSMaruthi Srinivas Bayyavarapu val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET); 4427c31335aSMaruthi Srinivas Bayyavarapu if (ACP_SOFT_RESET__SoftResetAudDone_MASK == 4437c31335aSMaruthi Srinivas Bayyavarapu (val & ACP_SOFT_RESET__SoftResetAudDone_MASK)) 4447c31335aSMaruthi Srinivas Bayyavarapu break; 4457c31335aSMaruthi Srinivas Bayyavarapu if (--count == 0) { 4467c31335aSMaruthi Srinivas Bayyavarapu pr_err("Failed to reset ACP\n"); 4477c31335aSMaruthi Srinivas Bayyavarapu return -ETIMEDOUT; 4487c31335aSMaruthi Srinivas Bayyavarapu } 4497c31335aSMaruthi Srinivas Bayyavarapu udelay(100); 4507c31335aSMaruthi Srinivas Bayyavarapu } 4517c31335aSMaruthi Srinivas Bayyavarapu 4527c31335aSMaruthi Srinivas Bayyavarapu /* Enable clock to ACP and wait until the clock is enabled */ 4537c31335aSMaruthi Srinivas Bayyavarapu val = acp_reg_read(acp_mmio, mmACP_CONTROL); 4547c31335aSMaruthi Srinivas Bayyavarapu val = val | ACP_CONTROL__ClkEn_MASK; 4557c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(val, acp_mmio, mmACP_CONTROL); 4567c31335aSMaruthi Srinivas Bayyavarapu 4577c31335aSMaruthi Srinivas Bayyavarapu count = ACP_CLOCK_EN_TIME_OUT_VALUE; 4587c31335aSMaruthi Srinivas Bayyavarapu 4597c31335aSMaruthi Srinivas Bayyavarapu while (true) { 4607c31335aSMaruthi Srinivas Bayyavarapu val = acp_reg_read(acp_mmio, mmACP_STATUS); 4617c31335aSMaruthi Srinivas Bayyavarapu if (val & (u32) 0x1) 4627c31335aSMaruthi Srinivas Bayyavarapu break; 4637c31335aSMaruthi Srinivas Bayyavarapu if (--count == 0) { 4647c31335aSMaruthi Srinivas Bayyavarapu pr_err("Failed to reset ACP\n"); 4657c31335aSMaruthi Srinivas Bayyavarapu return -ETIMEDOUT; 4667c31335aSMaruthi Srinivas Bayyavarapu } 4677c31335aSMaruthi Srinivas Bayyavarapu udelay(100); 4687c31335aSMaruthi Srinivas Bayyavarapu } 4697c31335aSMaruthi Srinivas Bayyavarapu 4707c31335aSMaruthi Srinivas Bayyavarapu /* Deassert the SOFT RESET flags */ 4717c31335aSMaruthi Srinivas Bayyavarapu val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET); 4727c31335aSMaruthi Srinivas Bayyavarapu val &= ~ACP_SOFT_RESET__SoftResetAud_MASK; 4737c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET); 4747c31335aSMaruthi Srinivas Bayyavarapu 4757c31335aSMaruthi Srinivas Bayyavarapu /* initiailize Onion control DAGB register */ 4767c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(ACP_ONION_CNTL_DEFAULT, acp_mmio, 4777c31335aSMaruthi Srinivas Bayyavarapu mmACP_AXI2DAGB_ONION_CNTL); 4787c31335aSMaruthi Srinivas Bayyavarapu 4797c31335aSMaruthi Srinivas Bayyavarapu /* initiailize Garlic control DAGB registers */ 4807c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(ACP_GARLIC_CNTL_DEFAULT, acp_mmio, 4817c31335aSMaruthi Srinivas Bayyavarapu mmACP_AXI2DAGB_GARLIC_CNTL); 4827c31335aSMaruthi Srinivas Bayyavarapu 4837c31335aSMaruthi Srinivas Bayyavarapu sram_pte_offset = ACP_DAGB_GRP_SRAM_BASE_ADDRESS | 4847c31335aSMaruthi Srinivas Bayyavarapu ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBSnoopSel_MASK | 4857c31335aSMaruthi Srinivas Bayyavarapu ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBTargetMemSel_MASK | 4867c31335aSMaruthi Srinivas Bayyavarapu ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBGrpEnable_MASK; 4877c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(sram_pte_offset, acp_mmio, mmACP_DAGB_BASE_ADDR_GRP_1); 4887c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(ACP_PAGE_SIZE_4K_ENABLE, acp_mmio, 4897c31335aSMaruthi Srinivas Bayyavarapu mmACP_DAGB_PAGE_SIZE_GRP_1); 4907c31335aSMaruthi Srinivas Bayyavarapu 4917c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(ACP_SRAM_BASE_ADDRESS, acp_mmio, 4927c31335aSMaruthi Srinivas Bayyavarapu mmACP_DMA_DESC_BASE_ADDR); 4937c31335aSMaruthi Srinivas Bayyavarapu 4947c31335aSMaruthi Srinivas Bayyavarapu /* Num of descriptiors in SRAM 0x4, means 256 descriptors;(64 * 4) */ 4957c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(0x4, acp_mmio, mmACP_DMA_DESC_MAX_NUM_DSCR); 4967c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(ACP_EXTERNAL_INTR_CNTL__DMAIOCMask_MASK, 4977c31335aSMaruthi Srinivas Bayyavarapu acp_mmio, mmACP_EXTERNAL_INTR_CNTL); 4987c31335aSMaruthi Srinivas Bayyavarapu 499c36d9b3fSMaruthi Srinivas Bayyavarapu /* When ACP_TILE_P1 is turned on, all SRAM banks get turned on. 500c36d9b3fSMaruthi Srinivas Bayyavarapu * Now, turn off all of them. This can't be done in 'poweron' of 501c36d9b3fSMaruthi Srinivas Bayyavarapu * ACP pm domain, as this requires ACP to be initialized. 502c36d9b3fSMaruthi Srinivas Bayyavarapu */ 503c36d9b3fSMaruthi Srinivas Bayyavarapu for (bank = 1; bank < 48; bank++) 504c36d9b3fSMaruthi Srinivas Bayyavarapu acp_set_sram_bank_state(acp_mmio, bank, false); 505c36d9b3fSMaruthi Srinivas Bayyavarapu 5067c31335aSMaruthi Srinivas Bayyavarapu return 0; 5077c31335aSMaruthi Srinivas Bayyavarapu } 5087c31335aSMaruthi Srinivas Bayyavarapu 5097c31335aSMaruthi Srinivas Bayyavarapu /* Deintialize ACP */ 5107c31335aSMaruthi Srinivas Bayyavarapu static int acp_deinit(void __iomem *acp_mmio) 5117c31335aSMaruthi Srinivas Bayyavarapu { 5127c31335aSMaruthi Srinivas Bayyavarapu u32 val; 5137c31335aSMaruthi Srinivas Bayyavarapu u32 count; 5147c31335aSMaruthi Srinivas Bayyavarapu 5157c31335aSMaruthi Srinivas Bayyavarapu /* Assert Soft reset of ACP */ 5167c31335aSMaruthi Srinivas Bayyavarapu val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET); 5177c31335aSMaruthi Srinivas Bayyavarapu 5187c31335aSMaruthi Srinivas Bayyavarapu val |= ACP_SOFT_RESET__SoftResetAud_MASK; 5197c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET); 5207c31335aSMaruthi Srinivas Bayyavarapu 5217c31335aSMaruthi Srinivas Bayyavarapu count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE; 5227c31335aSMaruthi Srinivas Bayyavarapu while (true) { 5237c31335aSMaruthi Srinivas Bayyavarapu val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET); 5247c31335aSMaruthi Srinivas Bayyavarapu if (ACP_SOFT_RESET__SoftResetAudDone_MASK == 5257c31335aSMaruthi Srinivas Bayyavarapu (val & ACP_SOFT_RESET__SoftResetAudDone_MASK)) 5267c31335aSMaruthi Srinivas Bayyavarapu break; 5277c31335aSMaruthi Srinivas Bayyavarapu if (--count == 0) { 5287c31335aSMaruthi Srinivas Bayyavarapu pr_err("Failed to reset ACP\n"); 5297c31335aSMaruthi Srinivas Bayyavarapu return -ETIMEDOUT; 5307c31335aSMaruthi Srinivas Bayyavarapu } 5317c31335aSMaruthi Srinivas Bayyavarapu udelay(100); 5327c31335aSMaruthi Srinivas Bayyavarapu } 5337c31335aSMaruthi Srinivas Bayyavarapu /** Disable ACP clock */ 5347c31335aSMaruthi Srinivas Bayyavarapu val = acp_reg_read(acp_mmio, mmACP_CONTROL); 5357c31335aSMaruthi Srinivas Bayyavarapu val &= ~ACP_CONTROL__ClkEn_MASK; 5367c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(val, acp_mmio, mmACP_CONTROL); 5377c31335aSMaruthi Srinivas Bayyavarapu 5387c31335aSMaruthi Srinivas Bayyavarapu count = ACP_CLOCK_EN_TIME_OUT_VALUE; 5397c31335aSMaruthi Srinivas Bayyavarapu 5407c31335aSMaruthi Srinivas Bayyavarapu while (true) { 5417c31335aSMaruthi Srinivas Bayyavarapu val = acp_reg_read(acp_mmio, mmACP_STATUS); 5427c31335aSMaruthi Srinivas Bayyavarapu if (!(val & (u32) 0x1)) 5437c31335aSMaruthi Srinivas Bayyavarapu break; 5447c31335aSMaruthi Srinivas Bayyavarapu if (--count == 0) { 5457c31335aSMaruthi Srinivas Bayyavarapu pr_err("Failed to reset ACP\n"); 5467c31335aSMaruthi Srinivas Bayyavarapu return -ETIMEDOUT; 5477c31335aSMaruthi Srinivas Bayyavarapu } 5487c31335aSMaruthi Srinivas Bayyavarapu udelay(100); 5497c31335aSMaruthi Srinivas Bayyavarapu } 5507c31335aSMaruthi Srinivas Bayyavarapu return 0; 5517c31335aSMaruthi Srinivas Bayyavarapu } 5527c31335aSMaruthi Srinivas Bayyavarapu 5537c31335aSMaruthi Srinivas Bayyavarapu /* ACP DMA irq handler routine for playback, capture usecases */ 5547c31335aSMaruthi Srinivas Bayyavarapu static irqreturn_t dma_irq_handler(int irq, void *arg) 5557c31335aSMaruthi Srinivas Bayyavarapu { 5567c31335aSMaruthi Srinivas Bayyavarapu u16 dscr_idx; 5577c31335aSMaruthi Srinivas Bayyavarapu u32 intr_flag, ext_intr_status; 5587c31335aSMaruthi Srinivas Bayyavarapu struct audio_drv_data *irq_data; 5597c31335aSMaruthi Srinivas Bayyavarapu void __iomem *acp_mmio; 5607c31335aSMaruthi Srinivas Bayyavarapu struct device *dev = arg; 5617c31335aSMaruthi Srinivas Bayyavarapu bool valid_irq = false; 5627c31335aSMaruthi Srinivas Bayyavarapu 5637c31335aSMaruthi Srinivas Bayyavarapu irq_data = dev_get_drvdata(dev); 5647c31335aSMaruthi Srinivas Bayyavarapu acp_mmio = irq_data->acp_mmio; 5657c31335aSMaruthi Srinivas Bayyavarapu 5667c31335aSMaruthi Srinivas Bayyavarapu ext_intr_status = acp_reg_read(acp_mmio, mmACP_EXTERNAL_INTR_STAT); 5677c31335aSMaruthi Srinivas Bayyavarapu intr_flag = (((ext_intr_status & 5687c31335aSMaruthi Srinivas Bayyavarapu ACP_EXTERNAL_INTR_STAT__DMAIOCStat_MASK) >> 5697c31335aSMaruthi Srinivas Bayyavarapu ACP_EXTERNAL_INTR_STAT__DMAIOCStat__SHIFT)); 5707c31335aSMaruthi Srinivas Bayyavarapu 5717c31335aSMaruthi Srinivas Bayyavarapu if ((intr_flag & BIT(ACP_TO_I2S_DMA_CH_NUM)) != 0) { 5727c31335aSMaruthi Srinivas Bayyavarapu valid_irq = true; 5737c31335aSMaruthi Srinivas Bayyavarapu if (acp_reg_read(acp_mmio, mmACP_DMA_CUR_DSCR_13) == 5747c31335aSMaruthi Srinivas Bayyavarapu PLAYBACK_START_DMA_DESCR_CH13) 5757c31335aSMaruthi Srinivas Bayyavarapu dscr_idx = PLAYBACK_START_DMA_DESCR_CH12; 5767c31335aSMaruthi Srinivas Bayyavarapu else 5777c31335aSMaruthi Srinivas Bayyavarapu dscr_idx = PLAYBACK_END_DMA_DESCR_CH12; 5787c31335aSMaruthi Srinivas Bayyavarapu config_acp_dma_channel(acp_mmio, SYSRAM_TO_ACP_CH_NUM, dscr_idx, 5797c31335aSMaruthi Srinivas Bayyavarapu 1, 0); 5807c31335aSMaruthi Srinivas Bayyavarapu acp_dma_start(acp_mmio, SYSRAM_TO_ACP_CH_NUM, false); 5817c31335aSMaruthi Srinivas Bayyavarapu 5827c31335aSMaruthi Srinivas Bayyavarapu snd_pcm_period_elapsed(irq_data->play_stream); 5837c31335aSMaruthi Srinivas Bayyavarapu 5847c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write((intr_flag & BIT(ACP_TO_I2S_DMA_CH_NUM)) << 16, 5857c31335aSMaruthi Srinivas Bayyavarapu acp_mmio, mmACP_EXTERNAL_INTR_STAT); 5867c31335aSMaruthi Srinivas Bayyavarapu } 5877c31335aSMaruthi Srinivas Bayyavarapu 5887c31335aSMaruthi Srinivas Bayyavarapu if ((intr_flag & BIT(I2S_TO_ACP_DMA_CH_NUM)) != 0) { 5897c31335aSMaruthi Srinivas Bayyavarapu valid_irq = true; 5907c31335aSMaruthi Srinivas Bayyavarapu if (acp_reg_read(acp_mmio, mmACP_DMA_CUR_DSCR_15) == 5917c31335aSMaruthi Srinivas Bayyavarapu CAPTURE_START_DMA_DESCR_CH15) 5927c31335aSMaruthi Srinivas Bayyavarapu dscr_idx = CAPTURE_END_DMA_DESCR_CH14; 5937c31335aSMaruthi Srinivas Bayyavarapu else 5947c31335aSMaruthi Srinivas Bayyavarapu dscr_idx = CAPTURE_START_DMA_DESCR_CH14; 5957c31335aSMaruthi Srinivas Bayyavarapu config_acp_dma_channel(acp_mmio, ACP_TO_SYSRAM_CH_NUM, dscr_idx, 5967c31335aSMaruthi Srinivas Bayyavarapu 1, 0); 5977c31335aSMaruthi Srinivas Bayyavarapu acp_dma_start(acp_mmio, ACP_TO_SYSRAM_CH_NUM, false); 5987c31335aSMaruthi Srinivas Bayyavarapu 5997c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write((intr_flag & BIT(I2S_TO_ACP_DMA_CH_NUM)) << 16, 6007c31335aSMaruthi Srinivas Bayyavarapu acp_mmio, mmACP_EXTERNAL_INTR_STAT); 6017c31335aSMaruthi Srinivas Bayyavarapu } 6027c31335aSMaruthi Srinivas Bayyavarapu 6037c31335aSMaruthi Srinivas Bayyavarapu if ((intr_flag & BIT(ACP_TO_SYSRAM_CH_NUM)) != 0) { 6047c31335aSMaruthi Srinivas Bayyavarapu valid_irq = true; 6057c31335aSMaruthi Srinivas Bayyavarapu snd_pcm_period_elapsed(irq_data->capture_stream); 6067c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write((intr_flag & BIT(ACP_TO_SYSRAM_CH_NUM)) << 16, 6077c31335aSMaruthi Srinivas Bayyavarapu acp_mmio, mmACP_EXTERNAL_INTR_STAT); 6087c31335aSMaruthi Srinivas Bayyavarapu } 6097c31335aSMaruthi Srinivas Bayyavarapu 6107c31335aSMaruthi Srinivas Bayyavarapu if (valid_irq) 6117c31335aSMaruthi Srinivas Bayyavarapu return IRQ_HANDLED; 6127c31335aSMaruthi Srinivas Bayyavarapu else 6137c31335aSMaruthi Srinivas Bayyavarapu return IRQ_NONE; 6147c31335aSMaruthi Srinivas Bayyavarapu } 6157c31335aSMaruthi Srinivas Bayyavarapu 6167c31335aSMaruthi Srinivas Bayyavarapu static int acp_dma_open(struct snd_pcm_substream *substream) 6177c31335aSMaruthi Srinivas Bayyavarapu { 618c36d9b3fSMaruthi Srinivas Bayyavarapu u16 bank; 6197c31335aSMaruthi Srinivas Bayyavarapu int ret = 0; 6207c31335aSMaruthi Srinivas Bayyavarapu struct snd_pcm_runtime *runtime = substream->runtime; 6217c31335aSMaruthi Srinivas Bayyavarapu struct snd_soc_pcm_runtime *prtd = substream->private_data; 6227c31335aSMaruthi Srinivas Bayyavarapu struct audio_drv_data *intr_data = dev_get_drvdata(prtd->platform->dev); 6237c31335aSMaruthi Srinivas Bayyavarapu 6247c31335aSMaruthi Srinivas Bayyavarapu struct audio_substream_data *adata = 6257c31335aSMaruthi Srinivas Bayyavarapu kzalloc(sizeof(struct audio_substream_data), GFP_KERNEL); 6267c31335aSMaruthi Srinivas Bayyavarapu if (adata == NULL) 6277c31335aSMaruthi Srinivas Bayyavarapu return -ENOMEM; 6287c31335aSMaruthi Srinivas Bayyavarapu 6297c31335aSMaruthi Srinivas Bayyavarapu if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 6307c31335aSMaruthi Srinivas Bayyavarapu runtime->hw = acp_pcm_hardware_playback; 6317c31335aSMaruthi Srinivas Bayyavarapu else 6327c31335aSMaruthi Srinivas Bayyavarapu runtime->hw = acp_pcm_hardware_capture; 6337c31335aSMaruthi Srinivas Bayyavarapu 6347c31335aSMaruthi Srinivas Bayyavarapu ret = snd_pcm_hw_constraint_integer(runtime, 6357c31335aSMaruthi Srinivas Bayyavarapu SNDRV_PCM_HW_PARAM_PERIODS); 6367c31335aSMaruthi Srinivas Bayyavarapu if (ret < 0) { 6377c31335aSMaruthi Srinivas Bayyavarapu dev_err(prtd->platform->dev, "set integer constraint failed\n"); 638cde6bcd5SDan Carpenter kfree(adata); 6397c31335aSMaruthi Srinivas Bayyavarapu return ret; 6407c31335aSMaruthi Srinivas Bayyavarapu } 6417c31335aSMaruthi Srinivas Bayyavarapu 6427c31335aSMaruthi Srinivas Bayyavarapu adata->acp_mmio = intr_data->acp_mmio; 6437c31335aSMaruthi Srinivas Bayyavarapu runtime->private_data = adata; 6447c31335aSMaruthi Srinivas Bayyavarapu 6457c31335aSMaruthi Srinivas Bayyavarapu /* Enable ACP irq, when neither playback or capture streams are 6467c31335aSMaruthi Srinivas Bayyavarapu * active by the time when a new stream is being opened. 6477c31335aSMaruthi Srinivas Bayyavarapu * This enablement is not required for another stream, if current 6487c31335aSMaruthi Srinivas Bayyavarapu * stream is not closed 6497c31335aSMaruthi Srinivas Bayyavarapu */ 6507c31335aSMaruthi Srinivas Bayyavarapu if (!intr_data->play_stream && !intr_data->capture_stream) 6517c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB); 6527c31335aSMaruthi Srinivas Bayyavarapu 653c36d9b3fSMaruthi Srinivas Bayyavarapu if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 6547c31335aSMaruthi Srinivas Bayyavarapu intr_data->play_stream = substream; 655c36d9b3fSMaruthi Srinivas Bayyavarapu for (bank = 1; bank <= 4; bank++) 656c36d9b3fSMaruthi Srinivas Bayyavarapu acp_set_sram_bank_state(intr_data->acp_mmio, bank, 657c36d9b3fSMaruthi Srinivas Bayyavarapu true); 658c36d9b3fSMaruthi Srinivas Bayyavarapu } else { 6597c31335aSMaruthi Srinivas Bayyavarapu intr_data->capture_stream = substream; 660c36d9b3fSMaruthi Srinivas Bayyavarapu for (bank = 5; bank <= 8; bank++) 661c36d9b3fSMaruthi Srinivas Bayyavarapu acp_set_sram_bank_state(intr_data->acp_mmio, bank, 662c36d9b3fSMaruthi Srinivas Bayyavarapu true); 663c36d9b3fSMaruthi Srinivas Bayyavarapu } 6647c31335aSMaruthi Srinivas Bayyavarapu 6657c31335aSMaruthi Srinivas Bayyavarapu return 0; 6667c31335aSMaruthi Srinivas Bayyavarapu } 6677c31335aSMaruthi Srinivas Bayyavarapu 6687c31335aSMaruthi Srinivas Bayyavarapu static int acp_dma_hw_params(struct snd_pcm_substream *substream, 6697c31335aSMaruthi Srinivas Bayyavarapu struct snd_pcm_hw_params *params) 6707c31335aSMaruthi Srinivas Bayyavarapu { 6717c31335aSMaruthi Srinivas Bayyavarapu int status; 6727c31335aSMaruthi Srinivas Bayyavarapu uint64_t size; 6737c31335aSMaruthi Srinivas Bayyavarapu struct snd_dma_buffer *dma_buffer; 6747c31335aSMaruthi Srinivas Bayyavarapu struct page *pg; 6757c31335aSMaruthi Srinivas Bayyavarapu struct snd_pcm_runtime *runtime; 6767c31335aSMaruthi Srinivas Bayyavarapu struct audio_substream_data *rtd; 6777c31335aSMaruthi Srinivas Bayyavarapu 6787c31335aSMaruthi Srinivas Bayyavarapu dma_buffer = &substream->dma_buffer; 6797c31335aSMaruthi Srinivas Bayyavarapu 6807c31335aSMaruthi Srinivas Bayyavarapu runtime = substream->runtime; 6817c31335aSMaruthi Srinivas Bayyavarapu rtd = runtime->private_data; 6827c31335aSMaruthi Srinivas Bayyavarapu 6837c31335aSMaruthi Srinivas Bayyavarapu if (WARN_ON(!rtd)) 6847c31335aSMaruthi Srinivas Bayyavarapu return -EINVAL; 6857c31335aSMaruthi Srinivas Bayyavarapu 6867c31335aSMaruthi Srinivas Bayyavarapu size = params_buffer_bytes(params); 6877c31335aSMaruthi Srinivas Bayyavarapu status = snd_pcm_lib_malloc_pages(substream, size); 6887c31335aSMaruthi Srinivas Bayyavarapu if (status < 0) 6897c31335aSMaruthi Srinivas Bayyavarapu return status; 6907c31335aSMaruthi Srinivas Bayyavarapu 6917c31335aSMaruthi Srinivas Bayyavarapu memset(substream->runtime->dma_area, 0, params_buffer_bytes(params)); 6927c31335aSMaruthi Srinivas Bayyavarapu pg = virt_to_page(substream->dma_buffer.area); 6937c31335aSMaruthi Srinivas Bayyavarapu 6947c31335aSMaruthi Srinivas Bayyavarapu if (pg != NULL) { 695c36d9b3fSMaruthi Srinivas Bayyavarapu acp_set_sram_bank_state(rtd->acp_mmio, 0, true); 6967c31335aSMaruthi Srinivas Bayyavarapu /* Save for runtime private data */ 6977c31335aSMaruthi Srinivas Bayyavarapu rtd->pg = pg; 6987c31335aSMaruthi Srinivas Bayyavarapu rtd->order = get_order(size); 6997c31335aSMaruthi Srinivas Bayyavarapu 7007c31335aSMaruthi Srinivas Bayyavarapu /* Fill the page table entries in ACP SRAM */ 7017c31335aSMaruthi Srinivas Bayyavarapu rtd->pg = pg; 7027c31335aSMaruthi Srinivas Bayyavarapu rtd->size = size; 7037c31335aSMaruthi Srinivas Bayyavarapu rtd->num_of_pages = PAGE_ALIGN(size) >> PAGE_SHIFT; 7047c31335aSMaruthi Srinivas Bayyavarapu rtd->direction = substream->stream; 7057c31335aSMaruthi Srinivas Bayyavarapu 7067c31335aSMaruthi Srinivas Bayyavarapu config_acp_dma(rtd->acp_mmio, rtd); 7077c31335aSMaruthi Srinivas Bayyavarapu status = 0; 7087c31335aSMaruthi Srinivas Bayyavarapu } else { 7097c31335aSMaruthi Srinivas Bayyavarapu status = -ENOMEM; 7107c31335aSMaruthi Srinivas Bayyavarapu } 7117c31335aSMaruthi Srinivas Bayyavarapu return status; 7127c31335aSMaruthi Srinivas Bayyavarapu } 7137c31335aSMaruthi Srinivas Bayyavarapu 7147c31335aSMaruthi Srinivas Bayyavarapu static int acp_dma_hw_free(struct snd_pcm_substream *substream) 7157c31335aSMaruthi Srinivas Bayyavarapu { 7167c31335aSMaruthi Srinivas Bayyavarapu return snd_pcm_lib_free_pages(substream); 7177c31335aSMaruthi Srinivas Bayyavarapu } 7187c31335aSMaruthi Srinivas Bayyavarapu 7197c31335aSMaruthi Srinivas Bayyavarapu static snd_pcm_uframes_t acp_dma_pointer(struct snd_pcm_substream *substream) 7207c31335aSMaruthi Srinivas Bayyavarapu { 7217c31335aSMaruthi Srinivas Bayyavarapu u16 dscr; 7227c31335aSMaruthi Srinivas Bayyavarapu u32 mul, dma_config, period_bytes; 7237c31335aSMaruthi Srinivas Bayyavarapu u32 pos = 0; 7247c31335aSMaruthi Srinivas Bayyavarapu 7257c31335aSMaruthi Srinivas Bayyavarapu struct snd_pcm_runtime *runtime = substream->runtime; 7267c31335aSMaruthi Srinivas Bayyavarapu struct audio_substream_data *rtd = runtime->private_data; 7277c31335aSMaruthi Srinivas Bayyavarapu 7287c31335aSMaruthi Srinivas Bayyavarapu period_bytes = frames_to_bytes(runtime, runtime->period_size); 7297c31335aSMaruthi Srinivas Bayyavarapu if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 7307c31335aSMaruthi Srinivas Bayyavarapu dscr = acp_reg_read(rtd->acp_mmio, mmACP_DMA_CUR_DSCR_13); 7317c31335aSMaruthi Srinivas Bayyavarapu 7327c31335aSMaruthi Srinivas Bayyavarapu if (dscr == PLAYBACK_START_DMA_DESCR_CH13) 7337c31335aSMaruthi Srinivas Bayyavarapu mul = 0; 7347c31335aSMaruthi Srinivas Bayyavarapu else 7357c31335aSMaruthi Srinivas Bayyavarapu mul = 1; 7367c31335aSMaruthi Srinivas Bayyavarapu pos = (mul * period_bytes); 7377c31335aSMaruthi Srinivas Bayyavarapu } else { 7387c31335aSMaruthi Srinivas Bayyavarapu dma_config = acp_reg_read(rtd->acp_mmio, mmACP_DMA_CNTL_14); 7397c31335aSMaruthi Srinivas Bayyavarapu if (dma_config != 0) { 7407c31335aSMaruthi Srinivas Bayyavarapu dscr = acp_reg_read(rtd->acp_mmio, 7417c31335aSMaruthi Srinivas Bayyavarapu mmACP_DMA_CUR_DSCR_14); 7427c31335aSMaruthi Srinivas Bayyavarapu if (dscr == CAPTURE_START_DMA_DESCR_CH14) 7437c31335aSMaruthi Srinivas Bayyavarapu mul = 1; 7447c31335aSMaruthi Srinivas Bayyavarapu else 7457c31335aSMaruthi Srinivas Bayyavarapu mul = 2; 7467c31335aSMaruthi Srinivas Bayyavarapu pos = (mul * period_bytes); 7477c31335aSMaruthi Srinivas Bayyavarapu } 7487c31335aSMaruthi Srinivas Bayyavarapu 7497c31335aSMaruthi Srinivas Bayyavarapu if (pos >= (2 * period_bytes)) 7507c31335aSMaruthi Srinivas Bayyavarapu pos = 0; 7517c31335aSMaruthi Srinivas Bayyavarapu 7527c31335aSMaruthi Srinivas Bayyavarapu } 7537c31335aSMaruthi Srinivas Bayyavarapu return bytes_to_frames(runtime, pos); 7547c31335aSMaruthi Srinivas Bayyavarapu } 7557c31335aSMaruthi Srinivas Bayyavarapu 7567c31335aSMaruthi Srinivas Bayyavarapu static int acp_dma_mmap(struct snd_pcm_substream *substream, 7577c31335aSMaruthi Srinivas Bayyavarapu struct vm_area_struct *vma) 7587c31335aSMaruthi Srinivas Bayyavarapu { 7597c31335aSMaruthi Srinivas Bayyavarapu return snd_pcm_lib_default_mmap(substream, vma); 7607c31335aSMaruthi Srinivas Bayyavarapu } 7617c31335aSMaruthi Srinivas Bayyavarapu 7627c31335aSMaruthi Srinivas Bayyavarapu static int acp_dma_prepare(struct snd_pcm_substream *substream) 7637c31335aSMaruthi Srinivas Bayyavarapu { 7647c31335aSMaruthi Srinivas Bayyavarapu struct snd_pcm_runtime *runtime = substream->runtime; 7657c31335aSMaruthi Srinivas Bayyavarapu struct audio_substream_data *rtd = runtime->private_data; 7667c31335aSMaruthi Srinivas Bayyavarapu 7677c31335aSMaruthi Srinivas Bayyavarapu if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 7687c31335aSMaruthi Srinivas Bayyavarapu config_acp_dma_channel(rtd->acp_mmio, SYSRAM_TO_ACP_CH_NUM, 7697c31335aSMaruthi Srinivas Bayyavarapu PLAYBACK_START_DMA_DESCR_CH12, 7707c31335aSMaruthi Srinivas Bayyavarapu NUM_DSCRS_PER_CHANNEL, 0); 7717c31335aSMaruthi Srinivas Bayyavarapu config_acp_dma_channel(rtd->acp_mmio, ACP_TO_I2S_DMA_CH_NUM, 7727c31335aSMaruthi Srinivas Bayyavarapu PLAYBACK_START_DMA_DESCR_CH13, 7737c31335aSMaruthi Srinivas Bayyavarapu NUM_DSCRS_PER_CHANNEL, 0); 7747c31335aSMaruthi Srinivas Bayyavarapu /* Fill ACP SRAM (2 periods) with zeros from System RAM 7757c31335aSMaruthi Srinivas Bayyavarapu * which is zero-ed in hw_params 7767c31335aSMaruthi Srinivas Bayyavarapu */ 7777c31335aSMaruthi Srinivas Bayyavarapu acp_dma_start(rtd->acp_mmio, SYSRAM_TO_ACP_CH_NUM, false); 7787c31335aSMaruthi Srinivas Bayyavarapu 7797c31335aSMaruthi Srinivas Bayyavarapu /* ACP SRAM (2 periods of buffer size) is intially filled with 7807c31335aSMaruthi Srinivas Bayyavarapu * zeros. Before rendering starts, 2nd half of SRAM will be 7817c31335aSMaruthi Srinivas Bayyavarapu * filled with valid audio data DMA'ed from first half of system 7827c31335aSMaruthi Srinivas Bayyavarapu * RAM and 1st half of SRAM will be filled with Zeros. This is 7837c31335aSMaruthi Srinivas Bayyavarapu * the initial scenario when redering starts from SRAM. Later 7847c31335aSMaruthi Srinivas Bayyavarapu * on, 2nd half of system memory will be DMA'ed to 1st half of 7857c31335aSMaruthi Srinivas Bayyavarapu * SRAM, 1st half of system memory will be DMA'ed to 2nd half of 7867c31335aSMaruthi Srinivas Bayyavarapu * SRAM in ping-pong way till rendering stops. 7877c31335aSMaruthi Srinivas Bayyavarapu */ 7887c31335aSMaruthi Srinivas Bayyavarapu config_acp_dma_channel(rtd->acp_mmio, SYSRAM_TO_ACP_CH_NUM, 7897c31335aSMaruthi Srinivas Bayyavarapu PLAYBACK_START_DMA_DESCR_CH12, 7907c31335aSMaruthi Srinivas Bayyavarapu 1, 0); 7917c31335aSMaruthi Srinivas Bayyavarapu } else { 7927c31335aSMaruthi Srinivas Bayyavarapu config_acp_dma_channel(rtd->acp_mmio, ACP_TO_SYSRAM_CH_NUM, 7937c31335aSMaruthi Srinivas Bayyavarapu CAPTURE_START_DMA_DESCR_CH14, 7947c31335aSMaruthi Srinivas Bayyavarapu NUM_DSCRS_PER_CHANNEL, 0); 7957c31335aSMaruthi Srinivas Bayyavarapu config_acp_dma_channel(rtd->acp_mmio, I2S_TO_ACP_DMA_CH_NUM, 7967c31335aSMaruthi Srinivas Bayyavarapu CAPTURE_START_DMA_DESCR_CH15, 7977c31335aSMaruthi Srinivas Bayyavarapu NUM_DSCRS_PER_CHANNEL, 0); 7987c31335aSMaruthi Srinivas Bayyavarapu } 7997c31335aSMaruthi Srinivas Bayyavarapu return 0; 8007c31335aSMaruthi Srinivas Bayyavarapu } 8017c31335aSMaruthi Srinivas Bayyavarapu 8027c31335aSMaruthi Srinivas Bayyavarapu static int acp_dma_trigger(struct snd_pcm_substream *substream, int cmd) 8037c31335aSMaruthi Srinivas Bayyavarapu { 8047c31335aSMaruthi Srinivas Bayyavarapu int ret; 8057c31335aSMaruthi Srinivas Bayyavarapu u32 loops = 1000; 8067c31335aSMaruthi Srinivas Bayyavarapu 8077c31335aSMaruthi Srinivas Bayyavarapu struct snd_pcm_runtime *runtime = substream->runtime; 8087c31335aSMaruthi Srinivas Bayyavarapu struct snd_soc_pcm_runtime *prtd = substream->private_data; 8097c31335aSMaruthi Srinivas Bayyavarapu struct audio_substream_data *rtd = runtime->private_data; 8107c31335aSMaruthi Srinivas Bayyavarapu 8117c31335aSMaruthi Srinivas Bayyavarapu if (!rtd) 8127c31335aSMaruthi Srinivas Bayyavarapu return -EINVAL; 8137c31335aSMaruthi Srinivas Bayyavarapu switch (cmd) { 8147c31335aSMaruthi Srinivas Bayyavarapu case SNDRV_PCM_TRIGGER_START: 8157c31335aSMaruthi Srinivas Bayyavarapu case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 8167c31335aSMaruthi Srinivas Bayyavarapu case SNDRV_PCM_TRIGGER_RESUME: 8177c31335aSMaruthi Srinivas Bayyavarapu if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 8187c31335aSMaruthi Srinivas Bayyavarapu acp_dma_start(rtd->acp_mmio, 8197c31335aSMaruthi Srinivas Bayyavarapu SYSRAM_TO_ACP_CH_NUM, false); 8207c31335aSMaruthi Srinivas Bayyavarapu while (acp_reg_read(rtd->acp_mmio, mmACP_DMA_CH_STS) & 8217c31335aSMaruthi Srinivas Bayyavarapu BIT(SYSRAM_TO_ACP_CH_NUM)) { 8227c31335aSMaruthi Srinivas Bayyavarapu if (!loops--) { 8237c31335aSMaruthi Srinivas Bayyavarapu dev_err(prtd->platform->dev, 8247c31335aSMaruthi Srinivas Bayyavarapu "acp dma start timeout\n"); 8257c31335aSMaruthi Srinivas Bayyavarapu return -ETIMEDOUT; 8267c31335aSMaruthi Srinivas Bayyavarapu } 8277c31335aSMaruthi Srinivas Bayyavarapu cpu_relax(); 8287c31335aSMaruthi Srinivas Bayyavarapu } 8297c31335aSMaruthi Srinivas Bayyavarapu 8307c31335aSMaruthi Srinivas Bayyavarapu acp_dma_start(rtd->acp_mmio, 8317c31335aSMaruthi Srinivas Bayyavarapu ACP_TO_I2S_DMA_CH_NUM, true); 8327c31335aSMaruthi Srinivas Bayyavarapu 8337c31335aSMaruthi Srinivas Bayyavarapu } else { 8347c31335aSMaruthi Srinivas Bayyavarapu acp_dma_start(rtd->acp_mmio, 8357c31335aSMaruthi Srinivas Bayyavarapu I2S_TO_ACP_DMA_CH_NUM, true); 8367c31335aSMaruthi Srinivas Bayyavarapu } 8377c31335aSMaruthi Srinivas Bayyavarapu ret = 0; 8387c31335aSMaruthi Srinivas Bayyavarapu break; 8397c31335aSMaruthi Srinivas Bayyavarapu case SNDRV_PCM_TRIGGER_STOP: 8407c31335aSMaruthi Srinivas Bayyavarapu case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 8417c31335aSMaruthi Srinivas Bayyavarapu case SNDRV_PCM_TRIGGER_SUSPEND: 8427c31335aSMaruthi Srinivas Bayyavarapu /* Need to stop only circular DMA channels : 8437c31335aSMaruthi Srinivas Bayyavarapu * ACP_TO_I2S_DMA_CH_NUM / I2S_TO_ACP_DMA_CH_NUM. Non-circular 8447c31335aSMaruthi Srinivas Bayyavarapu * channels will stopped automatically after its transfer 8457c31335aSMaruthi Srinivas Bayyavarapu * completes : SYSRAM_TO_ACP_CH_NUM / ACP_TO_SYSRAM_CH_NUM 8467c31335aSMaruthi Srinivas Bayyavarapu */ 8477c31335aSMaruthi Srinivas Bayyavarapu if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 8487c31335aSMaruthi Srinivas Bayyavarapu ret = acp_dma_stop(rtd->acp_mmio, 8497c31335aSMaruthi Srinivas Bayyavarapu ACP_TO_I2S_DMA_CH_NUM); 8507c31335aSMaruthi Srinivas Bayyavarapu else 8517c31335aSMaruthi Srinivas Bayyavarapu ret = acp_dma_stop(rtd->acp_mmio, 8527c31335aSMaruthi Srinivas Bayyavarapu I2S_TO_ACP_DMA_CH_NUM); 8537c31335aSMaruthi Srinivas Bayyavarapu break; 8547c31335aSMaruthi Srinivas Bayyavarapu default: 8557c31335aSMaruthi Srinivas Bayyavarapu ret = -EINVAL; 8567c31335aSMaruthi Srinivas Bayyavarapu 8577c31335aSMaruthi Srinivas Bayyavarapu } 8587c31335aSMaruthi Srinivas Bayyavarapu return ret; 8597c31335aSMaruthi Srinivas Bayyavarapu } 8607c31335aSMaruthi Srinivas Bayyavarapu 8617c31335aSMaruthi Srinivas Bayyavarapu static int acp_dma_new(struct snd_soc_pcm_runtime *rtd) 8627c31335aSMaruthi Srinivas Bayyavarapu { 8637c31335aSMaruthi Srinivas Bayyavarapu return snd_pcm_lib_preallocate_pages_for_all(rtd->pcm, 8647c31335aSMaruthi Srinivas Bayyavarapu SNDRV_DMA_TYPE_DEV, 8657c31335aSMaruthi Srinivas Bayyavarapu NULL, MIN_BUFFER, 8667c31335aSMaruthi Srinivas Bayyavarapu MAX_BUFFER); 8677c31335aSMaruthi Srinivas Bayyavarapu } 8687c31335aSMaruthi Srinivas Bayyavarapu 8697c31335aSMaruthi Srinivas Bayyavarapu static int acp_dma_close(struct snd_pcm_substream *substream) 8707c31335aSMaruthi Srinivas Bayyavarapu { 871c36d9b3fSMaruthi Srinivas Bayyavarapu u16 bank; 8727c31335aSMaruthi Srinivas Bayyavarapu struct snd_pcm_runtime *runtime = substream->runtime; 8737c31335aSMaruthi Srinivas Bayyavarapu struct audio_substream_data *rtd = runtime->private_data; 8747c31335aSMaruthi Srinivas Bayyavarapu struct snd_soc_pcm_runtime *prtd = substream->private_data; 8757c31335aSMaruthi Srinivas Bayyavarapu struct audio_drv_data *adata = dev_get_drvdata(prtd->platform->dev); 8767c31335aSMaruthi Srinivas Bayyavarapu 8777c31335aSMaruthi Srinivas Bayyavarapu kfree(rtd); 8787c31335aSMaruthi Srinivas Bayyavarapu 879c36d9b3fSMaruthi Srinivas Bayyavarapu if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 8807c31335aSMaruthi Srinivas Bayyavarapu adata->play_stream = NULL; 881c36d9b3fSMaruthi Srinivas Bayyavarapu for (bank = 1; bank <= 4; bank++) 882c36d9b3fSMaruthi Srinivas Bayyavarapu acp_set_sram_bank_state(adata->acp_mmio, bank, 883c36d9b3fSMaruthi Srinivas Bayyavarapu false); 884c36d9b3fSMaruthi Srinivas Bayyavarapu } else { 8857c31335aSMaruthi Srinivas Bayyavarapu adata->capture_stream = NULL; 886c36d9b3fSMaruthi Srinivas Bayyavarapu for (bank = 5; bank <= 8; bank++) 887c36d9b3fSMaruthi Srinivas Bayyavarapu acp_set_sram_bank_state(adata->acp_mmio, bank, 888c36d9b3fSMaruthi Srinivas Bayyavarapu false); 889c36d9b3fSMaruthi Srinivas Bayyavarapu } 8907c31335aSMaruthi Srinivas Bayyavarapu 8917c31335aSMaruthi Srinivas Bayyavarapu /* Disable ACP irq, when the current stream is being closed and 8927c31335aSMaruthi Srinivas Bayyavarapu * another stream is also not active. 8937c31335aSMaruthi Srinivas Bayyavarapu */ 8947c31335aSMaruthi Srinivas Bayyavarapu if (!adata->play_stream && !adata->capture_stream) 8957c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(0, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB); 8967c31335aSMaruthi Srinivas Bayyavarapu 8977c31335aSMaruthi Srinivas Bayyavarapu return 0; 8987c31335aSMaruthi Srinivas Bayyavarapu } 8997c31335aSMaruthi Srinivas Bayyavarapu 900*115c7254SJulia Lawall static const struct snd_pcm_ops acp_dma_ops = { 9017c31335aSMaruthi Srinivas Bayyavarapu .open = acp_dma_open, 9027c31335aSMaruthi Srinivas Bayyavarapu .close = acp_dma_close, 9037c31335aSMaruthi Srinivas Bayyavarapu .ioctl = snd_pcm_lib_ioctl, 9047c31335aSMaruthi Srinivas Bayyavarapu .hw_params = acp_dma_hw_params, 9057c31335aSMaruthi Srinivas Bayyavarapu .hw_free = acp_dma_hw_free, 9067c31335aSMaruthi Srinivas Bayyavarapu .trigger = acp_dma_trigger, 9077c31335aSMaruthi Srinivas Bayyavarapu .pointer = acp_dma_pointer, 9087c31335aSMaruthi Srinivas Bayyavarapu .mmap = acp_dma_mmap, 9097c31335aSMaruthi Srinivas Bayyavarapu .prepare = acp_dma_prepare, 9107c31335aSMaruthi Srinivas Bayyavarapu }; 9117c31335aSMaruthi Srinivas Bayyavarapu 9127c31335aSMaruthi Srinivas Bayyavarapu static struct snd_soc_platform_driver acp_asoc_platform = { 9137c31335aSMaruthi Srinivas Bayyavarapu .ops = &acp_dma_ops, 9147c31335aSMaruthi Srinivas Bayyavarapu .pcm_new = acp_dma_new, 9157c31335aSMaruthi Srinivas Bayyavarapu }; 9167c31335aSMaruthi Srinivas Bayyavarapu 9177c31335aSMaruthi Srinivas Bayyavarapu static int acp_audio_probe(struct platform_device *pdev) 9187c31335aSMaruthi Srinivas Bayyavarapu { 9197c31335aSMaruthi Srinivas Bayyavarapu int status; 9207c31335aSMaruthi Srinivas Bayyavarapu struct audio_drv_data *audio_drv_data; 9217c31335aSMaruthi Srinivas Bayyavarapu struct resource *res; 9227c31335aSMaruthi Srinivas Bayyavarapu 9237c31335aSMaruthi Srinivas Bayyavarapu audio_drv_data = devm_kzalloc(&pdev->dev, sizeof(struct audio_drv_data), 9247c31335aSMaruthi Srinivas Bayyavarapu GFP_KERNEL); 9257c31335aSMaruthi Srinivas Bayyavarapu if (audio_drv_data == NULL) 9267c31335aSMaruthi Srinivas Bayyavarapu return -ENOMEM; 9277c31335aSMaruthi Srinivas Bayyavarapu 9287c31335aSMaruthi Srinivas Bayyavarapu res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 9297c31335aSMaruthi Srinivas Bayyavarapu audio_drv_data->acp_mmio = devm_ioremap_resource(&pdev->dev, res); 9307c31335aSMaruthi Srinivas Bayyavarapu 9317c31335aSMaruthi Srinivas Bayyavarapu /* The following members gets populated in device 'open' 9327c31335aSMaruthi Srinivas Bayyavarapu * function. Till then interrupts are disabled in 'acp_init' 9337c31335aSMaruthi Srinivas Bayyavarapu * and device doesn't generate any interrupts. 9347c31335aSMaruthi Srinivas Bayyavarapu */ 9357c31335aSMaruthi Srinivas Bayyavarapu 9367c31335aSMaruthi Srinivas Bayyavarapu audio_drv_data->play_stream = NULL; 9377c31335aSMaruthi Srinivas Bayyavarapu audio_drv_data->capture_stream = NULL; 9387c31335aSMaruthi Srinivas Bayyavarapu 9397c31335aSMaruthi Srinivas Bayyavarapu res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 9407c31335aSMaruthi Srinivas Bayyavarapu if (!res) { 9417c31335aSMaruthi Srinivas Bayyavarapu dev_err(&pdev->dev, "IORESOURCE_IRQ FAILED\n"); 9427c31335aSMaruthi Srinivas Bayyavarapu return -ENODEV; 9437c31335aSMaruthi Srinivas Bayyavarapu } 9447c31335aSMaruthi Srinivas Bayyavarapu 9457c31335aSMaruthi Srinivas Bayyavarapu status = devm_request_irq(&pdev->dev, res->start, dma_irq_handler, 9467c31335aSMaruthi Srinivas Bayyavarapu 0, "ACP_IRQ", &pdev->dev); 9477c31335aSMaruthi Srinivas Bayyavarapu if (status) { 9487c31335aSMaruthi Srinivas Bayyavarapu dev_err(&pdev->dev, "ACP IRQ request failed\n"); 9497c31335aSMaruthi Srinivas Bayyavarapu return status; 9507c31335aSMaruthi Srinivas Bayyavarapu } 9517c31335aSMaruthi Srinivas Bayyavarapu 9527c31335aSMaruthi Srinivas Bayyavarapu dev_set_drvdata(&pdev->dev, audio_drv_data); 9537c31335aSMaruthi Srinivas Bayyavarapu 9547c31335aSMaruthi Srinivas Bayyavarapu /* Initialize the ACP */ 9557c31335aSMaruthi Srinivas Bayyavarapu acp_init(audio_drv_data->acp_mmio); 9567c31335aSMaruthi Srinivas Bayyavarapu 9577c31335aSMaruthi Srinivas Bayyavarapu status = snd_soc_register_platform(&pdev->dev, &acp_asoc_platform); 9587c31335aSMaruthi Srinivas Bayyavarapu if (status != 0) { 9597c31335aSMaruthi Srinivas Bayyavarapu dev_err(&pdev->dev, "Fail to register ALSA platform device\n"); 9607c31335aSMaruthi Srinivas Bayyavarapu return status; 9617c31335aSMaruthi Srinivas Bayyavarapu } 9627c31335aSMaruthi Srinivas Bayyavarapu 9631927da93SMaruthi Srinivas Bayyavarapu pm_runtime_set_autosuspend_delay(&pdev->dev, 10000); 9641927da93SMaruthi Srinivas Bayyavarapu pm_runtime_use_autosuspend(&pdev->dev); 9651927da93SMaruthi Srinivas Bayyavarapu pm_runtime_enable(&pdev->dev); 9661927da93SMaruthi Srinivas Bayyavarapu 9677c31335aSMaruthi Srinivas Bayyavarapu return status; 9687c31335aSMaruthi Srinivas Bayyavarapu } 9697c31335aSMaruthi Srinivas Bayyavarapu 9707c31335aSMaruthi Srinivas Bayyavarapu static int acp_audio_remove(struct platform_device *pdev) 9717c31335aSMaruthi Srinivas Bayyavarapu { 9727c31335aSMaruthi Srinivas Bayyavarapu struct audio_drv_data *adata = dev_get_drvdata(&pdev->dev); 9737c31335aSMaruthi Srinivas Bayyavarapu 9747c31335aSMaruthi Srinivas Bayyavarapu acp_deinit(adata->acp_mmio); 9757c31335aSMaruthi Srinivas Bayyavarapu snd_soc_unregister_platform(&pdev->dev); 9761927da93SMaruthi Srinivas Bayyavarapu pm_runtime_disable(&pdev->dev); 9777c31335aSMaruthi Srinivas Bayyavarapu 9787c31335aSMaruthi Srinivas Bayyavarapu return 0; 9797c31335aSMaruthi Srinivas Bayyavarapu } 9807c31335aSMaruthi Srinivas Bayyavarapu 9811927da93SMaruthi Srinivas Bayyavarapu static int acp_pcm_resume(struct device *dev) 9821927da93SMaruthi Srinivas Bayyavarapu { 983c36d9b3fSMaruthi Srinivas Bayyavarapu u16 bank; 9841927da93SMaruthi Srinivas Bayyavarapu struct audio_drv_data *adata = dev_get_drvdata(dev); 9851927da93SMaruthi Srinivas Bayyavarapu 9861927da93SMaruthi Srinivas Bayyavarapu acp_init(adata->acp_mmio); 9871927da93SMaruthi Srinivas Bayyavarapu 988c36d9b3fSMaruthi Srinivas Bayyavarapu if (adata->play_stream && adata->play_stream->runtime) { 989c36d9b3fSMaruthi Srinivas Bayyavarapu for (bank = 1; bank <= 4; bank++) 990c36d9b3fSMaruthi Srinivas Bayyavarapu acp_set_sram_bank_state(adata->acp_mmio, bank, 991c36d9b3fSMaruthi Srinivas Bayyavarapu true); 9921927da93SMaruthi Srinivas Bayyavarapu config_acp_dma(adata->acp_mmio, 9931927da93SMaruthi Srinivas Bayyavarapu adata->play_stream->runtime->private_data); 994c36d9b3fSMaruthi Srinivas Bayyavarapu } 995c36d9b3fSMaruthi Srinivas Bayyavarapu if (adata->capture_stream && adata->capture_stream->runtime) { 996c36d9b3fSMaruthi Srinivas Bayyavarapu for (bank = 5; bank <= 8; bank++) 997c36d9b3fSMaruthi Srinivas Bayyavarapu acp_set_sram_bank_state(adata->acp_mmio, bank, 998c36d9b3fSMaruthi Srinivas Bayyavarapu true); 9991927da93SMaruthi Srinivas Bayyavarapu config_acp_dma(adata->acp_mmio, 10001927da93SMaruthi Srinivas Bayyavarapu adata->capture_stream->runtime->private_data); 1001c36d9b3fSMaruthi Srinivas Bayyavarapu } 10021927da93SMaruthi Srinivas Bayyavarapu acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB); 10031927da93SMaruthi Srinivas Bayyavarapu return 0; 10041927da93SMaruthi Srinivas Bayyavarapu } 10051927da93SMaruthi Srinivas Bayyavarapu 10061927da93SMaruthi Srinivas Bayyavarapu static int acp_pcm_runtime_suspend(struct device *dev) 10071927da93SMaruthi Srinivas Bayyavarapu { 10081927da93SMaruthi Srinivas Bayyavarapu struct audio_drv_data *adata = dev_get_drvdata(dev); 10091927da93SMaruthi Srinivas Bayyavarapu 10101927da93SMaruthi Srinivas Bayyavarapu acp_deinit(adata->acp_mmio); 10111927da93SMaruthi Srinivas Bayyavarapu acp_reg_write(0, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB); 10121927da93SMaruthi Srinivas Bayyavarapu return 0; 10131927da93SMaruthi Srinivas Bayyavarapu } 10141927da93SMaruthi Srinivas Bayyavarapu 10151927da93SMaruthi Srinivas Bayyavarapu static int acp_pcm_runtime_resume(struct device *dev) 10161927da93SMaruthi Srinivas Bayyavarapu { 10171927da93SMaruthi Srinivas Bayyavarapu struct audio_drv_data *adata = dev_get_drvdata(dev); 10181927da93SMaruthi Srinivas Bayyavarapu 10191927da93SMaruthi Srinivas Bayyavarapu acp_init(adata->acp_mmio); 10201927da93SMaruthi Srinivas Bayyavarapu acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB); 10211927da93SMaruthi Srinivas Bayyavarapu return 0; 10221927da93SMaruthi Srinivas Bayyavarapu } 10231927da93SMaruthi Srinivas Bayyavarapu 10241927da93SMaruthi Srinivas Bayyavarapu static const struct dev_pm_ops acp_pm_ops = { 10251927da93SMaruthi Srinivas Bayyavarapu .resume = acp_pcm_resume, 10261927da93SMaruthi Srinivas Bayyavarapu .runtime_suspend = acp_pcm_runtime_suspend, 10271927da93SMaruthi Srinivas Bayyavarapu .runtime_resume = acp_pcm_runtime_resume, 10281927da93SMaruthi Srinivas Bayyavarapu }; 10291927da93SMaruthi Srinivas Bayyavarapu 10307c31335aSMaruthi Srinivas Bayyavarapu static struct platform_driver acp_dma_driver = { 10317c31335aSMaruthi Srinivas Bayyavarapu .probe = acp_audio_probe, 10327c31335aSMaruthi Srinivas Bayyavarapu .remove = acp_audio_remove, 10337c31335aSMaruthi Srinivas Bayyavarapu .driver = { 10347c31335aSMaruthi Srinivas Bayyavarapu .name = "acp_audio_dma", 10351927da93SMaruthi Srinivas Bayyavarapu .pm = &acp_pm_ops, 10367c31335aSMaruthi Srinivas Bayyavarapu }, 10377c31335aSMaruthi Srinivas Bayyavarapu }; 10387c31335aSMaruthi Srinivas Bayyavarapu 10397c31335aSMaruthi Srinivas Bayyavarapu module_platform_driver(acp_dma_driver); 10407c31335aSMaruthi Srinivas Bayyavarapu 10417c31335aSMaruthi Srinivas Bayyavarapu MODULE_AUTHOR("Maruthi.Bayyavarapu@amd.com"); 10427c31335aSMaruthi Srinivas Bayyavarapu MODULE_DESCRIPTION("AMD ACP PCM Driver"); 10437c31335aSMaruthi Srinivas Bayyavarapu MODULE_LICENSE("GPL v2"); 10447c31335aSMaruthi Srinivas Bayyavarapu MODULE_ALIAS("platform:acp-dma-audio"); 1045