12025cf9eSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 27c31335aSMaruthi Srinivas Bayyavarapu /* 37c31335aSMaruthi Srinivas Bayyavarapu * AMD ALSA SoC PCM Driver for ACP 2.x 47c31335aSMaruthi Srinivas Bayyavarapu * 57c31335aSMaruthi Srinivas Bayyavarapu * Copyright 2014-2015 Advanced Micro Devices, Inc. 67c31335aSMaruthi Srinivas Bayyavarapu */ 77c31335aSMaruthi Srinivas Bayyavarapu 87c31335aSMaruthi Srinivas Bayyavarapu #include <linux/module.h> 97c31335aSMaruthi Srinivas Bayyavarapu #include <linux/delay.h> 107cb1dc81SGuenter Roeck #include <linux/io.h> 112a665dbaSAkshu Agrawal #include <linux/iopoll.h> 127c31335aSMaruthi Srinivas Bayyavarapu #include <linux/sizes.h> 131927da93SMaruthi Srinivas Bayyavarapu #include <linux/pm_runtime.h> 147c31335aSMaruthi Srinivas Bayyavarapu 157c31335aSMaruthi Srinivas Bayyavarapu #include <sound/soc.h> 16607b39efSVijendar Mukunda #include <drm/amd_asic_type.h> 177c31335aSMaruthi Srinivas Bayyavarapu #include "acp.h" 187c31335aSMaruthi Srinivas Bayyavarapu 19a1042a42SKuninori Morimoto #define DRV_NAME "acp_audio_dma" 20a1042a42SKuninori Morimoto 217c31335aSMaruthi Srinivas Bayyavarapu #define PLAYBACK_MIN_NUM_PERIODS 2 227c31335aSMaruthi Srinivas Bayyavarapu #define PLAYBACK_MAX_NUM_PERIODS 2 237c31335aSMaruthi Srinivas Bayyavarapu #define PLAYBACK_MAX_PERIOD_SIZE 16384 247c31335aSMaruthi Srinivas Bayyavarapu #define PLAYBACK_MIN_PERIOD_SIZE 1024 257c31335aSMaruthi Srinivas Bayyavarapu #define CAPTURE_MIN_NUM_PERIODS 2 267c31335aSMaruthi Srinivas Bayyavarapu #define CAPTURE_MAX_NUM_PERIODS 2 277c31335aSMaruthi Srinivas Bayyavarapu #define CAPTURE_MAX_PERIOD_SIZE 16384 287c31335aSMaruthi Srinivas Bayyavarapu #define CAPTURE_MIN_PERIOD_SIZE 1024 297c31335aSMaruthi Srinivas Bayyavarapu 307c31335aSMaruthi Srinivas Bayyavarapu #define MAX_BUFFER (PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS) 317c31335aSMaruthi Srinivas Bayyavarapu #define MIN_BUFFER MAX_BUFFER 327c31335aSMaruthi Srinivas Bayyavarapu 33ccfbb4f5SMukunda, Vijendar #define ST_PLAYBACK_MAX_PERIOD_SIZE 4096 349c7d6fabSVijendar Mukunda #define ST_CAPTURE_MAX_PERIOD_SIZE ST_PLAYBACK_MAX_PERIOD_SIZE 359c7d6fabSVijendar Mukunda #define ST_MAX_BUFFER (ST_PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS) 369c7d6fabSVijendar Mukunda #define ST_MIN_BUFFER ST_MAX_BUFFER 379c7d6fabSVijendar Mukunda 38bdd2a858SAkshu Agrawal #define DRV_NAME "acp_audio_dma" 3919843302SPierre-Louis Bossart bool acp_bt_uart_enable = true; 4019843302SPierre-Louis Bossart EXPORT_SYMBOL(acp_bt_uart_enable); 41bdd2a858SAkshu Agrawal 427c31335aSMaruthi Srinivas Bayyavarapu static const struct snd_pcm_hardware acp_pcm_hardware_playback = { 437c31335aSMaruthi Srinivas Bayyavarapu .info = SNDRV_PCM_INFO_INTERLEAVED | 447c31335aSMaruthi Srinivas Bayyavarapu SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP | 457c31335aSMaruthi Srinivas Bayyavarapu SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH | 467c31335aSMaruthi Srinivas Bayyavarapu SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME, 477c31335aSMaruthi Srinivas Bayyavarapu .formats = SNDRV_PCM_FMTBIT_S16_LE | 487c31335aSMaruthi Srinivas Bayyavarapu SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, 497c31335aSMaruthi Srinivas Bayyavarapu .channels_min = 1, 507c31335aSMaruthi Srinivas Bayyavarapu .channels_max = 8, 517c31335aSMaruthi Srinivas Bayyavarapu .rates = SNDRV_PCM_RATE_8000_96000, 527c31335aSMaruthi Srinivas Bayyavarapu .rate_min = 8000, 537c31335aSMaruthi Srinivas Bayyavarapu .rate_max = 96000, 547c31335aSMaruthi Srinivas Bayyavarapu .buffer_bytes_max = PLAYBACK_MAX_NUM_PERIODS * PLAYBACK_MAX_PERIOD_SIZE, 557c31335aSMaruthi Srinivas Bayyavarapu .period_bytes_min = PLAYBACK_MIN_PERIOD_SIZE, 567c31335aSMaruthi Srinivas Bayyavarapu .period_bytes_max = PLAYBACK_MAX_PERIOD_SIZE, 577c31335aSMaruthi Srinivas Bayyavarapu .periods_min = PLAYBACK_MIN_NUM_PERIODS, 587c31335aSMaruthi Srinivas Bayyavarapu .periods_max = PLAYBACK_MAX_NUM_PERIODS, 597c31335aSMaruthi Srinivas Bayyavarapu }; 607c31335aSMaruthi Srinivas Bayyavarapu 617c31335aSMaruthi Srinivas Bayyavarapu static const struct snd_pcm_hardware acp_pcm_hardware_capture = { 627c31335aSMaruthi Srinivas Bayyavarapu .info = SNDRV_PCM_INFO_INTERLEAVED | 637c31335aSMaruthi Srinivas Bayyavarapu SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP | 647c31335aSMaruthi Srinivas Bayyavarapu SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH | 657c31335aSMaruthi Srinivas Bayyavarapu SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME, 667c31335aSMaruthi Srinivas Bayyavarapu .formats = SNDRV_PCM_FMTBIT_S16_LE | 677c31335aSMaruthi Srinivas Bayyavarapu SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, 687c31335aSMaruthi Srinivas Bayyavarapu .channels_min = 1, 697c31335aSMaruthi Srinivas Bayyavarapu .channels_max = 2, 707c31335aSMaruthi Srinivas Bayyavarapu .rates = SNDRV_PCM_RATE_8000_48000, 717c31335aSMaruthi Srinivas Bayyavarapu .rate_min = 8000, 727c31335aSMaruthi Srinivas Bayyavarapu .rate_max = 48000, 737c31335aSMaruthi Srinivas Bayyavarapu .buffer_bytes_max = CAPTURE_MAX_NUM_PERIODS * CAPTURE_MAX_PERIOD_SIZE, 747c31335aSMaruthi Srinivas Bayyavarapu .period_bytes_min = CAPTURE_MIN_PERIOD_SIZE, 757c31335aSMaruthi Srinivas Bayyavarapu .period_bytes_max = CAPTURE_MAX_PERIOD_SIZE, 767c31335aSMaruthi Srinivas Bayyavarapu .periods_min = CAPTURE_MIN_NUM_PERIODS, 777c31335aSMaruthi Srinivas Bayyavarapu .periods_max = CAPTURE_MAX_NUM_PERIODS, 787c31335aSMaruthi Srinivas Bayyavarapu }; 797c31335aSMaruthi Srinivas Bayyavarapu 809c7d6fabSVijendar Mukunda static const struct snd_pcm_hardware acp_st_pcm_hardware_playback = { 819c7d6fabSVijendar Mukunda .info = SNDRV_PCM_INFO_INTERLEAVED | 829c7d6fabSVijendar Mukunda SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP | 839c7d6fabSVijendar Mukunda SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH | 849c7d6fabSVijendar Mukunda SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME, 859c7d6fabSVijendar Mukunda .formats = SNDRV_PCM_FMTBIT_S16_LE | 869c7d6fabSVijendar Mukunda SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, 879c7d6fabSVijendar Mukunda .channels_min = 1, 889c7d6fabSVijendar Mukunda .channels_max = 8, 899c7d6fabSVijendar Mukunda .rates = SNDRV_PCM_RATE_8000_96000, 909c7d6fabSVijendar Mukunda .rate_min = 8000, 919c7d6fabSVijendar Mukunda .rate_max = 96000, 929c7d6fabSVijendar Mukunda .buffer_bytes_max = ST_MAX_BUFFER, 939c7d6fabSVijendar Mukunda .period_bytes_min = PLAYBACK_MIN_PERIOD_SIZE, 949c7d6fabSVijendar Mukunda .period_bytes_max = ST_PLAYBACK_MAX_PERIOD_SIZE, 959c7d6fabSVijendar Mukunda .periods_min = PLAYBACK_MIN_NUM_PERIODS, 969c7d6fabSVijendar Mukunda .periods_max = PLAYBACK_MAX_NUM_PERIODS, 979c7d6fabSVijendar Mukunda }; 989c7d6fabSVijendar Mukunda 999c7d6fabSVijendar Mukunda static const struct snd_pcm_hardware acp_st_pcm_hardware_capture = { 1009c7d6fabSVijendar Mukunda .info = SNDRV_PCM_INFO_INTERLEAVED | 1019c7d6fabSVijendar Mukunda SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP | 1029c7d6fabSVijendar Mukunda SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH | 1039c7d6fabSVijendar Mukunda SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME, 1049c7d6fabSVijendar Mukunda .formats = SNDRV_PCM_FMTBIT_S16_LE | 1059c7d6fabSVijendar Mukunda SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, 1069c7d6fabSVijendar Mukunda .channels_min = 1, 1079c7d6fabSVijendar Mukunda .channels_max = 2, 1089c7d6fabSVijendar Mukunda .rates = SNDRV_PCM_RATE_8000_48000, 1099c7d6fabSVijendar Mukunda .rate_min = 8000, 1109c7d6fabSVijendar Mukunda .rate_max = 48000, 1119c7d6fabSVijendar Mukunda .buffer_bytes_max = ST_MAX_BUFFER, 1129c7d6fabSVijendar Mukunda .period_bytes_min = CAPTURE_MIN_PERIOD_SIZE, 1139c7d6fabSVijendar Mukunda .period_bytes_max = ST_CAPTURE_MAX_PERIOD_SIZE, 1149c7d6fabSVijendar Mukunda .periods_min = CAPTURE_MIN_NUM_PERIODS, 1159c7d6fabSVijendar Mukunda .periods_max = CAPTURE_MAX_NUM_PERIODS, 1169c7d6fabSVijendar Mukunda }; 1179c7d6fabSVijendar Mukunda 1187c31335aSMaruthi Srinivas Bayyavarapu static u32 acp_reg_read(void __iomem *acp_mmio, u32 reg) 1197c31335aSMaruthi Srinivas Bayyavarapu { 1207c31335aSMaruthi Srinivas Bayyavarapu return readl(acp_mmio + (reg * 4)); 1217c31335aSMaruthi Srinivas Bayyavarapu } 1227c31335aSMaruthi Srinivas Bayyavarapu 1237c31335aSMaruthi Srinivas Bayyavarapu static void acp_reg_write(u32 val, void __iomem *acp_mmio, u32 reg) 1247c31335aSMaruthi Srinivas Bayyavarapu { 1257c31335aSMaruthi Srinivas Bayyavarapu writel(val, acp_mmio + (reg * 4)); 1267c31335aSMaruthi Srinivas Bayyavarapu } 1277c31335aSMaruthi Srinivas Bayyavarapu 12813838c11SMukunda, Vijendar /* 12913838c11SMukunda, Vijendar * Configure a given dma channel parameters - enable/disable, 1307c31335aSMaruthi Srinivas Bayyavarapu * number of descriptors, priority 1317c31335aSMaruthi Srinivas Bayyavarapu */ 1327c31335aSMaruthi Srinivas Bayyavarapu static void config_acp_dma_channel(void __iomem *acp_mmio, u8 ch_num, 1337c31335aSMaruthi Srinivas Bayyavarapu u16 dscr_strt_idx, u16 num_dscrs, 1347c31335aSMaruthi Srinivas Bayyavarapu enum acp_dma_priority_level priority_level) 1357c31335aSMaruthi Srinivas Bayyavarapu { 1367c31335aSMaruthi Srinivas Bayyavarapu u32 dma_ctrl; 1377c31335aSMaruthi Srinivas Bayyavarapu 1387c31335aSMaruthi Srinivas Bayyavarapu /* disable the channel run field */ 1397c31335aSMaruthi Srinivas Bayyavarapu dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 1407c31335aSMaruthi Srinivas Bayyavarapu dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRun_MASK; 1417c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 1427c31335aSMaruthi Srinivas Bayyavarapu 1437c31335aSMaruthi Srinivas Bayyavarapu /* program a DMA channel with first descriptor to be processed. */ 1447c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write((ACP_DMA_DSCR_STRT_IDX_0__DMAChDscrStrtIdx_MASK 1457c31335aSMaruthi Srinivas Bayyavarapu & dscr_strt_idx), 1467c31335aSMaruthi Srinivas Bayyavarapu acp_mmio, mmACP_DMA_DSCR_STRT_IDX_0 + ch_num); 1477c31335aSMaruthi Srinivas Bayyavarapu 14813838c11SMukunda, Vijendar /* 14913838c11SMukunda, Vijendar * program a DMA channel with the number of descriptors to be 1507c31335aSMaruthi Srinivas Bayyavarapu * processed in the transfer 1517c31335aSMaruthi Srinivas Bayyavarapu */ 1527c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(ACP_DMA_DSCR_CNT_0__DMAChDscrCnt_MASK & num_dscrs, 1537c31335aSMaruthi Srinivas Bayyavarapu acp_mmio, mmACP_DMA_DSCR_CNT_0 + ch_num); 1547c31335aSMaruthi Srinivas Bayyavarapu 1557c31335aSMaruthi Srinivas Bayyavarapu /* set DMA channel priority */ 1567c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(priority_level, acp_mmio, mmACP_DMA_PRIO_0 + ch_num); 1577c31335aSMaruthi Srinivas Bayyavarapu } 1587c31335aSMaruthi Srinivas Bayyavarapu 159f7c4fe9cSGu Shengxian /* Initialize a dma descriptor in SRAM based on descriptor information passed */ 1607c31335aSMaruthi Srinivas Bayyavarapu static void config_dma_descriptor_in_sram(void __iomem *acp_mmio, 1617c31335aSMaruthi Srinivas Bayyavarapu u16 descr_idx, 1627c31335aSMaruthi Srinivas Bayyavarapu acp_dma_dscr_transfer_t *descr_info) 1637c31335aSMaruthi Srinivas Bayyavarapu { 1647c31335aSMaruthi Srinivas Bayyavarapu u32 sram_offset; 1657c31335aSMaruthi Srinivas Bayyavarapu 1667c31335aSMaruthi Srinivas Bayyavarapu sram_offset = (descr_idx * sizeof(acp_dma_dscr_transfer_t)); 1677c31335aSMaruthi Srinivas Bayyavarapu 1687c31335aSMaruthi Srinivas Bayyavarapu /* program the source base address. */ 1697c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(sram_offset, acp_mmio, mmACP_SRBM_Targ_Idx_Addr); 1707c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(descr_info->src, acp_mmio, mmACP_SRBM_Targ_Idx_Data); 1717c31335aSMaruthi Srinivas Bayyavarapu /* program the destination base address. */ 1727c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(sram_offset + 4, acp_mmio, mmACP_SRBM_Targ_Idx_Addr); 1737c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(descr_info->dest, acp_mmio, mmACP_SRBM_Targ_Idx_Data); 1747c31335aSMaruthi Srinivas Bayyavarapu 1757c31335aSMaruthi Srinivas Bayyavarapu /* program the number of bytes to be transferred for this descriptor. */ 1767c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(sram_offset + 8, acp_mmio, mmACP_SRBM_Targ_Idx_Addr); 1777c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(descr_info->xfer_val, acp_mmio, mmACP_SRBM_Targ_Idx_Data); 1787c31335aSMaruthi Srinivas Bayyavarapu } 1797c31335aSMaruthi Srinivas Bayyavarapu 1802a665dbaSAkshu Agrawal static void pre_config_reset(void __iomem *acp_mmio, u16 ch_num) 1812a665dbaSAkshu Agrawal { 1822a665dbaSAkshu Agrawal u32 dma_ctrl; 1832a665dbaSAkshu Agrawal int ret; 1842a665dbaSAkshu Agrawal 1852a665dbaSAkshu Agrawal /* clear the reset bit */ 1862a665dbaSAkshu Agrawal dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 1872a665dbaSAkshu Agrawal dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRst_MASK; 1882a665dbaSAkshu Agrawal acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 1892a665dbaSAkshu Agrawal /* check the reset bit before programming configuration registers */ 1902a665dbaSAkshu Agrawal ret = readl_poll_timeout(acp_mmio + ((mmACP_DMA_CNTL_0 + ch_num) * 4), 1912a665dbaSAkshu Agrawal dma_ctrl, 1922a665dbaSAkshu Agrawal !(dma_ctrl & ACP_DMA_CNTL_0__DMAChRst_MASK), 1932a665dbaSAkshu Agrawal 100, ACP_DMA_RESET_TIME); 1942a665dbaSAkshu Agrawal if (ret < 0) 1952a665dbaSAkshu Agrawal pr_err("Failed to clear reset of channel : %d\n", ch_num); 1962a665dbaSAkshu Agrawal } 1972a665dbaSAkshu Agrawal 19813838c11SMukunda, Vijendar /* 19913838c11SMukunda, Vijendar * Initialize the DMA descriptor information for transfer between 2007c31335aSMaruthi Srinivas Bayyavarapu * system memory <-> ACP SRAM 2017c31335aSMaruthi Srinivas Bayyavarapu */ 2027c31335aSMaruthi Srinivas Bayyavarapu static void set_acp_sysmem_dma_descriptors(void __iomem *acp_mmio, 20313838c11SMukunda, Vijendar u32 size, int direction, 20413838c11SMukunda, Vijendar u32 pte_offset, u16 ch, 20513838c11SMukunda, Vijendar u32 sram_bank, u16 dma_dscr_idx, 20613838c11SMukunda, Vijendar u32 asic_type) 2077c31335aSMaruthi Srinivas Bayyavarapu { 2087c31335aSMaruthi Srinivas Bayyavarapu u16 i; 2097c31335aSMaruthi Srinivas Bayyavarapu acp_dma_dscr_transfer_t dmadscr[NUM_DSCRS_PER_CHANNEL]; 2107c31335aSMaruthi Srinivas Bayyavarapu 2117c31335aSMaruthi Srinivas Bayyavarapu for (i = 0; i < NUM_DSCRS_PER_CHANNEL; i++) { 2127c31335aSMaruthi Srinivas Bayyavarapu dmadscr[i].xfer_val = 0; 2137c31335aSMaruthi Srinivas Bayyavarapu if (direction == SNDRV_PCM_STREAM_PLAYBACK) { 2144376a86cSMukunda, Vijendar dma_dscr_idx = dma_dscr_idx + i; 2154376a86cSMukunda, Vijendar dmadscr[i].dest = sram_bank + (i * (size / 2)); 2167c31335aSMaruthi Srinivas Bayyavarapu dmadscr[i].src = ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS 2177c31335aSMaruthi Srinivas Bayyavarapu + (pte_offset * SZ_4K) + (i * (size / 2)); 218aac89748SVijendar Mukunda switch (asic_type) { 219aac89748SVijendar Mukunda case CHIP_STONEY: 220aac89748SVijendar Mukunda dmadscr[i].xfer_val |= 22113838c11SMukunda, Vijendar (ACP_DMA_ATTR_DAGB_GARLIC_TO_SHAREDMEM << 16) | 222aac89748SVijendar Mukunda (size / 2); 223aac89748SVijendar Mukunda break; 224aac89748SVijendar Mukunda default: 2257c31335aSMaruthi Srinivas Bayyavarapu dmadscr[i].xfer_val |= 22613838c11SMukunda, Vijendar (ACP_DMA_ATTR_DAGB_ONION_TO_SHAREDMEM << 16) | 2277c31335aSMaruthi Srinivas Bayyavarapu (size / 2); 228aac89748SVijendar Mukunda } 2297c31335aSMaruthi Srinivas Bayyavarapu } else { 2304376a86cSMukunda, Vijendar dma_dscr_idx = dma_dscr_idx + i; 2314376a86cSMukunda, Vijendar dmadscr[i].src = sram_bank + (i * (size / 2)); 232aac89748SVijendar Mukunda dmadscr[i].dest = 233aac89748SVijendar Mukunda ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS + 234aac89748SVijendar Mukunda (pte_offset * SZ_4K) + (i * (size / 2)); 2354376a86cSMukunda, Vijendar switch (asic_type) { 2364376a86cSMukunda, Vijendar case CHIP_STONEY: 237aac89748SVijendar Mukunda dmadscr[i].xfer_val |= 23813838c11SMukunda, Vijendar (ACP_DMA_ATTR_SHARED_MEM_TO_DAGB_GARLIC << 16) | 239aac89748SVijendar Mukunda (size / 2); 240aac89748SVijendar Mukunda break; 241aac89748SVijendar Mukunda default: 2427c31335aSMaruthi Srinivas Bayyavarapu dmadscr[i].xfer_val |= 24313838c11SMukunda, Vijendar (ACP_DMA_ATTR_SHAREDMEM_TO_DAGB_ONION << 16) | 2447c31335aSMaruthi Srinivas Bayyavarapu (size / 2); 2457c31335aSMaruthi Srinivas Bayyavarapu } 246aac89748SVijendar Mukunda } 2477c31335aSMaruthi Srinivas Bayyavarapu config_dma_descriptor_in_sram(acp_mmio, dma_dscr_idx, 2487c31335aSMaruthi Srinivas Bayyavarapu &dmadscr[i]); 2497c31335aSMaruthi Srinivas Bayyavarapu } 2502a665dbaSAkshu Agrawal pre_config_reset(acp_mmio, ch); 2514376a86cSMukunda, Vijendar config_acp_dma_channel(acp_mmio, ch, 2524376a86cSMukunda, Vijendar dma_dscr_idx - 1, 2537c31335aSMaruthi Srinivas Bayyavarapu NUM_DSCRS_PER_CHANNEL, 2547c31335aSMaruthi Srinivas Bayyavarapu ACP_DMA_PRIORITY_LEVEL_NORMAL); 2557c31335aSMaruthi Srinivas Bayyavarapu } 2567c31335aSMaruthi Srinivas Bayyavarapu 25713838c11SMukunda, Vijendar /* 25813838c11SMukunda, Vijendar * Initialize the DMA descriptor information for transfer between 2597c31335aSMaruthi Srinivas Bayyavarapu * ACP SRAM <-> I2S 2607c31335aSMaruthi Srinivas Bayyavarapu */ 2614376a86cSMukunda, Vijendar static void set_acp_to_i2s_dma_descriptors(void __iomem *acp_mmio, u32 size, 2624376a86cSMukunda, Vijendar int direction, u32 sram_bank, 2634376a86cSMukunda, Vijendar u16 destination, u16 ch, 2644376a86cSMukunda, Vijendar u16 dma_dscr_idx, u32 asic_type) 2657c31335aSMaruthi Srinivas Bayyavarapu { 2667c31335aSMaruthi Srinivas Bayyavarapu u16 i; 2677c31335aSMaruthi Srinivas Bayyavarapu acp_dma_dscr_transfer_t dmadscr[NUM_DSCRS_PER_CHANNEL]; 2687c31335aSMaruthi Srinivas Bayyavarapu 2697c31335aSMaruthi Srinivas Bayyavarapu for (i = 0; i < NUM_DSCRS_PER_CHANNEL; i++) { 2707c31335aSMaruthi Srinivas Bayyavarapu dmadscr[i].xfer_val = 0; 2717c31335aSMaruthi Srinivas Bayyavarapu if (direction == SNDRV_PCM_STREAM_PLAYBACK) { 2724376a86cSMukunda, Vijendar dma_dscr_idx = dma_dscr_idx + i; 2734376a86cSMukunda, Vijendar dmadscr[i].src = sram_bank + (i * (size / 2)); 2747c31335aSMaruthi Srinivas Bayyavarapu /* dmadscr[i].dest is unused by hardware. */ 2757c31335aSMaruthi Srinivas Bayyavarapu dmadscr[i].dest = 0; 2764376a86cSMukunda, Vijendar dmadscr[i].xfer_val |= BIT(22) | (destination << 16) | 2777c31335aSMaruthi Srinivas Bayyavarapu (size / 2); 2787c31335aSMaruthi Srinivas Bayyavarapu } else { 2794376a86cSMukunda, Vijendar dma_dscr_idx = dma_dscr_idx + i; 2807c31335aSMaruthi Srinivas Bayyavarapu /* dmadscr[i].src is unused by hardware. */ 2817c31335aSMaruthi Srinivas Bayyavarapu dmadscr[i].src = 0; 282aac89748SVijendar Mukunda dmadscr[i].dest = 2834376a86cSMukunda, Vijendar sram_bank + (i * (size / 2)); 2847c31335aSMaruthi Srinivas Bayyavarapu dmadscr[i].xfer_val |= BIT(22) | 2854376a86cSMukunda, Vijendar (destination << 16) | (size / 2); 2867c31335aSMaruthi Srinivas Bayyavarapu } 2877c31335aSMaruthi Srinivas Bayyavarapu config_dma_descriptor_in_sram(acp_mmio, dma_dscr_idx, 2887c31335aSMaruthi Srinivas Bayyavarapu &dmadscr[i]); 2897c31335aSMaruthi Srinivas Bayyavarapu } 2902a665dbaSAkshu Agrawal pre_config_reset(acp_mmio, ch); 291f7c4fe9cSGu Shengxian /* Configure the DMA channel with the above descriptor */ 2924376a86cSMukunda, Vijendar config_acp_dma_channel(acp_mmio, ch, dma_dscr_idx - 1, 2937c31335aSMaruthi Srinivas Bayyavarapu NUM_DSCRS_PER_CHANNEL, 2947c31335aSMaruthi Srinivas Bayyavarapu ACP_DMA_PRIORITY_LEVEL_NORMAL); 2957c31335aSMaruthi Srinivas Bayyavarapu } 2967c31335aSMaruthi Srinivas Bayyavarapu 2977c31335aSMaruthi Srinivas Bayyavarapu /* Create page table entries in ACP SRAM for the allocated memory */ 298d6d08273SYu Zhao static void acp_pte_config(void __iomem *acp_mmio, dma_addr_t addr, 2997c31335aSMaruthi Srinivas Bayyavarapu u16 num_of_pages, u32 pte_offset) 3007c31335aSMaruthi Srinivas Bayyavarapu { 3017c31335aSMaruthi Srinivas Bayyavarapu u16 page_idx; 3027c31335aSMaruthi Srinivas Bayyavarapu u32 low; 3037c31335aSMaruthi Srinivas Bayyavarapu u32 high; 3047c31335aSMaruthi Srinivas Bayyavarapu u32 offset; 3057c31335aSMaruthi Srinivas Bayyavarapu 3067c31335aSMaruthi Srinivas Bayyavarapu offset = ACP_DAGB_GRP_SRBM_SRAM_BASE_OFFSET + (pte_offset * 8); 3077c31335aSMaruthi Srinivas Bayyavarapu for (page_idx = 0; page_idx < (num_of_pages); page_idx++) { 3087c31335aSMaruthi Srinivas Bayyavarapu /* Load the low address of page int ACP SRAM through SRBM */ 3097c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write((offset + (page_idx * 8)), 3107c31335aSMaruthi Srinivas Bayyavarapu acp_mmio, mmACP_SRBM_Targ_Idx_Addr); 3117c31335aSMaruthi Srinivas Bayyavarapu 3127c31335aSMaruthi Srinivas Bayyavarapu low = lower_32_bits(addr); 3137c31335aSMaruthi Srinivas Bayyavarapu high = upper_32_bits(addr); 3147c31335aSMaruthi Srinivas Bayyavarapu 3157c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(low, acp_mmio, mmACP_SRBM_Targ_Idx_Data); 3167c31335aSMaruthi Srinivas Bayyavarapu 3177c31335aSMaruthi Srinivas Bayyavarapu /* Load the High address of page int ACP SRAM through SRBM */ 3187c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write((offset + (page_idx * 8) + 4), 3197c31335aSMaruthi Srinivas Bayyavarapu acp_mmio, mmACP_SRBM_Targ_Idx_Addr); 3207c31335aSMaruthi Srinivas Bayyavarapu 3217c31335aSMaruthi Srinivas Bayyavarapu /* page enable in ACP */ 3227c31335aSMaruthi Srinivas Bayyavarapu high |= BIT(31); 3237c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(high, acp_mmio, mmACP_SRBM_Targ_Idx_Data); 3247c31335aSMaruthi Srinivas Bayyavarapu 325f7c4fe9cSGu Shengxian /* Move to next physically contiguous page */ 326d6d08273SYu Zhao addr += PAGE_SIZE; 3277c31335aSMaruthi Srinivas Bayyavarapu } 3287c31335aSMaruthi Srinivas Bayyavarapu } 3297c31335aSMaruthi Srinivas Bayyavarapu 3307c31335aSMaruthi Srinivas Bayyavarapu static void config_acp_dma(void __iomem *acp_mmio, 3318349b7f5SMukunda, Vijendar struct audio_substream_data *rtd, 332aac89748SVijendar Mukunda u32 asic_type) 3337c31335aSMaruthi Srinivas Bayyavarapu { 334fa9d2f17SAgrawal, Akshu u16 ch_acp_sysmem, ch_acp_i2s; 335fa9d2f17SAgrawal, Akshu 336d6d08273SYu Zhao acp_pte_config(acp_mmio, rtd->dma_addr, rtd->num_of_pages, 337e188c525SMukunda, Vijendar rtd->pte_offset); 338fa9d2f17SAgrawal, Akshu 339fa9d2f17SAgrawal, Akshu if (rtd->direction == SNDRV_PCM_STREAM_PLAYBACK) { 340fa9d2f17SAgrawal, Akshu ch_acp_sysmem = rtd->ch1; 341fa9d2f17SAgrawal, Akshu ch_acp_i2s = rtd->ch2; 342fa9d2f17SAgrawal, Akshu } else { 343fa9d2f17SAgrawal, Akshu ch_acp_i2s = rtd->ch1; 344fa9d2f17SAgrawal, Akshu ch_acp_sysmem = rtd->ch2; 345fa9d2f17SAgrawal, Akshu } 3467c31335aSMaruthi Srinivas Bayyavarapu /* Configure System memory <-> ACP SRAM DMA descriptors */ 3478349b7f5SMukunda, Vijendar set_acp_sysmem_dma_descriptors(acp_mmio, rtd->size, 348e188c525SMukunda, Vijendar rtd->direction, rtd->pte_offset, 349fa9d2f17SAgrawal, Akshu ch_acp_sysmem, rtd->sram_bank, 3508769bb55SVijendar Mukunda rtd->dma_dscr_idx_1, asic_type); 3517c31335aSMaruthi Srinivas Bayyavarapu /* Configure ACP SRAM <-> I2S DMA descriptors */ 3528349b7f5SMukunda, Vijendar set_acp_to_i2s_dma_descriptors(acp_mmio, rtd->size, 35318e8a40dSMukunda, Vijendar rtd->direction, rtd->sram_bank, 354fa9d2f17SAgrawal, Akshu rtd->destination, ch_acp_i2s, 3558769bb55SVijendar Mukunda rtd->dma_dscr_idx_2, asic_type); 3567c31335aSMaruthi Srinivas Bayyavarapu } 3577c31335aSMaruthi Srinivas Bayyavarapu 3582718c89aSAkshu Agrawal static void acp_dma_cap_channel_enable(void __iomem *acp_mmio, 3592718c89aSAkshu Agrawal u16 cap_channel) 3602718c89aSAkshu Agrawal { 3612718c89aSAkshu Agrawal u32 val, ch_reg, imr_reg, res_reg; 3622718c89aSAkshu Agrawal 3632718c89aSAkshu Agrawal switch (cap_channel) { 3642718c89aSAkshu Agrawal case CAP_CHANNEL1: 3652718c89aSAkshu Agrawal ch_reg = mmACP_I2SMICSP_RER1; 3662718c89aSAkshu Agrawal res_reg = mmACP_I2SMICSP_RCR1; 3672718c89aSAkshu Agrawal imr_reg = mmACP_I2SMICSP_IMR1; 3682718c89aSAkshu Agrawal break; 3692718c89aSAkshu Agrawal case CAP_CHANNEL0: 3702718c89aSAkshu Agrawal default: 3712718c89aSAkshu Agrawal ch_reg = mmACP_I2SMICSP_RER0; 3722718c89aSAkshu Agrawal res_reg = mmACP_I2SMICSP_RCR0; 3732718c89aSAkshu Agrawal imr_reg = mmACP_I2SMICSP_IMR0; 3742718c89aSAkshu Agrawal break; 3752718c89aSAkshu Agrawal } 3762718c89aSAkshu Agrawal val = acp_reg_read(acp_mmio, 3772718c89aSAkshu Agrawal mmACP_I2S_16BIT_RESOLUTION_EN); 3782718c89aSAkshu Agrawal if (val & ACP_I2S_MIC_16BIT_RESOLUTION_EN) { 3792718c89aSAkshu Agrawal acp_reg_write(0x0, acp_mmio, ch_reg); 3802718c89aSAkshu Agrawal /* Set 16bit resolution on capture */ 3812718c89aSAkshu Agrawal acp_reg_write(0x2, acp_mmio, res_reg); 3822718c89aSAkshu Agrawal } 3832718c89aSAkshu Agrawal val = acp_reg_read(acp_mmio, imr_reg); 3842718c89aSAkshu Agrawal val &= ~ACP_I2SMICSP_IMR1__I2SMICSP_RXDAM_MASK; 3852718c89aSAkshu Agrawal val &= ~ACP_I2SMICSP_IMR1__I2SMICSP_RXFOM_MASK; 3862718c89aSAkshu Agrawal acp_reg_write(val, acp_mmio, imr_reg); 3872718c89aSAkshu Agrawal acp_reg_write(0x1, acp_mmio, ch_reg); 3882718c89aSAkshu Agrawal } 3892718c89aSAkshu Agrawal 3902718c89aSAkshu Agrawal static void acp_dma_cap_channel_disable(void __iomem *acp_mmio, 3912718c89aSAkshu Agrawal u16 cap_channel) 3922718c89aSAkshu Agrawal { 3932718c89aSAkshu Agrawal u32 val, ch_reg, imr_reg; 3942718c89aSAkshu Agrawal 3952718c89aSAkshu Agrawal switch (cap_channel) { 3962718c89aSAkshu Agrawal case CAP_CHANNEL1: 3972718c89aSAkshu Agrawal imr_reg = mmACP_I2SMICSP_IMR1; 3982718c89aSAkshu Agrawal ch_reg = mmACP_I2SMICSP_RER1; 3992718c89aSAkshu Agrawal break; 4002718c89aSAkshu Agrawal case CAP_CHANNEL0: 4012718c89aSAkshu Agrawal default: 4022718c89aSAkshu Agrawal imr_reg = mmACP_I2SMICSP_IMR0; 4032718c89aSAkshu Agrawal ch_reg = mmACP_I2SMICSP_RER0; 4042718c89aSAkshu Agrawal break; 4052718c89aSAkshu Agrawal } 4062718c89aSAkshu Agrawal val = acp_reg_read(acp_mmio, imr_reg); 4072718c89aSAkshu Agrawal val |= ACP_I2SMICSP_IMR1__I2SMICSP_RXDAM_MASK; 4082718c89aSAkshu Agrawal val |= ACP_I2SMICSP_IMR1__I2SMICSP_RXFOM_MASK; 4092718c89aSAkshu Agrawal acp_reg_write(val, acp_mmio, imr_reg); 4102718c89aSAkshu Agrawal acp_reg_write(0x0, acp_mmio, ch_reg); 4112718c89aSAkshu Agrawal } 4122718c89aSAkshu Agrawal 4137c31335aSMaruthi Srinivas Bayyavarapu /* Start a given DMA channel transfer */ 414bbdb7012SAkshu Agrawal static void acp_dma_start(void __iomem *acp_mmio, u16 ch_num, bool is_circular) 4157c31335aSMaruthi Srinivas Bayyavarapu { 4167c31335aSMaruthi Srinivas Bayyavarapu u32 dma_ctrl; 4177c31335aSMaruthi Srinivas Bayyavarapu 4187c31335aSMaruthi Srinivas Bayyavarapu /* read the dma control register and disable the channel run field */ 4197c31335aSMaruthi Srinivas Bayyavarapu dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 4207c31335aSMaruthi Srinivas Bayyavarapu 4217c31335aSMaruthi Srinivas Bayyavarapu /* Invalidating the DAGB cache */ 4227c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(1, acp_mmio, mmACP_DAGB_ATU_CTRL); 4237c31335aSMaruthi Srinivas Bayyavarapu 42413838c11SMukunda, Vijendar /* 42513838c11SMukunda, Vijendar * configure the DMA channel and start the DMA transfer 4267c31335aSMaruthi Srinivas Bayyavarapu * set dmachrun bit to start the transfer and enable the 4277c31335aSMaruthi Srinivas Bayyavarapu * interrupt on completion of the dma transfer 4287c31335aSMaruthi Srinivas Bayyavarapu */ 4297c31335aSMaruthi Srinivas Bayyavarapu dma_ctrl |= ACP_DMA_CNTL_0__DMAChRun_MASK; 4307c31335aSMaruthi Srinivas Bayyavarapu 4317c31335aSMaruthi Srinivas Bayyavarapu switch (ch_num) { 4327c31335aSMaruthi Srinivas Bayyavarapu case ACP_TO_I2S_DMA_CH_NUM: 43319e023e3SAgrawal, Akshu case I2S_TO_ACP_DMA_CH_NUM: 434ccfbb4f5SMukunda, Vijendar case ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM: 43519e023e3SAgrawal, Akshu case I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM: 4363eb8440dSVijendar Mukunda case ACP_TO_I2S_DMA_MICSP_INSTANCE_CH_NUM: 4377c31335aSMaruthi Srinivas Bayyavarapu dma_ctrl |= ACP_DMA_CNTL_0__DMAChIOCEn_MASK; 4387c31335aSMaruthi Srinivas Bayyavarapu break; 4397c31335aSMaruthi Srinivas Bayyavarapu default: 4407c31335aSMaruthi Srinivas Bayyavarapu dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChIOCEn_MASK; 4417c31335aSMaruthi Srinivas Bayyavarapu break; 4427c31335aSMaruthi Srinivas Bayyavarapu } 4437c31335aSMaruthi Srinivas Bayyavarapu 444bbdb7012SAkshu Agrawal /* enable for ACP to SRAM DMA channel */ 445bbdb7012SAkshu Agrawal if (is_circular == true) 4467c31335aSMaruthi Srinivas Bayyavarapu dma_ctrl |= ACP_DMA_CNTL_0__Circular_DMA_En_MASK; 447bbdb7012SAkshu Agrawal else 448bbdb7012SAkshu Agrawal dma_ctrl &= ~ACP_DMA_CNTL_0__Circular_DMA_En_MASK; 4497c31335aSMaruthi Srinivas Bayyavarapu 4507c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 4517c31335aSMaruthi Srinivas Bayyavarapu } 4527c31335aSMaruthi Srinivas Bayyavarapu 4537c31335aSMaruthi Srinivas Bayyavarapu /* Stop a given DMA channel transfer */ 4547c31335aSMaruthi Srinivas Bayyavarapu static int acp_dma_stop(void __iomem *acp_mmio, u8 ch_num) 4557c31335aSMaruthi Srinivas Bayyavarapu { 4567c31335aSMaruthi Srinivas Bayyavarapu u32 dma_ctrl; 4577c31335aSMaruthi Srinivas Bayyavarapu u32 dma_ch_sts; 4587c31335aSMaruthi Srinivas Bayyavarapu u32 count = ACP_DMA_RESET_TIME; 4597c31335aSMaruthi Srinivas Bayyavarapu 4607c31335aSMaruthi Srinivas Bayyavarapu dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 4617c31335aSMaruthi Srinivas Bayyavarapu 46213838c11SMukunda, Vijendar /* 46313838c11SMukunda, Vijendar * clear the dma control register fields before writing zero 4647c31335aSMaruthi Srinivas Bayyavarapu * in reset bit 4657c31335aSMaruthi Srinivas Bayyavarapu */ 4667c31335aSMaruthi Srinivas Bayyavarapu dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRun_MASK; 4677c31335aSMaruthi Srinivas Bayyavarapu dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChIOCEn_MASK; 4687c31335aSMaruthi Srinivas Bayyavarapu 4697c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 4707c31335aSMaruthi Srinivas Bayyavarapu dma_ch_sts = acp_reg_read(acp_mmio, mmACP_DMA_CH_STS); 4717c31335aSMaruthi Srinivas Bayyavarapu 4727c31335aSMaruthi Srinivas Bayyavarapu if (dma_ch_sts & BIT(ch_num)) { 47313838c11SMukunda, Vijendar /* 47413838c11SMukunda, Vijendar * set the reset bit for this channel to stop the dma 4757c31335aSMaruthi Srinivas Bayyavarapu * transfer 4767c31335aSMaruthi Srinivas Bayyavarapu */ 4777c31335aSMaruthi Srinivas Bayyavarapu dma_ctrl |= ACP_DMA_CNTL_0__DMAChRst_MASK; 4787c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 4797c31335aSMaruthi Srinivas Bayyavarapu } 4807c31335aSMaruthi Srinivas Bayyavarapu 4817c31335aSMaruthi Srinivas Bayyavarapu /* check the channel status bit for some time and return the status */ 4827c31335aSMaruthi Srinivas Bayyavarapu while (true) { 4837c31335aSMaruthi Srinivas Bayyavarapu dma_ch_sts = acp_reg_read(acp_mmio, mmACP_DMA_CH_STS); 4847c31335aSMaruthi Srinivas Bayyavarapu if (!(dma_ch_sts & BIT(ch_num))) { 48513838c11SMukunda, Vijendar /* 48613838c11SMukunda, Vijendar * clear the reset flag after successfully stopping 4877c31335aSMaruthi Srinivas Bayyavarapu * the dma transfer and break from the loop 4887c31335aSMaruthi Srinivas Bayyavarapu */ 4897c31335aSMaruthi Srinivas Bayyavarapu dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRst_MASK; 4907c31335aSMaruthi Srinivas Bayyavarapu 4917c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 4927c31335aSMaruthi Srinivas Bayyavarapu + ch_num); 4937c31335aSMaruthi Srinivas Bayyavarapu break; 4947c31335aSMaruthi Srinivas Bayyavarapu } 4957c31335aSMaruthi Srinivas Bayyavarapu if (--count == 0) { 4967c31335aSMaruthi Srinivas Bayyavarapu pr_err("Failed to stop ACP DMA channel : %d\n", ch_num); 4977c31335aSMaruthi Srinivas Bayyavarapu return -ETIMEDOUT; 4987c31335aSMaruthi Srinivas Bayyavarapu } 4997c31335aSMaruthi Srinivas Bayyavarapu udelay(100); 5007c31335aSMaruthi Srinivas Bayyavarapu } 5017c31335aSMaruthi Srinivas Bayyavarapu return 0; 5027c31335aSMaruthi Srinivas Bayyavarapu } 5037c31335aSMaruthi Srinivas Bayyavarapu 504c36d9b3fSMaruthi Srinivas Bayyavarapu static void acp_set_sram_bank_state(void __iomem *acp_mmio, u16 bank, 505c36d9b3fSMaruthi Srinivas Bayyavarapu bool power_on) 506c36d9b3fSMaruthi Srinivas Bayyavarapu { 507c36d9b3fSMaruthi Srinivas Bayyavarapu u32 val, req_reg, sts_reg, sts_reg_mask; 508c36d9b3fSMaruthi Srinivas Bayyavarapu u32 loops = 1000; 509c36d9b3fSMaruthi Srinivas Bayyavarapu 510c36d9b3fSMaruthi Srinivas Bayyavarapu if (bank < 32) { 511c36d9b3fSMaruthi Srinivas Bayyavarapu req_reg = mmACP_MEM_SHUT_DOWN_REQ_LO; 512c36d9b3fSMaruthi Srinivas Bayyavarapu sts_reg = mmACP_MEM_SHUT_DOWN_STS_LO; 513c36d9b3fSMaruthi Srinivas Bayyavarapu sts_reg_mask = 0xFFFFFFFF; 514c36d9b3fSMaruthi Srinivas Bayyavarapu 515c36d9b3fSMaruthi Srinivas Bayyavarapu } else { 516c36d9b3fSMaruthi Srinivas Bayyavarapu bank -= 32; 517c36d9b3fSMaruthi Srinivas Bayyavarapu req_reg = mmACP_MEM_SHUT_DOWN_REQ_HI; 518c36d9b3fSMaruthi Srinivas Bayyavarapu sts_reg = mmACP_MEM_SHUT_DOWN_STS_HI; 519c36d9b3fSMaruthi Srinivas Bayyavarapu sts_reg_mask = 0x0000FFFF; 520c36d9b3fSMaruthi Srinivas Bayyavarapu } 521c36d9b3fSMaruthi Srinivas Bayyavarapu 522c36d9b3fSMaruthi Srinivas Bayyavarapu val = acp_reg_read(acp_mmio, req_reg); 523c36d9b3fSMaruthi Srinivas Bayyavarapu if (val & (1 << bank)) { 524c36d9b3fSMaruthi Srinivas Bayyavarapu /* bank is in off state */ 525c36d9b3fSMaruthi Srinivas Bayyavarapu if (power_on == true) 526c36d9b3fSMaruthi Srinivas Bayyavarapu /* request to on */ 527c36d9b3fSMaruthi Srinivas Bayyavarapu val &= ~(1 << bank); 528c36d9b3fSMaruthi Srinivas Bayyavarapu else 529c36d9b3fSMaruthi Srinivas Bayyavarapu /* request to off */ 530c36d9b3fSMaruthi Srinivas Bayyavarapu return; 531c36d9b3fSMaruthi Srinivas Bayyavarapu } else { 532c36d9b3fSMaruthi Srinivas Bayyavarapu /* bank is in on state */ 533c36d9b3fSMaruthi Srinivas Bayyavarapu if (power_on == false) 534c36d9b3fSMaruthi Srinivas Bayyavarapu /* request to off */ 535c36d9b3fSMaruthi Srinivas Bayyavarapu val |= 1 << bank; 536c36d9b3fSMaruthi Srinivas Bayyavarapu else 537c36d9b3fSMaruthi Srinivas Bayyavarapu /* request to on */ 538c36d9b3fSMaruthi Srinivas Bayyavarapu return; 539c36d9b3fSMaruthi Srinivas Bayyavarapu } 540c36d9b3fSMaruthi Srinivas Bayyavarapu acp_reg_write(val, acp_mmio, req_reg); 541c36d9b3fSMaruthi Srinivas Bayyavarapu 542c36d9b3fSMaruthi Srinivas Bayyavarapu while (acp_reg_read(acp_mmio, sts_reg) != sts_reg_mask) { 543c36d9b3fSMaruthi Srinivas Bayyavarapu if (!loops--) { 544c36d9b3fSMaruthi Srinivas Bayyavarapu pr_err("ACP SRAM bank %d state change failed\n", bank); 545c36d9b3fSMaruthi Srinivas Bayyavarapu break; 546c36d9b3fSMaruthi Srinivas Bayyavarapu } 547c36d9b3fSMaruthi Srinivas Bayyavarapu cpu_relax(); 548c36d9b3fSMaruthi Srinivas Bayyavarapu } 549c36d9b3fSMaruthi Srinivas Bayyavarapu } 550c36d9b3fSMaruthi Srinivas Bayyavarapu 5517c31335aSMaruthi Srinivas Bayyavarapu /* Initialize and bring ACP hardware to default state. */ 552607b39efSVijendar Mukunda static int acp_init(void __iomem *acp_mmio, u32 asic_type) 5537c31335aSMaruthi Srinivas Bayyavarapu { 554c36d9b3fSMaruthi Srinivas Bayyavarapu u16 bank; 5557c31335aSMaruthi Srinivas Bayyavarapu u32 val, count, sram_pte_offset; 5567c31335aSMaruthi Srinivas Bayyavarapu 5577c31335aSMaruthi Srinivas Bayyavarapu /* Assert Soft reset of ACP */ 5587c31335aSMaruthi Srinivas Bayyavarapu val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET); 5597c31335aSMaruthi Srinivas Bayyavarapu 5607c31335aSMaruthi Srinivas Bayyavarapu val |= ACP_SOFT_RESET__SoftResetAud_MASK; 5617c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET); 5627c31335aSMaruthi Srinivas Bayyavarapu 5637c31335aSMaruthi Srinivas Bayyavarapu count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE; 5647c31335aSMaruthi Srinivas Bayyavarapu while (true) { 5657c31335aSMaruthi Srinivas Bayyavarapu val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET); 5667c31335aSMaruthi Srinivas Bayyavarapu if (ACP_SOFT_RESET__SoftResetAudDone_MASK == 5677c31335aSMaruthi Srinivas Bayyavarapu (val & ACP_SOFT_RESET__SoftResetAudDone_MASK)) 5687c31335aSMaruthi Srinivas Bayyavarapu break; 5697c31335aSMaruthi Srinivas Bayyavarapu if (--count == 0) { 5707c31335aSMaruthi Srinivas Bayyavarapu pr_err("Failed to reset ACP\n"); 5717c31335aSMaruthi Srinivas Bayyavarapu return -ETIMEDOUT; 5727c31335aSMaruthi Srinivas Bayyavarapu } 5737c31335aSMaruthi Srinivas Bayyavarapu udelay(100); 5747c31335aSMaruthi Srinivas Bayyavarapu } 5757c31335aSMaruthi Srinivas Bayyavarapu 5767c31335aSMaruthi Srinivas Bayyavarapu /* Enable clock to ACP and wait until the clock is enabled */ 5777c31335aSMaruthi Srinivas Bayyavarapu val = acp_reg_read(acp_mmio, mmACP_CONTROL); 5787c31335aSMaruthi Srinivas Bayyavarapu val = val | ACP_CONTROL__ClkEn_MASK; 5797c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(val, acp_mmio, mmACP_CONTROL); 5807c31335aSMaruthi Srinivas Bayyavarapu 5817c31335aSMaruthi Srinivas Bayyavarapu count = ACP_CLOCK_EN_TIME_OUT_VALUE; 5827c31335aSMaruthi Srinivas Bayyavarapu 5837c31335aSMaruthi Srinivas Bayyavarapu while (true) { 5847c31335aSMaruthi Srinivas Bayyavarapu val = acp_reg_read(acp_mmio, mmACP_STATUS); 5857c31335aSMaruthi Srinivas Bayyavarapu if (val & (u32)0x1) 5867c31335aSMaruthi Srinivas Bayyavarapu break; 5877c31335aSMaruthi Srinivas Bayyavarapu if (--count == 0) { 5887c31335aSMaruthi Srinivas Bayyavarapu pr_err("Failed to reset ACP\n"); 5897c31335aSMaruthi Srinivas Bayyavarapu return -ETIMEDOUT; 5907c31335aSMaruthi Srinivas Bayyavarapu } 5917c31335aSMaruthi Srinivas Bayyavarapu udelay(100); 5927c31335aSMaruthi Srinivas Bayyavarapu } 5937c31335aSMaruthi Srinivas Bayyavarapu 5947c31335aSMaruthi Srinivas Bayyavarapu /* Deassert the SOFT RESET flags */ 5957c31335aSMaruthi Srinivas Bayyavarapu val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET); 5967c31335aSMaruthi Srinivas Bayyavarapu val &= ~ACP_SOFT_RESET__SoftResetAud_MASK; 5977c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET); 5987c31335aSMaruthi Srinivas Bayyavarapu 599ccfbb4f5SMukunda, Vijendar /* For BT instance change pins from UART to BT */ 60019843302SPierre-Louis Bossart if (!acp_bt_uart_enable) { 601ccfbb4f5SMukunda, Vijendar val = acp_reg_read(acp_mmio, mmACP_BT_UART_PAD_SEL); 602ccfbb4f5SMukunda, Vijendar val |= ACP_BT_UART_PAD_SELECT_MASK; 603ccfbb4f5SMukunda, Vijendar acp_reg_write(val, acp_mmio, mmACP_BT_UART_PAD_SEL); 604ccfbb4f5SMukunda, Vijendar } 605ccfbb4f5SMukunda, Vijendar 606f7c4fe9cSGu Shengxian /* initialize Onion control DAGB register */ 6077c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(ACP_ONION_CNTL_DEFAULT, acp_mmio, 6087c31335aSMaruthi Srinivas Bayyavarapu mmACP_AXI2DAGB_ONION_CNTL); 6097c31335aSMaruthi Srinivas Bayyavarapu 610f7c4fe9cSGu Shengxian /* initialize Garlic control DAGB registers */ 6117c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(ACP_GARLIC_CNTL_DEFAULT, acp_mmio, 6127c31335aSMaruthi Srinivas Bayyavarapu mmACP_AXI2DAGB_GARLIC_CNTL); 6137c31335aSMaruthi Srinivas Bayyavarapu 6147c31335aSMaruthi Srinivas Bayyavarapu sram_pte_offset = ACP_DAGB_GRP_SRAM_BASE_ADDRESS | 6157c31335aSMaruthi Srinivas Bayyavarapu ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBSnoopSel_MASK | 6167c31335aSMaruthi Srinivas Bayyavarapu ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBTargetMemSel_MASK | 6177c31335aSMaruthi Srinivas Bayyavarapu ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBGrpEnable_MASK; 6187c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(sram_pte_offset, acp_mmio, mmACP_DAGB_BASE_ADDR_GRP_1); 6197c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(ACP_PAGE_SIZE_4K_ENABLE, acp_mmio, 6207c31335aSMaruthi Srinivas Bayyavarapu mmACP_DAGB_PAGE_SIZE_GRP_1); 6217c31335aSMaruthi Srinivas Bayyavarapu 6227c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(ACP_SRAM_BASE_ADDRESS, acp_mmio, 6237c31335aSMaruthi Srinivas Bayyavarapu mmACP_DMA_DESC_BASE_ADDR); 6247c31335aSMaruthi Srinivas Bayyavarapu 625f7c4fe9cSGu Shengxian /* Num of descriptors in SRAM 0x4, means 256 descriptors;(64 * 4) */ 6267c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(0x4, acp_mmio, mmACP_DMA_DESC_MAX_NUM_DSCR); 6277c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(ACP_EXTERNAL_INTR_CNTL__DMAIOCMask_MASK, 6287c31335aSMaruthi Srinivas Bayyavarapu acp_mmio, mmACP_EXTERNAL_INTR_CNTL); 6297c31335aSMaruthi Srinivas Bayyavarapu 63013838c11SMukunda, Vijendar /* 63113838c11SMukunda, Vijendar * When ACP_TILE_P1 is turned on, all SRAM banks get turned on. 632c36d9b3fSMaruthi Srinivas Bayyavarapu * Now, turn off all of them. This can't be done in 'poweron' of 633c36d9b3fSMaruthi Srinivas Bayyavarapu * ACP pm domain, as this requires ACP to be initialized. 634607b39efSVijendar Mukunda * For Stoney, Memory gating is disabled,i.e SRAM Banks 635607b39efSVijendar Mukunda * won't be turned off. The default state for SRAM banks is ON. 636607b39efSVijendar Mukunda * Setting SRAM bank state code skipped for STONEY platform. 637c36d9b3fSMaruthi Srinivas Bayyavarapu */ 638607b39efSVijendar Mukunda if (asic_type != CHIP_STONEY) { 639c36d9b3fSMaruthi Srinivas Bayyavarapu for (bank = 1; bank < 48; bank++) 640c36d9b3fSMaruthi Srinivas Bayyavarapu acp_set_sram_bank_state(acp_mmio, bank, false); 641607b39efSVijendar Mukunda } 6427c31335aSMaruthi Srinivas Bayyavarapu return 0; 6437c31335aSMaruthi Srinivas Bayyavarapu } 6447c31335aSMaruthi Srinivas Bayyavarapu 6451cce2000SMasahiro Yamada /* Deinitialize ACP */ 6467c31335aSMaruthi Srinivas Bayyavarapu static int acp_deinit(void __iomem *acp_mmio) 6477c31335aSMaruthi Srinivas Bayyavarapu { 6487c31335aSMaruthi Srinivas Bayyavarapu u32 val; 6497c31335aSMaruthi Srinivas Bayyavarapu u32 count; 6507c31335aSMaruthi Srinivas Bayyavarapu 6517c31335aSMaruthi Srinivas Bayyavarapu /* Assert Soft reset of ACP */ 6527c31335aSMaruthi Srinivas Bayyavarapu val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET); 6537c31335aSMaruthi Srinivas Bayyavarapu 6547c31335aSMaruthi Srinivas Bayyavarapu val |= ACP_SOFT_RESET__SoftResetAud_MASK; 6557c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET); 6567c31335aSMaruthi Srinivas Bayyavarapu 6577c31335aSMaruthi Srinivas Bayyavarapu count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE; 6587c31335aSMaruthi Srinivas Bayyavarapu while (true) { 6597c31335aSMaruthi Srinivas Bayyavarapu val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET); 6607c31335aSMaruthi Srinivas Bayyavarapu if (ACP_SOFT_RESET__SoftResetAudDone_MASK == 6617c31335aSMaruthi Srinivas Bayyavarapu (val & ACP_SOFT_RESET__SoftResetAudDone_MASK)) 6627c31335aSMaruthi Srinivas Bayyavarapu break; 6637c31335aSMaruthi Srinivas Bayyavarapu if (--count == 0) { 6647c31335aSMaruthi Srinivas Bayyavarapu pr_err("Failed to reset ACP\n"); 6657c31335aSMaruthi Srinivas Bayyavarapu return -ETIMEDOUT; 6667c31335aSMaruthi Srinivas Bayyavarapu } 6677c31335aSMaruthi Srinivas Bayyavarapu udelay(100); 6687c31335aSMaruthi Srinivas Bayyavarapu } 66913838c11SMukunda, Vijendar /* Disable ACP clock */ 6707c31335aSMaruthi Srinivas Bayyavarapu val = acp_reg_read(acp_mmio, mmACP_CONTROL); 6717c31335aSMaruthi Srinivas Bayyavarapu val &= ~ACP_CONTROL__ClkEn_MASK; 6727c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(val, acp_mmio, mmACP_CONTROL); 6737c31335aSMaruthi Srinivas Bayyavarapu 6747c31335aSMaruthi Srinivas Bayyavarapu count = ACP_CLOCK_EN_TIME_OUT_VALUE; 6757c31335aSMaruthi Srinivas Bayyavarapu 6767c31335aSMaruthi Srinivas Bayyavarapu while (true) { 6777c31335aSMaruthi Srinivas Bayyavarapu val = acp_reg_read(acp_mmio, mmACP_STATUS); 6787c31335aSMaruthi Srinivas Bayyavarapu if (!(val & (u32)0x1)) 6797c31335aSMaruthi Srinivas Bayyavarapu break; 6807c31335aSMaruthi Srinivas Bayyavarapu if (--count == 0) { 6817c31335aSMaruthi Srinivas Bayyavarapu pr_err("Failed to reset ACP\n"); 6827c31335aSMaruthi Srinivas Bayyavarapu return -ETIMEDOUT; 6837c31335aSMaruthi Srinivas Bayyavarapu } 6847c31335aSMaruthi Srinivas Bayyavarapu udelay(100); 6857c31335aSMaruthi Srinivas Bayyavarapu } 6867c31335aSMaruthi Srinivas Bayyavarapu return 0; 6877c31335aSMaruthi Srinivas Bayyavarapu } 6887c31335aSMaruthi Srinivas Bayyavarapu 6897c31335aSMaruthi Srinivas Bayyavarapu /* ACP DMA irq handler routine for playback, capture usecases */ 6907c31335aSMaruthi Srinivas Bayyavarapu static irqreturn_t dma_irq_handler(int irq, void *arg) 6917c31335aSMaruthi Srinivas Bayyavarapu { 692bbdb7012SAkshu Agrawal u16 dscr_idx; 6937c31335aSMaruthi Srinivas Bayyavarapu u32 intr_flag, ext_intr_status; 6947c31335aSMaruthi Srinivas Bayyavarapu struct audio_drv_data *irq_data; 6957c31335aSMaruthi Srinivas Bayyavarapu void __iomem *acp_mmio; 6967c31335aSMaruthi Srinivas Bayyavarapu struct device *dev = arg; 6977c31335aSMaruthi Srinivas Bayyavarapu bool valid_irq = false; 6987c31335aSMaruthi Srinivas Bayyavarapu 6997c31335aSMaruthi Srinivas Bayyavarapu irq_data = dev_get_drvdata(dev); 7007c31335aSMaruthi Srinivas Bayyavarapu acp_mmio = irq_data->acp_mmio; 7017c31335aSMaruthi Srinivas Bayyavarapu 7027c31335aSMaruthi Srinivas Bayyavarapu ext_intr_status = acp_reg_read(acp_mmio, mmACP_EXTERNAL_INTR_STAT); 7037c31335aSMaruthi Srinivas Bayyavarapu intr_flag = (((ext_intr_status & 7047c31335aSMaruthi Srinivas Bayyavarapu ACP_EXTERNAL_INTR_STAT__DMAIOCStat_MASK) >> 7057c31335aSMaruthi Srinivas Bayyavarapu ACP_EXTERNAL_INTR_STAT__DMAIOCStat__SHIFT)); 7067c31335aSMaruthi Srinivas Bayyavarapu 7077c31335aSMaruthi Srinivas Bayyavarapu if ((intr_flag & BIT(ACP_TO_I2S_DMA_CH_NUM)) != 0) { 7087c31335aSMaruthi Srinivas Bayyavarapu valid_irq = true; 709e21358c4SMukunda, Vijendar snd_pcm_period_elapsed(irq_data->play_i2ssp_stream); 7107c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write((intr_flag & BIT(ACP_TO_I2S_DMA_CH_NUM)) << 16, 7117c31335aSMaruthi Srinivas Bayyavarapu acp_mmio, mmACP_EXTERNAL_INTR_STAT); 7127c31335aSMaruthi Srinivas Bayyavarapu } 7137c31335aSMaruthi Srinivas Bayyavarapu 7143eb8440dSVijendar Mukunda if ((intr_flag & BIT(ACP_TO_I2S_DMA_MICSP_INSTANCE_CH_NUM)) != 0) { 7153eb8440dSVijendar Mukunda valid_irq = true; 7163eb8440dSVijendar Mukunda snd_pcm_period_elapsed(irq_data->play_i2s_micsp_stream); 7173eb8440dSVijendar Mukunda acp_reg_write((intr_flag & BIT(ACP_TO_I2S_DMA_MICSP_INSTANCE_CH_NUM)) << 16, 7183eb8440dSVijendar Mukunda acp_mmio, mmACP_EXTERNAL_INTR_STAT); 7193eb8440dSVijendar Mukunda } 7203eb8440dSVijendar Mukunda 721ccfbb4f5SMukunda, Vijendar if ((intr_flag & BIT(ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM)) != 0) { 722ccfbb4f5SMukunda, Vijendar valid_irq = true; 723ccfbb4f5SMukunda, Vijendar snd_pcm_period_elapsed(irq_data->play_i2sbt_stream); 724ccfbb4f5SMukunda, Vijendar acp_reg_write((intr_flag & 725ccfbb4f5SMukunda, Vijendar BIT(ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM)) << 16, 726ccfbb4f5SMukunda, Vijendar acp_mmio, mmACP_EXTERNAL_INTR_STAT); 727ccfbb4f5SMukunda, Vijendar } 728ccfbb4f5SMukunda, Vijendar 72919e023e3SAgrawal, Akshu if ((intr_flag & BIT(I2S_TO_ACP_DMA_CH_NUM)) != 0) { 7307c31335aSMaruthi Srinivas Bayyavarapu valid_irq = true; 731bbdb7012SAkshu Agrawal if (acp_reg_read(acp_mmio, mmACP_DMA_CUR_DSCR_14) == 732bbdb7012SAkshu Agrawal CAPTURE_START_DMA_DESCR_CH15) 733bbdb7012SAkshu Agrawal dscr_idx = CAPTURE_END_DMA_DESCR_CH14; 734bbdb7012SAkshu Agrawal else 735bbdb7012SAkshu Agrawal dscr_idx = CAPTURE_START_DMA_DESCR_CH14; 736bbdb7012SAkshu Agrawal config_acp_dma_channel(acp_mmio, ACP_TO_SYSRAM_CH_NUM, dscr_idx, 737bbdb7012SAkshu Agrawal 1, 0); 738bbdb7012SAkshu Agrawal acp_dma_start(acp_mmio, ACP_TO_SYSRAM_CH_NUM, false); 739bbdb7012SAkshu Agrawal 74055af49acSDaniel Kurtz snd_pcm_period_elapsed(irq_data->capture_i2ssp_stream); 74119e023e3SAgrawal, Akshu acp_reg_write((intr_flag & BIT(I2S_TO_ACP_DMA_CH_NUM)) << 16, 7427c31335aSMaruthi Srinivas Bayyavarapu acp_mmio, mmACP_EXTERNAL_INTR_STAT); 7437c31335aSMaruthi Srinivas Bayyavarapu } 7447c31335aSMaruthi Srinivas Bayyavarapu 74519e023e3SAgrawal, Akshu if ((intr_flag & BIT(I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM)) != 0) { 746ccfbb4f5SMukunda, Vijendar valid_irq = true; 747bbdb7012SAkshu Agrawal if (acp_reg_read(acp_mmio, mmACP_DMA_CUR_DSCR_10) == 748bbdb7012SAkshu Agrawal CAPTURE_START_DMA_DESCR_CH11) 749bbdb7012SAkshu Agrawal dscr_idx = CAPTURE_END_DMA_DESCR_CH10; 750bbdb7012SAkshu Agrawal else 751bbdb7012SAkshu Agrawal dscr_idx = CAPTURE_START_DMA_DESCR_CH10; 752bbdb7012SAkshu Agrawal config_acp_dma_channel(acp_mmio, 753bbdb7012SAkshu Agrawal ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM, 754bbdb7012SAkshu Agrawal dscr_idx, 1, 0); 755bbdb7012SAkshu Agrawal acp_dma_start(acp_mmio, ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM, 756bbdb7012SAkshu Agrawal false); 757bbdb7012SAkshu Agrawal 75855af49acSDaniel Kurtz snd_pcm_period_elapsed(irq_data->capture_i2sbt_stream); 759ccfbb4f5SMukunda, Vijendar acp_reg_write((intr_flag & 76019e023e3SAgrawal, Akshu BIT(I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM)) << 16, 761ccfbb4f5SMukunda, Vijendar acp_mmio, mmACP_EXTERNAL_INTR_STAT); 762ccfbb4f5SMukunda, Vijendar } 763ccfbb4f5SMukunda, Vijendar 7647c31335aSMaruthi Srinivas Bayyavarapu if (valid_irq) 7657c31335aSMaruthi Srinivas Bayyavarapu return IRQ_HANDLED; 7667c31335aSMaruthi Srinivas Bayyavarapu else 7677c31335aSMaruthi Srinivas Bayyavarapu return IRQ_NONE; 7687c31335aSMaruthi Srinivas Bayyavarapu } 7697c31335aSMaruthi Srinivas Bayyavarapu 7708c028a40SKuninori Morimoto static int acp_dma_open(struct snd_soc_component *component, 7718c028a40SKuninori Morimoto struct snd_pcm_substream *substream) 7727c31335aSMaruthi Srinivas Bayyavarapu { 773c36d9b3fSMaruthi Srinivas Bayyavarapu u16 bank; 7747c31335aSMaruthi Srinivas Bayyavarapu int ret = 0; 7757c31335aSMaruthi Srinivas Bayyavarapu struct snd_pcm_runtime *runtime = substream->runtime; 776a1042a42SKuninori Morimoto struct audio_drv_data *intr_data = dev_get_drvdata(component->dev); 7777c31335aSMaruthi Srinivas Bayyavarapu struct audio_substream_data *adata = 7787c31335aSMaruthi Srinivas Bayyavarapu kzalloc(sizeof(struct audio_substream_data), GFP_KERNEL); 77913838c11SMukunda, Vijendar if (!adata) 7807c31335aSMaruthi Srinivas Bayyavarapu return -ENOMEM; 7817c31335aSMaruthi Srinivas Bayyavarapu 7829c7d6fabSVijendar Mukunda if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 7839c7d6fabSVijendar Mukunda switch (intr_data->asic_type) { 7849c7d6fabSVijendar Mukunda case CHIP_STONEY: 7859c7d6fabSVijendar Mukunda runtime->hw = acp_st_pcm_hardware_playback; 7869c7d6fabSVijendar Mukunda break; 7879c7d6fabSVijendar Mukunda default: 7887c31335aSMaruthi Srinivas Bayyavarapu runtime->hw = acp_pcm_hardware_playback; 7899c7d6fabSVijendar Mukunda } 7909c7d6fabSVijendar Mukunda } else { 7919c7d6fabSVijendar Mukunda switch (intr_data->asic_type) { 7929c7d6fabSVijendar Mukunda case CHIP_STONEY: 7939c7d6fabSVijendar Mukunda runtime->hw = acp_st_pcm_hardware_capture; 7949c7d6fabSVijendar Mukunda break; 7959c7d6fabSVijendar Mukunda default: 7967c31335aSMaruthi Srinivas Bayyavarapu runtime->hw = acp_pcm_hardware_capture; 7979c7d6fabSVijendar Mukunda } 7989c7d6fabSVijendar Mukunda } 7997c31335aSMaruthi Srinivas Bayyavarapu 8007c31335aSMaruthi Srinivas Bayyavarapu ret = snd_pcm_hw_constraint_integer(runtime, 8017c31335aSMaruthi Srinivas Bayyavarapu SNDRV_PCM_HW_PARAM_PERIODS); 8027c31335aSMaruthi Srinivas Bayyavarapu if (ret < 0) { 803a1042a42SKuninori Morimoto dev_err(component->dev, "set integer constraint failed\n"); 804cde6bcd5SDan Carpenter kfree(adata); 8057c31335aSMaruthi Srinivas Bayyavarapu return ret; 8067c31335aSMaruthi Srinivas Bayyavarapu } 8077c31335aSMaruthi Srinivas Bayyavarapu 8087c31335aSMaruthi Srinivas Bayyavarapu adata->acp_mmio = intr_data->acp_mmio; 8097c31335aSMaruthi Srinivas Bayyavarapu runtime->private_data = adata; 8107c31335aSMaruthi Srinivas Bayyavarapu 81113838c11SMukunda, Vijendar /* 81213838c11SMukunda, Vijendar * Enable ACP irq, when neither playback or capture streams are 8137c31335aSMaruthi Srinivas Bayyavarapu * active by the time when a new stream is being opened. 8147c31335aSMaruthi Srinivas Bayyavarapu * This enablement is not required for another stream, if current 8157c31335aSMaruthi Srinivas Bayyavarapu * stream is not closed 8167c31335aSMaruthi Srinivas Bayyavarapu */ 817ccfbb4f5SMukunda, Vijendar if (!intr_data->play_i2ssp_stream && !intr_data->capture_i2ssp_stream && 8183eb8440dSVijendar Mukunda !intr_data->play_i2sbt_stream && !intr_data->capture_i2sbt_stream && 8193eb8440dSVijendar Mukunda !intr_data->play_i2s_micsp_stream) 8207c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB); 8217c31335aSMaruthi Srinivas Bayyavarapu 822c36d9b3fSMaruthi Srinivas Bayyavarapu if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 82313838c11SMukunda, Vijendar /* 82413838c11SMukunda, Vijendar * For Stoney, Memory gating is disabled,i.e SRAM Banks 825607b39efSVijendar Mukunda * won't be turned off. The default state for SRAM banks is ON. 826607b39efSVijendar Mukunda * Setting SRAM bank state code skipped for STONEY platform. 827607b39efSVijendar Mukunda */ 828607b39efSVijendar Mukunda if (intr_data->asic_type != CHIP_STONEY) { 829c36d9b3fSMaruthi Srinivas Bayyavarapu for (bank = 1; bank <= 4; bank++) 830607b39efSVijendar Mukunda acp_set_sram_bank_state(intr_data->acp_mmio, 831607b39efSVijendar Mukunda bank, true); 832607b39efSVijendar Mukunda } 833c36d9b3fSMaruthi Srinivas Bayyavarapu } else { 834607b39efSVijendar Mukunda if (intr_data->asic_type != CHIP_STONEY) { 835c36d9b3fSMaruthi Srinivas Bayyavarapu for (bank = 5; bank <= 8; bank++) 836607b39efSVijendar Mukunda acp_set_sram_bank_state(intr_data->acp_mmio, 837607b39efSVijendar Mukunda bank, true); 838607b39efSVijendar Mukunda } 839c36d9b3fSMaruthi Srinivas Bayyavarapu } 8407c31335aSMaruthi Srinivas Bayyavarapu 8417c31335aSMaruthi Srinivas Bayyavarapu return 0; 8427c31335aSMaruthi Srinivas Bayyavarapu } 8437c31335aSMaruthi Srinivas Bayyavarapu 8448c028a40SKuninori Morimoto static int acp_dma_hw_params(struct snd_soc_component *component, 8458c028a40SKuninori Morimoto struct snd_pcm_substream *substream, 8467c31335aSMaruthi Srinivas Bayyavarapu struct snd_pcm_hw_params *params) 8477c31335aSMaruthi Srinivas Bayyavarapu { 8487c31335aSMaruthi Srinivas Bayyavarapu uint64_t size; 849a37d48e3SVijendar Mukunda u32 val = 0; 8507c31335aSMaruthi Srinivas Bayyavarapu struct snd_pcm_runtime *runtime; 8517c31335aSMaruthi Srinivas Bayyavarapu struct audio_substream_data *rtd; 852d4f23dcdSKuninori Morimoto struct snd_soc_pcm_runtime *prtd = snd_soc_substream_to_rtd(substream); 853a1042a42SKuninori Morimoto struct audio_drv_data *adata = dev_get_drvdata(component->dev); 854ccfbb4f5SMukunda, Vijendar struct snd_soc_card *card = prtd->card; 855ccfbb4f5SMukunda, Vijendar struct acp_platform_info *pinfo = snd_soc_card_get_drvdata(card); 8567c31335aSMaruthi Srinivas Bayyavarapu 8577c31335aSMaruthi Srinivas Bayyavarapu runtime = substream->runtime; 8587c31335aSMaruthi Srinivas Bayyavarapu rtd = runtime->private_data; 8597c31335aSMaruthi Srinivas Bayyavarapu 8607c31335aSMaruthi Srinivas Bayyavarapu if (WARN_ON(!rtd)) 8617c31335aSMaruthi Srinivas Bayyavarapu return -EINVAL; 8627c31335aSMaruthi Srinivas Bayyavarapu 8632718c89aSAkshu Agrawal if (pinfo) { 8648dcb0c90SAkshu Agrawal if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 8658dcb0c90SAkshu Agrawal rtd->i2s_instance = pinfo->play_i2s_instance; 8668dcb0c90SAkshu Agrawal } else { 8678dcb0c90SAkshu Agrawal rtd->i2s_instance = pinfo->cap_i2s_instance; 8682718c89aSAkshu Agrawal rtd->capture_channel = pinfo->capture_channel; 8692718c89aSAkshu Agrawal } 8708dcb0c90SAkshu Agrawal } 871a37d48e3SVijendar Mukunda if (adata->asic_type == CHIP_STONEY) { 87213838c11SMukunda, Vijendar val = acp_reg_read(adata->acp_mmio, 87313838c11SMukunda, Vijendar mmACP_I2S_16BIT_RESOLUTION_EN); 874ccfbb4f5SMukunda, Vijendar if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 875ccfbb4f5SMukunda, Vijendar switch (rtd->i2s_instance) { 876ccfbb4f5SMukunda, Vijendar case I2S_BT_INSTANCE: 877ccfbb4f5SMukunda, Vijendar val |= ACP_I2S_BT_16BIT_RESOLUTION_EN; 878ccfbb4f5SMukunda, Vijendar break; 8793eb8440dSVijendar Mukunda case I2S_MICSP_INSTANCE: 8803eb8440dSVijendar Mukunda val |= ACP_I2S_MICSP_16BIT_RESOLUTION_EN; 8813eb8440dSVijendar Mukunda break; 882ccfbb4f5SMukunda, Vijendar case I2S_SP_INSTANCE: 883ccfbb4f5SMukunda, Vijendar default: 884a37d48e3SVijendar Mukunda val |= ACP_I2S_SP_16BIT_RESOLUTION_EN; 885ccfbb4f5SMukunda, Vijendar } 886ccfbb4f5SMukunda, Vijendar } else { 887ccfbb4f5SMukunda, Vijendar switch (rtd->i2s_instance) { 888ccfbb4f5SMukunda, Vijendar case I2S_BT_INSTANCE: 889ccfbb4f5SMukunda, Vijendar val |= ACP_I2S_BT_16BIT_RESOLUTION_EN; 890ccfbb4f5SMukunda, Vijendar break; 8913eb8440dSVijendar Mukunda case I2S_MICSP_INSTANCE: 892ccfbb4f5SMukunda, Vijendar case I2S_SP_INSTANCE: 893ccfbb4f5SMukunda, Vijendar default: 894a37d48e3SVijendar Mukunda val |= ACP_I2S_MIC_16BIT_RESOLUTION_EN; 895ccfbb4f5SMukunda, Vijendar } 896ccfbb4f5SMukunda, Vijendar } 89713838c11SMukunda, Vijendar acp_reg_write(val, adata->acp_mmio, 89813838c11SMukunda, Vijendar mmACP_I2S_16BIT_RESOLUTION_EN); 899a37d48e3SVijendar Mukunda } 9008769bb55SVijendar Mukunda 9018769bb55SVijendar Mukunda if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 902ccfbb4f5SMukunda, Vijendar switch (rtd->i2s_instance) { 903ccfbb4f5SMukunda, Vijendar case I2S_BT_INSTANCE: 904ccfbb4f5SMukunda, Vijendar rtd->pte_offset = ACP_ST_BT_PLAYBACK_PTE_OFFSET; 905ccfbb4f5SMukunda, Vijendar rtd->ch1 = SYSRAM_TO_ACP_BT_INSTANCE_CH_NUM; 906ccfbb4f5SMukunda, Vijendar rtd->ch2 = ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM; 907ccfbb4f5SMukunda, Vijendar rtd->sram_bank = ACP_SRAM_BANK_3_ADDRESS; 908ccfbb4f5SMukunda, Vijendar rtd->destination = TO_BLUETOOTH; 909ccfbb4f5SMukunda, Vijendar rtd->dma_dscr_idx_1 = PLAYBACK_START_DMA_DESCR_CH8; 910ccfbb4f5SMukunda, Vijendar rtd->dma_dscr_idx_2 = PLAYBACK_START_DMA_DESCR_CH9; 911ccfbb4f5SMukunda, Vijendar rtd->byte_cnt_high_reg_offset = 912ccfbb4f5SMukunda, Vijendar mmACP_I2S_BT_TRANSMIT_BYTE_CNT_HIGH; 913ccfbb4f5SMukunda, Vijendar rtd->byte_cnt_low_reg_offset = 914ccfbb4f5SMukunda, Vijendar mmACP_I2S_BT_TRANSMIT_BYTE_CNT_LOW; 915ccfbb4f5SMukunda, Vijendar adata->play_i2sbt_stream = substream; 916ccfbb4f5SMukunda, Vijendar break; 9173eb8440dSVijendar Mukunda case I2S_MICSP_INSTANCE: 9183eb8440dSVijendar Mukunda switch (adata->asic_type) { 9193eb8440dSVijendar Mukunda case CHIP_STONEY: 9203eb8440dSVijendar Mukunda rtd->pte_offset = ACP_ST_PLAYBACK_PTE_OFFSET; 9213eb8440dSVijendar Mukunda break; 9223eb8440dSVijendar Mukunda default: 9233eb8440dSVijendar Mukunda rtd->pte_offset = ACP_PLAYBACK_PTE_OFFSET; 9243eb8440dSVijendar Mukunda } 9253eb8440dSVijendar Mukunda rtd->ch1 = SYSRAM_TO_ACP_MICSP_INSTANCE_CH_NUM; 9263eb8440dSVijendar Mukunda rtd->ch2 = ACP_TO_I2S_DMA_MICSP_INSTANCE_CH_NUM; 9273eb8440dSVijendar Mukunda rtd->sram_bank = ACP_SRAM_BANK_1_ADDRESS; 9283eb8440dSVijendar Mukunda rtd->destination = TO_ACP_I2S_2; 9293eb8440dSVijendar Mukunda rtd->dma_dscr_idx_1 = PLAYBACK_START_DMA_DESCR_CH4; 9303eb8440dSVijendar Mukunda rtd->dma_dscr_idx_2 = PLAYBACK_START_DMA_DESCR_CH5; 9313eb8440dSVijendar Mukunda rtd->byte_cnt_high_reg_offset = 9323eb8440dSVijendar Mukunda mmACP_I2S_MICSP_TRANSMIT_BYTE_CNT_HIGH; 9333eb8440dSVijendar Mukunda rtd->byte_cnt_low_reg_offset = 9343eb8440dSVijendar Mukunda mmACP_I2S_MICSP_TRANSMIT_BYTE_CNT_LOW; 9353eb8440dSVijendar Mukunda 9363eb8440dSVijendar Mukunda adata->play_i2s_micsp_stream = substream; 9373eb8440dSVijendar Mukunda break; 938ccfbb4f5SMukunda, Vijendar case I2S_SP_INSTANCE: 939ccfbb4f5SMukunda, Vijendar default: 940e188c525SMukunda, Vijendar switch (adata->asic_type) { 941e188c525SMukunda, Vijendar case CHIP_STONEY: 942e188c525SMukunda, Vijendar rtd->pte_offset = ACP_ST_PLAYBACK_PTE_OFFSET; 943e188c525SMukunda, Vijendar break; 944e188c525SMukunda, Vijendar default: 945e188c525SMukunda, Vijendar rtd->pte_offset = ACP_PLAYBACK_PTE_OFFSET; 946e188c525SMukunda, Vijendar } 9478769bb55SVijendar Mukunda rtd->ch1 = SYSRAM_TO_ACP_CH_NUM; 9488769bb55SVijendar Mukunda rtd->ch2 = ACP_TO_I2S_DMA_CH_NUM; 94918e8a40dSMukunda, Vijendar rtd->sram_bank = ACP_SRAM_BANK_1_ADDRESS; 9508769bb55SVijendar Mukunda rtd->destination = TO_ACP_I2S_1; 9518769bb55SVijendar Mukunda rtd->dma_dscr_idx_1 = PLAYBACK_START_DMA_DESCR_CH12; 9528769bb55SVijendar Mukunda rtd->dma_dscr_idx_2 = PLAYBACK_START_DMA_DESCR_CH13; 9537f004847SVijendar Mukunda rtd->byte_cnt_high_reg_offset = 9547f004847SVijendar Mukunda mmACP_I2S_TRANSMIT_BYTE_CNT_HIGH; 955ccfbb4f5SMukunda, Vijendar rtd->byte_cnt_low_reg_offset = 956ccfbb4f5SMukunda, Vijendar mmACP_I2S_TRANSMIT_BYTE_CNT_LOW; 957ccfbb4f5SMukunda, Vijendar adata->play_i2ssp_stream = substream; 958ccfbb4f5SMukunda, Vijendar } 9598769bb55SVijendar Mukunda } else { 960ccfbb4f5SMukunda, Vijendar switch (rtd->i2s_instance) { 961ccfbb4f5SMukunda, Vijendar case I2S_BT_INSTANCE: 962ccfbb4f5SMukunda, Vijendar rtd->pte_offset = ACP_ST_BT_CAPTURE_PTE_OFFSET; 96355af49acSDaniel Kurtz rtd->ch1 = I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM; 96455af49acSDaniel Kurtz rtd->ch2 = ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM; 965ccfbb4f5SMukunda, Vijendar rtd->sram_bank = ACP_SRAM_BANK_4_ADDRESS; 966ccfbb4f5SMukunda, Vijendar rtd->destination = FROM_BLUETOOTH; 967ccfbb4f5SMukunda, Vijendar rtd->dma_dscr_idx_1 = CAPTURE_START_DMA_DESCR_CH10; 968ccfbb4f5SMukunda, Vijendar rtd->dma_dscr_idx_2 = CAPTURE_START_DMA_DESCR_CH11; 969c21c834aSAkshu Agrawal rtd->byte_cnt_high_reg_offset = 970c21c834aSAkshu Agrawal mmACP_I2S_BT_RECEIVE_BYTE_CNT_HIGH; 971c21c834aSAkshu Agrawal rtd->byte_cnt_low_reg_offset = 972c21c834aSAkshu Agrawal mmACP_I2S_BT_RECEIVE_BYTE_CNT_LOW; 973662fb3efSMukunda, Vijendar rtd->dma_curr_dscr = mmACP_DMA_CUR_DSCR_11; 974ccfbb4f5SMukunda, Vijendar adata->capture_i2sbt_stream = substream; 975ccfbb4f5SMukunda, Vijendar break; 9763eb8440dSVijendar Mukunda case I2S_MICSP_INSTANCE: 977ccfbb4f5SMukunda, Vijendar case I2S_SP_INSTANCE: 978ccfbb4f5SMukunda, Vijendar default: 979ccfbb4f5SMukunda, Vijendar rtd->pte_offset = ACP_CAPTURE_PTE_OFFSET; 98055af49acSDaniel Kurtz rtd->ch1 = I2S_TO_ACP_DMA_CH_NUM; 98155af49acSDaniel Kurtz rtd->ch2 = ACP_TO_SYSRAM_CH_NUM; 982e188c525SMukunda, Vijendar switch (adata->asic_type) { 983e188c525SMukunda, Vijendar case CHIP_STONEY: 984e188c525SMukunda, Vijendar rtd->pte_offset = ACP_ST_CAPTURE_PTE_OFFSET; 98518e8a40dSMukunda, Vijendar rtd->sram_bank = ACP_SRAM_BANK_2_ADDRESS; 986e188c525SMukunda, Vijendar break; 987e188c525SMukunda, Vijendar default: 988e188c525SMukunda, Vijendar rtd->pte_offset = ACP_CAPTURE_PTE_OFFSET; 98918e8a40dSMukunda, Vijendar rtd->sram_bank = ACP_SRAM_BANK_5_ADDRESS; 990e188c525SMukunda, Vijendar } 9918769bb55SVijendar Mukunda rtd->destination = FROM_ACP_I2S_1; 9928769bb55SVijendar Mukunda rtd->dma_dscr_idx_1 = CAPTURE_START_DMA_DESCR_CH14; 9938769bb55SVijendar Mukunda rtd->dma_dscr_idx_2 = CAPTURE_START_DMA_DESCR_CH15; 994c21c834aSAkshu Agrawal rtd->byte_cnt_high_reg_offset = 995c21c834aSAkshu Agrawal mmACP_I2S_RECEIVED_BYTE_CNT_HIGH; 996c21c834aSAkshu Agrawal rtd->byte_cnt_low_reg_offset = 997c21c834aSAkshu Agrawal mmACP_I2S_RECEIVED_BYTE_CNT_LOW; 998662fb3efSMukunda, Vijendar rtd->dma_curr_dscr = mmACP_DMA_CUR_DSCR_15; 999ccfbb4f5SMukunda, Vijendar adata->capture_i2ssp_stream = substream; 1000ccfbb4f5SMukunda, Vijendar } 10018769bb55SVijendar Mukunda } 10028769bb55SVijendar Mukunda 10037c31335aSMaruthi Srinivas Bayyavarapu size = params_buffer_bytes(params); 10047c31335aSMaruthi Srinivas Bayyavarapu 1005c36d9b3fSMaruthi Srinivas Bayyavarapu acp_set_sram_bank_state(rtd->acp_mmio, 0, true); 10067c31335aSMaruthi Srinivas Bayyavarapu /* Save for runtime private data */ 10078b5d9531STakashi Iwai rtd->dma_addr = runtime->dma_addr; 10087c31335aSMaruthi Srinivas Bayyavarapu rtd->order = get_order(size); 10097c31335aSMaruthi Srinivas Bayyavarapu 10107c31335aSMaruthi Srinivas Bayyavarapu /* Fill the page table entries in ACP SRAM */ 10117c31335aSMaruthi Srinivas Bayyavarapu rtd->size = size; 10127c31335aSMaruthi Srinivas Bayyavarapu rtd->num_of_pages = PAGE_ALIGN(size) >> PAGE_SHIFT; 10137c31335aSMaruthi Srinivas Bayyavarapu rtd->direction = substream->stream; 10147c31335aSMaruthi Srinivas Bayyavarapu 1015aac89748SVijendar Mukunda config_acp_dma(rtd->acp_mmio, rtd, adata->asic_type); 10167f4aee8fSTakashi Iwai return 0; 10177c31335aSMaruthi Srinivas Bayyavarapu } 10187c31335aSMaruthi Srinivas Bayyavarapu 10197f004847SVijendar Mukunda static u64 acp_get_byte_count(struct audio_substream_data *rtd) 102061add814SVijendar Mukunda { 10217f004847SVijendar Mukunda union acp_dma_count byte_count; 102261add814SVijendar Mukunda 10237f004847SVijendar Mukunda byte_count.bcount.high = acp_reg_read(rtd->acp_mmio, 10247f004847SVijendar Mukunda rtd->byte_cnt_high_reg_offset); 10257f004847SVijendar Mukunda byte_count.bcount.low = acp_reg_read(rtd->acp_mmio, 10267f004847SVijendar Mukunda rtd->byte_cnt_low_reg_offset); 10277f004847SVijendar Mukunda return byte_count.bytescount; 102861add814SVijendar Mukunda } 102961add814SVijendar Mukunda 10308c028a40SKuninori Morimoto static snd_pcm_uframes_t acp_dma_pointer(struct snd_soc_component *component, 10318c028a40SKuninori Morimoto struct snd_pcm_substream *substream) 10327c31335aSMaruthi Srinivas Bayyavarapu { 103361add814SVijendar Mukunda u32 buffersize; 10347c31335aSMaruthi Srinivas Bayyavarapu u32 pos = 0; 103561add814SVijendar Mukunda u64 bytescount = 0; 1036662fb3efSMukunda, Vijendar u16 dscr; 1037c21c834aSAkshu Agrawal u32 period_bytes, delay; 10387c31335aSMaruthi Srinivas Bayyavarapu 10397c31335aSMaruthi Srinivas Bayyavarapu struct snd_pcm_runtime *runtime = substream->runtime; 10407c31335aSMaruthi Srinivas Bayyavarapu struct audio_substream_data *rtd = runtime->private_data; 1041feea640aSKuninori Morimoto struct audio_drv_data *adata = dev_get_drvdata(component->dev); 10427c31335aSMaruthi Srinivas Bayyavarapu 10437afa535eSMukunda, Vijendar if (!rtd) 10447afa535eSMukunda, Vijendar return -EINVAL; 10457afa535eSMukunda, Vijendar 1046662fb3efSMukunda, Vijendar if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { 1047662fb3efSMukunda, Vijendar period_bytes = frames_to_bytes(runtime, runtime->period_size); 1048c50535edSAkshu Agrawal bytescount = acp_get_byte_count(rtd); 1049c50535edSAkshu Agrawal if (bytescount >= rtd->bytescount) 1050c50535edSAkshu Agrawal bytescount -= rtd->bytescount; 1051c50535edSAkshu Agrawal if (bytescount < period_bytes) { 1052c50535edSAkshu Agrawal pos = 0; 1053c50535edSAkshu Agrawal } else { 1054662fb3efSMukunda, Vijendar dscr = acp_reg_read(rtd->acp_mmio, rtd->dma_curr_dscr); 1055662fb3efSMukunda, Vijendar if (dscr == rtd->dma_dscr_idx_1) 1056662fb3efSMukunda, Vijendar pos = period_bytes; 1057662fb3efSMukunda, Vijendar else 1058662fb3efSMukunda, Vijendar pos = 0; 1059c50535edSAkshu Agrawal } 1060c50535edSAkshu Agrawal if (bytescount > 0) { 1061c21c834aSAkshu Agrawal delay = do_div(bytescount, period_bytes); 1062feea640aSKuninori Morimoto adata->delay += bytes_to_frames(runtime, delay); 1063c50535edSAkshu Agrawal } 1064662fb3efSMukunda, Vijendar } else { 106561add814SVijendar Mukunda buffersize = frames_to_bytes(runtime, runtime->buffer_size); 10667f004847SVijendar Mukunda bytescount = acp_get_byte_count(rtd); 1067662fb3efSMukunda, Vijendar if (bytescount > rtd->bytescount) 10689af8937eSVijendar Mukunda bytescount -= rtd->bytescount; 10697db08b2cSGuenter Roeck pos = do_div(bytescount, buffersize); 1070662fb3efSMukunda, Vijendar } 10717c31335aSMaruthi Srinivas Bayyavarapu return bytes_to_frames(runtime, pos); 10727c31335aSMaruthi Srinivas Bayyavarapu } 10737c31335aSMaruthi Srinivas Bayyavarapu 1074feea640aSKuninori Morimoto static snd_pcm_sframes_t acp_dma_delay(struct snd_soc_component *component, 1075feea640aSKuninori Morimoto struct snd_pcm_substream *substream) 1076feea640aSKuninori Morimoto { 1077feea640aSKuninori Morimoto struct audio_drv_data *adata = dev_get_drvdata(component->dev); 1078feea640aSKuninori Morimoto snd_pcm_sframes_t delay = adata->delay; 1079feea640aSKuninori Morimoto 1080feea640aSKuninori Morimoto adata->delay = 0; 1081feea640aSKuninori Morimoto 1082feea640aSKuninori Morimoto return delay; 1083feea640aSKuninori Morimoto } 1084feea640aSKuninori Morimoto 10858c028a40SKuninori Morimoto static int acp_dma_prepare(struct snd_soc_component *component, 10868c028a40SKuninori Morimoto struct snd_pcm_substream *substream) 10877c31335aSMaruthi Srinivas Bayyavarapu { 10887c31335aSMaruthi Srinivas Bayyavarapu struct snd_pcm_runtime *runtime = substream->runtime; 10897c31335aSMaruthi Srinivas Bayyavarapu struct audio_substream_data *rtd = runtime->private_data; 1090fa9d2f17SAgrawal, Akshu u16 ch_acp_sysmem, ch_acp_i2s; 10917c31335aSMaruthi Srinivas Bayyavarapu 10927afa535eSMukunda, Vijendar if (!rtd) 10937afa535eSMukunda, Vijendar return -EINVAL; 10948769bb55SVijendar Mukunda 1095fa9d2f17SAgrawal, Akshu if (rtd->direction == SNDRV_PCM_STREAM_PLAYBACK) { 1096fa9d2f17SAgrawal, Akshu ch_acp_sysmem = rtd->ch1; 1097fa9d2f17SAgrawal, Akshu ch_acp_i2s = rtd->ch2; 1098fa9d2f17SAgrawal, Akshu } else { 1099fa9d2f17SAgrawal, Akshu ch_acp_i2s = rtd->ch1; 1100fa9d2f17SAgrawal, Akshu ch_acp_sysmem = rtd->ch2; 1101fa9d2f17SAgrawal, Akshu } 11028769bb55SVijendar Mukunda config_acp_dma_channel(rtd->acp_mmio, 1103fa9d2f17SAgrawal, Akshu ch_acp_sysmem, 11048769bb55SVijendar Mukunda rtd->dma_dscr_idx_1, 11057c31335aSMaruthi Srinivas Bayyavarapu NUM_DSCRS_PER_CHANNEL, 0); 11068769bb55SVijendar Mukunda config_acp_dma_channel(rtd->acp_mmio, 1107fa9d2f17SAgrawal, Akshu ch_acp_i2s, 11088769bb55SVijendar Mukunda rtd->dma_dscr_idx_2, 11097c31335aSMaruthi Srinivas Bayyavarapu NUM_DSCRS_PER_CHANNEL, 0); 11107c31335aSMaruthi Srinivas Bayyavarapu return 0; 11117c31335aSMaruthi Srinivas Bayyavarapu } 11127c31335aSMaruthi Srinivas Bayyavarapu 11138c028a40SKuninori Morimoto static int acp_dma_trigger(struct snd_soc_component *component, 11148c028a40SKuninori Morimoto struct snd_pcm_substream *substream, int cmd) 11157c31335aSMaruthi Srinivas Bayyavarapu { 11167c31335aSMaruthi Srinivas Bayyavarapu int ret; 11177c31335aSMaruthi Srinivas Bayyavarapu 11187c31335aSMaruthi Srinivas Bayyavarapu struct snd_pcm_runtime *runtime = substream->runtime; 11197c31335aSMaruthi Srinivas Bayyavarapu struct audio_substream_data *rtd = runtime->private_data; 11207c31335aSMaruthi Srinivas Bayyavarapu 11217c31335aSMaruthi Srinivas Bayyavarapu if (!rtd) 11227c31335aSMaruthi Srinivas Bayyavarapu return -EINVAL; 11237c31335aSMaruthi Srinivas Bayyavarapu switch (cmd) { 11247c31335aSMaruthi Srinivas Bayyavarapu case SNDRV_PCM_TRIGGER_START: 11257c31335aSMaruthi Srinivas Bayyavarapu case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 11267c31335aSMaruthi Srinivas Bayyavarapu case SNDRV_PCM_TRIGGER_RESUME: 11271a337a1eSDaniel Kurtz rtd->bytescount = acp_get_byte_count(rtd); 1128df61f9f7SDaniel Kurtz if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { 11292718c89aSAkshu Agrawal if (rtd->capture_channel == CAP_CHANNEL0) { 11302718c89aSAkshu Agrawal acp_dma_cap_channel_disable(rtd->acp_mmio, 11312718c89aSAkshu Agrawal CAP_CHANNEL1); 11322718c89aSAkshu Agrawal acp_dma_cap_channel_enable(rtd->acp_mmio, 11332718c89aSAkshu Agrawal CAP_CHANNEL0); 11342718c89aSAkshu Agrawal } 11352718c89aSAkshu Agrawal if (rtd->capture_channel == CAP_CHANNEL1) { 11362718c89aSAkshu Agrawal acp_dma_cap_channel_disable(rtd->acp_mmio, 11372718c89aSAkshu Agrawal CAP_CHANNEL0); 11382718c89aSAkshu Agrawal acp_dma_cap_channel_enable(rtd->acp_mmio, 11392718c89aSAkshu Agrawal CAP_CHANNEL1); 11402718c89aSAkshu Agrawal } 1141bbdb7012SAkshu Agrawal acp_dma_start(rtd->acp_mmio, rtd->ch1, true); 1142bbdb7012SAkshu Agrawal } else { 1143bbdb7012SAkshu Agrawal acp_dma_start(rtd->acp_mmio, rtd->ch1, true); 1144bbdb7012SAkshu Agrawal acp_dma_start(rtd->acp_mmio, rtd->ch2, true); 11457c31335aSMaruthi Srinivas Bayyavarapu } 11467c31335aSMaruthi Srinivas Bayyavarapu ret = 0; 11477c31335aSMaruthi Srinivas Bayyavarapu break; 11487c31335aSMaruthi Srinivas Bayyavarapu case SNDRV_PCM_TRIGGER_STOP: 11497c31335aSMaruthi Srinivas Bayyavarapu case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 11507c31335aSMaruthi Srinivas Bayyavarapu case SNDRV_PCM_TRIGGER_SUSPEND: 11518769bb55SVijendar Mukunda acp_dma_stop(rtd->acp_mmio, rtd->ch2); 11528769bb55SVijendar Mukunda ret = acp_dma_stop(rtd->acp_mmio, rtd->ch1); 11537c31335aSMaruthi Srinivas Bayyavarapu break; 11547c31335aSMaruthi Srinivas Bayyavarapu default: 11557c31335aSMaruthi Srinivas Bayyavarapu ret = -EINVAL; 11567c31335aSMaruthi Srinivas Bayyavarapu } 11577c31335aSMaruthi Srinivas Bayyavarapu return ret; 11587c31335aSMaruthi Srinivas Bayyavarapu } 11597c31335aSMaruthi Srinivas Bayyavarapu 11608c028a40SKuninori Morimoto static int acp_dma_new(struct snd_soc_component *component, 11618c028a40SKuninori Morimoto struct snd_soc_pcm_runtime *rtd) 11627c31335aSMaruthi Srinivas Bayyavarapu { 1163a1042a42SKuninori Morimoto struct audio_drv_data *adata = dev_get_drvdata(component->dev); 116423aa128bSYu Zhao struct device *parent = component->dev->parent; 11659c7d6fabSVijendar Mukunda 11669c7d6fabSVijendar Mukunda switch (adata->asic_type) { 11679c7d6fabSVijendar Mukunda case CHIP_STONEY: 11687f4aee8fSTakashi Iwai snd_pcm_set_managed_buffer_all(rtd->pcm, 11699c7d6fabSVijendar Mukunda SNDRV_DMA_TYPE_DEV, 117023aa128bSYu Zhao parent, 117123aa128bSYu Zhao ST_MIN_BUFFER, 11729c7d6fabSVijendar Mukunda ST_MAX_BUFFER); 11739c7d6fabSVijendar Mukunda break; 11749c7d6fabSVijendar Mukunda default: 11757f4aee8fSTakashi Iwai snd_pcm_set_managed_buffer_all(rtd->pcm, 11767c31335aSMaruthi Srinivas Bayyavarapu SNDRV_DMA_TYPE_DEV, 117723aa128bSYu Zhao parent, 117823aa128bSYu Zhao MIN_BUFFER, 11797c31335aSMaruthi Srinivas Bayyavarapu MAX_BUFFER); 11809c7d6fabSVijendar Mukunda break; 11819c7d6fabSVijendar Mukunda } 1182f6aa470fSTakashi Iwai return 0; 11837c31335aSMaruthi Srinivas Bayyavarapu } 11847c31335aSMaruthi Srinivas Bayyavarapu 11858c028a40SKuninori Morimoto static int acp_dma_close(struct snd_soc_component *component, 11868c028a40SKuninori Morimoto struct snd_pcm_substream *substream) 11877c31335aSMaruthi Srinivas Bayyavarapu { 1188c36d9b3fSMaruthi Srinivas Bayyavarapu u16 bank; 11897c31335aSMaruthi Srinivas Bayyavarapu struct snd_pcm_runtime *runtime = substream->runtime; 11907c31335aSMaruthi Srinivas Bayyavarapu struct audio_substream_data *rtd = runtime->private_data; 1191a1042a42SKuninori Morimoto struct audio_drv_data *adata = dev_get_drvdata(component->dev); 11927c31335aSMaruthi Srinivas Bayyavarapu 1193c36d9b3fSMaruthi Srinivas Bayyavarapu if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 1194ccfbb4f5SMukunda, Vijendar switch (rtd->i2s_instance) { 1195ccfbb4f5SMukunda, Vijendar case I2S_BT_INSTANCE: 1196ccfbb4f5SMukunda, Vijendar adata->play_i2sbt_stream = NULL; 1197ccfbb4f5SMukunda, Vijendar break; 11983eb8440dSVijendar Mukunda case I2S_MICSP_INSTANCE: 11993eb8440dSVijendar Mukunda adata->play_i2s_micsp_stream = NULL; 12003eb8440dSVijendar Mukunda break; 1201ccfbb4f5SMukunda, Vijendar case I2S_SP_INSTANCE: 1202ccfbb4f5SMukunda, Vijendar default: 1203e21358c4SMukunda, Vijendar adata->play_i2ssp_stream = NULL; 120413838c11SMukunda, Vijendar /* 120513838c11SMukunda, Vijendar * For Stoney, Memory gating is disabled,i.e SRAM Banks 1206ccfbb4f5SMukunda, Vijendar * won't be turned off. The default state for SRAM banks 1207ccfbb4f5SMukunda, Vijendar * is ON.Setting SRAM bank state code skipped for STONEY 1208ccfbb4f5SMukunda, Vijendar * platform. Added condition checks for Carrizo platform 1209ccfbb4f5SMukunda, Vijendar * only. 1210607b39efSVijendar Mukunda */ 1211607b39efSVijendar Mukunda if (adata->asic_type != CHIP_STONEY) { 1212c36d9b3fSMaruthi Srinivas Bayyavarapu for (bank = 1; bank <= 4; bank++) 1213ccfbb4f5SMukunda, Vijendar acp_set_sram_bank_state(adata->acp_mmio, 1214ccfbb4f5SMukunda, Vijendar bank, false); 1215ccfbb4f5SMukunda, Vijendar } 1216607b39efSVijendar Mukunda } 1217c36d9b3fSMaruthi Srinivas Bayyavarapu } else { 1218ccfbb4f5SMukunda, Vijendar switch (rtd->i2s_instance) { 1219ccfbb4f5SMukunda, Vijendar case I2S_BT_INSTANCE: 1220ccfbb4f5SMukunda, Vijendar adata->capture_i2sbt_stream = NULL; 1221ccfbb4f5SMukunda, Vijendar break; 12223eb8440dSVijendar Mukunda case I2S_MICSP_INSTANCE: 1223ccfbb4f5SMukunda, Vijendar case I2S_SP_INSTANCE: 1224ccfbb4f5SMukunda, Vijendar default: 1225e21358c4SMukunda, Vijendar adata->capture_i2ssp_stream = NULL; 1226607b39efSVijendar Mukunda if (adata->asic_type != CHIP_STONEY) { 1227c36d9b3fSMaruthi Srinivas Bayyavarapu for (bank = 5; bank <= 8; bank++) 1228ccfbb4f5SMukunda, Vijendar acp_set_sram_bank_state(adata->acp_mmio, 1229ccfbb4f5SMukunda, Vijendar bank, false); 1230ccfbb4f5SMukunda, Vijendar } 1231c36d9b3fSMaruthi Srinivas Bayyavarapu } 1232607b39efSVijendar Mukunda } 12337c31335aSMaruthi Srinivas Bayyavarapu 123413838c11SMukunda, Vijendar /* 123513838c11SMukunda, Vijendar * Disable ACP irq, when the current stream is being closed and 12367c31335aSMaruthi Srinivas Bayyavarapu * another stream is also not active. 12377c31335aSMaruthi Srinivas Bayyavarapu */ 1238ccfbb4f5SMukunda, Vijendar if (!adata->play_i2ssp_stream && !adata->capture_i2ssp_stream && 12393eb8440dSVijendar Mukunda !adata->play_i2sbt_stream && !adata->capture_i2sbt_stream && 12403eb8440dSVijendar Mukunda !adata->play_i2s_micsp_stream) 12417c31335aSMaruthi Srinivas Bayyavarapu acp_reg_write(0, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB); 1242cac6f597SMukunda, Vijendar kfree(rtd); 12437c31335aSMaruthi Srinivas Bayyavarapu return 0; 12447c31335aSMaruthi Srinivas Bayyavarapu } 12457c31335aSMaruthi Srinivas Bayyavarapu 12468c028a40SKuninori Morimoto static const struct snd_soc_component_driver acp_asoc_platform = { 12478c028a40SKuninori Morimoto .name = DRV_NAME, 12487c31335aSMaruthi Srinivas Bayyavarapu .open = acp_dma_open, 12497c31335aSMaruthi Srinivas Bayyavarapu .close = acp_dma_close, 12507c31335aSMaruthi Srinivas Bayyavarapu .hw_params = acp_dma_hw_params, 12517c31335aSMaruthi Srinivas Bayyavarapu .trigger = acp_dma_trigger, 12527c31335aSMaruthi Srinivas Bayyavarapu .pointer = acp_dma_pointer, 1253feea640aSKuninori Morimoto .delay = acp_dma_delay, 12547c31335aSMaruthi Srinivas Bayyavarapu .prepare = acp_dma_prepare, 12558c028a40SKuninori Morimoto .pcm_construct = acp_dma_new, 12567c31335aSMaruthi Srinivas Bayyavarapu }; 12577c31335aSMaruthi Srinivas Bayyavarapu 12587c31335aSMaruthi Srinivas Bayyavarapu static int acp_audio_probe(struct platform_device *pdev) 12597c31335aSMaruthi Srinivas Bayyavarapu { 126087d71a12SMeng Tang int status, irq; 12617c31335aSMaruthi Srinivas Bayyavarapu struct audio_drv_data *audio_drv_data; 1262a1b16aaaSVijendar Mukunda const u32 *pdata = pdev->dev.platform_data; 12637c31335aSMaruthi Srinivas Bayyavarapu 1264fdaa4511SGuenter Roeck if (!pdata) { 1265fdaa4511SGuenter Roeck dev_err(&pdev->dev, "Missing platform data\n"); 1266fdaa4511SGuenter Roeck return -ENODEV; 1267fdaa4511SGuenter Roeck } 1268fdaa4511SGuenter Roeck 12697c31335aSMaruthi Srinivas Bayyavarapu audio_drv_data = devm_kzalloc(&pdev->dev, sizeof(struct audio_drv_data), 12707c31335aSMaruthi Srinivas Bayyavarapu GFP_KERNEL); 127113838c11SMukunda, Vijendar if (!audio_drv_data) 12727c31335aSMaruthi Srinivas Bayyavarapu return -ENOMEM; 12737c31335aSMaruthi Srinivas Bayyavarapu 1274dfafc182SYueHaibing audio_drv_data->acp_mmio = devm_platform_ioremap_resource(pdev, 0); 1275fdaa4511SGuenter Roeck if (IS_ERR(audio_drv_data->acp_mmio)) 1276fdaa4511SGuenter Roeck return PTR_ERR(audio_drv_data->acp_mmio); 12777c31335aSMaruthi Srinivas Bayyavarapu 127813838c11SMukunda, Vijendar /* 127913838c11SMukunda, Vijendar * The following members gets populated in device 'open' 12807c31335aSMaruthi Srinivas Bayyavarapu * function. Till then interrupts are disabled in 'acp_init' 12817c31335aSMaruthi Srinivas Bayyavarapu * and device doesn't generate any interrupts. 12827c31335aSMaruthi Srinivas Bayyavarapu */ 12837c31335aSMaruthi Srinivas Bayyavarapu 1284e21358c4SMukunda, Vijendar audio_drv_data->play_i2ssp_stream = NULL; 1285e21358c4SMukunda, Vijendar audio_drv_data->capture_i2ssp_stream = NULL; 1286ccfbb4f5SMukunda, Vijendar audio_drv_data->play_i2sbt_stream = NULL; 1287ccfbb4f5SMukunda, Vijendar audio_drv_data->capture_i2sbt_stream = NULL; 12883eb8440dSVijendar Mukunda audio_drv_data->play_i2s_micsp_stream = NULL; 1289e21358c4SMukunda, Vijendar 1290a1b16aaaSVijendar Mukunda audio_drv_data->asic_type = *pdata; 12917c31335aSMaruthi Srinivas Bayyavarapu 129287d71a12SMeng Tang irq = platform_get_irq(pdev, 0); 129387d71a12SMeng Tang if (irq < 0) 12947c31335aSMaruthi Srinivas Bayyavarapu return -ENODEV; 12957c31335aSMaruthi Srinivas Bayyavarapu 129687d71a12SMeng Tang status = devm_request_irq(&pdev->dev, irq, dma_irq_handler, 12977c31335aSMaruthi Srinivas Bayyavarapu 0, "ACP_IRQ", &pdev->dev); 12987c31335aSMaruthi Srinivas Bayyavarapu if (status) { 12997c31335aSMaruthi Srinivas Bayyavarapu dev_err(&pdev->dev, "ACP IRQ request failed\n"); 13007c31335aSMaruthi Srinivas Bayyavarapu return status; 13017c31335aSMaruthi Srinivas Bayyavarapu } 13027c31335aSMaruthi Srinivas Bayyavarapu 13037c31335aSMaruthi Srinivas Bayyavarapu dev_set_drvdata(&pdev->dev, audio_drv_data); 13047c31335aSMaruthi Srinivas Bayyavarapu 13057c31335aSMaruthi Srinivas Bayyavarapu /* Initialize the ACP */ 13067afa535eSMukunda, Vijendar status = acp_init(audio_drv_data->acp_mmio, audio_drv_data->asic_type); 13077afa535eSMukunda, Vijendar if (status) { 13087afa535eSMukunda, Vijendar dev_err(&pdev->dev, "ACP Init failed status:%d\n", status); 13097afa535eSMukunda, Vijendar return status; 13107afa535eSMukunda, Vijendar } 13117c31335aSMaruthi Srinivas Bayyavarapu 1312a1042a42SKuninori Morimoto status = devm_snd_soc_register_component(&pdev->dev, 1313a1042a42SKuninori Morimoto &acp_asoc_platform, NULL, 0); 13147c31335aSMaruthi Srinivas Bayyavarapu if (status != 0) { 13157c31335aSMaruthi Srinivas Bayyavarapu dev_err(&pdev->dev, "Fail to register ALSA platform device\n"); 13167c31335aSMaruthi Srinivas Bayyavarapu return status; 13177c31335aSMaruthi Srinivas Bayyavarapu } 13187c31335aSMaruthi Srinivas Bayyavarapu 13191927da93SMaruthi Srinivas Bayyavarapu pm_runtime_set_autosuspend_delay(&pdev->dev, 10000); 13201927da93SMaruthi Srinivas Bayyavarapu pm_runtime_use_autosuspend(&pdev->dev); 13211927da93SMaruthi Srinivas Bayyavarapu pm_runtime_enable(&pdev->dev); 13221927da93SMaruthi Srinivas Bayyavarapu 13237c31335aSMaruthi Srinivas Bayyavarapu return status; 13247c31335aSMaruthi Srinivas Bayyavarapu } 13257c31335aSMaruthi Srinivas Bayyavarapu 13266bbbbc24SUwe Kleine-König static void acp_audio_remove(struct platform_device *pdev) 13277c31335aSMaruthi Srinivas Bayyavarapu { 13287afa535eSMukunda, Vijendar int status; 13297c31335aSMaruthi Srinivas Bayyavarapu struct audio_drv_data *adata = dev_get_drvdata(&pdev->dev); 13307c31335aSMaruthi Srinivas Bayyavarapu 13317afa535eSMukunda, Vijendar status = acp_deinit(adata->acp_mmio); 13327afa535eSMukunda, Vijendar if (status) 13337afa535eSMukunda, Vijendar dev_err(&pdev->dev, "ACP Deinit failed status:%d\n", status); 13341927da93SMaruthi Srinivas Bayyavarapu pm_runtime_disable(&pdev->dev); 13357c31335aSMaruthi Srinivas Bayyavarapu } 13367c31335aSMaruthi Srinivas Bayyavarapu 13371927da93SMaruthi Srinivas Bayyavarapu static int acp_pcm_resume(struct device *dev) 13381927da93SMaruthi Srinivas Bayyavarapu { 1339c36d9b3fSMaruthi Srinivas Bayyavarapu u16 bank; 13407afa535eSMukunda, Vijendar int status; 1341ccfbb4f5SMukunda, Vijendar struct audio_substream_data *rtd; 13421927da93SMaruthi Srinivas Bayyavarapu struct audio_drv_data *adata = dev_get_drvdata(dev); 13431927da93SMaruthi Srinivas Bayyavarapu 13447afa535eSMukunda, Vijendar status = acp_init(adata->acp_mmio, adata->asic_type); 13457afa535eSMukunda, Vijendar if (status) { 13467afa535eSMukunda, Vijendar dev_err(dev, "ACP Init failed status:%d\n", status); 13477afa535eSMukunda, Vijendar return status; 13487afa535eSMukunda, Vijendar } 13491927da93SMaruthi Srinivas Bayyavarapu 1350e21358c4SMukunda, Vijendar if (adata->play_i2ssp_stream && adata->play_i2ssp_stream->runtime) { 135113838c11SMukunda, Vijendar /* 135213838c11SMukunda, Vijendar * For Stoney, Memory gating is disabled,i.e SRAM Banks 1353607b39efSVijendar Mukunda * won't be turned off. The default state for SRAM banks is ON. 1354607b39efSVijendar Mukunda * Setting SRAM bank state code skipped for STONEY platform. 1355607b39efSVijendar Mukunda */ 1356607b39efSVijendar Mukunda if (adata->asic_type != CHIP_STONEY) { 1357c36d9b3fSMaruthi Srinivas Bayyavarapu for (bank = 1; bank <= 4; bank++) 1358c36d9b3fSMaruthi Srinivas Bayyavarapu acp_set_sram_bank_state(adata->acp_mmio, bank, 1359c36d9b3fSMaruthi Srinivas Bayyavarapu true); 1360607b39efSVijendar Mukunda } 1361ccfbb4f5SMukunda, Vijendar rtd = adata->play_i2ssp_stream->runtime->private_data; 1362ccfbb4f5SMukunda, Vijendar config_acp_dma(adata->acp_mmio, rtd, adata->asic_type); 1363c36d9b3fSMaruthi Srinivas Bayyavarapu } 136413838c11SMukunda, Vijendar if (adata->capture_i2ssp_stream && 136513838c11SMukunda, Vijendar adata->capture_i2ssp_stream->runtime) { 1366607b39efSVijendar Mukunda if (adata->asic_type != CHIP_STONEY) { 1367c36d9b3fSMaruthi Srinivas Bayyavarapu for (bank = 5; bank <= 8; bank++) 1368c36d9b3fSMaruthi Srinivas Bayyavarapu acp_set_sram_bank_state(adata->acp_mmio, bank, 1369c36d9b3fSMaruthi Srinivas Bayyavarapu true); 1370607b39efSVijendar Mukunda } 1371ccfbb4f5SMukunda, Vijendar rtd = adata->capture_i2ssp_stream->runtime->private_data; 1372ccfbb4f5SMukunda, Vijendar config_acp_dma(adata->acp_mmio, rtd, adata->asic_type); 1373ccfbb4f5SMukunda, Vijendar } 1374ccfbb4f5SMukunda, Vijendar if (adata->asic_type != CHIP_CARRIZO) { 13753eb8440dSVijendar Mukunda if (adata->play_i2s_micsp_stream && 13763eb8440dSVijendar Mukunda adata->play_i2s_micsp_stream->runtime) { 13773eb8440dSVijendar Mukunda rtd = adata->play_i2s_micsp_stream->runtime->private_data; 13783eb8440dSVijendar Mukunda config_acp_dma(adata->acp_mmio, rtd, adata->asic_type); 13793eb8440dSVijendar Mukunda } 1380ccfbb4f5SMukunda, Vijendar if (adata->play_i2sbt_stream && 1381ccfbb4f5SMukunda, Vijendar adata->play_i2sbt_stream->runtime) { 1382ccfbb4f5SMukunda, Vijendar rtd = adata->play_i2sbt_stream->runtime->private_data; 1383ccfbb4f5SMukunda, Vijendar config_acp_dma(adata->acp_mmio, rtd, adata->asic_type); 1384ccfbb4f5SMukunda, Vijendar } 1385ccfbb4f5SMukunda, Vijendar if (adata->capture_i2sbt_stream && 1386ccfbb4f5SMukunda, Vijendar adata->capture_i2sbt_stream->runtime) { 1387ccfbb4f5SMukunda, Vijendar rtd = adata->capture_i2sbt_stream->runtime->private_data; 1388ccfbb4f5SMukunda, Vijendar config_acp_dma(adata->acp_mmio, rtd, adata->asic_type); 1389ccfbb4f5SMukunda, Vijendar } 1390c36d9b3fSMaruthi Srinivas Bayyavarapu } 13911927da93SMaruthi Srinivas Bayyavarapu acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB); 13921927da93SMaruthi Srinivas Bayyavarapu return 0; 13931927da93SMaruthi Srinivas Bayyavarapu } 13941927da93SMaruthi Srinivas Bayyavarapu 13951927da93SMaruthi Srinivas Bayyavarapu static int acp_pcm_runtime_suspend(struct device *dev) 13961927da93SMaruthi Srinivas Bayyavarapu { 13977afa535eSMukunda, Vijendar int status; 13981927da93SMaruthi Srinivas Bayyavarapu struct audio_drv_data *adata = dev_get_drvdata(dev); 13991927da93SMaruthi Srinivas Bayyavarapu 14007afa535eSMukunda, Vijendar status = acp_deinit(adata->acp_mmio); 14017afa535eSMukunda, Vijendar if (status) 14027afa535eSMukunda, Vijendar dev_err(dev, "ACP Deinit failed status:%d\n", status); 14031927da93SMaruthi Srinivas Bayyavarapu acp_reg_write(0, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB); 14041927da93SMaruthi Srinivas Bayyavarapu return 0; 14051927da93SMaruthi Srinivas Bayyavarapu } 14061927da93SMaruthi Srinivas Bayyavarapu 14071927da93SMaruthi Srinivas Bayyavarapu static int acp_pcm_runtime_resume(struct device *dev) 14081927da93SMaruthi Srinivas Bayyavarapu { 14097afa535eSMukunda, Vijendar int status; 14101927da93SMaruthi Srinivas Bayyavarapu struct audio_drv_data *adata = dev_get_drvdata(dev); 14111927da93SMaruthi Srinivas Bayyavarapu 14127afa535eSMukunda, Vijendar status = acp_init(adata->acp_mmio, adata->asic_type); 14137afa535eSMukunda, Vijendar if (status) { 14147afa535eSMukunda, Vijendar dev_err(dev, "ACP Init failed status:%d\n", status); 14157afa535eSMukunda, Vijendar return status; 14167afa535eSMukunda, Vijendar } 14171927da93SMaruthi Srinivas Bayyavarapu acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB); 14181927da93SMaruthi Srinivas Bayyavarapu return 0; 14191927da93SMaruthi Srinivas Bayyavarapu } 14201927da93SMaruthi Srinivas Bayyavarapu 14211927da93SMaruthi Srinivas Bayyavarapu static const struct dev_pm_ops acp_pm_ops = { 14221927da93SMaruthi Srinivas Bayyavarapu .resume = acp_pcm_resume, 14231927da93SMaruthi Srinivas Bayyavarapu .runtime_suspend = acp_pcm_runtime_suspend, 14241927da93SMaruthi Srinivas Bayyavarapu .runtime_resume = acp_pcm_runtime_resume, 14251927da93SMaruthi Srinivas Bayyavarapu }; 14261927da93SMaruthi Srinivas Bayyavarapu 14277c31335aSMaruthi Srinivas Bayyavarapu static struct platform_driver acp_dma_driver = { 14287c31335aSMaruthi Srinivas Bayyavarapu .probe = acp_audio_probe, 1429*130af75bSUwe Kleine-König .remove = acp_audio_remove, 14307c31335aSMaruthi Srinivas Bayyavarapu .driver = { 1431bdd2a858SAkshu Agrawal .name = DRV_NAME, 14321927da93SMaruthi Srinivas Bayyavarapu .pm = &acp_pm_ops, 14337c31335aSMaruthi Srinivas Bayyavarapu }, 14347c31335aSMaruthi Srinivas Bayyavarapu }; 14357c31335aSMaruthi Srinivas Bayyavarapu 14367c31335aSMaruthi Srinivas Bayyavarapu module_platform_driver(acp_dma_driver); 14377c31335aSMaruthi Srinivas Bayyavarapu 1438607b39efSVijendar Mukunda MODULE_AUTHOR("Vijendar.Mukunda@amd.com"); 14397c31335aSMaruthi Srinivas Bayyavarapu MODULE_AUTHOR("Maruthi.Bayyavarapu@amd.com"); 14407c31335aSMaruthi Srinivas Bayyavarapu MODULE_DESCRIPTION("AMD ACP PCM Driver"); 14417c31335aSMaruthi Srinivas Bayyavarapu MODULE_LICENSE("GPL v2"); 1442bdd2a858SAkshu Agrawal MODULE_ALIAS("platform:"DRV_NAME); 1443