1*873e65bcSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2c454fd4eSMasakazu Mokuno /* 3c454fd4eSMasakazu Mokuno * Audio support for PS3 4c454fd4eSMasakazu Mokuno * Copyright (C) 2007 Sony Computer Entertainment Inc. 5c454fd4eSMasakazu Mokuno * Copyright 2006, 2007 Sony Corporation 6c454fd4eSMasakazu Mokuno * All rights reserved. 7c454fd4eSMasakazu Mokuno */ 8c454fd4eSMasakazu Mokuno 9c454fd4eSMasakazu Mokuno /* 10c454fd4eSMasakazu Mokuno * interrupt / configure registers 11c454fd4eSMasakazu Mokuno */ 12c454fd4eSMasakazu Mokuno 13c454fd4eSMasakazu Mokuno #define PS3_AUDIO_INTR_0 (0x00000100) 14c454fd4eSMasakazu Mokuno #define PS3_AUDIO_INTR_EN_0 (0x00000140) 15c454fd4eSMasakazu Mokuno #define PS3_AUDIO_CONFIG (0x00000200) 16c454fd4eSMasakazu Mokuno 17c454fd4eSMasakazu Mokuno /* 18c454fd4eSMasakazu Mokuno * DMAC registers 19c454fd4eSMasakazu Mokuno * n:0..9 20c454fd4eSMasakazu Mokuno */ 21c454fd4eSMasakazu Mokuno #define PS3_AUDIO_DMAC_REGBASE(x) (0x0000210 + 0x20 * (x)) 22c454fd4eSMasakazu Mokuno 23c454fd4eSMasakazu Mokuno #define PS3_AUDIO_KICK(n) (PS3_AUDIO_DMAC_REGBASE(n) + 0x00) 24c454fd4eSMasakazu Mokuno #define PS3_AUDIO_SOURCE(n) (PS3_AUDIO_DMAC_REGBASE(n) + 0x04) 25c454fd4eSMasakazu Mokuno #define PS3_AUDIO_DEST(n) (PS3_AUDIO_DMAC_REGBASE(n) + 0x08) 26c454fd4eSMasakazu Mokuno #define PS3_AUDIO_DMASIZE(n) (PS3_AUDIO_DMAC_REGBASE(n) + 0x0C) 27c454fd4eSMasakazu Mokuno 28c454fd4eSMasakazu Mokuno /* 29c454fd4eSMasakazu Mokuno * mute control 30c454fd4eSMasakazu Mokuno */ 31c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AX_MCTRL (0x00004000) 32c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AX_ISBP (0x00004004) 33c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AX_AOBP (0x00004008) 34c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AX_IC (0x00004010) 35c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AX_IE (0x00004014) 36c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AX_IS (0x00004018) 37c454fd4eSMasakazu Mokuno 38c454fd4eSMasakazu Mokuno /* 39c454fd4eSMasakazu Mokuno * three wire serial 40c454fd4eSMasakazu Mokuno * n:0..3 41c454fd4eSMasakazu Mokuno */ 42c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_MCTRL (0x00006000) 43c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_3WMCTRL (0x00006004) 44c454fd4eSMasakazu Mokuno 45c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_3WCTRL(n) (0x00006200 + 0x200 * (n)) 46c454fd4eSMasakazu Mokuno 47c454fd4eSMasakazu Mokuno /* 48c454fd4eSMasakazu Mokuno * S/PDIF 49c454fd4eSMasakazu Mokuno * n:0..1 50c454fd4eSMasakazu Mokuno * x:0..11 51c454fd4eSMasakazu Mokuno * y:0..5 52c454fd4eSMasakazu Mokuno */ 53c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_SPD_REGBASE(n) (0x00007200 + 0x200 * (n)) 54c454fd4eSMasakazu Mokuno 55c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_SPDCTRL(n) \ 56c454fd4eSMasakazu Mokuno (PS3_AUDIO_AO_SPD_REGBASE(n) + 0x00) 57c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_SPDUB(n, x) \ 58c454fd4eSMasakazu Mokuno (PS3_AUDIO_AO_SPD_REGBASE(n) + 0x04 + 0x04 * (x)) 59c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_SPDCS(n, y) \ 60c454fd4eSMasakazu Mokuno (PS3_AUDIO_AO_SPD_REGBASE(n) + 0x34 + 0x04 * (y)) 61c454fd4eSMasakazu Mokuno 62c454fd4eSMasakazu Mokuno 63c454fd4eSMasakazu Mokuno /* 64c454fd4eSMasakazu Mokuno PS3_AUDIO_INTR_0 register tells an interrupt handler which audio 65c454fd4eSMasakazu Mokuno DMA channel triggered the interrupt. The interrupt status for a channel 66c454fd4eSMasakazu Mokuno can be cleared by writing a '1' to the corresponding bit. A new interrupt 67c454fd4eSMasakazu Mokuno cannot be generated until the previous interrupt has been cleared. 68c454fd4eSMasakazu Mokuno 69c454fd4eSMasakazu Mokuno Note that the status reported by PS3_AUDIO_INTR_0 is independent of the 70c454fd4eSMasakazu Mokuno value of PS3_AUDIO_INTR_EN_0. 71c454fd4eSMasakazu Mokuno 72c454fd4eSMasakazu Mokuno 31 24 23 16 15 8 7 0 73c454fd4eSMasakazu Mokuno +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+ 74c454fd4eSMasakazu Mokuno |0 0 0 0 0 0 0 0 0 0 0 0 0|C|0|C|0|C|0|C|0|C|0|C|0|C|0|C|0|C|0|C| INTR_0 75c454fd4eSMasakazu Mokuno +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+ 76c454fd4eSMasakazu Mokuno */ 77c454fd4eSMasakazu Mokuno #define PS3_AUDIO_INTR_0_CHAN(n) (1 << ((n) * 2)) 78c454fd4eSMasakazu Mokuno #define PS3_AUDIO_INTR_0_CHAN9 PS3_AUDIO_INTR_0_CHAN(9) 79c454fd4eSMasakazu Mokuno #define PS3_AUDIO_INTR_0_CHAN8 PS3_AUDIO_INTR_0_CHAN(8) 80c454fd4eSMasakazu Mokuno #define PS3_AUDIO_INTR_0_CHAN7 PS3_AUDIO_INTR_0_CHAN(7) 81c454fd4eSMasakazu Mokuno #define PS3_AUDIO_INTR_0_CHAN6 PS3_AUDIO_INTR_0_CHAN(6) 82c454fd4eSMasakazu Mokuno #define PS3_AUDIO_INTR_0_CHAN5 PS3_AUDIO_INTR_0_CHAN(5) 83c454fd4eSMasakazu Mokuno #define PS3_AUDIO_INTR_0_CHAN4 PS3_AUDIO_INTR_0_CHAN(4) 84c454fd4eSMasakazu Mokuno #define PS3_AUDIO_INTR_0_CHAN3 PS3_AUDIO_INTR_0_CHAN(3) 85c454fd4eSMasakazu Mokuno #define PS3_AUDIO_INTR_0_CHAN2 PS3_AUDIO_INTR_0_CHAN(2) 86c454fd4eSMasakazu Mokuno #define PS3_AUDIO_INTR_0_CHAN1 PS3_AUDIO_INTR_0_CHAN(1) 87c454fd4eSMasakazu Mokuno #define PS3_AUDIO_INTR_0_CHAN0 PS3_AUDIO_INTR_0_CHAN(0) 88c454fd4eSMasakazu Mokuno 89c454fd4eSMasakazu Mokuno /* 90c454fd4eSMasakazu Mokuno The PS3_AUDIO_INTR_EN_0 register specifies which DMA channels can generate 91c454fd4eSMasakazu Mokuno an interrupt to the PU. Each bit of PS3_AUDIO_INTR_EN_0 is ANDed with the 92c454fd4eSMasakazu Mokuno corresponding bit in PS3_AUDIO_INTR_0. The resulting bits are OR'd together 93c454fd4eSMasakazu Mokuno to generate the Audio interrupt. 94c454fd4eSMasakazu Mokuno 95c454fd4eSMasakazu Mokuno 31 24 23 16 15 8 7 0 96c454fd4eSMasakazu Mokuno +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+ 97c454fd4eSMasakazu Mokuno |0 0 0 0 0 0 0 0 0 0 0 0 0|C|0|C|0|C|0|C|0|C|0|C|0|C|0|C|0|C|0|C| INTR_EN_0 98c454fd4eSMasakazu Mokuno +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+ 99c454fd4eSMasakazu Mokuno 100c454fd4eSMasakazu Mokuno Bit assignments are same as PS3_AUDIO_INTR_0 101c454fd4eSMasakazu Mokuno */ 102c454fd4eSMasakazu Mokuno 103c454fd4eSMasakazu Mokuno /* 104c454fd4eSMasakazu Mokuno PS3_AUDIO_CONFIG 105c454fd4eSMasakazu Mokuno 31 24 23 16 15 8 7 0 106c454fd4eSMasakazu Mokuno +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+ 107c454fd4eSMasakazu Mokuno |0 0 0 0 0 0 0 0|0 0 0 0 0 0 0 0|0 0 0 0 0 0 0 C|0 0 0 0 0 0 0 0| CONFIG 108c454fd4eSMasakazu Mokuno +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+ 109c454fd4eSMasakazu Mokuno 110c454fd4eSMasakazu Mokuno */ 111c454fd4eSMasakazu Mokuno 112c454fd4eSMasakazu Mokuno /* The CLEAR field cancels all pending transfers, and stops any running DMA 113c454fd4eSMasakazu Mokuno transfers. Any interrupts associated with the canceled transfers 114c454fd4eSMasakazu Mokuno will occur as if the transfer had finished. 115c454fd4eSMasakazu Mokuno Since this bit is designed to recover from DMA related issues 11625985edcSLucas De Marchi which are caused by unpredictable situations, it is preferred to wait 117c454fd4eSMasakazu Mokuno for normal DMA transfer end without using this bit. 118c454fd4eSMasakazu Mokuno */ 119c454fd4eSMasakazu Mokuno #define PS3_AUDIO_CONFIG_CLEAR (1 << 8) /* RWIVF */ 120c454fd4eSMasakazu Mokuno 121c454fd4eSMasakazu Mokuno /* 122c454fd4eSMasakazu Mokuno PS3_AUDIO_AX_MCTRL: Audio Port Mute Control Register 123c454fd4eSMasakazu Mokuno 124c454fd4eSMasakazu Mokuno 31 24 23 16 15 8 7 0 125c454fd4eSMasakazu Mokuno +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+ 126c454fd4eSMasakazu Mokuno |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0|A|A|A|0 0 0 0 0 0 0|S|S|A|A|A|A| AX_MCTRL 127c454fd4eSMasakazu Mokuno +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+ 128c454fd4eSMasakazu Mokuno */ 129c454fd4eSMasakazu Mokuno 130c454fd4eSMasakazu Mokuno /* 3 Wire Audio Serial Output Channel Mutes (0..3) */ 131c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AX_MCTRL_ASOMT(n) (1 << (3 - (n))) /* RWIVF */ 132c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AX_MCTRL_ASO3MT (1 << 0) /* RWIVF */ 133c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AX_MCTRL_ASO2MT (1 << 1) /* RWIVF */ 134c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AX_MCTRL_ASO1MT (1 << 2) /* RWIVF */ 135c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AX_MCTRL_ASO0MT (1 << 3) /* RWIVF */ 136c454fd4eSMasakazu Mokuno 137c454fd4eSMasakazu Mokuno /* S/PDIF mutes (0,1)*/ 138c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AX_MCTRL_SPOMT(n) (1 << (5 - (n))) /* RWIVF */ 139c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AX_MCTRL_SPO1MT (1 << 4) /* RWIVF */ 140c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AX_MCTRL_SPO0MT (1 << 5) /* RWIVF */ 141c454fd4eSMasakazu Mokuno 142c454fd4eSMasakazu Mokuno /* All 3 Wire Serial Outputs Mute */ 143c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AX_MCTRL_AASOMT (1 << 13) /* RWIVF */ 144c454fd4eSMasakazu Mokuno 145c454fd4eSMasakazu Mokuno /* All S/PDIF Mute */ 146c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AX_MCTRL_ASPOMT (1 << 14) /* RWIVF */ 147c454fd4eSMasakazu Mokuno 148c454fd4eSMasakazu Mokuno /* All Audio Outputs Mute */ 149c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AX_MCTRL_AAOMT (1 << 15) /* RWIVF */ 150c454fd4eSMasakazu Mokuno 151c454fd4eSMasakazu Mokuno /* 152c454fd4eSMasakazu Mokuno S/PDIF Outputs Buffer Read/Write Pointer Register 153c454fd4eSMasakazu Mokuno 154c454fd4eSMasakazu Mokuno 31 24 23 16 15 8 7 0 155c454fd4eSMasakazu Mokuno +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+ 156c454fd4eSMasakazu Mokuno |0 0 0 0 0 0 0 0|0|SPO0B|0|SPO1B|0 0 0 0 0 0 0 0|0|SPO0B|0|SPO1B| AX_ISBP 157c454fd4eSMasakazu Mokuno +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+ 158c454fd4eSMasakazu Mokuno 159c454fd4eSMasakazu Mokuno */ 160c454fd4eSMasakazu Mokuno /* 161c454fd4eSMasakazu Mokuno S/PDIF Output Channel Read Buffer Numbers 162c454fd4eSMasakazu Mokuno Buffer number is value of field. 163c454fd4eSMasakazu Mokuno Indicates current read access buffer ID from Audio Data 164c454fd4eSMasakazu Mokuno Transfer controller of S/PDIF Output 165c454fd4eSMasakazu Mokuno */ 166c454fd4eSMasakazu Mokuno 167c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AX_ISBP_SPOBRN_MASK(n) (0x7 << 4 * (1 - (n))) /* R-IUF */ 168c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AX_ISBP_SPO1BRN_MASK (0x7 << 0) /* R-IUF */ 169c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AX_ISBP_SPO0BRN_MASK (0x7 << 4) /* R-IUF */ 170c454fd4eSMasakazu Mokuno 171c454fd4eSMasakazu Mokuno /* 172c454fd4eSMasakazu Mokuno S/PDIF Output Channel Buffer Write Numbers 173c454fd4eSMasakazu Mokuno Indicates current write access buffer ID from bus master. 174c454fd4eSMasakazu Mokuno */ 175c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AX_ISBP_SPOBWN_MASK(n) (0x7 << 4 * (5 - (n))) /* R-IUF */ 176c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AX_ISBP_SPO1BWN_MASK (0x7 << 16) /* R-IUF */ 177c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AX_ISBP_SPO0BWN_MASK (0x7 << 20) /* R-IUF */ 178c454fd4eSMasakazu Mokuno 179c454fd4eSMasakazu Mokuno /* 180c454fd4eSMasakazu Mokuno 3 Wire Audio Serial Outputs Buffer Read/Write 181c454fd4eSMasakazu Mokuno Pointer Register 182c454fd4eSMasakazu Mokuno Buffer number is value of field 183c454fd4eSMasakazu Mokuno 184c454fd4eSMasakazu Mokuno 31 24 23 16 15 8 7 0 185c454fd4eSMasakazu Mokuno +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+ 186c454fd4eSMasakazu Mokuno |0|ASO0B|0|ASO1B|0|ASO2B|0|ASO3B|0|ASO0B|0|ASO1B|0|ASO2B|0|ASO3B| AX_AOBP 187c454fd4eSMasakazu Mokuno +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+ 188c454fd4eSMasakazu Mokuno */ 189c454fd4eSMasakazu Mokuno 190c454fd4eSMasakazu Mokuno /* 191c454fd4eSMasakazu Mokuno 3 Wire Audio Serial Output Channel Buffer Read Numbers 192c454fd4eSMasakazu Mokuno Indicates current read access buffer Id from Audio Data Transfer 193c454fd4eSMasakazu Mokuno Controller of 3 Wire Audio Serial Output Channels 194c454fd4eSMasakazu Mokuno */ 195c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AX_AOBP_ASOBRN_MASK(n) (0x7 << 4 * (3 - (n))) /* R-IUF */ 196c454fd4eSMasakazu Mokuno 197c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AX_AOBP_ASO3BRN_MASK (0x7 << 0) /* R-IUF */ 198c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AX_AOBP_ASO2BRN_MASK (0x7 << 4) /* R-IUF */ 199c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AX_AOBP_ASO1BRN_MASK (0x7 << 8) /* R-IUF */ 200c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AX_AOBP_ASO0BRN_MASK (0x7 << 12) /* R-IUF */ 201c454fd4eSMasakazu Mokuno 202c454fd4eSMasakazu Mokuno /* 203c454fd4eSMasakazu Mokuno 3 Wire Audio Serial Output Channel Buffer Write Numbers 204c454fd4eSMasakazu Mokuno Indicates current write access buffer ID from bus master. 205c454fd4eSMasakazu Mokuno */ 206c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AX_AOBP_ASOBWN_MASK(n) (0x7 << 4 * (7 - (n))) /* R-IUF */ 207c454fd4eSMasakazu Mokuno 208c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AX_AOBP_ASO3BWN_MASK (0x7 << 16) /* R-IUF */ 209c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AX_AOBP_ASO2BWN_MASK (0x7 << 20) /* R-IUF */ 210c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AX_AOBP_ASO1BWN_MASK (0x7 << 24) /* R-IUF */ 211c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AX_AOBP_ASO0BWN_MASK (0x7 << 28) /* R-IUF */ 212c454fd4eSMasakazu Mokuno 213c454fd4eSMasakazu Mokuno 214c454fd4eSMasakazu Mokuno 215c454fd4eSMasakazu Mokuno /* 216c454fd4eSMasakazu Mokuno Audio Port Interrupt Condition Register 217c454fd4eSMasakazu Mokuno For the fields in this register, the following values apply: 218c454fd4eSMasakazu Mokuno 0 = Interrupt is generated every interrupt event. 219c454fd4eSMasakazu Mokuno 1 = Interrupt is generated every 2 interrupt events. 220c454fd4eSMasakazu Mokuno 2 = Interrupt is generated every 4 interrupt events. 221c454fd4eSMasakazu Mokuno 3 = Reserved 222c454fd4eSMasakazu Mokuno 223c454fd4eSMasakazu Mokuno 224c454fd4eSMasakazu Mokuno 31 24 23 16 15 8 7 0 225c454fd4eSMasakazu Mokuno +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+ 226c454fd4eSMasakazu Mokuno |0 0 0 0 0 0 0 0|0 0|SPO|0 0|SPO|0 0|AAS|0 0 0 0 0 0 0 0 0 0 0 0| AX_IC 227c454fd4eSMasakazu Mokuno +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+ 228c454fd4eSMasakazu Mokuno */ 229c454fd4eSMasakazu Mokuno /* 230c454fd4eSMasakazu Mokuno All 3-Wire Audio Serial Outputs Interrupt Mode 231c454fd4eSMasakazu Mokuno Configures the Interrupt and Signal Notification 232c454fd4eSMasakazu Mokuno condition of all 3-wire Audio Serial Outputs. 233c454fd4eSMasakazu Mokuno */ 234c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AX_IC_AASOIMD_MASK (0x3 << 12) /* RWIVF */ 235c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AX_IC_AASOIMD_EVERY1 (0x0 << 12) /* RWI-V */ 236c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AX_IC_AASOIMD_EVERY2 (0x1 << 12) /* RW--V */ 237c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AX_IC_AASOIMD_EVERY4 (0x2 << 12) /* RW--V */ 238c454fd4eSMasakazu Mokuno 239c454fd4eSMasakazu Mokuno /* 240c454fd4eSMasakazu Mokuno S/PDIF Output Channel Interrupt Modes 241c454fd4eSMasakazu Mokuno Configures the Interrupt and signal Notification 242c454fd4eSMasakazu Mokuno conditions of S/PDIF output channels. 243c454fd4eSMasakazu Mokuno */ 244c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AX_IC_SPO1IMD_MASK (0x3 << 16) /* RWIVF */ 245c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AX_IC_SPO1IMD_EVERY1 (0x0 << 16) /* RWI-V */ 246c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AX_IC_SPO1IMD_EVERY2 (0x1 << 16) /* RW--V */ 247c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AX_IC_SPO1IMD_EVERY4 (0x2 << 16) /* RW--V */ 248c454fd4eSMasakazu Mokuno 249c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AX_IC_SPO0IMD_MASK (0x3 << 20) /* RWIVF */ 250c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AX_IC_SPO0IMD_EVERY1 (0x0 << 20) /* RWI-V */ 251c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AX_IC_SPO0IMD_EVERY2 (0x1 << 20) /* RW--V */ 252c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AX_IC_SPO0IMD_EVERY4 (0x2 << 20) /* RW--V */ 253c454fd4eSMasakazu Mokuno 254c454fd4eSMasakazu Mokuno /* 255c454fd4eSMasakazu Mokuno Audio Port interrupt Enable Register 256c454fd4eSMasakazu Mokuno Configures whether to enable or disable each Interrupt Generation. 257c454fd4eSMasakazu Mokuno 258c454fd4eSMasakazu Mokuno 259c454fd4eSMasakazu Mokuno 31 24 23 16 15 8 7 0 260c454fd4eSMasakazu Mokuno +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+ 261c454fd4eSMasakazu Mokuno |0 0 0 0 0 0 0 0|S|S|0 0|A|A|A|A|0 0 0 0|S|S|0 0|S|S|0 0|A|A|A|A| AX_IE 262c454fd4eSMasakazu Mokuno +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+ 263c454fd4eSMasakazu Mokuno 264c454fd4eSMasakazu Mokuno */ 265c454fd4eSMasakazu Mokuno 266c454fd4eSMasakazu Mokuno /* 267c454fd4eSMasakazu Mokuno 3 Wire Audio Serial Output Channel Buffer Underflow 268c454fd4eSMasakazu Mokuno Interrupt Enables 269c454fd4eSMasakazu Mokuno Select enable/disable of Buffer Underflow Interrupts for 270c454fd4eSMasakazu Mokuno 3-Wire Audio Serial Output Channels 271c454fd4eSMasakazu Mokuno DISABLED=Interrupt generation disabled. 272c454fd4eSMasakazu Mokuno */ 273c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AX_IE_ASOBUIE(n) (1 << (3 - (n))) /* RWIVF */ 274c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AX_IE_ASO3BUIE (1 << 0) /* RWIVF */ 275c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AX_IE_ASO2BUIE (1 << 1) /* RWIVF */ 276c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AX_IE_ASO1BUIE (1 << 2) /* RWIVF */ 277c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AX_IE_ASO0BUIE (1 << 3) /* RWIVF */ 278c454fd4eSMasakazu Mokuno 279c454fd4eSMasakazu Mokuno /* S/PDIF Output Channel Buffer Underflow Interrupt Enables */ 280c454fd4eSMasakazu Mokuno 281c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AX_IE_SPOBUIE(n) (1 << (7 - (n))) /* RWIVF */ 282c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AX_IE_SPO1BUIE (1 << 6) /* RWIVF */ 283c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AX_IE_SPO0BUIE (1 << 7) /* RWIVF */ 284c454fd4eSMasakazu Mokuno 285c454fd4eSMasakazu Mokuno /* S/PDIF Output Channel One Block Transfer Completion Interrupt Enables */ 286c454fd4eSMasakazu Mokuno 287c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AX_IE_SPOBTCIE(n) (1 << (11 - (n))) /* RWIVF */ 288c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AX_IE_SPO1BTCIE (1 << 10) /* RWIVF */ 289c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AX_IE_SPO0BTCIE (1 << 11) /* RWIVF */ 290c454fd4eSMasakazu Mokuno 291c454fd4eSMasakazu Mokuno /* 3-Wire Audio Serial Output Channel Buffer Empty Interrupt Enables */ 292c454fd4eSMasakazu Mokuno 293c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AX_IE_ASOBEIE(n) (1 << (19 - (n))) /* RWIVF */ 294c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AX_IE_ASO3BEIE (1 << 16) /* RWIVF */ 295c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AX_IE_ASO2BEIE (1 << 17) /* RWIVF */ 296c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AX_IE_ASO1BEIE (1 << 18) /* RWIVF */ 297c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AX_IE_ASO0BEIE (1 << 19) /* RWIVF */ 298c454fd4eSMasakazu Mokuno 299c454fd4eSMasakazu Mokuno /* S/PDIF Output Channel Buffer Empty Interrupt Enables */ 300c454fd4eSMasakazu Mokuno 301c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AX_IE_SPOBEIE(n) (1 << (23 - (n))) /* RWIVF */ 302c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AX_IE_SPO1BEIE (1 << 22) /* RWIVF */ 303c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AX_IE_SPO0BEIE (1 << 23) /* RWIVF */ 304c454fd4eSMasakazu Mokuno 305c454fd4eSMasakazu Mokuno /* 306c454fd4eSMasakazu Mokuno Audio Port Interrupt Status Register 30725985edcSLucas De Marchi Indicates Interrupt status, which interrupt has occurred, and can clear 308c454fd4eSMasakazu Mokuno each interrupt in this register. 309c454fd4eSMasakazu Mokuno Writing 1b to a field containing 1b clears field and de-asserts interrupt. 310c454fd4eSMasakazu Mokuno Writing 0b to a field has no effect. 311c454fd4eSMasakazu Mokuno Field vaules are the following: 31225985edcSLucas De Marchi 0 - Interrupt hasn't occurred. 31325985edcSLucas De Marchi 1 - Interrupt has occurred. 314c454fd4eSMasakazu Mokuno 315c454fd4eSMasakazu Mokuno 316c454fd4eSMasakazu Mokuno 31 24 23 16 15 8 7 0 317c454fd4eSMasakazu Mokuno +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+ 318c454fd4eSMasakazu Mokuno |0 0 0 0 0 0 0 0|S|S|0 0|A|A|A|A|0 0 0 0|S|S|0 0|S|S|0 0|A|A|A|A| AX_IS 319c454fd4eSMasakazu Mokuno +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+ 320c454fd4eSMasakazu Mokuno 321c454fd4eSMasakazu Mokuno Bit assignment are same as AX_IE 322c454fd4eSMasakazu Mokuno */ 323c454fd4eSMasakazu Mokuno 324c454fd4eSMasakazu Mokuno /* 325c454fd4eSMasakazu Mokuno Audio Output Master Control Register 326c454fd4eSMasakazu Mokuno Configures Master Clock and other master Audio Output Settings 327c454fd4eSMasakazu Mokuno 328c454fd4eSMasakazu Mokuno 329c454fd4eSMasakazu Mokuno 31 24 23 16 15 8 7 0 330c454fd4eSMasakazu Mokuno +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+ 331c454fd4eSMasakazu Mokuno |0|SCKSE|0|SCKSE| MR0 | MR1 |MCL|MCL|0 0 0 0|0 0 0 0 0 0 0 0| AO_MCTRL 332c454fd4eSMasakazu Mokuno +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+ 333c454fd4eSMasakazu Mokuno */ 334c454fd4eSMasakazu Mokuno 335c454fd4eSMasakazu Mokuno /* 336c454fd4eSMasakazu Mokuno MCLK Output Control 337c454fd4eSMasakazu Mokuno Controls mclko[1] output. 338c454fd4eSMasakazu Mokuno 0 - Disable output (fixed at High) 339c454fd4eSMasakazu Mokuno 1 - Output clock produced by clock selected 340c454fd4eSMasakazu Mokuno with scksel1 by mr1 341c454fd4eSMasakazu Mokuno 2 - Reserved 342c454fd4eSMasakazu Mokuno 3 - Reserved 343c454fd4eSMasakazu Mokuno */ 344c454fd4eSMasakazu Mokuno 345c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_MCTRL_MCLKC1_MASK (0x3 << 12) /* RWIVF */ 346c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_MCTRL_MCLKC1_DISABLED (0x0 << 12) /* RWI-V */ 347c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_MCTRL_MCLKC1_ENABLED (0x1 << 12) /* RW--V */ 348c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_MCTRL_MCLKC1_RESVD2 (0x2 << 12) /* RW--V */ 349c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_MCTRL_MCLKC1_RESVD3 (0x3 << 12) /* RW--V */ 350c454fd4eSMasakazu Mokuno 351c454fd4eSMasakazu Mokuno /* 352c454fd4eSMasakazu Mokuno MCLK Output Control 353c454fd4eSMasakazu Mokuno Controls mclko[0] output. 354c454fd4eSMasakazu Mokuno 0 - Disable output (fixed at High) 355c454fd4eSMasakazu Mokuno 1 - Output clock produced by clock selected 356c454fd4eSMasakazu Mokuno with SCKSEL0 by MR0 357c454fd4eSMasakazu Mokuno 2 - Reserved 358c454fd4eSMasakazu Mokuno 3 - Reserved 359c454fd4eSMasakazu Mokuno */ 360c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_MCTRL_MCLKC0_MASK (0x3 << 14) /* RWIVF */ 361c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_MCTRL_MCLKC0_DISABLED (0x0 << 14) /* RWI-V */ 362c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_MCTRL_MCLKC0_ENABLED (0x1 << 14) /* RW--V */ 363c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_MCTRL_MCLKC0_RESVD2 (0x2 << 14) /* RW--V */ 364c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_MCTRL_MCLKC0_RESVD3 (0x3 << 14) /* RW--V */ 365c454fd4eSMasakazu Mokuno /* 366c454fd4eSMasakazu Mokuno Master Clock Rate 1 367c454fd4eSMasakazu Mokuno Sets the divide ration of Master Clock1 (clock output from 368c454fd4eSMasakazu Mokuno mclko[1] for the input clock selected by scksel1. 369c454fd4eSMasakazu Mokuno */ 370c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_MCTRL_MR1_MASK (0xf << 16) 371c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_MCTRL_MR1_DEFAULT (0x0 << 16) /* RWI-V */ 372c454fd4eSMasakazu Mokuno /* 373c454fd4eSMasakazu Mokuno Master Clock Rate 0 374c454fd4eSMasakazu Mokuno Sets the divide ratio of Master Clock0 (clock output from 375c454fd4eSMasakazu Mokuno mclko[0] for the input clock selected by scksel0). 376c454fd4eSMasakazu Mokuno */ 377c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_MCTRL_MR0_MASK (0xf << 20) /* RWIVF */ 378c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_MCTRL_MR0_DEFAULT (0x0 << 20) /* RWI-V */ 379c454fd4eSMasakazu Mokuno /* 380c454fd4eSMasakazu Mokuno System Clock Select 0/1 381c454fd4eSMasakazu Mokuno Selects the system clock to be used as Master Clock 0/1 382c454fd4eSMasakazu Mokuno Input the system clock that is appropriate for the sampling 383c454fd4eSMasakazu Mokuno rate. 384c454fd4eSMasakazu Mokuno */ 385c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_MCTRL_SCKSEL1_MASK (0x7 << 24) /* RWIVF */ 386c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_MCTRL_SCKSEL1_DEFAULT (0x2 << 24) /* RWI-V */ 387c454fd4eSMasakazu Mokuno 388c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_MCTRL_SCKSEL0_MASK (0x7 << 28) /* RWIVF */ 389c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_MCTRL_SCKSEL0_DEFAULT (0x2 << 28) /* RWI-V */ 390c454fd4eSMasakazu Mokuno 391c454fd4eSMasakazu Mokuno 392c454fd4eSMasakazu Mokuno /* 393c454fd4eSMasakazu Mokuno 3-Wire Audio Output Master Control Register 394c454fd4eSMasakazu Mokuno Configures clock, 3-Wire Audio Serial Output Enable, and 395c454fd4eSMasakazu Mokuno other 3-Wire Audio Serial Output Master Settings 396c454fd4eSMasakazu Mokuno 397c454fd4eSMasakazu Mokuno 398c454fd4eSMasakazu Mokuno 31 24 23 16 15 8 7 0 399c454fd4eSMasakazu Mokuno +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+ 400c454fd4eSMasakazu Mokuno |A|A|A|A|0 0 0|A| ASOSR |0 0 0 0|A|A|A|A|A|A|0|1|0 0 0 0 0 0 0 0| AO_3WMCTRL 401c454fd4eSMasakazu Mokuno +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+ 402c454fd4eSMasakazu Mokuno */ 403c454fd4eSMasakazu Mokuno 404c454fd4eSMasakazu Mokuno 405c454fd4eSMasakazu Mokuno /* 406c454fd4eSMasakazu Mokuno LRCKO Polarity 407c454fd4eSMasakazu Mokuno 0 - Reserved 408c454fd4eSMasakazu Mokuno 1 - default 409c454fd4eSMasakazu Mokuno */ 410c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_3WMCTRL_ASOPLRCK (1 << 8) /* RWIVF */ 411c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_3WMCTRL_ASOPLRCK_DEFAULT (1 << 8) /* RW--V */ 412c454fd4eSMasakazu Mokuno 413c454fd4eSMasakazu Mokuno /* LRCK Output Disable */ 414c454fd4eSMasakazu Mokuno 415c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_3WMCTRL_ASOLRCKD (1 << 10) /* RWIVF */ 416c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_3WMCTRL_ASOLRCKD_ENABLED (0 << 10) /* RW--V */ 417c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_3WMCTRL_ASOLRCKD_DISABLED (1 << 10) /* RWI-V */ 418c454fd4eSMasakazu Mokuno 419c454fd4eSMasakazu Mokuno /* Bit Clock Output Disable */ 420c454fd4eSMasakazu Mokuno 421c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_3WMCTRL_ASOBCLKD (1 << 11) /* RWIVF */ 422c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_3WMCTRL_ASOBCLKD_ENABLED (0 << 11) /* RW--V */ 423c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_3WMCTRL_ASOBCLKD_DISABLED (1 << 11) /* RWI-V */ 424c454fd4eSMasakazu Mokuno 425c454fd4eSMasakazu Mokuno /* 426c454fd4eSMasakazu Mokuno 3-Wire Audio Serial Output Channel 0-3 Operational 427c454fd4eSMasakazu Mokuno Status. Each bit becomes 1 after each 3-Wire Audio 428c454fd4eSMasakazu Mokuno Serial Output Channel N is in action by setting 1 to 429c454fd4eSMasakazu Mokuno asoen. 430c454fd4eSMasakazu Mokuno Each bit becomes 0 after each 3-Wire Audio Serial Output 431c454fd4eSMasakazu Mokuno Channel N is out of action by setting 0 to asoen. 432c454fd4eSMasakazu Mokuno */ 433c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_3WMCTRL_ASORUN(n) (1 << (15 - (n))) /* R-IVF */ 434c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_3WMCTRL_ASORUN_STOPPED(n) (0 << (15 - (n))) /* R-I-V */ 435c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_3WMCTRL_ASORUN_RUNNING(n) (1 << (15 - (n))) /* R---V */ 436c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_3WMCTRL_ASORUN0 \ 437c454fd4eSMasakazu Mokuno PS3_AUDIO_AO_3WMCTRL_ASORUN(0) 438c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_3WMCTRL_ASORUN0_STOPPED \ 439c454fd4eSMasakazu Mokuno PS3_AUDIO_AO_3WMCTRL_ASORUN_STOPPED(0) 440c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_3WMCTRL_ASORUN0_RUNNING \ 441c454fd4eSMasakazu Mokuno PS3_AUDIO_AO_3WMCTRL_ASORUN_RUNNING(0) 442c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_3WMCTRL_ASORUN1 \ 443c454fd4eSMasakazu Mokuno PS3_AUDIO_AO_3WMCTRL_ASORUN(1) 444c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_3WMCTRL_ASORUN1_STOPPED \ 445c454fd4eSMasakazu Mokuno PS3_AUDIO_AO_3WMCTRL_ASORUN_STOPPED(1) 446c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_3WMCTRL_ASORUN1_RUNNING \ 447c454fd4eSMasakazu Mokuno PS3_AUDIO_AO_3WMCTRL_ASORUN_RUNNING(1) 448c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_3WMCTRL_ASORUN2 \ 449c454fd4eSMasakazu Mokuno PS3_AUDIO_AO_3WMCTRL_ASORUN(2) 450c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_3WMCTRL_ASORUN2_STOPPED \ 451c454fd4eSMasakazu Mokuno PS3_AUDIO_AO_3WMCTRL_ASORUN_STOPPED(2) 452c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_3WMCTRL_ASORUN2_RUNNING \ 453c454fd4eSMasakazu Mokuno PS3_AUDIO_AO_3WMCTRL_ASORUN_RUNNING(2) 454c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_3WMCTRL_ASORUN3 \ 455c454fd4eSMasakazu Mokuno PS3_AUDIO_AO_3WMCTRL_ASORUN(3) 456c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_3WMCTRL_ASORUN3_STOPPED \ 457c454fd4eSMasakazu Mokuno PS3_AUDIO_AO_3WMCTRL_ASORUN_STOPPED(3) 458c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_3WMCTRL_ASORUN3_RUNNING \ 459c454fd4eSMasakazu Mokuno PS3_AUDIO_AO_3WMCTRL_ASORUN_RUNNING(3) 460c454fd4eSMasakazu Mokuno 461c454fd4eSMasakazu Mokuno /* 462c454fd4eSMasakazu Mokuno Sampling Rate 463c454fd4eSMasakazu Mokuno Specifies the divide ratio of the bit clock (clock output 46425985edcSLucas De Marchi from bclko) used by the 3-wire Audio Output Clock, which 465c454fd4eSMasakazu Mokuno is applied to the master clock selected by mcksel. 466c454fd4eSMasakazu Mokuno Data output is synchronized with this clock. 467c454fd4eSMasakazu Mokuno */ 468c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_3WMCTRL_ASOSR_MASK (0xf << 20) /* RWIVF */ 469c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_3WMCTRL_ASOSR_DIV2 (0x1 << 20) /* RWI-V */ 470c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_3WMCTRL_ASOSR_DIV4 (0x2 << 20) /* RW--V */ 471c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_3WMCTRL_ASOSR_DIV8 (0x4 << 20) /* RW--V */ 472c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_3WMCTRL_ASOSR_DIV12 (0x6 << 20) /* RW--V */ 473c454fd4eSMasakazu Mokuno 474c454fd4eSMasakazu Mokuno /* 475c454fd4eSMasakazu Mokuno Master Clock Select 476c454fd4eSMasakazu Mokuno 0 - Master Clock 0 477c454fd4eSMasakazu Mokuno 1 - Master Clock 1 478c454fd4eSMasakazu Mokuno */ 479c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_3WMCTRL_ASOMCKSEL (1 << 24) /* RWIVF */ 480c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_3WMCTRL_ASOMCKSEL_CLK0 (0 << 24) /* RWI-V */ 481c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_3WMCTRL_ASOMCKSEL_CLK1 (1 << 24) /* RW--V */ 482c454fd4eSMasakazu Mokuno 483c454fd4eSMasakazu Mokuno /* 484c454fd4eSMasakazu Mokuno Enables and disables 4ch 3-Wire Audio Serial Output 485c454fd4eSMasakazu Mokuno operation. Each Bit from 0 to 3 corresponds to an 486c454fd4eSMasakazu Mokuno output channel, which means that each output channel 487c454fd4eSMasakazu Mokuno can be enabled or disabled individually. When 488c454fd4eSMasakazu Mokuno multiple channels are enabled at the same time, output 489c454fd4eSMasakazu Mokuno operations are performed in synchronization. 490c454fd4eSMasakazu Mokuno Bit 0 - Output Channel 0 (SDOUT[0]) 491c454fd4eSMasakazu Mokuno Bit 1 - Output Channel 1 (SDOUT[1]) 492c454fd4eSMasakazu Mokuno Bit 2 - Output Channel 2 (SDOUT[2]) 493c454fd4eSMasakazu Mokuno Bit 3 - Output Channel 3 (SDOUT[3]) 494c454fd4eSMasakazu Mokuno */ 495c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_3WMCTRL_ASOEN(n) (1 << (31 - (n))) /* RWIVF */ 496c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_3WMCTRL_ASOEN_DISABLED(n) (0 << (31 - (n))) /* RWI-V */ 497c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_3WMCTRL_ASOEN_ENABLED(n) (1 << (31 - (n))) /* RW--V */ 498c454fd4eSMasakazu Mokuno 499c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_3WMCTRL_ASOEN0 \ 500c454fd4eSMasakazu Mokuno PS3_AUDIO_AO_3WMCTRL_ASOEN(0) /* RWIVF */ 501c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_3WMCTRL_ASOEN0_DISABLED \ 502c454fd4eSMasakazu Mokuno PS3_AUDIO_AO_3WMCTRL_ASOEN_DISABLED(0) /* RWI-V */ 503c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_3WMCTRL_ASOEN0_ENABLED \ 504c454fd4eSMasakazu Mokuno PS3_AUDIO_AO_3WMCTRL_ASOEN_ENABLED(0) /* RW--V */ 505c454fd4eSMasakazu Mokuno #define PS3_AUDIO_A1_3WMCTRL_ASOEN0 \ 506c454fd4eSMasakazu Mokuno PS3_AUDIO_AO_3WMCTRL_ASOEN(1) /* RWIVF */ 507c454fd4eSMasakazu Mokuno #define PS3_AUDIO_A1_3WMCTRL_ASOEN0_DISABLED \ 508c454fd4eSMasakazu Mokuno PS3_AUDIO_AO_3WMCTRL_ASOEN_DISABLED(1) /* RWI-V */ 509c454fd4eSMasakazu Mokuno #define PS3_AUDIO_A1_3WMCTRL_ASOEN0_ENABLED \ 510c454fd4eSMasakazu Mokuno PS3_AUDIO_AO_3WMCTRL_ASOEN_ENABLED(1) /* RW--V */ 511c454fd4eSMasakazu Mokuno #define PS3_AUDIO_A2_3WMCTRL_ASOEN0 \ 512c454fd4eSMasakazu Mokuno PS3_AUDIO_AO_3WMCTRL_ASOEN(2) /* RWIVF */ 513c454fd4eSMasakazu Mokuno #define PS3_AUDIO_A2_3WMCTRL_ASOEN0_DISABLED \ 514c454fd4eSMasakazu Mokuno PS3_AUDIO_AO_3WMCTRL_ASOEN_DISABLED(2) /* RWI-V */ 515c454fd4eSMasakazu Mokuno #define PS3_AUDIO_A2_3WMCTRL_ASOEN0_ENABLED \ 516c454fd4eSMasakazu Mokuno PS3_AUDIO_AO_3WMCTRL_ASOEN_ENABLED(2) /* RW--V */ 517c454fd4eSMasakazu Mokuno #define PS3_AUDIO_A3_3WMCTRL_ASOEN0 \ 518c454fd4eSMasakazu Mokuno PS3_AUDIO_AO_3WMCTRL_ASOEN(3) /* RWIVF */ 519c454fd4eSMasakazu Mokuno #define PS3_AUDIO_A3_3WMCTRL_ASOEN0_DISABLED \ 520c454fd4eSMasakazu Mokuno PS3_AUDIO_AO_3WMCTRL_ASOEN_DISABLED(3) /* RWI-V */ 521c454fd4eSMasakazu Mokuno #define PS3_AUDIO_A3_3WMCTRL_ASOEN0_ENABLED \ 522c454fd4eSMasakazu Mokuno PS3_AUDIO_AO_3WMCTRL_ASOEN_ENABLED(3) /* RW--V */ 523c454fd4eSMasakazu Mokuno 524c454fd4eSMasakazu Mokuno /* 525c454fd4eSMasakazu Mokuno 3-Wire Audio Serial output Channel 0-3 Control Register 526c454fd4eSMasakazu Mokuno Configures settings for 3-Wire Serial Audio Output Channel 0-3 527c454fd4eSMasakazu Mokuno 528c454fd4eSMasakazu Mokuno 529c454fd4eSMasakazu Mokuno 31 24 23 16 15 8 7 0 530c454fd4eSMasakazu Mokuno +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+ 531c454fd4eSMasakazu Mokuno |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0|A|0 0 0 0|A|0|ASO|0 0 0|0|0|0|0|0| AO_3WCTRL 532c454fd4eSMasakazu Mokuno +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+ 533c454fd4eSMasakazu Mokuno 534c454fd4eSMasakazu Mokuno */ 535c454fd4eSMasakazu Mokuno /* 536c454fd4eSMasakazu Mokuno Data Bit Mode 537c454fd4eSMasakazu Mokuno Specifies the number of data bits 538c454fd4eSMasakazu Mokuno 0 - 16 bits 539c454fd4eSMasakazu Mokuno 1 - reserved 540c454fd4eSMasakazu Mokuno 2 - 20 bits 541c454fd4eSMasakazu Mokuno 3 - 24 bits 542c454fd4eSMasakazu Mokuno */ 543c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_3WCTRL_ASODB_MASK (0x3 << 8) /* RWIVF */ 544c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_3WCTRL_ASODB_16BIT (0x0 << 8) /* RWI-V */ 545c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_3WCTRL_ASODB_RESVD (0x1 << 8) /* RWI-V */ 546c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_3WCTRL_ASODB_20BIT (0x2 << 8) /* RW--V */ 547c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_3WCTRL_ASODB_24BIT (0x3 << 8) /* RW--V */ 548c454fd4eSMasakazu Mokuno /* 549c454fd4eSMasakazu Mokuno Data Format Mode 550c454fd4eSMasakazu Mokuno Specifies the data format where (LSB side or MSB) the data(in 20 bit 551c454fd4eSMasakazu Mokuno or 24 bit resolution mode) is put in a 32 bit field. 552c454fd4eSMasakazu Mokuno 0 - Data put on LSB side 553c454fd4eSMasakazu Mokuno 1 - Data put on MSB side 554c454fd4eSMasakazu Mokuno */ 555c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_3WCTRL_ASODF (1 << 11) /* RWIVF */ 556c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_3WCTRL_ASODF_LSB (0 << 11) /* RWI-V */ 557c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_3WCTRL_ASODF_MSB (1 << 11) /* RW--V */ 558c454fd4eSMasakazu Mokuno /* 559c454fd4eSMasakazu Mokuno Buffer Reset 560c454fd4eSMasakazu Mokuno Performs buffer reset. Writing 1 to this bit initializes the 561c454fd4eSMasakazu Mokuno corresponding 3-Wire Audio Output buffers(both L and R). 562c454fd4eSMasakazu Mokuno */ 563c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_3WCTRL_ASOBRST (1 << 16) /* CWIVF */ 564c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_3WCTRL_ASOBRST_IDLE (0 << 16) /* -WI-V */ 565c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_3WCTRL_ASOBRST_RESET (1 << 16) /* -W--T */ 566c454fd4eSMasakazu Mokuno 567c454fd4eSMasakazu Mokuno /* 568c454fd4eSMasakazu Mokuno S/PDIF Audio Output Channel 0/1 Control Register 569c454fd4eSMasakazu Mokuno Configures settings for S/PDIF Audio Output Channel 0/1. 570c454fd4eSMasakazu Mokuno 571c454fd4eSMasakazu Mokuno 31 24 23 16 15 8 7 0 572c454fd4eSMasakazu Mokuno +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+ 573c454fd4eSMasakazu Mokuno |S|0 0 0|S|0 0|S| SPOSR |0 0|SPO|0 0 0 0|S|0|SPO|0 0 0 0 0 0 0|S| AO_SPDCTRL 574c454fd4eSMasakazu Mokuno +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+ 575c454fd4eSMasakazu Mokuno */ 576c454fd4eSMasakazu Mokuno /* 577c454fd4eSMasakazu Mokuno Buffer reset. Writing 1 to this bit initializes the 578c454fd4eSMasakazu Mokuno corresponding S/PDIF output buffer pointer. 579c454fd4eSMasakazu Mokuno */ 580c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_SPDCTRL_SPOBRST (1 << 0) /* CWIVF */ 581c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_SPDCTRL_SPOBRST_IDLE (0 << 0) /* -WI-V */ 582c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_SPDCTRL_SPOBRST_RESET (1 << 0) /* -W--T */ 583c454fd4eSMasakazu Mokuno 584c454fd4eSMasakazu Mokuno /* 585c454fd4eSMasakazu Mokuno Data Bit Mode 586c454fd4eSMasakazu Mokuno Specifies number of data bits 587c454fd4eSMasakazu Mokuno 0 - 16 bits 588c454fd4eSMasakazu Mokuno 1 - Reserved 589c454fd4eSMasakazu Mokuno 2 - 20 bits 590c454fd4eSMasakazu Mokuno 3 - 24 bits 591c454fd4eSMasakazu Mokuno */ 592c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_SPDCTRL_SPODB_MASK (0x3 << 8) /* RWIVF */ 593c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_SPDCTRL_SPODB_16BIT (0x0 << 8) /* RWI-V */ 594c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_SPDCTRL_SPODB_RESVD (0x1 << 8) /* RW--V */ 595c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_SPDCTRL_SPODB_20BIT (0x2 << 8) /* RW--V */ 596c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_SPDCTRL_SPODB_24BIT (0x3 << 8) /* RW--V */ 597c454fd4eSMasakazu Mokuno /* 598c454fd4eSMasakazu Mokuno Data format Mode 599c454fd4eSMasakazu Mokuno Specifies the data format, where (LSB side or MSB) 600c454fd4eSMasakazu Mokuno the data(in 20 or 24 bit resolution) is put in the 601c454fd4eSMasakazu Mokuno 32 bit field. 602c454fd4eSMasakazu Mokuno 0 - LSB Side 603c454fd4eSMasakazu Mokuno 1 - MSB Side 604c454fd4eSMasakazu Mokuno */ 605c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_SPDCTRL_SPODF (1 << 11) /* RWIVF */ 606c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_SPDCTRL_SPODF_LSB (0 << 11) /* RWI-V */ 607c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_SPDCTRL_SPODF_MSB (1 << 11) /* RW--V */ 608c454fd4eSMasakazu Mokuno /* 609c454fd4eSMasakazu Mokuno Source Select 610c454fd4eSMasakazu Mokuno Specifies the source of the S/PDIF output. When 0, output 611c454fd4eSMasakazu Mokuno operation is controlled by 3wen[0] of AO_3WMCTRL register. 612c454fd4eSMasakazu Mokuno The SR must have the same setting as the a0_3wmctrl reg. 613c454fd4eSMasakazu Mokuno 0 - 3-Wire Audio OUT Ch0 Buffer 614c454fd4eSMasakazu Mokuno 1 - S/PDIF buffer 615c454fd4eSMasakazu Mokuno */ 616c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_SPDCTRL_SPOSS_MASK (0x3 << 16) /* RWIVF */ 617c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_SPDCTRL_SPOSS_3WEN (0x0 << 16) /* RWI-V */ 618c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_SPDCTRL_SPOSS_SPDIF (0x1 << 16) /* RW--V */ 619c454fd4eSMasakazu Mokuno /* 620c454fd4eSMasakazu Mokuno Sampling Rate 621c454fd4eSMasakazu Mokuno Specifies the divide ratio of the bit clock (clock output 622c454fd4eSMasakazu Mokuno from bclko) used by the S/PDIF Output Clock, which 623c454fd4eSMasakazu Mokuno is applied to the master clock selected by mcksel. 624c454fd4eSMasakazu Mokuno */ 625c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_SPDCTRL_SPOSR (0xf << 20) /* RWIVF */ 626c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_SPDCTRL_SPOSR_DIV2 (0x1 << 20) /* RWI-V */ 627c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_SPDCTRL_SPOSR_DIV4 (0x2 << 20) /* RW--V */ 628c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_SPDCTRL_SPOSR_DIV8 (0x4 << 20) /* RW--V */ 629c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_SPDCTRL_SPOSR_DIV12 (0x6 << 20) /* RW--V */ 630c454fd4eSMasakazu Mokuno /* 631c454fd4eSMasakazu Mokuno Master Clock Select 632c454fd4eSMasakazu Mokuno 0 - Master Clock 0 633c454fd4eSMasakazu Mokuno 1 - Master Clock 1 634c454fd4eSMasakazu Mokuno */ 635c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_SPDCTRL_SPOMCKSEL (1 << 24) /* RWIVF */ 636c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_SPDCTRL_SPOMCKSEL_CLK0 (0 << 24) /* RWI-V */ 637c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_SPDCTRL_SPOMCKSEL_CLK1 (1 << 24) /* RW--V */ 638c454fd4eSMasakazu Mokuno 639c454fd4eSMasakazu Mokuno /* 640c454fd4eSMasakazu Mokuno S/PDIF Output Channel Operational Status 641c454fd4eSMasakazu Mokuno This bit becomes 1 after S/PDIF Output Channel is in 642c454fd4eSMasakazu Mokuno action by setting 1 to spoen. This bit becomes 0 643c454fd4eSMasakazu Mokuno after S/PDIF Output Channel is out of action by setting 644c454fd4eSMasakazu Mokuno 0 to spoen. 645c454fd4eSMasakazu Mokuno */ 646c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_SPDCTRL_SPORUN (1 << 27) /* R-IVF */ 647c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_SPDCTRL_SPORUN_STOPPED (0 << 27) /* R-I-V */ 648c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_SPDCTRL_SPORUN_RUNNING (1 << 27) /* R---V */ 649c454fd4eSMasakazu Mokuno 650c454fd4eSMasakazu Mokuno /* 651c454fd4eSMasakazu Mokuno S/PDIF Audio Output Channel Output Enable 652c454fd4eSMasakazu Mokuno Enables and disables output operation. This bit is used 653c454fd4eSMasakazu Mokuno only when sposs = 1 654c454fd4eSMasakazu Mokuno */ 655c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_SPDCTRL_SPOEN (1 << 31) /* RWIVF */ 656c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_SPDCTRL_SPOEN_DISABLED (0 << 31) /* RWI-V */ 657c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_SPDCTRL_SPOEN_ENABLED (1 << 31) /* RW--V */ 658c454fd4eSMasakazu Mokuno 659c454fd4eSMasakazu Mokuno /* 660c454fd4eSMasakazu Mokuno S/PDIF Audio Output Channel Channel Status 661c454fd4eSMasakazu Mokuno Setting Registers. 662c454fd4eSMasakazu Mokuno Configures channel status bit settings for each block 663c454fd4eSMasakazu Mokuno (192 bits). 664c454fd4eSMasakazu Mokuno Output is performed from the MSB(AO_SPDCS0 register bit 31). 665c454fd4eSMasakazu Mokuno The same value is added for subframes within the same frame. 666c454fd4eSMasakazu Mokuno 31 24 23 16 15 8 7 0 667c454fd4eSMasakazu Mokuno +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+ 668c454fd4eSMasakazu Mokuno | SPOCS | AO_SPDCS 669c454fd4eSMasakazu Mokuno +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+ 670c454fd4eSMasakazu Mokuno 671c454fd4eSMasakazu Mokuno S/PDIF Audio Output Channel User Bit Setting 672c454fd4eSMasakazu Mokuno Configures user bit settings for each block (384 bits). 673c454fd4eSMasakazu Mokuno Output is performed from the MSB(ao_spdub0 register bit 31). 674c454fd4eSMasakazu Mokuno 675c454fd4eSMasakazu Mokuno 676c454fd4eSMasakazu Mokuno 31 24 23 16 15 8 7 0 677c454fd4eSMasakazu Mokuno +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+ 678c454fd4eSMasakazu Mokuno | SPOUB | AO_SPDUB 679c454fd4eSMasakazu Mokuno +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+ 680c454fd4eSMasakazu Mokuno */ 681c454fd4eSMasakazu Mokuno /***************************************************************************** 682c454fd4eSMasakazu Mokuno * 683c454fd4eSMasakazu Mokuno * DMAC register 684c454fd4eSMasakazu Mokuno * 685c454fd4eSMasakazu Mokuno *****************************************************************************/ 686c454fd4eSMasakazu Mokuno /* 687c454fd4eSMasakazu Mokuno The PS3_AUDIO_KICK register is used to initiate a DMA transfer and monitor 688c454fd4eSMasakazu Mokuno its status 689c454fd4eSMasakazu Mokuno 690c454fd4eSMasakazu Mokuno 31 24 23 16 15 8 7 0 691c454fd4eSMasakazu Mokuno +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+ 692c454fd4eSMasakazu Mokuno |0 0 0 0 0|STATU|0 0 0| EVENT |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0|R| KICK 693c454fd4eSMasakazu Mokuno +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+ 694c454fd4eSMasakazu Mokuno */ 695c454fd4eSMasakazu Mokuno /* 696c454fd4eSMasakazu Mokuno The REQUEST field is written to ACTIVE to initiate a DMA request when EVENT 697c454fd4eSMasakazu Mokuno occurs. 698c454fd4eSMasakazu Mokuno It will return to the DONE state when the request is completed. 699c454fd4eSMasakazu Mokuno The registers for a DMA channel should only be written if REQUEST is IDLE. 700c454fd4eSMasakazu Mokuno */ 701c454fd4eSMasakazu Mokuno 702c454fd4eSMasakazu Mokuno #define PS3_AUDIO_KICK_REQUEST (1 << 0) /* RWIVF */ 703c454fd4eSMasakazu Mokuno #define PS3_AUDIO_KICK_REQUEST_IDLE (0 << 0) /* RWI-V */ 704c454fd4eSMasakazu Mokuno #define PS3_AUDIO_KICK_REQUEST_ACTIVE (1 << 0) /* -W--T */ 705c454fd4eSMasakazu Mokuno 706c454fd4eSMasakazu Mokuno /* 707c454fd4eSMasakazu Mokuno *The EVENT field is used to set the event in which 708c454fd4eSMasakazu Mokuno *the DMA request becomes active. 709c454fd4eSMasakazu Mokuno */ 710c454fd4eSMasakazu Mokuno #define PS3_AUDIO_KICK_EVENT_MASK (0x1f << 16) /* RWIVF */ 711c454fd4eSMasakazu Mokuno #define PS3_AUDIO_KICK_EVENT_ALWAYS (0x00 << 16) /* RWI-V */ 712c454fd4eSMasakazu Mokuno #define PS3_AUDIO_KICK_EVENT_SERIALOUT0_EMPTY (0x01 << 16) /* RW--V */ 713c454fd4eSMasakazu Mokuno #define PS3_AUDIO_KICK_EVENT_SERIALOUT0_UNDERFLOW (0x02 << 16) /* RW--V */ 714c454fd4eSMasakazu Mokuno #define PS3_AUDIO_KICK_EVENT_SERIALOUT1_EMPTY (0x03 << 16) /* RW--V */ 715c454fd4eSMasakazu Mokuno #define PS3_AUDIO_KICK_EVENT_SERIALOUT1_UNDERFLOW (0x04 << 16) /* RW--V */ 716c454fd4eSMasakazu Mokuno #define PS3_AUDIO_KICK_EVENT_SERIALOUT2_EMPTY (0x05 << 16) /* RW--V */ 717c454fd4eSMasakazu Mokuno #define PS3_AUDIO_KICK_EVENT_SERIALOUT2_UNDERFLOW (0x06 << 16) /* RW--V */ 718c454fd4eSMasakazu Mokuno #define PS3_AUDIO_KICK_EVENT_SERIALOUT3_EMPTY (0x07 << 16) /* RW--V */ 719c454fd4eSMasakazu Mokuno #define PS3_AUDIO_KICK_EVENT_SERIALOUT3_UNDERFLOW (0x08 << 16) /* RW--V */ 720c454fd4eSMasakazu Mokuno #define PS3_AUDIO_KICK_EVENT_SPDIF0_BLOCKTRANSFERCOMPLETE \ 721c454fd4eSMasakazu Mokuno (0x09 << 16) /* RW--V */ 722c454fd4eSMasakazu Mokuno #define PS3_AUDIO_KICK_EVENT_SPDIF0_UNDERFLOW (0x0A << 16) /* RW--V */ 723c454fd4eSMasakazu Mokuno #define PS3_AUDIO_KICK_EVENT_SPDIF0_EMPTY (0x0B << 16) /* RW--V */ 724c454fd4eSMasakazu Mokuno #define PS3_AUDIO_KICK_EVENT_SPDIF1_BLOCKTRANSFERCOMPLETE \ 725c454fd4eSMasakazu Mokuno (0x0C << 16) /* RW--V */ 726c454fd4eSMasakazu Mokuno #define PS3_AUDIO_KICK_EVENT_SPDIF1_UNDERFLOW (0x0D << 16) /* RW--V */ 727c454fd4eSMasakazu Mokuno #define PS3_AUDIO_KICK_EVENT_SPDIF1_EMPTY (0x0E << 16) /* RW--V */ 728c454fd4eSMasakazu Mokuno 729c454fd4eSMasakazu Mokuno #define PS3_AUDIO_KICK_EVENT_AUDIO_DMA(n) \ 730c454fd4eSMasakazu Mokuno ((0x13 + (n)) << 16) /* RW--V */ 731c454fd4eSMasakazu Mokuno #define PS3_AUDIO_KICK_EVENT_AUDIO_DMA0 (0x13 << 16) /* RW--V */ 732c454fd4eSMasakazu Mokuno #define PS3_AUDIO_KICK_EVENT_AUDIO_DMA1 (0x14 << 16) /* RW--V */ 733c454fd4eSMasakazu Mokuno #define PS3_AUDIO_KICK_EVENT_AUDIO_DMA2 (0x15 << 16) /* RW--V */ 734c454fd4eSMasakazu Mokuno #define PS3_AUDIO_KICK_EVENT_AUDIO_DMA3 (0x16 << 16) /* RW--V */ 735c454fd4eSMasakazu Mokuno #define PS3_AUDIO_KICK_EVENT_AUDIO_DMA4 (0x17 << 16) /* RW--V */ 736c454fd4eSMasakazu Mokuno #define PS3_AUDIO_KICK_EVENT_AUDIO_DMA5 (0x18 << 16) /* RW--V */ 737c454fd4eSMasakazu Mokuno #define PS3_AUDIO_KICK_EVENT_AUDIO_DMA6 (0x19 << 16) /* RW--V */ 738c454fd4eSMasakazu Mokuno #define PS3_AUDIO_KICK_EVENT_AUDIO_DMA7 (0x1A << 16) /* RW--V */ 739c454fd4eSMasakazu Mokuno #define PS3_AUDIO_KICK_EVENT_AUDIO_DMA8 (0x1B << 16) /* RW--V */ 740c454fd4eSMasakazu Mokuno #define PS3_AUDIO_KICK_EVENT_AUDIO_DMA9 (0x1C << 16) /* RW--V */ 741c454fd4eSMasakazu Mokuno 742c454fd4eSMasakazu Mokuno /* 743c454fd4eSMasakazu Mokuno The STATUS field can be used to monitor the progress of a DMA request. 744c454fd4eSMasakazu Mokuno DONE indicates the previous request has completed. 745c454fd4eSMasakazu Mokuno EVENT indicates that the DMA engine is waiting for the EVENT to occur. 746c454fd4eSMasakazu Mokuno PENDING indicates that the DMA engine has not started processing this 74725985edcSLucas De Marchi request, but the EVENT has occurred. 748c454fd4eSMasakazu Mokuno DMA indicates that the data transfer is in progress. 749c454fd4eSMasakazu Mokuno NOTIFY indicates that the notifier signalling end of transfer is being written. 750c454fd4eSMasakazu Mokuno CLEAR indicated that the previous transfer was cleared. 751c454fd4eSMasakazu Mokuno ERROR indicates the previous transfer requested an unsupported 752c454fd4eSMasakazu Mokuno source/destination combination. 753c454fd4eSMasakazu Mokuno */ 754c454fd4eSMasakazu Mokuno 755c454fd4eSMasakazu Mokuno #define PS3_AUDIO_KICK_STATUS_MASK (0x7 << 24) /* R-IVF */ 756c454fd4eSMasakazu Mokuno #define PS3_AUDIO_KICK_STATUS_DONE (0x0 << 24) /* R-I-V */ 757c454fd4eSMasakazu Mokuno #define PS3_AUDIO_KICK_STATUS_EVENT (0x1 << 24) /* R---V */ 758c454fd4eSMasakazu Mokuno #define PS3_AUDIO_KICK_STATUS_PENDING (0x2 << 24) /* R---V */ 759c454fd4eSMasakazu Mokuno #define PS3_AUDIO_KICK_STATUS_DMA (0x3 << 24) /* R---V */ 760c454fd4eSMasakazu Mokuno #define PS3_AUDIO_KICK_STATUS_NOTIFY (0x4 << 24) /* R---V */ 761c454fd4eSMasakazu Mokuno #define PS3_AUDIO_KICK_STATUS_CLEAR (0x5 << 24) /* R---V */ 762c454fd4eSMasakazu Mokuno #define PS3_AUDIO_KICK_STATUS_ERROR (0x6 << 24) /* R---V */ 763c454fd4eSMasakazu Mokuno 764c454fd4eSMasakazu Mokuno /* 765c454fd4eSMasakazu Mokuno The PS3_AUDIO_SOURCE register specifies the source address for transfers. 766c454fd4eSMasakazu Mokuno 767c454fd4eSMasakazu Mokuno 768c454fd4eSMasakazu Mokuno 31 24 23 16 15 8 7 0 769c454fd4eSMasakazu Mokuno +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+ 770c454fd4eSMasakazu Mokuno | START |0 0 0 0 0|TAR| SOURCE 771c454fd4eSMasakazu Mokuno +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+ 772c454fd4eSMasakazu Mokuno */ 773c454fd4eSMasakazu Mokuno 774c454fd4eSMasakazu Mokuno /* 775c454fd4eSMasakazu Mokuno The Audio DMA engine uses 128-byte transfers, thus the address must be aligned 776c454fd4eSMasakazu Mokuno to a 128 byte boundary. The low seven bits are assumed to be 0. 777c454fd4eSMasakazu Mokuno */ 778c454fd4eSMasakazu Mokuno 779c454fd4eSMasakazu Mokuno #define PS3_AUDIO_SOURCE_START_MASK (0x01FFFFFF << 7) /* RWIUF */ 780c454fd4eSMasakazu Mokuno 781c454fd4eSMasakazu Mokuno /* 782c454fd4eSMasakazu Mokuno The TARGET field specifies the memory space containing the source address. 783c454fd4eSMasakazu Mokuno */ 784c454fd4eSMasakazu Mokuno 785c454fd4eSMasakazu Mokuno #define PS3_AUDIO_SOURCE_TARGET_MASK (3 << 0) /* RWIVF */ 786c454fd4eSMasakazu Mokuno #define PS3_AUDIO_SOURCE_TARGET_SYSTEM_MEMORY (2 << 0) /* RW--V */ 787c454fd4eSMasakazu Mokuno 788c454fd4eSMasakazu Mokuno /* 789c454fd4eSMasakazu Mokuno The PS3_AUDIO_DEST register specifies the destination address for transfers. 790c454fd4eSMasakazu Mokuno 791c454fd4eSMasakazu Mokuno 792c454fd4eSMasakazu Mokuno 31 24 23 16 15 8 7 0 793c454fd4eSMasakazu Mokuno +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+ 794c454fd4eSMasakazu Mokuno | START |0 0 0 0 0|TAR| DEST 795c454fd4eSMasakazu Mokuno +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+ 796c454fd4eSMasakazu Mokuno */ 797c454fd4eSMasakazu Mokuno 798c454fd4eSMasakazu Mokuno /* 799c454fd4eSMasakazu Mokuno The Audio DMA engine uses 128-byte transfers, thus the address must be aligned 800c454fd4eSMasakazu Mokuno to a 128 byte boundary. The low seven bits are assumed to be 0. 801c454fd4eSMasakazu Mokuno */ 802c454fd4eSMasakazu Mokuno 803c454fd4eSMasakazu Mokuno #define PS3_AUDIO_DEST_START_MASK (0x01FFFFFF << 7) /* RWIUF */ 804c454fd4eSMasakazu Mokuno 805c454fd4eSMasakazu Mokuno /* 806c454fd4eSMasakazu Mokuno The TARGET field specifies the memory space containing the destination address 807c454fd4eSMasakazu Mokuno AUDIOFIFO = Audio WriteData FIFO, 808c454fd4eSMasakazu Mokuno */ 809c454fd4eSMasakazu Mokuno 810c454fd4eSMasakazu Mokuno #define PS3_AUDIO_DEST_TARGET_MASK (3 << 0) /* RWIVF */ 811c454fd4eSMasakazu Mokuno #define PS3_AUDIO_DEST_TARGET_AUDIOFIFO (1 << 0) /* RW--V */ 812c454fd4eSMasakazu Mokuno 813c454fd4eSMasakazu Mokuno /* 814c454fd4eSMasakazu Mokuno PS3_AUDIO_DMASIZE specifies the number of 128-byte blocks + 1 to transfer. 81525985edcSLucas De Marchi So a value of 0 means 128-bytes will get transferred. 816c454fd4eSMasakazu Mokuno 817c454fd4eSMasakazu Mokuno 818c454fd4eSMasakazu Mokuno 31 24 23 16 15 8 7 0 819c454fd4eSMasakazu Mokuno +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+ 820c454fd4eSMasakazu Mokuno |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| BLOCKS | DMASIZE 821c454fd4eSMasakazu Mokuno +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+ 822c454fd4eSMasakazu Mokuno */ 823c454fd4eSMasakazu Mokuno 824c454fd4eSMasakazu Mokuno 825c454fd4eSMasakazu Mokuno #define PS3_AUDIO_DMASIZE_BLOCKS_MASK (0x7f << 0) /* RWIUF */ 826c454fd4eSMasakazu Mokuno 827c454fd4eSMasakazu Mokuno /* 828c454fd4eSMasakazu Mokuno * source/destination address for internal fifos 829c454fd4eSMasakazu Mokuno */ 830c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_3W_LDATA(n) (0x1000 + (0x100 * (n))) 831c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_3W_RDATA(n) (0x1080 + (0x100 * (n))) 832c454fd4eSMasakazu Mokuno 833c454fd4eSMasakazu Mokuno #define PS3_AUDIO_AO_SPD_DATA(n) (0x2000 + (0x400 * (n))) 834c454fd4eSMasakazu Mokuno 835c454fd4eSMasakazu Mokuno 836c454fd4eSMasakazu Mokuno /* 837c454fd4eSMasakazu Mokuno * field attiribute 838c454fd4eSMasakazu Mokuno * 839c454fd4eSMasakazu Mokuno * Read 840c454fd4eSMasakazu Mokuno * ' ' = Other Information 841c454fd4eSMasakazu Mokuno * '-' = Field is part of a write-only register 842c454fd4eSMasakazu Mokuno * 'C' = Value read is always the same, constant value line follows (C) 843c454fd4eSMasakazu Mokuno * 'R' = Value is read 844c454fd4eSMasakazu Mokuno * 845c454fd4eSMasakazu Mokuno * Write 846c454fd4eSMasakazu Mokuno * ' ' = Other Information 847c454fd4eSMasakazu Mokuno * '-' = Must not be written (D), value ignored when written (R,A,F) 848c454fd4eSMasakazu Mokuno * 'W' = Can be written 849c454fd4eSMasakazu Mokuno * 850c454fd4eSMasakazu Mokuno * Internal State 851c454fd4eSMasakazu Mokuno * ' ' = Other Information 852c454fd4eSMasakazu Mokuno * '-' = No internal state 853c454fd4eSMasakazu Mokuno * 'X' = Internal state, initial value is unknown 854c454fd4eSMasakazu Mokuno * 'I' = Internal state, initial value is known and follows (I) 855c454fd4eSMasakazu Mokuno * 856c454fd4eSMasakazu Mokuno * Declaration/Size 857c454fd4eSMasakazu Mokuno * ' ' = Other Information 858c454fd4eSMasakazu Mokuno * '-' = Does Not Apply 859c454fd4eSMasakazu Mokuno * 'V' = Type is void 860c454fd4eSMasakazu Mokuno * 'U' = Type is unsigned integer 861c454fd4eSMasakazu Mokuno * 'S' = Type is signed integer 862c454fd4eSMasakazu Mokuno * 'F' = Type is IEEE floating point 863c454fd4eSMasakazu Mokuno * '1' = Byte size (008) 864c454fd4eSMasakazu Mokuno * '2' = Short size (016) 865c454fd4eSMasakazu Mokuno * '3' = Three byte size (024) 866c454fd4eSMasakazu Mokuno * '4' = Word size (032) 867c454fd4eSMasakazu Mokuno * '8' = Double size (064) 868c454fd4eSMasakazu Mokuno * 869c454fd4eSMasakazu Mokuno * Define Indicator 870c454fd4eSMasakazu Mokuno * ' ' = Other Information 871c454fd4eSMasakazu Mokuno * 'D' = Device 872c454fd4eSMasakazu Mokuno * 'M' = Memory 873c454fd4eSMasakazu Mokuno * 'R' = Register 874c454fd4eSMasakazu Mokuno * 'A' = Array of Registers 875c454fd4eSMasakazu Mokuno * 'F' = Field 876c454fd4eSMasakazu Mokuno * 'V' = Value 877c454fd4eSMasakazu Mokuno * 'T' = Task 878c454fd4eSMasakazu Mokuno */ 879c454fd4eSMasakazu Mokuno 880