1 /* 2 * Driver for Digigram VX222 V2/Mic soundcards 3 * 4 * VX222-specific low-level routines 5 * 6 * Copyright (c) 2002 by Takashi Iwai <tiwai@suse.de> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 21 */ 22 23 #include <linux/delay.h> 24 #include <linux/device.h> 25 #include <linux/firmware.h> 26 #include <linux/mutex.h> 27 #include <linux/io.h> 28 29 #include <sound/core.h> 30 #include <sound/control.h> 31 #include <sound/tlv.h> 32 #include "vx222.h" 33 34 35 static int vx2_reg_offset[VX_REG_MAX] = { 36 [VX_ICR] = 0x00, 37 [VX_CVR] = 0x04, 38 [VX_ISR] = 0x08, 39 [VX_IVR] = 0x0c, 40 [VX_RXH] = 0x14, 41 [VX_RXM] = 0x18, 42 [VX_RXL] = 0x1c, 43 [VX_DMA] = 0x10, 44 [VX_CDSP] = 0x20, 45 [VX_CFG] = 0x24, 46 [VX_RUER] = 0x28, 47 [VX_DATA] = 0x2c, 48 [VX_STATUS] = 0x30, 49 [VX_LOFREQ] = 0x34, 50 [VX_HIFREQ] = 0x38, 51 [VX_CSUER] = 0x3c, 52 [VX_SELMIC] = 0x40, 53 [VX_COMPOT] = 0x44, // Write: POTENTIOMETER ; Read: COMPRESSION LEVEL activate 54 [VX_SCOMPR] = 0x48, // Read: COMPRESSION THRESHOLD activate 55 [VX_GLIMIT] = 0x4c, // Read: LEVEL LIMITATION activate 56 [VX_INTCSR] = 0x4c, // VX_INTCSR_REGISTER_OFFSET 57 [VX_CNTRL] = 0x50, // VX_CNTRL_REGISTER_OFFSET 58 [VX_GPIOC] = 0x54, // VX_GPIOC (new with PLX9030) 59 }; 60 61 static int vx2_reg_index[VX_REG_MAX] = { 62 [VX_ICR] = 1, 63 [VX_CVR] = 1, 64 [VX_ISR] = 1, 65 [VX_IVR] = 1, 66 [VX_RXH] = 1, 67 [VX_RXM] = 1, 68 [VX_RXL] = 1, 69 [VX_DMA] = 1, 70 [VX_CDSP] = 1, 71 [VX_CFG] = 1, 72 [VX_RUER] = 1, 73 [VX_DATA] = 1, 74 [VX_STATUS] = 1, 75 [VX_LOFREQ] = 1, 76 [VX_HIFREQ] = 1, 77 [VX_CSUER] = 1, 78 [VX_SELMIC] = 1, 79 [VX_COMPOT] = 1, 80 [VX_SCOMPR] = 1, 81 [VX_GLIMIT] = 1, 82 [VX_INTCSR] = 0, /* on the PLX */ 83 [VX_CNTRL] = 0, /* on the PLX */ 84 [VX_GPIOC] = 0, /* on the PLX */ 85 }; 86 87 static inline unsigned long vx2_reg_addr(struct vx_core *_chip, int reg) 88 { 89 struct snd_vx222 *chip = to_vx222(_chip); 90 return chip->port[vx2_reg_index[reg]] + vx2_reg_offset[reg]; 91 } 92 93 /** 94 * snd_vx_inb - read a byte from the register 95 * @chip: VX core instance 96 * @offset: register enum 97 */ 98 static unsigned char vx2_inb(struct vx_core *chip, int offset) 99 { 100 return inb(vx2_reg_addr(chip, offset)); 101 } 102 103 /** 104 * snd_vx_outb - write a byte on the register 105 * @chip: VX core instance 106 * @offset: the register offset 107 * @val: the value to write 108 */ 109 static void vx2_outb(struct vx_core *chip, int offset, unsigned char val) 110 { 111 outb(val, vx2_reg_addr(chip, offset)); 112 /* 113 dev_dbg(chip->card->dev, "outb: %x -> %x\n", val, vx2_reg_addr(chip, offset)); 114 */ 115 } 116 117 /** 118 * snd_vx_inl - read a 32bit word from the register 119 * @chip: VX core instance 120 * @offset: register enum 121 */ 122 static unsigned int vx2_inl(struct vx_core *chip, int offset) 123 { 124 return inl(vx2_reg_addr(chip, offset)); 125 } 126 127 /** 128 * snd_vx_outl - write a 32bit word on the register 129 * @chip: VX core instance 130 * @offset: the register enum 131 * @val: the value to write 132 */ 133 static void vx2_outl(struct vx_core *chip, int offset, unsigned int val) 134 { 135 /* 136 dev_dbg(chip->card->dev, "outl: %x -> %x\n", val, vx2_reg_addr(chip, offset)); 137 */ 138 outl(val, vx2_reg_addr(chip, offset)); 139 } 140 141 /* 142 * redefine macros to call directly 143 */ 144 #undef vx_inb 145 #define vx_inb(chip,reg) vx2_inb((struct vx_core*)(chip), VX_##reg) 146 #undef vx_outb 147 #define vx_outb(chip,reg,val) vx2_outb((struct vx_core*)(chip), VX_##reg, val) 148 #undef vx_inl 149 #define vx_inl(chip,reg) vx2_inl((struct vx_core*)(chip), VX_##reg) 150 #undef vx_outl 151 #define vx_outl(chip,reg,val) vx2_outl((struct vx_core*)(chip), VX_##reg, val) 152 153 154 /* 155 * vx_reset_dsp - reset the DSP 156 */ 157 158 #define XX_DSP_RESET_WAIT_TIME 2 /* ms */ 159 160 static void vx2_reset_dsp(struct vx_core *_chip) 161 { 162 struct snd_vx222 *chip = to_vx222(_chip); 163 164 /* set the reset dsp bit to 0 */ 165 vx_outl(chip, CDSP, chip->regCDSP & ~VX_CDSP_DSP_RESET_MASK); 166 167 mdelay(XX_DSP_RESET_WAIT_TIME); 168 169 chip->regCDSP |= VX_CDSP_DSP_RESET_MASK; 170 /* set the reset dsp bit to 1 */ 171 vx_outl(chip, CDSP, chip->regCDSP); 172 } 173 174 175 static int vx2_test_xilinx(struct vx_core *_chip) 176 { 177 struct snd_vx222 *chip = to_vx222(_chip); 178 unsigned int data; 179 180 dev_dbg(_chip->card->dev, "testing xilinx...\n"); 181 /* This test uses several write/read sequences on TEST0 and TEST1 bits 182 * to figure out whever or not the xilinx was correctly loaded 183 */ 184 185 /* We write 1 on CDSP.TEST0. We should get 0 on STATUS.TEST0. */ 186 vx_outl(chip, CDSP, chip->regCDSP | VX_CDSP_TEST0_MASK); 187 vx_inl(chip, ISR); 188 data = vx_inl(chip, STATUS); 189 if ((data & VX_STATUS_VAL_TEST0_MASK) == VX_STATUS_VAL_TEST0_MASK) { 190 dev_dbg(_chip->card->dev, "bad!\n"); 191 return -ENODEV; 192 } 193 194 /* We write 0 on CDSP.TEST0. We should get 1 on STATUS.TEST0. */ 195 vx_outl(chip, CDSP, chip->regCDSP & ~VX_CDSP_TEST0_MASK); 196 vx_inl(chip, ISR); 197 data = vx_inl(chip, STATUS); 198 if (! (data & VX_STATUS_VAL_TEST0_MASK)) { 199 dev_dbg(_chip->card->dev, "bad! #2\n"); 200 return -ENODEV; 201 } 202 203 if (_chip->type == VX_TYPE_BOARD) { 204 /* not implemented on VX_2_BOARDS */ 205 /* We write 1 on CDSP.TEST1. We should get 0 on STATUS.TEST1. */ 206 vx_outl(chip, CDSP, chip->regCDSP | VX_CDSP_TEST1_MASK); 207 vx_inl(chip, ISR); 208 data = vx_inl(chip, STATUS); 209 if ((data & VX_STATUS_VAL_TEST1_MASK) == VX_STATUS_VAL_TEST1_MASK) { 210 dev_dbg(_chip->card->dev, "bad! #3\n"); 211 return -ENODEV; 212 } 213 214 /* We write 0 on CDSP.TEST1. We should get 1 on STATUS.TEST1. */ 215 vx_outl(chip, CDSP, chip->regCDSP & ~VX_CDSP_TEST1_MASK); 216 vx_inl(chip, ISR); 217 data = vx_inl(chip, STATUS); 218 if (! (data & VX_STATUS_VAL_TEST1_MASK)) { 219 dev_dbg(_chip->card->dev, "bad! #4\n"); 220 return -ENODEV; 221 } 222 } 223 dev_dbg(_chip->card->dev, "ok, xilinx fine.\n"); 224 return 0; 225 } 226 227 228 /** 229 * vx_setup_pseudo_dma - set up the pseudo dma read/write mode. 230 * @chip: VX core instance 231 * @do_write: 0 = read, 1 = set up for DMA write 232 */ 233 static void vx2_setup_pseudo_dma(struct vx_core *chip, int do_write) 234 { 235 /* Interrupt mode and HREQ pin enabled for host transmit data transfers 236 * (in case of the use of the pseudo-dma facility). 237 */ 238 vx_outl(chip, ICR, do_write ? ICR_TREQ : ICR_RREQ); 239 240 /* Reset the pseudo-dma register (in case of the use of the 241 * pseudo-dma facility). 242 */ 243 vx_outl(chip, RESET_DMA, 0); 244 } 245 246 /* 247 * vx_release_pseudo_dma - disable the pseudo-DMA mode 248 */ 249 static inline void vx2_release_pseudo_dma(struct vx_core *chip) 250 { 251 /* HREQ pin disabled. */ 252 vx_outl(chip, ICR, 0); 253 } 254 255 256 257 /* pseudo-dma write */ 258 static void vx2_dma_write(struct vx_core *chip, struct snd_pcm_runtime *runtime, 259 struct vx_pipe *pipe, int count) 260 { 261 unsigned long port = vx2_reg_addr(chip, VX_DMA); 262 int offset = pipe->hw_ptr; 263 u32 *addr = (u32 *)(runtime->dma_area + offset); 264 265 if (snd_BUG_ON(count % 4)) 266 return; 267 268 vx2_setup_pseudo_dma(chip, 1); 269 270 /* Transfer using pseudo-dma. 271 */ 272 if (offset + count >= pipe->buffer_bytes) { 273 int length = pipe->buffer_bytes - offset; 274 count -= length; 275 length >>= 2; /* in 32bit words */ 276 /* Transfer using pseudo-dma. */ 277 for (; length > 0; length--) { 278 outl(*addr, port); 279 addr++; 280 } 281 addr = (u32 *)runtime->dma_area; 282 pipe->hw_ptr = 0; 283 } 284 pipe->hw_ptr += count; 285 count >>= 2; /* in 32bit words */ 286 /* Transfer using pseudo-dma. */ 287 for (; count > 0; count--) { 288 outl(*addr, port); 289 addr++; 290 } 291 292 vx2_release_pseudo_dma(chip); 293 } 294 295 296 /* pseudo dma read */ 297 static void vx2_dma_read(struct vx_core *chip, struct snd_pcm_runtime *runtime, 298 struct vx_pipe *pipe, int count) 299 { 300 int offset = pipe->hw_ptr; 301 u32 *addr = (u32 *)(runtime->dma_area + offset); 302 unsigned long port = vx2_reg_addr(chip, VX_DMA); 303 304 if (snd_BUG_ON(count % 4)) 305 return; 306 307 vx2_setup_pseudo_dma(chip, 0); 308 /* Transfer using pseudo-dma. 309 */ 310 if (offset + count >= pipe->buffer_bytes) { 311 int length = pipe->buffer_bytes - offset; 312 count -= length; 313 length >>= 2; /* in 32bit words */ 314 /* Transfer using pseudo-dma. */ 315 for (; length > 0; length--) 316 *addr++ = inl(port); 317 addr = (u32 *)runtime->dma_area; 318 pipe->hw_ptr = 0; 319 } 320 pipe->hw_ptr += count; 321 count >>= 2; /* in 32bit words */ 322 /* Transfer using pseudo-dma. */ 323 for (; count > 0; count--) 324 *addr++ = inl(port); 325 326 vx2_release_pseudo_dma(chip); 327 } 328 329 #define VX_XILINX_RESET_MASK 0x40000000 330 #define VX_USERBIT0_MASK 0x00000004 331 #define VX_USERBIT1_MASK 0x00000020 332 #define VX_CNTRL_REGISTER_VALUE 0x00172012 333 334 /* 335 * transfer counts bits to PLX 336 */ 337 static int put_xilinx_data(struct vx_core *chip, unsigned int port, unsigned int counts, unsigned char data) 338 { 339 unsigned int i; 340 341 for (i = 0; i < counts; i++) { 342 unsigned int val; 343 344 /* set the clock bit to 0. */ 345 val = VX_CNTRL_REGISTER_VALUE & ~VX_USERBIT0_MASK; 346 vx2_outl(chip, port, val); 347 vx2_inl(chip, port); 348 udelay(1); 349 350 if (data & (1 << i)) 351 val |= VX_USERBIT1_MASK; 352 else 353 val &= ~VX_USERBIT1_MASK; 354 vx2_outl(chip, port, val); 355 vx2_inl(chip, port); 356 357 /* set the clock bit to 1. */ 358 val |= VX_USERBIT0_MASK; 359 vx2_outl(chip, port, val); 360 vx2_inl(chip, port); 361 udelay(1); 362 } 363 return 0; 364 } 365 366 /* 367 * load the xilinx image 368 */ 369 static int vx2_load_xilinx_binary(struct vx_core *chip, const struct firmware *xilinx) 370 { 371 unsigned int i; 372 unsigned int port; 373 const unsigned char *image; 374 375 /* XILINX reset (wait at least 1 millisecond between reset on and off). */ 376 vx_outl(chip, CNTRL, VX_CNTRL_REGISTER_VALUE | VX_XILINX_RESET_MASK); 377 vx_inl(chip, CNTRL); 378 msleep(10); 379 vx_outl(chip, CNTRL, VX_CNTRL_REGISTER_VALUE); 380 vx_inl(chip, CNTRL); 381 msleep(10); 382 383 if (chip->type == VX_TYPE_BOARD) 384 port = VX_CNTRL; 385 else 386 port = VX_GPIOC; /* VX222 V2 and VX222_MIC_BOARD with new PLX9030 use this register */ 387 388 image = xilinx->data; 389 for (i = 0; i < xilinx->size; i++, image++) { 390 if (put_xilinx_data(chip, port, 8, *image) < 0) 391 return -EINVAL; 392 /* don't take too much time in this loop... */ 393 cond_resched(); 394 } 395 put_xilinx_data(chip, port, 4, 0xff); /* end signature */ 396 397 msleep(200); 398 399 /* test after loading (is buggy with VX222) */ 400 if (chip->type != VX_TYPE_BOARD) { 401 /* Test if load successful: test bit 8 of register GPIOC (VX222: use CNTRL) ! */ 402 i = vx_inl(chip, GPIOC); 403 if (i & 0x0100) 404 return 0; 405 dev_err(chip->card->dev, 406 "xilinx test failed after load, GPIOC=0x%x\n", i); 407 return -EINVAL; 408 } 409 410 return 0; 411 } 412 413 414 /* 415 * load the boot/dsp images 416 */ 417 static int vx2_load_dsp(struct vx_core *vx, int index, const struct firmware *dsp) 418 { 419 int err; 420 421 switch (index) { 422 case 1: 423 /* xilinx image */ 424 if ((err = vx2_load_xilinx_binary(vx, dsp)) < 0) 425 return err; 426 if ((err = vx2_test_xilinx(vx)) < 0) 427 return err; 428 return 0; 429 case 2: 430 /* DSP boot */ 431 return snd_vx_dsp_boot(vx, dsp); 432 case 3: 433 /* DSP image */ 434 return snd_vx_dsp_load(vx, dsp); 435 default: 436 snd_BUG(); 437 return -EINVAL; 438 } 439 } 440 441 442 /* 443 * vx_test_and_ack - test and acknowledge interrupt 444 * 445 * called from irq hander, too 446 * 447 * spinlock held! 448 */ 449 static int vx2_test_and_ack(struct vx_core *chip) 450 { 451 /* not booted yet? */ 452 if (! (chip->chip_status & VX_STAT_XILINX_LOADED)) 453 return -ENXIO; 454 455 if (! (vx_inl(chip, STATUS) & VX_STATUS_MEMIRQ_MASK)) 456 return -EIO; 457 458 /* ok, interrupts generated, now ack it */ 459 /* set ACQUIT bit up and down */ 460 vx_outl(chip, STATUS, 0); 461 /* useless read just to spend some time and maintain 462 * the ACQUIT signal up for a while ( a bus cycle ) 463 */ 464 vx_inl(chip, STATUS); 465 /* ack */ 466 vx_outl(chip, STATUS, VX_STATUS_MEMIRQ_MASK); 467 /* useless read just to spend some time and maintain 468 * the ACQUIT signal up for a while ( a bus cycle ) */ 469 vx_inl(chip, STATUS); 470 /* clear */ 471 vx_outl(chip, STATUS, 0); 472 473 return 0; 474 } 475 476 477 /* 478 * vx_validate_irq - enable/disable IRQ 479 */ 480 static void vx2_validate_irq(struct vx_core *_chip, int enable) 481 { 482 struct snd_vx222 *chip = to_vx222(_chip); 483 484 /* Set the interrupt enable bit to 1 in CDSP register */ 485 if (enable) { 486 /* Set the PCI interrupt enable bit to 1.*/ 487 vx_outl(chip, INTCSR, VX_INTCSR_VALUE|VX_PCI_INTERRUPT_MASK); 488 chip->regCDSP |= VX_CDSP_VALID_IRQ_MASK; 489 } else { 490 /* Set the PCI interrupt enable bit to 0. */ 491 vx_outl(chip, INTCSR, VX_INTCSR_VALUE&~VX_PCI_INTERRUPT_MASK); 492 chip->regCDSP &= ~VX_CDSP_VALID_IRQ_MASK; 493 } 494 vx_outl(chip, CDSP, chip->regCDSP); 495 } 496 497 498 /* 499 * write an AKM codec data (24bit) 500 */ 501 static void vx2_write_codec_reg(struct vx_core *chip, unsigned int data) 502 { 503 unsigned int i; 504 505 vx_inl(chip, HIFREQ); 506 507 /* We have to send 24 bits (3 x 8 bits). Start with most signif. Bit */ 508 for (i = 0; i < 24; i++, data <<= 1) 509 vx_outl(chip, DATA, ((data & 0x800000) ? VX_DATA_CODEC_MASK : 0)); 510 /* Terminate access to codec registers */ 511 vx_inl(chip, RUER); 512 } 513 514 515 #define AKM_CODEC_POWER_CONTROL_CMD 0xA007 516 #define AKM_CODEC_RESET_ON_CMD 0xA100 517 #define AKM_CODEC_RESET_OFF_CMD 0xA103 518 #define AKM_CODEC_CLOCK_FORMAT_CMD 0xA240 519 #define AKM_CODEC_MUTE_CMD 0xA38D 520 #define AKM_CODEC_UNMUTE_CMD 0xA30D 521 #define AKM_CODEC_LEFT_LEVEL_CMD 0xA400 522 #define AKM_CODEC_RIGHT_LEVEL_CMD 0xA500 523 524 static const u8 vx2_akm_gains_lut[VX2_AKM_LEVEL_MAX+1] = { 525 0x7f, // [000] = +0.000 dB -> AKM(0x7f) = +0.000 dB error(+0.000 dB) 526 0x7d, // [001] = -0.500 dB -> AKM(0x7d) = -0.572 dB error(-0.072 dB) 527 0x7c, // [002] = -1.000 dB -> AKM(0x7c) = -0.873 dB error(+0.127 dB) 528 0x7a, // [003] = -1.500 dB -> AKM(0x7a) = -1.508 dB error(-0.008 dB) 529 0x79, // [004] = -2.000 dB -> AKM(0x79) = -1.844 dB error(+0.156 dB) 530 0x77, // [005] = -2.500 dB -> AKM(0x77) = -2.557 dB error(-0.057 dB) 531 0x76, // [006] = -3.000 dB -> AKM(0x76) = -2.937 dB error(+0.063 dB) 532 0x75, // [007] = -3.500 dB -> AKM(0x75) = -3.334 dB error(+0.166 dB) 533 0x73, // [008] = -4.000 dB -> AKM(0x73) = -4.188 dB error(-0.188 dB) 534 0x72, // [009] = -4.500 dB -> AKM(0x72) = -4.648 dB error(-0.148 dB) 535 0x71, // [010] = -5.000 dB -> AKM(0x71) = -5.134 dB error(-0.134 dB) 536 0x70, // [011] = -5.500 dB -> AKM(0x70) = -5.649 dB error(-0.149 dB) 537 0x6f, // [012] = -6.000 dB -> AKM(0x6f) = -6.056 dB error(-0.056 dB) 538 0x6d, // [013] = -6.500 dB -> AKM(0x6d) = -6.631 dB error(-0.131 dB) 539 0x6c, // [014] = -7.000 dB -> AKM(0x6c) = -6.933 dB error(+0.067 dB) 540 0x6a, // [015] = -7.500 dB -> AKM(0x6a) = -7.571 dB error(-0.071 dB) 541 0x69, // [016] = -8.000 dB -> AKM(0x69) = -7.909 dB error(+0.091 dB) 542 0x67, // [017] = -8.500 dB -> AKM(0x67) = -8.626 dB error(-0.126 dB) 543 0x66, // [018] = -9.000 dB -> AKM(0x66) = -9.008 dB error(-0.008 dB) 544 0x65, // [019] = -9.500 dB -> AKM(0x65) = -9.407 dB error(+0.093 dB) 545 0x64, // [020] = -10.000 dB -> AKM(0x64) = -9.826 dB error(+0.174 dB) 546 0x62, // [021] = -10.500 dB -> AKM(0x62) = -10.730 dB error(-0.230 dB) 547 0x61, // [022] = -11.000 dB -> AKM(0x61) = -11.219 dB error(-0.219 dB) 548 0x60, // [023] = -11.500 dB -> AKM(0x60) = -11.738 dB error(-0.238 dB) 549 0x5f, // [024] = -12.000 dB -> AKM(0x5f) = -12.149 dB error(-0.149 dB) 550 0x5e, // [025] = -12.500 dB -> AKM(0x5e) = -12.434 dB error(+0.066 dB) 551 0x5c, // [026] = -13.000 dB -> AKM(0x5c) = -13.033 dB error(-0.033 dB) 552 0x5b, // [027] = -13.500 dB -> AKM(0x5b) = -13.350 dB error(+0.150 dB) 553 0x59, // [028] = -14.000 dB -> AKM(0x59) = -14.018 dB error(-0.018 dB) 554 0x58, // [029] = -14.500 dB -> AKM(0x58) = -14.373 dB error(+0.127 dB) 555 0x56, // [030] = -15.000 dB -> AKM(0x56) = -15.130 dB error(-0.130 dB) 556 0x55, // [031] = -15.500 dB -> AKM(0x55) = -15.534 dB error(-0.034 dB) 557 0x54, // [032] = -16.000 dB -> AKM(0x54) = -15.958 dB error(+0.042 dB) 558 0x53, // [033] = -16.500 dB -> AKM(0x53) = -16.404 dB error(+0.096 dB) 559 0x52, // [034] = -17.000 dB -> AKM(0x52) = -16.874 dB error(+0.126 dB) 560 0x51, // [035] = -17.500 dB -> AKM(0x51) = -17.371 dB error(+0.129 dB) 561 0x50, // [036] = -18.000 dB -> AKM(0x50) = -17.898 dB error(+0.102 dB) 562 0x4e, // [037] = -18.500 dB -> AKM(0x4e) = -18.605 dB error(-0.105 dB) 563 0x4d, // [038] = -19.000 dB -> AKM(0x4d) = -18.905 dB error(+0.095 dB) 564 0x4b, // [039] = -19.500 dB -> AKM(0x4b) = -19.538 dB error(-0.038 dB) 565 0x4a, // [040] = -20.000 dB -> AKM(0x4a) = -19.872 dB error(+0.128 dB) 566 0x48, // [041] = -20.500 dB -> AKM(0x48) = -20.583 dB error(-0.083 dB) 567 0x47, // [042] = -21.000 dB -> AKM(0x47) = -20.961 dB error(+0.039 dB) 568 0x46, // [043] = -21.500 dB -> AKM(0x46) = -21.356 dB error(+0.144 dB) 569 0x44, // [044] = -22.000 dB -> AKM(0x44) = -22.206 dB error(-0.206 dB) 570 0x43, // [045] = -22.500 dB -> AKM(0x43) = -22.664 dB error(-0.164 dB) 571 0x42, // [046] = -23.000 dB -> AKM(0x42) = -23.147 dB error(-0.147 dB) 572 0x41, // [047] = -23.500 dB -> AKM(0x41) = -23.659 dB error(-0.159 dB) 573 0x40, // [048] = -24.000 dB -> AKM(0x40) = -24.203 dB error(-0.203 dB) 574 0x3f, // [049] = -24.500 dB -> AKM(0x3f) = -24.635 dB error(-0.135 dB) 575 0x3e, // [050] = -25.000 dB -> AKM(0x3e) = -24.935 dB error(+0.065 dB) 576 0x3c, // [051] = -25.500 dB -> AKM(0x3c) = -25.569 dB error(-0.069 dB) 577 0x3b, // [052] = -26.000 dB -> AKM(0x3b) = -25.904 dB error(+0.096 dB) 578 0x39, // [053] = -26.500 dB -> AKM(0x39) = -26.615 dB error(-0.115 dB) 579 0x38, // [054] = -27.000 dB -> AKM(0x38) = -26.994 dB error(+0.006 dB) 580 0x37, // [055] = -27.500 dB -> AKM(0x37) = -27.390 dB error(+0.110 dB) 581 0x36, // [056] = -28.000 dB -> AKM(0x36) = -27.804 dB error(+0.196 dB) 582 0x34, // [057] = -28.500 dB -> AKM(0x34) = -28.699 dB error(-0.199 dB) 583 0x33, // [058] = -29.000 dB -> AKM(0x33) = -29.183 dB error(-0.183 dB) 584 0x32, // [059] = -29.500 dB -> AKM(0x32) = -29.696 dB error(-0.196 dB) 585 0x31, // [060] = -30.000 dB -> AKM(0x31) = -30.241 dB error(-0.241 dB) 586 0x31, // [061] = -30.500 dB -> AKM(0x31) = -30.241 dB error(+0.259 dB) 587 0x30, // [062] = -31.000 dB -> AKM(0x30) = -30.823 dB error(+0.177 dB) 588 0x2e, // [063] = -31.500 dB -> AKM(0x2e) = -31.610 dB error(-0.110 dB) 589 0x2d, // [064] = -32.000 dB -> AKM(0x2d) = -31.945 dB error(+0.055 dB) 590 0x2b, // [065] = -32.500 dB -> AKM(0x2b) = -32.659 dB error(-0.159 dB) 591 0x2a, // [066] = -33.000 dB -> AKM(0x2a) = -33.038 dB error(-0.038 dB) 592 0x29, // [067] = -33.500 dB -> AKM(0x29) = -33.435 dB error(+0.065 dB) 593 0x28, // [068] = -34.000 dB -> AKM(0x28) = -33.852 dB error(+0.148 dB) 594 0x27, // [069] = -34.500 dB -> AKM(0x27) = -34.289 dB error(+0.211 dB) 595 0x25, // [070] = -35.000 dB -> AKM(0x25) = -35.235 dB error(-0.235 dB) 596 0x24, // [071] = -35.500 dB -> AKM(0x24) = -35.750 dB error(-0.250 dB) 597 0x24, // [072] = -36.000 dB -> AKM(0x24) = -35.750 dB error(+0.250 dB) 598 0x23, // [073] = -36.500 dB -> AKM(0x23) = -36.297 dB error(+0.203 dB) 599 0x22, // [074] = -37.000 dB -> AKM(0x22) = -36.881 dB error(+0.119 dB) 600 0x21, // [075] = -37.500 dB -> AKM(0x21) = -37.508 dB error(-0.008 dB) 601 0x20, // [076] = -38.000 dB -> AKM(0x20) = -38.183 dB error(-0.183 dB) 602 0x1f, // [077] = -38.500 dB -> AKM(0x1f) = -38.726 dB error(-0.226 dB) 603 0x1e, // [078] = -39.000 dB -> AKM(0x1e) = -39.108 dB error(-0.108 dB) 604 0x1d, // [079] = -39.500 dB -> AKM(0x1d) = -39.507 dB error(-0.007 dB) 605 0x1c, // [080] = -40.000 dB -> AKM(0x1c) = -39.926 dB error(+0.074 dB) 606 0x1b, // [081] = -40.500 dB -> AKM(0x1b) = -40.366 dB error(+0.134 dB) 607 0x1a, // [082] = -41.000 dB -> AKM(0x1a) = -40.829 dB error(+0.171 dB) 608 0x19, // [083] = -41.500 dB -> AKM(0x19) = -41.318 dB error(+0.182 dB) 609 0x18, // [084] = -42.000 dB -> AKM(0x18) = -41.837 dB error(+0.163 dB) 610 0x17, // [085] = -42.500 dB -> AKM(0x17) = -42.389 dB error(+0.111 dB) 611 0x16, // [086] = -43.000 dB -> AKM(0x16) = -42.978 dB error(+0.022 dB) 612 0x15, // [087] = -43.500 dB -> AKM(0x15) = -43.610 dB error(-0.110 dB) 613 0x14, // [088] = -44.000 dB -> AKM(0x14) = -44.291 dB error(-0.291 dB) 614 0x14, // [089] = -44.500 dB -> AKM(0x14) = -44.291 dB error(+0.209 dB) 615 0x13, // [090] = -45.000 dB -> AKM(0x13) = -45.031 dB error(-0.031 dB) 616 0x12, // [091] = -45.500 dB -> AKM(0x12) = -45.840 dB error(-0.340 dB) 617 0x12, // [092] = -46.000 dB -> AKM(0x12) = -45.840 dB error(+0.160 dB) 618 0x11, // [093] = -46.500 dB -> AKM(0x11) = -46.731 dB error(-0.231 dB) 619 0x11, // [094] = -47.000 dB -> AKM(0x11) = -46.731 dB error(+0.269 dB) 620 0x10, // [095] = -47.500 dB -> AKM(0x10) = -47.725 dB error(-0.225 dB) 621 0x10, // [096] = -48.000 dB -> AKM(0x10) = -47.725 dB error(+0.275 dB) 622 0x0f, // [097] = -48.500 dB -> AKM(0x0f) = -48.553 dB error(-0.053 dB) 623 0x0e, // [098] = -49.000 dB -> AKM(0x0e) = -49.152 dB error(-0.152 dB) 624 0x0d, // [099] = -49.500 dB -> AKM(0x0d) = -49.796 dB error(-0.296 dB) 625 0x0d, // [100] = -50.000 dB -> AKM(0x0d) = -49.796 dB error(+0.204 dB) 626 0x0c, // [101] = -50.500 dB -> AKM(0x0c) = -50.491 dB error(+0.009 dB) 627 0x0b, // [102] = -51.000 dB -> AKM(0x0b) = -51.247 dB error(-0.247 dB) 628 0x0b, // [103] = -51.500 dB -> AKM(0x0b) = -51.247 dB error(+0.253 dB) 629 0x0a, // [104] = -52.000 dB -> AKM(0x0a) = -52.075 dB error(-0.075 dB) 630 0x0a, // [105] = -52.500 dB -> AKM(0x0a) = -52.075 dB error(+0.425 dB) 631 0x09, // [106] = -53.000 dB -> AKM(0x09) = -52.990 dB error(+0.010 dB) 632 0x09, // [107] = -53.500 dB -> AKM(0x09) = -52.990 dB error(+0.510 dB) 633 0x08, // [108] = -54.000 dB -> AKM(0x08) = -54.013 dB error(-0.013 dB) 634 0x08, // [109] = -54.500 dB -> AKM(0x08) = -54.013 dB error(+0.487 dB) 635 0x07, // [110] = -55.000 dB -> AKM(0x07) = -55.173 dB error(-0.173 dB) 636 0x07, // [111] = -55.500 dB -> AKM(0x07) = -55.173 dB error(+0.327 dB) 637 0x06, // [112] = -56.000 dB -> AKM(0x06) = -56.512 dB error(-0.512 dB) 638 0x06, // [113] = -56.500 dB -> AKM(0x06) = -56.512 dB error(-0.012 dB) 639 0x06, // [114] = -57.000 dB -> AKM(0x06) = -56.512 dB error(+0.488 dB) 640 0x05, // [115] = -57.500 dB -> AKM(0x05) = -58.095 dB error(-0.595 dB) 641 0x05, // [116] = -58.000 dB -> AKM(0x05) = -58.095 dB error(-0.095 dB) 642 0x05, // [117] = -58.500 dB -> AKM(0x05) = -58.095 dB error(+0.405 dB) 643 0x05, // [118] = -59.000 dB -> AKM(0x05) = -58.095 dB error(+0.905 dB) 644 0x04, // [119] = -59.500 dB -> AKM(0x04) = -60.034 dB error(-0.534 dB) 645 0x04, // [120] = -60.000 dB -> AKM(0x04) = -60.034 dB error(-0.034 dB) 646 0x04, // [121] = -60.500 dB -> AKM(0x04) = -60.034 dB error(+0.466 dB) 647 0x04, // [122] = -61.000 dB -> AKM(0x04) = -60.034 dB error(+0.966 dB) 648 0x03, // [123] = -61.500 dB -> AKM(0x03) = -62.532 dB error(-1.032 dB) 649 0x03, // [124] = -62.000 dB -> AKM(0x03) = -62.532 dB error(-0.532 dB) 650 0x03, // [125] = -62.500 dB -> AKM(0x03) = -62.532 dB error(-0.032 dB) 651 0x03, // [126] = -63.000 dB -> AKM(0x03) = -62.532 dB error(+0.468 dB) 652 0x03, // [127] = -63.500 dB -> AKM(0x03) = -62.532 dB error(+0.968 dB) 653 0x03, // [128] = -64.000 dB -> AKM(0x03) = -62.532 dB error(+1.468 dB) 654 0x02, // [129] = -64.500 dB -> AKM(0x02) = -66.054 dB error(-1.554 dB) 655 0x02, // [130] = -65.000 dB -> AKM(0x02) = -66.054 dB error(-1.054 dB) 656 0x02, // [131] = -65.500 dB -> AKM(0x02) = -66.054 dB error(-0.554 dB) 657 0x02, // [132] = -66.000 dB -> AKM(0x02) = -66.054 dB error(-0.054 dB) 658 0x02, // [133] = -66.500 dB -> AKM(0x02) = -66.054 dB error(+0.446 dB) 659 0x02, // [134] = -67.000 dB -> AKM(0x02) = -66.054 dB error(+0.946 dB) 660 0x02, // [135] = -67.500 dB -> AKM(0x02) = -66.054 dB error(+1.446 dB) 661 0x02, // [136] = -68.000 dB -> AKM(0x02) = -66.054 dB error(+1.946 dB) 662 0x02, // [137] = -68.500 dB -> AKM(0x02) = -66.054 dB error(+2.446 dB) 663 0x02, // [138] = -69.000 dB -> AKM(0x02) = -66.054 dB error(+2.946 dB) 664 0x01, // [139] = -69.500 dB -> AKM(0x01) = -72.075 dB error(-2.575 dB) 665 0x01, // [140] = -70.000 dB -> AKM(0x01) = -72.075 dB error(-2.075 dB) 666 0x01, // [141] = -70.500 dB -> AKM(0x01) = -72.075 dB error(-1.575 dB) 667 0x01, // [142] = -71.000 dB -> AKM(0x01) = -72.075 dB error(-1.075 dB) 668 0x01, // [143] = -71.500 dB -> AKM(0x01) = -72.075 dB error(-0.575 dB) 669 0x01, // [144] = -72.000 dB -> AKM(0x01) = -72.075 dB error(-0.075 dB) 670 0x01, // [145] = -72.500 dB -> AKM(0x01) = -72.075 dB error(+0.425 dB) 671 0x01, // [146] = -73.000 dB -> AKM(0x01) = -72.075 dB error(+0.925 dB) 672 0x00}; // [147] = -73.500 dB -> AKM(0x00) = mute error(+infini) 673 674 /* 675 * pseudo-codec write entry 676 */ 677 static void vx2_write_akm(struct vx_core *chip, int reg, unsigned int data) 678 { 679 unsigned int val; 680 681 if (reg == XX_CODEC_DAC_CONTROL_REGISTER) { 682 vx2_write_codec_reg(chip, data ? AKM_CODEC_MUTE_CMD : AKM_CODEC_UNMUTE_CMD); 683 return; 684 } 685 686 /* `data' is a value between 0x0 and VX2_AKM_LEVEL_MAX = 0x093, in the case of the AKM codecs, we need 687 a look up table, as there is no linear matching between the driver codec values 688 and the real dBu value 689 */ 690 if (snd_BUG_ON(data >= sizeof(vx2_akm_gains_lut))) 691 return; 692 693 switch (reg) { 694 case XX_CODEC_LEVEL_LEFT_REGISTER: 695 val = AKM_CODEC_LEFT_LEVEL_CMD; 696 break; 697 case XX_CODEC_LEVEL_RIGHT_REGISTER: 698 val = AKM_CODEC_RIGHT_LEVEL_CMD; 699 break; 700 default: 701 snd_BUG(); 702 return; 703 } 704 val |= vx2_akm_gains_lut[data]; 705 706 vx2_write_codec_reg(chip, val); 707 } 708 709 710 /* 711 * write codec bit for old VX222 board 712 */ 713 static void vx2_old_write_codec_bit(struct vx_core *chip, int codec, unsigned int data) 714 { 715 int i; 716 717 /* activate access to codec registers */ 718 vx_inl(chip, HIFREQ); 719 720 for (i = 0; i < 24; i++, data <<= 1) 721 vx_outl(chip, DATA, ((data & 0x800000) ? VX_DATA_CODEC_MASK : 0)); 722 723 /* Terminate access to codec registers */ 724 vx_inl(chip, RUER); 725 } 726 727 728 /* 729 * reset codec bit 730 */ 731 static void vx2_reset_codec(struct vx_core *_chip) 732 { 733 struct snd_vx222 *chip = to_vx222(_chip); 734 735 /* Set the reset CODEC bit to 0. */ 736 vx_outl(chip, CDSP, chip->regCDSP &~ VX_CDSP_CODEC_RESET_MASK); 737 vx_inl(chip, CDSP); 738 msleep(10); 739 /* Set the reset CODEC bit to 1. */ 740 chip->regCDSP |= VX_CDSP_CODEC_RESET_MASK; 741 vx_outl(chip, CDSP, chip->regCDSP); 742 vx_inl(chip, CDSP); 743 if (_chip->type == VX_TYPE_BOARD) { 744 msleep(1); 745 return; 746 } 747 748 msleep(5); /* additionnel wait time for AKM's */ 749 750 vx2_write_codec_reg(_chip, AKM_CODEC_POWER_CONTROL_CMD); /* DAC power up, ADC power up, Vref power down */ 751 752 vx2_write_codec_reg(_chip, AKM_CODEC_CLOCK_FORMAT_CMD); /* default */ 753 vx2_write_codec_reg(_chip, AKM_CODEC_MUTE_CMD); /* Mute = ON ,Deemphasis = OFF */ 754 vx2_write_codec_reg(_chip, AKM_CODEC_RESET_OFF_CMD); /* DAC and ADC normal operation */ 755 756 if (_chip->type == VX_TYPE_MIC) { 757 /* set up the micro input selector */ 758 chip->regSELMIC = MICRO_SELECT_INPUT_NORM | 759 MICRO_SELECT_PREAMPLI_G_0 | 760 MICRO_SELECT_NOISE_T_52DB; 761 762 /* reset phantom power supply */ 763 chip->regSELMIC &= ~MICRO_SELECT_PHANTOM_ALIM; 764 765 vx_outl(_chip, SELMIC, chip->regSELMIC); 766 } 767 } 768 769 770 /* 771 * change the audio source 772 */ 773 static void vx2_change_audio_source(struct vx_core *_chip, int src) 774 { 775 struct snd_vx222 *chip = to_vx222(_chip); 776 777 switch (src) { 778 case VX_AUDIO_SRC_DIGITAL: 779 chip->regCFG |= VX_CFG_DATAIN_SEL_MASK; 780 break; 781 default: 782 chip->regCFG &= ~VX_CFG_DATAIN_SEL_MASK; 783 break; 784 } 785 vx_outl(chip, CFG, chip->regCFG); 786 } 787 788 789 /* 790 * set the clock source 791 */ 792 static void vx2_set_clock_source(struct vx_core *_chip, int source) 793 { 794 struct snd_vx222 *chip = to_vx222(_chip); 795 796 if (source == INTERNAL_QUARTZ) 797 chip->regCFG &= ~VX_CFG_CLOCKIN_SEL_MASK; 798 else 799 chip->regCFG |= VX_CFG_CLOCKIN_SEL_MASK; 800 vx_outl(chip, CFG, chip->regCFG); 801 } 802 803 /* 804 * reset the board 805 */ 806 static void vx2_reset_board(struct vx_core *_chip, int cold_reset) 807 { 808 struct snd_vx222 *chip = to_vx222(_chip); 809 810 /* initialize the register values */ 811 chip->regCDSP = VX_CDSP_CODEC_RESET_MASK | VX_CDSP_DSP_RESET_MASK ; 812 chip->regCFG = 0; 813 } 814 815 816 817 /* 818 * input level controls for VX222 Mic 819 */ 820 821 /* Micro level is specified to be adjustable from -96dB to 63 dB (board coded 0x00 ... 318), 822 * 318 = 210 + 36 + 36 + 36 (210 = +9dB variable) (3 * 36 = 3 steps of 18dB pre ampli) 823 * as we will mute if less than -110dB, so let's simply use line input coded levels and add constant offset ! 824 */ 825 #define V2_MICRO_LEVEL_RANGE (318 - 255) 826 827 static void vx2_set_input_level(struct snd_vx222 *chip) 828 { 829 int i, miclevel, preamp; 830 unsigned int data; 831 832 miclevel = chip->mic_level; 833 miclevel += V2_MICRO_LEVEL_RANGE; /* add 318 - 0xff */ 834 preamp = 0; 835 while (miclevel > 210) { /* limitation to +9dB of 3310 real gain */ 836 preamp++; /* raise pre ampli + 18dB */ 837 miclevel -= (18 * 2); /* lower level 18 dB (*2 because of 0.5 dB steps !) */ 838 } 839 if (snd_BUG_ON(preamp >= 4)) 840 return; 841 842 /* set pre-amp level */ 843 chip->regSELMIC &= ~MICRO_SELECT_PREAMPLI_MASK; 844 chip->regSELMIC |= (preamp << MICRO_SELECT_PREAMPLI_OFFSET) & MICRO_SELECT_PREAMPLI_MASK; 845 vx_outl(chip, SELMIC, chip->regSELMIC); 846 847 data = (unsigned int)miclevel << 16 | 848 (unsigned int)chip->input_level[1] << 8 | 849 (unsigned int)chip->input_level[0]; 850 vx_inl(chip, DATA); /* Activate input level programming */ 851 852 /* We have to send 32 bits (4 x 8 bits) */ 853 for (i = 0; i < 32; i++, data <<= 1) 854 vx_outl(chip, DATA, ((data & 0x80000000) ? VX_DATA_CODEC_MASK : 0)); 855 856 vx_inl(chip, RUER); /* Terminate input level programming */ 857 } 858 859 860 #define MIC_LEVEL_MAX 0xff 861 862 static const DECLARE_TLV_DB_SCALE(db_scale_mic, -6450, 50, 0); 863 864 /* 865 * controls API for input levels 866 */ 867 868 /* input levels */ 869 static int vx_input_level_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 870 { 871 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 872 uinfo->count = 2; 873 uinfo->value.integer.min = 0; 874 uinfo->value.integer.max = MIC_LEVEL_MAX; 875 return 0; 876 } 877 878 static int vx_input_level_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 879 { 880 struct vx_core *_chip = snd_kcontrol_chip(kcontrol); 881 struct snd_vx222 *chip = to_vx222(_chip); 882 mutex_lock(&_chip->mixer_mutex); 883 ucontrol->value.integer.value[0] = chip->input_level[0]; 884 ucontrol->value.integer.value[1] = chip->input_level[1]; 885 mutex_unlock(&_chip->mixer_mutex); 886 return 0; 887 } 888 889 static int vx_input_level_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 890 { 891 struct vx_core *_chip = snd_kcontrol_chip(kcontrol); 892 struct snd_vx222 *chip = to_vx222(_chip); 893 if (ucontrol->value.integer.value[0] < 0 || 894 ucontrol->value.integer.value[0] > MIC_LEVEL_MAX) 895 return -EINVAL; 896 if (ucontrol->value.integer.value[1] < 0 || 897 ucontrol->value.integer.value[1] > MIC_LEVEL_MAX) 898 return -EINVAL; 899 mutex_lock(&_chip->mixer_mutex); 900 if (chip->input_level[0] != ucontrol->value.integer.value[0] || 901 chip->input_level[1] != ucontrol->value.integer.value[1]) { 902 chip->input_level[0] = ucontrol->value.integer.value[0]; 903 chip->input_level[1] = ucontrol->value.integer.value[1]; 904 vx2_set_input_level(chip); 905 mutex_unlock(&_chip->mixer_mutex); 906 return 1; 907 } 908 mutex_unlock(&_chip->mixer_mutex); 909 return 0; 910 } 911 912 /* mic level */ 913 static int vx_mic_level_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 914 { 915 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 916 uinfo->count = 1; 917 uinfo->value.integer.min = 0; 918 uinfo->value.integer.max = MIC_LEVEL_MAX; 919 return 0; 920 } 921 922 static int vx_mic_level_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 923 { 924 struct vx_core *_chip = snd_kcontrol_chip(kcontrol); 925 struct snd_vx222 *chip = to_vx222(_chip); 926 ucontrol->value.integer.value[0] = chip->mic_level; 927 return 0; 928 } 929 930 static int vx_mic_level_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 931 { 932 struct vx_core *_chip = snd_kcontrol_chip(kcontrol); 933 struct snd_vx222 *chip = to_vx222(_chip); 934 if (ucontrol->value.integer.value[0] < 0 || 935 ucontrol->value.integer.value[0] > MIC_LEVEL_MAX) 936 return -EINVAL; 937 mutex_lock(&_chip->mixer_mutex); 938 if (chip->mic_level != ucontrol->value.integer.value[0]) { 939 chip->mic_level = ucontrol->value.integer.value[0]; 940 vx2_set_input_level(chip); 941 mutex_unlock(&_chip->mixer_mutex); 942 return 1; 943 } 944 mutex_unlock(&_chip->mixer_mutex); 945 return 0; 946 } 947 948 static const struct snd_kcontrol_new vx_control_input_level = { 949 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 950 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE | 951 SNDRV_CTL_ELEM_ACCESS_TLV_READ), 952 .name = "Capture Volume", 953 .info = vx_input_level_info, 954 .get = vx_input_level_get, 955 .put = vx_input_level_put, 956 .tlv = { .p = db_scale_mic }, 957 }; 958 959 static const struct snd_kcontrol_new vx_control_mic_level = { 960 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 961 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE | 962 SNDRV_CTL_ELEM_ACCESS_TLV_READ), 963 .name = "Mic Capture Volume", 964 .info = vx_mic_level_info, 965 .get = vx_mic_level_get, 966 .put = vx_mic_level_put, 967 .tlv = { .p = db_scale_mic }, 968 }; 969 970 /* 971 * FIXME: compressor/limiter implementation is missing yet... 972 */ 973 974 static int vx2_add_mic_controls(struct vx_core *_chip) 975 { 976 struct snd_vx222 *chip = to_vx222(_chip); 977 int err; 978 979 if (_chip->type != VX_TYPE_MIC) 980 return 0; 981 982 /* mute input levels */ 983 chip->input_level[0] = chip->input_level[1] = 0; 984 chip->mic_level = 0; 985 vx2_set_input_level(chip); 986 987 /* controls */ 988 if ((err = snd_ctl_add(_chip->card, snd_ctl_new1(&vx_control_input_level, chip))) < 0) 989 return err; 990 if ((err = snd_ctl_add(_chip->card, snd_ctl_new1(&vx_control_mic_level, chip))) < 0) 991 return err; 992 993 return 0; 994 } 995 996 997 /* 998 * callbacks 999 */ 1000 struct snd_vx_ops vx222_ops = { 1001 .in8 = vx2_inb, 1002 .in32 = vx2_inl, 1003 .out8 = vx2_outb, 1004 .out32 = vx2_outl, 1005 .test_and_ack = vx2_test_and_ack, 1006 .validate_irq = vx2_validate_irq, 1007 .akm_write = vx2_write_akm, 1008 .reset_codec = vx2_reset_codec, 1009 .change_audio_source = vx2_change_audio_source, 1010 .set_clock_source = vx2_set_clock_source, 1011 .load_dsp = vx2_load_dsp, 1012 .reset_dsp = vx2_reset_dsp, 1013 .reset_board = vx2_reset_board, 1014 .dma_write = vx2_dma_write, 1015 .dma_read = vx2_dma_read, 1016 .add_controls = vx2_add_mic_controls, 1017 }; 1018 1019 /* for old VX222 board */ 1020 struct snd_vx_ops vx222_old_ops = { 1021 .in8 = vx2_inb, 1022 .in32 = vx2_inl, 1023 .out8 = vx2_outb, 1024 .out32 = vx2_outl, 1025 .test_and_ack = vx2_test_and_ack, 1026 .validate_irq = vx2_validate_irq, 1027 .write_codec = vx2_old_write_codec_bit, 1028 .reset_codec = vx2_reset_codec, 1029 .change_audio_source = vx2_change_audio_source, 1030 .set_clock_source = vx2_set_clock_source, 1031 .load_dsp = vx2_load_dsp, 1032 .reset_dsp = vx2_reset_dsp, 1033 .reset_board = vx2_reset_board, 1034 .dma_write = vx2_dma_write, 1035 .dma_read = vx2_dma_read, 1036 }; 1037 1038