1 /* 2 * ALSA driver for RME Hammerfall DSP MADI audio interface(s) 3 * 4 * Copyright (c) 2003 Winfried Ritsch (IEM) 5 * code based on hdsp.c Paul Davis 6 * Marcus Andersson 7 * Thomas Charbonnel 8 * Modified 2006-06-01 for AES32 support by Remy Bruno 9 * <remy.bruno@trinnov.com> 10 * 11 * Modified 2009-04-13 for proper metering by Florian Faber 12 * <faber@faberman.de> 13 * 14 * Modified 2009-04-14 for native float support by Florian Faber 15 * <faber@faberman.de> 16 * 17 * Modified 2009-04-26 fixed bug in rms metering by Florian Faber 18 * <faber@faberman.de> 19 * 20 * Modified 2009-04-30 added hw serial number support by Florian Faber 21 * 22 * Modified 2011-01-14 added S/PDIF input on RayDATs by Adrian Knoth 23 * 24 * Modified 2011-01-25 variable period sizes on RayDAT/AIO by Adrian Knoth 25 * 26 * This program is free software; you can redistribute it and/or modify 27 * it under the terms of the GNU General Public License as published by 28 * the Free Software Foundation; either version 2 of the License, or 29 * (at your option) any later version. 30 * 31 * This program is distributed in the hope that it will be useful, 32 * but WITHOUT ANY WARRANTY; without even the implied warranty of 33 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 34 * GNU General Public License for more details. 35 * 36 * You should have received a copy of the GNU General Public License 37 * along with this program; if not, write to the Free Software 38 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 39 * 40 */ 41 #include <linux/init.h> 42 #include <linux/delay.h> 43 #include <linux/interrupt.h> 44 #include <linux/module.h> 45 #include <linux/slab.h> 46 #include <linux/pci.h> 47 #include <linux/math64.h> 48 #include <asm/io.h> 49 50 #include <sound/core.h> 51 #include <sound/control.h> 52 #include <sound/pcm.h> 53 #include <sound/pcm_params.h> 54 #include <sound/info.h> 55 #include <sound/asoundef.h> 56 #include <sound/rawmidi.h> 57 #include <sound/hwdep.h> 58 #include <sound/initval.h> 59 60 #include <sound/hdspm.h> 61 62 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ 63 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ 64 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;/* Enable this card */ 65 66 module_param_array(index, int, NULL, 0444); 67 MODULE_PARM_DESC(index, "Index value for RME HDSPM interface."); 68 69 module_param_array(id, charp, NULL, 0444); 70 MODULE_PARM_DESC(id, "ID string for RME HDSPM interface."); 71 72 module_param_array(enable, bool, NULL, 0444); 73 MODULE_PARM_DESC(enable, "Enable/disable specific HDSPM soundcards."); 74 75 76 MODULE_AUTHOR 77 ( 78 "Winfried Ritsch <ritsch_AT_iem.at>, " 79 "Paul Davis <paul@linuxaudiosystems.com>, " 80 "Marcus Andersson, Thomas Charbonnel <thomas@undata.org>, " 81 "Remy Bruno <remy.bruno@trinnov.com>, " 82 "Florian Faber <faberman@linuxproaudio.org>, " 83 "Adrian Knoth <adi@drcomp.erfurt.thur.de>" 84 ); 85 MODULE_DESCRIPTION("RME HDSPM"); 86 MODULE_LICENSE("GPL"); 87 MODULE_SUPPORTED_DEVICE("{{RME HDSPM-MADI}}"); 88 89 /* --- Write registers. --- 90 These are defined as byte-offsets from the iobase value. */ 91 92 #define HDSPM_WR_SETTINGS 0 93 #define HDSPM_outputBufferAddress 32 94 #define HDSPM_inputBufferAddress 36 95 #define HDSPM_controlRegister 64 96 #define HDSPM_interruptConfirmation 96 97 #define HDSPM_control2Reg 256 /* not in specs ???????? */ 98 #define HDSPM_freqReg 256 /* for AES32 */ 99 #define HDSPM_midiDataOut0 352 /* just believe in old code */ 100 #define HDSPM_midiDataOut1 356 101 #define HDSPM_eeprom_wr 384 /* for AES32 */ 102 103 /* DMA enable for 64 channels, only Bit 0 is relevant */ 104 #define HDSPM_outputEnableBase 512 /* 512-767 input DMA */ 105 #define HDSPM_inputEnableBase 768 /* 768-1023 output DMA */ 106 107 /* 16 page addresses for each of the 64 channels DMA buffer in and out 108 (each 64k=16*4k) Buffer must be 4k aligned (which is default i386 ????) */ 109 #define HDSPM_pageAddressBufferOut 8192 110 #define HDSPM_pageAddressBufferIn (HDSPM_pageAddressBufferOut+64*16*4) 111 112 #define HDSPM_MADI_mixerBase 32768 /* 32768-65535 for 2x64x64 Fader */ 113 114 #define HDSPM_MATRIX_MIXER_SIZE 8192 /* = 2*64*64 * 4 Byte => 32kB */ 115 116 /* --- Read registers. --- 117 These are defined as byte-offsets from the iobase value */ 118 #define HDSPM_statusRegister 0 119 /*#define HDSPM_statusRegister2 96 */ 120 /* after RME Windows driver sources, status2 is 4-byte word # 48 = word at 121 * offset 192, for AES32 *and* MADI 122 * => need to check that offset 192 is working on MADI */ 123 #define HDSPM_statusRegister2 192 124 #define HDSPM_timecodeRegister 128 125 126 /* AIO, RayDAT */ 127 #define HDSPM_RD_STATUS_0 0 128 #define HDSPM_RD_STATUS_1 64 129 #define HDSPM_RD_STATUS_2 128 130 #define HDSPM_RD_STATUS_3 192 131 132 #define HDSPM_RD_TCO 256 133 #define HDSPM_RD_PLL_FREQ 512 134 #define HDSPM_WR_TCO 128 135 136 #define HDSPM_TCO1_TCO_lock 0x00000001 137 #define HDSPM_TCO1_WCK_Input_Range_LSB 0x00000002 138 #define HDSPM_TCO1_WCK_Input_Range_MSB 0x00000004 139 #define HDSPM_TCO1_LTC_Input_valid 0x00000008 140 #define HDSPM_TCO1_WCK_Input_valid 0x00000010 141 #define HDSPM_TCO1_Video_Input_Format_NTSC 0x00000020 142 #define HDSPM_TCO1_Video_Input_Format_PAL 0x00000040 143 144 #define HDSPM_TCO1_set_TC 0x00000100 145 #define HDSPM_TCO1_set_drop_frame_flag 0x00000200 146 #define HDSPM_TCO1_LTC_Format_LSB 0x00000400 147 #define HDSPM_TCO1_LTC_Format_MSB 0x00000800 148 149 #define HDSPM_TCO2_TC_run 0x00010000 150 #define HDSPM_TCO2_WCK_IO_ratio_LSB 0x00020000 151 #define HDSPM_TCO2_WCK_IO_ratio_MSB 0x00040000 152 #define HDSPM_TCO2_set_num_drop_frames_LSB 0x00080000 153 #define HDSPM_TCO2_set_num_drop_frames_MSB 0x00100000 154 #define HDSPM_TCO2_set_jam_sync 0x00200000 155 #define HDSPM_TCO2_set_flywheel 0x00400000 156 157 #define HDSPM_TCO2_set_01_4 0x01000000 158 #define HDSPM_TCO2_set_pull_down 0x02000000 159 #define HDSPM_TCO2_set_pull_up 0x04000000 160 #define HDSPM_TCO2_set_freq 0x08000000 161 #define HDSPM_TCO2_set_term_75R 0x10000000 162 #define HDSPM_TCO2_set_input_LSB 0x20000000 163 #define HDSPM_TCO2_set_input_MSB 0x40000000 164 #define HDSPM_TCO2_set_freq_from_app 0x80000000 165 166 167 #define HDSPM_midiDataOut0 352 168 #define HDSPM_midiDataOut1 356 169 #define HDSPM_midiDataOut2 368 170 171 #define HDSPM_midiDataIn0 360 172 #define HDSPM_midiDataIn1 364 173 #define HDSPM_midiDataIn2 372 174 #define HDSPM_midiDataIn3 376 175 176 /* status is data bytes in MIDI-FIFO (0-128) */ 177 #define HDSPM_midiStatusOut0 384 178 #define HDSPM_midiStatusOut1 388 179 #define HDSPM_midiStatusOut2 400 180 181 #define HDSPM_midiStatusIn0 392 182 #define HDSPM_midiStatusIn1 396 183 #define HDSPM_midiStatusIn2 404 184 #define HDSPM_midiStatusIn3 408 185 186 187 /* the meters are regular i/o-mapped registers, but offset 188 considerably from the rest. the peak registers are reset 189 when read; the least-significant 4 bits are full-scale counters; 190 the actual peak value is in the most-significant 24 bits. 191 */ 192 193 #define HDSPM_MADI_INPUT_PEAK 4096 194 #define HDSPM_MADI_PLAYBACK_PEAK 4352 195 #define HDSPM_MADI_OUTPUT_PEAK 4608 196 197 #define HDSPM_MADI_INPUT_RMS_L 6144 198 #define HDSPM_MADI_PLAYBACK_RMS_L 6400 199 #define HDSPM_MADI_OUTPUT_RMS_L 6656 200 201 #define HDSPM_MADI_INPUT_RMS_H 7168 202 #define HDSPM_MADI_PLAYBACK_RMS_H 7424 203 #define HDSPM_MADI_OUTPUT_RMS_H 7680 204 205 /* --- Control Register bits --------- */ 206 #define HDSPM_Start (1<<0) /* start engine */ 207 208 #define HDSPM_Latency0 (1<<1) /* buffer size = 2^n */ 209 #define HDSPM_Latency1 (1<<2) /* where n is defined */ 210 #define HDSPM_Latency2 (1<<3) /* by Latency{2,1,0} */ 211 212 #define HDSPM_ClockModeMaster (1<<4) /* 1=Master, 0=Autosync */ 213 #define HDSPM_c0Master 0x1 /* Master clock bit in settings 214 register [RayDAT, AIO] */ 215 216 #define HDSPM_AudioInterruptEnable (1<<5) /* what do you think ? */ 217 218 #define HDSPM_Frequency0 (1<<6) /* 0=44.1kHz/88.2kHz 1=48kHz/96kHz */ 219 #define HDSPM_Frequency1 (1<<7) /* 0=32kHz/64kHz */ 220 #define HDSPM_DoubleSpeed (1<<8) /* 0=normal speed, 1=double speed */ 221 #define HDSPM_QuadSpeed (1<<31) /* quad speed bit */ 222 223 #define HDSPM_Professional (1<<9) /* Professional */ /* AES32 ONLY */ 224 #define HDSPM_TX_64ch (1<<10) /* Output 64channel MODE=1, 225 56channelMODE=0 */ /* MADI ONLY*/ 226 #define HDSPM_Emphasis (1<<10) /* Emphasis */ /* AES32 ONLY */ 227 228 #define HDSPM_AutoInp (1<<11) /* Auto Input (takeover) == Safe Mode, 229 0=off, 1=on */ /* MADI ONLY */ 230 #define HDSPM_Dolby (1<<11) /* Dolby = "NonAudio" ?? */ /* AES32 ONLY */ 231 232 #define HDSPM_InputSelect0 (1<<14) /* Input select 0= optical, 1=coax 233 * -- MADI ONLY 234 */ 235 #define HDSPM_InputSelect1 (1<<15) /* should be 0 */ 236 237 #define HDSPM_SyncRef2 (1<<13) 238 #define HDSPM_SyncRef3 (1<<25) 239 240 #define HDSPM_SMUX (1<<18) /* Frame ??? */ /* MADI ONY */ 241 #define HDSPM_clr_tms (1<<19) /* clear track marker, do not use 242 AES additional bits in 243 lower 5 Audiodatabits ??? */ 244 #define HDSPM_taxi_reset (1<<20) /* ??? */ /* MADI ONLY ? */ 245 #define HDSPM_WCK48 (1<<20) /* Frame ??? = HDSPM_SMUX */ /* AES32 ONLY */ 246 247 #define HDSPM_Midi0InterruptEnable 0x0400000 248 #define HDSPM_Midi1InterruptEnable 0x0800000 249 #define HDSPM_Midi2InterruptEnable 0x0200000 250 #define HDSPM_Midi3InterruptEnable 0x4000000 251 252 #define HDSPM_LineOut (1<<24) /* Analog Out on channel 63/64 on=1, mute=0 */ 253 #define HDSPe_FLOAT_FORMAT 0x2000000 254 255 #define HDSPM_DS_DoubleWire (1<<26) /* AES32 ONLY */ 256 #define HDSPM_QS_DoubleWire (1<<27) /* AES32 ONLY */ 257 #define HDSPM_QS_QuadWire (1<<28) /* AES32 ONLY */ 258 259 #define HDSPM_wclk_sel (1<<30) 260 261 /* --- bit helper defines */ 262 #define HDSPM_LatencyMask (HDSPM_Latency0|HDSPM_Latency1|HDSPM_Latency2) 263 #define HDSPM_FrequencyMask (HDSPM_Frequency0|HDSPM_Frequency1|\ 264 HDSPM_DoubleSpeed|HDSPM_QuadSpeed) 265 #define HDSPM_InputMask (HDSPM_InputSelect0|HDSPM_InputSelect1) 266 #define HDSPM_InputOptical 0 267 #define HDSPM_InputCoaxial (HDSPM_InputSelect0) 268 #define HDSPM_SyncRefMask (HDSPM_SyncRef0|HDSPM_SyncRef1|\ 269 HDSPM_SyncRef2|HDSPM_SyncRef3) 270 271 #define HDSPM_c0_SyncRef0 0x2 272 #define HDSPM_c0_SyncRef1 0x4 273 #define HDSPM_c0_SyncRef2 0x8 274 #define HDSPM_c0_SyncRef3 0x10 275 #define HDSPM_c0_SyncRefMask (HDSPM_c0_SyncRef0 | HDSPM_c0_SyncRef1 |\ 276 HDSPM_c0_SyncRef2 | HDSPM_c0_SyncRef3) 277 278 #define HDSPM_SYNC_FROM_WORD 0 /* Preferred sync reference */ 279 #define HDSPM_SYNC_FROM_MADI 1 /* choices - used by "pref_sync_ref" */ 280 #define HDSPM_SYNC_FROM_TCO 2 281 #define HDSPM_SYNC_FROM_SYNC_IN 3 282 283 #define HDSPM_Frequency32KHz HDSPM_Frequency0 284 #define HDSPM_Frequency44_1KHz HDSPM_Frequency1 285 #define HDSPM_Frequency48KHz (HDSPM_Frequency1|HDSPM_Frequency0) 286 #define HDSPM_Frequency64KHz (HDSPM_DoubleSpeed|HDSPM_Frequency0) 287 #define HDSPM_Frequency88_2KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1) 288 #define HDSPM_Frequency96KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1|\ 289 HDSPM_Frequency0) 290 #define HDSPM_Frequency128KHz (HDSPM_QuadSpeed|HDSPM_Frequency0) 291 #define HDSPM_Frequency176_4KHz (HDSPM_QuadSpeed|HDSPM_Frequency1) 292 #define HDSPM_Frequency192KHz (HDSPM_QuadSpeed|HDSPM_Frequency1|\ 293 HDSPM_Frequency0) 294 295 296 /* Synccheck Status */ 297 #define HDSPM_SYNC_CHECK_NO_LOCK 0 298 #define HDSPM_SYNC_CHECK_LOCK 1 299 #define HDSPM_SYNC_CHECK_SYNC 2 300 301 /* AutoSync References - used by "autosync_ref" control switch */ 302 #define HDSPM_AUTOSYNC_FROM_WORD 0 303 #define HDSPM_AUTOSYNC_FROM_MADI 1 304 #define HDSPM_AUTOSYNC_FROM_TCO 2 305 #define HDSPM_AUTOSYNC_FROM_SYNC_IN 3 306 #define HDSPM_AUTOSYNC_FROM_NONE 4 307 308 /* Possible sources of MADI input */ 309 #define HDSPM_OPTICAL 0 /* optical */ 310 #define HDSPM_COAXIAL 1 /* BNC */ 311 312 #define hdspm_encode_latency(x) (((x)<<1) & HDSPM_LatencyMask) 313 #define hdspm_decode_latency(x) ((((x) & HDSPM_LatencyMask)>>1)) 314 315 #define hdspm_encode_in(x) (((x)&0x3)<<14) 316 #define hdspm_decode_in(x) (((x)>>14)&0x3) 317 318 /* --- control2 register bits --- */ 319 #define HDSPM_TMS (1<<0) 320 #define HDSPM_TCK (1<<1) 321 #define HDSPM_TDI (1<<2) 322 #define HDSPM_JTAG (1<<3) 323 #define HDSPM_PWDN (1<<4) 324 #define HDSPM_PROGRAM (1<<5) 325 #define HDSPM_CONFIG_MODE_0 (1<<6) 326 #define HDSPM_CONFIG_MODE_1 (1<<7) 327 /*#define HDSPM_VERSION_BIT (1<<8) not defined any more*/ 328 #define HDSPM_BIGENDIAN_MODE (1<<9) 329 #define HDSPM_RD_MULTIPLE (1<<10) 330 331 /* --- Status Register bits --- */ /* MADI ONLY */ /* Bits defined here and 332 that do not conflict with specific bits for AES32 seem to be valid also 333 for the AES32 334 */ 335 #define HDSPM_audioIRQPending (1<<0) /* IRQ is high and pending */ 336 #define HDSPM_RX_64ch (1<<1) /* Input 64chan. MODE=1, 56chn MODE=0 */ 337 #define HDSPM_AB_int (1<<2) /* InputChannel Opt=0, Coax=1 338 * (like inp0) 339 */ 340 341 #define HDSPM_madiLock (1<<3) /* MADI Locked =1, no=0 */ 342 #define HDSPM_madiSync (1<<18) /* MADI is in sync */ 343 344 #define HDSPM_tcoLock 0x00000020 /* Optional TCO locked status FOR HDSPe MADI! */ 345 #define HDSPM_tcoSync 0x10000000 /* Optional TCO sync status */ 346 347 #define HDSPM_syncInLock 0x00010000 /* Sync In lock status FOR HDSPe MADI! */ 348 #define HDSPM_syncInSync 0x00020000 /* Sync In sync status FOR HDSPe MADI! */ 349 350 #define HDSPM_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */ 351 /* since 64byte accurate, last 6 bits are not used */ 352 353 354 355 #define HDSPM_DoubleSpeedStatus (1<<19) /* (input) card in double speed */ 356 357 #define HDSPM_madiFreq0 (1<<22) /* system freq 0=error */ 358 #define HDSPM_madiFreq1 (1<<23) /* 1=32, 2=44.1 3=48 */ 359 #define HDSPM_madiFreq2 (1<<24) /* 4=64, 5=88.2 6=96 */ 360 #define HDSPM_madiFreq3 (1<<25) /* 7=128, 8=176.4 9=192 */ 361 362 #define HDSPM_BufferID (1<<26) /* (Double)Buffer ID toggles with 363 * Interrupt 364 */ 365 #define HDSPM_tco_detect 0x08000000 366 #define HDSPM_tco_lock 0x20000000 367 368 #define HDSPM_s2_tco_detect 0x00000040 369 #define HDSPM_s2_AEBO_D 0x00000080 370 #define HDSPM_s2_AEBI_D 0x00000100 371 372 373 #define HDSPM_midi0IRQPending 0x40000000 374 #define HDSPM_midi1IRQPending 0x80000000 375 #define HDSPM_midi2IRQPending 0x20000000 376 #define HDSPM_midi2IRQPendingAES 0x00000020 377 #define HDSPM_midi3IRQPending 0x00200000 378 379 /* --- status bit helpers */ 380 #define HDSPM_madiFreqMask (HDSPM_madiFreq0|HDSPM_madiFreq1|\ 381 HDSPM_madiFreq2|HDSPM_madiFreq3) 382 #define HDSPM_madiFreq32 (HDSPM_madiFreq0) 383 #define HDSPM_madiFreq44_1 (HDSPM_madiFreq1) 384 #define HDSPM_madiFreq48 (HDSPM_madiFreq0|HDSPM_madiFreq1) 385 #define HDSPM_madiFreq64 (HDSPM_madiFreq2) 386 #define HDSPM_madiFreq88_2 (HDSPM_madiFreq0|HDSPM_madiFreq2) 387 #define HDSPM_madiFreq96 (HDSPM_madiFreq1|HDSPM_madiFreq2) 388 #define HDSPM_madiFreq128 (HDSPM_madiFreq0|HDSPM_madiFreq1|HDSPM_madiFreq2) 389 #define HDSPM_madiFreq176_4 (HDSPM_madiFreq3) 390 #define HDSPM_madiFreq192 (HDSPM_madiFreq3|HDSPM_madiFreq0) 391 392 /* Status2 Register bits */ /* MADI ONLY */ 393 394 #define HDSPM_version0 (1<<0) /* not really defined but I guess */ 395 #define HDSPM_version1 (1<<1) /* in former cards it was ??? */ 396 #define HDSPM_version2 (1<<2) 397 398 #define HDSPM_wcLock (1<<3) /* Wordclock is detected and locked */ 399 #define HDSPM_wcSync (1<<4) /* Wordclock is in sync with systemclock */ 400 401 #define HDSPM_wc_freq0 (1<<5) /* input freq detected via autosync */ 402 #define HDSPM_wc_freq1 (1<<6) /* 001=32, 010==44.1, 011=48, */ 403 #define HDSPM_wc_freq2 (1<<7) /* 100=64, 101=88.2, 110=96, */ 404 /* missing Bit for 111=128, 1000=176.4, 1001=192 */ 405 406 #define HDSPM_SyncRef0 0x10000 /* Sync Reference */ 407 #define HDSPM_SyncRef1 0x20000 408 409 #define HDSPM_SelSyncRef0 (1<<8) /* AutoSync Source */ 410 #define HDSPM_SelSyncRef1 (1<<9) /* 000=word, 001=MADI, */ 411 #define HDSPM_SelSyncRef2 (1<<10) /* 111=no valid signal */ 412 413 #define HDSPM_wc_valid (HDSPM_wcLock|HDSPM_wcSync) 414 415 #define HDSPM_wcFreqMask (HDSPM_wc_freq0|HDSPM_wc_freq1|HDSPM_wc_freq2) 416 #define HDSPM_wcFreq32 (HDSPM_wc_freq0) 417 #define HDSPM_wcFreq44_1 (HDSPM_wc_freq1) 418 #define HDSPM_wcFreq48 (HDSPM_wc_freq0|HDSPM_wc_freq1) 419 #define HDSPM_wcFreq64 (HDSPM_wc_freq2) 420 #define HDSPM_wcFreq88_2 (HDSPM_wc_freq0|HDSPM_wc_freq2) 421 #define HDSPM_wcFreq96 (HDSPM_wc_freq1|HDSPM_wc_freq2) 422 423 #define HDSPM_status1_F_0 0x0400000 424 #define HDSPM_status1_F_1 0x0800000 425 #define HDSPM_status1_F_2 0x1000000 426 #define HDSPM_status1_F_3 0x2000000 427 #define HDSPM_status1_freqMask (HDSPM_status1_F_0|HDSPM_status1_F_1|HDSPM_status1_F_2|HDSPM_status1_F_3) 428 429 430 #define HDSPM_SelSyncRefMask (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\ 431 HDSPM_SelSyncRef2) 432 #define HDSPM_SelSyncRef_WORD 0 433 #define HDSPM_SelSyncRef_MADI (HDSPM_SelSyncRef0) 434 #define HDSPM_SelSyncRef_TCO (HDSPM_SelSyncRef1) 435 #define HDSPM_SelSyncRef_SyncIn (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1) 436 #define HDSPM_SelSyncRef_NVALID (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\ 437 HDSPM_SelSyncRef2) 438 439 /* 440 For AES32, bits for status, status2 and timecode are different 441 */ 442 /* status */ 443 #define HDSPM_AES32_wcLock 0x0200000 444 #define HDSPM_AES32_wcFreq_bit 22 445 /* (status >> HDSPM_AES32_wcFreq_bit) & 0xF gives WC frequency (cf function 446 HDSPM_bit2freq */ 447 #define HDSPM_AES32_syncref_bit 16 448 /* (status >> HDSPM_AES32_syncref_bit) & 0xF gives sync source */ 449 450 #define HDSPM_AES32_AUTOSYNC_FROM_WORD 0 451 #define HDSPM_AES32_AUTOSYNC_FROM_AES1 1 452 #define HDSPM_AES32_AUTOSYNC_FROM_AES2 2 453 #define HDSPM_AES32_AUTOSYNC_FROM_AES3 3 454 #define HDSPM_AES32_AUTOSYNC_FROM_AES4 4 455 #define HDSPM_AES32_AUTOSYNC_FROM_AES5 5 456 #define HDSPM_AES32_AUTOSYNC_FROM_AES6 6 457 #define HDSPM_AES32_AUTOSYNC_FROM_AES7 7 458 #define HDSPM_AES32_AUTOSYNC_FROM_AES8 8 459 #define HDSPM_AES32_AUTOSYNC_FROM_NONE 9 460 461 /* status2 */ 462 /* HDSPM_LockAES_bit is given by HDSPM_LockAES >> (AES# - 1) */ 463 #define HDSPM_LockAES 0x80 464 #define HDSPM_LockAES1 0x80 465 #define HDSPM_LockAES2 0x40 466 #define HDSPM_LockAES3 0x20 467 #define HDSPM_LockAES4 0x10 468 #define HDSPM_LockAES5 0x8 469 #define HDSPM_LockAES6 0x4 470 #define HDSPM_LockAES7 0x2 471 #define HDSPM_LockAES8 0x1 472 /* 473 Timecode 474 After windows driver sources, bits 4*i to 4*i+3 give the input frequency on 475 AES i+1 476 bits 3210 477 0001 32kHz 478 0010 44.1kHz 479 0011 48kHz 480 0100 64kHz 481 0101 88.2kHz 482 0110 96kHz 483 0111 128kHz 484 1000 176.4kHz 485 1001 192kHz 486 NB: Timecode register doesn't seem to work on AES32 card revision 230 487 */ 488 489 /* Mixer Values */ 490 #define UNITY_GAIN 32768 /* = 65536/2 */ 491 #define MINUS_INFINITY_GAIN 0 492 493 /* Number of channels for different Speed Modes */ 494 #define MADI_SS_CHANNELS 64 495 #define MADI_DS_CHANNELS 32 496 #define MADI_QS_CHANNELS 16 497 498 #define RAYDAT_SS_CHANNELS 36 499 #define RAYDAT_DS_CHANNELS 20 500 #define RAYDAT_QS_CHANNELS 12 501 502 #define AIO_IN_SS_CHANNELS 14 503 #define AIO_IN_DS_CHANNELS 10 504 #define AIO_IN_QS_CHANNELS 8 505 #define AIO_OUT_SS_CHANNELS 16 506 #define AIO_OUT_DS_CHANNELS 12 507 #define AIO_OUT_QS_CHANNELS 10 508 509 #define AES32_CHANNELS 16 510 511 /* the size of a substream (1 mono data stream) */ 512 #define HDSPM_CHANNEL_BUFFER_SAMPLES (16*1024) 513 #define HDSPM_CHANNEL_BUFFER_BYTES (4*HDSPM_CHANNEL_BUFFER_SAMPLES) 514 515 /* the size of the area we need to allocate for DMA transfers. the 516 size is the same regardless of the number of channels, and 517 also the latency to use. 518 for one direction !!! 519 */ 520 #define HDSPM_DMA_AREA_BYTES (HDSPM_MAX_CHANNELS * HDSPM_CHANNEL_BUFFER_BYTES) 521 #define HDSPM_DMA_AREA_KILOBYTES (HDSPM_DMA_AREA_BYTES/1024) 522 523 #define HDSPM_RAYDAT_REV 211 524 #define HDSPM_AIO_REV 212 525 #define HDSPM_MADIFACE_REV 213 526 527 /* speed factor modes */ 528 #define HDSPM_SPEED_SINGLE 0 529 #define HDSPM_SPEED_DOUBLE 1 530 #define HDSPM_SPEED_QUAD 2 531 532 /* names for speed modes */ 533 static char *hdspm_speed_names[] = { "single", "double", "quad" }; 534 535 static char *texts_autosync_aes_tco[] = { "Word Clock", 536 "AES1", "AES2", "AES3", "AES4", 537 "AES5", "AES6", "AES7", "AES8", 538 "TCO" }; 539 static char *texts_autosync_aes[] = { "Word Clock", 540 "AES1", "AES2", "AES3", "AES4", 541 "AES5", "AES6", "AES7", "AES8" }; 542 static char *texts_autosync_madi_tco[] = { "Word Clock", 543 "MADI", "TCO", "Sync In" }; 544 static char *texts_autosync_madi[] = { "Word Clock", 545 "MADI", "Sync In" }; 546 547 static char *texts_autosync_raydat_tco[] = { 548 "Word Clock", 549 "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4", 550 "AES", "SPDIF", "TCO", "Sync In" 551 }; 552 static char *texts_autosync_raydat[] = { 553 "Word Clock", 554 "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4", 555 "AES", "SPDIF", "Sync In" 556 }; 557 static char *texts_autosync_aio_tco[] = { 558 "Word Clock", 559 "ADAT", "AES", "SPDIF", "TCO", "Sync In" 560 }; 561 static char *texts_autosync_aio[] = { "Word Clock", 562 "ADAT", "AES", "SPDIF", "Sync In" }; 563 564 static char *texts_freq[] = { 565 "No Lock", 566 "32 kHz", 567 "44.1 kHz", 568 "48 kHz", 569 "64 kHz", 570 "88.2 kHz", 571 "96 kHz", 572 "128 kHz", 573 "176.4 kHz", 574 "192 kHz" 575 }; 576 577 static char *texts_ports_madi[] = { 578 "MADI.1", "MADI.2", "MADI.3", "MADI.4", "MADI.5", "MADI.6", 579 "MADI.7", "MADI.8", "MADI.9", "MADI.10", "MADI.11", "MADI.12", 580 "MADI.13", "MADI.14", "MADI.15", "MADI.16", "MADI.17", "MADI.18", 581 "MADI.19", "MADI.20", "MADI.21", "MADI.22", "MADI.23", "MADI.24", 582 "MADI.25", "MADI.26", "MADI.27", "MADI.28", "MADI.29", "MADI.30", 583 "MADI.31", "MADI.32", "MADI.33", "MADI.34", "MADI.35", "MADI.36", 584 "MADI.37", "MADI.38", "MADI.39", "MADI.40", "MADI.41", "MADI.42", 585 "MADI.43", "MADI.44", "MADI.45", "MADI.46", "MADI.47", "MADI.48", 586 "MADI.49", "MADI.50", "MADI.51", "MADI.52", "MADI.53", "MADI.54", 587 "MADI.55", "MADI.56", "MADI.57", "MADI.58", "MADI.59", "MADI.60", 588 "MADI.61", "MADI.62", "MADI.63", "MADI.64", 589 }; 590 591 592 static char *texts_ports_raydat_ss[] = { 593 "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4", "ADAT1.5", "ADAT1.6", 594 "ADAT1.7", "ADAT1.8", "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4", 595 "ADAT2.5", "ADAT2.6", "ADAT2.7", "ADAT2.8", "ADAT3.1", "ADAT3.2", 596 "ADAT3.3", "ADAT3.4", "ADAT3.5", "ADAT3.6", "ADAT3.7", "ADAT3.8", 597 "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4", "ADAT4.5", "ADAT4.6", 598 "ADAT4.7", "ADAT4.8", 599 "AES.L", "AES.R", 600 "SPDIF.L", "SPDIF.R" 601 }; 602 603 static char *texts_ports_raydat_ds[] = { 604 "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4", 605 "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4", 606 "ADAT3.1", "ADAT3.2", "ADAT3.3", "ADAT3.4", 607 "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4", 608 "AES.L", "AES.R", 609 "SPDIF.L", "SPDIF.R" 610 }; 611 612 static char *texts_ports_raydat_qs[] = { 613 "ADAT1.1", "ADAT1.2", 614 "ADAT2.1", "ADAT2.2", 615 "ADAT3.1", "ADAT3.2", 616 "ADAT4.1", "ADAT4.2", 617 "AES.L", "AES.R", 618 "SPDIF.L", "SPDIF.R" 619 }; 620 621 622 static char *texts_ports_aio_in_ss[] = { 623 "Analogue.L", "Analogue.R", 624 "AES.L", "AES.R", 625 "SPDIF.L", "SPDIF.R", 626 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6", 627 "ADAT.7", "ADAT.8" 628 }; 629 630 static char *texts_ports_aio_out_ss[] = { 631 "Analogue.L", "Analogue.R", 632 "AES.L", "AES.R", 633 "SPDIF.L", "SPDIF.R", 634 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6", 635 "ADAT.7", "ADAT.8", 636 "Phone.L", "Phone.R" 637 }; 638 639 static char *texts_ports_aio_in_ds[] = { 640 "Analogue.L", "Analogue.R", 641 "AES.L", "AES.R", 642 "SPDIF.L", "SPDIF.R", 643 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4" 644 }; 645 646 static char *texts_ports_aio_out_ds[] = { 647 "Analogue.L", "Analogue.R", 648 "AES.L", "AES.R", 649 "SPDIF.L", "SPDIF.R", 650 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", 651 "Phone.L", "Phone.R" 652 }; 653 654 static char *texts_ports_aio_in_qs[] = { 655 "Analogue.L", "Analogue.R", 656 "AES.L", "AES.R", 657 "SPDIF.L", "SPDIF.R", 658 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4" 659 }; 660 661 static char *texts_ports_aio_out_qs[] = { 662 "Analogue.L", "Analogue.R", 663 "AES.L", "AES.R", 664 "SPDIF.L", "SPDIF.R", 665 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", 666 "Phone.L", "Phone.R" 667 }; 668 669 static char *texts_ports_aes32[] = { 670 "AES.1", "AES.2", "AES.3", "AES.4", "AES.5", "AES.6", "AES.7", 671 "AES.8", "AES.9.", "AES.10", "AES.11", "AES.12", "AES.13", "AES.14", 672 "AES.15", "AES.16" 673 }; 674 675 /* These tables map the ALSA channels 1..N to the channels that we 676 need to use in order to find the relevant channel buffer. RME 677 refers to this kind of mapping as between "the ADAT channel and 678 the DMA channel." We index it using the logical audio channel, 679 and the value is the DMA channel (i.e. channel buffer number) 680 where the data for that channel can be read/written from/to. 681 */ 682 683 static char channel_map_unity_ss[HDSPM_MAX_CHANNELS] = { 684 0, 1, 2, 3, 4, 5, 6, 7, 685 8, 9, 10, 11, 12, 13, 14, 15, 686 16, 17, 18, 19, 20, 21, 22, 23, 687 24, 25, 26, 27, 28, 29, 30, 31, 688 32, 33, 34, 35, 36, 37, 38, 39, 689 40, 41, 42, 43, 44, 45, 46, 47, 690 48, 49, 50, 51, 52, 53, 54, 55, 691 56, 57, 58, 59, 60, 61, 62, 63 692 }; 693 694 static char channel_map_raydat_ss[HDSPM_MAX_CHANNELS] = { 695 4, 5, 6, 7, 8, 9, 10, 11, /* ADAT 1 */ 696 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT 2 */ 697 20, 21, 22, 23, 24, 25, 26, 27, /* ADAT 3 */ 698 28, 29, 30, 31, 32, 33, 34, 35, /* ADAT 4 */ 699 0, 1, /* AES */ 700 2, 3, /* SPDIF */ 701 -1, -1, -1, -1, 702 -1, -1, -1, -1, -1, -1, -1, -1, 703 -1, -1, -1, -1, -1, -1, -1, -1, 704 -1, -1, -1, -1, -1, -1, -1, -1, 705 }; 706 707 static char channel_map_raydat_ds[HDSPM_MAX_CHANNELS] = { 708 4, 5, 6, 7, /* ADAT 1 */ 709 8, 9, 10, 11, /* ADAT 2 */ 710 12, 13, 14, 15, /* ADAT 3 */ 711 16, 17, 18, 19, /* ADAT 4 */ 712 0, 1, /* AES */ 713 2, 3, /* SPDIF */ 714 -1, -1, -1, -1, 715 -1, -1, -1, -1, -1, -1, -1, -1, 716 -1, -1, -1, -1, -1, -1, -1, -1, 717 -1, -1, -1, -1, -1, -1, -1, -1, 718 -1, -1, -1, -1, -1, -1, -1, -1, 719 -1, -1, -1, -1, -1, -1, -1, -1, 720 }; 721 722 static char channel_map_raydat_qs[HDSPM_MAX_CHANNELS] = { 723 4, 5, /* ADAT 1 */ 724 6, 7, /* ADAT 2 */ 725 8, 9, /* ADAT 3 */ 726 10, 11, /* ADAT 4 */ 727 0, 1, /* AES */ 728 2, 3, /* SPDIF */ 729 -1, -1, -1, -1, 730 -1, -1, -1, -1, -1, -1, -1, -1, 731 -1, -1, -1, -1, -1, -1, -1, -1, 732 -1, -1, -1, -1, -1, -1, -1, -1, 733 -1, -1, -1, -1, -1, -1, -1, -1, 734 -1, -1, -1, -1, -1, -1, -1, -1, 735 -1, -1, -1, -1, -1, -1, -1, -1, 736 }; 737 738 static char channel_map_aio_in_ss[HDSPM_MAX_CHANNELS] = { 739 0, 1, /* line in */ 740 8, 9, /* aes in, */ 741 10, 11, /* spdif in */ 742 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT in */ 743 -1, -1, 744 -1, -1, -1, -1, -1, -1, -1, -1, 745 -1, -1, -1, -1, -1, -1, -1, -1, 746 -1, -1, -1, -1, -1, -1, -1, -1, 747 -1, -1, -1, -1, -1, -1, -1, -1, 748 -1, -1, -1, -1, -1, -1, -1, -1, 749 -1, -1, -1, -1, -1, -1, -1, -1, 750 }; 751 752 static char channel_map_aio_out_ss[HDSPM_MAX_CHANNELS] = { 753 0, 1, /* line out */ 754 8, 9, /* aes out */ 755 10, 11, /* spdif out */ 756 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT out */ 757 6, 7, /* phone out */ 758 -1, -1, -1, -1, -1, -1, -1, -1, 759 -1, -1, -1, -1, -1, -1, -1, -1, 760 -1, -1, -1, -1, -1, -1, -1, -1, 761 -1, -1, -1, -1, -1, -1, -1, -1, 762 -1, -1, -1, -1, -1, -1, -1, -1, 763 -1, -1, -1, -1, -1, -1, -1, -1, 764 }; 765 766 static char channel_map_aio_in_ds[HDSPM_MAX_CHANNELS] = { 767 0, 1, /* line in */ 768 8, 9, /* aes in */ 769 10, 11, /* spdif in */ 770 12, 14, 16, 18, /* adat in */ 771 -1, -1, -1, -1, -1, -1, 772 -1, -1, -1, -1, -1, -1, -1, -1, 773 -1, -1, -1, -1, -1, -1, -1, -1, 774 -1, -1, -1, -1, -1, -1, -1, -1, 775 -1, -1, -1, -1, -1, -1, -1, -1, 776 -1, -1, -1, -1, -1, -1, -1, -1, 777 -1, -1, -1, -1, -1, -1, -1, -1 778 }; 779 780 static char channel_map_aio_out_ds[HDSPM_MAX_CHANNELS] = { 781 0, 1, /* line out */ 782 8, 9, /* aes out */ 783 10, 11, /* spdif out */ 784 12, 14, 16, 18, /* adat out */ 785 6, 7, /* phone out */ 786 -1, -1, -1, -1, 787 -1, -1, -1, -1, -1, -1, -1, -1, 788 -1, -1, -1, -1, -1, -1, -1, -1, 789 -1, -1, -1, -1, -1, -1, -1, -1, 790 -1, -1, -1, -1, -1, -1, -1, -1, 791 -1, -1, -1, -1, -1, -1, -1, -1, 792 -1, -1, -1, -1, -1, -1, -1, -1 793 }; 794 795 static char channel_map_aio_in_qs[HDSPM_MAX_CHANNELS] = { 796 0, 1, /* line in */ 797 8, 9, /* aes in */ 798 10, 11, /* spdif in */ 799 12, 16, /* adat in */ 800 -1, -1, -1, -1, -1, -1, -1, -1, 801 -1, -1, -1, -1, -1, -1, -1, -1, 802 -1, -1, -1, -1, -1, -1, -1, -1, 803 -1, -1, -1, -1, -1, -1, -1, -1, 804 -1, -1, -1, -1, -1, -1, -1, -1, 805 -1, -1, -1, -1, -1, -1, -1, -1, 806 -1, -1, -1, -1, -1, -1, -1, -1 807 }; 808 809 static char channel_map_aio_out_qs[HDSPM_MAX_CHANNELS] = { 810 0, 1, /* line out */ 811 8, 9, /* aes out */ 812 10, 11, /* spdif out */ 813 12, 16, /* adat out */ 814 6, 7, /* phone out */ 815 -1, -1, -1, -1, -1, -1, 816 -1, -1, -1, -1, -1, -1, -1, -1, 817 -1, -1, -1, -1, -1, -1, -1, -1, 818 -1, -1, -1, -1, -1, -1, -1, -1, 819 -1, -1, -1, -1, -1, -1, -1, -1, 820 -1, -1, -1, -1, -1, -1, -1, -1, 821 -1, -1, -1, -1, -1, -1, -1, -1 822 }; 823 824 static char channel_map_aes32[HDSPM_MAX_CHANNELS] = { 825 0, 1, 2, 3, 4, 5, 6, 7, 826 8, 9, 10, 11, 12, 13, 14, 15, 827 -1, -1, -1, -1, -1, -1, -1, -1, 828 -1, -1, -1, -1, -1, -1, -1, -1, 829 -1, -1, -1, -1, -1, -1, -1, -1, 830 -1, -1, -1, -1, -1, -1, -1, -1, 831 -1, -1, -1, -1, -1, -1, -1, -1, 832 -1, -1, -1, -1, -1, -1, -1, -1 833 }; 834 835 struct hdspm_midi { 836 struct hdspm *hdspm; 837 int id; 838 struct snd_rawmidi *rmidi; 839 struct snd_rawmidi_substream *input; 840 struct snd_rawmidi_substream *output; 841 char istimer; /* timer in use */ 842 struct timer_list timer; 843 spinlock_t lock; 844 int pending; 845 int dataIn; 846 int statusIn; 847 int dataOut; 848 int statusOut; 849 int ie; 850 int irq; 851 }; 852 853 struct hdspm_tco { 854 int input; 855 int framerate; 856 int wordclock; 857 int samplerate; 858 int pull; 859 int term; /* 0 = off, 1 = on */ 860 }; 861 862 struct hdspm { 863 spinlock_t lock; 864 /* only one playback and/or capture stream */ 865 struct snd_pcm_substream *capture_substream; 866 struct snd_pcm_substream *playback_substream; 867 868 char *card_name; /* for procinfo */ 869 unsigned short firmware_rev; /* dont know if relevant (yes if AES32)*/ 870 871 uint8_t io_type; 872 873 int monitor_outs; /* set up monitoring outs init flag */ 874 875 u32 control_register; /* cached value */ 876 u32 control2_register; /* cached value */ 877 u32 settings_register; 878 879 struct hdspm_midi midi[4]; 880 struct tasklet_struct midi_tasklet; 881 882 size_t period_bytes; 883 unsigned char ss_in_channels; 884 unsigned char ds_in_channels; 885 unsigned char qs_in_channels; 886 unsigned char ss_out_channels; 887 unsigned char ds_out_channels; 888 unsigned char qs_out_channels; 889 890 unsigned char max_channels_in; 891 unsigned char max_channels_out; 892 893 signed char *channel_map_in; 894 signed char *channel_map_out; 895 896 signed char *channel_map_in_ss, *channel_map_in_ds, *channel_map_in_qs; 897 signed char *channel_map_out_ss, *channel_map_out_ds, *channel_map_out_qs; 898 899 char **port_names_in; 900 char **port_names_out; 901 902 char **port_names_in_ss, **port_names_in_ds, **port_names_in_qs; 903 char **port_names_out_ss, **port_names_out_ds, **port_names_out_qs; 904 905 unsigned char *playback_buffer; /* suitably aligned address */ 906 unsigned char *capture_buffer; /* suitably aligned address */ 907 908 pid_t capture_pid; /* process id which uses capture */ 909 pid_t playback_pid; /* process id which uses capture */ 910 int running; /* running status */ 911 912 int last_external_sample_rate; /* samplerate mystic ... */ 913 int last_internal_sample_rate; 914 int system_sample_rate; 915 916 int dev; /* Hardware vars... */ 917 int irq; 918 unsigned long port; 919 void __iomem *iobase; 920 921 int irq_count; /* for debug */ 922 int midiPorts; 923 924 struct snd_card *card; /* one card */ 925 struct snd_pcm *pcm; /* has one pcm */ 926 struct snd_hwdep *hwdep; /* and a hwdep for additional ioctl */ 927 struct pci_dev *pci; /* and an pci info */ 928 929 /* Mixer vars */ 930 /* fast alsa mixer */ 931 struct snd_kcontrol *playback_mixer_ctls[HDSPM_MAX_CHANNELS]; 932 /* but input to much, so not used */ 933 struct snd_kcontrol *input_mixer_ctls[HDSPM_MAX_CHANNELS]; 934 /* full mixer accessible over mixer ioctl or hwdep-device */ 935 struct hdspm_mixer *mixer; 936 937 struct hdspm_tco *tco; /* NULL if no TCO detected */ 938 939 char **texts_autosync; 940 int texts_autosync_items; 941 942 cycles_t last_interrupt; 943 944 struct hdspm_peak_rms peak_rms; 945 }; 946 947 948 static DEFINE_PCI_DEVICE_TABLE(snd_hdspm_ids) = { 949 { 950 .vendor = PCI_VENDOR_ID_XILINX, 951 .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP_MADI, 952 .subvendor = PCI_ANY_ID, 953 .subdevice = PCI_ANY_ID, 954 .class = 0, 955 .class_mask = 0, 956 .driver_data = 0}, 957 {0,} 958 }; 959 960 MODULE_DEVICE_TABLE(pci, snd_hdspm_ids); 961 962 /* prototypes */ 963 static int __devinit snd_hdspm_create_alsa_devices(struct snd_card *card, 964 struct hdspm * hdspm); 965 static int __devinit snd_hdspm_create_pcm(struct snd_card *card, 966 struct hdspm * hdspm); 967 968 static inline void snd_hdspm_initialize_midi_flush(struct hdspm *hdspm); 969 static int hdspm_update_simple_mixer_controls(struct hdspm *hdspm); 970 static int hdspm_autosync_ref(struct hdspm *hdspm); 971 static int snd_hdspm_set_defaults(struct hdspm *hdspm); 972 static void hdspm_set_sgbuf(struct hdspm *hdspm, 973 struct snd_pcm_substream *substream, 974 unsigned int reg, int channels); 975 976 static inline int HDSPM_bit2freq(int n) 977 { 978 static const int bit2freq_tab[] = { 979 0, 32000, 44100, 48000, 64000, 88200, 980 96000, 128000, 176400, 192000 }; 981 if (n < 1 || n > 9) 982 return 0; 983 return bit2freq_tab[n]; 984 } 985 986 /* Write/read to/from HDSPM with Adresses in Bytes 987 not words but only 32Bit writes are allowed */ 988 989 static inline void hdspm_write(struct hdspm * hdspm, unsigned int reg, 990 unsigned int val) 991 { 992 writel(val, hdspm->iobase + reg); 993 } 994 995 static inline unsigned int hdspm_read(struct hdspm * hdspm, unsigned int reg) 996 { 997 return readl(hdspm->iobase + reg); 998 } 999 1000 /* for each output channel (chan) I have an Input (in) and Playback (pb) Fader 1001 mixer is write only on hardware so we have to cache him for read 1002 each fader is a u32, but uses only the first 16 bit */ 1003 1004 static inline int hdspm_read_in_gain(struct hdspm * hdspm, unsigned int chan, 1005 unsigned int in) 1006 { 1007 if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS) 1008 return 0; 1009 1010 return hdspm->mixer->ch[chan].in[in]; 1011 } 1012 1013 static inline int hdspm_read_pb_gain(struct hdspm * hdspm, unsigned int chan, 1014 unsigned int pb) 1015 { 1016 if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS) 1017 return 0; 1018 return hdspm->mixer->ch[chan].pb[pb]; 1019 } 1020 1021 static int hdspm_write_in_gain(struct hdspm *hdspm, unsigned int chan, 1022 unsigned int in, unsigned short data) 1023 { 1024 if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS) 1025 return -1; 1026 1027 hdspm_write(hdspm, 1028 HDSPM_MADI_mixerBase + 1029 ((in + 128 * chan) * sizeof(u32)), 1030 (hdspm->mixer->ch[chan].in[in] = data & 0xFFFF)); 1031 return 0; 1032 } 1033 1034 static int hdspm_write_pb_gain(struct hdspm *hdspm, unsigned int chan, 1035 unsigned int pb, unsigned short data) 1036 { 1037 if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS) 1038 return -1; 1039 1040 hdspm_write(hdspm, 1041 HDSPM_MADI_mixerBase + 1042 ((64 + pb + 128 * chan) * sizeof(u32)), 1043 (hdspm->mixer->ch[chan].pb[pb] = data & 0xFFFF)); 1044 return 0; 1045 } 1046 1047 1048 /* enable DMA for specific channels, now available for DSP-MADI */ 1049 static inline void snd_hdspm_enable_in(struct hdspm * hdspm, int i, int v) 1050 { 1051 hdspm_write(hdspm, HDSPM_inputEnableBase + (4 * i), v); 1052 } 1053 1054 static inline void snd_hdspm_enable_out(struct hdspm * hdspm, int i, int v) 1055 { 1056 hdspm_write(hdspm, HDSPM_outputEnableBase + (4 * i), v); 1057 } 1058 1059 /* check if same process is writing and reading */ 1060 static int snd_hdspm_use_is_exclusive(struct hdspm *hdspm) 1061 { 1062 unsigned long flags; 1063 int ret = 1; 1064 1065 spin_lock_irqsave(&hdspm->lock, flags); 1066 if ((hdspm->playback_pid != hdspm->capture_pid) && 1067 (hdspm->playback_pid >= 0) && (hdspm->capture_pid >= 0)) { 1068 ret = 0; 1069 } 1070 spin_unlock_irqrestore(&hdspm->lock, flags); 1071 return ret; 1072 } 1073 1074 /* check for external sample rate */ 1075 static int hdspm_external_sample_rate(struct hdspm *hdspm) 1076 { 1077 unsigned int status, status2, timecode; 1078 int syncref, rate = 0, rate_bits; 1079 1080 switch (hdspm->io_type) { 1081 case AES32: 1082 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 1083 status = hdspm_read(hdspm, HDSPM_statusRegister); 1084 timecode = hdspm_read(hdspm, HDSPM_timecodeRegister); 1085 1086 syncref = hdspm_autosync_ref(hdspm); 1087 1088 if (syncref == HDSPM_AES32_AUTOSYNC_FROM_WORD && 1089 status & HDSPM_AES32_wcLock) 1090 return HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF); 1091 1092 if (syncref >= HDSPM_AES32_AUTOSYNC_FROM_AES1 && 1093 syncref <= HDSPM_AES32_AUTOSYNC_FROM_AES8 && 1094 status2 & (HDSPM_LockAES >> 1095 (syncref - HDSPM_AES32_AUTOSYNC_FROM_AES1))) 1096 return HDSPM_bit2freq((timecode >> (4*(syncref-HDSPM_AES32_AUTOSYNC_FROM_AES1))) & 0xF); 1097 return 0; 1098 break; 1099 1100 case MADIface: 1101 status = hdspm_read(hdspm, HDSPM_statusRegister); 1102 1103 if (!(status & HDSPM_madiLock)) { 1104 rate = 0; /* no lock */ 1105 } else { 1106 switch (status & (HDSPM_status1_freqMask)) { 1107 case HDSPM_status1_F_0*1: 1108 rate = 32000; break; 1109 case HDSPM_status1_F_0*2: 1110 rate = 44100; break; 1111 case HDSPM_status1_F_0*3: 1112 rate = 48000; break; 1113 case HDSPM_status1_F_0*4: 1114 rate = 64000; break; 1115 case HDSPM_status1_F_0*5: 1116 rate = 88200; break; 1117 case HDSPM_status1_F_0*6: 1118 rate = 96000; break; 1119 case HDSPM_status1_F_0*7: 1120 rate = 128000; break; 1121 case HDSPM_status1_F_0*8: 1122 rate = 176400; break; 1123 case HDSPM_status1_F_0*9: 1124 rate = 192000; break; 1125 default: 1126 rate = 0; break; 1127 } 1128 } 1129 1130 break; 1131 1132 case MADI: 1133 case AIO: 1134 case RayDAT: 1135 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 1136 status = hdspm_read(hdspm, HDSPM_statusRegister); 1137 rate = 0; 1138 1139 /* if wordclock has synced freq and wordclock is valid */ 1140 if ((status2 & HDSPM_wcLock) != 0 && 1141 (status2 & HDSPM_SelSyncRef0) == 0) { 1142 1143 rate_bits = status2 & HDSPM_wcFreqMask; 1144 1145 1146 switch (rate_bits) { 1147 case HDSPM_wcFreq32: 1148 rate = 32000; 1149 break; 1150 case HDSPM_wcFreq44_1: 1151 rate = 44100; 1152 break; 1153 case HDSPM_wcFreq48: 1154 rate = 48000; 1155 break; 1156 case HDSPM_wcFreq64: 1157 rate = 64000; 1158 break; 1159 case HDSPM_wcFreq88_2: 1160 rate = 88200; 1161 break; 1162 case HDSPM_wcFreq96: 1163 rate = 96000; 1164 break; 1165 default: 1166 rate = 0; 1167 break; 1168 } 1169 } 1170 1171 /* if rate detected and Syncref is Word than have it, 1172 * word has priority to MADI 1173 */ 1174 if (rate != 0 && 1175 (status2 & HDSPM_SelSyncRefMask) == HDSPM_SelSyncRef_WORD) 1176 return rate; 1177 1178 /* maybe a madi input (which is taken if sel sync is madi) */ 1179 if (status & HDSPM_madiLock) { 1180 rate_bits = status & HDSPM_madiFreqMask; 1181 1182 switch (rate_bits) { 1183 case HDSPM_madiFreq32: 1184 rate = 32000; 1185 break; 1186 case HDSPM_madiFreq44_1: 1187 rate = 44100; 1188 break; 1189 case HDSPM_madiFreq48: 1190 rate = 48000; 1191 break; 1192 case HDSPM_madiFreq64: 1193 rate = 64000; 1194 break; 1195 case HDSPM_madiFreq88_2: 1196 rate = 88200; 1197 break; 1198 case HDSPM_madiFreq96: 1199 rate = 96000; 1200 break; 1201 case HDSPM_madiFreq128: 1202 rate = 128000; 1203 break; 1204 case HDSPM_madiFreq176_4: 1205 rate = 176400; 1206 break; 1207 case HDSPM_madiFreq192: 1208 rate = 192000; 1209 break; 1210 default: 1211 rate = 0; 1212 break; 1213 } 1214 1215 /* QS and DS rates normally can not be detected 1216 * automatically by the card. Only exception is MADI 1217 * in 96k frame mode. 1218 * 1219 * So if we read SS values (32 .. 48k), check for 1220 * user-provided DS/QS bits in the control register 1221 * and multiply the base frequency accordingly. 1222 */ 1223 if (rate <= 48000) { 1224 if (hdspm->control_register & HDSPM_QuadSpeed) 1225 rate *= 4; 1226 else if (hdspm->control_register & 1227 HDSPM_DoubleSpeed) 1228 rate *= 2; 1229 } 1230 } 1231 break; 1232 } 1233 1234 return rate; 1235 } 1236 1237 /* return latency in samples per period */ 1238 static int hdspm_get_latency(struct hdspm *hdspm) 1239 { 1240 int n; 1241 1242 n = hdspm_decode_latency(hdspm->control_register); 1243 1244 /* Special case for new RME cards with 32 samples period size. 1245 * The three latency bits in the control register 1246 * (HDSP_LatencyMask) encode latency values of 64 samples as 1247 * 0, 128 samples as 1 ... 4096 samples as 6. For old cards, 7 1248 * denotes 8192 samples, but on new cards like RayDAT or AIO, 1249 * it corresponds to 32 samples. 1250 */ 1251 if ((7 == n) && (RayDAT == hdspm->io_type || AIO == hdspm->io_type)) 1252 n = -1; 1253 1254 return 1 << (n + 6); 1255 } 1256 1257 /* Latency function */ 1258 static inline void hdspm_compute_period_size(struct hdspm *hdspm) 1259 { 1260 hdspm->period_bytes = 4 * hdspm_get_latency(hdspm); 1261 } 1262 1263 1264 static snd_pcm_uframes_t hdspm_hw_pointer(struct hdspm *hdspm) 1265 { 1266 int position; 1267 1268 position = hdspm_read(hdspm, HDSPM_statusRegister); 1269 1270 switch (hdspm->io_type) { 1271 case RayDAT: 1272 case AIO: 1273 position &= HDSPM_BufferPositionMask; 1274 position /= 4; /* Bytes per sample */ 1275 break; 1276 default: 1277 position = (position & HDSPM_BufferID) ? 1278 (hdspm->period_bytes / 4) : 0; 1279 } 1280 1281 return position; 1282 } 1283 1284 1285 static inline void hdspm_start_audio(struct hdspm * s) 1286 { 1287 s->control_register |= (HDSPM_AudioInterruptEnable | HDSPM_Start); 1288 hdspm_write(s, HDSPM_controlRegister, s->control_register); 1289 } 1290 1291 static inline void hdspm_stop_audio(struct hdspm * s) 1292 { 1293 s->control_register &= ~(HDSPM_Start | HDSPM_AudioInterruptEnable); 1294 hdspm_write(s, HDSPM_controlRegister, s->control_register); 1295 } 1296 1297 /* should I silence all or only opened ones ? doit all for first even is 4MB*/ 1298 static void hdspm_silence_playback(struct hdspm *hdspm) 1299 { 1300 int i; 1301 int n = hdspm->period_bytes; 1302 void *buf = hdspm->playback_buffer; 1303 1304 if (buf == NULL) 1305 return; 1306 1307 for (i = 0; i < HDSPM_MAX_CHANNELS; i++) { 1308 memset(buf, 0, n); 1309 buf += HDSPM_CHANNEL_BUFFER_BYTES; 1310 } 1311 } 1312 1313 static int hdspm_set_interrupt_interval(struct hdspm *s, unsigned int frames) 1314 { 1315 int n; 1316 1317 spin_lock_irq(&s->lock); 1318 1319 if (32 == frames) { 1320 /* Special case for new RME cards like RayDAT/AIO which 1321 * support period sizes of 32 samples. Since latency is 1322 * encoded in the three bits of HDSP_LatencyMask, we can only 1323 * have values from 0 .. 7. While 0 still means 64 samples and 1324 * 6 represents 4096 samples on all cards, 7 represents 8192 1325 * on older cards and 32 samples on new cards. 1326 * 1327 * In other words, period size in samples is calculated by 1328 * 2^(n+6) with n ranging from 0 .. 7. 1329 */ 1330 n = 7; 1331 } else { 1332 frames >>= 7; 1333 n = 0; 1334 while (frames) { 1335 n++; 1336 frames >>= 1; 1337 } 1338 } 1339 1340 s->control_register &= ~HDSPM_LatencyMask; 1341 s->control_register |= hdspm_encode_latency(n); 1342 1343 hdspm_write(s, HDSPM_controlRegister, s->control_register); 1344 1345 hdspm_compute_period_size(s); 1346 1347 spin_unlock_irq(&s->lock); 1348 1349 return 0; 1350 } 1351 1352 static u64 hdspm_calc_dds_value(struct hdspm *hdspm, u64 period) 1353 { 1354 u64 freq_const; 1355 1356 if (period == 0) 1357 return 0; 1358 1359 switch (hdspm->io_type) { 1360 case MADI: 1361 case AES32: 1362 freq_const = 110069313433624ULL; 1363 break; 1364 case RayDAT: 1365 case AIO: 1366 freq_const = 104857600000000ULL; 1367 break; 1368 case MADIface: 1369 freq_const = 131072000000000ULL; 1370 break; 1371 default: 1372 snd_BUG(); 1373 return 0; 1374 } 1375 1376 return div_u64(freq_const, period); 1377 } 1378 1379 1380 static void hdspm_set_dds_value(struct hdspm *hdspm, int rate) 1381 { 1382 u64 n; 1383 1384 if (rate >= 112000) 1385 rate /= 4; 1386 else if (rate >= 56000) 1387 rate /= 2; 1388 1389 switch (hdspm->io_type) { 1390 case MADIface: 1391 n = 131072000000000ULL; /* 125 MHz */ 1392 break; 1393 case MADI: 1394 case AES32: 1395 n = 110069313433624ULL; /* 105 MHz */ 1396 break; 1397 case RayDAT: 1398 case AIO: 1399 n = 104857600000000ULL; /* 100 MHz */ 1400 break; 1401 default: 1402 snd_BUG(); 1403 return; 1404 } 1405 1406 n = div_u64(n, rate); 1407 /* n should be less than 2^32 for being written to FREQ register */ 1408 snd_BUG_ON(n >> 32); 1409 hdspm_write(hdspm, HDSPM_freqReg, (u32)n); 1410 } 1411 1412 /* dummy set rate lets see what happens */ 1413 static int hdspm_set_rate(struct hdspm * hdspm, int rate, int called_internally) 1414 { 1415 int current_rate; 1416 int rate_bits; 1417 int not_set = 0; 1418 int current_speed, target_speed; 1419 1420 /* ASSUMPTION: hdspm->lock is either set, or there is no need for 1421 it (e.g. during module initialization). 1422 */ 1423 1424 if (!(hdspm->control_register & HDSPM_ClockModeMaster)) { 1425 1426 /* SLAVE --- */ 1427 if (called_internally) { 1428 1429 /* request from ctl or card initialization 1430 just make a warning an remember setting 1431 for future master mode switching */ 1432 1433 snd_printk(KERN_WARNING "HDSPM: " 1434 "Warning: device is not running " 1435 "as a clock master.\n"); 1436 not_set = 1; 1437 } else { 1438 1439 /* hw_param request while in AutoSync mode */ 1440 int external_freq = 1441 hdspm_external_sample_rate(hdspm); 1442 1443 if (hdspm_autosync_ref(hdspm) == 1444 HDSPM_AUTOSYNC_FROM_NONE) { 1445 1446 snd_printk(KERN_WARNING "HDSPM: " 1447 "Detected no Externel Sync \n"); 1448 not_set = 1; 1449 1450 } else if (rate != external_freq) { 1451 1452 snd_printk(KERN_WARNING "HDSPM: " 1453 "Warning: No AutoSync source for " 1454 "requested rate\n"); 1455 not_set = 1; 1456 } 1457 } 1458 } 1459 1460 current_rate = hdspm->system_sample_rate; 1461 1462 /* Changing between Singe, Double and Quad speed is not 1463 allowed if any substreams are open. This is because such a change 1464 causes a shift in the location of the DMA buffers and a reduction 1465 in the number of available buffers. 1466 1467 Note that a similar but essentially insoluble problem exists for 1468 externally-driven rate changes. All we can do is to flag rate 1469 changes in the read/write routines. 1470 */ 1471 1472 if (current_rate <= 48000) 1473 current_speed = HDSPM_SPEED_SINGLE; 1474 else if (current_rate <= 96000) 1475 current_speed = HDSPM_SPEED_DOUBLE; 1476 else 1477 current_speed = HDSPM_SPEED_QUAD; 1478 1479 if (rate <= 48000) 1480 target_speed = HDSPM_SPEED_SINGLE; 1481 else if (rate <= 96000) 1482 target_speed = HDSPM_SPEED_DOUBLE; 1483 else 1484 target_speed = HDSPM_SPEED_QUAD; 1485 1486 switch (rate) { 1487 case 32000: 1488 rate_bits = HDSPM_Frequency32KHz; 1489 break; 1490 case 44100: 1491 rate_bits = HDSPM_Frequency44_1KHz; 1492 break; 1493 case 48000: 1494 rate_bits = HDSPM_Frequency48KHz; 1495 break; 1496 case 64000: 1497 rate_bits = HDSPM_Frequency64KHz; 1498 break; 1499 case 88200: 1500 rate_bits = HDSPM_Frequency88_2KHz; 1501 break; 1502 case 96000: 1503 rate_bits = HDSPM_Frequency96KHz; 1504 break; 1505 case 128000: 1506 rate_bits = HDSPM_Frequency128KHz; 1507 break; 1508 case 176400: 1509 rate_bits = HDSPM_Frequency176_4KHz; 1510 break; 1511 case 192000: 1512 rate_bits = HDSPM_Frequency192KHz; 1513 break; 1514 default: 1515 return -EINVAL; 1516 } 1517 1518 if (current_speed != target_speed 1519 && (hdspm->capture_pid >= 0 || hdspm->playback_pid >= 0)) { 1520 snd_printk 1521 (KERN_ERR "HDSPM: " 1522 "cannot change from %s speed to %s speed mode " 1523 "(capture PID = %d, playback PID = %d)\n", 1524 hdspm_speed_names[current_speed], 1525 hdspm_speed_names[target_speed], 1526 hdspm->capture_pid, hdspm->playback_pid); 1527 return -EBUSY; 1528 } 1529 1530 hdspm->control_register &= ~HDSPM_FrequencyMask; 1531 hdspm->control_register |= rate_bits; 1532 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 1533 1534 /* For AES32, need to set DDS value in FREQ register 1535 For MADI, also apparently */ 1536 hdspm_set_dds_value(hdspm, rate); 1537 1538 if (AES32 == hdspm->io_type && rate != current_rate) 1539 hdspm_write(hdspm, HDSPM_eeprom_wr, 0); 1540 1541 hdspm->system_sample_rate = rate; 1542 1543 if (rate <= 48000) { 1544 hdspm->channel_map_in = hdspm->channel_map_in_ss; 1545 hdspm->channel_map_out = hdspm->channel_map_out_ss; 1546 hdspm->max_channels_in = hdspm->ss_in_channels; 1547 hdspm->max_channels_out = hdspm->ss_out_channels; 1548 hdspm->port_names_in = hdspm->port_names_in_ss; 1549 hdspm->port_names_out = hdspm->port_names_out_ss; 1550 } else if (rate <= 96000) { 1551 hdspm->channel_map_in = hdspm->channel_map_in_ds; 1552 hdspm->channel_map_out = hdspm->channel_map_out_ds; 1553 hdspm->max_channels_in = hdspm->ds_in_channels; 1554 hdspm->max_channels_out = hdspm->ds_out_channels; 1555 hdspm->port_names_in = hdspm->port_names_in_ds; 1556 hdspm->port_names_out = hdspm->port_names_out_ds; 1557 } else { 1558 hdspm->channel_map_in = hdspm->channel_map_in_qs; 1559 hdspm->channel_map_out = hdspm->channel_map_out_qs; 1560 hdspm->max_channels_in = hdspm->qs_in_channels; 1561 hdspm->max_channels_out = hdspm->qs_out_channels; 1562 hdspm->port_names_in = hdspm->port_names_in_qs; 1563 hdspm->port_names_out = hdspm->port_names_out_qs; 1564 } 1565 1566 if (not_set != 0) 1567 return -1; 1568 1569 return 0; 1570 } 1571 1572 /* mainly for init to 0 on load */ 1573 static void all_in_all_mixer(struct hdspm * hdspm, int sgain) 1574 { 1575 int i, j; 1576 unsigned int gain; 1577 1578 if (sgain > UNITY_GAIN) 1579 gain = UNITY_GAIN; 1580 else if (sgain < 0) 1581 gain = 0; 1582 else 1583 gain = sgain; 1584 1585 for (i = 0; i < HDSPM_MIXER_CHANNELS; i++) 1586 for (j = 0; j < HDSPM_MIXER_CHANNELS; j++) { 1587 hdspm_write_in_gain(hdspm, i, j, gain); 1588 hdspm_write_pb_gain(hdspm, i, j, gain); 1589 } 1590 } 1591 1592 /*---------------------------------------------------------------------------- 1593 MIDI 1594 ----------------------------------------------------------------------------*/ 1595 1596 static inline unsigned char snd_hdspm_midi_read_byte (struct hdspm *hdspm, 1597 int id) 1598 { 1599 /* the hardware already does the relevant bit-mask with 0xff */ 1600 return hdspm_read(hdspm, hdspm->midi[id].dataIn); 1601 } 1602 1603 static inline void snd_hdspm_midi_write_byte (struct hdspm *hdspm, int id, 1604 int val) 1605 { 1606 /* the hardware already does the relevant bit-mask with 0xff */ 1607 return hdspm_write(hdspm, hdspm->midi[id].dataOut, val); 1608 } 1609 1610 static inline int snd_hdspm_midi_input_available (struct hdspm *hdspm, int id) 1611 { 1612 return hdspm_read(hdspm, hdspm->midi[id].statusIn) & 0xFF; 1613 } 1614 1615 static inline int snd_hdspm_midi_output_possible (struct hdspm *hdspm, int id) 1616 { 1617 int fifo_bytes_used; 1618 1619 fifo_bytes_used = hdspm_read(hdspm, hdspm->midi[id].statusOut) & 0xFF; 1620 1621 if (fifo_bytes_used < 128) 1622 return 128 - fifo_bytes_used; 1623 else 1624 return 0; 1625 } 1626 1627 static void snd_hdspm_flush_midi_input(struct hdspm *hdspm, int id) 1628 { 1629 while (snd_hdspm_midi_input_available (hdspm, id)) 1630 snd_hdspm_midi_read_byte (hdspm, id); 1631 } 1632 1633 static int snd_hdspm_midi_output_write (struct hdspm_midi *hmidi) 1634 { 1635 unsigned long flags; 1636 int n_pending; 1637 int to_write; 1638 int i; 1639 unsigned char buf[128]; 1640 1641 /* Output is not interrupt driven */ 1642 1643 spin_lock_irqsave (&hmidi->lock, flags); 1644 if (hmidi->output && 1645 !snd_rawmidi_transmit_empty (hmidi->output)) { 1646 n_pending = snd_hdspm_midi_output_possible (hmidi->hdspm, 1647 hmidi->id); 1648 if (n_pending > 0) { 1649 if (n_pending > (int)sizeof (buf)) 1650 n_pending = sizeof (buf); 1651 1652 to_write = snd_rawmidi_transmit (hmidi->output, buf, 1653 n_pending); 1654 if (to_write > 0) { 1655 for (i = 0; i < to_write; ++i) 1656 snd_hdspm_midi_write_byte (hmidi->hdspm, 1657 hmidi->id, 1658 buf[i]); 1659 } 1660 } 1661 } 1662 spin_unlock_irqrestore (&hmidi->lock, flags); 1663 return 0; 1664 } 1665 1666 static int snd_hdspm_midi_input_read (struct hdspm_midi *hmidi) 1667 { 1668 unsigned char buf[128]; /* this buffer is designed to match the MIDI 1669 * input FIFO size 1670 */ 1671 unsigned long flags; 1672 int n_pending; 1673 int i; 1674 1675 spin_lock_irqsave (&hmidi->lock, flags); 1676 n_pending = snd_hdspm_midi_input_available (hmidi->hdspm, hmidi->id); 1677 if (n_pending > 0) { 1678 if (hmidi->input) { 1679 if (n_pending > (int)sizeof (buf)) 1680 n_pending = sizeof (buf); 1681 for (i = 0; i < n_pending; ++i) 1682 buf[i] = snd_hdspm_midi_read_byte (hmidi->hdspm, 1683 hmidi->id); 1684 if (n_pending) 1685 snd_rawmidi_receive (hmidi->input, buf, 1686 n_pending); 1687 } else { 1688 /* flush the MIDI input FIFO */ 1689 while (n_pending--) 1690 snd_hdspm_midi_read_byte (hmidi->hdspm, 1691 hmidi->id); 1692 } 1693 } 1694 hmidi->pending = 0; 1695 spin_unlock_irqrestore(&hmidi->lock, flags); 1696 1697 spin_lock_irqsave(&hmidi->hdspm->lock, flags); 1698 hmidi->hdspm->control_register |= hmidi->ie; 1699 hdspm_write(hmidi->hdspm, HDSPM_controlRegister, 1700 hmidi->hdspm->control_register); 1701 spin_unlock_irqrestore(&hmidi->hdspm->lock, flags); 1702 1703 return snd_hdspm_midi_output_write (hmidi); 1704 } 1705 1706 static void 1707 snd_hdspm_midi_input_trigger(struct snd_rawmidi_substream *substream, int up) 1708 { 1709 struct hdspm *hdspm; 1710 struct hdspm_midi *hmidi; 1711 unsigned long flags; 1712 1713 hmidi = substream->rmidi->private_data; 1714 hdspm = hmidi->hdspm; 1715 1716 spin_lock_irqsave (&hdspm->lock, flags); 1717 if (up) { 1718 if (!(hdspm->control_register & hmidi->ie)) { 1719 snd_hdspm_flush_midi_input (hdspm, hmidi->id); 1720 hdspm->control_register |= hmidi->ie; 1721 } 1722 } else { 1723 hdspm->control_register &= ~hmidi->ie; 1724 } 1725 1726 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 1727 spin_unlock_irqrestore (&hdspm->lock, flags); 1728 } 1729 1730 static void snd_hdspm_midi_output_timer(unsigned long data) 1731 { 1732 struct hdspm_midi *hmidi = (struct hdspm_midi *) data; 1733 unsigned long flags; 1734 1735 snd_hdspm_midi_output_write(hmidi); 1736 spin_lock_irqsave (&hmidi->lock, flags); 1737 1738 /* this does not bump hmidi->istimer, because the 1739 kernel automatically removed the timer when it 1740 expired, and we are now adding it back, thus 1741 leaving istimer wherever it was set before. 1742 */ 1743 1744 if (hmidi->istimer) { 1745 hmidi->timer.expires = 1 + jiffies; 1746 add_timer(&hmidi->timer); 1747 } 1748 1749 spin_unlock_irqrestore (&hmidi->lock, flags); 1750 } 1751 1752 static void 1753 snd_hdspm_midi_output_trigger(struct snd_rawmidi_substream *substream, int up) 1754 { 1755 struct hdspm_midi *hmidi; 1756 unsigned long flags; 1757 1758 hmidi = substream->rmidi->private_data; 1759 spin_lock_irqsave (&hmidi->lock, flags); 1760 if (up) { 1761 if (!hmidi->istimer) { 1762 init_timer(&hmidi->timer); 1763 hmidi->timer.function = snd_hdspm_midi_output_timer; 1764 hmidi->timer.data = (unsigned long) hmidi; 1765 hmidi->timer.expires = 1 + jiffies; 1766 add_timer(&hmidi->timer); 1767 hmidi->istimer++; 1768 } 1769 } else { 1770 if (hmidi->istimer && --hmidi->istimer <= 0) 1771 del_timer (&hmidi->timer); 1772 } 1773 spin_unlock_irqrestore (&hmidi->lock, flags); 1774 if (up) 1775 snd_hdspm_midi_output_write(hmidi); 1776 } 1777 1778 static int snd_hdspm_midi_input_open(struct snd_rawmidi_substream *substream) 1779 { 1780 struct hdspm_midi *hmidi; 1781 1782 hmidi = substream->rmidi->private_data; 1783 spin_lock_irq (&hmidi->lock); 1784 snd_hdspm_flush_midi_input (hmidi->hdspm, hmidi->id); 1785 hmidi->input = substream; 1786 spin_unlock_irq (&hmidi->lock); 1787 1788 return 0; 1789 } 1790 1791 static int snd_hdspm_midi_output_open(struct snd_rawmidi_substream *substream) 1792 { 1793 struct hdspm_midi *hmidi; 1794 1795 hmidi = substream->rmidi->private_data; 1796 spin_lock_irq (&hmidi->lock); 1797 hmidi->output = substream; 1798 spin_unlock_irq (&hmidi->lock); 1799 1800 return 0; 1801 } 1802 1803 static int snd_hdspm_midi_input_close(struct snd_rawmidi_substream *substream) 1804 { 1805 struct hdspm_midi *hmidi; 1806 1807 snd_hdspm_midi_input_trigger (substream, 0); 1808 1809 hmidi = substream->rmidi->private_data; 1810 spin_lock_irq (&hmidi->lock); 1811 hmidi->input = NULL; 1812 spin_unlock_irq (&hmidi->lock); 1813 1814 return 0; 1815 } 1816 1817 static int snd_hdspm_midi_output_close(struct snd_rawmidi_substream *substream) 1818 { 1819 struct hdspm_midi *hmidi; 1820 1821 snd_hdspm_midi_output_trigger (substream, 0); 1822 1823 hmidi = substream->rmidi->private_data; 1824 spin_lock_irq (&hmidi->lock); 1825 hmidi->output = NULL; 1826 spin_unlock_irq (&hmidi->lock); 1827 1828 return 0; 1829 } 1830 1831 static struct snd_rawmidi_ops snd_hdspm_midi_output = 1832 { 1833 .open = snd_hdspm_midi_output_open, 1834 .close = snd_hdspm_midi_output_close, 1835 .trigger = snd_hdspm_midi_output_trigger, 1836 }; 1837 1838 static struct snd_rawmidi_ops snd_hdspm_midi_input = 1839 { 1840 .open = snd_hdspm_midi_input_open, 1841 .close = snd_hdspm_midi_input_close, 1842 .trigger = snd_hdspm_midi_input_trigger, 1843 }; 1844 1845 static int __devinit snd_hdspm_create_midi (struct snd_card *card, 1846 struct hdspm *hdspm, int id) 1847 { 1848 int err; 1849 char buf[32]; 1850 1851 hdspm->midi[id].id = id; 1852 hdspm->midi[id].hdspm = hdspm; 1853 spin_lock_init (&hdspm->midi[id].lock); 1854 1855 if (0 == id) { 1856 if (MADIface == hdspm->io_type) { 1857 /* MIDI-over-MADI on HDSPe MADIface */ 1858 hdspm->midi[0].dataIn = HDSPM_midiDataIn2; 1859 hdspm->midi[0].statusIn = HDSPM_midiStatusIn2; 1860 hdspm->midi[0].dataOut = HDSPM_midiDataOut2; 1861 hdspm->midi[0].statusOut = HDSPM_midiStatusOut2; 1862 hdspm->midi[0].ie = HDSPM_Midi2InterruptEnable; 1863 hdspm->midi[0].irq = HDSPM_midi2IRQPending; 1864 } else { 1865 hdspm->midi[0].dataIn = HDSPM_midiDataIn0; 1866 hdspm->midi[0].statusIn = HDSPM_midiStatusIn0; 1867 hdspm->midi[0].dataOut = HDSPM_midiDataOut0; 1868 hdspm->midi[0].statusOut = HDSPM_midiStatusOut0; 1869 hdspm->midi[0].ie = HDSPM_Midi0InterruptEnable; 1870 hdspm->midi[0].irq = HDSPM_midi0IRQPending; 1871 } 1872 } else if (1 == id) { 1873 hdspm->midi[1].dataIn = HDSPM_midiDataIn1; 1874 hdspm->midi[1].statusIn = HDSPM_midiStatusIn1; 1875 hdspm->midi[1].dataOut = HDSPM_midiDataOut1; 1876 hdspm->midi[1].statusOut = HDSPM_midiStatusOut1; 1877 hdspm->midi[1].ie = HDSPM_Midi1InterruptEnable; 1878 hdspm->midi[1].irq = HDSPM_midi1IRQPending; 1879 } else if ((2 == id) && (MADI == hdspm->io_type)) { 1880 /* MIDI-over-MADI on HDSPe MADI */ 1881 hdspm->midi[2].dataIn = HDSPM_midiDataIn2; 1882 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2; 1883 hdspm->midi[2].dataOut = HDSPM_midiDataOut2; 1884 hdspm->midi[2].statusOut = HDSPM_midiStatusOut2; 1885 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable; 1886 hdspm->midi[2].irq = HDSPM_midi2IRQPending; 1887 } else if (2 == id) { 1888 /* TCO MTC, read only */ 1889 hdspm->midi[2].dataIn = HDSPM_midiDataIn2; 1890 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2; 1891 hdspm->midi[2].dataOut = -1; 1892 hdspm->midi[2].statusOut = -1; 1893 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable; 1894 hdspm->midi[2].irq = HDSPM_midi2IRQPendingAES; 1895 } else if (3 == id) { 1896 /* TCO MTC on HDSPe MADI */ 1897 hdspm->midi[3].dataIn = HDSPM_midiDataIn3; 1898 hdspm->midi[3].statusIn = HDSPM_midiStatusIn3; 1899 hdspm->midi[3].dataOut = -1; 1900 hdspm->midi[3].statusOut = -1; 1901 hdspm->midi[3].ie = HDSPM_Midi3InterruptEnable; 1902 hdspm->midi[3].irq = HDSPM_midi3IRQPending; 1903 } 1904 1905 if ((id < 2) || ((2 == id) && ((MADI == hdspm->io_type) || 1906 (MADIface == hdspm->io_type)))) { 1907 if ((id == 0) && (MADIface == hdspm->io_type)) { 1908 sprintf(buf, "%s MIDIoverMADI", card->shortname); 1909 } else if ((id == 2) && (MADI == hdspm->io_type)) { 1910 sprintf(buf, "%s MIDIoverMADI", card->shortname); 1911 } else { 1912 sprintf(buf, "%s MIDI %d", card->shortname, id+1); 1913 } 1914 err = snd_rawmidi_new(card, buf, id, 1, 1, 1915 &hdspm->midi[id].rmidi); 1916 if (err < 0) 1917 return err; 1918 1919 sprintf(hdspm->midi[id].rmidi->name, "%s MIDI %d", 1920 card->id, id+1); 1921 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id]; 1922 1923 snd_rawmidi_set_ops(hdspm->midi[id].rmidi, 1924 SNDRV_RAWMIDI_STREAM_OUTPUT, 1925 &snd_hdspm_midi_output); 1926 snd_rawmidi_set_ops(hdspm->midi[id].rmidi, 1927 SNDRV_RAWMIDI_STREAM_INPUT, 1928 &snd_hdspm_midi_input); 1929 1930 hdspm->midi[id].rmidi->info_flags |= 1931 SNDRV_RAWMIDI_INFO_OUTPUT | 1932 SNDRV_RAWMIDI_INFO_INPUT | 1933 SNDRV_RAWMIDI_INFO_DUPLEX; 1934 } else { 1935 /* TCO MTC, read only */ 1936 sprintf(buf, "%s MTC %d", card->shortname, id+1); 1937 err = snd_rawmidi_new(card, buf, id, 1, 1, 1938 &hdspm->midi[id].rmidi); 1939 if (err < 0) 1940 return err; 1941 1942 sprintf(hdspm->midi[id].rmidi->name, 1943 "%s MTC %d", card->id, id+1); 1944 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id]; 1945 1946 snd_rawmidi_set_ops(hdspm->midi[id].rmidi, 1947 SNDRV_RAWMIDI_STREAM_INPUT, 1948 &snd_hdspm_midi_input); 1949 1950 hdspm->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_INPUT; 1951 } 1952 1953 return 0; 1954 } 1955 1956 1957 static void hdspm_midi_tasklet(unsigned long arg) 1958 { 1959 struct hdspm *hdspm = (struct hdspm *)arg; 1960 int i = 0; 1961 1962 while (i < hdspm->midiPorts) { 1963 if (hdspm->midi[i].pending) 1964 snd_hdspm_midi_input_read(&hdspm->midi[i]); 1965 1966 i++; 1967 } 1968 } 1969 1970 1971 /*----------------------------------------------------------------------------- 1972 Status Interface 1973 ----------------------------------------------------------------------------*/ 1974 1975 /* get the system sample rate which is set */ 1976 1977 1978 /** 1979 * Calculate the real sample rate from the 1980 * current DDS value. 1981 **/ 1982 static int hdspm_get_system_sample_rate(struct hdspm *hdspm) 1983 { 1984 unsigned int period, rate; 1985 1986 period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ); 1987 rate = hdspm_calc_dds_value(hdspm, period); 1988 1989 return rate; 1990 } 1991 1992 1993 #define HDSPM_SYSTEM_SAMPLE_RATE(xname, xindex) \ 1994 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 1995 .name = xname, \ 1996 .index = xindex, \ 1997 .access = SNDRV_CTL_ELEM_ACCESS_READ, \ 1998 .info = snd_hdspm_info_system_sample_rate, \ 1999 .get = snd_hdspm_get_system_sample_rate \ 2000 } 2001 2002 static int snd_hdspm_info_system_sample_rate(struct snd_kcontrol *kcontrol, 2003 struct snd_ctl_elem_info *uinfo) 2004 { 2005 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 2006 uinfo->count = 1; 2007 uinfo->value.integer.min = 27000; 2008 uinfo->value.integer.max = 207000; 2009 uinfo->value.integer.step = 1; 2010 return 0; 2011 } 2012 2013 2014 static int snd_hdspm_get_system_sample_rate(struct snd_kcontrol *kcontrol, 2015 struct snd_ctl_elem_value * 2016 ucontrol) 2017 { 2018 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2019 2020 ucontrol->value.integer.value[0] = hdspm_get_system_sample_rate(hdspm); 2021 return 0; 2022 } 2023 2024 2025 /** 2026 * Returns the WordClock sample rate class for the given card. 2027 **/ 2028 static int hdspm_get_wc_sample_rate(struct hdspm *hdspm) 2029 { 2030 int status; 2031 2032 switch (hdspm->io_type) { 2033 case RayDAT: 2034 case AIO: 2035 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1); 2036 return (status >> 16) & 0xF; 2037 break; 2038 default: 2039 break; 2040 } 2041 2042 2043 return 0; 2044 } 2045 2046 2047 /** 2048 * Returns the TCO sample rate class for the given card. 2049 **/ 2050 static int hdspm_get_tco_sample_rate(struct hdspm *hdspm) 2051 { 2052 int status; 2053 2054 if (hdspm->tco) { 2055 switch (hdspm->io_type) { 2056 case RayDAT: 2057 case AIO: 2058 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1); 2059 return (status >> 20) & 0xF; 2060 break; 2061 default: 2062 break; 2063 } 2064 } 2065 2066 return 0; 2067 } 2068 2069 2070 /** 2071 * Returns the SYNC_IN sample rate class for the given card. 2072 **/ 2073 static int hdspm_get_sync_in_sample_rate(struct hdspm *hdspm) 2074 { 2075 int status; 2076 2077 if (hdspm->tco) { 2078 switch (hdspm->io_type) { 2079 case RayDAT: 2080 case AIO: 2081 status = hdspm_read(hdspm, HDSPM_RD_STATUS_2); 2082 return (status >> 12) & 0xF; 2083 break; 2084 default: 2085 break; 2086 } 2087 } 2088 2089 return 0; 2090 } 2091 2092 2093 /** 2094 * Returns the sample rate class for input source <idx> for 2095 * 'new style' cards like the AIO and RayDAT. 2096 **/ 2097 static int hdspm_get_s1_sample_rate(struct hdspm *hdspm, unsigned int idx) 2098 { 2099 int status = hdspm_read(hdspm, HDSPM_RD_STATUS_2); 2100 2101 return (status >> (idx*4)) & 0xF; 2102 } 2103 2104 2105 2106 #define HDSPM_AUTOSYNC_SAMPLE_RATE(xname, xindex) \ 2107 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2108 .name = xname, \ 2109 .private_value = xindex, \ 2110 .access = SNDRV_CTL_ELEM_ACCESS_READ, \ 2111 .info = snd_hdspm_info_autosync_sample_rate, \ 2112 .get = snd_hdspm_get_autosync_sample_rate \ 2113 } 2114 2115 2116 static int snd_hdspm_info_autosync_sample_rate(struct snd_kcontrol *kcontrol, 2117 struct snd_ctl_elem_info *uinfo) 2118 { 2119 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2120 uinfo->count = 1; 2121 uinfo->value.enumerated.items = 10; 2122 2123 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 2124 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; 2125 strcpy(uinfo->value.enumerated.name, 2126 texts_freq[uinfo->value.enumerated.item]); 2127 return 0; 2128 } 2129 2130 2131 static int snd_hdspm_get_autosync_sample_rate(struct snd_kcontrol *kcontrol, 2132 struct snd_ctl_elem_value * 2133 ucontrol) 2134 { 2135 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2136 2137 switch (hdspm->io_type) { 2138 case RayDAT: 2139 switch (kcontrol->private_value) { 2140 case 0: 2141 ucontrol->value.enumerated.item[0] = 2142 hdspm_get_wc_sample_rate(hdspm); 2143 break; 2144 case 7: 2145 ucontrol->value.enumerated.item[0] = 2146 hdspm_get_tco_sample_rate(hdspm); 2147 break; 2148 case 8: 2149 ucontrol->value.enumerated.item[0] = 2150 hdspm_get_sync_in_sample_rate(hdspm); 2151 break; 2152 default: 2153 ucontrol->value.enumerated.item[0] = 2154 hdspm_get_s1_sample_rate(hdspm, 2155 kcontrol->private_value-1); 2156 } 2157 2158 case AIO: 2159 switch (kcontrol->private_value) { 2160 case 0: /* WC */ 2161 ucontrol->value.enumerated.item[0] = 2162 hdspm_get_wc_sample_rate(hdspm); 2163 break; 2164 case 4: /* TCO */ 2165 ucontrol->value.enumerated.item[0] = 2166 hdspm_get_tco_sample_rate(hdspm); 2167 break; 2168 case 5: /* SYNC_IN */ 2169 ucontrol->value.enumerated.item[0] = 2170 hdspm_get_sync_in_sample_rate(hdspm); 2171 break; 2172 default: 2173 ucontrol->value.enumerated.item[0] = 2174 hdspm_get_s1_sample_rate(hdspm, 2175 ucontrol->id.index-1); 2176 } 2177 2178 case AES32: 2179 2180 switch (kcontrol->private_value) { 2181 case 0: /* WC */ 2182 ucontrol->value.enumerated.item[0] = 2183 hdspm_get_wc_sample_rate(hdspm); 2184 break; 2185 case 9: /* TCO */ 2186 ucontrol->value.enumerated.item[0] = 2187 hdspm_get_tco_sample_rate(hdspm); 2188 break; 2189 case 10: /* SYNC_IN */ 2190 ucontrol->value.enumerated.item[0] = 2191 hdspm_get_sync_in_sample_rate(hdspm); 2192 break; 2193 default: /* AES1 to AES8 */ 2194 ucontrol->value.enumerated.item[0] = 2195 hdspm_get_s1_sample_rate(hdspm, 2196 kcontrol->private_value-1); 2197 break; 2198 2199 } 2200 default: 2201 break; 2202 } 2203 2204 return 0; 2205 } 2206 2207 2208 #define HDSPM_SYSTEM_CLOCK_MODE(xname, xindex) \ 2209 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2210 .name = xname, \ 2211 .index = xindex, \ 2212 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 2213 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 2214 .info = snd_hdspm_info_system_clock_mode, \ 2215 .get = snd_hdspm_get_system_clock_mode, \ 2216 .put = snd_hdspm_put_system_clock_mode, \ 2217 } 2218 2219 2220 /** 2221 * Returns the system clock mode for the given card. 2222 * @returns 0 - master, 1 - slave 2223 **/ 2224 static int hdspm_system_clock_mode(struct hdspm *hdspm) 2225 { 2226 switch (hdspm->io_type) { 2227 case AIO: 2228 case RayDAT: 2229 if (hdspm->settings_register & HDSPM_c0Master) 2230 return 0; 2231 break; 2232 2233 default: 2234 if (hdspm->control_register & HDSPM_ClockModeMaster) 2235 return 0; 2236 } 2237 2238 return 1; 2239 } 2240 2241 2242 /** 2243 * Sets the system clock mode. 2244 * @param mode 0 - master, 1 - slave 2245 **/ 2246 static void hdspm_set_system_clock_mode(struct hdspm *hdspm, int mode) 2247 { 2248 switch (hdspm->io_type) { 2249 case AIO: 2250 case RayDAT: 2251 if (0 == mode) 2252 hdspm->settings_register |= HDSPM_c0Master; 2253 else 2254 hdspm->settings_register &= ~HDSPM_c0Master; 2255 2256 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register); 2257 break; 2258 2259 default: 2260 if (0 == mode) 2261 hdspm->control_register |= HDSPM_ClockModeMaster; 2262 else 2263 hdspm->control_register &= ~HDSPM_ClockModeMaster; 2264 2265 hdspm_write(hdspm, HDSPM_controlRegister, 2266 hdspm->control_register); 2267 } 2268 } 2269 2270 2271 static int snd_hdspm_info_system_clock_mode(struct snd_kcontrol *kcontrol, 2272 struct snd_ctl_elem_info *uinfo) 2273 { 2274 static char *texts[] = { "Master", "AutoSync" }; 2275 2276 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2277 uinfo->count = 1; 2278 uinfo->value.enumerated.items = 2; 2279 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 2280 uinfo->value.enumerated.item = 2281 uinfo->value.enumerated.items - 1; 2282 strcpy(uinfo->value.enumerated.name, 2283 texts[uinfo->value.enumerated.item]); 2284 return 0; 2285 } 2286 2287 static int snd_hdspm_get_system_clock_mode(struct snd_kcontrol *kcontrol, 2288 struct snd_ctl_elem_value *ucontrol) 2289 { 2290 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2291 2292 ucontrol->value.enumerated.item[0] = hdspm_system_clock_mode(hdspm); 2293 return 0; 2294 } 2295 2296 static int snd_hdspm_put_system_clock_mode(struct snd_kcontrol *kcontrol, 2297 struct snd_ctl_elem_value *ucontrol) 2298 { 2299 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2300 int val; 2301 2302 if (!snd_hdspm_use_is_exclusive(hdspm)) 2303 return -EBUSY; 2304 2305 val = ucontrol->value.enumerated.item[0]; 2306 if (val < 0) 2307 val = 0; 2308 else if (val > 1) 2309 val = 1; 2310 2311 hdspm_set_system_clock_mode(hdspm, val); 2312 2313 return 0; 2314 } 2315 2316 2317 #define HDSPM_INTERNAL_CLOCK(xname, xindex) \ 2318 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2319 .name = xname, \ 2320 .index = xindex, \ 2321 .info = snd_hdspm_info_clock_source, \ 2322 .get = snd_hdspm_get_clock_source, \ 2323 .put = snd_hdspm_put_clock_source \ 2324 } 2325 2326 2327 static int hdspm_clock_source(struct hdspm * hdspm) 2328 { 2329 switch (hdspm->system_sample_rate) { 2330 case 32000: return 0; 2331 case 44100: return 1; 2332 case 48000: return 2; 2333 case 64000: return 3; 2334 case 88200: return 4; 2335 case 96000: return 5; 2336 case 128000: return 6; 2337 case 176400: return 7; 2338 case 192000: return 8; 2339 } 2340 2341 return -1; 2342 } 2343 2344 static int hdspm_set_clock_source(struct hdspm * hdspm, int mode) 2345 { 2346 int rate; 2347 switch (mode) { 2348 case 0: 2349 rate = 32000; break; 2350 case 1: 2351 rate = 44100; break; 2352 case 2: 2353 rate = 48000; break; 2354 case 3: 2355 rate = 64000; break; 2356 case 4: 2357 rate = 88200; break; 2358 case 5: 2359 rate = 96000; break; 2360 case 6: 2361 rate = 128000; break; 2362 case 7: 2363 rate = 176400; break; 2364 case 8: 2365 rate = 192000; break; 2366 default: 2367 rate = 48000; 2368 } 2369 hdspm_set_rate(hdspm, rate, 1); 2370 return 0; 2371 } 2372 2373 static int snd_hdspm_info_clock_source(struct snd_kcontrol *kcontrol, 2374 struct snd_ctl_elem_info *uinfo) 2375 { 2376 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2377 uinfo->count = 1; 2378 uinfo->value.enumerated.items = 9; 2379 2380 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 2381 uinfo->value.enumerated.item = 2382 uinfo->value.enumerated.items - 1; 2383 2384 strcpy(uinfo->value.enumerated.name, 2385 texts_freq[uinfo->value.enumerated.item+1]); 2386 2387 return 0; 2388 } 2389 2390 static int snd_hdspm_get_clock_source(struct snd_kcontrol *kcontrol, 2391 struct snd_ctl_elem_value *ucontrol) 2392 { 2393 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2394 2395 ucontrol->value.enumerated.item[0] = hdspm_clock_source(hdspm); 2396 return 0; 2397 } 2398 2399 static int snd_hdspm_put_clock_source(struct snd_kcontrol *kcontrol, 2400 struct snd_ctl_elem_value *ucontrol) 2401 { 2402 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2403 int change; 2404 int val; 2405 2406 if (!snd_hdspm_use_is_exclusive(hdspm)) 2407 return -EBUSY; 2408 val = ucontrol->value.enumerated.item[0]; 2409 if (val < 0) 2410 val = 0; 2411 if (val > 9) 2412 val = 9; 2413 spin_lock_irq(&hdspm->lock); 2414 if (val != hdspm_clock_source(hdspm)) 2415 change = (hdspm_set_clock_source(hdspm, val) == 0) ? 1 : 0; 2416 else 2417 change = 0; 2418 spin_unlock_irq(&hdspm->lock); 2419 return change; 2420 } 2421 2422 2423 #define HDSPM_PREF_SYNC_REF(xname, xindex) \ 2424 {.iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2425 .name = xname, \ 2426 .index = xindex, \ 2427 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 2428 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 2429 .info = snd_hdspm_info_pref_sync_ref, \ 2430 .get = snd_hdspm_get_pref_sync_ref, \ 2431 .put = snd_hdspm_put_pref_sync_ref \ 2432 } 2433 2434 2435 /** 2436 * Returns the current preferred sync reference setting. 2437 * The semantics of the return value are depending on the 2438 * card, please see the comments for clarification. 2439 **/ 2440 static int hdspm_pref_sync_ref(struct hdspm * hdspm) 2441 { 2442 switch (hdspm->io_type) { 2443 case AES32: 2444 switch (hdspm->control_register & HDSPM_SyncRefMask) { 2445 case 0: return 0; /* WC */ 2446 case HDSPM_SyncRef0: return 1; /* AES 1 */ 2447 case HDSPM_SyncRef1: return 2; /* AES 2 */ 2448 case HDSPM_SyncRef1+HDSPM_SyncRef0: return 3; /* AES 3 */ 2449 case HDSPM_SyncRef2: return 4; /* AES 4 */ 2450 case HDSPM_SyncRef2+HDSPM_SyncRef0: return 5; /* AES 5 */ 2451 case HDSPM_SyncRef2+HDSPM_SyncRef1: return 6; /* AES 6 */ 2452 case HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0: 2453 return 7; /* AES 7 */ 2454 case HDSPM_SyncRef3: return 8; /* AES 8 */ 2455 case HDSPM_SyncRef3+HDSPM_SyncRef0: return 9; /* TCO */ 2456 } 2457 break; 2458 2459 case MADI: 2460 case MADIface: 2461 if (hdspm->tco) { 2462 switch (hdspm->control_register & HDSPM_SyncRefMask) { 2463 case 0: return 0; /* WC */ 2464 case HDSPM_SyncRef0: return 1; /* MADI */ 2465 case HDSPM_SyncRef1: return 2; /* TCO */ 2466 case HDSPM_SyncRef1+HDSPM_SyncRef0: 2467 return 3; /* SYNC_IN */ 2468 } 2469 } else { 2470 switch (hdspm->control_register & HDSPM_SyncRefMask) { 2471 case 0: return 0; /* WC */ 2472 case HDSPM_SyncRef0: return 1; /* MADI */ 2473 case HDSPM_SyncRef1+HDSPM_SyncRef0: 2474 return 2; /* SYNC_IN */ 2475 } 2476 } 2477 break; 2478 2479 case RayDAT: 2480 if (hdspm->tco) { 2481 switch ((hdspm->settings_register & 2482 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) { 2483 case 0: return 0; /* WC */ 2484 case 3: return 1; /* ADAT 1 */ 2485 case 4: return 2; /* ADAT 2 */ 2486 case 5: return 3; /* ADAT 3 */ 2487 case 6: return 4; /* ADAT 4 */ 2488 case 1: return 5; /* AES */ 2489 case 2: return 6; /* SPDIF */ 2490 case 9: return 7; /* TCO */ 2491 case 10: return 8; /* SYNC_IN */ 2492 } 2493 } else { 2494 switch ((hdspm->settings_register & 2495 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) { 2496 case 0: return 0; /* WC */ 2497 case 3: return 1; /* ADAT 1 */ 2498 case 4: return 2; /* ADAT 2 */ 2499 case 5: return 3; /* ADAT 3 */ 2500 case 6: return 4; /* ADAT 4 */ 2501 case 1: return 5; /* AES */ 2502 case 2: return 6; /* SPDIF */ 2503 case 10: return 7; /* SYNC_IN */ 2504 } 2505 } 2506 2507 break; 2508 2509 case AIO: 2510 if (hdspm->tco) { 2511 switch ((hdspm->settings_register & 2512 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) { 2513 case 0: return 0; /* WC */ 2514 case 3: return 1; /* ADAT */ 2515 case 1: return 2; /* AES */ 2516 case 2: return 3; /* SPDIF */ 2517 case 9: return 4; /* TCO */ 2518 case 10: return 5; /* SYNC_IN */ 2519 } 2520 } else { 2521 switch ((hdspm->settings_register & 2522 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) { 2523 case 0: return 0; /* WC */ 2524 case 3: return 1; /* ADAT */ 2525 case 1: return 2; /* AES */ 2526 case 2: return 3; /* SPDIF */ 2527 case 10: return 4; /* SYNC_IN */ 2528 } 2529 } 2530 2531 break; 2532 } 2533 2534 return -1; 2535 } 2536 2537 2538 /** 2539 * Set the preferred sync reference to <pref>. The semantics 2540 * of <pref> are depending on the card type, see the comments 2541 * for clarification. 2542 **/ 2543 static int hdspm_set_pref_sync_ref(struct hdspm * hdspm, int pref) 2544 { 2545 int p = 0; 2546 2547 switch (hdspm->io_type) { 2548 case AES32: 2549 hdspm->control_register &= ~HDSPM_SyncRefMask; 2550 switch (pref) { 2551 case 0: /* WC */ 2552 break; 2553 case 1: /* AES 1 */ 2554 hdspm->control_register |= HDSPM_SyncRef0; 2555 break; 2556 case 2: /* AES 2 */ 2557 hdspm->control_register |= HDSPM_SyncRef1; 2558 break; 2559 case 3: /* AES 3 */ 2560 hdspm->control_register |= 2561 HDSPM_SyncRef1+HDSPM_SyncRef0; 2562 break; 2563 case 4: /* AES 4 */ 2564 hdspm->control_register |= HDSPM_SyncRef2; 2565 break; 2566 case 5: /* AES 5 */ 2567 hdspm->control_register |= 2568 HDSPM_SyncRef2+HDSPM_SyncRef0; 2569 break; 2570 case 6: /* AES 6 */ 2571 hdspm->control_register |= 2572 HDSPM_SyncRef2+HDSPM_SyncRef1; 2573 break; 2574 case 7: /* AES 7 */ 2575 hdspm->control_register |= 2576 HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0; 2577 break; 2578 case 8: /* AES 8 */ 2579 hdspm->control_register |= HDSPM_SyncRef3; 2580 break; 2581 case 9: /* TCO */ 2582 hdspm->control_register |= 2583 HDSPM_SyncRef3+HDSPM_SyncRef0; 2584 break; 2585 default: 2586 return -1; 2587 } 2588 2589 break; 2590 2591 case MADI: 2592 case MADIface: 2593 hdspm->control_register &= ~HDSPM_SyncRefMask; 2594 if (hdspm->tco) { 2595 switch (pref) { 2596 case 0: /* WC */ 2597 break; 2598 case 1: /* MADI */ 2599 hdspm->control_register |= HDSPM_SyncRef0; 2600 break; 2601 case 2: /* TCO */ 2602 hdspm->control_register |= HDSPM_SyncRef1; 2603 break; 2604 case 3: /* SYNC_IN */ 2605 hdspm->control_register |= 2606 HDSPM_SyncRef0+HDSPM_SyncRef1; 2607 break; 2608 default: 2609 return -1; 2610 } 2611 } else { 2612 switch (pref) { 2613 case 0: /* WC */ 2614 break; 2615 case 1: /* MADI */ 2616 hdspm->control_register |= HDSPM_SyncRef0; 2617 break; 2618 case 2: /* SYNC_IN */ 2619 hdspm->control_register |= 2620 HDSPM_SyncRef0+HDSPM_SyncRef1; 2621 break; 2622 default: 2623 return -1; 2624 } 2625 } 2626 2627 break; 2628 2629 case RayDAT: 2630 if (hdspm->tco) { 2631 switch (pref) { 2632 case 0: p = 0; break; /* WC */ 2633 case 1: p = 3; break; /* ADAT 1 */ 2634 case 2: p = 4; break; /* ADAT 2 */ 2635 case 3: p = 5; break; /* ADAT 3 */ 2636 case 4: p = 6; break; /* ADAT 4 */ 2637 case 5: p = 1; break; /* AES */ 2638 case 6: p = 2; break; /* SPDIF */ 2639 case 7: p = 9; break; /* TCO */ 2640 case 8: p = 10; break; /* SYNC_IN */ 2641 default: return -1; 2642 } 2643 } else { 2644 switch (pref) { 2645 case 0: p = 0; break; /* WC */ 2646 case 1: p = 3; break; /* ADAT 1 */ 2647 case 2: p = 4; break; /* ADAT 2 */ 2648 case 3: p = 5; break; /* ADAT 3 */ 2649 case 4: p = 6; break; /* ADAT 4 */ 2650 case 5: p = 1; break; /* AES */ 2651 case 6: p = 2; break; /* SPDIF */ 2652 case 7: p = 10; break; /* SYNC_IN */ 2653 default: return -1; 2654 } 2655 } 2656 break; 2657 2658 case AIO: 2659 if (hdspm->tco) { 2660 switch (pref) { 2661 case 0: p = 0; break; /* WC */ 2662 case 1: p = 3; break; /* ADAT */ 2663 case 2: p = 1; break; /* AES */ 2664 case 3: p = 2; break; /* SPDIF */ 2665 case 4: p = 9; break; /* TCO */ 2666 case 5: p = 10; break; /* SYNC_IN */ 2667 default: return -1; 2668 } 2669 } else { 2670 switch (pref) { 2671 case 0: p = 0; break; /* WC */ 2672 case 1: p = 3; break; /* ADAT */ 2673 case 2: p = 1; break; /* AES */ 2674 case 3: p = 2; break; /* SPDIF */ 2675 case 4: p = 10; break; /* SYNC_IN */ 2676 default: return -1; 2677 } 2678 } 2679 break; 2680 } 2681 2682 switch (hdspm->io_type) { 2683 case RayDAT: 2684 case AIO: 2685 hdspm->settings_register &= ~HDSPM_c0_SyncRefMask; 2686 hdspm->settings_register |= HDSPM_c0_SyncRef0 * p; 2687 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register); 2688 break; 2689 2690 case MADI: 2691 case MADIface: 2692 case AES32: 2693 hdspm_write(hdspm, HDSPM_controlRegister, 2694 hdspm->control_register); 2695 } 2696 2697 return 0; 2698 } 2699 2700 2701 static int snd_hdspm_info_pref_sync_ref(struct snd_kcontrol *kcontrol, 2702 struct snd_ctl_elem_info *uinfo) 2703 { 2704 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2705 2706 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2707 uinfo->count = 1; 2708 uinfo->value.enumerated.items = hdspm->texts_autosync_items; 2709 2710 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 2711 uinfo->value.enumerated.item = 2712 uinfo->value.enumerated.items - 1; 2713 2714 strcpy(uinfo->value.enumerated.name, 2715 hdspm->texts_autosync[uinfo->value.enumerated.item]); 2716 2717 return 0; 2718 } 2719 2720 static int snd_hdspm_get_pref_sync_ref(struct snd_kcontrol *kcontrol, 2721 struct snd_ctl_elem_value *ucontrol) 2722 { 2723 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2724 int psf = hdspm_pref_sync_ref(hdspm); 2725 2726 if (psf >= 0) { 2727 ucontrol->value.enumerated.item[0] = psf; 2728 return 0; 2729 } 2730 2731 return -1; 2732 } 2733 2734 static int snd_hdspm_put_pref_sync_ref(struct snd_kcontrol *kcontrol, 2735 struct snd_ctl_elem_value *ucontrol) 2736 { 2737 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2738 int val, change = 0; 2739 2740 if (!snd_hdspm_use_is_exclusive(hdspm)) 2741 return -EBUSY; 2742 2743 val = ucontrol->value.enumerated.item[0]; 2744 2745 if (val < 0) 2746 val = 0; 2747 else if (val >= hdspm->texts_autosync_items) 2748 val = hdspm->texts_autosync_items-1; 2749 2750 spin_lock_irq(&hdspm->lock); 2751 if (val != hdspm_pref_sync_ref(hdspm)) 2752 change = (0 == hdspm_set_pref_sync_ref(hdspm, val)) ? 1 : 0; 2753 2754 spin_unlock_irq(&hdspm->lock); 2755 return change; 2756 } 2757 2758 2759 #define HDSPM_AUTOSYNC_REF(xname, xindex) \ 2760 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2761 .name = xname, \ 2762 .index = xindex, \ 2763 .access = SNDRV_CTL_ELEM_ACCESS_READ, \ 2764 .info = snd_hdspm_info_autosync_ref, \ 2765 .get = snd_hdspm_get_autosync_ref, \ 2766 } 2767 2768 static int hdspm_autosync_ref(struct hdspm *hdspm) 2769 { 2770 if (AES32 == hdspm->io_type) { 2771 unsigned int status = hdspm_read(hdspm, HDSPM_statusRegister); 2772 unsigned int syncref = 2773 (status >> HDSPM_AES32_syncref_bit) & 0xF; 2774 if (syncref == 0) 2775 return HDSPM_AES32_AUTOSYNC_FROM_WORD; 2776 if (syncref <= 8) 2777 return syncref; 2778 return HDSPM_AES32_AUTOSYNC_FROM_NONE; 2779 } else if (MADI == hdspm->io_type) { 2780 /* This looks at the autosync selected sync reference */ 2781 unsigned int status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 2782 2783 switch (status2 & HDSPM_SelSyncRefMask) { 2784 case HDSPM_SelSyncRef_WORD: 2785 return HDSPM_AUTOSYNC_FROM_WORD; 2786 case HDSPM_SelSyncRef_MADI: 2787 return HDSPM_AUTOSYNC_FROM_MADI; 2788 case HDSPM_SelSyncRef_TCO: 2789 return HDSPM_AUTOSYNC_FROM_TCO; 2790 case HDSPM_SelSyncRef_SyncIn: 2791 return HDSPM_AUTOSYNC_FROM_SYNC_IN; 2792 case HDSPM_SelSyncRef_NVALID: 2793 return HDSPM_AUTOSYNC_FROM_NONE; 2794 default: 2795 return 0; 2796 } 2797 2798 } 2799 return 0; 2800 } 2801 2802 2803 static int snd_hdspm_info_autosync_ref(struct snd_kcontrol *kcontrol, 2804 struct snd_ctl_elem_info *uinfo) 2805 { 2806 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2807 2808 if (AES32 == hdspm->io_type) { 2809 static char *texts[] = { "WordClock", "AES1", "AES2", "AES3", 2810 "AES4", "AES5", "AES6", "AES7", "AES8", "None"}; 2811 2812 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2813 uinfo->count = 1; 2814 uinfo->value.enumerated.items = 10; 2815 if (uinfo->value.enumerated.item >= 2816 uinfo->value.enumerated.items) 2817 uinfo->value.enumerated.item = 2818 uinfo->value.enumerated.items - 1; 2819 strcpy(uinfo->value.enumerated.name, 2820 texts[uinfo->value.enumerated.item]); 2821 } else if (MADI == hdspm->io_type) { 2822 static char *texts[] = {"Word Clock", "MADI", "TCO", 2823 "Sync In", "None" }; 2824 2825 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2826 uinfo->count = 1; 2827 uinfo->value.enumerated.items = 5; 2828 if (uinfo->value.enumerated.item >= 2829 uinfo->value.enumerated.items) 2830 uinfo->value.enumerated.item = 2831 uinfo->value.enumerated.items - 1; 2832 strcpy(uinfo->value.enumerated.name, 2833 texts[uinfo->value.enumerated.item]); 2834 } 2835 return 0; 2836 } 2837 2838 static int snd_hdspm_get_autosync_ref(struct snd_kcontrol *kcontrol, 2839 struct snd_ctl_elem_value *ucontrol) 2840 { 2841 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2842 2843 ucontrol->value.enumerated.item[0] = hdspm_autosync_ref(hdspm); 2844 return 0; 2845 } 2846 2847 2848 #define HDSPM_LINE_OUT(xname, xindex) \ 2849 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2850 .name = xname, \ 2851 .index = xindex, \ 2852 .info = snd_hdspm_info_line_out, \ 2853 .get = snd_hdspm_get_line_out, \ 2854 .put = snd_hdspm_put_line_out \ 2855 } 2856 2857 static int hdspm_line_out(struct hdspm * hdspm) 2858 { 2859 return (hdspm->control_register & HDSPM_LineOut) ? 1 : 0; 2860 } 2861 2862 2863 static int hdspm_set_line_output(struct hdspm * hdspm, int out) 2864 { 2865 if (out) 2866 hdspm->control_register |= HDSPM_LineOut; 2867 else 2868 hdspm->control_register &= ~HDSPM_LineOut; 2869 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 2870 2871 return 0; 2872 } 2873 2874 #define snd_hdspm_info_line_out snd_ctl_boolean_mono_info 2875 2876 static int snd_hdspm_get_line_out(struct snd_kcontrol *kcontrol, 2877 struct snd_ctl_elem_value *ucontrol) 2878 { 2879 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2880 2881 spin_lock_irq(&hdspm->lock); 2882 ucontrol->value.integer.value[0] = hdspm_line_out(hdspm); 2883 spin_unlock_irq(&hdspm->lock); 2884 return 0; 2885 } 2886 2887 static int snd_hdspm_put_line_out(struct snd_kcontrol *kcontrol, 2888 struct snd_ctl_elem_value *ucontrol) 2889 { 2890 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2891 int change; 2892 unsigned int val; 2893 2894 if (!snd_hdspm_use_is_exclusive(hdspm)) 2895 return -EBUSY; 2896 val = ucontrol->value.integer.value[0] & 1; 2897 spin_lock_irq(&hdspm->lock); 2898 change = (int) val != hdspm_line_out(hdspm); 2899 hdspm_set_line_output(hdspm, val); 2900 spin_unlock_irq(&hdspm->lock); 2901 return change; 2902 } 2903 2904 2905 #define HDSPM_TX_64(xname, xindex) \ 2906 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2907 .name = xname, \ 2908 .index = xindex, \ 2909 .info = snd_hdspm_info_tx_64, \ 2910 .get = snd_hdspm_get_tx_64, \ 2911 .put = snd_hdspm_put_tx_64 \ 2912 } 2913 2914 static int hdspm_tx_64(struct hdspm * hdspm) 2915 { 2916 return (hdspm->control_register & HDSPM_TX_64ch) ? 1 : 0; 2917 } 2918 2919 static int hdspm_set_tx_64(struct hdspm * hdspm, int out) 2920 { 2921 if (out) 2922 hdspm->control_register |= HDSPM_TX_64ch; 2923 else 2924 hdspm->control_register &= ~HDSPM_TX_64ch; 2925 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 2926 2927 return 0; 2928 } 2929 2930 #define snd_hdspm_info_tx_64 snd_ctl_boolean_mono_info 2931 2932 static int snd_hdspm_get_tx_64(struct snd_kcontrol *kcontrol, 2933 struct snd_ctl_elem_value *ucontrol) 2934 { 2935 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2936 2937 spin_lock_irq(&hdspm->lock); 2938 ucontrol->value.integer.value[0] = hdspm_tx_64(hdspm); 2939 spin_unlock_irq(&hdspm->lock); 2940 return 0; 2941 } 2942 2943 static int snd_hdspm_put_tx_64(struct snd_kcontrol *kcontrol, 2944 struct snd_ctl_elem_value *ucontrol) 2945 { 2946 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2947 int change; 2948 unsigned int val; 2949 2950 if (!snd_hdspm_use_is_exclusive(hdspm)) 2951 return -EBUSY; 2952 val = ucontrol->value.integer.value[0] & 1; 2953 spin_lock_irq(&hdspm->lock); 2954 change = (int) val != hdspm_tx_64(hdspm); 2955 hdspm_set_tx_64(hdspm, val); 2956 spin_unlock_irq(&hdspm->lock); 2957 return change; 2958 } 2959 2960 2961 #define HDSPM_C_TMS(xname, xindex) \ 2962 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2963 .name = xname, \ 2964 .index = xindex, \ 2965 .info = snd_hdspm_info_c_tms, \ 2966 .get = snd_hdspm_get_c_tms, \ 2967 .put = snd_hdspm_put_c_tms \ 2968 } 2969 2970 static int hdspm_c_tms(struct hdspm * hdspm) 2971 { 2972 return (hdspm->control_register & HDSPM_clr_tms) ? 1 : 0; 2973 } 2974 2975 static int hdspm_set_c_tms(struct hdspm * hdspm, int out) 2976 { 2977 if (out) 2978 hdspm->control_register |= HDSPM_clr_tms; 2979 else 2980 hdspm->control_register &= ~HDSPM_clr_tms; 2981 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 2982 2983 return 0; 2984 } 2985 2986 #define snd_hdspm_info_c_tms snd_ctl_boolean_mono_info 2987 2988 static int snd_hdspm_get_c_tms(struct snd_kcontrol *kcontrol, 2989 struct snd_ctl_elem_value *ucontrol) 2990 { 2991 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2992 2993 spin_lock_irq(&hdspm->lock); 2994 ucontrol->value.integer.value[0] = hdspm_c_tms(hdspm); 2995 spin_unlock_irq(&hdspm->lock); 2996 return 0; 2997 } 2998 2999 static int snd_hdspm_put_c_tms(struct snd_kcontrol *kcontrol, 3000 struct snd_ctl_elem_value *ucontrol) 3001 { 3002 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3003 int change; 3004 unsigned int val; 3005 3006 if (!snd_hdspm_use_is_exclusive(hdspm)) 3007 return -EBUSY; 3008 val = ucontrol->value.integer.value[0] & 1; 3009 spin_lock_irq(&hdspm->lock); 3010 change = (int) val != hdspm_c_tms(hdspm); 3011 hdspm_set_c_tms(hdspm, val); 3012 spin_unlock_irq(&hdspm->lock); 3013 return change; 3014 } 3015 3016 3017 #define HDSPM_SAFE_MODE(xname, xindex) \ 3018 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3019 .name = xname, \ 3020 .index = xindex, \ 3021 .info = snd_hdspm_info_safe_mode, \ 3022 .get = snd_hdspm_get_safe_mode, \ 3023 .put = snd_hdspm_put_safe_mode \ 3024 } 3025 3026 static int hdspm_safe_mode(struct hdspm * hdspm) 3027 { 3028 return (hdspm->control_register & HDSPM_AutoInp) ? 1 : 0; 3029 } 3030 3031 static int hdspm_set_safe_mode(struct hdspm * hdspm, int out) 3032 { 3033 if (out) 3034 hdspm->control_register |= HDSPM_AutoInp; 3035 else 3036 hdspm->control_register &= ~HDSPM_AutoInp; 3037 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 3038 3039 return 0; 3040 } 3041 3042 #define snd_hdspm_info_safe_mode snd_ctl_boolean_mono_info 3043 3044 static int snd_hdspm_get_safe_mode(struct snd_kcontrol *kcontrol, 3045 struct snd_ctl_elem_value *ucontrol) 3046 { 3047 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3048 3049 spin_lock_irq(&hdspm->lock); 3050 ucontrol->value.integer.value[0] = hdspm_safe_mode(hdspm); 3051 spin_unlock_irq(&hdspm->lock); 3052 return 0; 3053 } 3054 3055 static int snd_hdspm_put_safe_mode(struct snd_kcontrol *kcontrol, 3056 struct snd_ctl_elem_value *ucontrol) 3057 { 3058 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3059 int change; 3060 unsigned int val; 3061 3062 if (!snd_hdspm_use_is_exclusive(hdspm)) 3063 return -EBUSY; 3064 val = ucontrol->value.integer.value[0] & 1; 3065 spin_lock_irq(&hdspm->lock); 3066 change = (int) val != hdspm_safe_mode(hdspm); 3067 hdspm_set_safe_mode(hdspm, val); 3068 spin_unlock_irq(&hdspm->lock); 3069 return change; 3070 } 3071 3072 3073 #define HDSPM_EMPHASIS(xname, xindex) \ 3074 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3075 .name = xname, \ 3076 .index = xindex, \ 3077 .info = snd_hdspm_info_emphasis, \ 3078 .get = snd_hdspm_get_emphasis, \ 3079 .put = snd_hdspm_put_emphasis \ 3080 } 3081 3082 static int hdspm_emphasis(struct hdspm * hdspm) 3083 { 3084 return (hdspm->control_register & HDSPM_Emphasis) ? 1 : 0; 3085 } 3086 3087 static int hdspm_set_emphasis(struct hdspm * hdspm, int emp) 3088 { 3089 if (emp) 3090 hdspm->control_register |= HDSPM_Emphasis; 3091 else 3092 hdspm->control_register &= ~HDSPM_Emphasis; 3093 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 3094 3095 return 0; 3096 } 3097 3098 #define snd_hdspm_info_emphasis snd_ctl_boolean_mono_info 3099 3100 static int snd_hdspm_get_emphasis(struct snd_kcontrol *kcontrol, 3101 struct snd_ctl_elem_value *ucontrol) 3102 { 3103 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3104 3105 spin_lock_irq(&hdspm->lock); 3106 ucontrol->value.enumerated.item[0] = hdspm_emphasis(hdspm); 3107 spin_unlock_irq(&hdspm->lock); 3108 return 0; 3109 } 3110 3111 static int snd_hdspm_put_emphasis(struct snd_kcontrol *kcontrol, 3112 struct snd_ctl_elem_value *ucontrol) 3113 { 3114 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3115 int change; 3116 unsigned int val; 3117 3118 if (!snd_hdspm_use_is_exclusive(hdspm)) 3119 return -EBUSY; 3120 val = ucontrol->value.integer.value[0] & 1; 3121 spin_lock_irq(&hdspm->lock); 3122 change = (int) val != hdspm_emphasis(hdspm); 3123 hdspm_set_emphasis(hdspm, val); 3124 spin_unlock_irq(&hdspm->lock); 3125 return change; 3126 } 3127 3128 3129 #define HDSPM_DOLBY(xname, xindex) \ 3130 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3131 .name = xname, \ 3132 .index = xindex, \ 3133 .info = snd_hdspm_info_dolby, \ 3134 .get = snd_hdspm_get_dolby, \ 3135 .put = snd_hdspm_put_dolby \ 3136 } 3137 3138 static int hdspm_dolby(struct hdspm * hdspm) 3139 { 3140 return (hdspm->control_register & HDSPM_Dolby) ? 1 : 0; 3141 } 3142 3143 static int hdspm_set_dolby(struct hdspm * hdspm, int dol) 3144 { 3145 if (dol) 3146 hdspm->control_register |= HDSPM_Dolby; 3147 else 3148 hdspm->control_register &= ~HDSPM_Dolby; 3149 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 3150 3151 return 0; 3152 } 3153 3154 #define snd_hdspm_info_dolby snd_ctl_boolean_mono_info 3155 3156 static int snd_hdspm_get_dolby(struct snd_kcontrol *kcontrol, 3157 struct snd_ctl_elem_value *ucontrol) 3158 { 3159 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3160 3161 spin_lock_irq(&hdspm->lock); 3162 ucontrol->value.enumerated.item[0] = hdspm_dolby(hdspm); 3163 spin_unlock_irq(&hdspm->lock); 3164 return 0; 3165 } 3166 3167 static int snd_hdspm_put_dolby(struct snd_kcontrol *kcontrol, 3168 struct snd_ctl_elem_value *ucontrol) 3169 { 3170 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3171 int change; 3172 unsigned int val; 3173 3174 if (!snd_hdspm_use_is_exclusive(hdspm)) 3175 return -EBUSY; 3176 val = ucontrol->value.integer.value[0] & 1; 3177 spin_lock_irq(&hdspm->lock); 3178 change = (int) val != hdspm_dolby(hdspm); 3179 hdspm_set_dolby(hdspm, val); 3180 spin_unlock_irq(&hdspm->lock); 3181 return change; 3182 } 3183 3184 3185 #define HDSPM_PROFESSIONAL(xname, xindex) \ 3186 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3187 .name = xname, \ 3188 .index = xindex, \ 3189 .info = snd_hdspm_info_professional, \ 3190 .get = snd_hdspm_get_professional, \ 3191 .put = snd_hdspm_put_professional \ 3192 } 3193 3194 static int hdspm_professional(struct hdspm * hdspm) 3195 { 3196 return (hdspm->control_register & HDSPM_Professional) ? 1 : 0; 3197 } 3198 3199 static int hdspm_set_professional(struct hdspm * hdspm, int dol) 3200 { 3201 if (dol) 3202 hdspm->control_register |= HDSPM_Professional; 3203 else 3204 hdspm->control_register &= ~HDSPM_Professional; 3205 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 3206 3207 return 0; 3208 } 3209 3210 #define snd_hdspm_info_professional snd_ctl_boolean_mono_info 3211 3212 static int snd_hdspm_get_professional(struct snd_kcontrol *kcontrol, 3213 struct snd_ctl_elem_value *ucontrol) 3214 { 3215 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3216 3217 spin_lock_irq(&hdspm->lock); 3218 ucontrol->value.enumerated.item[0] = hdspm_professional(hdspm); 3219 spin_unlock_irq(&hdspm->lock); 3220 return 0; 3221 } 3222 3223 static int snd_hdspm_put_professional(struct snd_kcontrol *kcontrol, 3224 struct snd_ctl_elem_value *ucontrol) 3225 { 3226 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3227 int change; 3228 unsigned int val; 3229 3230 if (!snd_hdspm_use_is_exclusive(hdspm)) 3231 return -EBUSY; 3232 val = ucontrol->value.integer.value[0] & 1; 3233 spin_lock_irq(&hdspm->lock); 3234 change = (int) val != hdspm_professional(hdspm); 3235 hdspm_set_professional(hdspm, val); 3236 spin_unlock_irq(&hdspm->lock); 3237 return change; 3238 } 3239 3240 #define HDSPM_INPUT_SELECT(xname, xindex) \ 3241 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3242 .name = xname, \ 3243 .index = xindex, \ 3244 .info = snd_hdspm_info_input_select, \ 3245 .get = snd_hdspm_get_input_select, \ 3246 .put = snd_hdspm_put_input_select \ 3247 } 3248 3249 static int hdspm_input_select(struct hdspm * hdspm) 3250 { 3251 return (hdspm->control_register & HDSPM_InputSelect0) ? 1 : 0; 3252 } 3253 3254 static int hdspm_set_input_select(struct hdspm * hdspm, int out) 3255 { 3256 if (out) 3257 hdspm->control_register |= HDSPM_InputSelect0; 3258 else 3259 hdspm->control_register &= ~HDSPM_InputSelect0; 3260 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 3261 3262 return 0; 3263 } 3264 3265 static int snd_hdspm_info_input_select(struct snd_kcontrol *kcontrol, 3266 struct snd_ctl_elem_info *uinfo) 3267 { 3268 static char *texts[] = { "optical", "coaxial" }; 3269 3270 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 3271 uinfo->count = 1; 3272 uinfo->value.enumerated.items = 2; 3273 3274 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 3275 uinfo->value.enumerated.item = 3276 uinfo->value.enumerated.items - 1; 3277 strcpy(uinfo->value.enumerated.name, 3278 texts[uinfo->value.enumerated.item]); 3279 3280 return 0; 3281 } 3282 3283 static int snd_hdspm_get_input_select(struct snd_kcontrol *kcontrol, 3284 struct snd_ctl_elem_value *ucontrol) 3285 { 3286 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3287 3288 spin_lock_irq(&hdspm->lock); 3289 ucontrol->value.enumerated.item[0] = hdspm_input_select(hdspm); 3290 spin_unlock_irq(&hdspm->lock); 3291 return 0; 3292 } 3293 3294 static int snd_hdspm_put_input_select(struct snd_kcontrol *kcontrol, 3295 struct snd_ctl_elem_value *ucontrol) 3296 { 3297 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3298 int change; 3299 unsigned int val; 3300 3301 if (!snd_hdspm_use_is_exclusive(hdspm)) 3302 return -EBUSY; 3303 val = ucontrol->value.integer.value[0] & 1; 3304 spin_lock_irq(&hdspm->lock); 3305 change = (int) val != hdspm_input_select(hdspm); 3306 hdspm_set_input_select(hdspm, val); 3307 spin_unlock_irq(&hdspm->lock); 3308 return change; 3309 } 3310 3311 3312 #define HDSPM_DS_WIRE(xname, xindex) \ 3313 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3314 .name = xname, \ 3315 .index = xindex, \ 3316 .info = snd_hdspm_info_ds_wire, \ 3317 .get = snd_hdspm_get_ds_wire, \ 3318 .put = snd_hdspm_put_ds_wire \ 3319 } 3320 3321 static int hdspm_ds_wire(struct hdspm * hdspm) 3322 { 3323 return (hdspm->control_register & HDSPM_DS_DoubleWire) ? 1 : 0; 3324 } 3325 3326 static int hdspm_set_ds_wire(struct hdspm * hdspm, int ds) 3327 { 3328 if (ds) 3329 hdspm->control_register |= HDSPM_DS_DoubleWire; 3330 else 3331 hdspm->control_register &= ~HDSPM_DS_DoubleWire; 3332 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 3333 3334 return 0; 3335 } 3336 3337 static int snd_hdspm_info_ds_wire(struct snd_kcontrol *kcontrol, 3338 struct snd_ctl_elem_info *uinfo) 3339 { 3340 static char *texts[] = { "Single", "Double" }; 3341 3342 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 3343 uinfo->count = 1; 3344 uinfo->value.enumerated.items = 2; 3345 3346 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 3347 uinfo->value.enumerated.item = 3348 uinfo->value.enumerated.items - 1; 3349 strcpy(uinfo->value.enumerated.name, 3350 texts[uinfo->value.enumerated.item]); 3351 3352 return 0; 3353 } 3354 3355 static int snd_hdspm_get_ds_wire(struct snd_kcontrol *kcontrol, 3356 struct snd_ctl_elem_value *ucontrol) 3357 { 3358 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3359 3360 spin_lock_irq(&hdspm->lock); 3361 ucontrol->value.enumerated.item[0] = hdspm_ds_wire(hdspm); 3362 spin_unlock_irq(&hdspm->lock); 3363 return 0; 3364 } 3365 3366 static int snd_hdspm_put_ds_wire(struct snd_kcontrol *kcontrol, 3367 struct snd_ctl_elem_value *ucontrol) 3368 { 3369 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3370 int change; 3371 unsigned int val; 3372 3373 if (!snd_hdspm_use_is_exclusive(hdspm)) 3374 return -EBUSY; 3375 val = ucontrol->value.integer.value[0] & 1; 3376 spin_lock_irq(&hdspm->lock); 3377 change = (int) val != hdspm_ds_wire(hdspm); 3378 hdspm_set_ds_wire(hdspm, val); 3379 spin_unlock_irq(&hdspm->lock); 3380 return change; 3381 } 3382 3383 3384 #define HDSPM_QS_WIRE(xname, xindex) \ 3385 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3386 .name = xname, \ 3387 .index = xindex, \ 3388 .info = snd_hdspm_info_qs_wire, \ 3389 .get = snd_hdspm_get_qs_wire, \ 3390 .put = snd_hdspm_put_qs_wire \ 3391 } 3392 3393 static int hdspm_qs_wire(struct hdspm * hdspm) 3394 { 3395 if (hdspm->control_register & HDSPM_QS_DoubleWire) 3396 return 1; 3397 if (hdspm->control_register & HDSPM_QS_QuadWire) 3398 return 2; 3399 return 0; 3400 } 3401 3402 static int hdspm_set_qs_wire(struct hdspm * hdspm, int mode) 3403 { 3404 hdspm->control_register &= ~(HDSPM_QS_DoubleWire | HDSPM_QS_QuadWire); 3405 switch (mode) { 3406 case 0: 3407 break; 3408 case 1: 3409 hdspm->control_register |= HDSPM_QS_DoubleWire; 3410 break; 3411 case 2: 3412 hdspm->control_register |= HDSPM_QS_QuadWire; 3413 break; 3414 } 3415 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 3416 3417 return 0; 3418 } 3419 3420 static int snd_hdspm_info_qs_wire(struct snd_kcontrol *kcontrol, 3421 struct snd_ctl_elem_info *uinfo) 3422 { 3423 static char *texts[] = { "Single", "Double", "Quad" }; 3424 3425 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 3426 uinfo->count = 1; 3427 uinfo->value.enumerated.items = 3; 3428 3429 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 3430 uinfo->value.enumerated.item = 3431 uinfo->value.enumerated.items - 1; 3432 strcpy(uinfo->value.enumerated.name, 3433 texts[uinfo->value.enumerated.item]); 3434 3435 return 0; 3436 } 3437 3438 static int snd_hdspm_get_qs_wire(struct snd_kcontrol *kcontrol, 3439 struct snd_ctl_elem_value *ucontrol) 3440 { 3441 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3442 3443 spin_lock_irq(&hdspm->lock); 3444 ucontrol->value.enumerated.item[0] = hdspm_qs_wire(hdspm); 3445 spin_unlock_irq(&hdspm->lock); 3446 return 0; 3447 } 3448 3449 static int snd_hdspm_put_qs_wire(struct snd_kcontrol *kcontrol, 3450 struct snd_ctl_elem_value *ucontrol) 3451 { 3452 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3453 int change; 3454 int val; 3455 3456 if (!snd_hdspm_use_is_exclusive(hdspm)) 3457 return -EBUSY; 3458 val = ucontrol->value.integer.value[0]; 3459 if (val < 0) 3460 val = 0; 3461 if (val > 2) 3462 val = 2; 3463 spin_lock_irq(&hdspm->lock); 3464 change = val != hdspm_qs_wire(hdspm); 3465 hdspm_set_qs_wire(hdspm, val); 3466 spin_unlock_irq(&hdspm->lock); 3467 return change; 3468 } 3469 3470 #define HDSPM_MADI_SPEEDMODE(xname, xindex) \ 3471 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3472 .name = xname, \ 3473 .index = xindex, \ 3474 .info = snd_hdspm_info_madi_speedmode, \ 3475 .get = snd_hdspm_get_madi_speedmode, \ 3476 .put = snd_hdspm_put_madi_speedmode \ 3477 } 3478 3479 static int hdspm_madi_speedmode(struct hdspm *hdspm) 3480 { 3481 if (hdspm->control_register & HDSPM_QuadSpeed) 3482 return 2; 3483 if (hdspm->control_register & HDSPM_DoubleSpeed) 3484 return 1; 3485 return 0; 3486 } 3487 3488 static int hdspm_set_madi_speedmode(struct hdspm *hdspm, int mode) 3489 { 3490 hdspm->control_register &= ~(HDSPM_DoubleSpeed | HDSPM_QuadSpeed); 3491 switch (mode) { 3492 case 0: 3493 break; 3494 case 1: 3495 hdspm->control_register |= HDSPM_DoubleSpeed; 3496 break; 3497 case 2: 3498 hdspm->control_register |= HDSPM_QuadSpeed; 3499 break; 3500 } 3501 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 3502 3503 return 0; 3504 } 3505 3506 static int snd_hdspm_info_madi_speedmode(struct snd_kcontrol *kcontrol, 3507 struct snd_ctl_elem_info *uinfo) 3508 { 3509 static char *texts[] = { "Single", "Double", "Quad" }; 3510 3511 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 3512 uinfo->count = 1; 3513 uinfo->value.enumerated.items = 3; 3514 3515 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 3516 uinfo->value.enumerated.item = 3517 uinfo->value.enumerated.items - 1; 3518 strcpy(uinfo->value.enumerated.name, 3519 texts[uinfo->value.enumerated.item]); 3520 3521 return 0; 3522 } 3523 3524 static int snd_hdspm_get_madi_speedmode(struct snd_kcontrol *kcontrol, 3525 struct snd_ctl_elem_value *ucontrol) 3526 { 3527 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3528 3529 spin_lock_irq(&hdspm->lock); 3530 ucontrol->value.enumerated.item[0] = hdspm_madi_speedmode(hdspm); 3531 spin_unlock_irq(&hdspm->lock); 3532 return 0; 3533 } 3534 3535 static int snd_hdspm_put_madi_speedmode(struct snd_kcontrol *kcontrol, 3536 struct snd_ctl_elem_value *ucontrol) 3537 { 3538 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3539 int change; 3540 int val; 3541 3542 if (!snd_hdspm_use_is_exclusive(hdspm)) 3543 return -EBUSY; 3544 val = ucontrol->value.integer.value[0]; 3545 if (val < 0) 3546 val = 0; 3547 if (val > 2) 3548 val = 2; 3549 spin_lock_irq(&hdspm->lock); 3550 change = val != hdspm_madi_speedmode(hdspm); 3551 hdspm_set_madi_speedmode(hdspm, val); 3552 spin_unlock_irq(&hdspm->lock); 3553 return change; 3554 } 3555 3556 #define HDSPM_MIXER(xname, xindex) \ 3557 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \ 3558 .name = xname, \ 3559 .index = xindex, \ 3560 .device = 0, \ 3561 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \ 3562 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3563 .info = snd_hdspm_info_mixer, \ 3564 .get = snd_hdspm_get_mixer, \ 3565 .put = snd_hdspm_put_mixer \ 3566 } 3567 3568 static int snd_hdspm_info_mixer(struct snd_kcontrol *kcontrol, 3569 struct snd_ctl_elem_info *uinfo) 3570 { 3571 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 3572 uinfo->count = 3; 3573 uinfo->value.integer.min = 0; 3574 uinfo->value.integer.max = 65535; 3575 uinfo->value.integer.step = 1; 3576 return 0; 3577 } 3578 3579 static int snd_hdspm_get_mixer(struct snd_kcontrol *kcontrol, 3580 struct snd_ctl_elem_value *ucontrol) 3581 { 3582 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3583 int source; 3584 int destination; 3585 3586 source = ucontrol->value.integer.value[0]; 3587 if (source < 0) 3588 source = 0; 3589 else if (source >= 2 * HDSPM_MAX_CHANNELS) 3590 source = 2 * HDSPM_MAX_CHANNELS - 1; 3591 3592 destination = ucontrol->value.integer.value[1]; 3593 if (destination < 0) 3594 destination = 0; 3595 else if (destination >= HDSPM_MAX_CHANNELS) 3596 destination = HDSPM_MAX_CHANNELS - 1; 3597 3598 spin_lock_irq(&hdspm->lock); 3599 if (source >= HDSPM_MAX_CHANNELS) 3600 ucontrol->value.integer.value[2] = 3601 hdspm_read_pb_gain(hdspm, destination, 3602 source - HDSPM_MAX_CHANNELS); 3603 else 3604 ucontrol->value.integer.value[2] = 3605 hdspm_read_in_gain(hdspm, destination, source); 3606 3607 spin_unlock_irq(&hdspm->lock); 3608 3609 return 0; 3610 } 3611 3612 static int snd_hdspm_put_mixer(struct snd_kcontrol *kcontrol, 3613 struct snd_ctl_elem_value *ucontrol) 3614 { 3615 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3616 int change; 3617 int source; 3618 int destination; 3619 int gain; 3620 3621 if (!snd_hdspm_use_is_exclusive(hdspm)) 3622 return -EBUSY; 3623 3624 source = ucontrol->value.integer.value[0]; 3625 destination = ucontrol->value.integer.value[1]; 3626 3627 if (source < 0 || source >= 2 * HDSPM_MAX_CHANNELS) 3628 return -1; 3629 if (destination < 0 || destination >= HDSPM_MAX_CHANNELS) 3630 return -1; 3631 3632 gain = ucontrol->value.integer.value[2]; 3633 3634 spin_lock_irq(&hdspm->lock); 3635 3636 if (source >= HDSPM_MAX_CHANNELS) 3637 change = gain != hdspm_read_pb_gain(hdspm, destination, 3638 source - 3639 HDSPM_MAX_CHANNELS); 3640 else 3641 change = gain != hdspm_read_in_gain(hdspm, destination, 3642 source); 3643 3644 if (change) { 3645 if (source >= HDSPM_MAX_CHANNELS) 3646 hdspm_write_pb_gain(hdspm, destination, 3647 source - HDSPM_MAX_CHANNELS, 3648 gain); 3649 else 3650 hdspm_write_in_gain(hdspm, destination, source, 3651 gain); 3652 } 3653 spin_unlock_irq(&hdspm->lock); 3654 3655 return change; 3656 } 3657 3658 /* The simple mixer control(s) provide gain control for the 3659 basic 1:1 mappings of playback streams to output 3660 streams. 3661 */ 3662 3663 #define HDSPM_PLAYBACK_MIXER \ 3664 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3665 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_WRITE | \ 3666 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3667 .info = snd_hdspm_info_playback_mixer, \ 3668 .get = snd_hdspm_get_playback_mixer, \ 3669 .put = snd_hdspm_put_playback_mixer \ 3670 } 3671 3672 static int snd_hdspm_info_playback_mixer(struct snd_kcontrol *kcontrol, 3673 struct snd_ctl_elem_info *uinfo) 3674 { 3675 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 3676 uinfo->count = 1; 3677 uinfo->value.integer.min = 0; 3678 uinfo->value.integer.max = 64; 3679 uinfo->value.integer.step = 1; 3680 return 0; 3681 } 3682 3683 static int snd_hdspm_get_playback_mixer(struct snd_kcontrol *kcontrol, 3684 struct snd_ctl_elem_value *ucontrol) 3685 { 3686 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3687 int channel; 3688 3689 channel = ucontrol->id.index - 1; 3690 3691 if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS)) 3692 return -EINVAL; 3693 3694 spin_lock_irq(&hdspm->lock); 3695 ucontrol->value.integer.value[0] = 3696 (hdspm_read_pb_gain(hdspm, channel, channel)*64)/UNITY_GAIN; 3697 spin_unlock_irq(&hdspm->lock); 3698 3699 return 0; 3700 } 3701 3702 static int snd_hdspm_put_playback_mixer(struct snd_kcontrol *kcontrol, 3703 struct snd_ctl_elem_value *ucontrol) 3704 { 3705 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3706 int change; 3707 int channel; 3708 int gain; 3709 3710 if (!snd_hdspm_use_is_exclusive(hdspm)) 3711 return -EBUSY; 3712 3713 channel = ucontrol->id.index - 1; 3714 3715 if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS)) 3716 return -EINVAL; 3717 3718 gain = ucontrol->value.integer.value[0]*UNITY_GAIN/64; 3719 3720 spin_lock_irq(&hdspm->lock); 3721 change = 3722 gain != hdspm_read_pb_gain(hdspm, channel, 3723 channel); 3724 if (change) 3725 hdspm_write_pb_gain(hdspm, channel, channel, 3726 gain); 3727 spin_unlock_irq(&hdspm->lock); 3728 return change; 3729 } 3730 3731 #define HDSPM_SYNC_CHECK(xname, xindex) \ 3732 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3733 .name = xname, \ 3734 .private_value = xindex, \ 3735 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3736 .info = snd_hdspm_info_sync_check, \ 3737 .get = snd_hdspm_get_sync_check \ 3738 } 3739 3740 3741 static int snd_hdspm_info_sync_check(struct snd_kcontrol *kcontrol, 3742 struct snd_ctl_elem_info *uinfo) 3743 { 3744 static char *texts[] = { "No Lock", "Lock", "Sync", "N/A" }; 3745 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 3746 uinfo->count = 1; 3747 uinfo->value.enumerated.items = 4; 3748 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 3749 uinfo->value.enumerated.item = 3750 uinfo->value.enumerated.items - 1; 3751 strcpy(uinfo->value.enumerated.name, 3752 texts[uinfo->value.enumerated.item]); 3753 return 0; 3754 } 3755 3756 static int hdspm_wc_sync_check(struct hdspm *hdspm) 3757 { 3758 int status, status2; 3759 3760 switch (hdspm->io_type) { 3761 case AES32: 3762 status = hdspm_read(hdspm, HDSPM_statusRegister); 3763 if (status & HDSPM_wcSync) 3764 return 2; 3765 else if (status & HDSPM_wcLock) 3766 return 1; 3767 return 0; 3768 break; 3769 3770 case MADI: 3771 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 3772 if (status2 & HDSPM_wcLock) { 3773 if (status2 & HDSPM_wcSync) 3774 return 2; 3775 else 3776 return 1; 3777 } 3778 return 0; 3779 break; 3780 3781 case RayDAT: 3782 case AIO: 3783 status = hdspm_read(hdspm, HDSPM_statusRegister); 3784 3785 if (status & 0x2000000) 3786 return 2; 3787 else if (status & 0x1000000) 3788 return 1; 3789 return 0; 3790 3791 break; 3792 3793 case MADIface: 3794 break; 3795 } 3796 3797 3798 return 3; 3799 } 3800 3801 3802 static int hdspm_madi_sync_check(struct hdspm *hdspm) 3803 { 3804 int status = hdspm_read(hdspm, HDSPM_statusRegister); 3805 if (status & HDSPM_madiLock) { 3806 if (status & HDSPM_madiSync) 3807 return 2; 3808 else 3809 return 1; 3810 } 3811 return 0; 3812 } 3813 3814 3815 static int hdspm_s1_sync_check(struct hdspm *hdspm, int idx) 3816 { 3817 int status, lock, sync; 3818 3819 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1); 3820 3821 lock = (status & (0x1<<idx)) ? 1 : 0; 3822 sync = (status & (0x100<<idx)) ? 1 : 0; 3823 3824 if (lock && sync) 3825 return 2; 3826 else if (lock) 3827 return 1; 3828 return 0; 3829 } 3830 3831 3832 static int hdspm_sync_in_sync_check(struct hdspm *hdspm) 3833 { 3834 int status, lock = 0, sync = 0; 3835 3836 switch (hdspm->io_type) { 3837 case RayDAT: 3838 case AIO: 3839 status = hdspm_read(hdspm, HDSPM_RD_STATUS_3); 3840 lock = (status & 0x400) ? 1 : 0; 3841 sync = (status & 0x800) ? 1 : 0; 3842 break; 3843 3844 case MADI: 3845 case AES32: 3846 status = hdspm_read(hdspm, HDSPM_statusRegister2); 3847 lock = (status & HDSPM_syncInLock) ? 1 : 0; 3848 sync = (status & HDSPM_syncInSync) ? 1 : 0; 3849 break; 3850 3851 case MADIface: 3852 break; 3853 } 3854 3855 if (lock && sync) 3856 return 2; 3857 else if (lock) 3858 return 1; 3859 3860 return 0; 3861 } 3862 3863 static int hdspm_aes_sync_check(struct hdspm *hdspm, int idx) 3864 { 3865 int status2, lock, sync; 3866 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 3867 3868 lock = (status2 & (0x0080 >> idx)) ? 1 : 0; 3869 sync = (status2 & (0x8000 >> idx)) ? 1 : 0; 3870 3871 if (sync) 3872 return 2; 3873 else if (lock) 3874 return 1; 3875 return 0; 3876 } 3877 3878 3879 static int hdspm_tco_sync_check(struct hdspm *hdspm) 3880 { 3881 int status; 3882 3883 if (hdspm->tco) { 3884 switch (hdspm->io_type) { 3885 case MADI: 3886 case AES32: 3887 status = hdspm_read(hdspm, HDSPM_statusRegister); 3888 if (status & HDSPM_tcoLock) { 3889 if (status & HDSPM_tcoSync) 3890 return 2; 3891 else 3892 return 1; 3893 } 3894 return 0; 3895 3896 break; 3897 3898 case RayDAT: 3899 case AIO: 3900 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1); 3901 3902 if (status & 0x8000000) 3903 return 2; /* Sync */ 3904 if (status & 0x4000000) 3905 return 1; /* Lock */ 3906 return 0; /* No signal */ 3907 break; 3908 3909 default: 3910 break; 3911 } 3912 } 3913 3914 return 3; /* N/A */ 3915 } 3916 3917 3918 static int snd_hdspm_get_sync_check(struct snd_kcontrol *kcontrol, 3919 struct snd_ctl_elem_value *ucontrol) 3920 { 3921 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3922 int val = -1; 3923 3924 switch (hdspm->io_type) { 3925 case RayDAT: 3926 switch (kcontrol->private_value) { 3927 case 0: /* WC */ 3928 val = hdspm_wc_sync_check(hdspm); break; 3929 case 7: /* TCO */ 3930 val = hdspm_tco_sync_check(hdspm); break; 3931 case 8: /* SYNC IN */ 3932 val = hdspm_sync_in_sync_check(hdspm); break; 3933 default: 3934 val = hdspm_s1_sync_check(hdspm, ucontrol->id.index-1); 3935 } 3936 3937 case AIO: 3938 switch (kcontrol->private_value) { 3939 case 0: /* WC */ 3940 val = hdspm_wc_sync_check(hdspm); break; 3941 case 4: /* TCO */ 3942 val = hdspm_tco_sync_check(hdspm); break; 3943 case 5: /* SYNC IN */ 3944 val = hdspm_sync_in_sync_check(hdspm); break; 3945 default: 3946 val = hdspm_s1_sync_check(hdspm, ucontrol->id.index-1); 3947 } 3948 3949 case MADI: 3950 switch (kcontrol->private_value) { 3951 case 0: /* WC */ 3952 val = hdspm_wc_sync_check(hdspm); break; 3953 case 1: /* MADI */ 3954 val = hdspm_madi_sync_check(hdspm); break; 3955 case 2: /* TCO */ 3956 val = hdspm_tco_sync_check(hdspm); break; 3957 case 3: /* SYNC_IN */ 3958 val = hdspm_sync_in_sync_check(hdspm); break; 3959 } 3960 3961 case MADIface: 3962 val = hdspm_madi_sync_check(hdspm); /* MADI */ 3963 break; 3964 3965 case AES32: 3966 switch (kcontrol->private_value) { 3967 case 0: /* WC */ 3968 val = hdspm_wc_sync_check(hdspm); break; 3969 case 9: /* TCO */ 3970 val = hdspm_tco_sync_check(hdspm); break; 3971 case 10 /* SYNC IN */: 3972 val = hdspm_sync_in_sync_check(hdspm); break; 3973 default: /* AES1 to AES8 */ 3974 val = hdspm_aes_sync_check(hdspm, 3975 kcontrol->private_value-1); 3976 } 3977 3978 } 3979 3980 if (-1 == val) 3981 val = 3; 3982 3983 ucontrol->value.enumerated.item[0] = val; 3984 return 0; 3985 } 3986 3987 3988 3989 /** 3990 * TCO controls 3991 **/ 3992 static void hdspm_tco_write(struct hdspm *hdspm) 3993 { 3994 unsigned int tc[4] = { 0, 0, 0, 0}; 3995 3996 switch (hdspm->tco->input) { 3997 case 0: 3998 tc[2] |= HDSPM_TCO2_set_input_MSB; 3999 break; 4000 case 1: 4001 tc[2] |= HDSPM_TCO2_set_input_LSB; 4002 break; 4003 default: 4004 break; 4005 } 4006 4007 switch (hdspm->tco->framerate) { 4008 case 1: 4009 tc[1] |= HDSPM_TCO1_LTC_Format_LSB; 4010 break; 4011 case 2: 4012 tc[1] |= HDSPM_TCO1_LTC_Format_MSB; 4013 break; 4014 case 3: 4015 tc[1] |= HDSPM_TCO1_LTC_Format_MSB + 4016 HDSPM_TCO1_set_drop_frame_flag; 4017 break; 4018 case 4: 4019 tc[1] |= HDSPM_TCO1_LTC_Format_LSB + 4020 HDSPM_TCO1_LTC_Format_MSB; 4021 break; 4022 case 5: 4023 tc[1] |= HDSPM_TCO1_LTC_Format_LSB + 4024 HDSPM_TCO1_LTC_Format_MSB + 4025 HDSPM_TCO1_set_drop_frame_flag; 4026 break; 4027 default: 4028 break; 4029 } 4030 4031 switch (hdspm->tco->wordclock) { 4032 case 1: 4033 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_LSB; 4034 break; 4035 case 2: 4036 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_MSB; 4037 break; 4038 default: 4039 break; 4040 } 4041 4042 switch (hdspm->tco->samplerate) { 4043 case 1: 4044 tc[2] |= HDSPM_TCO2_set_freq; 4045 break; 4046 case 2: 4047 tc[2] |= HDSPM_TCO2_set_freq_from_app; 4048 break; 4049 default: 4050 break; 4051 } 4052 4053 switch (hdspm->tco->pull) { 4054 case 1: 4055 tc[2] |= HDSPM_TCO2_set_pull_up; 4056 break; 4057 case 2: 4058 tc[2] |= HDSPM_TCO2_set_pull_down; 4059 break; 4060 case 3: 4061 tc[2] |= HDSPM_TCO2_set_pull_up + HDSPM_TCO2_set_01_4; 4062 break; 4063 case 4: 4064 tc[2] |= HDSPM_TCO2_set_pull_down + HDSPM_TCO2_set_01_4; 4065 break; 4066 default: 4067 break; 4068 } 4069 4070 if (1 == hdspm->tco->term) { 4071 tc[2] |= HDSPM_TCO2_set_term_75R; 4072 } 4073 4074 hdspm_write(hdspm, HDSPM_WR_TCO, tc[0]); 4075 hdspm_write(hdspm, HDSPM_WR_TCO+4, tc[1]); 4076 hdspm_write(hdspm, HDSPM_WR_TCO+8, tc[2]); 4077 hdspm_write(hdspm, HDSPM_WR_TCO+12, tc[3]); 4078 } 4079 4080 4081 #define HDSPM_TCO_SAMPLE_RATE(xname, xindex) \ 4082 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4083 .name = xname, \ 4084 .index = xindex, \ 4085 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 4086 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 4087 .info = snd_hdspm_info_tco_sample_rate, \ 4088 .get = snd_hdspm_get_tco_sample_rate, \ 4089 .put = snd_hdspm_put_tco_sample_rate \ 4090 } 4091 4092 static int snd_hdspm_info_tco_sample_rate(struct snd_kcontrol *kcontrol, 4093 struct snd_ctl_elem_info *uinfo) 4094 { 4095 static char *texts[] = { "44.1 kHz", "48 kHz" }; 4096 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 4097 uinfo->count = 1; 4098 uinfo->value.enumerated.items = 2; 4099 4100 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 4101 uinfo->value.enumerated.item = 4102 uinfo->value.enumerated.items - 1; 4103 4104 strcpy(uinfo->value.enumerated.name, 4105 texts[uinfo->value.enumerated.item]); 4106 4107 return 0; 4108 } 4109 4110 static int snd_hdspm_get_tco_sample_rate(struct snd_kcontrol *kcontrol, 4111 struct snd_ctl_elem_value *ucontrol) 4112 { 4113 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4114 4115 ucontrol->value.enumerated.item[0] = hdspm->tco->samplerate; 4116 4117 return 0; 4118 } 4119 4120 static int snd_hdspm_put_tco_sample_rate(struct snd_kcontrol *kcontrol, 4121 struct snd_ctl_elem_value *ucontrol) 4122 { 4123 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4124 4125 if (hdspm->tco->samplerate != ucontrol->value.enumerated.item[0]) { 4126 hdspm->tco->samplerate = ucontrol->value.enumerated.item[0]; 4127 4128 hdspm_tco_write(hdspm); 4129 4130 return 1; 4131 } 4132 4133 return 0; 4134 } 4135 4136 4137 #define HDSPM_TCO_PULL(xname, xindex) \ 4138 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4139 .name = xname, \ 4140 .index = xindex, \ 4141 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 4142 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 4143 .info = snd_hdspm_info_tco_pull, \ 4144 .get = snd_hdspm_get_tco_pull, \ 4145 .put = snd_hdspm_put_tco_pull \ 4146 } 4147 4148 static int snd_hdspm_info_tco_pull(struct snd_kcontrol *kcontrol, 4149 struct snd_ctl_elem_info *uinfo) 4150 { 4151 static char *texts[] = { "0", "+ 0.1 %", "- 0.1 %", "+ 4 %", "- 4 %" }; 4152 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 4153 uinfo->count = 1; 4154 uinfo->value.enumerated.items = 5; 4155 4156 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 4157 uinfo->value.enumerated.item = 4158 uinfo->value.enumerated.items - 1; 4159 4160 strcpy(uinfo->value.enumerated.name, 4161 texts[uinfo->value.enumerated.item]); 4162 4163 return 0; 4164 } 4165 4166 static int snd_hdspm_get_tco_pull(struct snd_kcontrol *kcontrol, 4167 struct snd_ctl_elem_value *ucontrol) 4168 { 4169 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4170 4171 ucontrol->value.enumerated.item[0] = hdspm->tco->pull; 4172 4173 return 0; 4174 } 4175 4176 static int snd_hdspm_put_tco_pull(struct snd_kcontrol *kcontrol, 4177 struct snd_ctl_elem_value *ucontrol) 4178 { 4179 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4180 4181 if (hdspm->tco->pull != ucontrol->value.enumerated.item[0]) { 4182 hdspm->tco->pull = ucontrol->value.enumerated.item[0]; 4183 4184 hdspm_tco_write(hdspm); 4185 4186 return 1; 4187 } 4188 4189 return 0; 4190 } 4191 4192 #define HDSPM_TCO_WCK_CONVERSION(xname, xindex) \ 4193 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4194 .name = xname, \ 4195 .index = xindex, \ 4196 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 4197 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 4198 .info = snd_hdspm_info_tco_wck_conversion, \ 4199 .get = snd_hdspm_get_tco_wck_conversion, \ 4200 .put = snd_hdspm_put_tco_wck_conversion \ 4201 } 4202 4203 static int snd_hdspm_info_tco_wck_conversion(struct snd_kcontrol *kcontrol, 4204 struct snd_ctl_elem_info *uinfo) 4205 { 4206 static char *texts[] = { "1:1", "44.1 -> 48", "48 -> 44.1" }; 4207 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 4208 uinfo->count = 1; 4209 uinfo->value.enumerated.items = 3; 4210 4211 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 4212 uinfo->value.enumerated.item = 4213 uinfo->value.enumerated.items - 1; 4214 4215 strcpy(uinfo->value.enumerated.name, 4216 texts[uinfo->value.enumerated.item]); 4217 4218 return 0; 4219 } 4220 4221 static int snd_hdspm_get_tco_wck_conversion(struct snd_kcontrol *kcontrol, 4222 struct snd_ctl_elem_value *ucontrol) 4223 { 4224 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4225 4226 ucontrol->value.enumerated.item[0] = hdspm->tco->wordclock; 4227 4228 return 0; 4229 } 4230 4231 static int snd_hdspm_put_tco_wck_conversion(struct snd_kcontrol *kcontrol, 4232 struct snd_ctl_elem_value *ucontrol) 4233 { 4234 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4235 4236 if (hdspm->tco->wordclock != ucontrol->value.enumerated.item[0]) { 4237 hdspm->tco->wordclock = ucontrol->value.enumerated.item[0]; 4238 4239 hdspm_tco_write(hdspm); 4240 4241 return 1; 4242 } 4243 4244 return 0; 4245 } 4246 4247 4248 #define HDSPM_TCO_FRAME_RATE(xname, xindex) \ 4249 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4250 .name = xname, \ 4251 .index = xindex, \ 4252 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 4253 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 4254 .info = snd_hdspm_info_tco_frame_rate, \ 4255 .get = snd_hdspm_get_tco_frame_rate, \ 4256 .put = snd_hdspm_put_tco_frame_rate \ 4257 } 4258 4259 static int snd_hdspm_info_tco_frame_rate(struct snd_kcontrol *kcontrol, 4260 struct snd_ctl_elem_info *uinfo) 4261 { 4262 static char *texts[] = { "24 fps", "25 fps", "29.97fps", 4263 "29.97 dfps", "30 fps", "30 dfps" }; 4264 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 4265 uinfo->count = 1; 4266 uinfo->value.enumerated.items = 6; 4267 4268 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 4269 uinfo->value.enumerated.item = 4270 uinfo->value.enumerated.items - 1; 4271 4272 strcpy(uinfo->value.enumerated.name, 4273 texts[uinfo->value.enumerated.item]); 4274 4275 return 0; 4276 } 4277 4278 static int snd_hdspm_get_tco_frame_rate(struct snd_kcontrol *kcontrol, 4279 struct snd_ctl_elem_value *ucontrol) 4280 { 4281 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4282 4283 ucontrol->value.enumerated.item[0] = hdspm->tco->framerate; 4284 4285 return 0; 4286 } 4287 4288 static int snd_hdspm_put_tco_frame_rate(struct snd_kcontrol *kcontrol, 4289 struct snd_ctl_elem_value *ucontrol) 4290 { 4291 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4292 4293 if (hdspm->tco->framerate != ucontrol->value.enumerated.item[0]) { 4294 hdspm->tco->framerate = ucontrol->value.enumerated.item[0]; 4295 4296 hdspm_tco_write(hdspm); 4297 4298 return 1; 4299 } 4300 4301 return 0; 4302 } 4303 4304 4305 #define HDSPM_TCO_SYNC_SOURCE(xname, xindex) \ 4306 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4307 .name = xname, \ 4308 .index = xindex, \ 4309 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 4310 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 4311 .info = snd_hdspm_info_tco_sync_source, \ 4312 .get = snd_hdspm_get_tco_sync_source, \ 4313 .put = snd_hdspm_put_tco_sync_source \ 4314 } 4315 4316 static int snd_hdspm_info_tco_sync_source(struct snd_kcontrol *kcontrol, 4317 struct snd_ctl_elem_info *uinfo) 4318 { 4319 static char *texts[] = { "LTC", "Video", "WCK" }; 4320 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 4321 uinfo->count = 1; 4322 uinfo->value.enumerated.items = 3; 4323 4324 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 4325 uinfo->value.enumerated.item = 4326 uinfo->value.enumerated.items - 1; 4327 4328 strcpy(uinfo->value.enumerated.name, 4329 texts[uinfo->value.enumerated.item]); 4330 4331 return 0; 4332 } 4333 4334 static int snd_hdspm_get_tco_sync_source(struct snd_kcontrol *kcontrol, 4335 struct snd_ctl_elem_value *ucontrol) 4336 { 4337 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4338 4339 ucontrol->value.enumerated.item[0] = hdspm->tco->input; 4340 4341 return 0; 4342 } 4343 4344 static int snd_hdspm_put_tco_sync_source(struct snd_kcontrol *kcontrol, 4345 struct snd_ctl_elem_value *ucontrol) 4346 { 4347 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4348 4349 if (hdspm->tco->input != ucontrol->value.enumerated.item[0]) { 4350 hdspm->tco->input = ucontrol->value.enumerated.item[0]; 4351 4352 hdspm_tco_write(hdspm); 4353 4354 return 1; 4355 } 4356 4357 return 0; 4358 } 4359 4360 4361 #define HDSPM_TCO_WORD_TERM(xname, xindex) \ 4362 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4363 .name = xname, \ 4364 .index = xindex, \ 4365 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 4366 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 4367 .info = snd_hdspm_info_tco_word_term, \ 4368 .get = snd_hdspm_get_tco_word_term, \ 4369 .put = snd_hdspm_put_tco_word_term \ 4370 } 4371 4372 static int snd_hdspm_info_tco_word_term(struct snd_kcontrol *kcontrol, 4373 struct snd_ctl_elem_info *uinfo) 4374 { 4375 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 4376 uinfo->count = 1; 4377 uinfo->value.integer.min = 0; 4378 uinfo->value.integer.max = 1; 4379 4380 return 0; 4381 } 4382 4383 4384 static int snd_hdspm_get_tco_word_term(struct snd_kcontrol *kcontrol, 4385 struct snd_ctl_elem_value *ucontrol) 4386 { 4387 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4388 4389 ucontrol->value.enumerated.item[0] = hdspm->tco->term; 4390 4391 return 0; 4392 } 4393 4394 4395 static int snd_hdspm_put_tco_word_term(struct snd_kcontrol *kcontrol, 4396 struct snd_ctl_elem_value *ucontrol) 4397 { 4398 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4399 4400 if (hdspm->tco->term != ucontrol->value.enumerated.item[0]) { 4401 hdspm->tco->term = ucontrol->value.enumerated.item[0]; 4402 4403 hdspm_tco_write(hdspm); 4404 4405 return 1; 4406 } 4407 4408 return 0; 4409 } 4410 4411 4412 4413 4414 static struct snd_kcontrol_new snd_hdspm_controls_madi[] = { 4415 HDSPM_MIXER("Mixer", 0), 4416 HDSPM_INTERNAL_CLOCK("Internal Clock", 0), 4417 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0), 4418 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0), 4419 HDSPM_AUTOSYNC_REF("AutoSync Reference", 0), 4420 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), 4421 HDSPM_SYNC_CHECK("WC SyncCheck", 0), 4422 HDSPM_SYNC_CHECK("MADI SyncCheck", 1), 4423 HDSPM_SYNC_CHECK("TCO SyncCHeck", 2), 4424 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 3), 4425 HDSPM_LINE_OUT("Line Out", 0), 4426 HDSPM_TX_64("TX 64 channels mode", 0), 4427 HDSPM_C_TMS("Clear Track Marker", 0), 4428 HDSPM_SAFE_MODE("Safe Mode", 0), 4429 HDSPM_INPUT_SELECT("Input Select", 0), 4430 HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0) 4431 }; 4432 4433 4434 static struct snd_kcontrol_new snd_hdspm_controls_madiface[] = { 4435 HDSPM_MIXER("Mixer", 0), 4436 HDSPM_INTERNAL_CLOCK("Internal Clock", 0), 4437 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0), 4438 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), 4439 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0), 4440 HDSPM_SYNC_CHECK("MADI SyncCheck", 0), 4441 HDSPM_TX_64("TX 64 channels mode", 0), 4442 HDSPM_C_TMS("Clear Track Marker", 0), 4443 HDSPM_SAFE_MODE("Safe Mode", 0), 4444 HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0) 4445 }; 4446 4447 static struct snd_kcontrol_new snd_hdspm_controls_aio[] = { 4448 HDSPM_MIXER("Mixer", 0), 4449 HDSPM_INTERNAL_CLOCK("Internal Clock", 0), 4450 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0), 4451 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0), 4452 HDSPM_AUTOSYNC_REF("AutoSync Reference", 0), 4453 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), 4454 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0), 4455 HDSPM_SYNC_CHECK("WC SyncCheck", 0), 4456 HDSPM_SYNC_CHECK("AES SyncCheck", 1), 4457 HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2), 4458 HDSPM_SYNC_CHECK("ADAT SyncCheck", 3), 4459 HDSPM_SYNC_CHECK("TCO SyncCheck", 4), 4460 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 5), 4461 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0), 4462 HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1), 4463 HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2), 4464 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT Frequency", 3), 4465 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 4), 4466 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 5) 4467 4468 /* 4469 HDSPM_INPUT_SELECT("Input Select", 0), 4470 HDSPM_SPDIF_OPTICAL("SPDIF Out Optical", 0), 4471 HDSPM_PROFESSIONAL("SPDIF Out Professional", 0); 4472 HDSPM_SPDIF_IN("SPDIF In", 0); 4473 HDSPM_BREAKOUT_CABLE("Breakout Cable", 0); 4474 HDSPM_INPUT_LEVEL("Input Level", 0); 4475 HDSPM_OUTPUT_LEVEL("Output Level", 0); 4476 HDSPM_PHONES("Phones", 0); 4477 */ 4478 }; 4479 4480 static struct snd_kcontrol_new snd_hdspm_controls_raydat[] = { 4481 HDSPM_MIXER("Mixer", 0), 4482 HDSPM_INTERNAL_CLOCK("Internal Clock", 0), 4483 HDSPM_SYSTEM_CLOCK_MODE("Clock Mode", 0), 4484 HDSPM_PREF_SYNC_REF("Pref Sync Ref", 0), 4485 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), 4486 HDSPM_SYNC_CHECK("WC SyncCheck", 0), 4487 HDSPM_SYNC_CHECK("AES SyncCheck", 1), 4488 HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2), 4489 HDSPM_SYNC_CHECK("ADAT1 SyncCheck", 3), 4490 HDSPM_SYNC_CHECK("ADAT2 SyncCheck", 4), 4491 HDSPM_SYNC_CHECK("ADAT3 SyncCheck", 5), 4492 HDSPM_SYNC_CHECK("ADAT4 SyncCheck", 6), 4493 HDSPM_SYNC_CHECK("TCO SyncCheck", 7), 4494 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 8), 4495 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0), 4496 HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1), 4497 HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2), 4498 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT1 Frequency", 3), 4499 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT2 Frequency", 4), 4500 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT3 Frequency", 5), 4501 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT4 Frequency", 6), 4502 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 7), 4503 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 8) 4504 }; 4505 4506 static struct snd_kcontrol_new snd_hdspm_controls_aes32[] = { 4507 HDSPM_MIXER("Mixer", 0), 4508 HDSPM_INTERNAL_CLOCK("Internal Clock", 0), 4509 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0), 4510 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0), 4511 HDSPM_AUTOSYNC_REF("AutoSync Reference", 0), 4512 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), 4513 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0), 4514 HDSPM_SYNC_CHECK("WC Sync Check", 0), 4515 HDSPM_SYNC_CHECK("AES1 Sync Check", 1), 4516 HDSPM_SYNC_CHECK("AES2 Sync Check", 2), 4517 HDSPM_SYNC_CHECK("AES3 Sync Check", 3), 4518 HDSPM_SYNC_CHECK("AES4 Sync Check", 4), 4519 HDSPM_SYNC_CHECK("AES5 Sync Check", 5), 4520 HDSPM_SYNC_CHECK("AES6 Sync Check", 6), 4521 HDSPM_SYNC_CHECK("AES7 Sync Check", 7), 4522 HDSPM_SYNC_CHECK("AES8 Sync Check", 8), 4523 HDSPM_SYNC_CHECK("TCO Sync Check", 9), 4524 HDSPM_SYNC_CHECK("SYNC IN Sync Check", 10), 4525 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0), 4526 HDSPM_AUTOSYNC_SAMPLE_RATE("AES1 Frequency", 1), 4527 HDSPM_AUTOSYNC_SAMPLE_RATE("AES2 Frequency", 2), 4528 HDSPM_AUTOSYNC_SAMPLE_RATE("AES3 Frequency", 3), 4529 HDSPM_AUTOSYNC_SAMPLE_RATE("AES4 Frequency", 4), 4530 HDSPM_AUTOSYNC_SAMPLE_RATE("AES5 Frequency", 5), 4531 HDSPM_AUTOSYNC_SAMPLE_RATE("AES6 Frequency", 6), 4532 HDSPM_AUTOSYNC_SAMPLE_RATE("AES7 Frequency", 7), 4533 HDSPM_AUTOSYNC_SAMPLE_RATE("AES8 Frequency", 8), 4534 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 9), 4535 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 10), 4536 HDSPM_LINE_OUT("Line Out", 0), 4537 HDSPM_EMPHASIS("Emphasis", 0), 4538 HDSPM_DOLBY("Non Audio", 0), 4539 HDSPM_PROFESSIONAL("Professional", 0), 4540 HDSPM_C_TMS("Clear Track Marker", 0), 4541 HDSPM_DS_WIRE("Double Speed Wire Mode", 0), 4542 HDSPM_QS_WIRE("Quad Speed Wire Mode", 0), 4543 }; 4544 4545 4546 4547 /* Control elements for the optional TCO module */ 4548 static struct snd_kcontrol_new snd_hdspm_controls_tco[] = { 4549 HDSPM_TCO_SAMPLE_RATE("TCO Sample Rate", 0), 4550 HDSPM_TCO_PULL("TCO Pull", 0), 4551 HDSPM_TCO_WCK_CONVERSION("TCO WCK Conversion", 0), 4552 HDSPM_TCO_FRAME_RATE("TCO Frame Rate", 0), 4553 HDSPM_TCO_SYNC_SOURCE("TCO Sync Source", 0), 4554 HDSPM_TCO_WORD_TERM("TCO Word Term", 0) 4555 }; 4556 4557 4558 static struct snd_kcontrol_new snd_hdspm_playback_mixer = HDSPM_PLAYBACK_MIXER; 4559 4560 4561 static int hdspm_update_simple_mixer_controls(struct hdspm * hdspm) 4562 { 4563 int i; 4564 4565 for (i = hdspm->ds_out_channels; i < hdspm->ss_out_channels; ++i) { 4566 if (hdspm->system_sample_rate > 48000) { 4567 hdspm->playback_mixer_ctls[i]->vd[0].access = 4568 SNDRV_CTL_ELEM_ACCESS_INACTIVE | 4569 SNDRV_CTL_ELEM_ACCESS_READ | 4570 SNDRV_CTL_ELEM_ACCESS_VOLATILE; 4571 } else { 4572 hdspm->playback_mixer_ctls[i]->vd[0].access = 4573 SNDRV_CTL_ELEM_ACCESS_READWRITE | 4574 SNDRV_CTL_ELEM_ACCESS_VOLATILE; 4575 } 4576 snd_ctl_notify(hdspm->card, SNDRV_CTL_EVENT_MASK_VALUE | 4577 SNDRV_CTL_EVENT_MASK_INFO, 4578 &hdspm->playback_mixer_ctls[i]->id); 4579 } 4580 4581 return 0; 4582 } 4583 4584 4585 static int snd_hdspm_create_controls(struct snd_card *card, 4586 struct hdspm *hdspm) 4587 { 4588 unsigned int idx, limit; 4589 int err; 4590 struct snd_kcontrol *kctl; 4591 struct snd_kcontrol_new *list = NULL; 4592 4593 switch (hdspm->io_type) { 4594 case MADI: 4595 list = snd_hdspm_controls_madi; 4596 limit = ARRAY_SIZE(snd_hdspm_controls_madi); 4597 break; 4598 case MADIface: 4599 list = snd_hdspm_controls_madiface; 4600 limit = ARRAY_SIZE(snd_hdspm_controls_madiface); 4601 break; 4602 case AIO: 4603 list = snd_hdspm_controls_aio; 4604 limit = ARRAY_SIZE(snd_hdspm_controls_aio); 4605 break; 4606 case RayDAT: 4607 list = snd_hdspm_controls_raydat; 4608 limit = ARRAY_SIZE(snd_hdspm_controls_raydat); 4609 break; 4610 case AES32: 4611 list = snd_hdspm_controls_aes32; 4612 limit = ARRAY_SIZE(snd_hdspm_controls_aes32); 4613 break; 4614 } 4615 4616 if (NULL != list) { 4617 for (idx = 0; idx < limit; idx++) { 4618 err = snd_ctl_add(card, 4619 snd_ctl_new1(&list[idx], hdspm)); 4620 if (err < 0) 4621 return err; 4622 } 4623 } 4624 4625 4626 /* create simple 1:1 playback mixer controls */ 4627 snd_hdspm_playback_mixer.name = "Chn"; 4628 if (hdspm->system_sample_rate >= 128000) { 4629 limit = hdspm->qs_out_channels; 4630 } else if (hdspm->system_sample_rate >= 64000) { 4631 limit = hdspm->ds_out_channels; 4632 } else { 4633 limit = hdspm->ss_out_channels; 4634 } 4635 for (idx = 0; idx < limit; ++idx) { 4636 snd_hdspm_playback_mixer.index = idx + 1; 4637 kctl = snd_ctl_new1(&snd_hdspm_playback_mixer, hdspm); 4638 err = snd_ctl_add(card, kctl); 4639 if (err < 0) 4640 return err; 4641 hdspm->playback_mixer_ctls[idx] = kctl; 4642 } 4643 4644 4645 if (hdspm->tco) { 4646 /* add tco control elements */ 4647 list = snd_hdspm_controls_tco; 4648 limit = ARRAY_SIZE(snd_hdspm_controls_tco); 4649 for (idx = 0; idx < limit; idx++) { 4650 err = snd_ctl_add(card, 4651 snd_ctl_new1(&list[idx], hdspm)); 4652 if (err < 0) 4653 return err; 4654 } 4655 } 4656 4657 return 0; 4658 } 4659 4660 /*------------------------------------------------------------ 4661 /proc interface 4662 ------------------------------------------------------------*/ 4663 4664 static void 4665 snd_hdspm_proc_read_madi(struct snd_info_entry * entry, 4666 struct snd_info_buffer *buffer) 4667 { 4668 struct hdspm *hdspm = entry->private_data; 4669 unsigned int status, status2, control, freq; 4670 4671 char *pref_sync_ref; 4672 char *autosync_ref; 4673 char *system_clock_mode; 4674 char *insel; 4675 int x, x2; 4676 4677 /* TCO stuff */ 4678 int a, ltc, frames, seconds, minutes, hours; 4679 unsigned int period; 4680 u64 freq_const = 0; 4681 u32 rate; 4682 4683 status = hdspm_read(hdspm, HDSPM_statusRegister); 4684 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 4685 control = hdspm->control_register; 4686 freq = hdspm_read(hdspm, HDSPM_timecodeRegister); 4687 4688 snd_iprintf(buffer, "%s (Card #%d) Rev.%x Status2first3bits: %x\n", 4689 hdspm->card_name, hdspm->card->number + 1, 4690 hdspm->firmware_rev, 4691 (status2 & HDSPM_version0) | 4692 (status2 & HDSPM_version1) | (status2 & 4693 HDSPM_version2)); 4694 4695 snd_iprintf(buffer, "HW Serial: 0x%06x%06x\n", 4696 (hdspm_read(hdspm, HDSPM_midiStatusIn1)>>8) & 0xFFFFFF, 4697 (hdspm_read(hdspm, HDSPM_midiStatusIn0)>>8) & 0xFFFFFF); 4698 4699 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n", 4700 hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase); 4701 4702 snd_iprintf(buffer, "--- System ---\n"); 4703 4704 snd_iprintf(buffer, 4705 "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n", 4706 status & HDSPM_audioIRQPending, 4707 (status & HDSPM_midi0IRQPending) ? 1 : 0, 4708 (status & HDSPM_midi1IRQPending) ? 1 : 0, 4709 hdspm->irq_count); 4710 snd_iprintf(buffer, 4711 "HW pointer: id = %d, rawptr = %d (%d->%d) " 4712 "estimated= %ld (bytes)\n", 4713 ((status & HDSPM_BufferID) ? 1 : 0), 4714 (status & HDSPM_BufferPositionMask), 4715 (status & HDSPM_BufferPositionMask) % 4716 (2 * (int)hdspm->period_bytes), 4717 ((status & HDSPM_BufferPositionMask) - 64) % 4718 (2 * (int)hdspm->period_bytes), 4719 (long) hdspm_hw_pointer(hdspm) * 4); 4720 4721 snd_iprintf(buffer, 4722 "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n", 4723 hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF, 4724 hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF, 4725 hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF, 4726 hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF); 4727 snd_iprintf(buffer, 4728 "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n", 4729 hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF, 4730 hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF); 4731 snd_iprintf(buffer, 4732 "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, " 4733 "status2=0x%x\n", 4734 hdspm->control_register, hdspm->control2_register, 4735 status, status2); 4736 if (status & HDSPM_tco_detect) { 4737 snd_iprintf(buffer, "TCO module detected.\n"); 4738 a = hdspm_read(hdspm, HDSPM_RD_TCO+4); 4739 if (a & HDSPM_TCO1_LTC_Input_valid) { 4740 snd_iprintf(buffer, " LTC valid, "); 4741 switch (a & (HDSPM_TCO1_LTC_Format_LSB | 4742 HDSPM_TCO1_LTC_Format_MSB)) { 4743 case 0: 4744 snd_iprintf(buffer, "24 fps, "); 4745 break; 4746 case HDSPM_TCO1_LTC_Format_LSB: 4747 snd_iprintf(buffer, "25 fps, "); 4748 break; 4749 case HDSPM_TCO1_LTC_Format_MSB: 4750 snd_iprintf(buffer, "29.97 fps, "); 4751 break; 4752 default: 4753 snd_iprintf(buffer, "30 fps, "); 4754 break; 4755 } 4756 if (a & HDSPM_TCO1_set_drop_frame_flag) { 4757 snd_iprintf(buffer, "drop frame\n"); 4758 } else { 4759 snd_iprintf(buffer, "full frame\n"); 4760 } 4761 } else { 4762 snd_iprintf(buffer, " no LTC\n"); 4763 } 4764 if (a & HDSPM_TCO1_Video_Input_Format_NTSC) { 4765 snd_iprintf(buffer, " Video: NTSC\n"); 4766 } else if (a & HDSPM_TCO1_Video_Input_Format_PAL) { 4767 snd_iprintf(buffer, " Video: PAL\n"); 4768 } else { 4769 snd_iprintf(buffer, " No video\n"); 4770 } 4771 if (a & HDSPM_TCO1_TCO_lock) { 4772 snd_iprintf(buffer, " Sync: lock\n"); 4773 } else { 4774 snd_iprintf(buffer, " Sync: no lock\n"); 4775 } 4776 4777 switch (hdspm->io_type) { 4778 case MADI: 4779 case AES32: 4780 freq_const = 110069313433624ULL; 4781 break; 4782 case RayDAT: 4783 case AIO: 4784 freq_const = 104857600000000ULL; 4785 break; 4786 case MADIface: 4787 break; /* no TCO possible */ 4788 } 4789 4790 period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ); 4791 snd_iprintf(buffer, " period: %u\n", period); 4792 4793 4794 /* rate = freq_const/period; */ 4795 rate = div_u64(freq_const, period); 4796 4797 if (control & HDSPM_QuadSpeed) { 4798 rate *= 4; 4799 } else if (control & HDSPM_DoubleSpeed) { 4800 rate *= 2; 4801 } 4802 4803 snd_iprintf(buffer, " Frequency: %u Hz\n", 4804 (unsigned int) rate); 4805 4806 ltc = hdspm_read(hdspm, HDSPM_RD_TCO); 4807 frames = ltc & 0xF; 4808 ltc >>= 4; 4809 frames += (ltc & 0x3) * 10; 4810 ltc >>= 4; 4811 seconds = ltc & 0xF; 4812 ltc >>= 4; 4813 seconds += (ltc & 0x7) * 10; 4814 ltc >>= 4; 4815 minutes = ltc & 0xF; 4816 ltc >>= 4; 4817 minutes += (ltc & 0x7) * 10; 4818 ltc >>= 4; 4819 hours = ltc & 0xF; 4820 ltc >>= 4; 4821 hours += (ltc & 0x3) * 10; 4822 snd_iprintf(buffer, 4823 " LTC In: %02d:%02d:%02d:%02d\n", 4824 hours, minutes, seconds, frames); 4825 4826 } else { 4827 snd_iprintf(buffer, "No TCO module detected.\n"); 4828 } 4829 4830 snd_iprintf(buffer, "--- Settings ---\n"); 4831 4832 x = hdspm_get_latency(hdspm); 4833 4834 snd_iprintf(buffer, 4835 "Size (Latency): %d samples (2 periods of %lu bytes)\n", 4836 x, (unsigned long) hdspm->period_bytes); 4837 4838 snd_iprintf(buffer, "Line out: %s\n", 4839 (hdspm->control_register & HDSPM_LineOut) ? "on " : "off"); 4840 4841 switch (hdspm->control_register & HDSPM_InputMask) { 4842 case HDSPM_InputOptical: 4843 insel = "Optical"; 4844 break; 4845 case HDSPM_InputCoaxial: 4846 insel = "Coaxial"; 4847 break; 4848 default: 4849 insel = "Unkown"; 4850 } 4851 4852 snd_iprintf(buffer, 4853 "ClearTrackMarker = %s, Transmit in %s Channel Mode, " 4854 "Auto Input %s\n", 4855 (hdspm->control_register & HDSPM_clr_tms) ? "on" : "off", 4856 (hdspm->control_register & HDSPM_TX_64ch) ? "64" : "56", 4857 (hdspm->control_register & HDSPM_AutoInp) ? "on" : "off"); 4858 4859 4860 if (!(hdspm->control_register & HDSPM_ClockModeMaster)) 4861 system_clock_mode = "AutoSync"; 4862 else 4863 system_clock_mode = "Master"; 4864 snd_iprintf(buffer, "AutoSync Reference: %s\n", system_clock_mode); 4865 4866 switch (hdspm_pref_sync_ref(hdspm)) { 4867 case HDSPM_SYNC_FROM_WORD: 4868 pref_sync_ref = "Word Clock"; 4869 break; 4870 case HDSPM_SYNC_FROM_MADI: 4871 pref_sync_ref = "MADI Sync"; 4872 break; 4873 case HDSPM_SYNC_FROM_TCO: 4874 pref_sync_ref = "TCO"; 4875 break; 4876 case HDSPM_SYNC_FROM_SYNC_IN: 4877 pref_sync_ref = "Sync In"; 4878 break; 4879 default: 4880 pref_sync_ref = "XXXX Clock"; 4881 break; 4882 } 4883 snd_iprintf(buffer, "Preferred Sync Reference: %s\n", 4884 pref_sync_ref); 4885 4886 snd_iprintf(buffer, "System Clock Frequency: %d\n", 4887 hdspm->system_sample_rate); 4888 4889 4890 snd_iprintf(buffer, "--- Status:\n"); 4891 4892 x = status & HDSPM_madiSync; 4893 x2 = status2 & HDSPM_wcSync; 4894 4895 snd_iprintf(buffer, "Inputs MADI=%s, WordClock=%s\n", 4896 (status & HDSPM_madiLock) ? (x ? "Sync" : "Lock") : 4897 "NoLock", 4898 (status2 & HDSPM_wcLock) ? (x2 ? "Sync" : "Lock") : 4899 "NoLock"); 4900 4901 switch (hdspm_autosync_ref(hdspm)) { 4902 case HDSPM_AUTOSYNC_FROM_SYNC_IN: 4903 autosync_ref = "Sync In"; 4904 break; 4905 case HDSPM_AUTOSYNC_FROM_TCO: 4906 autosync_ref = "TCO"; 4907 break; 4908 case HDSPM_AUTOSYNC_FROM_WORD: 4909 autosync_ref = "Word Clock"; 4910 break; 4911 case HDSPM_AUTOSYNC_FROM_MADI: 4912 autosync_ref = "MADI Sync"; 4913 break; 4914 case HDSPM_AUTOSYNC_FROM_NONE: 4915 autosync_ref = "Input not valid"; 4916 break; 4917 default: 4918 autosync_ref = "---"; 4919 break; 4920 } 4921 snd_iprintf(buffer, 4922 "AutoSync: Reference= %s, Freq=%d (MADI = %d, Word = %d)\n", 4923 autosync_ref, hdspm_external_sample_rate(hdspm), 4924 (status & HDSPM_madiFreqMask) >> 22, 4925 (status2 & HDSPM_wcFreqMask) >> 5); 4926 4927 snd_iprintf(buffer, "Input: %s, Mode=%s\n", 4928 (status & HDSPM_AB_int) ? "Coax" : "Optical", 4929 (status & HDSPM_RX_64ch) ? "64 channels" : 4930 "56 channels"); 4931 4932 snd_iprintf(buffer, "\n"); 4933 } 4934 4935 static void 4936 snd_hdspm_proc_read_aes32(struct snd_info_entry * entry, 4937 struct snd_info_buffer *buffer) 4938 { 4939 struct hdspm *hdspm = entry->private_data; 4940 unsigned int status; 4941 unsigned int status2; 4942 unsigned int timecode; 4943 int pref_syncref; 4944 char *autosync_ref; 4945 int x; 4946 4947 status = hdspm_read(hdspm, HDSPM_statusRegister); 4948 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 4949 timecode = hdspm_read(hdspm, HDSPM_timecodeRegister); 4950 4951 snd_iprintf(buffer, "%s (Card #%d) Rev.%x\n", 4952 hdspm->card_name, hdspm->card->number + 1, 4953 hdspm->firmware_rev); 4954 4955 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n", 4956 hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase); 4957 4958 snd_iprintf(buffer, "--- System ---\n"); 4959 4960 snd_iprintf(buffer, 4961 "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n", 4962 status & HDSPM_audioIRQPending, 4963 (status & HDSPM_midi0IRQPending) ? 1 : 0, 4964 (status & HDSPM_midi1IRQPending) ? 1 : 0, 4965 hdspm->irq_count); 4966 snd_iprintf(buffer, 4967 "HW pointer: id = %d, rawptr = %d (%d->%d) " 4968 "estimated= %ld (bytes)\n", 4969 ((status & HDSPM_BufferID) ? 1 : 0), 4970 (status & HDSPM_BufferPositionMask), 4971 (status & HDSPM_BufferPositionMask) % 4972 (2 * (int)hdspm->period_bytes), 4973 ((status & HDSPM_BufferPositionMask) - 64) % 4974 (2 * (int)hdspm->period_bytes), 4975 (long) hdspm_hw_pointer(hdspm) * 4); 4976 4977 snd_iprintf(buffer, 4978 "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n", 4979 hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF, 4980 hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF, 4981 hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF, 4982 hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF); 4983 snd_iprintf(buffer, 4984 "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n", 4985 hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF, 4986 hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF); 4987 snd_iprintf(buffer, 4988 "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, " 4989 "status2=0x%x\n", 4990 hdspm->control_register, hdspm->control2_register, 4991 status, status2); 4992 4993 snd_iprintf(buffer, "--- Settings ---\n"); 4994 4995 x = hdspm_get_latency(hdspm); 4996 4997 snd_iprintf(buffer, 4998 "Size (Latency): %d samples (2 periods of %lu bytes)\n", 4999 x, (unsigned long) hdspm->period_bytes); 5000 5001 snd_iprintf(buffer, "Line out: %s\n", 5002 (hdspm-> 5003 control_register & HDSPM_LineOut) ? "on " : "off"); 5004 5005 snd_iprintf(buffer, 5006 "ClearTrackMarker %s, Emphasis %s, Dolby %s\n", 5007 (hdspm-> 5008 control_register & HDSPM_clr_tms) ? "on" : "off", 5009 (hdspm-> 5010 control_register & HDSPM_Emphasis) ? "on" : "off", 5011 (hdspm-> 5012 control_register & HDSPM_Dolby) ? "on" : "off"); 5013 5014 5015 pref_syncref = hdspm_pref_sync_ref(hdspm); 5016 if (pref_syncref == 0) 5017 snd_iprintf(buffer, "Preferred Sync Reference: Word Clock\n"); 5018 else 5019 snd_iprintf(buffer, "Preferred Sync Reference: AES%d\n", 5020 pref_syncref); 5021 5022 snd_iprintf(buffer, "System Clock Frequency: %d\n", 5023 hdspm->system_sample_rate); 5024 5025 snd_iprintf(buffer, "Double speed: %s\n", 5026 hdspm->control_register & HDSPM_DS_DoubleWire? 5027 "Double wire" : "Single wire"); 5028 snd_iprintf(buffer, "Quad speed: %s\n", 5029 hdspm->control_register & HDSPM_QS_DoubleWire? 5030 "Double wire" : 5031 hdspm->control_register & HDSPM_QS_QuadWire? 5032 "Quad wire" : "Single wire"); 5033 5034 snd_iprintf(buffer, "--- Status:\n"); 5035 5036 snd_iprintf(buffer, "Word: %s Frequency: %d\n", 5037 (status & HDSPM_AES32_wcLock) ? "Sync " : "No Lock", 5038 HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF)); 5039 5040 for (x = 0; x < 8; x++) { 5041 snd_iprintf(buffer, "AES%d: %s Frequency: %d\n", 5042 x+1, 5043 (status2 & (HDSPM_LockAES >> x)) ? 5044 "Sync " : "No Lock", 5045 HDSPM_bit2freq((timecode >> (4*x)) & 0xF)); 5046 } 5047 5048 switch (hdspm_autosync_ref(hdspm)) { 5049 case HDSPM_AES32_AUTOSYNC_FROM_NONE: 5050 autosync_ref = "None"; break; 5051 case HDSPM_AES32_AUTOSYNC_FROM_WORD: 5052 autosync_ref = "Word Clock"; break; 5053 case HDSPM_AES32_AUTOSYNC_FROM_AES1: 5054 autosync_ref = "AES1"; break; 5055 case HDSPM_AES32_AUTOSYNC_FROM_AES2: 5056 autosync_ref = "AES2"; break; 5057 case HDSPM_AES32_AUTOSYNC_FROM_AES3: 5058 autosync_ref = "AES3"; break; 5059 case HDSPM_AES32_AUTOSYNC_FROM_AES4: 5060 autosync_ref = "AES4"; break; 5061 case HDSPM_AES32_AUTOSYNC_FROM_AES5: 5062 autosync_ref = "AES5"; break; 5063 case HDSPM_AES32_AUTOSYNC_FROM_AES6: 5064 autosync_ref = "AES6"; break; 5065 case HDSPM_AES32_AUTOSYNC_FROM_AES7: 5066 autosync_ref = "AES7"; break; 5067 case HDSPM_AES32_AUTOSYNC_FROM_AES8: 5068 autosync_ref = "AES8"; break; 5069 default: 5070 autosync_ref = "---"; break; 5071 } 5072 snd_iprintf(buffer, "AutoSync ref = %s\n", autosync_ref); 5073 5074 snd_iprintf(buffer, "\n"); 5075 } 5076 5077 static void 5078 snd_hdspm_proc_read_raydat(struct snd_info_entry *entry, 5079 struct snd_info_buffer *buffer) 5080 { 5081 struct hdspm *hdspm = entry->private_data; 5082 unsigned int status1, status2, status3, control, i; 5083 unsigned int lock, sync; 5084 5085 status1 = hdspm_read(hdspm, HDSPM_RD_STATUS_1); /* s1 */ 5086 status2 = hdspm_read(hdspm, HDSPM_RD_STATUS_2); /* freq */ 5087 status3 = hdspm_read(hdspm, HDSPM_RD_STATUS_3); /* s2 */ 5088 5089 control = hdspm->control_register; 5090 5091 snd_iprintf(buffer, "STATUS1: 0x%08x\n", status1); 5092 snd_iprintf(buffer, "STATUS2: 0x%08x\n", status2); 5093 snd_iprintf(buffer, "STATUS3: 0x%08x\n", status3); 5094 5095 5096 snd_iprintf(buffer, "\n*** CLOCK MODE\n\n"); 5097 5098 snd_iprintf(buffer, "Clock mode : %s\n", 5099 (hdspm_system_clock_mode(hdspm) == 0) ? "master" : "slave"); 5100 snd_iprintf(buffer, "System frequency: %d Hz\n", 5101 hdspm_get_system_sample_rate(hdspm)); 5102 5103 snd_iprintf(buffer, "\n*** INPUT STATUS\n\n"); 5104 5105 lock = 0x1; 5106 sync = 0x100; 5107 5108 for (i = 0; i < 8; i++) { 5109 snd_iprintf(buffer, "s1_input %d: Lock %d, Sync %d, Freq %s\n", 5110 i, 5111 (status1 & lock) ? 1 : 0, 5112 (status1 & sync) ? 1 : 0, 5113 texts_freq[(status2 >> (i * 4)) & 0xF]); 5114 5115 lock = lock<<1; 5116 sync = sync<<1; 5117 } 5118 5119 snd_iprintf(buffer, "WC input: Lock %d, Sync %d, Freq %s\n", 5120 (status1 & 0x1000000) ? 1 : 0, 5121 (status1 & 0x2000000) ? 1 : 0, 5122 texts_freq[(status1 >> 16) & 0xF]); 5123 5124 snd_iprintf(buffer, "TCO input: Lock %d, Sync %d, Freq %s\n", 5125 (status1 & 0x4000000) ? 1 : 0, 5126 (status1 & 0x8000000) ? 1 : 0, 5127 texts_freq[(status1 >> 20) & 0xF]); 5128 5129 snd_iprintf(buffer, "SYNC IN: Lock %d, Sync %d, Freq %s\n", 5130 (status3 & 0x400) ? 1 : 0, 5131 (status3 & 0x800) ? 1 : 0, 5132 texts_freq[(status2 >> 12) & 0xF]); 5133 5134 } 5135 5136 #ifdef CONFIG_SND_DEBUG 5137 static void 5138 snd_hdspm_proc_read_debug(struct snd_info_entry *entry, 5139 struct snd_info_buffer *buffer) 5140 { 5141 struct hdspm *hdspm = entry->private_data; 5142 5143 int j,i; 5144 5145 for (i = 0; i < 256 /* 1024*64 */; i += j) { 5146 snd_iprintf(buffer, "0x%08X: ", i); 5147 for (j = 0; j < 16; j += 4) 5148 snd_iprintf(buffer, "%08X ", hdspm_read(hdspm, i + j)); 5149 snd_iprintf(buffer, "\n"); 5150 } 5151 } 5152 #endif 5153 5154 5155 static void snd_hdspm_proc_ports_in(struct snd_info_entry *entry, 5156 struct snd_info_buffer *buffer) 5157 { 5158 struct hdspm *hdspm = entry->private_data; 5159 int i; 5160 5161 snd_iprintf(buffer, "# generated by hdspm\n"); 5162 5163 for (i = 0; i < hdspm->max_channels_in; i++) { 5164 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_in[i]); 5165 } 5166 } 5167 5168 static void snd_hdspm_proc_ports_out(struct snd_info_entry *entry, 5169 struct snd_info_buffer *buffer) 5170 { 5171 struct hdspm *hdspm = entry->private_data; 5172 int i; 5173 5174 snd_iprintf(buffer, "# generated by hdspm\n"); 5175 5176 for (i = 0; i < hdspm->max_channels_out; i++) { 5177 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_out[i]); 5178 } 5179 } 5180 5181 5182 static void __devinit snd_hdspm_proc_init(struct hdspm *hdspm) 5183 { 5184 struct snd_info_entry *entry; 5185 5186 if (!snd_card_proc_new(hdspm->card, "hdspm", &entry)) { 5187 switch (hdspm->io_type) { 5188 case AES32: 5189 snd_info_set_text_ops(entry, hdspm, 5190 snd_hdspm_proc_read_aes32); 5191 break; 5192 case MADI: 5193 snd_info_set_text_ops(entry, hdspm, 5194 snd_hdspm_proc_read_madi); 5195 break; 5196 case MADIface: 5197 /* snd_info_set_text_ops(entry, hdspm, 5198 snd_hdspm_proc_read_madiface); */ 5199 break; 5200 case RayDAT: 5201 snd_info_set_text_ops(entry, hdspm, 5202 snd_hdspm_proc_read_raydat); 5203 break; 5204 case AIO: 5205 break; 5206 } 5207 } 5208 5209 if (!snd_card_proc_new(hdspm->card, "ports.in", &entry)) { 5210 snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_in); 5211 } 5212 5213 if (!snd_card_proc_new(hdspm->card, "ports.out", &entry)) { 5214 snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_out); 5215 } 5216 5217 #ifdef CONFIG_SND_DEBUG 5218 /* debug file to read all hdspm registers */ 5219 if (!snd_card_proc_new(hdspm->card, "debug", &entry)) 5220 snd_info_set_text_ops(entry, hdspm, 5221 snd_hdspm_proc_read_debug); 5222 #endif 5223 } 5224 5225 /*------------------------------------------------------------ 5226 hdspm intitialize 5227 ------------------------------------------------------------*/ 5228 5229 static int snd_hdspm_set_defaults(struct hdspm * hdspm) 5230 { 5231 /* ASSUMPTION: hdspm->lock is either held, or there is no need to 5232 hold it (e.g. during module initialization). 5233 */ 5234 5235 /* set defaults: */ 5236 5237 hdspm->settings_register = 0; 5238 5239 switch (hdspm->io_type) { 5240 case MADI: 5241 case MADIface: 5242 hdspm->control_register = 5243 0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000; 5244 break; 5245 5246 case RayDAT: 5247 case AIO: 5248 hdspm->settings_register = 0x1 + 0x1000; 5249 /* Magic values are: LAT_0, LAT_2, Master, freq1, tx64ch, inp_0, 5250 * line_out */ 5251 hdspm->control_register = 5252 0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000; 5253 break; 5254 5255 case AES32: 5256 hdspm->control_register = 5257 HDSPM_ClockModeMaster | /* Master Cloack Mode on */ 5258 hdspm_encode_latency(7) | /* latency max=8192samples */ 5259 HDSPM_SyncRef0 | /* AES1 is syncclock */ 5260 HDSPM_LineOut | /* Analog output in */ 5261 HDSPM_Professional; /* Professional mode */ 5262 break; 5263 } 5264 5265 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 5266 5267 if (AES32 == hdspm->io_type) { 5268 /* No control2 register for AES32 */ 5269 #ifdef SNDRV_BIG_ENDIAN 5270 hdspm->control2_register = HDSPM_BIGENDIAN_MODE; 5271 #else 5272 hdspm->control2_register = 0; 5273 #endif 5274 5275 hdspm_write(hdspm, HDSPM_control2Reg, hdspm->control2_register); 5276 } 5277 hdspm_compute_period_size(hdspm); 5278 5279 /* silence everything */ 5280 5281 all_in_all_mixer(hdspm, 0 * UNITY_GAIN); 5282 5283 if (hdspm->io_type == AIO || hdspm->io_type == RayDAT) { 5284 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register); 5285 } 5286 5287 /* set a default rate so that the channel map is set up. */ 5288 hdspm_set_rate(hdspm, 48000, 1); 5289 5290 return 0; 5291 } 5292 5293 5294 /*------------------------------------------------------------ 5295 interrupt 5296 ------------------------------------------------------------*/ 5297 5298 static irqreturn_t snd_hdspm_interrupt(int irq, void *dev_id) 5299 { 5300 struct hdspm *hdspm = (struct hdspm *) dev_id; 5301 unsigned int status; 5302 int i, audio, midi, schedule = 0; 5303 /* cycles_t now; */ 5304 5305 status = hdspm_read(hdspm, HDSPM_statusRegister); 5306 5307 audio = status & HDSPM_audioIRQPending; 5308 midi = status & (HDSPM_midi0IRQPending | HDSPM_midi1IRQPending | 5309 HDSPM_midi2IRQPending | HDSPM_midi3IRQPending); 5310 5311 /* now = get_cycles(); */ 5312 /** 5313 * LAT_2..LAT_0 period counter (win) counter (mac) 5314 * 6 4096 ~256053425 ~514672358 5315 * 5 2048 ~128024983 ~257373821 5316 * 4 1024 ~64023706 ~128718089 5317 * 3 512 ~32005945 ~64385999 5318 * 2 256 ~16003039 ~32260176 5319 * 1 128 ~7998738 ~16194507 5320 * 0 64 ~3998231 ~8191558 5321 **/ 5322 /* 5323 snd_printk(KERN_INFO "snd_hdspm_interrupt %llu @ %llx\n", 5324 now-hdspm->last_interrupt, status & 0xFFC0); 5325 hdspm->last_interrupt = now; 5326 */ 5327 5328 if (!audio && !midi) 5329 return IRQ_NONE; 5330 5331 hdspm_write(hdspm, HDSPM_interruptConfirmation, 0); 5332 hdspm->irq_count++; 5333 5334 5335 if (audio) { 5336 if (hdspm->capture_substream) 5337 snd_pcm_period_elapsed(hdspm->capture_substream); 5338 5339 if (hdspm->playback_substream) 5340 snd_pcm_period_elapsed(hdspm->playback_substream); 5341 } 5342 5343 if (midi) { 5344 i = 0; 5345 while (i < hdspm->midiPorts) { 5346 if ((hdspm_read(hdspm, 5347 hdspm->midi[i].statusIn) & 0xff) && 5348 (status & hdspm->midi[i].irq)) { 5349 /* we disable interrupts for this input until 5350 * processing is done 5351 */ 5352 hdspm->control_register &= ~hdspm->midi[i].ie; 5353 hdspm_write(hdspm, HDSPM_controlRegister, 5354 hdspm->control_register); 5355 hdspm->midi[i].pending = 1; 5356 schedule = 1; 5357 } 5358 5359 i++; 5360 } 5361 5362 if (schedule) 5363 tasklet_hi_schedule(&hdspm->midi_tasklet); 5364 } 5365 5366 return IRQ_HANDLED; 5367 } 5368 5369 /*------------------------------------------------------------ 5370 pcm interface 5371 ------------------------------------------------------------*/ 5372 5373 5374 static snd_pcm_uframes_t snd_hdspm_hw_pointer(struct snd_pcm_substream 5375 *substream) 5376 { 5377 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5378 return hdspm_hw_pointer(hdspm); 5379 } 5380 5381 5382 static int snd_hdspm_reset(struct snd_pcm_substream *substream) 5383 { 5384 struct snd_pcm_runtime *runtime = substream->runtime; 5385 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5386 struct snd_pcm_substream *other; 5387 5388 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 5389 other = hdspm->capture_substream; 5390 else 5391 other = hdspm->playback_substream; 5392 5393 if (hdspm->running) 5394 runtime->status->hw_ptr = hdspm_hw_pointer(hdspm); 5395 else 5396 runtime->status->hw_ptr = 0; 5397 if (other) { 5398 struct snd_pcm_substream *s; 5399 struct snd_pcm_runtime *oruntime = other->runtime; 5400 snd_pcm_group_for_each_entry(s, substream) { 5401 if (s == other) { 5402 oruntime->status->hw_ptr = 5403 runtime->status->hw_ptr; 5404 break; 5405 } 5406 } 5407 } 5408 return 0; 5409 } 5410 5411 static int snd_hdspm_hw_params(struct snd_pcm_substream *substream, 5412 struct snd_pcm_hw_params *params) 5413 { 5414 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5415 int err; 5416 int i; 5417 pid_t this_pid; 5418 pid_t other_pid; 5419 5420 spin_lock_irq(&hdspm->lock); 5421 5422 if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) { 5423 this_pid = hdspm->playback_pid; 5424 other_pid = hdspm->capture_pid; 5425 } else { 5426 this_pid = hdspm->capture_pid; 5427 other_pid = hdspm->playback_pid; 5428 } 5429 5430 if (other_pid > 0 && this_pid != other_pid) { 5431 5432 /* The other stream is open, and not by the same 5433 task as this one. Make sure that the parameters 5434 that matter are the same. 5435 */ 5436 5437 if (params_rate(params) != hdspm->system_sample_rate) { 5438 spin_unlock_irq(&hdspm->lock); 5439 _snd_pcm_hw_param_setempty(params, 5440 SNDRV_PCM_HW_PARAM_RATE); 5441 return -EBUSY; 5442 } 5443 5444 if (params_period_size(params) != hdspm->period_bytes / 4) { 5445 spin_unlock_irq(&hdspm->lock); 5446 _snd_pcm_hw_param_setempty(params, 5447 SNDRV_PCM_HW_PARAM_PERIOD_SIZE); 5448 return -EBUSY; 5449 } 5450 5451 } 5452 /* We're fine. */ 5453 spin_unlock_irq(&hdspm->lock); 5454 5455 /* how to make sure that the rate matches an externally-set one ? */ 5456 5457 spin_lock_irq(&hdspm->lock); 5458 err = hdspm_set_rate(hdspm, params_rate(params), 0); 5459 if (err < 0) { 5460 snd_printk(KERN_INFO "err on hdspm_set_rate: %d\n", err); 5461 spin_unlock_irq(&hdspm->lock); 5462 _snd_pcm_hw_param_setempty(params, 5463 SNDRV_PCM_HW_PARAM_RATE); 5464 return err; 5465 } 5466 spin_unlock_irq(&hdspm->lock); 5467 5468 err = hdspm_set_interrupt_interval(hdspm, 5469 params_period_size(params)); 5470 if (err < 0) { 5471 snd_printk(KERN_INFO "err on hdspm_set_interrupt_interval: %d\n", err); 5472 _snd_pcm_hw_param_setempty(params, 5473 SNDRV_PCM_HW_PARAM_PERIOD_SIZE); 5474 return err; 5475 } 5476 5477 /* Memory allocation, takashi's method, dont know if we should 5478 * spinlock 5479 */ 5480 /* malloc all buffer even if not enabled to get sure */ 5481 /* Update for MADI rev 204: we need to allocate for all channels, 5482 * otherwise it doesn't work at 96kHz */ 5483 5484 err = 5485 snd_pcm_lib_malloc_pages(substream, HDSPM_DMA_AREA_BYTES); 5486 if (err < 0) { 5487 snd_printk(KERN_INFO "err on snd_pcm_lib_malloc_pages: %d\n", err); 5488 return err; 5489 } 5490 5491 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 5492 5493 hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferOut, 5494 params_channels(params)); 5495 5496 for (i = 0; i < params_channels(params); ++i) 5497 snd_hdspm_enable_out(hdspm, i, 1); 5498 5499 hdspm->playback_buffer = 5500 (unsigned char *) substream->runtime->dma_area; 5501 snd_printdd("Allocated sample buffer for playback at %p\n", 5502 hdspm->playback_buffer); 5503 } else { 5504 hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferIn, 5505 params_channels(params)); 5506 5507 for (i = 0; i < params_channels(params); ++i) 5508 snd_hdspm_enable_in(hdspm, i, 1); 5509 5510 hdspm->capture_buffer = 5511 (unsigned char *) substream->runtime->dma_area; 5512 snd_printdd("Allocated sample buffer for capture at %p\n", 5513 hdspm->capture_buffer); 5514 } 5515 5516 /* 5517 snd_printdd("Allocated sample buffer for %s at 0x%08X\n", 5518 substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 5519 "playback" : "capture", 5520 snd_pcm_sgbuf_get_addr(substream, 0)); 5521 */ 5522 /* 5523 snd_printdd("set_hwparams: %s %d Hz, %d channels, bs = %d\n", 5524 substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 5525 "playback" : "capture", 5526 params_rate(params), params_channels(params), 5527 params_buffer_size(params)); 5528 */ 5529 5530 5531 /* Switch to native float format if requested */ 5532 if (SNDRV_PCM_FORMAT_FLOAT_LE == params_format(params)) { 5533 if (!(hdspm->control_register & HDSPe_FLOAT_FORMAT)) 5534 snd_printk(KERN_INFO "hdspm: Switching to native 32bit LE float format.\n"); 5535 5536 hdspm->control_register |= HDSPe_FLOAT_FORMAT; 5537 } else if (SNDRV_PCM_FORMAT_S32_LE == params_format(params)) { 5538 if (hdspm->control_register & HDSPe_FLOAT_FORMAT) 5539 snd_printk(KERN_INFO "hdspm: Switching to native 32bit LE integer format.\n"); 5540 5541 hdspm->control_register &= ~HDSPe_FLOAT_FORMAT; 5542 } 5543 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 5544 5545 return 0; 5546 } 5547 5548 static int snd_hdspm_hw_free(struct snd_pcm_substream *substream) 5549 { 5550 int i; 5551 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5552 5553 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 5554 5555 /* params_channels(params) should be enough, 5556 but to get sure in case of error */ 5557 for (i = 0; i < hdspm->max_channels_out; ++i) 5558 snd_hdspm_enable_out(hdspm, i, 0); 5559 5560 hdspm->playback_buffer = NULL; 5561 } else { 5562 for (i = 0; i < hdspm->max_channels_in; ++i) 5563 snd_hdspm_enable_in(hdspm, i, 0); 5564 5565 hdspm->capture_buffer = NULL; 5566 5567 } 5568 5569 snd_pcm_lib_free_pages(substream); 5570 5571 return 0; 5572 } 5573 5574 5575 static int snd_hdspm_channel_info(struct snd_pcm_substream *substream, 5576 struct snd_pcm_channel_info *info) 5577 { 5578 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5579 5580 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 5581 if (snd_BUG_ON(info->channel >= hdspm->max_channels_out)) { 5582 snd_printk(KERN_INFO "snd_hdspm_channel_info: output channel out of range (%d)\n", info->channel); 5583 return -EINVAL; 5584 } 5585 5586 if (hdspm->channel_map_out[info->channel] < 0) { 5587 snd_printk(KERN_INFO "snd_hdspm_channel_info: output channel %d mapped out\n", info->channel); 5588 return -EINVAL; 5589 } 5590 5591 info->offset = hdspm->channel_map_out[info->channel] * 5592 HDSPM_CHANNEL_BUFFER_BYTES; 5593 } else { 5594 if (snd_BUG_ON(info->channel >= hdspm->max_channels_in)) { 5595 snd_printk(KERN_INFO "snd_hdspm_channel_info: input channel out of range (%d)\n", info->channel); 5596 return -EINVAL; 5597 } 5598 5599 if (hdspm->channel_map_in[info->channel] < 0) { 5600 snd_printk(KERN_INFO "snd_hdspm_channel_info: input channel %d mapped out\n", info->channel); 5601 return -EINVAL; 5602 } 5603 5604 info->offset = hdspm->channel_map_in[info->channel] * 5605 HDSPM_CHANNEL_BUFFER_BYTES; 5606 } 5607 5608 info->first = 0; 5609 info->step = 32; 5610 return 0; 5611 } 5612 5613 5614 static int snd_hdspm_ioctl(struct snd_pcm_substream *substream, 5615 unsigned int cmd, void *arg) 5616 { 5617 switch (cmd) { 5618 case SNDRV_PCM_IOCTL1_RESET: 5619 return snd_hdspm_reset(substream); 5620 5621 case SNDRV_PCM_IOCTL1_CHANNEL_INFO: 5622 { 5623 struct snd_pcm_channel_info *info = arg; 5624 return snd_hdspm_channel_info(substream, info); 5625 } 5626 default: 5627 break; 5628 } 5629 5630 return snd_pcm_lib_ioctl(substream, cmd, arg); 5631 } 5632 5633 static int snd_hdspm_trigger(struct snd_pcm_substream *substream, int cmd) 5634 { 5635 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5636 struct snd_pcm_substream *other; 5637 int running; 5638 5639 spin_lock(&hdspm->lock); 5640 running = hdspm->running; 5641 switch (cmd) { 5642 case SNDRV_PCM_TRIGGER_START: 5643 running |= 1 << substream->stream; 5644 break; 5645 case SNDRV_PCM_TRIGGER_STOP: 5646 running &= ~(1 << substream->stream); 5647 break; 5648 default: 5649 snd_BUG(); 5650 spin_unlock(&hdspm->lock); 5651 return -EINVAL; 5652 } 5653 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 5654 other = hdspm->capture_substream; 5655 else 5656 other = hdspm->playback_substream; 5657 5658 if (other) { 5659 struct snd_pcm_substream *s; 5660 snd_pcm_group_for_each_entry(s, substream) { 5661 if (s == other) { 5662 snd_pcm_trigger_done(s, substream); 5663 if (cmd == SNDRV_PCM_TRIGGER_START) 5664 running |= 1 << s->stream; 5665 else 5666 running &= ~(1 << s->stream); 5667 goto _ok; 5668 } 5669 } 5670 if (cmd == SNDRV_PCM_TRIGGER_START) { 5671 if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK)) 5672 && substream->stream == 5673 SNDRV_PCM_STREAM_CAPTURE) 5674 hdspm_silence_playback(hdspm); 5675 } else { 5676 if (running && 5677 substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 5678 hdspm_silence_playback(hdspm); 5679 } 5680 } else { 5681 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 5682 hdspm_silence_playback(hdspm); 5683 } 5684 _ok: 5685 snd_pcm_trigger_done(substream, substream); 5686 if (!hdspm->running && running) 5687 hdspm_start_audio(hdspm); 5688 else if (hdspm->running && !running) 5689 hdspm_stop_audio(hdspm); 5690 hdspm->running = running; 5691 spin_unlock(&hdspm->lock); 5692 5693 return 0; 5694 } 5695 5696 static int snd_hdspm_prepare(struct snd_pcm_substream *substream) 5697 { 5698 return 0; 5699 } 5700 5701 static struct snd_pcm_hardware snd_hdspm_playback_subinfo = { 5702 .info = (SNDRV_PCM_INFO_MMAP | 5703 SNDRV_PCM_INFO_MMAP_VALID | 5704 SNDRV_PCM_INFO_NONINTERLEAVED | 5705 SNDRV_PCM_INFO_SYNC_START | SNDRV_PCM_INFO_DOUBLE), 5706 .formats = SNDRV_PCM_FMTBIT_S32_LE, 5707 .rates = (SNDRV_PCM_RATE_32000 | 5708 SNDRV_PCM_RATE_44100 | 5709 SNDRV_PCM_RATE_48000 | 5710 SNDRV_PCM_RATE_64000 | 5711 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | 5712 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000 ), 5713 .rate_min = 32000, 5714 .rate_max = 192000, 5715 .channels_min = 1, 5716 .channels_max = HDSPM_MAX_CHANNELS, 5717 .buffer_bytes_max = 5718 HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS, 5719 .period_bytes_min = (32 * 4), 5720 .period_bytes_max = (8192 * 4) * HDSPM_MAX_CHANNELS, 5721 .periods_min = 2, 5722 .periods_max = 512, 5723 .fifo_size = 0 5724 }; 5725 5726 static struct snd_pcm_hardware snd_hdspm_capture_subinfo = { 5727 .info = (SNDRV_PCM_INFO_MMAP | 5728 SNDRV_PCM_INFO_MMAP_VALID | 5729 SNDRV_PCM_INFO_NONINTERLEAVED | 5730 SNDRV_PCM_INFO_SYNC_START), 5731 .formats = SNDRV_PCM_FMTBIT_S32_LE, 5732 .rates = (SNDRV_PCM_RATE_32000 | 5733 SNDRV_PCM_RATE_44100 | 5734 SNDRV_PCM_RATE_48000 | 5735 SNDRV_PCM_RATE_64000 | 5736 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | 5737 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000), 5738 .rate_min = 32000, 5739 .rate_max = 192000, 5740 .channels_min = 1, 5741 .channels_max = HDSPM_MAX_CHANNELS, 5742 .buffer_bytes_max = 5743 HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS, 5744 .period_bytes_min = (32 * 4), 5745 .period_bytes_max = (8192 * 4) * HDSPM_MAX_CHANNELS, 5746 .periods_min = 2, 5747 .periods_max = 512, 5748 .fifo_size = 0 5749 }; 5750 5751 static int snd_hdspm_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params, 5752 struct snd_pcm_hw_rule *rule) 5753 { 5754 struct hdspm *hdspm = rule->private; 5755 struct snd_interval *c = 5756 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 5757 struct snd_interval *r = 5758 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 5759 5760 if (r->min > 96000 && r->max <= 192000) { 5761 struct snd_interval t = { 5762 .min = hdspm->qs_in_channels, 5763 .max = hdspm->qs_in_channels, 5764 .integer = 1, 5765 }; 5766 return snd_interval_refine(c, &t); 5767 } else if (r->min > 48000 && r->max <= 96000) { 5768 struct snd_interval t = { 5769 .min = hdspm->ds_in_channels, 5770 .max = hdspm->ds_in_channels, 5771 .integer = 1, 5772 }; 5773 return snd_interval_refine(c, &t); 5774 } else if (r->max < 64000) { 5775 struct snd_interval t = { 5776 .min = hdspm->ss_in_channels, 5777 .max = hdspm->ss_in_channels, 5778 .integer = 1, 5779 }; 5780 return snd_interval_refine(c, &t); 5781 } 5782 5783 return 0; 5784 } 5785 5786 static int snd_hdspm_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params, 5787 struct snd_pcm_hw_rule * rule) 5788 { 5789 struct hdspm *hdspm = rule->private; 5790 struct snd_interval *c = 5791 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 5792 struct snd_interval *r = 5793 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 5794 5795 if (r->min > 96000 && r->max <= 192000) { 5796 struct snd_interval t = { 5797 .min = hdspm->qs_out_channels, 5798 .max = hdspm->qs_out_channels, 5799 .integer = 1, 5800 }; 5801 return snd_interval_refine(c, &t); 5802 } else if (r->min > 48000 && r->max <= 96000) { 5803 struct snd_interval t = { 5804 .min = hdspm->ds_out_channels, 5805 .max = hdspm->ds_out_channels, 5806 .integer = 1, 5807 }; 5808 return snd_interval_refine(c, &t); 5809 } else if (r->max < 64000) { 5810 struct snd_interval t = { 5811 .min = hdspm->ss_out_channels, 5812 .max = hdspm->ss_out_channels, 5813 .integer = 1, 5814 }; 5815 return snd_interval_refine(c, &t); 5816 } else { 5817 } 5818 return 0; 5819 } 5820 5821 static int snd_hdspm_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params, 5822 struct snd_pcm_hw_rule * rule) 5823 { 5824 struct hdspm *hdspm = rule->private; 5825 struct snd_interval *c = 5826 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 5827 struct snd_interval *r = 5828 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 5829 5830 if (c->min >= hdspm->ss_in_channels) { 5831 struct snd_interval t = { 5832 .min = 32000, 5833 .max = 48000, 5834 .integer = 1, 5835 }; 5836 return snd_interval_refine(r, &t); 5837 } else if (c->max <= hdspm->qs_in_channels) { 5838 struct snd_interval t = { 5839 .min = 128000, 5840 .max = 192000, 5841 .integer = 1, 5842 }; 5843 return snd_interval_refine(r, &t); 5844 } else if (c->max <= hdspm->ds_in_channels) { 5845 struct snd_interval t = { 5846 .min = 64000, 5847 .max = 96000, 5848 .integer = 1, 5849 }; 5850 return snd_interval_refine(r, &t); 5851 } 5852 5853 return 0; 5854 } 5855 static int snd_hdspm_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params, 5856 struct snd_pcm_hw_rule *rule) 5857 { 5858 struct hdspm *hdspm = rule->private; 5859 struct snd_interval *c = 5860 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 5861 struct snd_interval *r = 5862 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 5863 5864 if (c->min >= hdspm->ss_out_channels) { 5865 struct snd_interval t = { 5866 .min = 32000, 5867 .max = 48000, 5868 .integer = 1, 5869 }; 5870 return snd_interval_refine(r, &t); 5871 } else if (c->max <= hdspm->qs_out_channels) { 5872 struct snd_interval t = { 5873 .min = 128000, 5874 .max = 192000, 5875 .integer = 1, 5876 }; 5877 return snd_interval_refine(r, &t); 5878 } else if (c->max <= hdspm->ds_out_channels) { 5879 struct snd_interval t = { 5880 .min = 64000, 5881 .max = 96000, 5882 .integer = 1, 5883 }; 5884 return snd_interval_refine(r, &t); 5885 } 5886 5887 return 0; 5888 } 5889 5890 static int snd_hdspm_hw_rule_in_channels(struct snd_pcm_hw_params *params, 5891 struct snd_pcm_hw_rule *rule) 5892 { 5893 unsigned int list[3]; 5894 struct hdspm *hdspm = rule->private; 5895 struct snd_interval *c = hw_param_interval(params, 5896 SNDRV_PCM_HW_PARAM_CHANNELS); 5897 5898 list[0] = hdspm->qs_in_channels; 5899 list[1] = hdspm->ds_in_channels; 5900 list[2] = hdspm->ss_in_channels; 5901 return snd_interval_list(c, 3, list, 0); 5902 } 5903 5904 static int snd_hdspm_hw_rule_out_channels(struct snd_pcm_hw_params *params, 5905 struct snd_pcm_hw_rule *rule) 5906 { 5907 unsigned int list[3]; 5908 struct hdspm *hdspm = rule->private; 5909 struct snd_interval *c = hw_param_interval(params, 5910 SNDRV_PCM_HW_PARAM_CHANNELS); 5911 5912 list[0] = hdspm->qs_out_channels; 5913 list[1] = hdspm->ds_out_channels; 5914 list[2] = hdspm->ss_out_channels; 5915 return snd_interval_list(c, 3, list, 0); 5916 } 5917 5918 5919 static unsigned int hdspm_aes32_sample_rates[] = { 5920 32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000 5921 }; 5922 5923 static struct snd_pcm_hw_constraint_list 5924 hdspm_hw_constraints_aes32_sample_rates = { 5925 .count = ARRAY_SIZE(hdspm_aes32_sample_rates), 5926 .list = hdspm_aes32_sample_rates, 5927 .mask = 0 5928 }; 5929 5930 static int snd_hdspm_playback_open(struct snd_pcm_substream *substream) 5931 { 5932 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5933 struct snd_pcm_runtime *runtime = substream->runtime; 5934 5935 spin_lock_irq(&hdspm->lock); 5936 5937 snd_pcm_set_sync(substream); 5938 5939 5940 runtime->hw = snd_hdspm_playback_subinfo; 5941 5942 if (hdspm->capture_substream == NULL) 5943 hdspm_stop_audio(hdspm); 5944 5945 hdspm->playback_pid = current->pid; 5946 hdspm->playback_substream = substream; 5947 5948 spin_unlock_irq(&hdspm->lock); 5949 5950 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24); 5951 snd_pcm_hw_constraint_pow2(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE); 5952 5953 switch (hdspm->io_type) { 5954 case AIO: 5955 case RayDAT: 5956 snd_pcm_hw_constraint_minmax(runtime, 5957 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 5958 32, 4096); 5959 /* RayDAT & AIO have a fixed buffer of 16384 samples per channel */ 5960 snd_pcm_hw_constraint_minmax(runtime, 5961 SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 5962 16384, 16384); 5963 break; 5964 5965 default: 5966 snd_pcm_hw_constraint_minmax(runtime, 5967 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 5968 64, 8192); 5969 break; 5970 } 5971 5972 if (AES32 == hdspm->io_type) { 5973 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT; 5974 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 5975 &hdspm_hw_constraints_aes32_sample_rates); 5976 } else { 5977 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 5978 snd_hdspm_hw_rule_rate_out_channels, hdspm, 5979 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 5980 } 5981 5982 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 5983 snd_hdspm_hw_rule_out_channels, hdspm, 5984 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 5985 5986 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 5987 snd_hdspm_hw_rule_out_channels_rate, hdspm, 5988 SNDRV_PCM_HW_PARAM_RATE, -1); 5989 5990 return 0; 5991 } 5992 5993 static int snd_hdspm_playback_release(struct snd_pcm_substream *substream) 5994 { 5995 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5996 5997 spin_lock_irq(&hdspm->lock); 5998 5999 hdspm->playback_pid = -1; 6000 hdspm->playback_substream = NULL; 6001 6002 spin_unlock_irq(&hdspm->lock); 6003 6004 return 0; 6005 } 6006 6007 6008 static int snd_hdspm_capture_open(struct snd_pcm_substream *substream) 6009 { 6010 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 6011 struct snd_pcm_runtime *runtime = substream->runtime; 6012 6013 spin_lock_irq(&hdspm->lock); 6014 snd_pcm_set_sync(substream); 6015 runtime->hw = snd_hdspm_capture_subinfo; 6016 6017 if (hdspm->playback_substream == NULL) 6018 hdspm_stop_audio(hdspm); 6019 6020 hdspm->capture_pid = current->pid; 6021 hdspm->capture_substream = substream; 6022 6023 spin_unlock_irq(&hdspm->lock); 6024 6025 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24); 6026 snd_pcm_hw_constraint_pow2(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE); 6027 6028 switch (hdspm->io_type) { 6029 case AIO: 6030 case RayDAT: 6031 snd_pcm_hw_constraint_minmax(runtime, 6032 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 6033 32, 4096); 6034 snd_pcm_hw_constraint_minmax(runtime, 6035 SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 6036 16384, 16384); 6037 break; 6038 6039 default: 6040 snd_pcm_hw_constraint_minmax(runtime, 6041 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 6042 64, 8192); 6043 break; 6044 } 6045 6046 if (AES32 == hdspm->io_type) { 6047 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT; 6048 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 6049 &hdspm_hw_constraints_aes32_sample_rates); 6050 } else { 6051 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 6052 snd_hdspm_hw_rule_rate_in_channels, hdspm, 6053 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 6054 } 6055 6056 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 6057 snd_hdspm_hw_rule_in_channels, hdspm, 6058 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 6059 6060 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 6061 snd_hdspm_hw_rule_in_channels_rate, hdspm, 6062 SNDRV_PCM_HW_PARAM_RATE, -1); 6063 6064 return 0; 6065 } 6066 6067 static int snd_hdspm_capture_release(struct snd_pcm_substream *substream) 6068 { 6069 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 6070 6071 spin_lock_irq(&hdspm->lock); 6072 6073 hdspm->capture_pid = -1; 6074 hdspm->capture_substream = NULL; 6075 6076 spin_unlock_irq(&hdspm->lock); 6077 return 0; 6078 } 6079 6080 static int snd_hdspm_hwdep_dummy_op(struct snd_hwdep *hw, struct file *file) 6081 { 6082 /* we have nothing to initialize but the call is required */ 6083 return 0; 6084 } 6085 6086 static inline int copy_u32_le(void __user *dest, void __iomem *src) 6087 { 6088 u32 val = readl(src); 6089 return copy_to_user(dest, &val, 4); 6090 } 6091 6092 static int snd_hdspm_hwdep_ioctl(struct snd_hwdep *hw, struct file *file, 6093 unsigned int cmd, unsigned long arg) 6094 { 6095 void __user *argp = (void __user *)arg; 6096 struct hdspm *hdspm = hw->private_data; 6097 struct hdspm_mixer_ioctl mixer; 6098 struct hdspm_config info; 6099 struct hdspm_status status; 6100 struct hdspm_version hdspm_version; 6101 struct hdspm_peak_rms *levels; 6102 struct hdspm_ltc ltc; 6103 unsigned int statusregister; 6104 long unsigned int s; 6105 int i = 0; 6106 6107 switch (cmd) { 6108 6109 case SNDRV_HDSPM_IOCTL_GET_PEAK_RMS: 6110 levels = &hdspm->peak_rms; 6111 for (i = 0; i < HDSPM_MAX_CHANNELS; i++) { 6112 levels->input_peaks[i] = 6113 readl(hdspm->iobase + 6114 HDSPM_MADI_INPUT_PEAK + i*4); 6115 levels->playback_peaks[i] = 6116 readl(hdspm->iobase + 6117 HDSPM_MADI_PLAYBACK_PEAK + i*4); 6118 levels->output_peaks[i] = 6119 readl(hdspm->iobase + 6120 HDSPM_MADI_OUTPUT_PEAK + i*4); 6121 6122 levels->input_rms[i] = 6123 ((uint64_t) readl(hdspm->iobase + 6124 HDSPM_MADI_INPUT_RMS_H + i*4) << 32) | 6125 (uint64_t) readl(hdspm->iobase + 6126 HDSPM_MADI_INPUT_RMS_L + i*4); 6127 levels->playback_rms[i] = 6128 ((uint64_t)readl(hdspm->iobase + 6129 HDSPM_MADI_PLAYBACK_RMS_H+i*4) << 32) | 6130 (uint64_t)readl(hdspm->iobase + 6131 HDSPM_MADI_PLAYBACK_RMS_L + i*4); 6132 levels->output_rms[i] = 6133 ((uint64_t)readl(hdspm->iobase + 6134 HDSPM_MADI_OUTPUT_RMS_H + i*4) << 32) | 6135 (uint64_t)readl(hdspm->iobase + 6136 HDSPM_MADI_OUTPUT_RMS_L + i*4); 6137 } 6138 6139 if (hdspm->system_sample_rate > 96000) { 6140 levels->speed = qs; 6141 } else if (hdspm->system_sample_rate > 48000) { 6142 levels->speed = ds; 6143 } else { 6144 levels->speed = ss; 6145 } 6146 levels->status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 6147 6148 s = copy_to_user(argp, levels, sizeof(struct hdspm_peak_rms)); 6149 if (0 != s) { 6150 /* snd_printk(KERN_ERR "copy_to_user(.., .., %lu): %lu 6151 [Levels]\n", sizeof(struct hdspm_peak_rms), s); 6152 */ 6153 return -EFAULT; 6154 } 6155 break; 6156 6157 case SNDRV_HDSPM_IOCTL_GET_LTC: 6158 ltc.ltc = hdspm_read(hdspm, HDSPM_RD_TCO); 6159 i = hdspm_read(hdspm, HDSPM_RD_TCO + 4); 6160 if (i & HDSPM_TCO1_LTC_Input_valid) { 6161 switch (i & (HDSPM_TCO1_LTC_Format_LSB | 6162 HDSPM_TCO1_LTC_Format_MSB)) { 6163 case 0: 6164 ltc.format = fps_24; 6165 break; 6166 case HDSPM_TCO1_LTC_Format_LSB: 6167 ltc.format = fps_25; 6168 break; 6169 case HDSPM_TCO1_LTC_Format_MSB: 6170 ltc.format = fps_2997; 6171 break; 6172 default: 6173 ltc.format = 30; 6174 break; 6175 } 6176 if (i & HDSPM_TCO1_set_drop_frame_flag) { 6177 ltc.frame = drop_frame; 6178 } else { 6179 ltc.frame = full_frame; 6180 } 6181 } else { 6182 ltc.format = format_invalid; 6183 ltc.frame = frame_invalid; 6184 } 6185 if (i & HDSPM_TCO1_Video_Input_Format_NTSC) { 6186 ltc.input_format = ntsc; 6187 } else if (i & HDSPM_TCO1_Video_Input_Format_PAL) { 6188 ltc.input_format = pal; 6189 } else { 6190 ltc.input_format = no_video; 6191 } 6192 6193 s = copy_to_user(argp, <c, sizeof(struct hdspm_ltc)); 6194 if (0 != s) { 6195 /* 6196 snd_printk(KERN_ERR "copy_to_user(.., .., %lu): %lu [LTC]\n", sizeof(struct hdspm_ltc), s); */ 6197 return -EFAULT; 6198 } 6199 6200 break; 6201 6202 case SNDRV_HDSPM_IOCTL_GET_CONFIG: 6203 6204 memset(&info, 0, sizeof(info)); 6205 spin_lock_irq(&hdspm->lock); 6206 info.pref_sync_ref = hdspm_pref_sync_ref(hdspm); 6207 info.wordclock_sync_check = hdspm_wc_sync_check(hdspm); 6208 6209 info.system_sample_rate = hdspm->system_sample_rate; 6210 info.autosync_sample_rate = 6211 hdspm_external_sample_rate(hdspm); 6212 info.system_clock_mode = hdspm_system_clock_mode(hdspm); 6213 info.clock_source = hdspm_clock_source(hdspm); 6214 info.autosync_ref = hdspm_autosync_ref(hdspm); 6215 info.line_out = hdspm_line_out(hdspm); 6216 info.passthru = 0; 6217 spin_unlock_irq(&hdspm->lock); 6218 if (copy_to_user(argp, &info, sizeof(info))) 6219 return -EFAULT; 6220 break; 6221 6222 case SNDRV_HDSPM_IOCTL_GET_STATUS: 6223 memset(&status, 0, sizeof(status)); 6224 6225 status.card_type = hdspm->io_type; 6226 6227 status.autosync_source = hdspm_autosync_ref(hdspm); 6228 6229 status.card_clock = 110069313433624ULL; 6230 status.master_period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ); 6231 6232 switch (hdspm->io_type) { 6233 case MADI: 6234 case MADIface: 6235 status.card_specific.madi.sync_wc = 6236 hdspm_wc_sync_check(hdspm); 6237 status.card_specific.madi.sync_madi = 6238 hdspm_madi_sync_check(hdspm); 6239 status.card_specific.madi.sync_tco = 6240 hdspm_tco_sync_check(hdspm); 6241 status.card_specific.madi.sync_in = 6242 hdspm_sync_in_sync_check(hdspm); 6243 6244 statusregister = 6245 hdspm_read(hdspm, HDSPM_statusRegister); 6246 status.card_specific.madi.madi_input = 6247 (statusregister & HDSPM_AB_int) ? 1 : 0; 6248 status.card_specific.madi.channel_format = 6249 (statusregister & HDSPM_RX_64ch) ? 1 : 0; 6250 /* TODO: Mac driver sets it when f_s>48kHz */ 6251 status.card_specific.madi.frame_format = 0; 6252 6253 default: 6254 break; 6255 } 6256 6257 if (copy_to_user(argp, &status, sizeof(status))) 6258 return -EFAULT; 6259 6260 6261 break; 6262 6263 case SNDRV_HDSPM_IOCTL_GET_VERSION: 6264 memset(&hdspm_version, 0, sizeof(hdspm_version)); 6265 6266 hdspm_version.card_type = hdspm->io_type; 6267 strncpy(hdspm_version.cardname, hdspm->card_name, 6268 sizeof(hdspm_version.cardname)); 6269 hdspm_version.serial = (hdspm_read(hdspm, 6270 HDSPM_midiStatusIn0)>>8) & 0xFFFFFF; 6271 hdspm_version.firmware_rev = hdspm->firmware_rev; 6272 hdspm_version.addons = 0; 6273 if (hdspm->tco) 6274 hdspm_version.addons |= HDSPM_ADDON_TCO; 6275 6276 if (copy_to_user(argp, &hdspm_version, 6277 sizeof(hdspm_version))) 6278 return -EFAULT; 6279 break; 6280 6281 case SNDRV_HDSPM_IOCTL_GET_MIXER: 6282 if (copy_from_user(&mixer, argp, sizeof(mixer))) 6283 return -EFAULT; 6284 if (copy_to_user((void __user *)mixer.mixer, hdspm->mixer, 6285 sizeof(struct hdspm_mixer))) 6286 return -EFAULT; 6287 break; 6288 6289 default: 6290 return -EINVAL; 6291 } 6292 return 0; 6293 } 6294 6295 static struct snd_pcm_ops snd_hdspm_playback_ops = { 6296 .open = snd_hdspm_playback_open, 6297 .close = snd_hdspm_playback_release, 6298 .ioctl = snd_hdspm_ioctl, 6299 .hw_params = snd_hdspm_hw_params, 6300 .hw_free = snd_hdspm_hw_free, 6301 .prepare = snd_hdspm_prepare, 6302 .trigger = snd_hdspm_trigger, 6303 .pointer = snd_hdspm_hw_pointer, 6304 .page = snd_pcm_sgbuf_ops_page, 6305 }; 6306 6307 static struct snd_pcm_ops snd_hdspm_capture_ops = { 6308 .open = snd_hdspm_capture_open, 6309 .close = snd_hdspm_capture_release, 6310 .ioctl = snd_hdspm_ioctl, 6311 .hw_params = snd_hdspm_hw_params, 6312 .hw_free = snd_hdspm_hw_free, 6313 .prepare = snd_hdspm_prepare, 6314 .trigger = snd_hdspm_trigger, 6315 .pointer = snd_hdspm_hw_pointer, 6316 .page = snd_pcm_sgbuf_ops_page, 6317 }; 6318 6319 static int __devinit snd_hdspm_create_hwdep(struct snd_card *card, 6320 struct hdspm * hdspm) 6321 { 6322 struct snd_hwdep *hw; 6323 int err; 6324 6325 err = snd_hwdep_new(card, "HDSPM hwdep", 0, &hw); 6326 if (err < 0) 6327 return err; 6328 6329 hdspm->hwdep = hw; 6330 hw->private_data = hdspm; 6331 strcpy(hw->name, "HDSPM hwdep interface"); 6332 6333 hw->ops.open = snd_hdspm_hwdep_dummy_op; 6334 hw->ops.ioctl = snd_hdspm_hwdep_ioctl; 6335 hw->ops.release = snd_hdspm_hwdep_dummy_op; 6336 6337 return 0; 6338 } 6339 6340 6341 /*------------------------------------------------------------ 6342 memory interface 6343 ------------------------------------------------------------*/ 6344 static int __devinit snd_hdspm_preallocate_memory(struct hdspm *hdspm) 6345 { 6346 int err; 6347 struct snd_pcm *pcm; 6348 size_t wanted; 6349 6350 pcm = hdspm->pcm; 6351 6352 wanted = HDSPM_DMA_AREA_BYTES; 6353 6354 err = 6355 snd_pcm_lib_preallocate_pages_for_all(pcm, 6356 SNDRV_DMA_TYPE_DEV_SG, 6357 snd_dma_pci_data(hdspm->pci), 6358 wanted, 6359 wanted); 6360 if (err < 0) { 6361 snd_printdd("Could not preallocate %zd Bytes\n", wanted); 6362 6363 return err; 6364 } else 6365 snd_printdd(" Preallocated %zd Bytes\n", wanted); 6366 6367 return 0; 6368 } 6369 6370 6371 static void hdspm_set_sgbuf(struct hdspm *hdspm, 6372 struct snd_pcm_substream *substream, 6373 unsigned int reg, int channels) 6374 { 6375 int i; 6376 6377 /* continuous memory segment */ 6378 for (i = 0; i < (channels * 16); i++) 6379 hdspm_write(hdspm, reg + 4 * i, 6380 snd_pcm_sgbuf_get_addr(substream, 4096 * i)); 6381 } 6382 6383 6384 /* ------------- ALSA Devices ---------------------------- */ 6385 static int __devinit snd_hdspm_create_pcm(struct snd_card *card, 6386 struct hdspm *hdspm) 6387 { 6388 struct snd_pcm *pcm; 6389 int err; 6390 6391 err = snd_pcm_new(card, hdspm->card_name, 0, 1, 1, &pcm); 6392 if (err < 0) 6393 return err; 6394 6395 hdspm->pcm = pcm; 6396 pcm->private_data = hdspm; 6397 strcpy(pcm->name, hdspm->card_name); 6398 6399 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, 6400 &snd_hdspm_playback_ops); 6401 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, 6402 &snd_hdspm_capture_ops); 6403 6404 pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX; 6405 6406 err = snd_hdspm_preallocate_memory(hdspm); 6407 if (err < 0) 6408 return err; 6409 6410 return 0; 6411 } 6412 6413 static inline void snd_hdspm_initialize_midi_flush(struct hdspm * hdspm) 6414 { 6415 int i; 6416 6417 for (i = 0; i < hdspm->midiPorts; i++) 6418 snd_hdspm_flush_midi_input(hdspm, i); 6419 } 6420 6421 static int __devinit snd_hdspm_create_alsa_devices(struct snd_card *card, 6422 struct hdspm * hdspm) 6423 { 6424 int err, i; 6425 6426 snd_printdd("Create card...\n"); 6427 err = snd_hdspm_create_pcm(card, hdspm); 6428 if (err < 0) 6429 return err; 6430 6431 i = 0; 6432 while (i < hdspm->midiPorts) { 6433 err = snd_hdspm_create_midi(card, hdspm, i); 6434 if (err < 0) { 6435 return err; 6436 } 6437 i++; 6438 } 6439 6440 err = snd_hdspm_create_controls(card, hdspm); 6441 if (err < 0) 6442 return err; 6443 6444 err = snd_hdspm_create_hwdep(card, hdspm); 6445 if (err < 0) 6446 return err; 6447 6448 snd_printdd("proc init...\n"); 6449 snd_hdspm_proc_init(hdspm); 6450 6451 hdspm->system_sample_rate = -1; 6452 hdspm->last_external_sample_rate = -1; 6453 hdspm->last_internal_sample_rate = -1; 6454 hdspm->playback_pid = -1; 6455 hdspm->capture_pid = -1; 6456 hdspm->capture_substream = NULL; 6457 hdspm->playback_substream = NULL; 6458 6459 snd_printdd("Set defaults...\n"); 6460 err = snd_hdspm_set_defaults(hdspm); 6461 if (err < 0) 6462 return err; 6463 6464 snd_printdd("Update mixer controls...\n"); 6465 hdspm_update_simple_mixer_controls(hdspm); 6466 6467 snd_printdd("Initializeing complete ???\n"); 6468 6469 err = snd_card_register(card); 6470 if (err < 0) { 6471 snd_printk(KERN_ERR "HDSPM: error registering card\n"); 6472 return err; 6473 } 6474 6475 snd_printdd("... yes now\n"); 6476 6477 return 0; 6478 } 6479 6480 static int __devinit snd_hdspm_create(struct snd_card *card, 6481 struct hdspm *hdspm) { 6482 6483 struct pci_dev *pci = hdspm->pci; 6484 int err; 6485 unsigned long io_extent; 6486 6487 hdspm->irq = -1; 6488 hdspm->card = card; 6489 6490 spin_lock_init(&hdspm->lock); 6491 6492 pci_read_config_word(hdspm->pci, 6493 PCI_CLASS_REVISION, &hdspm->firmware_rev); 6494 6495 strcpy(card->mixername, "Xilinx FPGA"); 6496 strcpy(card->driver, "HDSPM"); 6497 6498 switch (hdspm->firmware_rev) { 6499 case HDSPM_RAYDAT_REV: 6500 hdspm->io_type = RayDAT; 6501 hdspm->card_name = "RME RayDAT"; 6502 hdspm->midiPorts = 2; 6503 break; 6504 case HDSPM_AIO_REV: 6505 hdspm->io_type = AIO; 6506 hdspm->card_name = "RME AIO"; 6507 hdspm->midiPorts = 1; 6508 break; 6509 case HDSPM_MADIFACE_REV: 6510 hdspm->io_type = MADIface; 6511 hdspm->card_name = "RME MADIface"; 6512 hdspm->midiPorts = 1; 6513 break; 6514 default: 6515 if ((hdspm->firmware_rev == 0xf0) || 6516 ((hdspm->firmware_rev >= 0xe6) && 6517 (hdspm->firmware_rev <= 0xea))) { 6518 hdspm->io_type = AES32; 6519 hdspm->card_name = "RME AES32"; 6520 hdspm->midiPorts = 2; 6521 } else if ((hdspm->firmware_rev == 0xd5) || 6522 ((hdspm->firmware_rev >= 0xc8) && 6523 (hdspm->firmware_rev <= 0xcf))) { 6524 hdspm->io_type = MADI; 6525 hdspm->card_name = "RME MADI"; 6526 hdspm->midiPorts = 3; 6527 } else { 6528 snd_printk(KERN_ERR 6529 "HDSPM: unknown firmware revision %x\n", 6530 hdspm->firmware_rev); 6531 return -ENODEV; 6532 } 6533 } 6534 6535 err = pci_enable_device(pci); 6536 if (err < 0) 6537 return err; 6538 6539 pci_set_master(hdspm->pci); 6540 6541 err = pci_request_regions(pci, "hdspm"); 6542 if (err < 0) 6543 return err; 6544 6545 hdspm->port = pci_resource_start(pci, 0); 6546 io_extent = pci_resource_len(pci, 0); 6547 6548 snd_printdd("grabbed memory region 0x%lx-0x%lx\n", 6549 hdspm->port, hdspm->port + io_extent - 1); 6550 6551 hdspm->iobase = ioremap_nocache(hdspm->port, io_extent); 6552 if (!hdspm->iobase) { 6553 snd_printk(KERN_ERR "HDSPM: " 6554 "unable to remap region 0x%lx-0x%lx\n", 6555 hdspm->port, hdspm->port + io_extent - 1); 6556 return -EBUSY; 6557 } 6558 snd_printdd("remapped region (0x%lx) 0x%lx-0x%lx\n", 6559 (unsigned long)hdspm->iobase, hdspm->port, 6560 hdspm->port + io_extent - 1); 6561 6562 if (request_irq(pci->irq, snd_hdspm_interrupt, 6563 IRQF_SHARED, KBUILD_MODNAME, hdspm)) { 6564 snd_printk(KERN_ERR "HDSPM: unable to use IRQ %d\n", pci->irq); 6565 return -EBUSY; 6566 } 6567 6568 snd_printdd("use IRQ %d\n", pci->irq); 6569 6570 hdspm->irq = pci->irq; 6571 6572 snd_printdd("kmalloc Mixer memory of %zd Bytes\n", 6573 sizeof(struct hdspm_mixer)); 6574 hdspm->mixer = kzalloc(sizeof(struct hdspm_mixer), GFP_KERNEL); 6575 if (!hdspm->mixer) { 6576 snd_printk(KERN_ERR "HDSPM: " 6577 "unable to kmalloc Mixer memory of %d Bytes\n", 6578 (int)sizeof(struct hdspm_mixer)); 6579 return err; 6580 } 6581 6582 hdspm->port_names_in = NULL; 6583 hdspm->port_names_out = NULL; 6584 6585 switch (hdspm->io_type) { 6586 case AES32: 6587 hdspm->ss_in_channels = hdspm->ss_out_channels = AES32_CHANNELS; 6588 hdspm->ds_in_channels = hdspm->ds_out_channels = AES32_CHANNELS; 6589 hdspm->qs_in_channels = hdspm->qs_out_channels = AES32_CHANNELS; 6590 6591 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss = 6592 channel_map_aes32; 6593 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds = 6594 channel_map_aes32; 6595 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs = 6596 channel_map_aes32; 6597 hdspm->port_names_in_ss = hdspm->port_names_out_ss = 6598 texts_ports_aes32; 6599 hdspm->port_names_in_ds = hdspm->port_names_out_ds = 6600 texts_ports_aes32; 6601 hdspm->port_names_in_qs = hdspm->port_names_out_qs = 6602 texts_ports_aes32; 6603 6604 hdspm->max_channels_out = hdspm->max_channels_in = 6605 AES32_CHANNELS; 6606 hdspm->port_names_in = hdspm->port_names_out = 6607 texts_ports_aes32; 6608 hdspm->channel_map_in = hdspm->channel_map_out = 6609 channel_map_aes32; 6610 6611 break; 6612 6613 case MADI: 6614 case MADIface: 6615 hdspm->ss_in_channels = hdspm->ss_out_channels = 6616 MADI_SS_CHANNELS; 6617 hdspm->ds_in_channels = hdspm->ds_out_channels = 6618 MADI_DS_CHANNELS; 6619 hdspm->qs_in_channels = hdspm->qs_out_channels = 6620 MADI_QS_CHANNELS; 6621 6622 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss = 6623 channel_map_unity_ss; 6624 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds = 6625 channel_map_unity_ss; 6626 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs = 6627 channel_map_unity_ss; 6628 6629 hdspm->port_names_in_ss = hdspm->port_names_out_ss = 6630 texts_ports_madi; 6631 hdspm->port_names_in_ds = hdspm->port_names_out_ds = 6632 texts_ports_madi; 6633 hdspm->port_names_in_qs = hdspm->port_names_out_qs = 6634 texts_ports_madi; 6635 break; 6636 6637 case AIO: 6638 if (0 == (hdspm_read(hdspm, HDSPM_statusRegister2) & HDSPM_s2_AEBI_D)) { 6639 snd_printk(KERN_INFO "HDSPM: AEB input board found, but not supported\n"); 6640 } 6641 6642 hdspm->ss_in_channels = AIO_IN_SS_CHANNELS; 6643 hdspm->ds_in_channels = AIO_IN_DS_CHANNELS; 6644 hdspm->qs_in_channels = AIO_IN_QS_CHANNELS; 6645 hdspm->ss_out_channels = AIO_OUT_SS_CHANNELS; 6646 hdspm->ds_out_channels = AIO_OUT_DS_CHANNELS; 6647 hdspm->qs_out_channels = AIO_OUT_QS_CHANNELS; 6648 6649 hdspm->channel_map_out_ss = channel_map_aio_out_ss; 6650 hdspm->channel_map_out_ds = channel_map_aio_out_ds; 6651 hdspm->channel_map_out_qs = channel_map_aio_out_qs; 6652 6653 hdspm->channel_map_in_ss = channel_map_aio_in_ss; 6654 hdspm->channel_map_in_ds = channel_map_aio_in_ds; 6655 hdspm->channel_map_in_qs = channel_map_aio_in_qs; 6656 6657 hdspm->port_names_in_ss = texts_ports_aio_in_ss; 6658 hdspm->port_names_out_ss = texts_ports_aio_out_ss; 6659 hdspm->port_names_in_ds = texts_ports_aio_in_ds; 6660 hdspm->port_names_out_ds = texts_ports_aio_out_ds; 6661 hdspm->port_names_in_qs = texts_ports_aio_in_qs; 6662 hdspm->port_names_out_qs = texts_ports_aio_out_qs; 6663 6664 break; 6665 6666 case RayDAT: 6667 hdspm->ss_in_channels = hdspm->ss_out_channels = 6668 RAYDAT_SS_CHANNELS; 6669 hdspm->ds_in_channels = hdspm->ds_out_channels = 6670 RAYDAT_DS_CHANNELS; 6671 hdspm->qs_in_channels = hdspm->qs_out_channels = 6672 RAYDAT_QS_CHANNELS; 6673 6674 hdspm->max_channels_in = RAYDAT_SS_CHANNELS; 6675 hdspm->max_channels_out = RAYDAT_SS_CHANNELS; 6676 6677 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss = 6678 channel_map_raydat_ss; 6679 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds = 6680 channel_map_raydat_ds; 6681 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs = 6682 channel_map_raydat_qs; 6683 hdspm->channel_map_in = hdspm->channel_map_out = 6684 channel_map_raydat_ss; 6685 6686 hdspm->port_names_in_ss = hdspm->port_names_out_ss = 6687 texts_ports_raydat_ss; 6688 hdspm->port_names_in_ds = hdspm->port_names_out_ds = 6689 texts_ports_raydat_ds; 6690 hdspm->port_names_in_qs = hdspm->port_names_out_qs = 6691 texts_ports_raydat_qs; 6692 6693 6694 break; 6695 6696 } 6697 6698 /* TCO detection */ 6699 switch (hdspm->io_type) { 6700 case AIO: 6701 case RayDAT: 6702 if (hdspm_read(hdspm, HDSPM_statusRegister2) & 6703 HDSPM_s2_tco_detect) { 6704 hdspm->midiPorts++; 6705 hdspm->tco = kzalloc(sizeof(struct hdspm_tco), 6706 GFP_KERNEL); 6707 if (NULL != hdspm->tco) { 6708 hdspm_tco_write(hdspm); 6709 } 6710 snd_printk(KERN_INFO "HDSPM: AIO/RayDAT TCO module found\n"); 6711 } else { 6712 hdspm->tco = NULL; 6713 } 6714 break; 6715 6716 case MADI: 6717 if (hdspm_read(hdspm, HDSPM_statusRegister) & HDSPM_tco_detect) { 6718 hdspm->midiPorts++; 6719 hdspm->tco = kzalloc(sizeof(struct hdspm_tco), 6720 GFP_KERNEL); 6721 if (NULL != hdspm->tco) { 6722 hdspm_tco_write(hdspm); 6723 } 6724 snd_printk(KERN_INFO "HDSPM: MADI TCO module found\n"); 6725 } else { 6726 hdspm->tco = NULL; 6727 } 6728 break; 6729 6730 default: 6731 hdspm->tco = NULL; 6732 } 6733 6734 /* texts */ 6735 switch (hdspm->io_type) { 6736 case AES32: 6737 if (hdspm->tco) { 6738 hdspm->texts_autosync = texts_autosync_aes_tco; 6739 hdspm->texts_autosync_items = 10; 6740 } else { 6741 hdspm->texts_autosync = texts_autosync_aes; 6742 hdspm->texts_autosync_items = 9; 6743 } 6744 break; 6745 6746 case MADI: 6747 if (hdspm->tco) { 6748 hdspm->texts_autosync = texts_autosync_madi_tco; 6749 hdspm->texts_autosync_items = 4; 6750 } else { 6751 hdspm->texts_autosync = texts_autosync_madi; 6752 hdspm->texts_autosync_items = 3; 6753 } 6754 break; 6755 6756 case MADIface: 6757 6758 break; 6759 6760 case RayDAT: 6761 if (hdspm->tco) { 6762 hdspm->texts_autosync = texts_autosync_raydat_tco; 6763 hdspm->texts_autosync_items = 9; 6764 } else { 6765 hdspm->texts_autosync = texts_autosync_raydat; 6766 hdspm->texts_autosync_items = 8; 6767 } 6768 break; 6769 6770 case AIO: 6771 if (hdspm->tco) { 6772 hdspm->texts_autosync = texts_autosync_aio_tco; 6773 hdspm->texts_autosync_items = 6; 6774 } else { 6775 hdspm->texts_autosync = texts_autosync_aio; 6776 hdspm->texts_autosync_items = 5; 6777 } 6778 break; 6779 6780 } 6781 6782 tasklet_init(&hdspm->midi_tasklet, 6783 hdspm_midi_tasklet, (unsigned long) hdspm); 6784 6785 snd_printdd("create alsa devices.\n"); 6786 err = snd_hdspm_create_alsa_devices(card, hdspm); 6787 if (err < 0) 6788 return err; 6789 6790 snd_hdspm_initialize_midi_flush(hdspm); 6791 6792 return 0; 6793 } 6794 6795 6796 static int snd_hdspm_free(struct hdspm * hdspm) 6797 { 6798 6799 if (hdspm->port) { 6800 6801 /* stop th audio, and cancel all interrupts */ 6802 hdspm->control_register &= 6803 ~(HDSPM_Start | HDSPM_AudioInterruptEnable | 6804 HDSPM_Midi0InterruptEnable | HDSPM_Midi1InterruptEnable | 6805 HDSPM_Midi2InterruptEnable | HDSPM_Midi3InterruptEnable); 6806 hdspm_write(hdspm, HDSPM_controlRegister, 6807 hdspm->control_register); 6808 } 6809 6810 if (hdspm->irq >= 0) 6811 free_irq(hdspm->irq, (void *) hdspm); 6812 6813 kfree(hdspm->mixer); 6814 6815 if (hdspm->iobase) 6816 iounmap(hdspm->iobase); 6817 6818 if (hdspm->port) 6819 pci_release_regions(hdspm->pci); 6820 6821 pci_disable_device(hdspm->pci); 6822 return 0; 6823 } 6824 6825 6826 static void snd_hdspm_card_free(struct snd_card *card) 6827 { 6828 struct hdspm *hdspm = card->private_data; 6829 6830 if (hdspm) 6831 snd_hdspm_free(hdspm); 6832 } 6833 6834 6835 static int __devinit snd_hdspm_probe(struct pci_dev *pci, 6836 const struct pci_device_id *pci_id) 6837 { 6838 static int dev; 6839 struct hdspm *hdspm; 6840 struct snd_card *card; 6841 int err; 6842 6843 if (dev >= SNDRV_CARDS) 6844 return -ENODEV; 6845 if (!enable[dev]) { 6846 dev++; 6847 return -ENOENT; 6848 } 6849 6850 err = snd_card_create(index[dev], id[dev], 6851 THIS_MODULE, sizeof(struct hdspm), &card); 6852 if (err < 0) 6853 return err; 6854 6855 hdspm = card->private_data; 6856 card->private_free = snd_hdspm_card_free; 6857 hdspm->dev = dev; 6858 hdspm->pci = pci; 6859 6860 snd_card_set_dev(card, &pci->dev); 6861 6862 err = snd_hdspm_create(card, hdspm); 6863 if (err < 0) { 6864 snd_card_free(card); 6865 return err; 6866 } 6867 6868 if (hdspm->io_type != MADIface) { 6869 sprintf(card->shortname, "%s_%x", 6870 hdspm->card_name, 6871 (hdspm_read(hdspm, HDSPM_midiStatusIn0)>>8) & 0xFFFFFF); 6872 sprintf(card->longname, "%s S/N 0x%x at 0x%lx, irq %d", 6873 hdspm->card_name, 6874 (hdspm_read(hdspm, HDSPM_midiStatusIn0)>>8) & 0xFFFFFF, 6875 hdspm->port, hdspm->irq); 6876 } else { 6877 sprintf(card->shortname, "%s", hdspm->card_name); 6878 sprintf(card->longname, "%s at 0x%lx, irq %d", 6879 hdspm->card_name, hdspm->port, hdspm->irq); 6880 } 6881 6882 err = snd_card_register(card); 6883 if (err < 0) { 6884 snd_card_free(card); 6885 return err; 6886 } 6887 6888 pci_set_drvdata(pci, card); 6889 6890 dev++; 6891 return 0; 6892 } 6893 6894 static void __devexit snd_hdspm_remove(struct pci_dev *pci) 6895 { 6896 snd_card_free(pci_get_drvdata(pci)); 6897 pci_set_drvdata(pci, NULL); 6898 } 6899 6900 static struct pci_driver driver = { 6901 .name = KBUILD_MODNAME, 6902 .id_table = snd_hdspm_ids, 6903 .probe = snd_hdspm_probe, 6904 .remove = __devexit_p(snd_hdspm_remove), 6905 }; 6906 6907 6908 static int __init alsa_card_hdspm_init(void) 6909 { 6910 return pci_register_driver(&driver); 6911 } 6912 6913 static void __exit alsa_card_hdspm_exit(void) 6914 { 6915 pci_unregister_driver(&driver); 6916 } 6917 6918 module_init(alsa_card_hdspm_init) 6919 module_exit(alsa_card_hdspm_exit) 6920