1 /* 2 * ALSA driver for RME Hammerfall DSP MADI audio interface(s) 3 * 4 * Copyright (c) 2003 Winfried Ritsch (IEM) 5 * code based on hdsp.c Paul Davis 6 * Marcus Andersson 7 * Thomas Charbonnel 8 * Modified 2006-06-01 for AES32 support by Remy Bruno 9 * <remy.bruno@trinnov.com> 10 * 11 * Modified 2009-04-13 for proper metering by Florian Faber 12 * <faber@faberman.de> 13 * 14 * Modified 2009-04-14 for native float support by Florian Faber 15 * <faber@faberman.de> 16 * 17 * Modified 2009-04-26 fixed bug in rms metering by Florian Faber 18 * <faber@faberman.de> 19 * 20 * Modified 2009-04-30 added hw serial number support by Florian Faber 21 * 22 * Modified 2011-01-14 added S/PDIF input on RayDATs by Adrian Knoth 23 * 24 * Modified 2011-01-25 variable period sizes on RayDAT/AIO by Adrian Knoth 25 * 26 * This program is free software; you can redistribute it and/or modify 27 * it under the terms of the GNU General Public License as published by 28 * the Free Software Foundation; either version 2 of the License, or 29 * (at your option) any later version. 30 * 31 * This program is distributed in the hope that it will be useful, 32 * but WITHOUT ANY WARRANTY; without even the implied warranty of 33 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 34 * GNU General Public License for more details. 35 * 36 * You should have received a copy of the GNU General Public License 37 * along with this program; if not, write to the Free Software 38 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 39 * 40 */ 41 #include <linux/init.h> 42 #include <linux/delay.h> 43 #include <linux/interrupt.h> 44 #include <linux/moduleparam.h> 45 #include <linux/slab.h> 46 #include <linux/pci.h> 47 #include <linux/math64.h> 48 #include <asm/io.h> 49 50 #include <sound/core.h> 51 #include <sound/control.h> 52 #include <sound/pcm.h> 53 #include <sound/pcm_params.h> 54 #include <sound/info.h> 55 #include <sound/asoundef.h> 56 #include <sound/rawmidi.h> 57 #include <sound/hwdep.h> 58 #include <sound/initval.h> 59 60 #include <sound/hdspm.h> 61 62 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ 63 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ 64 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;/* Enable this card */ 65 66 module_param_array(index, int, NULL, 0444); 67 MODULE_PARM_DESC(index, "Index value for RME HDSPM interface."); 68 69 module_param_array(id, charp, NULL, 0444); 70 MODULE_PARM_DESC(id, "ID string for RME HDSPM interface."); 71 72 module_param_array(enable, bool, NULL, 0444); 73 MODULE_PARM_DESC(enable, "Enable/disable specific HDSPM soundcards."); 74 75 76 MODULE_AUTHOR 77 ( 78 "Winfried Ritsch <ritsch_AT_iem.at>, " 79 "Paul Davis <paul@linuxaudiosystems.com>, " 80 "Marcus Andersson, Thomas Charbonnel <thomas@undata.org>, " 81 "Remy Bruno <remy.bruno@trinnov.com>, " 82 "Florian Faber <faberman@linuxproaudio.org>, " 83 "Adrian Knoth <adi@drcomp.erfurt.thur.de>" 84 ); 85 MODULE_DESCRIPTION("RME HDSPM"); 86 MODULE_LICENSE("GPL"); 87 MODULE_SUPPORTED_DEVICE("{{RME HDSPM-MADI}}"); 88 89 /* --- Write registers. --- 90 These are defined as byte-offsets from the iobase value. */ 91 92 #define HDSPM_WR_SETTINGS 0 93 #define HDSPM_outputBufferAddress 32 94 #define HDSPM_inputBufferAddress 36 95 #define HDSPM_controlRegister 64 96 #define HDSPM_interruptConfirmation 96 97 #define HDSPM_control2Reg 256 /* not in specs ???????? */ 98 #define HDSPM_freqReg 256 /* for AES32 */ 99 #define HDSPM_midiDataOut0 352 /* just believe in old code */ 100 #define HDSPM_midiDataOut1 356 101 #define HDSPM_eeprom_wr 384 /* for AES32 */ 102 103 /* DMA enable for 64 channels, only Bit 0 is relevant */ 104 #define HDSPM_outputEnableBase 512 /* 512-767 input DMA */ 105 #define HDSPM_inputEnableBase 768 /* 768-1023 output DMA */ 106 107 /* 16 page addresses for each of the 64 channels DMA buffer in and out 108 (each 64k=16*4k) Buffer must be 4k aligned (which is default i386 ????) */ 109 #define HDSPM_pageAddressBufferOut 8192 110 #define HDSPM_pageAddressBufferIn (HDSPM_pageAddressBufferOut+64*16*4) 111 112 #define HDSPM_MADI_mixerBase 32768 /* 32768-65535 for 2x64x64 Fader */ 113 114 #define HDSPM_MATRIX_MIXER_SIZE 8192 /* = 2*64*64 * 4 Byte => 32kB */ 115 116 /* --- Read registers. --- 117 These are defined as byte-offsets from the iobase value */ 118 #define HDSPM_statusRegister 0 119 /*#define HDSPM_statusRegister2 96 */ 120 /* after RME Windows driver sources, status2 is 4-byte word # 48 = word at 121 * offset 192, for AES32 *and* MADI 122 * => need to check that offset 192 is working on MADI */ 123 #define HDSPM_statusRegister2 192 124 #define HDSPM_timecodeRegister 128 125 126 /* AIO, RayDAT */ 127 #define HDSPM_RD_STATUS_0 0 128 #define HDSPM_RD_STATUS_1 64 129 #define HDSPM_RD_STATUS_2 128 130 #define HDSPM_RD_STATUS_3 192 131 132 #define HDSPM_RD_TCO 256 133 #define HDSPM_RD_PLL_FREQ 512 134 #define HDSPM_WR_TCO 128 135 136 #define HDSPM_TCO1_TCO_lock 0x00000001 137 #define HDSPM_TCO1_WCK_Input_Range_LSB 0x00000002 138 #define HDSPM_TCO1_WCK_Input_Range_MSB 0x00000004 139 #define HDSPM_TCO1_LTC_Input_valid 0x00000008 140 #define HDSPM_TCO1_WCK_Input_valid 0x00000010 141 #define HDSPM_TCO1_Video_Input_Format_NTSC 0x00000020 142 #define HDSPM_TCO1_Video_Input_Format_PAL 0x00000040 143 144 #define HDSPM_TCO1_set_TC 0x00000100 145 #define HDSPM_TCO1_set_drop_frame_flag 0x00000200 146 #define HDSPM_TCO1_LTC_Format_LSB 0x00000400 147 #define HDSPM_TCO1_LTC_Format_MSB 0x00000800 148 149 #define HDSPM_TCO2_TC_run 0x00010000 150 #define HDSPM_TCO2_WCK_IO_ratio_LSB 0x00020000 151 #define HDSPM_TCO2_WCK_IO_ratio_MSB 0x00040000 152 #define HDSPM_TCO2_set_num_drop_frames_LSB 0x00080000 153 #define HDSPM_TCO2_set_num_drop_frames_MSB 0x00100000 154 #define HDSPM_TCO2_set_jam_sync 0x00200000 155 #define HDSPM_TCO2_set_flywheel 0x00400000 156 157 #define HDSPM_TCO2_set_01_4 0x01000000 158 #define HDSPM_TCO2_set_pull_down 0x02000000 159 #define HDSPM_TCO2_set_pull_up 0x04000000 160 #define HDSPM_TCO2_set_freq 0x08000000 161 #define HDSPM_TCO2_set_term_75R 0x10000000 162 #define HDSPM_TCO2_set_input_LSB 0x20000000 163 #define HDSPM_TCO2_set_input_MSB 0x40000000 164 #define HDSPM_TCO2_set_freq_from_app 0x80000000 165 166 167 #define HDSPM_midiDataOut0 352 168 #define HDSPM_midiDataOut1 356 169 #define HDSPM_midiDataOut2 368 170 171 #define HDSPM_midiDataIn0 360 172 #define HDSPM_midiDataIn1 364 173 #define HDSPM_midiDataIn2 372 174 #define HDSPM_midiDataIn3 376 175 176 /* status is data bytes in MIDI-FIFO (0-128) */ 177 #define HDSPM_midiStatusOut0 384 178 #define HDSPM_midiStatusOut1 388 179 #define HDSPM_midiStatusOut2 400 180 181 #define HDSPM_midiStatusIn0 392 182 #define HDSPM_midiStatusIn1 396 183 #define HDSPM_midiStatusIn2 404 184 #define HDSPM_midiStatusIn3 408 185 186 187 /* the meters are regular i/o-mapped registers, but offset 188 considerably from the rest. the peak registers are reset 189 when read; the least-significant 4 bits are full-scale counters; 190 the actual peak value is in the most-significant 24 bits. 191 */ 192 193 #define HDSPM_MADI_INPUT_PEAK 4096 194 #define HDSPM_MADI_PLAYBACK_PEAK 4352 195 #define HDSPM_MADI_OUTPUT_PEAK 4608 196 197 #define HDSPM_MADI_INPUT_RMS_L 6144 198 #define HDSPM_MADI_PLAYBACK_RMS_L 6400 199 #define HDSPM_MADI_OUTPUT_RMS_L 6656 200 201 #define HDSPM_MADI_INPUT_RMS_H 7168 202 #define HDSPM_MADI_PLAYBACK_RMS_H 7424 203 #define HDSPM_MADI_OUTPUT_RMS_H 7680 204 205 /* --- Control Register bits --------- */ 206 #define HDSPM_Start (1<<0) /* start engine */ 207 208 #define HDSPM_Latency0 (1<<1) /* buffer size = 2^n */ 209 #define HDSPM_Latency1 (1<<2) /* where n is defined */ 210 #define HDSPM_Latency2 (1<<3) /* by Latency{2,1,0} */ 211 212 #define HDSPM_ClockModeMaster (1<<4) /* 1=Master, 0=Autosync */ 213 #define HDSPM_c0Master 0x1 /* Master clock bit in settings 214 register [RayDAT, AIO] */ 215 216 #define HDSPM_AudioInterruptEnable (1<<5) /* what do you think ? */ 217 218 #define HDSPM_Frequency0 (1<<6) /* 0=44.1kHz/88.2kHz 1=48kHz/96kHz */ 219 #define HDSPM_Frequency1 (1<<7) /* 0=32kHz/64kHz */ 220 #define HDSPM_DoubleSpeed (1<<8) /* 0=normal speed, 1=double speed */ 221 #define HDSPM_QuadSpeed (1<<31) /* quad speed bit */ 222 223 #define HDSPM_Professional (1<<9) /* Professional */ /* AES32 ONLY */ 224 #define HDSPM_TX_64ch (1<<10) /* Output 64channel MODE=1, 225 56channelMODE=0 */ /* MADI ONLY*/ 226 #define HDSPM_Emphasis (1<<10) /* Emphasis */ /* AES32 ONLY */ 227 228 #define HDSPM_AutoInp (1<<11) /* Auto Input (takeover) == Safe Mode, 229 0=off, 1=on */ /* MADI ONLY */ 230 #define HDSPM_Dolby (1<<11) /* Dolby = "NonAudio" ?? */ /* AES32 ONLY */ 231 232 #define HDSPM_InputSelect0 (1<<14) /* Input select 0= optical, 1=coax 233 * -- MADI ONLY 234 */ 235 #define HDSPM_InputSelect1 (1<<15) /* should be 0 */ 236 237 #define HDSPM_SyncRef2 (1<<13) 238 #define HDSPM_SyncRef3 (1<<25) 239 240 #define HDSPM_SMUX (1<<18) /* Frame ??? */ /* MADI ONY */ 241 #define HDSPM_clr_tms (1<<19) /* clear track marker, do not use 242 AES additional bits in 243 lower 5 Audiodatabits ??? */ 244 #define HDSPM_taxi_reset (1<<20) /* ??? */ /* MADI ONLY ? */ 245 #define HDSPM_WCK48 (1<<20) /* Frame ??? = HDSPM_SMUX */ /* AES32 ONLY */ 246 247 #define HDSPM_Midi0InterruptEnable 0x0400000 248 #define HDSPM_Midi1InterruptEnable 0x0800000 249 #define HDSPM_Midi2InterruptEnable 0x0200000 250 #define HDSPM_Midi3InterruptEnable 0x4000000 251 252 #define HDSPM_LineOut (1<<24) /* Analog Out on channel 63/64 on=1, mute=0 */ 253 #define HDSPe_FLOAT_FORMAT 0x2000000 254 255 #define HDSPM_DS_DoubleWire (1<<26) /* AES32 ONLY */ 256 #define HDSPM_QS_DoubleWire (1<<27) /* AES32 ONLY */ 257 #define HDSPM_QS_QuadWire (1<<28) /* AES32 ONLY */ 258 259 #define HDSPM_wclk_sel (1<<30) 260 261 /* --- bit helper defines */ 262 #define HDSPM_LatencyMask (HDSPM_Latency0|HDSPM_Latency1|HDSPM_Latency2) 263 #define HDSPM_FrequencyMask (HDSPM_Frequency0|HDSPM_Frequency1|\ 264 HDSPM_DoubleSpeed|HDSPM_QuadSpeed) 265 #define HDSPM_InputMask (HDSPM_InputSelect0|HDSPM_InputSelect1) 266 #define HDSPM_InputOptical 0 267 #define HDSPM_InputCoaxial (HDSPM_InputSelect0) 268 #define HDSPM_SyncRefMask (HDSPM_SyncRef0|HDSPM_SyncRef1|\ 269 HDSPM_SyncRef2|HDSPM_SyncRef3) 270 271 #define HDSPM_c0_SyncRef0 0x2 272 #define HDSPM_c0_SyncRef1 0x4 273 #define HDSPM_c0_SyncRef2 0x8 274 #define HDSPM_c0_SyncRef3 0x10 275 #define HDSPM_c0_SyncRefMask (HDSPM_c0_SyncRef0 | HDSPM_c0_SyncRef1 |\ 276 HDSPM_c0_SyncRef2 | HDSPM_c0_SyncRef3) 277 278 #define HDSPM_SYNC_FROM_WORD 0 /* Preferred sync reference */ 279 #define HDSPM_SYNC_FROM_MADI 1 /* choices - used by "pref_sync_ref" */ 280 #define HDSPM_SYNC_FROM_TCO 2 281 #define HDSPM_SYNC_FROM_SYNC_IN 3 282 283 #define HDSPM_Frequency32KHz HDSPM_Frequency0 284 #define HDSPM_Frequency44_1KHz HDSPM_Frequency1 285 #define HDSPM_Frequency48KHz (HDSPM_Frequency1|HDSPM_Frequency0) 286 #define HDSPM_Frequency64KHz (HDSPM_DoubleSpeed|HDSPM_Frequency0) 287 #define HDSPM_Frequency88_2KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1) 288 #define HDSPM_Frequency96KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1|\ 289 HDSPM_Frequency0) 290 #define HDSPM_Frequency128KHz (HDSPM_QuadSpeed|HDSPM_Frequency0) 291 #define HDSPM_Frequency176_4KHz (HDSPM_QuadSpeed|HDSPM_Frequency1) 292 #define HDSPM_Frequency192KHz (HDSPM_QuadSpeed|HDSPM_Frequency1|\ 293 HDSPM_Frequency0) 294 295 296 /* Synccheck Status */ 297 #define HDSPM_SYNC_CHECK_NO_LOCK 0 298 #define HDSPM_SYNC_CHECK_LOCK 1 299 #define HDSPM_SYNC_CHECK_SYNC 2 300 301 /* AutoSync References - used by "autosync_ref" control switch */ 302 #define HDSPM_AUTOSYNC_FROM_WORD 0 303 #define HDSPM_AUTOSYNC_FROM_MADI 1 304 #define HDSPM_AUTOSYNC_FROM_TCO 2 305 #define HDSPM_AUTOSYNC_FROM_SYNC_IN 3 306 #define HDSPM_AUTOSYNC_FROM_NONE 4 307 308 /* Possible sources of MADI input */ 309 #define HDSPM_OPTICAL 0 /* optical */ 310 #define HDSPM_COAXIAL 1 /* BNC */ 311 312 #define hdspm_encode_latency(x) (((x)<<1) & HDSPM_LatencyMask) 313 #define hdspm_decode_latency(x) ((((x) & HDSPM_LatencyMask)>>1)) 314 315 #define hdspm_encode_in(x) (((x)&0x3)<<14) 316 #define hdspm_decode_in(x) (((x)>>14)&0x3) 317 318 /* --- control2 register bits --- */ 319 #define HDSPM_TMS (1<<0) 320 #define HDSPM_TCK (1<<1) 321 #define HDSPM_TDI (1<<2) 322 #define HDSPM_JTAG (1<<3) 323 #define HDSPM_PWDN (1<<4) 324 #define HDSPM_PROGRAM (1<<5) 325 #define HDSPM_CONFIG_MODE_0 (1<<6) 326 #define HDSPM_CONFIG_MODE_1 (1<<7) 327 /*#define HDSPM_VERSION_BIT (1<<8) not defined any more*/ 328 #define HDSPM_BIGENDIAN_MODE (1<<9) 329 #define HDSPM_RD_MULTIPLE (1<<10) 330 331 /* --- Status Register bits --- */ /* MADI ONLY */ /* Bits defined here and 332 that do not conflict with specific bits for AES32 seem to be valid also 333 for the AES32 334 */ 335 #define HDSPM_audioIRQPending (1<<0) /* IRQ is high and pending */ 336 #define HDSPM_RX_64ch (1<<1) /* Input 64chan. MODE=1, 56chn MODE=0 */ 337 #define HDSPM_AB_int (1<<2) /* InputChannel Opt=0, Coax=1 338 * (like inp0) 339 */ 340 341 #define HDSPM_madiLock (1<<3) /* MADI Locked =1, no=0 */ 342 #define HDSPM_madiSync (1<<18) /* MADI is in sync */ 343 344 #define HDSPM_tcoLock 0x00000020 /* Optional TCO locked status FOR HDSPe MADI! */ 345 #define HDSPM_tcoSync 0x10000000 /* Optional TCO sync status */ 346 347 #define HDSPM_syncInLock 0x00010000 /* Sync In lock status FOR HDSPe MADI! */ 348 #define HDSPM_syncInSync 0x00020000 /* Sync In sync status FOR HDSPe MADI! */ 349 350 #define HDSPM_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */ 351 /* since 64byte accurate, last 6 bits are not used */ 352 353 354 355 #define HDSPM_DoubleSpeedStatus (1<<19) /* (input) card in double speed */ 356 357 #define HDSPM_madiFreq0 (1<<22) /* system freq 0=error */ 358 #define HDSPM_madiFreq1 (1<<23) /* 1=32, 2=44.1 3=48 */ 359 #define HDSPM_madiFreq2 (1<<24) /* 4=64, 5=88.2 6=96 */ 360 #define HDSPM_madiFreq3 (1<<25) /* 7=128, 8=176.4 9=192 */ 361 362 #define HDSPM_BufferID (1<<26) /* (Double)Buffer ID toggles with 363 * Interrupt 364 */ 365 #define HDSPM_tco_detect 0x08000000 366 #define HDSPM_tco_lock 0x20000000 367 368 #define HDSPM_s2_tco_detect 0x00000040 369 #define HDSPM_s2_AEBO_D 0x00000080 370 #define HDSPM_s2_AEBI_D 0x00000100 371 372 373 #define HDSPM_midi0IRQPending 0x40000000 374 #define HDSPM_midi1IRQPending 0x80000000 375 #define HDSPM_midi2IRQPending 0x20000000 376 #define HDSPM_midi2IRQPendingAES 0x00000020 377 #define HDSPM_midi3IRQPending 0x00200000 378 379 /* --- status bit helpers */ 380 #define HDSPM_madiFreqMask (HDSPM_madiFreq0|HDSPM_madiFreq1|\ 381 HDSPM_madiFreq2|HDSPM_madiFreq3) 382 #define HDSPM_madiFreq32 (HDSPM_madiFreq0) 383 #define HDSPM_madiFreq44_1 (HDSPM_madiFreq1) 384 #define HDSPM_madiFreq48 (HDSPM_madiFreq0|HDSPM_madiFreq1) 385 #define HDSPM_madiFreq64 (HDSPM_madiFreq2) 386 #define HDSPM_madiFreq88_2 (HDSPM_madiFreq0|HDSPM_madiFreq2) 387 #define HDSPM_madiFreq96 (HDSPM_madiFreq1|HDSPM_madiFreq2) 388 #define HDSPM_madiFreq128 (HDSPM_madiFreq0|HDSPM_madiFreq1|HDSPM_madiFreq2) 389 #define HDSPM_madiFreq176_4 (HDSPM_madiFreq3) 390 #define HDSPM_madiFreq192 (HDSPM_madiFreq3|HDSPM_madiFreq0) 391 392 /* Status2 Register bits */ /* MADI ONLY */ 393 394 #define HDSPM_version0 (1<<0) /* not really defined but I guess */ 395 #define HDSPM_version1 (1<<1) /* in former cards it was ??? */ 396 #define HDSPM_version2 (1<<2) 397 398 #define HDSPM_wcLock (1<<3) /* Wordclock is detected and locked */ 399 #define HDSPM_wcSync (1<<4) /* Wordclock is in sync with systemclock */ 400 401 #define HDSPM_wc_freq0 (1<<5) /* input freq detected via autosync */ 402 #define HDSPM_wc_freq1 (1<<6) /* 001=32, 010==44.1, 011=48, */ 403 #define HDSPM_wc_freq2 (1<<7) /* 100=64, 101=88.2, 110=96, */ 404 /* missing Bit for 111=128, 1000=176.4, 1001=192 */ 405 406 #define HDSPM_SyncRef0 0x10000 /* Sync Reference */ 407 #define HDSPM_SyncRef1 0x20000 408 409 #define HDSPM_SelSyncRef0 (1<<8) /* AutoSync Source */ 410 #define HDSPM_SelSyncRef1 (1<<9) /* 000=word, 001=MADI, */ 411 #define HDSPM_SelSyncRef2 (1<<10) /* 111=no valid signal */ 412 413 #define HDSPM_wc_valid (HDSPM_wcLock|HDSPM_wcSync) 414 415 #define HDSPM_wcFreqMask (HDSPM_wc_freq0|HDSPM_wc_freq1|HDSPM_wc_freq2) 416 #define HDSPM_wcFreq32 (HDSPM_wc_freq0) 417 #define HDSPM_wcFreq44_1 (HDSPM_wc_freq1) 418 #define HDSPM_wcFreq48 (HDSPM_wc_freq0|HDSPM_wc_freq1) 419 #define HDSPM_wcFreq64 (HDSPM_wc_freq2) 420 #define HDSPM_wcFreq88_2 (HDSPM_wc_freq0|HDSPM_wc_freq2) 421 #define HDSPM_wcFreq96 (HDSPM_wc_freq1|HDSPM_wc_freq2) 422 423 #define HDSPM_status1_F_0 0x0400000 424 #define HDSPM_status1_F_1 0x0800000 425 #define HDSPM_status1_F_2 0x1000000 426 #define HDSPM_status1_F_3 0x2000000 427 #define HDSPM_status1_freqMask (HDSPM_status1_F_0|HDSPM_status1_F_1|HDSPM_status1_F_2|HDSPM_status1_F_3) 428 429 430 #define HDSPM_SelSyncRefMask (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\ 431 HDSPM_SelSyncRef2) 432 #define HDSPM_SelSyncRef_WORD 0 433 #define HDSPM_SelSyncRef_MADI (HDSPM_SelSyncRef0) 434 #define HDSPM_SelSyncRef_TCO (HDSPM_SelSyncRef1) 435 #define HDSPM_SelSyncRef_SyncIn (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1) 436 #define HDSPM_SelSyncRef_NVALID (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\ 437 HDSPM_SelSyncRef2) 438 439 /* 440 For AES32, bits for status, status2 and timecode are different 441 */ 442 /* status */ 443 #define HDSPM_AES32_wcLock 0x0200000 444 #define HDSPM_AES32_wcFreq_bit 22 445 /* (status >> HDSPM_AES32_wcFreq_bit) & 0xF gives WC frequency (cf function 446 HDSPM_bit2freq */ 447 #define HDSPM_AES32_syncref_bit 16 448 /* (status >> HDSPM_AES32_syncref_bit) & 0xF gives sync source */ 449 450 #define HDSPM_AES32_AUTOSYNC_FROM_WORD 0 451 #define HDSPM_AES32_AUTOSYNC_FROM_AES1 1 452 #define HDSPM_AES32_AUTOSYNC_FROM_AES2 2 453 #define HDSPM_AES32_AUTOSYNC_FROM_AES3 3 454 #define HDSPM_AES32_AUTOSYNC_FROM_AES4 4 455 #define HDSPM_AES32_AUTOSYNC_FROM_AES5 5 456 #define HDSPM_AES32_AUTOSYNC_FROM_AES6 6 457 #define HDSPM_AES32_AUTOSYNC_FROM_AES7 7 458 #define HDSPM_AES32_AUTOSYNC_FROM_AES8 8 459 #define HDSPM_AES32_AUTOSYNC_FROM_NONE 9 460 461 /* status2 */ 462 /* HDSPM_LockAES_bit is given by HDSPM_LockAES >> (AES# - 1) */ 463 #define HDSPM_LockAES 0x80 464 #define HDSPM_LockAES1 0x80 465 #define HDSPM_LockAES2 0x40 466 #define HDSPM_LockAES3 0x20 467 #define HDSPM_LockAES4 0x10 468 #define HDSPM_LockAES5 0x8 469 #define HDSPM_LockAES6 0x4 470 #define HDSPM_LockAES7 0x2 471 #define HDSPM_LockAES8 0x1 472 /* 473 Timecode 474 After windows driver sources, bits 4*i to 4*i+3 give the input frequency on 475 AES i+1 476 bits 3210 477 0001 32kHz 478 0010 44.1kHz 479 0011 48kHz 480 0100 64kHz 481 0101 88.2kHz 482 0110 96kHz 483 0111 128kHz 484 1000 176.4kHz 485 1001 192kHz 486 NB: Timecode register doesn't seem to work on AES32 card revision 230 487 */ 488 489 /* Mixer Values */ 490 #define UNITY_GAIN 32768 /* = 65536/2 */ 491 #define MINUS_INFINITY_GAIN 0 492 493 /* Number of channels for different Speed Modes */ 494 #define MADI_SS_CHANNELS 64 495 #define MADI_DS_CHANNELS 32 496 #define MADI_QS_CHANNELS 16 497 498 #define RAYDAT_SS_CHANNELS 36 499 #define RAYDAT_DS_CHANNELS 20 500 #define RAYDAT_QS_CHANNELS 12 501 502 #define AIO_IN_SS_CHANNELS 14 503 #define AIO_IN_DS_CHANNELS 10 504 #define AIO_IN_QS_CHANNELS 8 505 #define AIO_OUT_SS_CHANNELS 16 506 #define AIO_OUT_DS_CHANNELS 12 507 #define AIO_OUT_QS_CHANNELS 10 508 509 #define AES32_CHANNELS 16 510 511 /* the size of a substream (1 mono data stream) */ 512 #define HDSPM_CHANNEL_BUFFER_SAMPLES (16*1024) 513 #define HDSPM_CHANNEL_BUFFER_BYTES (4*HDSPM_CHANNEL_BUFFER_SAMPLES) 514 515 /* the size of the area we need to allocate for DMA transfers. the 516 size is the same regardless of the number of channels, and 517 also the latency to use. 518 for one direction !!! 519 */ 520 #define HDSPM_DMA_AREA_BYTES (HDSPM_MAX_CHANNELS * HDSPM_CHANNEL_BUFFER_BYTES) 521 #define HDSPM_DMA_AREA_KILOBYTES (HDSPM_DMA_AREA_BYTES/1024) 522 523 /* revisions >= 230 indicate AES32 card */ 524 #define HDSPM_MADI_ANCIENT_REV 204 525 #define HDSPM_MADI_OLD_REV 207 526 #define HDSPM_MADI_REV 210 527 #define HDSPM_RAYDAT_REV 211 528 #define HDSPM_AIO_REV 212 529 #define HDSPM_MADIFACE_REV 213 530 #define HDSPM_AES_REV 240 531 #define HDSPM_AES32_REV 234 532 #define HDSPM_AES32_OLD_REV 233 533 534 /* speed factor modes */ 535 #define HDSPM_SPEED_SINGLE 0 536 #define HDSPM_SPEED_DOUBLE 1 537 #define HDSPM_SPEED_QUAD 2 538 539 /* names for speed modes */ 540 static char *hdspm_speed_names[] = { "single", "double", "quad" }; 541 542 static char *texts_autosync_aes_tco[] = { "Word Clock", 543 "AES1", "AES2", "AES3", "AES4", 544 "AES5", "AES6", "AES7", "AES8", 545 "TCO" }; 546 static char *texts_autosync_aes[] = { "Word Clock", 547 "AES1", "AES2", "AES3", "AES4", 548 "AES5", "AES6", "AES7", "AES8" }; 549 static char *texts_autosync_madi_tco[] = { "Word Clock", 550 "MADI", "TCO", "Sync In" }; 551 static char *texts_autosync_madi[] = { "Word Clock", 552 "MADI", "Sync In" }; 553 554 static char *texts_autosync_raydat_tco[] = { 555 "Word Clock", 556 "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4", 557 "AES", "SPDIF", "TCO", "Sync In" 558 }; 559 static char *texts_autosync_raydat[] = { 560 "Word Clock", 561 "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4", 562 "AES", "SPDIF", "Sync In" 563 }; 564 static char *texts_autosync_aio_tco[] = { 565 "Word Clock", 566 "ADAT", "AES", "SPDIF", "TCO", "Sync In" 567 }; 568 static char *texts_autosync_aio[] = { "Word Clock", 569 "ADAT", "AES", "SPDIF", "Sync In" }; 570 571 static char *texts_freq[] = { 572 "No Lock", 573 "32 kHz", 574 "44.1 kHz", 575 "48 kHz", 576 "64 kHz", 577 "88.2 kHz", 578 "96 kHz", 579 "128 kHz", 580 "176.4 kHz", 581 "192 kHz" 582 }; 583 584 static char *texts_ports_madi[] = { 585 "MADI.1", "MADI.2", "MADI.3", "MADI.4", "MADI.5", "MADI.6", 586 "MADI.7", "MADI.8", "MADI.9", "MADI.10", "MADI.11", "MADI.12", 587 "MADI.13", "MADI.14", "MADI.15", "MADI.16", "MADI.17", "MADI.18", 588 "MADI.19", "MADI.20", "MADI.21", "MADI.22", "MADI.23", "MADI.24", 589 "MADI.25", "MADI.26", "MADI.27", "MADI.28", "MADI.29", "MADI.30", 590 "MADI.31", "MADI.32", "MADI.33", "MADI.34", "MADI.35", "MADI.36", 591 "MADI.37", "MADI.38", "MADI.39", "MADI.40", "MADI.41", "MADI.42", 592 "MADI.43", "MADI.44", "MADI.45", "MADI.46", "MADI.47", "MADI.48", 593 "MADI.49", "MADI.50", "MADI.51", "MADI.52", "MADI.53", "MADI.54", 594 "MADI.55", "MADI.56", "MADI.57", "MADI.58", "MADI.59", "MADI.60", 595 "MADI.61", "MADI.62", "MADI.63", "MADI.64", 596 }; 597 598 599 static char *texts_ports_raydat_ss[] = { 600 "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4", "ADAT1.5", "ADAT1.6", 601 "ADAT1.7", "ADAT1.8", "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4", 602 "ADAT2.5", "ADAT2.6", "ADAT2.7", "ADAT2.8", "ADAT3.1", "ADAT3.2", 603 "ADAT3.3", "ADAT3.4", "ADAT3.5", "ADAT3.6", "ADAT3.7", "ADAT3.8", 604 "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4", "ADAT4.5", "ADAT4.6", 605 "ADAT4.7", "ADAT4.8", 606 "AES.L", "AES.R", 607 "SPDIF.L", "SPDIF.R" 608 }; 609 610 static char *texts_ports_raydat_ds[] = { 611 "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4", 612 "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4", 613 "ADAT3.1", "ADAT3.2", "ADAT3.3", "ADAT3.4", 614 "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4", 615 "AES.L", "AES.R", 616 "SPDIF.L", "SPDIF.R" 617 }; 618 619 static char *texts_ports_raydat_qs[] = { 620 "ADAT1.1", "ADAT1.2", 621 "ADAT2.1", "ADAT2.2", 622 "ADAT3.1", "ADAT3.2", 623 "ADAT4.1", "ADAT4.2", 624 "AES.L", "AES.R", 625 "SPDIF.L", "SPDIF.R" 626 }; 627 628 629 static char *texts_ports_aio_in_ss[] = { 630 "Analogue.L", "Analogue.R", 631 "AES.L", "AES.R", 632 "SPDIF.L", "SPDIF.R", 633 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6", 634 "ADAT.7", "ADAT.8" 635 }; 636 637 static char *texts_ports_aio_out_ss[] = { 638 "Analogue.L", "Analogue.R", 639 "AES.L", "AES.R", 640 "SPDIF.L", "SPDIF.R", 641 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6", 642 "ADAT.7", "ADAT.8", 643 "Phone.L", "Phone.R" 644 }; 645 646 static char *texts_ports_aio_in_ds[] = { 647 "Analogue.L", "Analogue.R", 648 "AES.L", "AES.R", 649 "SPDIF.L", "SPDIF.R", 650 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4" 651 }; 652 653 static char *texts_ports_aio_out_ds[] = { 654 "Analogue.L", "Analogue.R", 655 "AES.L", "AES.R", 656 "SPDIF.L", "SPDIF.R", 657 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", 658 "Phone.L", "Phone.R" 659 }; 660 661 static char *texts_ports_aio_in_qs[] = { 662 "Analogue.L", "Analogue.R", 663 "AES.L", "AES.R", 664 "SPDIF.L", "SPDIF.R", 665 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4" 666 }; 667 668 static char *texts_ports_aio_out_qs[] = { 669 "Analogue.L", "Analogue.R", 670 "AES.L", "AES.R", 671 "SPDIF.L", "SPDIF.R", 672 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", 673 "Phone.L", "Phone.R" 674 }; 675 676 static char *texts_ports_aes32[] = { 677 "AES.1", "AES.2", "AES.3", "AES.4", "AES.5", "AES.6", "AES.7", 678 "AES.8", "AES.9.", "AES.10", "AES.11", "AES.12", "AES.13", "AES.14", 679 "AES.15", "AES.16" 680 }; 681 682 /* These tables map the ALSA channels 1..N to the channels that we 683 need to use in order to find the relevant channel buffer. RME 684 refers to this kind of mapping as between "the ADAT channel and 685 the DMA channel." We index it using the logical audio channel, 686 and the value is the DMA channel (i.e. channel buffer number) 687 where the data for that channel can be read/written from/to. 688 */ 689 690 static char channel_map_unity_ss[HDSPM_MAX_CHANNELS] = { 691 0, 1, 2, 3, 4, 5, 6, 7, 692 8, 9, 10, 11, 12, 13, 14, 15, 693 16, 17, 18, 19, 20, 21, 22, 23, 694 24, 25, 26, 27, 28, 29, 30, 31, 695 32, 33, 34, 35, 36, 37, 38, 39, 696 40, 41, 42, 43, 44, 45, 46, 47, 697 48, 49, 50, 51, 52, 53, 54, 55, 698 56, 57, 58, 59, 60, 61, 62, 63 699 }; 700 701 static char channel_map_raydat_ss[HDSPM_MAX_CHANNELS] = { 702 4, 5, 6, 7, 8, 9, 10, 11, /* ADAT 1 */ 703 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT 2 */ 704 20, 21, 22, 23, 24, 25, 26, 27, /* ADAT 3 */ 705 28, 29, 30, 31, 32, 33, 34, 35, /* ADAT 4 */ 706 0, 1, /* AES */ 707 2, 3, /* SPDIF */ 708 -1, -1, -1, -1, 709 -1, -1, -1, -1, -1, -1, -1, -1, 710 -1, -1, -1, -1, -1, -1, -1, -1, 711 -1, -1, -1, -1, -1, -1, -1, -1, 712 }; 713 714 static char channel_map_raydat_ds[HDSPM_MAX_CHANNELS] = { 715 4, 5, 6, 7, /* ADAT 1 */ 716 8, 9, 10, 11, /* ADAT 2 */ 717 12, 13, 14, 15, /* ADAT 3 */ 718 16, 17, 18, 19, /* ADAT 4 */ 719 0, 1, /* AES */ 720 2, 3, /* SPDIF */ 721 -1, -1, -1, -1, 722 -1, -1, -1, -1, -1, -1, -1, -1, 723 -1, -1, -1, -1, -1, -1, -1, -1, 724 -1, -1, -1, -1, -1, -1, -1, -1, 725 -1, -1, -1, -1, -1, -1, -1, -1, 726 -1, -1, -1, -1, -1, -1, -1, -1, 727 }; 728 729 static char channel_map_raydat_qs[HDSPM_MAX_CHANNELS] = { 730 4, 5, /* ADAT 1 */ 731 6, 7, /* ADAT 2 */ 732 8, 9, /* ADAT 3 */ 733 10, 11, /* ADAT 4 */ 734 0, 1, /* AES */ 735 2, 3, /* SPDIF */ 736 -1, -1, -1, -1, 737 -1, -1, -1, -1, -1, -1, -1, -1, 738 -1, -1, -1, -1, -1, -1, -1, -1, 739 -1, -1, -1, -1, -1, -1, -1, -1, 740 -1, -1, -1, -1, -1, -1, -1, -1, 741 -1, -1, -1, -1, -1, -1, -1, -1, 742 -1, -1, -1, -1, -1, -1, -1, -1, 743 }; 744 745 static char channel_map_aio_in_ss[HDSPM_MAX_CHANNELS] = { 746 0, 1, /* line in */ 747 8, 9, /* aes in, */ 748 10, 11, /* spdif in */ 749 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT in */ 750 -1, -1, 751 -1, -1, -1, -1, -1, -1, -1, -1, 752 -1, -1, -1, -1, -1, -1, -1, -1, 753 -1, -1, -1, -1, -1, -1, -1, -1, 754 -1, -1, -1, -1, -1, -1, -1, -1, 755 -1, -1, -1, -1, -1, -1, -1, -1, 756 -1, -1, -1, -1, -1, -1, -1, -1, 757 }; 758 759 static char channel_map_aio_out_ss[HDSPM_MAX_CHANNELS] = { 760 0, 1, /* line out */ 761 8, 9, /* aes out */ 762 10, 11, /* spdif out */ 763 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT out */ 764 6, 7, /* phone out */ 765 -1, -1, -1, -1, -1, -1, -1, -1, 766 -1, -1, -1, -1, -1, -1, -1, -1, 767 -1, -1, -1, -1, -1, -1, -1, -1, 768 -1, -1, -1, -1, -1, -1, -1, -1, 769 -1, -1, -1, -1, -1, -1, -1, -1, 770 -1, -1, -1, -1, -1, -1, -1, -1, 771 }; 772 773 static char channel_map_aio_in_ds[HDSPM_MAX_CHANNELS] = { 774 0, 1, /* line in */ 775 8, 9, /* aes in */ 776 10, 11, /* spdif in */ 777 12, 14, 16, 18, /* adat in */ 778 -1, -1, -1, -1, -1, -1, 779 -1, -1, -1, -1, -1, -1, -1, -1, 780 -1, -1, -1, -1, -1, -1, -1, -1, 781 -1, -1, -1, -1, -1, -1, -1, -1, 782 -1, -1, -1, -1, -1, -1, -1, -1, 783 -1, -1, -1, -1, -1, -1, -1, -1, 784 -1, -1, -1, -1, -1, -1, -1, -1 785 }; 786 787 static char channel_map_aio_out_ds[HDSPM_MAX_CHANNELS] = { 788 0, 1, /* line out */ 789 8, 9, /* aes out */ 790 10, 11, /* spdif out */ 791 12, 14, 16, 18, /* adat out */ 792 6, 7, /* phone out */ 793 -1, -1, -1, -1, 794 -1, -1, -1, -1, -1, -1, -1, -1, 795 -1, -1, -1, -1, -1, -1, -1, -1, 796 -1, -1, -1, -1, -1, -1, -1, -1, 797 -1, -1, -1, -1, -1, -1, -1, -1, 798 -1, -1, -1, -1, -1, -1, -1, -1, 799 -1, -1, -1, -1, -1, -1, -1, -1 800 }; 801 802 static char channel_map_aio_in_qs[HDSPM_MAX_CHANNELS] = { 803 0, 1, /* line in */ 804 8, 9, /* aes in */ 805 10, 11, /* spdif in */ 806 12, 16, /* adat in */ 807 -1, -1, -1, -1, -1, -1, -1, -1, 808 -1, -1, -1, -1, -1, -1, -1, -1, 809 -1, -1, -1, -1, -1, -1, -1, -1, 810 -1, -1, -1, -1, -1, -1, -1, -1, 811 -1, -1, -1, -1, -1, -1, -1, -1, 812 -1, -1, -1, -1, -1, -1, -1, -1, 813 -1, -1, -1, -1, -1, -1, -1, -1 814 }; 815 816 static char channel_map_aio_out_qs[HDSPM_MAX_CHANNELS] = { 817 0, 1, /* line out */ 818 8, 9, /* aes out */ 819 10, 11, /* spdif out */ 820 12, 16, /* adat out */ 821 6, 7, /* phone out */ 822 -1, -1, -1, -1, -1, -1, 823 -1, -1, -1, -1, -1, -1, -1, -1, 824 -1, -1, -1, -1, -1, -1, -1, -1, 825 -1, -1, -1, -1, -1, -1, -1, -1, 826 -1, -1, -1, -1, -1, -1, -1, -1, 827 -1, -1, -1, -1, -1, -1, -1, -1, 828 -1, -1, -1, -1, -1, -1, -1, -1 829 }; 830 831 static char channel_map_aes32[HDSPM_MAX_CHANNELS] = { 832 0, 1, 2, 3, 4, 5, 6, 7, 833 8, 9, 10, 11, 12, 13, 14, 15, 834 -1, -1, -1, -1, -1, -1, -1, -1, 835 -1, -1, -1, -1, -1, -1, -1, -1, 836 -1, -1, -1, -1, -1, -1, -1, -1, 837 -1, -1, -1, -1, -1, -1, -1, -1, 838 -1, -1, -1, -1, -1, -1, -1, -1, 839 -1, -1, -1, -1, -1, -1, -1, -1 840 }; 841 842 struct hdspm_midi { 843 struct hdspm *hdspm; 844 int id; 845 struct snd_rawmidi *rmidi; 846 struct snd_rawmidi_substream *input; 847 struct snd_rawmidi_substream *output; 848 char istimer; /* timer in use */ 849 struct timer_list timer; 850 spinlock_t lock; 851 int pending; 852 int dataIn; 853 int statusIn; 854 int dataOut; 855 int statusOut; 856 int ie; 857 int irq; 858 }; 859 860 struct hdspm_tco { 861 int input; 862 int framerate; 863 int wordclock; 864 int samplerate; 865 int pull; 866 int term; /* 0 = off, 1 = on */ 867 }; 868 869 struct hdspm { 870 spinlock_t lock; 871 /* only one playback and/or capture stream */ 872 struct snd_pcm_substream *capture_substream; 873 struct snd_pcm_substream *playback_substream; 874 875 char *card_name; /* for procinfo */ 876 unsigned short firmware_rev; /* dont know if relevant (yes if AES32)*/ 877 878 uint8_t io_type; 879 880 int monitor_outs; /* set up monitoring outs init flag */ 881 882 u32 control_register; /* cached value */ 883 u32 control2_register; /* cached value */ 884 u32 settings_register; 885 886 struct hdspm_midi midi[4]; 887 struct tasklet_struct midi_tasklet; 888 889 size_t period_bytes; 890 unsigned char ss_in_channels; 891 unsigned char ds_in_channels; 892 unsigned char qs_in_channels; 893 unsigned char ss_out_channels; 894 unsigned char ds_out_channels; 895 unsigned char qs_out_channels; 896 897 unsigned char max_channels_in; 898 unsigned char max_channels_out; 899 900 signed char *channel_map_in; 901 signed char *channel_map_out; 902 903 signed char *channel_map_in_ss, *channel_map_in_ds, *channel_map_in_qs; 904 signed char *channel_map_out_ss, *channel_map_out_ds, *channel_map_out_qs; 905 906 char **port_names_in; 907 char **port_names_out; 908 909 char **port_names_in_ss, **port_names_in_ds, **port_names_in_qs; 910 char **port_names_out_ss, **port_names_out_ds, **port_names_out_qs; 911 912 unsigned char *playback_buffer; /* suitably aligned address */ 913 unsigned char *capture_buffer; /* suitably aligned address */ 914 915 pid_t capture_pid; /* process id which uses capture */ 916 pid_t playback_pid; /* process id which uses capture */ 917 int running; /* running status */ 918 919 int last_external_sample_rate; /* samplerate mystic ... */ 920 int last_internal_sample_rate; 921 int system_sample_rate; 922 923 int dev; /* Hardware vars... */ 924 int irq; 925 unsigned long port; 926 void __iomem *iobase; 927 928 int irq_count; /* for debug */ 929 int midiPorts; 930 931 struct snd_card *card; /* one card */ 932 struct snd_pcm *pcm; /* has one pcm */ 933 struct snd_hwdep *hwdep; /* and a hwdep for additional ioctl */ 934 struct pci_dev *pci; /* and an pci info */ 935 936 /* Mixer vars */ 937 /* fast alsa mixer */ 938 struct snd_kcontrol *playback_mixer_ctls[HDSPM_MAX_CHANNELS]; 939 /* but input to much, so not used */ 940 struct snd_kcontrol *input_mixer_ctls[HDSPM_MAX_CHANNELS]; 941 /* full mixer accessible over mixer ioctl or hwdep-device */ 942 struct hdspm_mixer *mixer; 943 944 struct hdspm_tco *tco; /* NULL if no TCO detected */ 945 946 char **texts_autosync; 947 int texts_autosync_items; 948 949 cycles_t last_interrupt; 950 951 struct hdspm_peak_rms peak_rms; 952 }; 953 954 955 static DEFINE_PCI_DEVICE_TABLE(snd_hdspm_ids) = { 956 { 957 .vendor = PCI_VENDOR_ID_XILINX, 958 .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP_MADI, 959 .subvendor = PCI_ANY_ID, 960 .subdevice = PCI_ANY_ID, 961 .class = 0, 962 .class_mask = 0, 963 .driver_data = 0}, 964 {0,} 965 }; 966 967 MODULE_DEVICE_TABLE(pci, snd_hdspm_ids); 968 969 /* prototypes */ 970 static int __devinit snd_hdspm_create_alsa_devices(struct snd_card *card, 971 struct hdspm * hdspm); 972 static int __devinit snd_hdspm_create_pcm(struct snd_card *card, 973 struct hdspm * hdspm); 974 975 static inline void snd_hdspm_initialize_midi_flush(struct hdspm *hdspm); 976 static int hdspm_update_simple_mixer_controls(struct hdspm *hdspm); 977 static int hdspm_autosync_ref(struct hdspm *hdspm); 978 static int snd_hdspm_set_defaults(struct hdspm *hdspm); 979 static void hdspm_set_sgbuf(struct hdspm *hdspm, 980 struct snd_pcm_substream *substream, 981 unsigned int reg, int channels); 982 983 static inline int HDSPM_bit2freq(int n) 984 { 985 static const int bit2freq_tab[] = { 986 0, 32000, 44100, 48000, 64000, 88200, 987 96000, 128000, 176400, 192000 }; 988 if (n < 1 || n > 9) 989 return 0; 990 return bit2freq_tab[n]; 991 } 992 993 /* Write/read to/from HDSPM with Adresses in Bytes 994 not words but only 32Bit writes are allowed */ 995 996 static inline void hdspm_write(struct hdspm * hdspm, unsigned int reg, 997 unsigned int val) 998 { 999 writel(val, hdspm->iobase + reg); 1000 } 1001 1002 static inline unsigned int hdspm_read(struct hdspm * hdspm, unsigned int reg) 1003 { 1004 return readl(hdspm->iobase + reg); 1005 } 1006 1007 /* for each output channel (chan) I have an Input (in) and Playback (pb) Fader 1008 mixer is write only on hardware so we have to cache him for read 1009 each fader is a u32, but uses only the first 16 bit */ 1010 1011 static inline int hdspm_read_in_gain(struct hdspm * hdspm, unsigned int chan, 1012 unsigned int in) 1013 { 1014 if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS) 1015 return 0; 1016 1017 return hdspm->mixer->ch[chan].in[in]; 1018 } 1019 1020 static inline int hdspm_read_pb_gain(struct hdspm * hdspm, unsigned int chan, 1021 unsigned int pb) 1022 { 1023 if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS) 1024 return 0; 1025 return hdspm->mixer->ch[chan].pb[pb]; 1026 } 1027 1028 static int hdspm_write_in_gain(struct hdspm *hdspm, unsigned int chan, 1029 unsigned int in, unsigned short data) 1030 { 1031 if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS) 1032 return -1; 1033 1034 hdspm_write(hdspm, 1035 HDSPM_MADI_mixerBase + 1036 ((in + 128 * chan) * sizeof(u32)), 1037 (hdspm->mixer->ch[chan].in[in] = data & 0xFFFF)); 1038 return 0; 1039 } 1040 1041 static int hdspm_write_pb_gain(struct hdspm *hdspm, unsigned int chan, 1042 unsigned int pb, unsigned short data) 1043 { 1044 if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS) 1045 return -1; 1046 1047 hdspm_write(hdspm, 1048 HDSPM_MADI_mixerBase + 1049 ((64 + pb + 128 * chan) * sizeof(u32)), 1050 (hdspm->mixer->ch[chan].pb[pb] = data & 0xFFFF)); 1051 return 0; 1052 } 1053 1054 1055 /* enable DMA for specific channels, now available for DSP-MADI */ 1056 static inline void snd_hdspm_enable_in(struct hdspm * hdspm, int i, int v) 1057 { 1058 hdspm_write(hdspm, HDSPM_inputEnableBase + (4 * i), v); 1059 } 1060 1061 static inline void snd_hdspm_enable_out(struct hdspm * hdspm, int i, int v) 1062 { 1063 hdspm_write(hdspm, HDSPM_outputEnableBase + (4 * i), v); 1064 } 1065 1066 /* check if same process is writing and reading */ 1067 static int snd_hdspm_use_is_exclusive(struct hdspm *hdspm) 1068 { 1069 unsigned long flags; 1070 int ret = 1; 1071 1072 spin_lock_irqsave(&hdspm->lock, flags); 1073 if ((hdspm->playback_pid != hdspm->capture_pid) && 1074 (hdspm->playback_pid >= 0) && (hdspm->capture_pid >= 0)) { 1075 ret = 0; 1076 } 1077 spin_unlock_irqrestore(&hdspm->lock, flags); 1078 return ret; 1079 } 1080 1081 /* check for external sample rate */ 1082 static int hdspm_external_sample_rate(struct hdspm *hdspm) 1083 { 1084 unsigned int status, status2, timecode; 1085 int syncref, rate = 0, rate_bits; 1086 1087 switch (hdspm->io_type) { 1088 case AES32: 1089 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 1090 status = hdspm_read(hdspm, HDSPM_statusRegister); 1091 timecode = hdspm_read(hdspm, HDSPM_timecodeRegister); 1092 1093 syncref = hdspm_autosync_ref(hdspm); 1094 1095 if (syncref == HDSPM_AES32_AUTOSYNC_FROM_WORD && 1096 status & HDSPM_AES32_wcLock) 1097 return HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF); 1098 1099 if (syncref >= HDSPM_AES32_AUTOSYNC_FROM_AES1 && 1100 syncref <= HDSPM_AES32_AUTOSYNC_FROM_AES8 && 1101 status2 & (HDSPM_LockAES >> 1102 (syncref - HDSPM_AES32_AUTOSYNC_FROM_AES1))) 1103 return HDSPM_bit2freq((timecode >> (4*(syncref-HDSPM_AES32_AUTOSYNC_FROM_AES1))) & 0xF); 1104 return 0; 1105 break; 1106 1107 case MADIface: 1108 status = hdspm_read(hdspm, HDSPM_statusRegister); 1109 1110 if (!(status & HDSPM_madiLock)) { 1111 rate = 0; /* no lock */ 1112 } else { 1113 switch (status & (HDSPM_status1_freqMask)) { 1114 case HDSPM_status1_F_0*1: 1115 rate = 32000; break; 1116 case HDSPM_status1_F_0*2: 1117 rate = 44100; break; 1118 case HDSPM_status1_F_0*3: 1119 rate = 48000; break; 1120 case HDSPM_status1_F_0*4: 1121 rate = 64000; break; 1122 case HDSPM_status1_F_0*5: 1123 rate = 88200; break; 1124 case HDSPM_status1_F_0*6: 1125 rate = 96000; break; 1126 case HDSPM_status1_F_0*7: 1127 rate = 128000; break; 1128 case HDSPM_status1_F_0*8: 1129 rate = 176400; break; 1130 case HDSPM_status1_F_0*9: 1131 rate = 192000; break; 1132 default: 1133 rate = 0; break; 1134 } 1135 } 1136 1137 break; 1138 1139 case MADI: 1140 case AIO: 1141 case RayDAT: 1142 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 1143 status = hdspm_read(hdspm, HDSPM_statusRegister); 1144 rate = 0; 1145 1146 /* if wordclock has synced freq and wordclock is valid */ 1147 if ((status2 & HDSPM_wcLock) != 0 && 1148 (status2 & HDSPM_SelSyncRef0) == 0) { 1149 1150 rate_bits = status2 & HDSPM_wcFreqMask; 1151 1152 1153 switch (rate_bits) { 1154 case HDSPM_wcFreq32: 1155 rate = 32000; 1156 break; 1157 case HDSPM_wcFreq44_1: 1158 rate = 44100; 1159 break; 1160 case HDSPM_wcFreq48: 1161 rate = 48000; 1162 break; 1163 case HDSPM_wcFreq64: 1164 rate = 64000; 1165 break; 1166 case HDSPM_wcFreq88_2: 1167 rate = 88200; 1168 break; 1169 case HDSPM_wcFreq96: 1170 rate = 96000; 1171 break; 1172 default: 1173 rate = 0; 1174 break; 1175 } 1176 } 1177 1178 /* if rate detected and Syncref is Word than have it, 1179 * word has priority to MADI 1180 */ 1181 if (rate != 0 && 1182 (status2 & HDSPM_SelSyncRefMask) == HDSPM_SelSyncRef_WORD) 1183 return rate; 1184 1185 /* maybe a madi input (which is taken if sel sync is madi) */ 1186 if (status & HDSPM_madiLock) { 1187 rate_bits = status & HDSPM_madiFreqMask; 1188 1189 switch (rate_bits) { 1190 case HDSPM_madiFreq32: 1191 rate = 32000; 1192 break; 1193 case HDSPM_madiFreq44_1: 1194 rate = 44100; 1195 break; 1196 case HDSPM_madiFreq48: 1197 rate = 48000; 1198 break; 1199 case HDSPM_madiFreq64: 1200 rate = 64000; 1201 break; 1202 case HDSPM_madiFreq88_2: 1203 rate = 88200; 1204 break; 1205 case HDSPM_madiFreq96: 1206 rate = 96000; 1207 break; 1208 case HDSPM_madiFreq128: 1209 rate = 128000; 1210 break; 1211 case HDSPM_madiFreq176_4: 1212 rate = 176400; 1213 break; 1214 case HDSPM_madiFreq192: 1215 rate = 192000; 1216 break; 1217 default: 1218 rate = 0; 1219 break; 1220 } 1221 1222 /* QS and DS rates normally can not be detected 1223 * automatically by the card. Only exception is MADI 1224 * in 96k frame mode. 1225 * 1226 * So if we read SS values (32 .. 48k), check for 1227 * user-provided DS/QS bits in the control register 1228 * and multiply the base frequency accordingly. 1229 */ 1230 if (rate <= 48000) { 1231 if (hdspm->control_register & HDSPM_QuadSpeed) 1232 rate *= 4; 1233 else if (hdspm->control_register & 1234 HDSPM_DoubleSpeed) 1235 rate *= 2; 1236 } 1237 } 1238 break; 1239 } 1240 1241 return rate; 1242 } 1243 1244 /* Latency function */ 1245 static inline void hdspm_compute_period_size(struct hdspm *hdspm) 1246 { 1247 hdspm->period_bytes = 1 << ((hdspm_decode_latency(hdspm->control_register) + 8)); 1248 } 1249 1250 1251 static snd_pcm_uframes_t hdspm_hw_pointer(struct hdspm *hdspm) 1252 { 1253 int position; 1254 1255 position = hdspm_read(hdspm, HDSPM_statusRegister); 1256 1257 switch (hdspm->io_type) { 1258 case RayDAT: 1259 case AIO: 1260 position &= HDSPM_BufferPositionMask; 1261 position /= 4; /* Bytes per sample */ 1262 break; 1263 default: 1264 position = (position & HDSPM_BufferID) ? 1265 (hdspm->period_bytes / 4) : 0; 1266 } 1267 1268 return position; 1269 } 1270 1271 1272 static inline void hdspm_start_audio(struct hdspm * s) 1273 { 1274 s->control_register |= (HDSPM_AudioInterruptEnable | HDSPM_Start); 1275 hdspm_write(s, HDSPM_controlRegister, s->control_register); 1276 } 1277 1278 static inline void hdspm_stop_audio(struct hdspm * s) 1279 { 1280 s->control_register &= ~(HDSPM_Start | HDSPM_AudioInterruptEnable); 1281 hdspm_write(s, HDSPM_controlRegister, s->control_register); 1282 } 1283 1284 /* should I silence all or only opened ones ? doit all for first even is 4MB*/ 1285 static void hdspm_silence_playback(struct hdspm *hdspm) 1286 { 1287 int i; 1288 int n = hdspm->period_bytes; 1289 void *buf = hdspm->playback_buffer; 1290 1291 if (buf == NULL) 1292 return; 1293 1294 for (i = 0; i < HDSPM_MAX_CHANNELS; i++) { 1295 memset(buf, 0, n); 1296 buf += HDSPM_CHANNEL_BUFFER_BYTES; 1297 } 1298 } 1299 1300 static int hdspm_set_interrupt_interval(struct hdspm *s, unsigned int frames) 1301 { 1302 int n; 1303 1304 spin_lock_irq(&s->lock); 1305 1306 frames >>= 7; 1307 n = 0; 1308 while (frames) { 1309 n++; 1310 frames >>= 1; 1311 } 1312 s->control_register &= ~HDSPM_LatencyMask; 1313 s->control_register |= hdspm_encode_latency(n); 1314 1315 hdspm_write(s, HDSPM_controlRegister, s->control_register); 1316 1317 hdspm_compute_period_size(s); 1318 1319 spin_unlock_irq(&s->lock); 1320 1321 return 0; 1322 } 1323 1324 static u64 hdspm_calc_dds_value(struct hdspm *hdspm, u64 period) 1325 { 1326 u64 freq_const; 1327 1328 if (period == 0) 1329 return 0; 1330 1331 switch (hdspm->io_type) { 1332 case MADI: 1333 case AES32: 1334 freq_const = 110069313433624ULL; 1335 break; 1336 case RayDAT: 1337 case AIO: 1338 freq_const = 104857600000000ULL; 1339 break; 1340 case MADIface: 1341 freq_const = 131072000000000ULL; 1342 break; 1343 default: 1344 snd_BUG(); 1345 return 0; 1346 } 1347 1348 return div_u64(freq_const, period); 1349 } 1350 1351 1352 static void hdspm_set_dds_value(struct hdspm *hdspm, int rate) 1353 { 1354 u64 n; 1355 1356 if (rate >= 112000) 1357 rate /= 4; 1358 else if (rate >= 56000) 1359 rate /= 2; 1360 1361 switch (hdspm->io_type) { 1362 case MADIface: 1363 n = 131072000000000ULL; /* 125 MHz */ 1364 break; 1365 case MADI: 1366 case AES32: 1367 n = 110069313433624ULL; /* 105 MHz */ 1368 break; 1369 case RayDAT: 1370 case AIO: 1371 n = 104857600000000ULL; /* 100 MHz */ 1372 break; 1373 default: 1374 snd_BUG(); 1375 return; 1376 } 1377 1378 n = div_u64(n, rate); 1379 /* n should be less than 2^32 for being written to FREQ register */ 1380 snd_BUG_ON(n >> 32); 1381 hdspm_write(hdspm, HDSPM_freqReg, (u32)n); 1382 } 1383 1384 /* dummy set rate lets see what happens */ 1385 static int hdspm_set_rate(struct hdspm * hdspm, int rate, int called_internally) 1386 { 1387 int current_rate; 1388 int rate_bits; 1389 int not_set = 0; 1390 int current_speed, target_speed; 1391 1392 /* ASSUMPTION: hdspm->lock is either set, or there is no need for 1393 it (e.g. during module initialization). 1394 */ 1395 1396 if (!(hdspm->control_register & HDSPM_ClockModeMaster)) { 1397 1398 /* SLAVE --- */ 1399 if (called_internally) { 1400 1401 /* request from ctl or card initialization 1402 just make a warning an remember setting 1403 for future master mode switching */ 1404 1405 snd_printk(KERN_WARNING "HDSPM: " 1406 "Warning: device is not running " 1407 "as a clock master.\n"); 1408 not_set = 1; 1409 } else { 1410 1411 /* hw_param request while in AutoSync mode */ 1412 int external_freq = 1413 hdspm_external_sample_rate(hdspm); 1414 1415 if (hdspm_autosync_ref(hdspm) == 1416 HDSPM_AUTOSYNC_FROM_NONE) { 1417 1418 snd_printk(KERN_WARNING "HDSPM: " 1419 "Detected no Externel Sync \n"); 1420 not_set = 1; 1421 1422 } else if (rate != external_freq) { 1423 1424 snd_printk(KERN_WARNING "HDSPM: " 1425 "Warning: No AutoSync source for " 1426 "requested rate\n"); 1427 not_set = 1; 1428 } 1429 } 1430 } 1431 1432 current_rate = hdspm->system_sample_rate; 1433 1434 /* Changing between Singe, Double and Quad speed is not 1435 allowed if any substreams are open. This is because such a change 1436 causes a shift in the location of the DMA buffers and a reduction 1437 in the number of available buffers. 1438 1439 Note that a similar but essentially insoluble problem exists for 1440 externally-driven rate changes. All we can do is to flag rate 1441 changes in the read/write routines. 1442 */ 1443 1444 if (current_rate <= 48000) 1445 current_speed = HDSPM_SPEED_SINGLE; 1446 else if (current_rate <= 96000) 1447 current_speed = HDSPM_SPEED_DOUBLE; 1448 else 1449 current_speed = HDSPM_SPEED_QUAD; 1450 1451 if (rate <= 48000) 1452 target_speed = HDSPM_SPEED_SINGLE; 1453 else if (rate <= 96000) 1454 target_speed = HDSPM_SPEED_DOUBLE; 1455 else 1456 target_speed = HDSPM_SPEED_QUAD; 1457 1458 switch (rate) { 1459 case 32000: 1460 rate_bits = HDSPM_Frequency32KHz; 1461 break; 1462 case 44100: 1463 rate_bits = HDSPM_Frequency44_1KHz; 1464 break; 1465 case 48000: 1466 rate_bits = HDSPM_Frequency48KHz; 1467 break; 1468 case 64000: 1469 rate_bits = HDSPM_Frequency64KHz; 1470 break; 1471 case 88200: 1472 rate_bits = HDSPM_Frequency88_2KHz; 1473 break; 1474 case 96000: 1475 rate_bits = HDSPM_Frequency96KHz; 1476 break; 1477 case 128000: 1478 rate_bits = HDSPM_Frequency128KHz; 1479 break; 1480 case 176400: 1481 rate_bits = HDSPM_Frequency176_4KHz; 1482 break; 1483 case 192000: 1484 rate_bits = HDSPM_Frequency192KHz; 1485 break; 1486 default: 1487 return -EINVAL; 1488 } 1489 1490 if (current_speed != target_speed 1491 && (hdspm->capture_pid >= 0 || hdspm->playback_pid >= 0)) { 1492 snd_printk 1493 (KERN_ERR "HDSPM: " 1494 "cannot change from %s speed to %s speed mode " 1495 "(capture PID = %d, playback PID = %d)\n", 1496 hdspm_speed_names[current_speed], 1497 hdspm_speed_names[target_speed], 1498 hdspm->capture_pid, hdspm->playback_pid); 1499 return -EBUSY; 1500 } 1501 1502 hdspm->control_register &= ~HDSPM_FrequencyMask; 1503 hdspm->control_register |= rate_bits; 1504 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 1505 1506 /* For AES32, need to set DDS value in FREQ register 1507 For MADI, also apparently */ 1508 hdspm_set_dds_value(hdspm, rate); 1509 1510 if (AES32 == hdspm->io_type && rate != current_rate) 1511 hdspm_write(hdspm, HDSPM_eeprom_wr, 0); 1512 1513 hdspm->system_sample_rate = rate; 1514 1515 if (rate <= 48000) { 1516 hdspm->channel_map_in = hdspm->channel_map_in_ss; 1517 hdspm->channel_map_out = hdspm->channel_map_out_ss; 1518 hdspm->max_channels_in = hdspm->ss_in_channels; 1519 hdspm->max_channels_out = hdspm->ss_out_channels; 1520 hdspm->port_names_in = hdspm->port_names_in_ss; 1521 hdspm->port_names_out = hdspm->port_names_out_ss; 1522 } else if (rate <= 96000) { 1523 hdspm->channel_map_in = hdspm->channel_map_in_ds; 1524 hdspm->channel_map_out = hdspm->channel_map_out_ds; 1525 hdspm->max_channels_in = hdspm->ds_in_channels; 1526 hdspm->max_channels_out = hdspm->ds_out_channels; 1527 hdspm->port_names_in = hdspm->port_names_in_ds; 1528 hdspm->port_names_out = hdspm->port_names_out_ds; 1529 } else { 1530 hdspm->channel_map_in = hdspm->channel_map_in_qs; 1531 hdspm->channel_map_out = hdspm->channel_map_out_qs; 1532 hdspm->max_channels_in = hdspm->qs_in_channels; 1533 hdspm->max_channels_out = hdspm->qs_out_channels; 1534 hdspm->port_names_in = hdspm->port_names_in_qs; 1535 hdspm->port_names_out = hdspm->port_names_out_qs; 1536 } 1537 1538 if (not_set != 0) 1539 return -1; 1540 1541 return 0; 1542 } 1543 1544 /* mainly for init to 0 on load */ 1545 static void all_in_all_mixer(struct hdspm * hdspm, int sgain) 1546 { 1547 int i, j; 1548 unsigned int gain; 1549 1550 if (sgain > UNITY_GAIN) 1551 gain = UNITY_GAIN; 1552 else if (sgain < 0) 1553 gain = 0; 1554 else 1555 gain = sgain; 1556 1557 for (i = 0; i < HDSPM_MIXER_CHANNELS; i++) 1558 for (j = 0; j < HDSPM_MIXER_CHANNELS; j++) { 1559 hdspm_write_in_gain(hdspm, i, j, gain); 1560 hdspm_write_pb_gain(hdspm, i, j, gain); 1561 } 1562 } 1563 1564 /*---------------------------------------------------------------------------- 1565 MIDI 1566 ----------------------------------------------------------------------------*/ 1567 1568 static inline unsigned char snd_hdspm_midi_read_byte (struct hdspm *hdspm, 1569 int id) 1570 { 1571 /* the hardware already does the relevant bit-mask with 0xff */ 1572 return hdspm_read(hdspm, hdspm->midi[id].dataIn); 1573 } 1574 1575 static inline void snd_hdspm_midi_write_byte (struct hdspm *hdspm, int id, 1576 int val) 1577 { 1578 /* the hardware already does the relevant bit-mask with 0xff */ 1579 return hdspm_write(hdspm, hdspm->midi[id].dataOut, val); 1580 } 1581 1582 static inline int snd_hdspm_midi_input_available (struct hdspm *hdspm, int id) 1583 { 1584 return hdspm_read(hdspm, hdspm->midi[id].statusIn) & 0xFF; 1585 } 1586 1587 static inline int snd_hdspm_midi_output_possible (struct hdspm *hdspm, int id) 1588 { 1589 int fifo_bytes_used; 1590 1591 fifo_bytes_used = hdspm_read(hdspm, hdspm->midi[id].statusOut) & 0xFF; 1592 1593 if (fifo_bytes_used < 128) 1594 return 128 - fifo_bytes_used; 1595 else 1596 return 0; 1597 } 1598 1599 static void snd_hdspm_flush_midi_input(struct hdspm *hdspm, int id) 1600 { 1601 while (snd_hdspm_midi_input_available (hdspm, id)) 1602 snd_hdspm_midi_read_byte (hdspm, id); 1603 } 1604 1605 static int snd_hdspm_midi_output_write (struct hdspm_midi *hmidi) 1606 { 1607 unsigned long flags; 1608 int n_pending; 1609 int to_write; 1610 int i; 1611 unsigned char buf[128]; 1612 1613 /* Output is not interrupt driven */ 1614 1615 spin_lock_irqsave (&hmidi->lock, flags); 1616 if (hmidi->output && 1617 !snd_rawmidi_transmit_empty (hmidi->output)) { 1618 n_pending = snd_hdspm_midi_output_possible (hmidi->hdspm, 1619 hmidi->id); 1620 if (n_pending > 0) { 1621 if (n_pending > (int)sizeof (buf)) 1622 n_pending = sizeof (buf); 1623 1624 to_write = snd_rawmidi_transmit (hmidi->output, buf, 1625 n_pending); 1626 if (to_write > 0) { 1627 for (i = 0; i < to_write; ++i) 1628 snd_hdspm_midi_write_byte (hmidi->hdspm, 1629 hmidi->id, 1630 buf[i]); 1631 } 1632 } 1633 } 1634 spin_unlock_irqrestore (&hmidi->lock, flags); 1635 return 0; 1636 } 1637 1638 static int snd_hdspm_midi_input_read (struct hdspm_midi *hmidi) 1639 { 1640 unsigned char buf[128]; /* this buffer is designed to match the MIDI 1641 * input FIFO size 1642 */ 1643 unsigned long flags; 1644 int n_pending; 1645 int i; 1646 1647 spin_lock_irqsave (&hmidi->lock, flags); 1648 n_pending = snd_hdspm_midi_input_available (hmidi->hdspm, hmidi->id); 1649 if (n_pending > 0) { 1650 if (hmidi->input) { 1651 if (n_pending > (int)sizeof (buf)) 1652 n_pending = sizeof (buf); 1653 for (i = 0; i < n_pending; ++i) 1654 buf[i] = snd_hdspm_midi_read_byte (hmidi->hdspm, 1655 hmidi->id); 1656 if (n_pending) 1657 snd_rawmidi_receive (hmidi->input, buf, 1658 n_pending); 1659 } else { 1660 /* flush the MIDI input FIFO */ 1661 while (n_pending--) 1662 snd_hdspm_midi_read_byte (hmidi->hdspm, 1663 hmidi->id); 1664 } 1665 } 1666 hmidi->pending = 0; 1667 spin_unlock_irqrestore(&hmidi->lock, flags); 1668 1669 spin_lock_irqsave(&hmidi->hdspm->lock, flags); 1670 hmidi->hdspm->control_register |= hmidi->ie; 1671 hdspm_write(hmidi->hdspm, HDSPM_controlRegister, 1672 hmidi->hdspm->control_register); 1673 spin_unlock_irqrestore(&hmidi->hdspm->lock, flags); 1674 1675 return snd_hdspm_midi_output_write (hmidi); 1676 } 1677 1678 static void 1679 snd_hdspm_midi_input_trigger(struct snd_rawmidi_substream *substream, int up) 1680 { 1681 struct hdspm *hdspm; 1682 struct hdspm_midi *hmidi; 1683 unsigned long flags; 1684 1685 hmidi = substream->rmidi->private_data; 1686 hdspm = hmidi->hdspm; 1687 1688 spin_lock_irqsave (&hdspm->lock, flags); 1689 if (up) { 1690 if (!(hdspm->control_register & hmidi->ie)) { 1691 snd_hdspm_flush_midi_input (hdspm, hmidi->id); 1692 hdspm->control_register |= hmidi->ie; 1693 } 1694 } else { 1695 hdspm->control_register &= ~hmidi->ie; 1696 } 1697 1698 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 1699 spin_unlock_irqrestore (&hdspm->lock, flags); 1700 } 1701 1702 static void snd_hdspm_midi_output_timer(unsigned long data) 1703 { 1704 struct hdspm_midi *hmidi = (struct hdspm_midi *) data; 1705 unsigned long flags; 1706 1707 snd_hdspm_midi_output_write(hmidi); 1708 spin_lock_irqsave (&hmidi->lock, flags); 1709 1710 /* this does not bump hmidi->istimer, because the 1711 kernel automatically removed the timer when it 1712 expired, and we are now adding it back, thus 1713 leaving istimer wherever it was set before. 1714 */ 1715 1716 if (hmidi->istimer) { 1717 hmidi->timer.expires = 1 + jiffies; 1718 add_timer(&hmidi->timer); 1719 } 1720 1721 spin_unlock_irqrestore (&hmidi->lock, flags); 1722 } 1723 1724 static void 1725 snd_hdspm_midi_output_trigger(struct snd_rawmidi_substream *substream, int up) 1726 { 1727 struct hdspm_midi *hmidi; 1728 unsigned long flags; 1729 1730 hmidi = substream->rmidi->private_data; 1731 spin_lock_irqsave (&hmidi->lock, flags); 1732 if (up) { 1733 if (!hmidi->istimer) { 1734 init_timer(&hmidi->timer); 1735 hmidi->timer.function = snd_hdspm_midi_output_timer; 1736 hmidi->timer.data = (unsigned long) hmidi; 1737 hmidi->timer.expires = 1 + jiffies; 1738 add_timer(&hmidi->timer); 1739 hmidi->istimer++; 1740 } 1741 } else { 1742 if (hmidi->istimer && --hmidi->istimer <= 0) 1743 del_timer (&hmidi->timer); 1744 } 1745 spin_unlock_irqrestore (&hmidi->lock, flags); 1746 if (up) 1747 snd_hdspm_midi_output_write(hmidi); 1748 } 1749 1750 static int snd_hdspm_midi_input_open(struct snd_rawmidi_substream *substream) 1751 { 1752 struct hdspm_midi *hmidi; 1753 1754 hmidi = substream->rmidi->private_data; 1755 spin_lock_irq (&hmidi->lock); 1756 snd_hdspm_flush_midi_input (hmidi->hdspm, hmidi->id); 1757 hmidi->input = substream; 1758 spin_unlock_irq (&hmidi->lock); 1759 1760 return 0; 1761 } 1762 1763 static int snd_hdspm_midi_output_open(struct snd_rawmidi_substream *substream) 1764 { 1765 struct hdspm_midi *hmidi; 1766 1767 hmidi = substream->rmidi->private_data; 1768 spin_lock_irq (&hmidi->lock); 1769 hmidi->output = substream; 1770 spin_unlock_irq (&hmidi->lock); 1771 1772 return 0; 1773 } 1774 1775 static int snd_hdspm_midi_input_close(struct snd_rawmidi_substream *substream) 1776 { 1777 struct hdspm_midi *hmidi; 1778 1779 snd_hdspm_midi_input_trigger (substream, 0); 1780 1781 hmidi = substream->rmidi->private_data; 1782 spin_lock_irq (&hmidi->lock); 1783 hmidi->input = NULL; 1784 spin_unlock_irq (&hmidi->lock); 1785 1786 return 0; 1787 } 1788 1789 static int snd_hdspm_midi_output_close(struct snd_rawmidi_substream *substream) 1790 { 1791 struct hdspm_midi *hmidi; 1792 1793 snd_hdspm_midi_output_trigger (substream, 0); 1794 1795 hmidi = substream->rmidi->private_data; 1796 spin_lock_irq (&hmidi->lock); 1797 hmidi->output = NULL; 1798 spin_unlock_irq (&hmidi->lock); 1799 1800 return 0; 1801 } 1802 1803 static struct snd_rawmidi_ops snd_hdspm_midi_output = 1804 { 1805 .open = snd_hdspm_midi_output_open, 1806 .close = snd_hdspm_midi_output_close, 1807 .trigger = snd_hdspm_midi_output_trigger, 1808 }; 1809 1810 static struct snd_rawmidi_ops snd_hdspm_midi_input = 1811 { 1812 .open = snd_hdspm_midi_input_open, 1813 .close = snd_hdspm_midi_input_close, 1814 .trigger = snd_hdspm_midi_input_trigger, 1815 }; 1816 1817 static int __devinit snd_hdspm_create_midi (struct snd_card *card, 1818 struct hdspm *hdspm, int id) 1819 { 1820 int err; 1821 char buf[32]; 1822 1823 hdspm->midi[id].id = id; 1824 hdspm->midi[id].hdspm = hdspm; 1825 spin_lock_init (&hdspm->midi[id].lock); 1826 1827 if (0 == id) { 1828 if (MADIface == hdspm->io_type) { 1829 /* MIDI-over-MADI on HDSPe MADIface */ 1830 hdspm->midi[0].dataIn = HDSPM_midiDataIn2; 1831 hdspm->midi[0].statusIn = HDSPM_midiStatusIn2; 1832 hdspm->midi[0].dataOut = HDSPM_midiDataOut2; 1833 hdspm->midi[0].statusOut = HDSPM_midiStatusOut2; 1834 hdspm->midi[0].ie = HDSPM_Midi2InterruptEnable; 1835 hdspm->midi[0].irq = HDSPM_midi2IRQPending; 1836 } else { 1837 hdspm->midi[0].dataIn = HDSPM_midiDataIn0; 1838 hdspm->midi[0].statusIn = HDSPM_midiStatusIn0; 1839 hdspm->midi[0].dataOut = HDSPM_midiDataOut0; 1840 hdspm->midi[0].statusOut = HDSPM_midiStatusOut0; 1841 hdspm->midi[0].ie = HDSPM_Midi0InterruptEnable; 1842 hdspm->midi[0].irq = HDSPM_midi0IRQPending; 1843 } 1844 } else if (1 == id) { 1845 hdspm->midi[1].dataIn = HDSPM_midiDataIn1; 1846 hdspm->midi[1].statusIn = HDSPM_midiStatusIn1; 1847 hdspm->midi[1].dataOut = HDSPM_midiDataOut1; 1848 hdspm->midi[1].statusOut = HDSPM_midiStatusOut1; 1849 hdspm->midi[1].ie = HDSPM_Midi1InterruptEnable; 1850 hdspm->midi[1].irq = HDSPM_midi1IRQPending; 1851 } else if ((2 == id) && (MADI == hdspm->io_type)) { 1852 /* MIDI-over-MADI on HDSPe MADI */ 1853 hdspm->midi[2].dataIn = HDSPM_midiDataIn2; 1854 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2; 1855 hdspm->midi[2].dataOut = HDSPM_midiDataOut2; 1856 hdspm->midi[2].statusOut = HDSPM_midiStatusOut2; 1857 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable; 1858 hdspm->midi[2].irq = HDSPM_midi2IRQPending; 1859 } else if (2 == id) { 1860 /* TCO MTC, read only */ 1861 hdspm->midi[2].dataIn = HDSPM_midiDataIn2; 1862 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2; 1863 hdspm->midi[2].dataOut = -1; 1864 hdspm->midi[2].statusOut = -1; 1865 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable; 1866 hdspm->midi[2].irq = HDSPM_midi2IRQPendingAES; 1867 } else if (3 == id) { 1868 /* TCO MTC on HDSPe MADI */ 1869 hdspm->midi[3].dataIn = HDSPM_midiDataIn3; 1870 hdspm->midi[3].statusIn = HDSPM_midiStatusIn3; 1871 hdspm->midi[3].dataOut = -1; 1872 hdspm->midi[3].statusOut = -1; 1873 hdspm->midi[3].ie = HDSPM_Midi3InterruptEnable; 1874 hdspm->midi[3].irq = HDSPM_midi3IRQPending; 1875 } 1876 1877 if ((id < 2) || ((2 == id) && ((MADI == hdspm->io_type) || 1878 (MADIface == hdspm->io_type)))) { 1879 if ((id == 0) && (MADIface == hdspm->io_type)) { 1880 sprintf(buf, "%s MIDIoverMADI", card->shortname); 1881 } else if ((id == 2) && (MADI == hdspm->io_type)) { 1882 sprintf(buf, "%s MIDIoverMADI", card->shortname); 1883 } else { 1884 sprintf(buf, "%s MIDI %d", card->shortname, id+1); 1885 } 1886 err = snd_rawmidi_new(card, buf, id, 1, 1, 1887 &hdspm->midi[id].rmidi); 1888 if (err < 0) 1889 return err; 1890 1891 sprintf(hdspm->midi[id].rmidi->name, "%s MIDI %d", 1892 card->id, id+1); 1893 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id]; 1894 1895 snd_rawmidi_set_ops(hdspm->midi[id].rmidi, 1896 SNDRV_RAWMIDI_STREAM_OUTPUT, 1897 &snd_hdspm_midi_output); 1898 snd_rawmidi_set_ops(hdspm->midi[id].rmidi, 1899 SNDRV_RAWMIDI_STREAM_INPUT, 1900 &snd_hdspm_midi_input); 1901 1902 hdspm->midi[id].rmidi->info_flags |= 1903 SNDRV_RAWMIDI_INFO_OUTPUT | 1904 SNDRV_RAWMIDI_INFO_INPUT | 1905 SNDRV_RAWMIDI_INFO_DUPLEX; 1906 } else { 1907 /* TCO MTC, read only */ 1908 sprintf(buf, "%s MTC %d", card->shortname, id+1); 1909 err = snd_rawmidi_new(card, buf, id, 1, 1, 1910 &hdspm->midi[id].rmidi); 1911 if (err < 0) 1912 return err; 1913 1914 sprintf(hdspm->midi[id].rmidi->name, 1915 "%s MTC %d", card->id, id+1); 1916 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id]; 1917 1918 snd_rawmidi_set_ops(hdspm->midi[id].rmidi, 1919 SNDRV_RAWMIDI_STREAM_INPUT, 1920 &snd_hdspm_midi_input); 1921 1922 hdspm->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_INPUT; 1923 } 1924 1925 return 0; 1926 } 1927 1928 1929 static void hdspm_midi_tasklet(unsigned long arg) 1930 { 1931 struct hdspm *hdspm = (struct hdspm *)arg; 1932 int i = 0; 1933 1934 while (i < hdspm->midiPorts) { 1935 if (hdspm->midi[i].pending) 1936 snd_hdspm_midi_input_read(&hdspm->midi[i]); 1937 1938 i++; 1939 } 1940 } 1941 1942 1943 /*----------------------------------------------------------------------------- 1944 Status Interface 1945 ----------------------------------------------------------------------------*/ 1946 1947 /* get the system sample rate which is set */ 1948 1949 1950 /** 1951 * Calculate the real sample rate from the 1952 * current DDS value. 1953 **/ 1954 static int hdspm_get_system_sample_rate(struct hdspm *hdspm) 1955 { 1956 unsigned int period, rate; 1957 1958 period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ); 1959 rate = hdspm_calc_dds_value(hdspm, period); 1960 1961 return rate; 1962 } 1963 1964 1965 #define HDSPM_SYSTEM_SAMPLE_RATE(xname, xindex) \ 1966 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 1967 .name = xname, \ 1968 .index = xindex, \ 1969 .access = SNDRV_CTL_ELEM_ACCESS_READ, \ 1970 .info = snd_hdspm_info_system_sample_rate, \ 1971 .get = snd_hdspm_get_system_sample_rate \ 1972 } 1973 1974 static int snd_hdspm_info_system_sample_rate(struct snd_kcontrol *kcontrol, 1975 struct snd_ctl_elem_info *uinfo) 1976 { 1977 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 1978 uinfo->count = 1; 1979 uinfo->value.integer.min = 27000; 1980 uinfo->value.integer.max = 207000; 1981 uinfo->value.integer.step = 1; 1982 return 0; 1983 } 1984 1985 1986 static int snd_hdspm_get_system_sample_rate(struct snd_kcontrol *kcontrol, 1987 struct snd_ctl_elem_value * 1988 ucontrol) 1989 { 1990 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 1991 1992 ucontrol->value.integer.value[0] = hdspm_get_system_sample_rate(hdspm); 1993 return 0; 1994 } 1995 1996 1997 /** 1998 * Returns the WordClock sample rate class for the given card. 1999 **/ 2000 static int hdspm_get_wc_sample_rate(struct hdspm *hdspm) 2001 { 2002 int status; 2003 2004 switch (hdspm->io_type) { 2005 case RayDAT: 2006 case AIO: 2007 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1); 2008 return (status >> 16) & 0xF; 2009 break; 2010 default: 2011 break; 2012 } 2013 2014 2015 return 0; 2016 } 2017 2018 2019 /** 2020 * Returns the TCO sample rate class for the given card. 2021 **/ 2022 static int hdspm_get_tco_sample_rate(struct hdspm *hdspm) 2023 { 2024 int status; 2025 2026 if (hdspm->tco) { 2027 switch (hdspm->io_type) { 2028 case RayDAT: 2029 case AIO: 2030 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1); 2031 return (status >> 20) & 0xF; 2032 break; 2033 default: 2034 break; 2035 } 2036 } 2037 2038 return 0; 2039 } 2040 2041 2042 /** 2043 * Returns the SYNC_IN sample rate class for the given card. 2044 **/ 2045 static int hdspm_get_sync_in_sample_rate(struct hdspm *hdspm) 2046 { 2047 int status; 2048 2049 if (hdspm->tco) { 2050 switch (hdspm->io_type) { 2051 case RayDAT: 2052 case AIO: 2053 status = hdspm_read(hdspm, HDSPM_RD_STATUS_2); 2054 return (status >> 12) & 0xF; 2055 break; 2056 default: 2057 break; 2058 } 2059 } 2060 2061 return 0; 2062 } 2063 2064 2065 /** 2066 * Returns the sample rate class for input source <idx> for 2067 * 'new style' cards like the AIO and RayDAT. 2068 **/ 2069 static int hdspm_get_s1_sample_rate(struct hdspm *hdspm, unsigned int idx) 2070 { 2071 int status = hdspm_read(hdspm, HDSPM_RD_STATUS_2); 2072 2073 return (status >> (idx*4)) & 0xF; 2074 } 2075 2076 2077 2078 #define HDSPM_AUTOSYNC_SAMPLE_RATE(xname, xindex) \ 2079 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2080 .name = xname, \ 2081 .private_value = xindex, \ 2082 .access = SNDRV_CTL_ELEM_ACCESS_READ, \ 2083 .info = snd_hdspm_info_autosync_sample_rate, \ 2084 .get = snd_hdspm_get_autosync_sample_rate \ 2085 } 2086 2087 2088 static int snd_hdspm_info_autosync_sample_rate(struct snd_kcontrol *kcontrol, 2089 struct snd_ctl_elem_info *uinfo) 2090 { 2091 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2092 uinfo->count = 1; 2093 uinfo->value.enumerated.items = 10; 2094 2095 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 2096 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; 2097 strcpy(uinfo->value.enumerated.name, 2098 texts_freq[uinfo->value.enumerated.item]); 2099 return 0; 2100 } 2101 2102 2103 static int snd_hdspm_get_autosync_sample_rate(struct snd_kcontrol *kcontrol, 2104 struct snd_ctl_elem_value * 2105 ucontrol) 2106 { 2107 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2108 2109 switch (hdspm->io_type) { 2110 case RayDAT: 2111 switch (kcontrol->private_value) { 2112 case 0: 2113 ucontrol->value.enumerated.item[0] = 2114 hdspm_get_wc_sample_rate(hdspm); 2115 break; 2116 case 7: 2117 ucontrol->value.enumerated.item[0] = 2118 hdspm_get_tco_sample_rate(hdspm); 2119 break; 2120 case 8: 2121 ucontrol->value.enumerated.item[0] = 2122 hdspm_get_sync_in_sample_rate(hdspm); 2123 break; 2124 default: 2125 ucontrol->value.enumerated.item[0] = 2126 hdspm_get_s1_sample_rate(hdspm, 2127 kcontrol->private_value-1); 2128 } 2129 2130 case AIO: 2131 switch (kcontrol->private_value) { 2132 case 0: /* WC */ 2133 ucontrol->value.enumerated.item[0] = 2134 hdspm_get_wc_sample_rate(hdspm); 2135 break; 2136 case 4: /* TCO */ 2137 ucontrol->value.enumerated.item[0] = 2138 hdspm_get_tco_sample_rate(hdspm); 2139 break; 2140 case 5: /* SYNC_IN */ 2141 ucontrol->value.enumerated.item[0] = 2142 hdspm_get_sync_in_sample_rate(hdspm); 2143 break; 2144 default: 2145 ucontrol->value.enumerated.item[0] = 2146 hdspm_get_s1_sample_rate(hdspm, 2147 ucontrol->id.index-1); 2148 } 2149 2150 case AES32: 2151 2152 switch (kcontrol->private_value) { 2153 case 0: /* WC */ 2154 ucontrol->value.enumerated.item[0] = 2155 hdspm_get_wc_sample_rate(hdspm); 2156 break; 2157 case 9: /* TCO */ 2158 ucontrol->value.enumerated.item[0] = 2159 hdspm_get_tco_sample_rate(hdspm); 2160 break; 2161 case 10: /* SYNC_IN */ 2162 ucontrol->value.enumerated.item[0] = 2163 hdspm_get_sync_in_sample_rate(hdspm); 2164 break; 2165 default: /* AES1 to AES8 */ 2166 ucontrol->value.enumerated.item[0] = 2167 hdspm_get_s1_sample_rate(hdspm, 2168 kcontrol->private_value-1); 2169 break; 2170 2171 } 2172 default: 2173 break; 2174 } 2175 2176 return 0; 2177 } 2178 2179 2180 #define HDSPM_SYSTEM_CLOCK_MODE(xname, xindex) \ 2181 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2182 .name = xname, \ 2183 .index = xindex, \ 2184 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 2185 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 2186 .info = snd_hdspm_info_system_clock_mode, \ 2187 .get = snd_hdspm_get_system_clock_mode, \ 2188 .put = snd_hdspm_put_system_clock_mode, \ 2189 } 2190 2191 2192 /** 2193 * Returns the system clock mode for the given card. 2194 * @returns 0 - master, 1 - slave 2195 **/ 2196 static int hdspm_system_clock_mode(struct hdspm *hdspm) 2197 { 2198 switch (hdspm->io_type) { 2199 case AIO: 2200 case RayDAT: 2201 if (hdspm->settings_register & HDSPM_c0Master) 2202 return 0; 2203 break; 2204 2205 default: 2206 if (hdspm->control_register & HDSPM_ClockModeMaster) 2207 return 0; 2208 } 2209 2210 return 1; 2211 } 2212 2213 2214 /** 2215 * Sets the system clock mode. 2216 * @param mode 0 - master, 1 - slave 2217 **/ 2218 static void hdspm_set_system_clock_mode(struct hdspm *hdspm, int mode) 2219 { 2220 switch (hdspm->io_type) { 2221 case AIO: 2222 case RayDAT: 2223 if (0 == mode) 2224 hdspm->settings_register |= HDSPM_c0Master; 2225 else 2226 hdspm->settings_register &= ~HDSPM_c0Master; 2227 2228 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register); 2229 break; 2230 2231 default: 2232 if (0 == mode) 2233 hdspm->control_register |= HDSPM_ClockModeMaster; 2234 else 2235 hdspm->control_register &= ~HDSPM_ClockModeMaster; 2236 2237 hdspm_write(hdspm, HDSPM_controlRegister, 2238 hdspm->control_register); 2239 } 2240 } 2241 2242 2243 static int snd_hdspm_info_system_clock_mode(struct snd_kcontrol *kcontrol, 2244 struct snd_ctl_elem_info *uinfo) 2245 { 2246 static char *texts[] = { "Master", "AutoSync" }; 2247 2248 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2249 uinfo->count = 1; 2250 uinfo->value.enumerated.items = 2; 2251 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 2252 uinfo->value.enumerated.item = 2253 uinfo->value.enumerated.items - 1; 2254 strcpy(uinfo->value.enumerated.name, 2255 texts[uinfo->value.enumerated.item]); 2256 return 0; 2257 } 2258 2259 static int snd_hdspm_get_system_clock_mode(struct snd_kcontrol *kcontrol, 2260 struct snd_ctl_elem_value *ucontrol) 2261 { 2262 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2263 2264 ucontrol->value.enumerated.item[0] = hdspm_system_clock_mode(hdspm); 2265 return 0; 2266 } 2267 2268 static int snd_hdspm_put_system_clock_mode(struct snd_kcontrol *kcontrol, 2269 struct snd_ctl_elem_value *ucontrol) 2270 { 2271 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2272 int val; 2273 2274 if (!snd_hdspm_use_is_exclusive(hdspm)) 2275 return -EBUSY; 2276 2277 val = ucontrol->value.enumerated.item[0]; 2278 if (val < 0) 2279 val = 0; 2280 else if (val > 1) 2281 val = 1; 2282 2283 hdspm_set_system_clock_mode(hdspm, val); 2284 2285 return 0; 2286 } 2287 2288 2289 #define HDSPM_INTERNAL_CLOCK(xname, xindex) \ 2290 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2291 .name = xname, \ 2292 .index = xindex, \ 2293 .info = snd_hdspm_info_clock_source, \ 2294 .get = snd_hdspm_get_clock_source, \ 2295 .put = snd_hdspm_put_clock_source \ 2296 } 2297 2298 2299 static int hdspm_clock_source(struct hdspm * hdspm) 2300 { 2301 switch (hdspm->system_sample_rate) { 2302 case 32000: return 0; 2303 case 44100: return 1; 2304 case 48000: return 2; 2305 case 64000: return 3; 2306 case 88200: return 4; 2307 case 96000: return 5; 2308 case 128000: return 6; 2309 case 176400: return 7; 2310 case 192000: return 8; 2311 } 2312 2313 return -1; 2314 } 2315 2316 static int hdspm_set_clock_source(struct hdspm * hdspm, int mode) 2317 { 2318 int rate; 2319 switch (mode) { 2320 case 0: 2321 rate = 32000; break; 2322 case 1: 2323 rate = 44100; break; 2324 case 2: 2325 rate = 48000; break; 2326 case 3: 2327 rate = 64000; break; 2328 case 4: 2329 rate = 88200; break; 2330 case 5: 2331 rate = 96000; break; 2332 case 6: 2333 rate = 128000; break; 2334 case 7: 2335 rate = 176400; break; 2336 case 8: 2337 rate = 192000; break; 2338 default: 2339 rate = 48000; 2340 } 2341 hdspm_set_rate(hdspm, rate, 1); 2342 return 0; 2343 } 2344 2345 static int snd_hdspm_info_clock_source(struct snd_kcontrol *kcontrol, 2346 struct snd_ctl_elem_info *uinfo) 2347 { 2348 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2349 uinfo->count = 1; 2350 uinfo->value.enumerated.items = 9; 2351 2352 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 2353 uinfo->value.enumerated.item = 2354 uinfo->value.enumerated.items - 1; 2355 2356 strcpy(uinfo->value.enumerated.name, 2357 texts_freq[uinfo->value.enumerated.item+1]); 2358 2359 return 0; 2360 } 2361 2362 static int snd_hdspm_get_clock_source(struct snd_kcontrol *kcontrol, 2363 struct snd_ctl_elem_value *ucontrol) 2364 { 2365 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2366 2367 ucontrol->value.enumerated.item[0] = hdspm_clock_source(hdspm); 2368 return 0; 2369 } 2370 2371 static int snd_hdspm_put_clock_source(struct snd_kcontrol *kcontrol, 2372 struct snd_ctl_elem_value *ucontrol) 2373 { 2374 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2375 int change; 2376 int val; 2377 2378 if (!snd_hdspm_use_is_exclusive(hdspm)) 2379 return -EBUSY; 2380 val = ucontrol->value.enumerated.item[0]; 2381 if (val < 0) 2382 val = 0; 2383 if (val > 9) 2384 val = 9; 2385 spin_lock_irq(&hdspm->lock); 2386 if (val != hdspm_clock_source(hdspm)) 2387 change = (hdspm_set_clock_source(hdspm, val) == 0) ? 1 : 0; 2388 else 2389 change = 0; 2390 spin_unlock_irq(&hdspm->lock); 2391 return change; 2392 } 2393 2394 2395 #define HDSPM_PREF_SYNC_REF(xname, xindex) \ 2396 {.iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2397 .name = xname, \ 2398 .index = xindex, \ 2399 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 2400 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 2401 .info = snd_hdspm_info_pref_sync_ref, \ 2402 .get = snd_hdspm_get_pref_sync_ref, \ 2403 .put = snd_hdspm_put_pref_sync_ref \ 2404 } 2405 2406 2407 /** 2408 * Returns the current preferred sync reference setting. 2409 * The semantics of the return value are depending on the 2410 * card, please see the comments for clarification. 2411 **/ 2412 static int hdspm_pref_sync_ref(struct hdspm * hdspm) 2413 { 2414 switch (hdspm->io_type) { 2415 case AES32: 2416 switch (hdspm->control_register & HDSPM_SyncRefMask) { 2417 case 0: return 0; /* WC */ 2418 case HDSPM_SyncRef0: return 1; /* AES 1 */ 2419 case HDSPM_SyncRef1: return 2; /* AES 2 */ 2420 case HDSPM_SyncRef1+HDSPM_SyncRef0: return 3; /* AES 3 */ 2421 case HDSPM_SyncRef2: return 4; /* AES 4 */ 2422 case HDSPM_SyncRef2+HDSPM_SyncRef0: return 5; /* AES 5 */ 2423 case HDSPM_SyncRef2+HDSPM_SyncRef1: return 6; /* AES 6 */ 2424 case HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0: 2425 return 7; /* AES 7 */ 2426 case HDSPM_SyncRef3: return 8; /* AES 8 */ 2427 case HDSPM_SyncRef3+HDSPM_SyncRef0: return 9; /* TCO */ 2428 } 2429 break; 2430 2431 case MADI: 2432 case MADIface: 2433 if (hdspm->tco) { 2434 switch (hdspm->control_register & HDSPM_SyncRefMask) { 2435 case 0: return 0; /* WC */ 2436 case HDSPM_SyncRef0: return 1; /* MADI */ 2437 case HDSPM_SyncRef1: return 2; /* TCO */ 2438 case HDSPM_SyncRef1+HDSPM_SyncRef0: 2439 return 3; /* SYNC_IN */ 2440 } 2441 } else { 2442 switch (hdspm->control_register & HDSPM_SyncRefMask) { 2443 case 0: return 0; /* WC */ 2444 case HDSPM_SyncRef0: return 1; /* MADI */ 2445 case HDSPM_SyncRef1+HDSPM_SyncRef0: 2446 return 2; /* SYNC_IN */ 2447 } 2448 } 2449 break; 2450 2451 case RayDAT: 2452 if (hdspm->tco) { 2453 switch ((hdspm->settings_register & 2454 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) { 2455 case 0: return 0; /* WC */ 2456 case 3: return 1; /* ADAT 1 */ 2457 case 4: return 2; /* ADAT 2 */ 2458 case 5: return 3; /* ADAT 3 */ 2459 case 6: return 4; /* ADAT 4 */ 2460 case 1: return 5; /* AES */ 2461 case 2: return 6; /* SPDIF */ 2462 case 9: return 7; /* TCO */ 2463 case 10: return 8; /* SYNC_IN */ 2464 } 2465 } else { 2466 switch ((hdspm->settings_register & 2467 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) { 2468 case 0: return 0; /* WC */ 2469 case 3: return 1; /* ADAT 1 */ 2470 case 4: return 2; /* ADAT 2 */ 2471 case 5: return 3; /* ADAT 3 */ 2472 case 6: return 4; /* ADAT 4 */ 2473 case 1: return 5; /* AES */ 2474 case 2: return 6; /* SPDIF */ 2475 case 10: return 7; /* SYNC_IN */ 2476 } 2477 } 2478 2479 break; 2480 2481 case AIO: 2482 if (hdspm->tco) { 2483 switch ((hdspm->settings_register & 2484 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) { 2485 case 0: return 0; /* WC */ 2486 case 3: return 1; /* ADAT */ 2487 case 1: return 2; /* AES */ 2488 case 2: return 3; /* SPDIF */ 2489 case 9: return 4; /* TCO */ 2490 case 10: return 5; /* SYNC_IN */ 2491 } 2492 } else { 2493 switch ((hdspm->settings_register & 2494 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) { 2495 case 0: return 0; /* WC */ 2496 case 3: return 1; /* ADAT */ 2497 case 1: return 2; /* AES */ 2498 case 2: return 3; /* SPDIF */ 2499 case 10: return 4; /* SYNC_IN */ 2500 } 2501 } 2502 2503 break; 2504 } 2505 2506 return -1; 2507 } 2508 2509 2510 /** 2511 * Set the preferred sync reference to <pref>. The semantics 2512 * of <pref> are depending on the card type, see the comments 2513 * for clarification. 2514 **/ 2515 static int hdspm_set_pref_sync_ref(struct hdspm * hdspm, int pref) 2516 { 2517 int p = 0; 2518 2519 switch (hdspm->io_type) { 2520 case AES32: 2521 hdspm->control_register &= ~HDSPM_SyncRefMask; 2522 switch (pref) { 2523 case 0: /* WC */ 2524 break; 2525 case 1: /* AES 1 */ 2526 hdspm->control_register |= HDSPM_SyncRef0; 2527 break; 2528 case 2: /* AES 2 */ 2529 hdspm->control_register |= HDSPM_SyncRef1; 2530 break; 2531 case 3: /* AES 3 */ 2532 hdspm->control_register |= 2533 HDSPM_SyncRef1+HDSPM_SyncRef0; 2534 break; 2535 case 4: /* AES 4 */ 2536 hdspm->control_register |= HDSPM_SyncRef2; 2537 break; 2538 case 5: /* AES 5 */ 2539 hdspm->control_register |= 2540 HDSPM_SyncRef2+HDSPM_SyncRef0; 2541 break; 2542 case 6: /* AES 6 */ 2543 hdspm->control_register |= 2544 HDSPM_SyncRef2+HDSPM_SyncRef1; 2545 break; 2546 case 7: /* AES 7 */ 2547 hdspm->control_register |= 2548 HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0; 2549 break; 2550 case 8: /* AES 8 */ 2551 hdspm->control_register |= HDSPM_SyncRef3; 2552 break; 2553 case 9: /* TCO */ 2554 hdspm->control_register |= 2555 HDSPM_SyncRef3+HDSPM_SyncRef0; 2556 break; 2557 default: 2558 return -1; 2559 } 2560 2561 break; 2562 2563 case MADI: 2564 case MADIface: 2565 hdspm->control_register &= ~HDSPM_SyncRefMask; 2566 if (hdspm->tco) { 2567 switch (pref) { 2568 case 0: /* WC */ 2569 break; 2570 case 1: /* MADI */ 2571 hdspm->control_register |= HDSPM_SyncRef0; 2572 break; 2573 case 2: /* TCO */ 2574 hdspm->control_register |= HDSPM_SyncRef1; 2575 break; 2576 case 3: /* SYNC_IN */ 2577 hdspm->control_register |= 2578 HDSPM_SyncRef0+HDSPM_SyncRef1; 2579 break; 2580 default: 2581 return -1; 2582 } 2583 } else { 2584 switch (pref) { 2585 case 0: /* WC */ 2586 break; 2587 case 1: /* MADI */ 2588 hdspm->control_register |= HDSPM_SyncRef0; 2589 break; 2590 case 2: /* SYNC_IN */ 2591 hdspm->control_register |= 2592 HDSPM_SyncRef0+HDSPM_SyncRef1; 2593 break; 2594 default: 2595 return -1; 2596 } 2597 } 2598 2599 break; 2600 2601 case RayDAT: 2602 if (hdspm->tco) { 2603 switch (pref) { 2604 case 0: p = 0; break; /* WC */ 2605 case 1: p = 3; break; /* ADAT 1 */ 2606 case 2: p = 4; break; /* ADAT 2 */ 2607 case 3: p = 5; break; /* ADAT 3 */ 2608 case 4: p = 6; break; /* ADAT 4 */ 2609 case 5: p = 1; break; /* AES */ 2610 case 6: p = 2; break; /* SPDIF */ 2611 case 7: p = 9; break; /* TCO */ 2612 case 8: p = 10; break; /* SYNC_IN */ 2613 default: return -1; 2614 } 2615 } else { 2616 switch (pref) { 2617 case 0: p = 0; break; /* WC */ 2618 case 1: p = 3; break; /* ADAT 1 */ 2619 case 2: p = 4; break; /* ADAT 2 */ 2620 case 3: p = 5; break; /* ADAT 3 */ 2621 case 4: p = 6; break; /* ADAT 4 */ 2622 case 5: p = 1; break; /* AES */ 2623 case 6: p = 2; break; /* SPDIF */ 2624 case 7: p = 10; break; /* SYNC_IN */ 2625 default: return -1; 2626 } 2627 } 2628 break; 2629 2630 case AIO: 2631 if (hdspm->tco) { 2632 switch (pref) { 2633 case 0: p = 0; break; /* WC */ 2634 case 1: p = 3; break; /* ADAT */ 2635 case 2: p = 1; break; /* AES */ 2636 case 3: p = 2; break; /* SPDIF */ 2637 case 4: p = 9; break; /* TCO */ 2638 case 5: p = 10; break; /* SYNC_IN */ 2639 default: return -1; 2640 } 2641 } else { 2642 switch (pref) { 2643 case 0: p = 0; break; /* WC */ 2644 case 1: p = 3; break; /* ADAT */ 2645 case 2: p = 1; break; /* AES */ 2646 case 3: p = 2; break; /* SPDIF */ 2647 case 4: p = 10; break; /* SYNC_IN */ 2648 default: return -1; 2649 } 2650 } 2651 break; 2652 } 2653 2654 switch (hdspm->io_type) { 2655 case RayDAT: 2656 case AIO: 2657 hdspm->settings_register &= ~HDSPM_c0_SyncRefMask; 2658 hdspm->settings_register |= HDSPM_c0_SyncRef0 * p; 2659 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register); 2660 break; 2661 2662 case MADI: 2663 case MADIface: 2664 case AES32: 2665 hdspm_write(hdspm, HDSPM_controlRegister, 2666 hdspm->control_register); 2667 } 2668 2669 return 0; 2670 } 2671 2672 2673 static int snd_hdspm_info_pref_sync_ref(struct snd_kcontrol *kcontrol, 2674 struct snd_ctl_elem_info *uinfo) 2675 { 2676 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2677 2678 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2679 uinfo->count = 1; 2680 uinfo->value.enumerated.items = hdspm->texts_autosync_items; 2681 2682 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 2683 uinfo->value.enumerated.item = 2684 uinfo->value.enumerated.items - 1; 2685 2686 strcpy(uinfo->value.enumerated.name, 2687 hdspm->texts_autosync[uinfo->value.enumerated.item]); 2688 2689 return 0; 2690 } 2691 2692 static int snd_hdspm_get_pref_sync_ref(struct snd_kcontrol *kcontrol, 2693 struct snd_ctl_elem_value *ucontrol) 2694 { 2695 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2696 int psf = hdspm_pref_sync_ref(hdspm); 2697 2698 if (psf >= 0) { 2699 ucontrol->value.enumerated.item[0] = psf; 2700 return 0; 2701 } 2702 2703 return -1; 2704 } 2705 2706 static int snd_hdspm_put_pref_sync_ref(struct snd_kcontrol *kcontrol, 2707 struct snd_ctl_elem_value *ucontrol) 2708 { 2709 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2710 int val, change = 0; 2711 2712 if (!snd_hdspm_use_is_exclusive(hdspm)) 2713 return -EBUSY; 2714 2715 val = ucontrol->value.enumerated.item[0]; 2716 2717 if (val < 0) 2718 val = 0; 2719 else if (val >= hdspm->texts_autosync_items) 2720 val = hdspm->texts_autosync_items-1; 2721 2722 spin_lock_irq(&hdspm->lock); 2723 if (val != hdspm_pref_sync_ref(hdspm)) 2724 change = (0 == hdspm_set_pref_sync_ref(hdspm, val)) ? 1 : 0; 2725 2726 spin_unlock_irq(&hdspm->lock); 2727 return change; 2728 } 2729 2730 2731 #define HDSPM_AUTOSYNC_REF(xname, xindex) \ 2732 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2733 .name = xname, \ 2734 .index = xindex, \ 2735 .access = SNDRV_CTL_ELEM_ACCESS_READ, \ 2736 .info = snd_hdspm_info_autosync_ref, \ 2737 .get = snd_hdspm_get_autosync_ref, \ 2738 } 2739 2740 static int hdspm_autosync_ref(struct hdspm *hdspm) 2741 { 2742 if (AES32 == hdspm->io_type) { 2743 unsigned int status = hdspm_read(hdspm, HDSPM_statusRegister); 2744 unsigned int syncref = 2745 (status >> HDSPM_AES32_syncref_bit) & 0xF; 2746 if (syncref == 0) 2747 return HDSPM_AES32_AUTOSYNC_FROM_WORD; 2748 if (syncref <= 8) 2749 return syncref; 2750 return HDSPM_AES32_AUTOSYNC_FROM_NONE; 2751 } else if (MADI == hdspm->io_type) { 2752 /* This looks at the autosync selected sync reference */ 2753 unsigned int status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 2754 2755 switch (status2 & HDSPM_SelSyncRefMask) { 2756 case HDSPM_SelSyncRef_WORD: 2757 return HDSPM_AUTOSYNC_FROM_WORD; 2758 case HDSPM_SelSyncRef_MADI: 2759 return HDSPM_AUTOSYNC_FROM_MADI; 2760 case HDSPM_SelSyncRef_TCO: 2761 return HDSPM_AUTOSYNC_FROM_TCO; 2762 case HDSPM_SelSyncRef_SyncIn: 2763 return HDSPM_AUTOSYNC_FROM_SYNC_IN; 2764 case HDSPM_SelSyncRef_NVALID: 2765 return HDSPM_AUTOSYNC_FROM_NONE; 2766 default: 2767 return 0; 2768 } 2769 2770 } 2771 return 0; 2772 } 2773 2774 2775 static int snd_hdspm_info_autosync_ref(struct snd_kcontrol *kcontrol, 2776 struct snd_ctl_elem_info *uinfo) 2777 { 2778 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2779 2780 if (AES32 == hdspm->io_type) { 2781 static char *texts[] = { "WordClock", "AES1", "AES2", "AES3", 2782 "AES4", "AES5", "AES6", "AES7", "AES8", "None"}; 2783 2784 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2785 uinfo->count = 1; 2786 uinfo->value.enumerated.items = 10; 2787 if (uinfo->value.enumerated.item >= 2788 uinfo->value.enumerated.items) 2789 uinfo->value.enumerated.item = 2790 uinfo->value.enumerated.items - 1; 2791 strcpy(uinfo->value.enumerated.name, 2792 texts[uinfo->value.enumerated.item]); 2793 } else if (MADI == hdspm->io_type) { 2794 static char *texts[] = {"Word Clock", "MADI", "TCO", 2795 "Sync In", "None" }; 2796 2797 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2798 uinfo->count = 1; 2799 uinfo->value.enumerated.items = 5; 2800 if (uinfo->value.enumerated.item >= 2801 uinfo->value.enumerated.items) 2802 uinfo->value.enumerated.item = 2803 uinfo->value.enumerated.items - 1; 2804 strcpy(uinfo->value.enumerated.name, 2805 texts[uinfo->value.enumerated.item]); 2806 } 2807 return 0; 2808 } 2809 2810 static int snd_hdspm_get_autosync_ref(struct snd_kcontrol *kcontrol, 2811 struct snd_ctl_elem_value *ucontrol) 2812 { 2813 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2814 2815 ucontrol->value.enumerated.item[0] = hdspm_autosync_ref(hdspm); 2816 return 0; 2817 } 2818 2819 2820 #define HDSPM_LINE_OUT(xname, xindex) \ 2821 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2822 .name = xname, \ 2823 .index = xindex, \ 2824 .info = snd_hdspm_info_line_out, \ 2825 .get = snd_hdspm_get_line_out, \ 2826 .put = snd_hdspm_put_line_out \ 2827 } 2828 2829 static int hdspm_line_out(struct hdspm * hdspm) 2830 { 2831 return (hdspm->control_register & HDSPM_LineOut) ? 1 : 0; 2832 } 2833 2834 2835 static int hdspm_set_line_output(struct hdspm * hdspm, int out) 2836 { 2837 if (out) 2838 hdspm->control_register |= HDSPM_LineOut; 2839 else 2840 hdspm->control_register &= ~HDSPM_LineOut; 2841 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 2842 2843 return 0; 2844 } 2845 2846 #define snd_hdspm_info_line_out snd_ctl_boolean_mono_info 2847 2848 static int snd_hdspm_get_line_out(struct snd_kcontrol *kcontrol, 2849 struct snd_ctl_elem_value *ucontrol) 2850 { 2851 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2852 2853 spin_lock_irq(&hdspm->lock); 2854 ucontrol->value.integer.value[0] = hdspm_line_out(hdspm); 2855 spin_unlock_irq(&hdspm->lock); 2856 return 0; 2857 } 2858 2859 static int snd_hdspm_put_line_out(struct snd_kcontrol *kcontrol, 2860 struct snd_ctl_elem_value *ucontrol) 2861 { 2862 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2863 int change; 2864 unsigned int val; 2865 2866 if (!snd_hdspm_use_is_exclusive(hdspm)) 2867 return -EBUSY; 2868 val = ucontrol->value.integer.value[0] & 1; 2869 spin_lock_irq(&hdspm->lock); 2870 change = (int) val != hdspm_line_out(hdspm); 2871 hdspm_set_line_output(hdspm, val); 2872 spin_unlock_irq(&hdspm->lock); 2873 return change; 2874 } 2875 2876 2877 #define HDSPM_TX_64(xname, xindex) \ 2878 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2879 .name = xname, \ 2880 .index = xindex, \ 2881 .info = snd_hdspm_info_tx_64, \ 2882 .get = snd_hdspm_get_tx_64, \ 2883 .put = snd_hdspm_put_tx_64 \ 2884 } 2885 2886 static int hdspm_tx_64(struct hdspm * hdspm) 2887 { 2888 return (hdspm->control_register & HDSPM_TX_64ch) ? 1 : 0; 2889 } 2890 2891 static int hdspm_set_tx_64(struct hdspm * hdspm, int out) 2892 { 2893 if (out) 2894 hdspm->control_register |= HDSPM_TX_64ch; 2895 else 2896 hdspm->control_register &= ~HDSPM_TX_64ch; 2897 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 2898 2899 return 0; 2900 } 2901 2902 #define snd_hdspm_info_tx_64 snd_ctl_boolean_mono_info 2903 2904 static int snd_hdspm_get_tx_64(struct snd_kcontrol *kcontrol, 2905 struct snd_ctl_elem_value *ucontrol) 2906 { 2907 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2908 2909 spin_lock_irq(&hdspm->lock); 2910 ucontrol->value.integer.value[0] = hdspm_tx_64(hdspm); 2911 spin_unlock_irq(&hdspm->lock); 2912 return 0; 2913 } 2914 2915 static int snd_hdspm_put_tx_64(struct snd_kcontrol *kcontrol, 2916 struct snd_ctl_elem_value *ucontrol) 2917 { 2918 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2919 int change; 2920 unsigned int val; 2921 2922 if (!snd_hdspm_use_is_exclusive(hdspm)) 2923 return -EBUSY; 2924 val = ucontrol->value.integer.value[0] & 1; 2925 spin_lock_irq(&hdspm->lock); 2926 change = (int) val != hdspm_tx_64(hdspm); 2927 hdspm_set_tx_64(hdspm, val); 2928 spin_unlock_irq(&hdspm->lock); 2929 return change; 2930 } 2931 2932 2933 #define HDSPM_C_TMS(xname, xindex) \ 2934 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2935 .name = xname, \ 2936 .index = xindex, \ 2937 .info = snd_hdspm_info_c_tms, \ 2938 .get = snd_hdspm_get_c_tms, \ 2939 .put = snd_hdspm_put_c_tms \ 2940 } 2941 2942 static int hdspm_c_tms(struct hdspm * hdspm) 2943 { 2944 return (hdspm->control_register & HDSPM_clr_tms) ? 1 : 0; 2945 } 2946 2947 static int hdspm_set_c_tms(struct hdspm * hdspm, int out) 2948 { 2949 if (out) 2950 hdspm->control_register |= HDSPM_clr_tms; 2951 else 2952 hdspm->control_register &= ~HDSPM_clr_tms; 2953 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 2954 2955 return 0; 2956 } 2957 2958 #define snd_hdspm_info_c_tms snd_ctl_boolean_mono_info 2959 2960 static int snd_hdspm_get_c_tms(struct snd_kcontrol *kcontrol, 2961 struct snd_ctl_elem_value *ucontrol) 2962 { 2963 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2964 2965 spin_lock_irq(&hdspm->lock); 2966 ucontrol->value.integer.value[0] = hdspm_c_tms(hdspm); 2967 spin_unlock_irq(&hdspm->lock); 2968 return 0; 2969 } 2970 2971 static int snd_hdspm_put_c_tms(struct snd_kcontrol *kcontrol, 2972 struct snd_ctl_elem_value *ucontrol) 2973 { 2974 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2975 int change; 2976 unsigned int val; 2977 2978 if (!snd_hdspm_use_is_exclusive(hdspm)) 2979 return -EBUSY; 2980 val = ucontrol->value.integer.value[0] & 1; 2981 spin_lock_irq(&hdspm->lock); 2982 change = (int) val != hdspm_c_tms(hdspm); 2983 hdspm_set_c_tms(hdspm, val); 2984 spin_unlock_irq(&hdspm->lock); 2985 return change; 2986 } 2987 2988 2989 #define HDSPM_SAFE_MODE(xname, xindex) \ 2990 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2991 .name = xname, \ 2992 .index = xindex, \ 2993 .info = snd_hdspm_info_safe_mode, \ 2994 .get = snd_hdspm_get_safe_mode, \ 2995 .put = snd_hdspm_put_safe_mode \ 2996 } 2997 2998 static int hdspm_safe_mode(struct hdspm * hdspm) 2999 { 3000 return (hdspm->control_register & HDSPM_AutoInp) ? 1 : 0; 3001 } 3002 3003 static int hdspm_set_safe_mode(struct hdspm * hdspm, int out) 3004 { 3005 if (out) 3006 hdspm->control_register |= HDSPM_AutoInp; 3007 else 3008 hdspm->control_register &= ~HDSPM_AutoInp; 3009 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 3010 3011 return 0; 3012 } 3013 3014 #define snd_hdspm_info_safe_mode snd_ctl_boolean_mono_info 3015 3016 static int snd_hdspm_get_safe_mode(struct snd_kcontrol *kcontrol, 3017 struct snd_ctl_elem_value *ucontrol) 3018 { 3019 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3020 3021 spin_lock_irq(&hdspm->lock); 3022 ucontrol->value.integer.value[0] = hdspm_safe_mode(hdspm); 3023 spin_unlock_irq(&hdspm->lock); 3024 return 0; 3025 } 3026 3027 static int snd_hdspm_put_safe_mode(struct snd_kcontrol *kcontrol, 3028 struct snd_ctl_elem_value *ucontrol) 3029 { 3030 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3031 int change; 3032 unsigned int val; 3033 3034 if (!snd_hdspm_use_is_exclusive(hdspm)) 3035 return -EBUSY; 3036 val = ucontrol->value.integer.value[0] & 1; 3037 spin_lock_irq(&hdspm->lock); 3038 change = (int) val != hdspm_safe_mode(hdspm); 3039 hdspm_set_safe_mode(hdspm, val); 3040 spin_unlock_irq(&hdspm->lock); 3041 return change; 3042 } 3043 3044 3045 #define HDSPM_EMPHASIS(xname, xindex) \ 3046 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3047 .name = xname, \ 3048 .index = xindex, \ 3049 .info = snd_hdspm_info_emphasis, \ 3050 .get = snd_hdspm_get_emphasis, \ 3051 .put = snd_hdspm_put_emphasis \ 3052 } 3053 3054 static int hdspm_emphasis(struct hdspm * hdspm) 3055 { 3056 return (hdspm->control_register & HDSPM_Emphasis) ? 1 : 0; 3057 } 3058 3059 static int hdspm_set_emphasis(struct hdspm * hdspm, int emp) 3060 { 3061 if (emp) 3062 hdspm->control_register |= HDSPM_Emphasis; 3063 else 3064 hdspm->control_register &= ~HDSPM_Emphasis; 3065 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 3066 3067 return 0; 3068 } 3069 3070 #define snd_hdspm_info_emphasis snd_ctl_boolean_mono_info 3071 3072 static int snd_hdspm_get_emphasis(struct snd_kcontrol *kcontrol, 3073 struct snd_ctl_elem_value *ucontrol) 3074 { 3075 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3076 3077 spin_lock_irq(&hdspm->lock); 3078 ucontrol->value.enumerated.item[0] = hdspm_emphasis(hdspm); 3079 spin_unlock_irq(&hdspm->lock); 3080 return 0; 3081 } 3082 3083 static int snd_hdspm_put_emphasis(struct snd_kcontrol *kcontrol, 3084 struct snd_ctl_elem_value *ucontrol) 3085 { 3086 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3087 int change; 3088 unsigned int val; 3089 3090 if (!snd_hdspm_use_is_exclusive(hdspm)) 3091 return -EBUSY; 3092 val = ucontrol->value.integer.value[0] & 1; 3093 spin_lock_irq(&hdspm->lock); 3094 change = (int) val != hdspm_emphasis(hdspm); 3095 hdspm_set_emphasis(hdspm, val); 3096 spin_unlock_irq(&hdspm->lock); 3097 return change; 3098 } 3099 3100 3101 #define HDSPM_DOLBY(xname, xindex) \ 3102 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3103 .name = xname, \ 3104 .index = xindex, \ 3105 .info = snd_hdspm_info_dolby, \ 3106 .get = snd_hdspm_get_dolby, \ 3107 .put = snd_hdspm_put_dolby \ 3108 } 3109 3110 static int hdspm_dolby(struct hdspm * hdspm) 3111 { 3112 return (hdspm->control_register & HDSPM_Dolby) ? 1 : 0; 3113 } 3114 3115 static int hdspm_set_dolby(struct hdspm * hdspm, int dol) 3116 { 3117 if (dol) 3118 hdspm->control_register |= HDSPM_Dolby; 3119 else 3120 hdspm->control_register &= ~HDSPM_Dolby; 3121 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 3122 3123 return 0; 3124 } 3125 3126 #define snd_hdspm_info_dolby snd_ctl_boolean_mono_info 3127 3128 static int snd_hdspm_get_dolby(struct snd_kcontrol *kcontrol, 3129 struct snd_ctl_elem_value *ucontrol) 3130 { 3131 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3132 3133 spin_lock_irq(&hdspm->lock); 3134 ucontrol->value.enumerated.item[0] = hdspm_dolby(hdspm); 3135 spin_unlock_irq(&hdspm->lock); 3136 return 0; 3137 } 3138 3139 static int snd_hdspm_put_dolby(struct snd_kcontrol *kcontrol, 3140 struct snd_ctl_elem_value *ucontrol) 3141 { 3142 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3143 int change; 3144 unsigned int val; 3145 3146 if (!snd_hdspm_use_is_exclusive(hdspm)) 3147 return -EBUSY; 3148 val = ucontrol->value.integer.value[0] & 1; 3149 spin_lock_irq(&hdspm->lock); 3150 change = (int) val != hdspm_dolby(hdspm); 3151 hdspm_set_dolby(hdspm, val); 3152 spin_unlock_irq(&hdspm->lock); 3153 return change; 3154 } 3155 3156 3157 #define HDSPM_PROFESSIONAL(xname, xindex) \ 3158 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3159 .name = xname, \ 3160 .index = xindex, \ 3161 .info = snd_hdspm_info_professional, \ 3162 .get = snd_hdspm_get_professional, \ 3163 .put = snd_hdspm_put_professional \ 3164 } 3165 3166 static int hdspm_professional(struct hdspm * hdspm) 3167 { 3168 return (hdspm->control_register & HDSPM_Professional) ? 1 : 0; 3169 } 3170 3171 static int hdspm_set_professional(struct hdspm * hdspm, int dol) 3172 { 3173 if (dol) 3174 hdspm->control_register |= HDSPM_Professional; 3175 else 3176 hdspm->control_register &= ~HDSPM_Professional; 3177 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 3178 3179 return 0; 3180 } 3181 3182 #define snd_hdspm_info_professional snd_ctl_boolean_mono_info 3183 3184 static int snd_hdspm_get_professional(struct snd_kcontrol *kcontrol, 3185 struct snd_ctl_elem_value *ucontrol) 3186 { 3187 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3188 3189 spin_lock_irq(&hdspm->lock); 3190 ucontrol->value.enumerated.item[0] = hdspm_professional(hdspm); 3191 spin_unlock_irq(&hdspm->lock); 3192 return 0; 3193 } 3194 3195 static int snd_hdspm_put_professional(struct snd_kcontrol *kcontrol, 3196 struct snd_ctl_elem_value *ucontrol) 3197 { 3198 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3199 int change; 3200 unsigned int val; 3201 3202 if (!snd_hdspm_use_is_exclusive(hdspm)) 3203 return -EBUSY; 3204 val = ucontrol->value.integer.value[0] & 1; 3205 spin_lock_irq(&hdspm->lock); 3206 change = (int) val != hdspm_professional(hdspm); 3207 hdspm_set_professional(hdspm, val); 3208 spin_unlock_irq(&hdspm->lock); 3209 return change; 3210 } 3211 3212 #define HDSPM_INPUT_SELECT(xname, xindex) \ 3213 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3214 .name = xname, \ 3215 .index = xindex, \ 3216 .info = snd_hdspm_info_input_select, \ 3217 .get = snd_hdspm_get_input_select, \ 3218 .put = snd_hdspm_put_input_select \ 3219 } 3220 3221 static int hdspm_input_select(struct hdspm * hdspm) 3222 { 3223 return (hdspm->control_register & HDSPM_InputSelect0) ? 1 : 0; 3224 } 3225 3226 static int hdspm_set_input_select(struct hdspm * hdspm, int out) 3227 { 3228 if (out) 3229 hdspm->control_register |= HDSPM_InputSelect0; 3230 else 3231 hdspm->control_register &= ~HDSPM_InputSelect0; 3232 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 3233 3234 return 0; 3235 } 3236 3237 static int snd_hdspm_info_input_select(struct snd_kcontrol *kcontrol, 3238 struct snd_ctl_elem_info *uinfo) 3239 { 3240 static char *texts[] = { "optical", "coaxial" }; 3241 3242 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 3243 uinfo->count = 1; 3244 uinfo->value.enumerated.items = 2; 3245 3246 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 3247 uinfo->value.enumerated.item = 3248 uinfo->value.enumerated.items - 1; 3249 strcpy(uinfo->value.enumerated.name, 3250 texts[uinfo->value.enumerated.item]); 3251 3252 return 0; 3253 } 3254 3255 static int snd_hdspm_get_input_select(struct snd_kcontrol *kcontrol, 3256 struct snd_ctl_elem_value *ucontrol) 3257 { 3258 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3259 3260 spin_lock_irq(&hdspm->lock); 3261 ucontrol->value.enumerated.item[0] = hdspm_input_select(hdspm); 3262 spin_unlock_irq(&hdspm->lock); 3263 return 0; 3264 } 3265 3266 static int snd_hdspm_put_input_select(struct snd_kcontrol *kcontrol, 3267 struct snd_ctl_elem_value *ucontrol) 3268 { 3269 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3270 int change; 3271 unsigned int val; 3272 3273 if (!snd_hdspm_use_is_exclusive(hdspm)) 3274 return -EBUSY; 3275 val = ucontrol->value.integer.value[0] & 1; 3276 spin_lock_irq(&hdspm->lock); 3277 change = (int) val != hdspm_input_select(hdspm); 3278 hdspm_set_input_select(hdspm, val); 3279 spin_unlock_irq(&hdspm->lock); 3280 return change; 3281 } 3282 3283 3284 #define HDSPM_DS_WIRE(xname, xindex) \ 3285 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3286 .name = xname, \ 3287 .index = xindex, \ 3288 .info = snd_hdspm_info_ds_wire, \ 3289 .get = snd_hdspm_get_ds_wire, \ 3290 .put = snd_hdspm_put_ds_wire \ 3291 } 3292 3293 static int hdspm_ds_wire(struct hdspm * hdspm) 3294 { 3295 return (hdspm->control_register & HDSPM_DS_DoubleWire) ? 1 : 0; 3296 } 3297 3298 static int hdspm_set_ds_wire(struct hdspm * hdspm, int ds) 3299 { 3300 if (ds) 3301 hdspm->control_register |= HDSPM_DS_DoubleWire; 3302 else 3303 hdspm->control_register &= ~HDSPM_DS_DoubleWire; 3304 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 3305 3306 return 0; 3307 } 3308 3309 static int snd_hdspm_info_ds_wire(struct snd_kcontrol *kcontrol, 3310 struct snd_ctl_elem_info *uinfo) 3311 { 3312 static char *texts[] = { "Single", "Double" }; 3313 3314 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 3315 uinfo->count = 1; 3316 uinfo->value.enumerated.items = 2; 3317 3318 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 3319 uinfo->value.enumerated.item = 3320 uinfo->value.enumerated.items - 1; 3321 strcpy(uinfo->value.enumerated.name, 3322 texts[uinfo->value.enumerated.item]); 3323 3324 return 0; 3325 } 3326 3327 static int snd_hdspm_get_ds_wire(struct snd_kcontrol *kcontrol, 3328 struct snd_ctl_elem_value *ucontrol) 3329 { 3330 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3331 3332 spin_lock_irq(&hdspm->lock); 3333 ucontrol->value.enumerated.item[0] = hdspm_ds_wire(hdspm); 3334 spin_unlock_irq(&hdspm->lock); 3335 return 0; 3336 } 3337 3338 static int snd_hdspm_put_ds_wire(struct snd_kcontrol *kcontrol, 3339 struct snd_ctl_elem_value *ucontrol) 3340 { 3341 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3342 int change; 3343 unsigned int val; 3344 3345 if (!snd_hdspm_use_is_exclusive(hdspm)) 3346 return -EBUSY; 3347 val = ucontrol->value.integer.value[0] & 1; 3348 spin_lock_irq(&hdspm->lock); 3349 change = (int) val != hdspm_ds_wire(hdspm); 3350 hdspm_set_ds_wire(hdspm, val); 3351 spin_unlock_irq(&hdspm->lock); 3352 return change; 3353 } 3354 3355 3356 #define HDSPM_QS_WIRE(xname, xindex) \ 3357 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3358 .name = xname, \ 3359 .index = xindex, \ 3360 .info = snd_hdspm_info_qs_wire, \ 3361 .get = snd_hdspm_get_qs_wire, \ 3362 .put = snd_hdspm_put_qs_wire \ 3363 } 3364 3365 static int hdspm_qs_wire(struct hdspm * hdspm) 3366 { 3367 if (hdspm->control_register & HDSPM_QS_DoubleWire) 3368 return 1; 3369 if (hdspm->control_register & HDSPM_QS_QuadWire) 3370 return 2; 3371 return 0; 3372 } 3373 3374 static int hdspm_set_qs_wire(struct hdspm * hdspm, int mode) 3375 { 3376 hdspm->control_register &= ~(HDSPM_QS_DoubleWire | HDSPM_QS_QuadWire); 3377 switch (mode) { 3378 case 0: 3379 break; 3380 case 1: 3381 hdspm->control_register |= HDSPM_QS_DoubleWire; 3382 break; 3383 case 2: 3384 hdspm->control_register |= HDSPM_QS_QuadWire; 3385 break; 3386 } 3387 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 3388 3389 return 0; 3390 } 3391 3392 static int snd_hdspm_info_qs_wire(struct snd_kcontrol *kcontrol, 3393 struct snd_ctl_elem_info *uinfo) 3394 { 3395 static char *texts[] = { "Single", "Double", "Quad" }; 3396 3397 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 3398 uinfo->count = 1; 3399 uinfo->value.enumerated.items = 3; 3400 3401 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 3402 uinfo->value.enumerated.item = 3403 uinfo->value.enumerated.items - 1; 3404 strcpy(uinfo->value.enumerated.name, 3405 texts[uinfo->value.enumerated.item]); 3406 3407 return 0; 3408 } 3409 3410 static int snd_hdspm_get_qs_wire(struct snd_kcontrol *kcontrol, 3411 struct snd_ctl_elem_value *ucontrol) 3412 { 3413 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3414 3415 spin_lock_irq(&hdspm->lock); 3416 ucontrol->value.enumerated.item[0] = hdspm_qs_wire(hdspm); 3417 spin_unlock_irq(&hdspm->lock); 3418 return 0; 3419 } 3420 3421 static int snd_hdspm_put_qs_wire(struct snd_kcontrol *kcontrol, 3422 struct snd_ctl_elem_value *ucontrol) 3423 { 3424 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3425 int change; 3426 int val; 3427 3428 if (!snd_hdspm_use_is_exclusive(hdspm)) 3429 return -EBUSY; 3430 val = ucontrol->value.integer.value[0]; 3431 if (val < 0) 3432 val = 0; 3433 if (val > 2) 3434 val = 2; 3435 spin_lock_irq(&hdspm->lock); 3436 change = val != hdspm_qs_wire(hdspm); 3437 hdspm_set_qs_wire(hdspm, val); 3438 spin_unlock_irq(&hdspm->lock); 3439 return change; 3440 } 3441 3442 #define HDSPM_MADI_SPEEDMODE(xname, xindex) \ 3443 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3444 .name = xname, \ 3445 .index = xindex, \ 3446 .info = snd_hdspm_info_madi_speedmode, \ 3447 .get = snd_hdspm_get_madi_speedmode, \ 3448 .put = snd_hdspm_put_madi_speedmode \ 3449 } 3450 3451 static int hdspm_madi_speedmode(struct hdspm *hdspm) 3452 { 3453 if (hdspm->control_register & HDSPM_QuadSpeed) 3454 return 2; 3455 if (hdspm->control_register & HDSPM_DoubleSpeed) 3456 return 1; 3457 return 0; 3458 } 3459 3460 static int hdspm_set_madi_speedmode(struct hdspm *hdspm, int mode) 3461 { 3462 hdspm->control_register &= ~(HDSPM_DoubleSpeed | HDSPM_QuadSpeed); 3463 switch (mode) { 3464 case 0: 3465 break; 3466 case 1: 3467 hdspm->control_register |= HDSPM_DoubleSpeed; 3468 break; 3469 case 2: 3470 hdspm->control_register |= HDSPM_QuadSpeed; 3471 break; 3472 } 3473 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 3474 3475 return 0; 3476 } 3477 3478 static int snd_hdspm_info_madi_speedmode(struct snd_kcontrol *kcontrol, 3479 struct snd_ctl_elem_info *uinfo) 3480 { 3481 static char *texts[] = { "Single", "Double", "Quad" }; 3482 3483 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 3484 uinfo->count = 1; 3485 uinfo->value.enumerated.items = 3; 3486 3487 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 3488 uinfo->value.enumerated.item = 3489 uinfo->value.enumerated.items - 1; 3490 strcpy(uinfo->value.enumerated.name, 3491 texts[uinfo->value.enumerated.item]); 3492 3493 return 0; 3494 } 3495 3496 static int snd_hdspm_get_madi_speedmode(struct snd_kcontrol *kcontrol, 3497 struct snd_ctl_elem_value *ucontrol) 3498 { 3499 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3500 3501 spin_lock_irq(&hdspm->lock); 3502 ucontrol->value.enumerated.item[0] = hdspm_madi_speedmode(hdspm); 3503 spin_unlock_irq(&hdspm->lock); 3504 return 0; 3505 } 3506 3507 static int snd_hdspm_put_madi_speedmode(struct snd_kcontrol *kcontrol, 3508 struct snd_ctl_elem_value *ucontrol) 3509 { 3510 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3511 int change; 3512 int val; 3513 3514 if (!snd_hdspm_use_is_exclusive(hdspm)) 3515 return -EBUSY; 3516 val = ucontrol->value.integer.value[0]; 3517 if (val < 0) 3518 val = 0; 3519 if (val > 2) 3520 val = 2; 3521 spin_lock_irq(&hdspm->lock); 3522 change = val != hdspm_madi_speedmode(hdspm); 3523 hdspm_set_madi_speedmode(hdspm, val); 3524 spin_unlock_irq(&hdspm->lock); 3525 return change; 3526 } 3527 3528 #define HDSPM_MIXER(xname, xindex) \ 3529 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \ 3530 .name = xname, \ 3531 .index = xindex, \ 3532 .device = 0, \ 3533 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \ 3534 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3535 .info = snd_hdspm_info_mixer, \ 3536 .get = snd_hdspm_get_mixer, \ 3537 .put = snd_hdspm_put_mixer \ 3538 } 3539 3540 static int snd_hdspm_info_mixer(struct snd_kcontrol *kcontrol, 3541 struct snd_ctl_elem_info *uinfo) 3542 { 3543 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 3544 uinfo->count = 3; 3545 uinfo->value.integer.min = 0; 3546 uinfo->value.integer.max = 65535; 3547 uinfo->value.integer.step = 1; 3548 return 0; 3549 } 3550 3551 static int snd_hdspm_get_mixer(struct snd_kcontrol *kcontrol, 3552 struct snd_ctl_elem_value *ucontrol) 3553 { 3554 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3555 int source; 3556 int destination; 3557 3558 source = ucontrol->value.integer.value[0]; 3559 if (source < 0) 3560 source = 0; 3561 else if (source >= 2 * HDSPM_MAX_CHANNELS) 3562 source = 2 * HDSPM_MAX_CHANNELS - 1; 3563 3564 destination = ucontrol->value.integer.value[1]; 3565 if (destination < 0) 3566 destination = 0; 3567 else if (destination >= HDSPM_MAX_CHANNELS) 3568 destination = HDSPM_MAX_CHANNELS - 1; 3569 3570 spin_lock_irq(&hdspm->lock); 3571 if (source >= HDSPM_MAX_CHANNELS) 3572 ucontrol->value.integer.value[2] = 3573 hdspm_read_pb_gain(hdspm, destination, 3574 source - HDSPM_MAX_CHANNELS); 3575 else 3576 ucontrol->value.integer.value[2] = 3577 hdspm_read_in_gain(hdspm, destination, source); 3578 3579 spin_unlock_irq(&hdspm->lock); 3580 3581 return 0; 3582 } 3583 3584 static int snd_hdspm_put_mixer(struct snd_kcontrol *kcontrol, 3585 struct snd_ctl_elem_value *ucontrol) 3586 { 3587 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3588 int change; 3589 int source; 3590 int destination; 3591 int gain; 3592 3593 if (!snd_hdspm_use_is_exclusive(hdspm)) 3594 return -EBUSY; 3595 3596 source = ucontrol->value.integer.value[0]; 3597 destination = ucontrol->value.integer.value[1]; 3598 3599 if (source < 0 || source >= 2 * HDSPM_MAX_CHANNELS) 3600 return -1; 3601 if (destination < 0 || destination >= HDSPM_MAX_CHANNELS) 3602 return -1; 3603 3604 gain = ucontrol->value.integer.value[2]; 3605 3606 spin_lock_irq(&hdspm->lock); 3607 3608 if (source >= HDSPM_MAX_CHANNELS) 3609 change = gain != hdspm_read_pb_gain(hdspm, destination, 3610 source - 3611 HDSPM_MAX_CHANNELS); 3612 else 3613 change = gain != hdspm_read_in_gain(hdspm, destination, 3614 source); 3615 3616 if (change) { 3617 if (source >= HDSPM_MAX_CHANNELS) 3618 hdspm_write_pb_gain(hdspm, destination, 3619 source - HDSPM_MAX_CHANNELS, 3620 gain); 3621 else 3622 hdspm_write_in_gain(hdspm, destination, source, 3623 gain); 3624 } 3625 spin_unlock_irq(&hdspm->lock); 3626 3627 return change; 3628 } 3629 3630 /* The simple mixer control(s) provide gain control for the 3631 basic 1:1 mappings of playback streams to output 3632 streams. 3633 */ 3634 3635 #define HDSPM_PLAYBACK_MIXER \ 3636 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3637 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_WRITE | \ 3638 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3639 .info = snd_hdspm_info_playback_mixer, \ 3640 .get = snd_hdspm_get_playback_mixer, \ 3641 .put = snd_hdspm_put_playback_mixer \ 3642 } 3643 3644 static int snd_hdspm_info_playback_mixer(struct snd_kcontrol *kcontrol, 3645 struct snd_ctl_elem_info *uinfo) 3646 { 3647 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 3648 uinfo->count = 1; 3649 uinfo->value.integer.min = 0; 3650 uinfo->value.integer.max = 64; 3651 uinfo->value.integer.step = 1; 3652 return 0; 3653 } 3654 3655 static int snd_hdspm_get_playback_mixer(struct snd_kcontrol *kcontrol, 3656 struct snd_ctl_elem_value *ucontrol) 3657 { 3658 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3659 int channel; 3660 3661 channel = ucontrol->id.index - 1; 3662 3663 if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS)) 3664 return -EINVAL; 3665 3666 spin_lock_irq(&hdspm->lock); 3667 ucontrol->value.integer.value[0] = 3668 (hdspm_read_pb_gain(hdspm, channel, channel)*64)/UNITY_GAIN; 3669 spin_unlock_irq(&hdspm->lock); 3670 3671 return 0; 3672 } 3673 3674 static int snd_hdspm_put_playback_mixer(struct snd_kcontrol *kcontrol, 3675 struct snd_ctl_elem_value *ucontrol) 3676 { 3677 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3678 int change; 3679 int channel; 3680 int gain; 3681 3682 if (!snd_hdspm_use_is_exclusive(hdspm)) 3683 return -EBUSY; 3684 3685 channel = ucontrol->id.index - 1; 3686 3687 if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS)) 3688 return -EINVAL; 3689 3690 gain = ucontrol->value.integer.value[0]*UNITY_GAIN/64; 3691 3692 spin_lock_irq(&hdspm->lock); 3693 change = 3694 gain != hdspm_read_pb_gain(hdspm, channel, 3695 channel); 3696 if (change) 3697 hdspm_write_pb_gain(hdspm, channel, channel, 3698 gain); 3699 spin_unlock_irq(&hdspm->lock); 3700 return change; 3701 } 3702 3703 #define HDSPM_SYNC_CHECK(xname, xindex) \ 3704 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3705 .name = xname, \ 3706 .private_value = xindex, \ 3707 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3708 .info = snd_hdspm_info_sync_check, \ 3709 .get = snd_hdspm_get_sync_check \ 3710 } 3711 3712 3713 static int snd_hdspm_info_sync_check(struct snd_kcontrol *kcontrol, 3714 struct snd_ctl_elem_info *uinfo) 3715 { 3716 static char *texts[] = { "No Lock", "Lock", "Sync", "N/A" }; 3717 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 3718 uinfo->count = 1; 3719 uinfo->value.enumerated.items = 4; 3720 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 3721 uinfo->value.enumerated.item = 3722 uinfo->value.enumerated.items - 1; 3723 strcpy(uinfo->value.enumerated.name, 3724 texts[uinfo->value.enumerated.item]); 3725 return 0; 3726 } 3727 3728 static int hdspm_wc_sync_check(struct hdspm *hdspm) 3729 { 3730 int status, status2; 3731 3732 switch (hdspm->io_type) { 3733 case AES32: 3734 status = hdspm_read(hdspm, HDSPM_statusRegister); 3735 if (status & HDSPM_wcSync) 3736 return 2; 3737 else if (status & HDSPM_wcLock) 3738 return 1; 3739 return 0; 3740 break; 3741 3742 case MADI: 3743 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 3744 if (status2 & HDSPM_wcLock) { 3745 if (status2 & HDSPM_wcSync) 3746 return 2; 3747 else 3748 return 1; 3749 } 3750 return 0; 3751 break; 3752 3753 case RayDAT: 3754 case AIO: 3755 status = hdspm_read(hdspm, HDSPM_statusRegister); 3756 3757 if (status & 0x2000000) 3758 return 2; 3759 else if (status & 0x1000000) 3760 return 1; 3761 return 0; 3762 3763 break; 3764 3765 case MADIface: 3766 break; 3767 } 3768 3769 3770 return 3; 3771 } 3772 3773 3774 static int hdspm_madi_sync_check(struct hdspm *hdspm) 3775 { 3776 int status = hdspm_read(hdspm, HDSPM_statusRegister); 3777 if (status & HDSPM_madiLock) { 3778 if (status & HDSPM_madiSync) 3779 return 2; 3780 else 3781 return 1; 3782 } 3783 return 0; 3784 } 3785 3786 3787 static int hdspm_s1_sync_check(struct hdspm *hdspm, int idx) 3788 { 3789 int status, lock, sync; 3790 3791 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1); 3792 3793 lock = (status & (0x1<<idx)) ? 1 : 0; 3794 sync = (status & (0x100<<idx)) ? 1 : 0; 3795 3796 if (lock && sync) 3797 return 2; 3798 else if (lock) 3799 return 1; 3800 return 0; 3801 } 3802 3803 3804 static int hdspm_sync_in_sync_check(struct hdspm *hdspm) 3805 { 3806 int status, lock = 0, sync = 0; 3807 3808 switch (hdspm->io_type) { 3809 case RayDAT: 3810 case AIO: 3811 status = hdspm_read(hdspm, HDSPM_RD_STATUS_3); 3812 lock = (status & 0x400) ? 1 : 0; 3813 sync = (status & 0x800) ? 1 : 0; 3814 break; 3815 3816 case MADI: 3817 case AES32: 3818 status = hdspm_read(hdspm, HDSPM_statusRegister2); 3819 lock = (status & HDSPM_syncInLock) ? 1 : 0; 3820 sync = (status & HDSPM_syncInSync) ? 1 : 0; 3821 break; 3822 3823 case MADIface: 3824 break; 3825 } 3826 3827 if (lock && sync) 3828 return 2; 3829 else if (lock) 3830 return 1; 3831 3832 return 0; 3833 } 3834 3835 static int hdspm_aes_sync_check(struct hdspm *hdspm, int idx) 3836 { 3837 int status2, lock, sync; 3838 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 3839 3840 lock = (status2 & (0x0080 >> idx)) ? 1 : 0; 3841 sync = (status2 & (0x8000 >> idx)) ? 1 : 0; 3842 3843 if (sync) 3844 return 2; 3845 else if (lock) 3846 return 1; 3847 return 0; 3848 } 3849 3850 3851 static int hdspm_tco_sync_check(struct hdspm *hdspm) 3852 { 3853 int status; 3854 3855 if (hdspm->tco) { 3856 switch (hdspm->io_type) { 3857 case MADI: 3858 case AES32: 3859 status = hdspm_read(hdspm, HDSPM_statusRegister); 3860 if (status & HDSPM_tcoLock) { 3861 if (status & HDSPM_tcoSync) 3862 return 2; 3863 else 3864 return 1; 3865 } 3866 return 0; 3867 3868 break; 3869 3870 case RayDAT: 3871 case AIO: 3872 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1); 3873 3874 if (status & 0x8000000) 3875 return 2; /* Sync */ 3876 if (status & 0x4000000) 3877 return 1; /* Lock */ 3878 return 0; /* No signal */ 3879 break; 3880 3881 default: 3882 break; 3883 } 3884 } 3885 3886 return 3; /* N/A */ 3887 } 3888 3889 3890 static int snd_hdspm_get_sync_check(struct snd_kcontrol *kcontrol, 3891 struct snd_ctl_elem_value *ucontrol) 3892 { 3893 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3894 int val = -1; 3895 3896 switch (hdspm->io_type) { 3897 case RayDAT: 3898 switch (kcontrol->private_value) { 3899 case 0: /* WC */ 3900 val = hdspm_wc_sync_check(hdspm); break; 3901 case 7: /* TCO */ 3902 val = hdspm_tco_sync_check(hdspm); break; 3903 case 8: /* SYNC IN */ 3904 val = hdspm_sync_in_sync_check(hdspm); break; 3905 default: 3906 val = hdspm_s1_sync_check(hdspm, ucontrol->id.index-1); 3907 } 3908 3909 case AIO: 3910 switch (kcontrol->private_value) { 3911 case 0: /* WC */ 3912 val = hdspm_wc_sync_check(hdspm); break; 3913 case 4: /* TCO */ 3914 val = hdspm_tco_sync_check(hdspm); break; 3915 case 5: /* SYNC IN */ 3916 val = hdspm_sync_in_sync_check(hdspm); break; 3917 default: 3918 val = hdspm_s1_sync_check(hdspm, ucontrol->id.index-1); 3919 } 3920 3921 case MADI: 3922 switch (kcontrol->private_value) { 3923 case 0: /* WC */ 3924 val = hdspm_wc_sync_check(hdspm); break; 3925 case 1: /* MADI */ 3926 val = hdspm_madi_sync_check(hdspm); break; 3927 case 2: /* TCO */ 3928 val = hdspm_tco_sync_check(hdspm); break; 3929 case 3: /* SYNC_IN */ 3930 val = hdspm_sync_in_sync_check(hdspm); break; 3931 } 3932 3933 case MADIface: 3934 val = hdspm_madi_sync_check(hdspm); /* MADI */ 3935 break; 3936 3937 case AES32: 3938 switch (kcontrol->private_value) { 3939 case 0: /* WC */ 3940 val = hdspm_wc_sync_check(hdspm); break; 3941 case 9: /* TCO */ 3942 val = hdspm_tco_sync_check(hdspm); break; 3943 case 10 /* SYNC IN */: 3944 val = hdspm_sync_in_sync_check(hdspm); break; 3945 default: /* AES1 to AES8 */ 3946 val = hdspm_aes_sync_check(hdspm, 3947 kcontrol->private_value-1); 3948 } 3949 3950 } 3951 3952 if (-1 == val) 3953 val = 3; 3954 3955 ucontrol->value.enumerated.item[0] = val; 3956 return 0; 3957 } 3958 3959 3960 3961 /** 3962 * TCO controls 3963 **/ 3964 static void hdspm_tco_write(struct hdspm *hdspm) 3965 { 3966 unsigned int tc[4] = { 0, 0, 0, 0}; 3967 3968 switch (hdspm->tco->input) { 3969 case 0: 3970 tc[2] |= HDSPM_TCO2_set_input_MSB; 3971 break; 3972 case 1: 3973 tc[2] |= HDSPM_TCO2_set_input_LSB; 3974 break; 3975 default: 3976 break; 3977 } 3978 3979 switch (hdspm->tco->framerate) { 3980 case 1: 3981 tc[1] |= HDSPM_TCO1_LTC_Format_LSB; 3982 break; 3983 case 2: 3984 tc[1] |= HDSPM_TCO1_LTC_Format_MSB; 3985 break; 3986 case 3: 3987 tc[1] |= HDSPM_TCO1_LTC_Format_MSB + 3988 HDSPM_TCO1_set_drop_frame_flag; 3989 break; 3990 case 4: 3991 tc[1] |= HDSPM_TCO1_LTC_Format_LSB + 3992 HDSPM_TCO1_LTC_Format_MSB; 3993 break; 3994 case 5: 3995 tc[1] |= HDSPM_TCO1_LTC_Format_LSB + 3996 HDSPM_TCO1_LTC_Format_MSB + 3997 HDSPM_TCO1_set_drop_frame_flag; 3998 break; 3999 default: 4000 break; 4001 } 4002 4003 switch (hdspm->tco->wordclock) { 4004 case 1: 4005 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_LSB; 4006 break; 4007 case 2: 4008 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_MSB; 4009 break; 4010 default: 4011 break; 4012 } 4013 4014 switch (hdspm->tco->samplerate) { 4015 case 1: 4016 tc[2] |= HDSPM_TCO2_set_freq; 4017 break; 4018 case 2: 4019 tc[2] |= HDSPM_TCO2_set_freq_from_app; 4020 break; 4021 default: 4022 break; 4023 } 4024 4025 switch (hdspm->tco->pull) { 4026 case 1: 4027 tc[2] |= HDSPM_TCO2_set_pull_up; 4028 break; 4029 case 2: 4030 tc[2] |= HDSPM_TCO2_set_pull_down; 4031 break; 4032 case 3: 4033 tc[2] |= HDSPM_TCO2_set_pull_up + HDSPM_TCO2_set_01_4; 4034 break; 4035 case 4: 4036 tc[2] |= HDSPM_TCO2_set_pull_down + HDSPM_TCO2_set_01_4; 4037 break; 4038 default: 4039 break; 4040 } 4041 4042 if (1 == hdspm->tco->term) { 4043 tc[2] |= HDSPM_TCO2_set_term_75R; 4044 } 4045 4046 hdspm_write(hdspm, HDSPM_WR_TCO, tc[0]); 4047 hdspm_write(hdspm, HDSPM_WR_TCO+4, tc[1]); 4048 hdspm_write(hdspm, HDSPM_WR_TCO+8, tc[2]); 4049 hdspm_write(hdspm, HDSPM_WR_TCO+12, tc[3]); 4050 } 4051 4052 4053 #define HDSPM_TCO_SAMPLE_RATE(xname, xindex) \ 4054 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4055 .name = xname, \ 4056 .index = xindex, \ 4057 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 4058 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 4059 .info = snd_hdspm_info_tco_sample_rate, \ 4060 .get = snd_hdspm_get_tco_sample_rate, \ 4061 .put = snd_hdspm_put_tco_sample_rate \ 4062 } 4063 4064 static int snd_hdspm_info_tco_sample_rate(struct snd_kcontrol *kcontrol, 4065 struct snd_ctl_elem_info *uinfo) 4066 { 4067 static char *texts[] = { "44.1 kHz", "48 kHz" }; 4068 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 4069 uinfo->count = 1; 4070 uinfo->value.enumerated.items = 2; 4071 4072 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 4073 uinfo->value.enumerated.item = 4074 uinfo->value.enumerated.items - 1; 4075 4076 strcpy(uinfo->value.enumerated.name, 4077 texts[uinfo->value.enumerated.item]); 4078 4079 return 0; 4080 } 4081 4082 static int snd_hdspm_get_tco_sample_rate(struct snd_kcontrol *kcontrol, 4083 struct snd_ctl_elem_value *ucontrol) 4084 { 4085 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4086 4087 ucontrol->value.enumerated.item[0] = hdspm->tco->samplerate; 4088 4089 return 0; 4090 } 4091 4092 static int snd_hdspm_put_tco_sample_rate(struct snd_kcontrol *kcontrol, 4093 struct snd_ctl_elem_value *ucontrol) 4094 { 4095 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4096 4097 if (hdspm->tco->samplerate != ucontrol->value.enumerated.item[0]) { 4098 hdspm->tco->samplerate = ucontrol->value.enumerated.item[0]; 4099 4100 hdspm_tco_write(hdspm); 4101 4102 return 1; 4103 } 4104 4105 return 0; 4106 } 4107 4108 4109 #define HDSPM_TCO_PULL(xname, xindex) \ 4110 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4111 .name = xname, \ 4112 .index = xindex, \ 4113 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 4114 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 4115 .info = snd_hdspm_info_tco_pull, \ 4116 .get = snd_hdspm_get_tco_pull, \ 4117 .put = snd_hdspm_put_tco_pull \ 4118 } 4119 4120 static int snd_hdspm_info_tco_pull(struct snd_kcontrol *kcontrol, 4121 struct snd_ctl_elem_info *uinfo) 4122 { 4123 static char *texts[] = { "0", "+ 0.1 %", "- 0.1 %", "+ 4 %", "- 4 %" }; 4124 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 4125 uinfo->count = 1; 4126 uinfo->value.enumerated.items = 5; 4127 4128 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 4129 uinfo->value.enumerated.item = 4130 uinfo->value.enumerated.items - 1; 4131 4132 strcpy(uinfo->value.enumerated.name, 4133 texts[uinfo->value.enumerated.item]); 4134 4135 return 0; 4136 } 4137 4138 static int snd_hdspm_get_tco_pull(struct snd_kcontrol *kcontrol, 4139 struct snd_ctl_elem_value *ucontrol) 4140 { 4141 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4142 4143 ucontrol->value.enumerated.item[0] = hdspm->tco->pull; 4144 4145 return 0; 4146 } 4147 4148 static int snd_hdspm_put_tco_pull(struct snd_kcontrol *kcontrol, 4149 struct snd_ctl_elem_value *ucontrol) 4150 { 4151 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4152 4153 if (hdspm->tco->pull != ucontrol->value.enumerated.item[0]) { 4154 hdspm->tco->pull = ucontrol->value.enumerated.item[0]; 4155 4156 hdspm_tco_write(hdspm); 4157 4158 return 1; 4159 } 4160 4161 return 0; 4162 } 4163 4164 #define HDSPM_TCO_WCK_CONVERSION(xname, xindex) \ 4165 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4166 .name = xname, \ 4167 .index = xindex, \ 4168 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 4169 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 4170 .info = snd_hdspm_info_tco_wck_conversion, \ 4171 .get = snd_hdspm_get_tco_wck_conversion, \ 4172 .put = snd_hdspm_put_tco_wck_conversion \ 4173 } 4174 4175 static int snd_hdspm_info_tco_wck_conversion(struct snd_kcontrol *kcontrol, 4176 struct snd_ctl_elem_info *uinfo) 4177 { 4178 static char *texts[] = { "1:1", "44.1 -> 48", "48 -> 44.1" }; 4179 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 4180 uinfo->count = 1; 4181 uinfo->value.enumerated.items = 3; 4182 4183 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 4184 uinfo->value.enumerated.item = 4185 uinfo->value.enumerated.items - 1; 4186 4187 strcpy(uinfo->value.enumerated.name, 4188 texts[uinfo->value.enumerated.item]); 4189 4190 return 0; 4191 } 4192 4193 static int snd_hdspm_get_tco_wck_conversion(struct snd_kcontrol *kcontrol, 4194 struct snd_ctl_elem_value *ucontrol) 4195 { 4196 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4197 4198 ucontrol->value.enumerated.item[0] = hdspm->tco->wordclock; 4199 4200 return 0; 4201 } 4202 4203 static int snd_hdspm_put_tco_wck_conversion(struct snd_kcontrol *kcontrol, 4204 struct snd_ctl_elem_value *ucontrol) 4205 { 4206 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4207 4208 if (hdspm->tco->wordclock != ucontrol->value.enumerated.item[0]) { 4209 hdspm->tco->wordclock = ucontrol->value.enumerated.item[0]; 4210 4211 hdspm_tco_write(hdspm); 4212 4213 return 1; 4214 } 4215 4216 return 0; 4217 } 4218 4219 4220 #define HDSPM_TCO_FRAME_RATE(xname, xindex) \ 4221 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4222 .name = xname, \ 4223 .index = xindex, \ 4224 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 4225 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 4226 .info = snd_hdspm_info_tco_frame_rate, \ 4227 .get = snd_hdspm_get_tco_frame_rate, \ 4228 .put = snd_hdspm_put_tco_frame_rate \ 4229 } 4230 4231 static int snd_hdspm_info_tco_frame_rate(struct snd_kcontrol *kcontrol, 4232 struct snd_ctl_elem_info *uinfo) 4233 { 4234 static char *texts[] = { "24 fps", "25 fps", "29.97fps", 4235 "29.97 dfps", "30 fps", "30 dfps" }; 4236 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 4237 uinfo->count = 1; 4238 uinfo->value.enumerated.items = 6; 4239 4240 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 4241 uinfo->value.enumerated.item = 4242 uinfo->value.enumerated.items - 1; 4243 4244 strcpy(uinfo->value.enumerated.name, 4245 texts[uinfo->value.enumerated.item]); 4246 4247 return 0; 4248 } 4249 4250 static int snd_hdspm_get_tco_frame_rate(struct snd_kcontrol *kcontrol, 4251 struct snd_ctl_elem_value *ucontrol) 4252 { 4253 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4254 4255 ucontrol->value.enumerated.item[0] = hdspm->tco->framerate; 4256 4257 return 0; 4258 } 4259 4260 static int snd_hdspm_put_tco_frame_rate(struct snd_kcontrol *kcontrol, 4261 struct snd_ctl_elem_value *ucontrol) 4262 { 4263 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4264 4265 if (hdspm->tco->framerate != ucontrol->value.enumerated.item[0]) { 4266 hdspm->tco->framerate = ucontrol->value.enumerated.item[0]; 4267 4268 hdspm_tco_write(hdspm); 4269 4270 return 1; 4271 } 4272 4273 return 0; 4274 } 4275 4276 4277 #define HDSPM_TCO_SYNC_SOURCE(xname, xindex) \ 4278 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4279 .name = xname, \ 4280 .index = xindex, \ 4281 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 4282 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 4283 .info = snd_hdspm_info_tco_sync_source, \ 4284 .get = snd_hdspm_get_tco_sync_source, \ 4285 .put = snd_hdspm_put_tco_sync_source \ 4286 } 4287 4288 static int snd_hdspm_info_tco_sync_source(struct snd_kcontrol *kcontrol, 4289 struct snd_ctl_elem_info *uinfo) 4290 { 4291 static char *texts[] = { "LTC", "Video", "WCK" }; 4292 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 4293 uinfo->count = 1; 4294 uinfo->value.enumerated.items = 3; 4295 4296 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 4297 uinfo->value.enumerated.item = 4298 uinfo->value.enumerated.items - 1; 4299 4300 strcpy(uinfo->value.enumerated.name, 4301 texts[uinfo->value.enumerated.item]); 4302 4303 return 0; 4304 } 4305 4306 static int snd_hdspm_get_tco_sync_source(struct snd_kcontrol *kcontrol, 4307 struct snd_ctl_elem_value *ucontrol) 4308 { 4309 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4310 4311 ucontrol->value.enumerated.item[0] = hdspm->tco->input; 4312 4313 return 0; 4314 } 4315 4316 static int snd_hdspm_put_tco_sync_source(struct snd_kcontrol *kcontrol, 4317 struct snd_ctl_elem_value *ucontrol) 4318 { 4319 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4320 4321 if (hdspm->tco->input != ucontrol->value.enumerated.item[0]) { 4322 hdspm->tco->input = ucontrol->value.enumerated.item[0]; 4323 4324 hdspm_tco_write(hdspm); 4325 4326 return 1; 4327 } 4328 4329 return 0; 4330 } 4331 4332 4333 #define HDSPM_TCO_WORD_TERM(xname, xindex) \ 4334 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4335 .name = xname, \ 4336 .index = xindex, \ 4337 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 4338 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 4339 .info = snd_hdspm_info_tco_word_term, \ 4340 .get = snd_hdspm_get_tco_word_term, \ 4341 .put = snd_hdspm_put_tco_word_term \ 4342 } 4343 4344 static int snd_hdspm_info_tco_word_term(struct snd_kcontrol *kcontrol, 4345 struct snd_ctl_elem_info *uinfo) 4346 { 4347 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 4348 uinfo->count = 1; 4349 uinfo->value.integer.min = 0; 4350 uinfo->value.integer.max = 1; 4351 4352 return 0; 4353 } 4354 4355 4356 static int snd_hdspm_get_tco_word_term(struct snd_kcontrol *kcontrol, 4357 struct snd_ctl_elem_value *ucontrol) 4358 { 4359 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4360 4361 ucontrol->value.enumerated.item[0] = hdspm->tco->term; 4362 4363 return 0; 4364 } 4365 4366 4367 static int snd_hdspm_put_tco_word_term(struct snd_kcontrol *kcontrol, 4368 struct snd_ctl_elem_value *ucontrol) 4369 { 4370 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4371 4372 if (hdspm->tco->term != ucontrol->value.enumerated.item[0]) { 4373 hdspm->tco->term = ucontrol->value.enumerated.item[0]; 4374 4375 hdspm_tco_write(hdspm); 4376 4377 return 1; 4378 } 4379 4380 return 0; 4381 } 4382 4383 4384 4385 4386 static struct snd_kcontrol_new snd_hdspm_controls_madi[] = { 4387 HDSPM_MIXER("Mixer", 0), 4388 HDSPM_INTERNAL_CLOCK("Internal Clock", 0), 4389 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0), 4390 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0), 4391 HDSPM_AUTOSYNC_REF("AutoSync Reference", 0), 4392 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), 4393 HDSPM_SYNC_CHECK("WC SyncCheck", 0), 4394 HDSPM_SYNC_CHECK("MADI SyncCheck", 1), 4395 HDSPM_SYNC_CHECK("TCO SyncCHeck", 2), 4396 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 3), 4397 HDSPM_LINE_OUT("Line Out", 0), 4398 HDSPM_TX_64("TX 64 channels mode", 0), 4399 HDSPM_C_TMS("Clear Track Marker", 0), 4400 HDSPM_SAFE_MODE("Safe Mode", 0), 4401 HDSPM_INPUT_SELECT("Input Select", 0), 4402 HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0) 4403 }; 4404 4405 4406 static struct snd_kcontrol_new snd_hdspm_controls_madiface[] = { 4407 HDSPM_MIXER("Mixer", 0), 4408 HDSPM_INTERNAL_CLOCK("Internal Clock", 0), 4409 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0), 4410 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), 4411 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0), 4412 HDSPM_SYNC_CHECK("MADI SyncCheck", 0), 4413 HDSPM_TX_64("TX 64 channels mode", 0), 4414 HDSPM_C_TMS("Clear Track Marker", 0), 4415 HDSPM_SAFE_MODE("Safe Mode", 0), 4416 HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0) 4417 }; 4418 4419 static struct snd_kcontrol_new snd_hdspm_controls_aio[] = { 4420 HDSPM_MIXER("Mixer", 0), 4421 HDSPM_INTERNAL_CLOCK("Internal Clock", 0), 4422 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0), 4423 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0), 4424 HDSPM_AUTOSYNC_REF("AutoSync Reference", 0), 4425 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), 4426 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0), 4427 HDSPM_SYNC_CHECK("WC SyncCheck", 0), 4428 HDSPM_SYNC_CHECK("AES SyncCheck", 1), 4429 HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2), 4430 HDSPM_SYNC_CHECK("ADAT SyncCheck", 3), 4431 HDSPM_SYNC_CHECK("TCO SyncCheck", 4), 4432 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 5), 4433 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0), 4434 HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1), 4435 HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2), 4436 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT Frequency", 3), 4437 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 4), 4438 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 5) 4439 4440 /* 4441 HDSPM_INPUT_SELECT("Input Select", 0), 4442 HDSPM_SPDIF_OPTICAL("SPDIF Out Optical", 0), 4443 HDSPM_PROFESSIONAL("SPDIF Out Professional", 0); 4444 HDSPM_SPDIF_IN("SPDIF In", 0); 4445 HDSPM_BREAKOUT_CABLE("Breakout Cable", 0); 4446 HDSPM_INPUT_LEVEL("Input Level", 0); 4447 HDSPM_OUTPUT_LEVEL("Output Level", 0); 4448 HDSPM_PHONES("Phones", 0); 4449 */ 4450 }; 4451 4452 static struct snd_kcontrol_new snd_hdspm_controls_raydat[] = { 4453 HDSPM_MIXER("Mixer", 0), 4454 HDSPM_INTERNAL_CLOCK("Internal Clock", 0), 4455 HDSPM_SYSTEM_CLOCK_MODE("Clock Mode", 0), 4456 HDSPM_PREF_SYNC_REF("Pref Sync Ref", 0), 4457 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), 4458 HDSPM_SYNC_CHECK("WC SyncCheck", 0), 4459 HDSPM_SYNC_CHECK("AES SyncCheck", 1), 4460 HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2), 4461 HDSPM_SYNC_CHECK("ADAT1 SyncCheck", 3), 4462 HDSPM_SYNC_CHECK("ADAT2 SyncCheck", 4), 4463 HDSPM_SYNC_CHECK("ADAT3 SyncCheck", 5), 4464 HDSPM_SYNC_CHECK("ADAT4 SyncCheck", 6), 4465 HDSPM_SYNC_CHECK("TCO SyncCheck", 7), 4466 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 8), 4467 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0), 4468 HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1), 4469 HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2), 4470 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT1 Frequency", 3), 4471 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT2 Frequency", 4), 4472 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT3 Frequency", 5), 4473 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT4 Frequency", 6), 4474 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 7), 4475 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 8) 4476 }; 4477 4478 static struct snd_kcontrol_new snd_hdspm_controls_aes32[] = { 4479 HDSPM_MIXER("Mixer", 0), 4480 HDSPM_INTERNAL_CLOCK("Internal Clock", 0), 4481 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0), 4482 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0), 4483 HDSPM_AUTOSYNC_REF("AutoSync Reference", 0), 4484 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), 4485 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0), 4486 HDSPM_SYNC_CHECK("WC Sync Check", 0), 4487 HDSPM_SYNC_CHECK("AES1 Sync Check", 1), 4488 HDSPM_SYNC_CHECK("AES2 Sync Check", 2), 4489 HDSPM_SYNC_CHECK("AES3 Sync Check", 3), 4490 HDSPM_SYNC_CHECK("AES4 Sync Check", 4), 4491 HDSPM_SYNC_CHECK("AES5 Sync Check", 5), 4492 HDSPM_SYNC_CHECK("AES6 Sync Check", 6), 4493 HDSPM_SYNC_CHECK("AES7 Sync Check", 7), 4494 HDSPM_SYNC_CHECK("AES8 Sync Check", 8), 4495 HDSPM_SYNC_CHECK("TCO Sync Check", 9), 4496 HDSPM_SYNC_CHECK("SYNC IN Sync Check", 10), 4497 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0), 4498 HDSPM_AUTOSYNC_SAMPLE_RATE("AES1 Frequency", 1), 4499 HDSPM_AUTOSYNC_SAMPLE_RATE("AES2 Frequency", 2), 4500 HDSPM_AUTOSYNC_SAMPLE_RATE("AES3 Frequency", 3), 4501 HDSPM_AUTOSYNC_SAMPLE_RATE("AES4 Frequency", 4), 4502 HDSPM_AUTOSYNC_SAMPLE_RATE("AES5 Frequency", 5), 4503 HDSPM_AUTOSYNC_SAMPLE_RATE("AES6 Frequency", 6), 4504 HDSPM_AUTOSYNC_SAMPLE_RATE("AES7 Frequency", 7), 4505 HDSPM_AUTOSYNC_SAMPLE_RATE("AES8 Frequency", 8), 4506 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 9), 4507 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 10), 4508 HDSPM_LINE_OUT("Line Out", 0), 4509 HDSPM_EMPHASIS("Emphasis", 0), 4510 HDSPM_DOLBY("Non Audio", 0), 4511 HDSPM_PROFESSIONAL("Professional", 0), 4512 HDSPM_C_TMS("Clear Track Marker", 0), 4513 HDSPM_DS_WIRE("Double Speed Wire Mode", 0), 4514 HDSPM_QS_WIRE("Quad Speed Wire Mode", 0), 4515 }; 4516 4517 4518 4519 /* Control elements for the optional TCO module */ 4520 static struct snd_kcontrol_new snd_hdspm_controls_tco[] = { 4521 HDSPM_TCO_SAMPLE_RATE("TCO Sample Rate", 0), 4522 HDSPM_TCO_PULL("TCO Pull", 0), 4523 HDSPM_TCO_WCK_CONVERSION("TCO WCK Conversion", 0), 4524 HDSPM_TCO_FRAME_RATE("TCO Frame Rate", 0), 4525 HDSPM_TCO_SYNC_SOURCE("TCO Sync Source", 0), 4526 HDSPM_TCO_WORD_TERM("TCO Word Term", 0) 4527 }; 4528 4529 4530 static struct snd_kcontrol_new snd_hdspm_playback_mixer = HDSPM_PLAYBACK_MIXER; 4531 4532 4533 static int hdspm_update_simple_mixer_controls(struct hdspm * hdspm) 4534 { 4535 int i; 4536 4537 for (i = hdspm->ds_out_channels; i < hdspm->ss_out_channels; ++i) { 4538 if (hdspm->system_sample_rate > 48000) { 4539 hdspm->playback_mixer_ctls[i]->vd[0].access = 4540 SNDRV_CTL_ELEM_ACCESS_INACTIVE | 4541 SNDRV_CTL_ELEM_ACCESS_READ | 4542 SNDRV_CTL_ELEM_ACCESS_VOLATILE; 4543 } else { 4544 hdspm->playback_mixer_ctls[i]->vd[0].access = 4545 SNDRV_CTL_ELEM_ACCESS_READWRITE | 4546 SNDRV_CTL_ELEM_ACCESS_VOLATILE; 4547 } 4548 snd_ctl_notify(hdspm->card, SNDRV_CTL_EVENT_MASK_VALUE | 4549 SNDRV_CTL_EVENT_MASK_INFO, 4550 &hdspm->playback_mixer_ctls[i]->id); 4551 } 4552 4553 return 0; 4554 } 4555 4556 4557 static int snd_hdspm_create_controls(struct snd_card *card, 4558 struct hdspm *hdspm) 4559 { 4560 unsigned int idx, limit; 4561 int err; 4562 struct snd_kcontrol *kctl; 4563 struct snd_kcontrol_new *list = NULL; 4564 4565 switch (hdspm->io_type) { 4566 case MADI: 4567 list = snd_hdspm_controls_madi; 4568 limit = ARRAY_SIZE(snd_hdspm_controls_madi); 4569 break; 4570 case MADIface: 4571 list = snd_hdspm_controls_madiface; 4572 limit = ARRAY_SIZE(snd_hdspm_controls_madiface); 4573 break; 4574 case AIO: 4575 list = snd_hdspm_controls_aio; 4576 limit = ARRAY_SIZE(snd_hdspm_controls_aio); 4577 break; 4578 case RayDAT: 4579 list = snd_hdspm_controls_raydat; 4580 limit = ARRAY_SIZE(snd_hdspm_controls_raydat); 4581 break; 4582 case AES32: 4583 list = snd_hdspm_controls_aes32; 4584 limit = ARRAY_SIZE(snd_hdspm_controls_aes32); 4585 break; 4586 } 4587 4588 if (NULL != list) { 4589 for (idx = 0; idx < limit; idx++) { 4590 err = snd_ctl_add(card, 4591 snd_ctl_new1(&list[idx], hdspm)); 4592 if (err < 0) 4593 return err; 4594 } 4595 } 4596 4597 4598 /* create simple 1:1 playback mixer controls */ 4599 snd_hdspm_playback_mixer.name = "Chn"; 4600 if (hdspm->system_sample_rate >= 128000) { 4601 limit = hdspm->qs_out_channels; 4602 } else if (hdspm->system_sample_rate >= 64000) { 4603 limit = hdspm->ds_out_channels; 4604 } else { 4605 limit = hdspm->ss_out_channels; 4606 } 4607 for (idx = 0; idx < limit; ++idx) { 4608 snd_hdspm_playback_mixer.index = idx + 1; 4609 kctl = snd_ctl_new1(&snd_hdspm_playback_mixer, hdspm); 4610 err = snd_ctl_add(card, kctl); 4611 if (err < 0) 4612 return err; 4613 hdspm->playback_mixer_ctls[idx] = kctl; 4614 } 4615 4616 4617 if (hdspm->tco) { 4618 /* add tco control elements */ 4619 list = snd_hdspm_controls_tco; 4620 limit = ARRAY_SIZE(snd_hdspm_controls_tco); 4621 for (idx = 0; idx < limit; idx++) { 4622 err = snd_ctl_add(card, 4623 snd_ctl_new1(&list[idx], hdspm)); 4624 if (err < 0) 4625 return err; 4626 } 4627 } 4628 4629 return 0; 4630 } 4631 4632 /*------------------------------------------------------------ 4633 /proc interface 4634 ------------------------------------------------------------*/ 4635 4636 static void 4637 snd_hdspm_proc_read_madi(struct snd_info_entry * entry, 4638 struct snd_info_buffer *buffer) 4639 { 4640 struct hdspm *hdspm = entry->private_data; 4641 unsigned int status, status2, control, freq; 4642 4643 char *pref_sync_ref; 4644 char *autosync_ref; 4645 char *system_clock_mode; 4646 char *insel; 4647 int x, x2; 4648 4649 /* TCO stuff */ 4650 int a, ltc, frames, seconds, minutes, hours; 4651 unsigned int period; 4652 u64 freq_const = 0; 4653 u32 rate; 4654 4655 status = hdspm_read(hdspm, HDSPM_statusRegister); 4656 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 4657 control = hdspm->control_register; 4658 freq = hdspm_read(hdspm, HDSPM_timecodeRegister); 4659 4660 snd_iprintf(buffer, "%s (Card #%d) Rev.%x Status2first3bits: %x\n", 4661 hdspm->card_name, hdspm->card->number + 1, 4662 hdspm->firmware_rev, 4663 (status2 & HDSPM_version0) | 4664 (status2 & HDSPM_version1) | (status2 & 4665 HDSPM_version2)); 4666 4667 snd_iprintf(buffer, "HW Serial: 0x%06x%06x\n", 4668 (hdspm_read(hdspm, HDSPM_midiStatusIn1)>>8) & 0xFFFFFF, 4669 (hdspm_read(hdspm, HDSPM_midiStatusIn0)>>8) & 0xFFFFFF); 4670 4671 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n", 4672 hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase); 4673 4674 snd_iprintf(buffer, "--- System ---\n"); 4675 4676 snd_iprintf(buffer, 4677 "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n", 4678 status & HDSPM_audioIRQPending, 4679 (status & HDSPM_midi0IRQPending) ? 1 : 0, 4680 (status & HDSPM_midi1IRQPending) ? 1 : 0, 4681 hdspm->irq_count); 4682 snd_iprintf(buffer, 4683 "HW pointer: id = %d, rawptr = %d (%d->%d) " 4684 "estimated= %ld (bytes)\n", 4685 ((status & HDSPM_BufferID) ? 1 : 0), 4686 (status & HDSPM_BufferPositionMask), 4687 (status & HDSPM_BufferPositionMask) % 4688 (2 * (int)hdspm->period_bytes), 4689 ((status & HDSPM_BufferPositionMask) - 64) % 4690 (2 * (int)hdspm->period_bytes), 4691 (long) hdspm_hw_pointer(hdspm) * 4); 4692 4693 snd_iprintf(buffer, 4694 "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n", 4695 hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF, 4696 hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF, 4697 hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF, 4698 hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF); 4699 snd_iprintf(buffer, 4700 "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n", 4701 hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF, 4702 hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF); 4703 snd_iprintf(buffer, 4704 "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, " 4705 "status2=0x%x\n", 4706 hdspm->control_register, hdspm->control2_register, 4707 status, status2); 4708 if (status & HDSPM_tco_detect) { 4709 snd_iprintf(buffer, "TCO module detected.\n"); 4710 a = hdspm_read(hdspm, HDSPM_RD_TCO+4); 4711 if (a & HDSPM_TCO1_LTC_Input_valid) { 4712 snd_iprintf(buffer, " LTC valid, "); 4713 switch (a & (HDSPM_TCO1_LTC_Format_LSB | 4714 HDSPM_TCO1_LTC_Format_MSB)) { 4715 case 0: 4716 snd_iprintf(buffer, "24 fps, "); 4717 break; 4718 case HDSPM_TCO1_LTC_Format_LSB: 4719 snd_iprintf(buffer, "25 fps, "); 4720 break; 4721 case HDSPM_TCO1_LTC_Format_MSB: 4722 snd_iprintf(buffer, "29.97 fps, "); 4723 break; 4724 default: 4725 snd_iprintf(buffer, "30 fps, "); 4726 break; 4727 } 4728 if (a & HDSPM_TCO1_set_drop_frame_flag) { 4729 snd_iprintf(buffer, "drop frame\n"); 4730 } else { 4731 snd_iprintf(buffer, "full frame\n"); 4732 } 4733 } else { 4734 snd_iprintf(buffer, " no LTC\n"); 4735 } 4736 if (a & HDSPM_TCO1_Video_Input_Format_NTSC) { 4737 snd_iprintf(buffer, " Video: NTSC\n"); 4738 } else if (a & HDSPM_TCO1_Video_Input_Format_PAL) { 4739 snd_iprintf(buffer, " Video: PAL\n"); 4740 } else { 4741 snd_iprintf(buffer, " No video\n"); 4742 } 4743 if (a & HDSPM_TCO1_TCO_lock) { 4744 snd_iprintf(buffer, " Sync: lock\n"); 4745 } else { 4746 snd_iprintf(buffer, " Sync: no lock\n"); 4747 } 4748 4749 switch (hdspm->io_type) { 4750 case MADI: 4751 case AES32: 4752 freq_const = 110069313433624ULL; 4753 break; 4754 case RayDAT: 4755 case AIO: 4756 freq_const = 104857600000000ULL; 4757 break; 4758 case MADIface: 4759 break; /* no TCO possible */ 4760 } 4761 4762 period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ); 4763 snd_iprintf(buffer, " period: %u\n", period); 4764 4765 4766 /* rate = freq_const/period; */ 4767 rate = div_u64(freq_const, period); 4768 4769 if (control & HDSPM_QuadSpeed) { 4770 rate *= 4; 4771 } else if (control & HDSPM_DoubleSpeed) { 4772 rate *= 2; 4773 } 4774 4775 snd_iprintf(buffer, " Frequency: %u Hz\n", 4776 (unsigned int) rate); 4777 4778 ltc = hdspm_read(hdspm, HDSPM_RD_TCO); 4779 frames = ltc & 0xF; 4780 ltc >>= 4; 4781 frames += (ltc & 0x3) * 10; 4782 ltc >>= 4; 4783 seconds = ltc & 0xF; 4784 ltc >>= 4; 4785 seconds += (ltc & 0x7) * 10; 4786 ltc >>= 4; 4787 minutes = ltc & 0xF; 4788 ltc >>= 4; 4789 minutes += (ltc & 0x7) * 10; 4790 ltc >>= 4; 4791 hours = ltc & 0xF; 4792 ltc >>= 4; 4793 hours += (ltc & 0x3) * 10; 4794 snd_iprintf(buffer, 4795 " LTC In: %02d:%02d:%02d:%02d\n", 4796 hours, minutes, seconds, frames); 4797 4798 } else { 4799 snd_iprintf(buffer, "No TCO module detected.\n"); 4800 } 4801 4802 snd_iprintf(buffer, "--- Settings ---\n"); 4803 4804 x = 1 << (6 + hdspm_decode_latency(hdspm->control_register & 4805 HDSPM_LatencyMask)); 4806 4807 snd_iprintf(buffer, 4808 "Size (Latency): %d samples (2 periods of %lu bytes)\n", 4809 x, (unsigned long) hdspm->period_bytes); 4810 4811 snd_iprintf(buffer, "Line out: %s\n", 4812 (hdspm->control_register & HDSPM_LineOut) ? "on " : "off"); 4813 4814 switch (hdspm->control_register & HDSPM_InputMask) { 4815 case HDSPM_InputOptical: 4816 insel = "Optical"; 4817 break; 4818 case HDSPM_InputCoaxial: 4819 insel = "Coaxial"; 4820 break; 4821 default: 4822 insel = "Unkown"; 4823 } 4824 4825 snd_iprintf(buffer, 4826 "ClearTrackMarker = %s, Transmit in %s Channel Mode, " 4827 "Auto Input %s\n", 4828 (hdspm->control_register & HDSPM_clr_tms) ? "on" : "off", 4829 (hdspm->control_register & HDSPM_TX_64ch) ? "64" : "56", 4830 (hdspm->control_register & HDSPM_AutoInp) ? "on" : "off"); 4831 4832 4833 if (!(hdspm->control_register & HDSPM_ClockModeMaster)) 4834 system_clock_mode = "AutoSync"; 4835 else 4836 system_clock_mode = "Master"; 4837 snd_iprintf(buffer, "AutoSync Reference: %s\n", system_clock_mode); 4838 4839 switch (hdspm_pref_sync_ref(hdspm)) { 4840 case HDSPM_SYNC_FROM_WORD: 4841 pref_sync_ref = "Word Clock"; 4842 break; 4843 case HDSPM_SYNC_FROM_MADI: 4844 pref_sync_ref = "MADI Sync"; 4845 break; 4846 case HDSPM_SYNC_FROM_TCO: 4847 pref_sync_ref = "TCO"; 4848 break; 4849 case HDSPM_SYNC_FROM_SYNC_IN: 4850 pref_sync_ref = "Sync In"; 4851 break; 4852 default: 4853 pref_sync_ref = "XXXX Clock"; 4854 break; 4855 } 4856 snd_iprintf(buffer, "Preferred Sync Reference: %s\n", 4857 pref_sync_ref); 4858 4859 snd_iprintf(buffer, "System Clock Frequency: %d\n", 4860 hdspm->system_sample_rate); 4861 4862 4863 snd_iprintf(buffer, "--- Status:\n"); 4864 4865 x = status & HDSPM_madiSync; 4866 x2 = status2 & HDSPM_wcSync; 4867 4868 snd_iprintf(buffer, "Inputs MADI=%s, WordClock=%s\n", 4869 (status & HDSPM_madiLock) ? (x ? "Sync" : "Lock") : 4870 "NoLock", 4871 (status2 & HDSPM_wcLock) ? (x2 ? "Sync" : "Lock") : 4872 "NoLock"); 4873 4874 switch (hdspm_autosync_ref(hdspm)) { 4875 case HDSPM_AUTOSYNC_FROM_SYNC_IN: 4876 autosync_ref = "Sync In"; 4877 break; 4878 case HDSPM_AUTOSYNC_FROM_TCO: 4879 autosync_ref = "TCO"; 4880 break; 4881 case HDSPM_AUTOSYNC_FROM_WORD: 4882 autosync_ref = "Word Clock"; 4883 break; 4884 case HDSPM_AUTOSYNC_FROM_MADI: 4885 autosync_ref = "MADI Sync"; 4886 break; 4887 case HDSPM_AUTOSYNC_FROM_NONE: 4888 autosync_ref = "Input not valid"; 4889 break; 4890 default: 4891 autosync_ref = "---"; 4892 break; 4893 } 4894 snd_iprintf(buffer, 4895 "AutoSync: Reference= %s, Freq=%d (MADI = %d, Word = %d)\n", 4896 autosync_ref, hdspm_external_sample_rate(hdspm), 4897 (status & HDSPM_madiFreqMask) >> 22, 4898 (status2 & HDSPM_wcFreqMask) >> 5); 4899 4900 snd_iprintf(buffer, "Input: %s, Mode=%s\n", 4901 (status & HDSPM_AB_int) ? "Coax" : "Optical", 4902 (status & HDSPM_RX_64ch) ? "64 channels" : 4903 "56 channels"); 4904 4905 snd_iprintf(buffer, "\n"); 4906 } 4907 4908 static void 4909 snd_hdspm_proc_read_aes32(struct snd_info_entry * entry, 4910 struct snd_info_buffer *buffer) 4911 { 4912 struct hdspm *hdspm = entry->private_data; 4913 unsigned int status; 4914 unsigned int status2; 4915 unsigned int timecode; 4916 int pref_syncref; 4917 char *autosync_ref; 4918 int x; 4919 4920 status = hdspm_read(hdspm, HDSPM_statusRegister); 4921 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 4922 timecode = hdspm_read(hdspm, HDSPM_timecodeRegister); 4923 4924 snd_iprintf(buffer, "%s (Card #%d) Rev.%x\n", 4925 hdspm->card_name, hdspm->card->number + 1, 4926 hdspm->firmware_rev); 4927 4928 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n", 4929 hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase); 4930 4931 snd_iprintf(buffer, "--- System ---\n"); 4932 4933 snd_iprintf(buffer, 4934 "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n", 4935 status & HDSPM_audioIRQPending, 4936 (status & HDSPM_midi0IRQPending) ? 1 : 0, 4937 (status & HDSPM_midi1IRQPending) ? 1 : 0, 4938 hdspm->irq_count); 4939 snd_iprintf(buffer, 4940 "HW pointer: id = %d, rawptr = %d (%d->%d) " 4941 "estimated= %ld (bytes)\n", 4942 ((status & HDSPM_BufferID) ? 1 : 0), 4943 (status & HDSPM_BufferPositionMask), 4944 (status & HDSPM_BufferPositionMask) % 4945 (2 * (int)hdspm->period_bytes), 4946 ((status & HDSPM_BufferPositionMask) - 64) % 4947 (2 * (int)hdspm->period_bytes), 4948 (long) hdspm_hw_pointer(hdspm) * 4); 4949 4950 snd_iprintf(buffer, 4951 "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n", 4952 hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF, 4953 hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF, 4954 hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF, 4955 hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF); 4956 snd_iprintf(buffer, 4957 "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n", 4958 hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF, 4959 hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF); 4960 snd_iprintf(buffer, 4961 "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, " 4962 "status2=0x%x\n", 4963 hdspm->control_register, hdspm->control2_register, 4964 status, status2); 4965 4966 snd_iprintf(buffer, "--- Settings ---\n"); 4967 4968 x = 1 << (6 + hdspm_decode_latency(hdspm->control_register & 4969 HDSPM_LatencyMask)); 4970 4971 snd_iprintf(buffer, 4972 "Size (Latency): %d samples (2 periods of %lu bytes)\n", 4973 x, (unsigned long) hdspm->period_bytes); 4974 4975 snd_iprintf(buffer, "Line out: %s\n", 4976 (hdspm-> 4977 control_register & HDSPM_LineOut) ? "on " : "off"); 4978 4979 snd_iprintf(buffer, 4980 "ClearTrackMarker %s, Emphasis %s, Dolby %s\n", 4981 (hdspm-> 4982 control_register & HDSPM_clr_tms) ? "on" : "off", 4983 (hdspm-> 4984 control_register & HDSPM_Emphasis) ? "on" : "off", 4985 (hdspm-> 4986 control_register & HDSPM_Dolby) ? "on" : "off"); 4987 4988 4989 pref_syncref = hdspm_pref_sync_ref(hdspm); 4990 if (pref_syncref == 0) 4991 snd_iprintf(buffer, "Preferred Sync Reference: Word Clock\n"); 4992 else 4993 snd_iprintf(buffer, "Preferred Sync Reference: AES%d\n", 4994 pref_syncref); 4995 4996 snd_iprintf(buffer, "System Clock Frequency: %d\n", 4997 hdspm->system_sample_rate); 4998 4999 snd_iprintf(buffer, "Double speed: %s\n", 5000 hdspm->control_register & HDSPM_DS_DoubleWire? 5001 "Double wire" : "Single wire"); 5002 snd_iprintf(buffer, "Quad speed: %s\n", 5003 hdspm->control_register & HDSPM_QS_DoubleWire? 5004 "Double wire" : 5005 hdspm->control_register & HDSPM_QS_QuadWire? 5006 "Quad wire" : "Single wire"); 5007 5008 snd_iprintf(buffer, "--- Status:\n"); 5009 5010 snd_iprintf(buffer, "Word: %s Frequency: %d\n", 5011 (status & HDSPM_AES32_wcLock) ? "Sync " : "No Lock", 5012 HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF)); 5013 5014 for (x = 0; x < 8; x++) { 5015 snd_iprintf(buffer, "AES%d: %s Frequency: %d\n", 5016 x+1, 5017 (status2 & (HDSPM_LockAES >> x)) ? 5018 "Sync " : "No Lock", 5019 HDSPM_bit2freq((timecode >> (4*x)) & 0xF)); 5020 } 5021 5022 switch (hdspm_autosync_ref(hdspm)) { 5023 case HDSPM_AES32_AUTOSYNC_FROM_NONE: 5024 autosync_ref = "None"; break; 5025 case HDSPM_AES32_AUTOSYNC_FROM_WORD: 5026 autosync_ref = "Word Clock"; break; 5027 case HDSPM_AES32_AUTOSYNC_FROM_AES1: 5028 autosync_ref = "AES1"; break; 5029 case HDSPM_AES32_AUTOSYNC_FROM_AES2: 5030 autosync_ref = "AES2"; break; 5031 case HDSPM_AES32_AUTOSYNC_FROM_AES3: 5032 autosync_ref = "AES3"; break; 5033 case HDSPM_AES32_AUTOSYNC_FROM_AES4: 5034 autosync_ref = "AES4"; break; 5035 case HDSPM_AES32_AUTOSYNC_FROM_AES5: 5036 autosync_ref = "AES5"; break; 5037 case HDSPM_AES32_AUTOSYNC_FROM_AES6: 5038 autosync_ref = "AES6"; break; 5039 case HDSPM_AES32_AUTOSYNC_FROM_AES7: 5040 autosync_ref = "AES7"; break; 5041 case HDSPM_AES32_AUTOSYNC_FROM_AES8: 5042 autosync_ref = "AES8"; break; 5043 default: 5044 autosync_ref = "---"; break; 5045 } 5046 snd_iprintf(buffer, "AutoSync ref = %s\n", autosync_ref); 5047 5048 snd_iprintf(buffer, "\n"); 5049 } 5050 5051 static void 5052 snd_hdspm_proc_read_raydat(struct snd_info_entry *entry, 5053 struct snd_info_buffer *buffer) 5054 { 5055 struct hdspm *hdspm = entry->private_data; 5056 unsigned int status1, status2, status3, control, i; 5057 unsigned int lock, sync; 5058 5059 status1 = hdspm_read(hdspm, HDSPM_RD_STATUS_1); /* s1 */ 5060 status2 = hdspm_read(hdspm, HDSPM_RD_STATUS_2); /* freq */ 5061 status3 = hdspm_read(hdspm, HDSPM_RD_STATUS_3); /* s2 */ 5062 5063 control = hdspm->control_register; 5064 5065 snd_iprintf(buffer, "STATUS1: 0x%08x\n", status1); 5066 snd_iprintf(buffer, "STATUS2: 0x%08x\n", status2); 5067 snd_iprintf(buffer, "STATUS3: 0x%08x\n", status3); 5068 5069 5070 snd_iprintf(buffer, "\n*** CLOCK MODE\n\n"); 5071 5072 snd_iprintf(buffer, "Clock mode : %s\n", 5073 (hdspm_system_clock_mode(hdspm) == 0) ? "master" : "slave"); 5074 snd_iprintf(buffer, "System frequency: %d Hz\n", 5075 hdspm_get_system_sample_rate(hdspm)); 5076 5077 snd_iprintf(buffer, "\n*** INPUT STATUS\n\n"); 5078 5079 lock = 0x1; 5080 sync = 0x100; 5081 5082 for (i = 0; i < 8; i++) { 5083 snd_iprintf(buffer, "s1_input %d: Lock %d, Sync %d, Freq %s\n", 5084 i, 5085 (status1 & lock) ? 1 : 0, 5086 (status1 & sync) ? 1 : 0, 5087 texts_freq[(status2 >> (i * 4)) & 0xF]); 5088 5089 lock = lock<<1; 5090 sync = sync<<1; 5091 } 5092 5093 snd_iprintf(buffer, "WC input: Lock %d, Sync %d, Freq %s\n", 5094 (status1 & 0x1000000) ? 1 : 0, 5095 (status1 & 0x2000000) ? 1 : 0, 5096 texts_freq[(status1 >> 16) & 0xF]); 5097 5098 snd_iprintf(buffer, "TCO input: Lock %d, Sync %d, Freq %s\n", 5099 (status1 & 0x4000000) ? 1 : 0, 5100 (status1 & 0x8000000) ? 1 : 0, 5101 texts_freq[(status1 >> 20) & 0xF]); 5102 5103 snd_iprintf(buffer, "SYNC IN: Lock %d, Sync %d, Freq %s\n", 5104 (status3 & 0x400) ? 1 : 0, 5105 (status3 & 0x800) ? 1 : 0, 5106 texts_freq[(status2 >> 12) & 0xF]); 5107 5108 } 5109 5110 #ifdef CONFIG_SND_DEBUG 5111 static void 5112 snd_hdspm_proc_read_debug(struct snd_info_entry *entry, 5113 struct snd_info_buffer *buffer) 5114 { 5115 struct hdspm *hdspm = entry->private_data; 5116 5117 int j,i; 5118 5119 for (i = 0; i < 256 /* 1024*64 */; i += j) { 5120 snd_iprintf(buffer, "0x%08X: ", i); 5121 for (j = 0; j < 16; j += 4) 5122 snd_iprintf(buffer, "%08X ", hdspm_read(hdspm, i + j)); 5123 snd_iprintf(buffer, "\n"); 5124 } 5125 } 5126 #endif 5127 5128 5129 static void snd_hdspm_proc_ports_in(struct snd_info_entry *entry, 5130 struct snd_info_buffer *buffer) 5131 { 5132 struct hdspm *hdspm = entry->private_data; 5133 int i; 5134 5135 snd_iprintf(buffer, "# generated by hdspm\n"); 5136 5137 for (i = 0; i < hdspm->max_channels_in; i++) { 5138 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_in[i]); 5139 } 5140 } 5141 5142 static void snd_hdspm_proc_ports_out(struct snd_info_entry *entry, 5143 struct snd_info_buffer *buffer) 5144 { 5145 struct hdspm *hdspm = entry->private_data; 5146 int i; 5147 5148 snd_iprintf(buffer, "# generated by hdspm\n"); 5149 5150 for (i = 0; i < hdspm->max_channels_out; i++) { 5151 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_out[i]); 5152 } 5153 } 5154 5155 5156 static void __devinit snd_hdspm_proc_init(struct hdspm *hdspm) 5157 { 5158 struct snd_info_entry *entry; 5159 5160 if (!snd_card_proc_new(hdspm->card, "hdspm", &entry)) { 5161 switch (hdspm->io_type) { 5162 case AES32: 5163 snd_info_set_text_ops(entry, hdspm, 5164 snd_hdspm_proc_read_aes32); 5165 break; 5166 case MADI: 5167 snd_info_set_text_ops(entry, hdspm, 5168 snd_hdspm_proc_read_madi); 5169 break; 5170 case MADIface: 5171 /* snd_info_set_text_ops(entry, hdspm, 5172 snd_hdspm_proc_read_madiface); */ 5173 break; 5174 case RayDAT: 5175 snd_info_set_text_ops(entry, hdspm, 5176 snd_hdspm_proc_read_raydat); 5177 break; 5178 case AIO: 5179 break; 5180 } 5181 } 5182 5183 if (!snd_card_proc_new(hdspm->card, "ports.in", &entry)) { 5184 snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_in); 5185 } 5186 5187 if (!snd_card_proc_new(hdspm->card, "ports.out", &entry)) { 5188 snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_out); 5189 } 5190 5191 #ifdef CONFIG_SND_DEBUG 5192 /* debug file to read all hdspm registers */ 5193 if (!snd_card_proc_new(hdspm->card, "debug", &entry)) 5194 snd_info_set_text_ops(entry, hdspm, 5195 snd_hdspm_proc_read_debug); 5196 #endif 5197 } 5198 5199 /*------------------------------------------------------------ 5200 hdspm intitialize 5201 ------------------------------------------------------------*/ 5202 5203 static int snd_hdspm_set_defaults(struct hdspm * hdspm) 5204 { 5205 /* ASSUMPTION: hdspm->lock is either held, or there is no need to 5206 hold it (e.g. during module initialization). 5207 */ 5208 5209 /* set defaults: */ 5210 5211 hdspm->settings_register = 0; 5212 5213 switch (hdspm->io_type) { 5214 case MADI: 5215 case MADIface: 5216 hdspm->control_register = 5217 0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000; 5218 break; 5219 5220 case RayDAT: 5221 case AIO: 5222 hdspm->settings_register = 0x1 + 0x1000; 5223 /* Magic values are: LAT_0, LAT_2, Master, freq1, tx64ch, inp_0, 5224 * line_out */ 5225 hdspm->control_register = 5226 0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000; 5227 break; 5228 5229 case AES32: 5230 hdspm->control_register = 5231 HDSPM_ClockModeMaster | /* Master Cloack Mode on */ 5232 hdspm_encode_latency(7) | /* latency max=8192samples */ 5233 HDSPM_SyncRef0 | /* AES1 is syncclock */ 5234 HDSPM_LineOut | /* Analog output in */ 5235 HDSPM_Professional; /* Professional mode */ 5236 break; 5237 } 5238 5239 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 5240 5241 if (AES32 == hdspm->io_type) { 5242 /* No control2 register for AES32 */ 5243 #ifdef SNDRV_BIG_ENDIAN 5244 hdspm->control2_register = HDSPM_BIGENDIAN_MODE; 5245 #else 5246 hdspm->control2_register = 0; 5247 #endif 5248 5249 hdspm_write(hdspm, HDSPM_control2Reg, hdspm->control2_register); 5250 } 5251 hdspm_compute_period_size(hdspm); 5252 5253 /* silence everything */ 5254 5255 all_in_all_mixer(hdspm, 0 * UNITY_GAIN); 5256 5257 if (hdspm->io_type == AIO || hdspm->io_type == RayDAT) { 5258 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register); 5259 } 5260 5261 /* set a default rate so that the channel map is set up. */ 5262 hdspm_set_rate(hdspm, 48000, 1); 5263 5264 return 0; 5265 } 5266 5267 5268 /*------------------------------------------------------------ 5269 interrupt 5270 ------------------------------------------------------------*/ 5271 5272 static irqreturn_t snd_hdspm_interrupt(int irq, void *dev_id) 5273 { 5274 struct hdspm *hdspm = (struct hdspm *) dev_id; 5275 unsigned int status; 5276 int i, audio, midi, schedule = 0; 5277 /* cycles_t now; */ 5278 5279 status = hdspm_read(hdspm, HDSPM_statusRegister); 5280 5281 audio = status & HDSPM_audioIRQPending; 5282 midi = status & (HDSPM_midi0IRQPending | HDSPM_midi1IRQPending | 5283 HDSPM_midi2IRQPending | HDSPM_midi3IRQPending); 5284 5285 /* now = get_cycles(); */ 5286 /** 5287 * LAT_2..LAT_0 period counter (win) counter (mac) 5288 * 6 4096 ~256053425 ~514672358 5289 * 5 2048 ~128024983 ~257373821 5290 * 4 1024 ~64023706 ~128718089 5291 * 3 512 ~32005945 ~64385999 5292 * 2 256 ~16003039 ~32260176 5293 * 1 128 ~7998738 ~16194507 5294 * 0 64 ~3998231 ~8191558 5295 **/ 5296 /* 5297 snd_printk(KERN_INFO "snd_hdspm_interrupt %llu @ %llx\n", 5298 now-hdspm->last_interrupt, status & 0xFFC0); 5299 hdspm->last_interrupt = now; 5300 */ 5301 5302 if (!audio && !midi) 5303 return IRQ_NONE; 5304 5305 hdspm_write(hdspm, HDSPM_interruptConfirmation, 0); 5306 hdspm->irq_count++; 5307 5308 5309 if (audio) { 5310 if (hdspm->capture_substream) 5311 snd_pcm_period_elapsed(hdspm->capture_substream); 5312 5313 if (hdspm->playback_substream) 5314 snd_pcm_period_elapsed(hdspm->playback_substream); 5315 } 5316 5317 if (midi) { 5318 i = 0; 5319 while (i < hdspm->midiPorts) { 5320 if ((hdspm_read(hdspm, 5321 hdspm->midi[i].statusIn) & 0xff) && 5322 (status & hdspm->midi[i].irq)) { 5323 /* we disable interrupts for this input until 5324 * processing is done 5325 */ 5326 hdspm->control_register &= ~hdspm->midi[i].ie; 5327 hdspm_write(hdspm, HDSPM_controlRegister, 5328 hdspm->control_register); 5329 hdspm->midi[i].pending = 1; 5330 schedule = 1; 5331 } 5332 5333 i++; 5334 } 5335 5336 if (schedule) 5337 tasklet_hi_schedule(&hdspm->midi_tasklet); 5338 } 5339 5340 return IRQ_HANDLED; 5341 } 5342 5343 /*------------------------------------------------------------ 5344 pcm interface 5345 ------------------------------------------------------------*/ 5346 5347 5348 static snd_pcm_uframes_t snd_hdspm_hw_pointer(struct snd_pcm_substream 5349 *substream) 5350 { 5351 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5352 return hdspm_hw_pointer(hdspm); 5353 } 5354 5355 5356 static int snd_hdspm_reset(struct snd_pcm_substream *substream) 5357 { 5358 struct snd_pcm_runtime *runtime = substream->runtime; 5359 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5360 struct snd_pcm_substream *other; 5361 5362 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 5363 other = hdspm->capture_substream; 5364 else 5365 other = hdspm->playback_substream; 5366 5367 if (hdspm->running) 5368 runtime->status->hw_ptr = hdspm_hw_pointer(hdspm); 5369 else 5370 runtime->status->hw_ptr = 0; 5371 if (other) { 5372 struct snd_pcm_substream *s; 5373 struct snd_pcm_runtime *oruntime = other->runtime; 5374 snd_pcm_group_for_each_entry(s, substream) { 5375 if (s == other) { 5376 oruntime->status->hw_ptr = 5377 runtime->status->hw_ptr; 5378 break; 5379 } 5380 } 5381 } 5382 return 0; 5383 } 5384 5385 static int snd_hdspm_hw_params(struct snd_pcm_substream *substream, 5386 struct snd_pcm_hw_params *params) 5387 { 5388 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5389 int err; 5390 int i; 5391 pid_t this_pid; 5392 pid_t other_pid; 5393 5394 spin_lock_irq(&hdspm->lock); 5395 5396 if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) { 5397 this_pid = hdspm->playback_pid; 5398 other_pid = hdspm->capture_pid; 5399 } else { 5400 this_pid = hdspm->capture_pid; 5401 other_pid = hdspm->playback_pid; 5402 } 5403 5404 if (other_pid > 0 && this_pid != other_pid) { 5405 5406 /* The other stream is open, and not by the same 5407 task as this one. Make sure that the parameters 5408 that matter are the same. 5409 */ 5410 5411 if (params_rate(params) != hdspm->system_sample_rate) { 5412 spin_unlock_irq(&hdspm->lock); 5413 _snd_pcm_hw_param_setempty(params, 5414 SNDRV_PCM_HW_PARAM_RATE); 5415 return -EBUSY; 5416 } 5417 5418 if (params_period_size(params) != hdspm->period_bytes / 4) { 5419 spin_unlock_irq(&hdspm->lock); 5420 _snd_pcm_hw_param_setempty(params, 5421 SNDRV_PCM_HW_PARAM_PERIOD_SIZE); 5422 return -EBUSY; 5423 } 5424 5425 } 5426 /* We're fine. */ 5427 spin_unlock_irq(&hdspm->lock); 5428 5429 /* how to make sure that the rate matches an externally-set one ? */ 5430 5431 spin_lock_irq(&hdspm->lock); 5432 err = hdspm_set_rate(hdspm, params_rate(params), 0); 5433 if (err < 0) { 5434 snd_printk(KERN_INFO "err on hdspm_set_rate: %d\n", err); 5435 spin_unlock_irq(&hdspm->lock); 5436 _snd_pcm_hw_param_setempty(params, 5437 SNDRV_PCM_HW_PARAM_RATE); 5438 return err; 5439 } 5440 spin_unlock_irq(&hdspm->lock); 5441 5442 err = hdspm_set_interrupt_interval(hdspm, 5443 params_period_size(params)); 5444 if (err < 0) { 5445 snd_printk(KERN_INFO "err on hdspm_set_interrupt_interval: %d\n", err); 5446 _snd_pcm_hw_param_setempty(params, 5447 SNDRV_PCM_HW_PARAM_PERIOD_SIZE); 5448 return err; 5449 } 5450 5451 /* Memory allocation, takashi's method, dont know if we should 5452 * spinlock 5453 */ 5454 /* malloc all buffer even if not enabled to get sure */ 5455 /* Update for MADI rev 204: we need to allocate for all channels, 5456 * otherwise it doesn't work at 96kHz */ 5457 5458 err = 5459 snd_pcm_lib_malloc_pages(substream, HDSPM_DMA_AREA_BYTES); 5460 if (err < 0) { 5461 snd_printk(KERN_INFO "err on snd_pcm_lib_malloc_pages: %d\n", err); 5462 return err; 5463 } 5464 5465 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 5466 5467 hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferOut, 5468 params_channels(params)); 5469 5470 for (i = 0; i < params_channels(params); ++i) 5471 snd_hdspm_enable_out(hdspm, i, 1); 5472 5473 hdspm->playback_buffer = 5474 (unsigned char *) substream->runtime->dma_area; 5475 snd_printdd("Allocated sample buffer for playback at %p\n", 5476 hdspm->playback_buffer); 5477 } else { 5478 hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferIn, 5479 params_channels(params)); 5480 5481 for (i = 0; i < params_channels(params); ++i) 5482 snd_hdspm_enable_in(hdspm, i, 1); 5483 5484 hdspm->capture_buffer = 5485 (unsigned char *) substream->runtime->dma_area; 5486 snd_printdd("Allocated sample buffer for capture at %p\n", 5487 hdspm->capture_buffer); 5488 } 5489 5490 /* 5491 snd_printdd("Allocated sample buffer for %s at 0x%08X\n", 5492 substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 5493 "playback" : "capture", 5494 snd_pcm_sgbuf_get_addr(substream, 0)); 5495 */ 5496 /* 5497 snd_printdd("set_hwparams: %s %d Hz, %d channels, bs = %d\n", 5498 substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 5499 "playback" : "capture", 5500 params_rate(params), params_channels(params), 5501 params_buffer_size(params)); 5502 */ 5503 5504 5505 /* Switch to native float format if requested */ 5506 if (SNDRV_PCM_FORMAT_FLOAT_LE == params_format(params)) { 5507 if (!(hdspm->control_register & HDSPe_FLOAT_FORMAT)) 5508 snd_printk(KERN_INFO "hdspm: Switching to native 32bit LE float format.\n"); 5509 5510 hdspm->control_register |= HDSPe_FLOAT_FORMAT; 5511 } else if (SNDRV_PCM_FORMAT_S32_LE == params_format(params)) { 5512 if (hdspm->control_register & HDSPe_FLOAT_FORMAT) 5513 snd_printk(KERN_INFO "hdspm: Switching to native 32bit LE integer format.\n"); 5514 5515 hdspm->control_register &= ~HDSPe_FLOAT_FORMAT; 5516 } 5517 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 5518 5519 return 0; 5520 } 5521 5522 static int snd_hdspm_hw_free(struct snd_pcm_substream *substream) 5523 { 5524 int i; 5525 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5526 5527 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 5528 5529 /* params_channels(params) should be enough, 5530 but to get sure in case of error */ 5531 for (i = 0; i < hdspm->max_channels_out; ++i) 5532 snd_hdspm_enable_out(hdspm, i, 0); 5533 5534 hdspm->playback_buffer = NULL; 5535 } else { 5536 for (i = 0; i < hdspm->max_channels_in; ++i) 5537 snd_hdspm_enable_in(hdspm, i, 0); 5538 5539 hdspm->capture_buffer = NULL; 5540 5541 } 5542 5543 snd_pcm_lib_free_pages(substream); 5544 5545 return 0; 5546 } 5547 5548 5549 static int snd_hdspm_channel_info(struct snd_pcm_substream *substream, 5550 struct snd_pcm_channel_info *info) 5551 { 5552 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5553 5554 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 5555 if (snd_BUG_ON(info->channel >= hdspm->max_channels_out)) { 5556 snd_printk(KERN_INFO "snd_hdspm_channel_info: output channel out of range (%d)\n", info->channel); 5557 return -EINVAL; 5558 } 5559 5560 if (hdspm->channel_map_out[info->channel] < 0) { 5561 snd_printk(KERN_INFO "snd_hdspm_channel_info: output channel %d mapped out\n", info->channel); 5562 return -EINVAL; 5563 } 5564 5565 info->offset = hdspm->channel_map_out[info->channel] * 5566 HDSPM_CHANNEL_BUFFER_BYTES; 5567 } else { 5568 if (snd_BUG_ON(info->channel >= hdspm->max_channels_in)) { 5569 snd_printk(KERN_INFO "snd_hdspm_channel_info: input channel out of range (%d)\n", info->channel); 5570 return -EINVAL; 5571 } 5572 5573 if (hdspm->channel_map_in[info->channel] < 0) { 5574 snd_printk(KERN_INFO "snd_hdspm_channel_info: input channel %d mapped out\n", info->channel); 5575 return -EINVAL; 5576 } 5577 5578 info->offset = hdspm->channel_map_in[info->channel] * 5579 HDSPM_CHANNEL_BUFFER_BYTES; 5580 } 5581 5582 info->first = 0; 5583 info->step = 32; 5584 return 0; 5585 } 5586 5587 5588 static int snd_hdspm_ioctl(struct snd_pcm_substream *substream, 5589 unsigned int cmd, void *arg) 5590 { 5591 switch (cmd) { 5592 case SNDRV_PCM_IOCTL1_RESET: 5593 return snd_hdspm_reset(substream); 5594 5595 case SNDRV_PCM_IOCTL1_CHANNEL_INFO: 5596 { 5597 struct snd_pcm_channel_info *info = arg; 5598 return snd_hdspm_channel_info(substream, info); 5599 } 5600 default: 5601 break; 5602 } 5603 5604 return snd_pcm_lib_ioctl(substream, cmd, arg); 5605 } 5606 5607 static int snd_hdspm_trigger(struct snd_pcm_substream *substream, int cmd) 5608 { 5609 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5610 struct snd_pcm_substream *other; 5611 int running; 5612 5613 spin_lock(&hdspm->lock); 5614 running = hdspm->running; 5615 switch (cmd) { 5616 case SNDRV_PCM_TRIGGER_START: 5617 running |= 1 << substream->stream; 5618 break; 5619 case SNDRV_PCM_TRIGGER_STOP: 5620 running &= ~(1 << substream->stream); 5621 break; 5622 default: 5623 snd_BUG(); 5624 spin_unlock(&hdspm->lock); 5625 return -EINVAL; 5626 } 5627 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 5628 other = hdspm->capture_substream; 5629 else 5630 other = hdspm->playback_substream; 5631 5632 if (other) { 5633 struct snd_pcm_substream *s; 5634 snd_pcm_group_for_each_entry(s, substream) { 5635 if (s == other) { 5636 snd_pcm_trigger_done(s, substream); 5637 if (cmd == SNDRV_PCM_TRIGGER_START) 5638 running |= 1 << s->stream; 5639 else 5640 running &= ~(1 << s->stream); 5641 goto _ok; 5642 } 5643 } 5644 if (cmd == SNDRV_PCM_TRIGGER_START) { 5645 if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK)) 5646 && substream->stream == 5647 SNDRV_PCM_STREAM_CAPTURE) 5648 hdspm_silence_playback(hdspm); 5649 } else { 5650 if (running && 5651 substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 5652 hdspm_silence_playback(hdspm); 5653 } 5654 } else { 5655 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 5656 hdspm_silence_playback(hdspm); 5657 } 5658 _ok: 5659 snd_pcm_trigger_done(substream, substream); 5660 if (!hdspm->running && running) 5661 hdspm_start_audio(hdspm); 5662 else if (hdspm->running && !running) 5663 hdspm_stop_audio(hdspm); 5664 hdspm->running = running; 5665 spin_unlock(&hdspm->lock); 5666 5667 return 0; 5668 } 5669 5670 static int snd_hdspm_prepare(struct snd_pcm_substream *substream) 5671 { 5672 return 0; 5673 } 5674 5675 static unsigned int period_sizes_old[] = { 5676 64, 128, 256, 512, 1024, 2048, 4096 5677 }; 5678 5679 static unsigned int period_sizes_new[] = { 5680 32, 64, 128, 256, 512, 1024, 2048, 4096 5681 }; 5682 5683 /* RayDAT and AIO always have a buffer of 16384 samples per channel */ 5684 static unsigned int raydat_aio_buffer_sizes[] = { 5685 16384 5686 }; 5687 5688 static struct snd_pcm_hardware snd_hdspm_playback_subinfo = { 5689 .info = (SNDRV_PCM_INFO_MMAP | 5690 SNDRV_PCM_INFO_MMAP_VALID | 5691 SNDRV_PCM_INFO_NONINTERLEAVED | 5692 SNDRV_PCM_INFO_SYNC_START | SNDRV_PCM_INFO_DOUBLE), 5693 .formats = SNDRV_PCM_FMTBIT_S32_LE, 5694 .rates = (SNDRV_PCM_RATE_32000 | 5695 SNDRV_PCM_RATE_44100 | 5696 SNDRV_PCM_RATE_48000 | 5697 SNDRV_PCM_RATE_64000 | 5698 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | 5699 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000 ), 5700 .rate_min = 32000, 5701 .rate_max = 192000, 5702 .channels_min = 1, 5703 .channels_max = HDSPM_MAX_CHANNELS, 5704 .buffer_bytes_max = 5705 HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS, 5706 .period_bytes_min = (64 * 4), 5707 .period_bytes_max = (4096 * 4) * HDSPM_MAX_CHANNELS, 5708 .periods_min = 2, 5709 .periods_max = 512, 5710 .fifo_size = 0 5711 }; 5712 5713 static struct snd_pcm_hardware snd_hdspm_capture_subinfo = { 5714 .info = (SNDRV_PCM_INFO_MMAP | 5715 SNDRV_PCM_INFO_MMAP_VALID | 5716 SNDRV_PCM_INFO_NONINTERLEAVED | 5717 SNDRV_PCM_INFO_SYNC_START), 5718 .formats = SNDRV_PCM_FMTBIT_S32_LE, 5719 .rates = (SNDRV_PCM_RATE_32000 | 5720 SNDRV_PCM_RATE_44100 | 5721 SNDRV_PCM_RATE_48000 | 5722 SNDRV_PCM_RATE_64000 | 5723 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | 5724 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000), 5725 .rate_min = 32000, 5726 .rate_max = 192000, 5727 .channels_min = 1, 5728 .channels_max = HDSPM_MAX_CHANNELS, 5729 .buffer_bytes_max = 5730 HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS, 5731 .period_bytes_min = (64 * 4), 5732 .period_bytes_max = (4096 * 4) * HDSPM_MAX_CHANNELS, 5733 .periods_min = 2, 5734 .periods_max = 512, 5735 .fifo_size = 0 5736 }; 5737 5738 static struct snd_pcm_hw_constraint_list hw_constraints_period_sizes_old = { 5739 .count = ARRAY_SIZE(period_sizes_old), 5740 .list = period_sizes_old, 5741 .mask = 0 5742 }; 5743 5744 static struct snd_pcm_hw_constraint_list hw_constraints_period_sizes_new = { 5745 .count = ARRAY_SIZE(period_sizes_new), 5746 .list = period_sizes_new, 5747 .mask = 0 5748 }; 5749 5750 static struct snd_pcm_hw_constraint_list hw_constraints_raydat_io_buffer = { 5751 .count = ARRAY_SIZE(raydat_aio_buffer_sizes), 5752 .list = raydat_aio_buffer_sizes, 5753 .mask = 0 5754 }; 5755 5756 static int snd_hdspm_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params, 5757 struct snd_pcm_hw_rule *rule) 5758 { 5759 struct hdspm *hdspm = rule->private; 5760 struct snd_interval *c = 5761 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 5762 struct snd_interval *r = 5763 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 5764 5765 if (r->min > 96000 && r->max <= 192000) { 5766 struct snd_interval t = { 5767 .min = hdspm->qs_in_channels, 5768 .max = hdspm->qs_in_channels, 5769 .integer = 1, 5770 }; 5771 return snd_interval_refine(c, &t); 5772 } else if (r->min > 48000 && r->max <= 96000) { 5773 struct snd_interval t = { 5774 .min = hdspm->ds_in_channels, 5775 .max = hdspm->ds_in_channels, 5776 .integer = 1, 5777 }; 5778 return snd_interval_refine(c, &t); 5779 } else if (r->max < 64000) { 5780 struct snd_interval t = { 5781 .min = hdspm->ss_in_channels, 5782 .max = hdspm->ss_in_channels, 5783 .integer = 1, 5784 }; 5785 return snd_interval_refine(c, &t); 5786 } 5787 5788 return 0; 5789 } 5790 5791 static int snd_hdspm_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params, 5792 struct snd_pcm_hw_rule * rule) 5793 { 5794 struct hdspm *hdspm = rule->private; 5795 struct snd_interval *c = 5796 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 5797 struct snd_interval *r = 5798 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 5799 5800 if (r->min > 96000 && r->max <= 192000) { 5801 struct snd_interval t = { 5802 .min = hdspm->qs_out_channels, 5803 .max = hdspm->qs_out_channels, 5804 .integer = 1, 5805 }; 5806 return snd_interval_refine(c, &t); 5807 } else if (r->min > 48000 && r->max <= 96000) { 5808 struct snd_interval t = { 5809 .min = hdspm->ds_out_channels, 5810 .max = hdspm->ds_out_channels, 5811 .integer = 1, 5812 }; 5813 return snd_interval_refine(c, &t); 5814 } else if (r->max < 64000) { 5815 struct snd_interval t = { 5816 .min = hdspm->ss_out_channels, 5817 .max = hdspm->ss_out_channels, 5818 .integer = 1, 5819 }; 5820 return snd_interval_refine(c, &t); 5821 } else { 5822 } 5823 return 0; 5824 } 5825 5826 static int snd_hdspm_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params, 5827 struct snd_pcm_hw_rule * rule) 5828 { 5829 struct hdspm *hdspm = rule->private; 5830 struct snd_interval *c = 5831 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 5832 struct snd_interval *r = 5833 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 5834 5835 if (c->min >= hdspm->ss_in_channels) { 5836 struct snd_interval t = { 5837 .min = 32000, 5838 .max = 48000, 5839 .integer = 1, 5840 }; 5841 return snd_interval_refine(r, &t); 5842 } else if (c->max <= hdspm->qs_in_channels) { 5843 struct snd_interval t = { 5844 .min = 128000, 5845 .max = 192000, 5846 .integer = 1, 5847 }; 5848 return snd_interval_refine(r, &t); 5849 } else if (c->max <= hdspm->ds_in_channels) { 5850 struct snd_interval t = { 5851 .min = 64000, 5852 .max = 96000, 5853 .integer = 1, 5854 }; 5855 return snd_interval_refine(r, &t); 5856 } 5857 5858 return 0; 5859 } 5860 static int snd_hdspm_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params, 5861 struct snd_pcm_hw_rule *rule) 5862 { 5863 struct hdspm *hdspm = rule->private; 5864 struct snd_interval *c = 5865 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 5866 struct snd_interval *r = 5867 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 5868 5869 if (c->min >= hdspm->ss_out_channels) { 5870 struct snd_interval t = { 5871 .min = 32000, 5872 .max = 48000, 5873 .integer = 1, 5874 }; 5875 return snd_interval_refine(r, &t); 5876 } else if (c->max <= hdspm->qs_out_channels) { 5877 struct snd_interval t = { 5878 .min = 128000, 5879 .max = 192000, 5880 .integer = 1, 5881 }; 5882 return snd_interval_refine(r, &t); 5883 } else if (c->max <= hdspm->ds_out_channels) { 5884 struct snd_interval t = { 5885 .min = 64000, 5886 .max = 96000, 5887 .integer = 1, 5888 }; 5889 return snd_interval_refine(r, &t); 5890 } 5891 5892 return 0; 5893 } 5894 5895 static int snd_hdspm_hw_rule_in_channels(struct snd_pcm_hw_params *params, 5896 struct snd_pcm_hw_rule *rule) 5897 { 5898 unsigned int list[3]; 5899 struct hdspm *hdspm = rule->private; 5900 struct snd_interval *c = hw_param_interval(params, 5901 SNDRV_PCM_HW_PARAM_CHANNELS); 5902 5903 list[0] = hdspm->qs_in_channels; 5904 list[1] = hdspm->ds_in_channels; 5905 list[2] = hdspm->ss_in_channels; 5906 return snd_interval_list(c, 3, list, 0); 5907 } 5908 5909 static int snd_hdspm_hw_rule_out_channels(struct snd_pcm_hw_params *params, 5910 struct snd_pcm_hw_rule *rule) 5911 { 5912 unsigned int list[3]; 5913 struct hdspm *hdspm = rule->private; 5914 struct snd_interval *c = hw_param_interval(params, 5915 SNDRV_PCM_HW_PARAM_CHANNELS); 5916 5917 list[0] = hdspm->qs_out_channels; 5918 list[1] = hdspm->ds_out_channels; 5919 list[2] = hdspm->ss_out_channels; 5920 return snd_interval_list(c, 3, list, 0); 5921 } 5922 5923 5924 static unsigned int hdspm_aes32_sample_rates[] = { 5925 32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000 5926 }; 5927 5928 static struct snd_pcm_hw_constraint_list 5929 hdspm_hw_constraints_aes32_sample_rates = { 5930 .count = ARRAY_SIZE(hdspm_aes32_sample_rates), 5931 .list = hdspm_aes32_sample_rates, 5932 .mask = 0 5933 }; 5934 5935 static int snd_hdspm_playback_open(struct snd_pcm_substream *substream) 5936 { 5937 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5938 struct snd_pcm_runtime *runtime = substream->runtime; 5939 5940 spin_lock_irq(&hdspm->lock); 5941 5942 snd_pcm_set_sync(substream); 5943 5944 5945 runtime->hw = snd_hdspm_playback_subinfo; 5946 5947 if (hdspm->capture_substream == NULL) 5948 hdspm_stop_audio(hdspm); 5949 5950 hdspm->playback_pid = current->pid; 5951 hdspm->playback_substream = substream; 5952 5953 spin_unlock_irq(&hdspm->lock); 5954 5955 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24); 5956 5957 switch (hdspm->io_type) { 5958 case AIO: 5959 case RayDAT: 5960 snd_pcm_hw_constraint_list(runtime, 0, 5961 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 5962 &hw_constraints_period_sizes_new); 5963 snd_pcm_hw_constraint_list(runtime, 0, 5964 SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 5965 &hw_constraints_raydat_io_buffer); 5966 5967 break; 5968 5969 default: 5970 snd_pcm_hw_constraint_list(runtime, 0, 5971 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 5972 &hw_constraints_period_sizes_old); 5973 } 5974 5975 if (AES32 == hdspm->io_type) { 5976 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 5977 &hdspm_hw_constraints_aes32_sample_rates); 5978 } else { 5979 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 5980 snd_hdspm_hw_rule_rate_out_channels, hdspm, 5981 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 5982 } 5983 5984 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 5985 snd_hdspm_hw_rule_out_channels, hdspm, 5986 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 5987 5988 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 5989 snd_hdspm_hw_rule_out_channels_rate, hdspm, 5990 SNDRV_PCM_HW_PARAM_RATE, -1); 5991 5992 return 0; 5993 } 5994 5995 static int snd_hdspm_playback_release(struct snd_pcm_substream *substream) 5996 { 5997 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5998 5999 spin_lock_irq(&hdspm->lock); 6000 6001 hdspm->playback_pid = -1; 6002 hdspm->playback_substream = NULL; 6003 6004 spin_unlock_irq(&hdspm->lock); 6005 6006 return 0; 6007 } 6008 6009 6010 static int snd_hdspm_capture_open(struct snd_pcm_substream *substream) 6011 { 6012 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 6013 struct snd_pcm_runtime *runtime = substream->runtime; 6014 6015 spin_lock_irq(&hdspm->lock); 6016 snd_pcm_set_sync(substream); 6017 runtime->hw = snd_hdspm_capture_subinfo; 6018 6019 if (hdspm->playback_substream == NULL) 6020 hdspm_stop_audio(hdspm); 6021 6022 hdspm->capture_pid = current->pid; 6023 hdspm->capture_substream = substream; 6024 6025 spin_unlock_irq(&hdspm->lock); 6026 6027 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24); 6028 switch (hdspm->io_type) { 6029 case AIO: 6030 case RayDAT: 6031 snd_pcm_hw_constraint_list(runtime, 0, 6032 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 6033 &hw_constraints_period_sizes_new); 6034 snd_pcm_hw_constraint_list(runtime, 0, 6035 SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 6036 &hw_constraints_raydat_io_buffer); 6037 break; 6038 6039 default: 6040 snd_pcm_hw_constraint_list(runtime, 0, 6041 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 6042 &hw_constraints_period_sizes_old); 6043 } 6044 6045 if (AES32 == hdspm->io_type) { 6046 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 6047 &hdspm_hw_constraints_aes32_sample_rates); 6048 } else { 6049 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 6050 snd_hdspm_hw_rule_rate_in_channels, hdspm, 6051 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 6052 } 6053 6054 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 6055 snd_hdspm_hw_rule_in_channels, hdspm, 6056 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 6057 6058 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 6059 snd_hdspm_hw_rule_in_channels_rate, hdspm, 6060 SNDRV_PCM_HW_PARAM_RATE, -1); 6061 6062 return 0; 6063 } 6064 6065 static int snd_hdspm_capture_release(struct snd_pcm_substream *substream) 6066 { 6067 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 6068 6069 spin_lock_irq(&hdspm->lock); 6070 6071 hdspm->capture_pid = -1; 6072 hdspm->capture_substream = NULL; 6073 6074 spin_unlock_irq(&hdspm->lock); 6075 return 0; 6076 } 6077 6078 static int snd_hdspm_hwdep_dummy_op(struct snd_hwdep *hw, struct file *file) 6079 { 6080 /* we have nothing to initialize but the call is required */ 6081 return 0; 6082 } 6083 6084 static inline int copy_u32_le(void __user *dest, void __iomem *src) 6085 { 6086 u32 val = readl(src); 6087 return copy_to_user(dest, &val, 4); 6088 } 6089 6090 static int snd_hdspm_hwdep_ioctl(struct snd_hwdep *hw, struct file *file, 6091 unsigned int cmd, unsigned long __user arg) 6092 { 6093 void __user *argp = (void __user *)arg; 6094 struct hdspm *hdspm = hw->private_data; 6095 struct hdspm_mixer_ioctl mixer; 6096 struct hdspm_config info; 6097 struct hdspm_status status; 6098 struct hdspm_version hdspm_version; 6099 struct hdspm_peak_rms *levels; 6100 struct hdspm_ltc ltc; 6101 unsigned int statusregister; 6102 long unsigned int s; 6103 int i = 0; 6104 6105 switch (cmd) { 6106 6107 case SNDRV_HDSPM_IOCTL_GET_PEAK_RMS: 6108 levels = &hdspm->peak_rms; 6109 for (i = 0; i < HDSPM_MAX_CHANNELS; i++) { 6110 levels->input_peaks[i] = 6111 readl(hdspm->iobase + 6112 HDSPM_MADI_INPUT_PEAK + i*4); 6113 levels->playback_peaks[i] = 6114 readl(hdspm->iobase + 6115 HDSPM_MADI_PLAYBACK_PEAK + i*4); 6116 levels->output_peaks[i] = 6117 readl(hdspm->iobase + 6118 HDSPM_MADI_OUTPUT_PEAK + i*4); 6119 6120 levels->input_rms[i] = 6121 ((uint64_t) readl(hdspm->iobase + 6122 HDSPM_MADI_INPUT_RMS_H + i*4) << 32) | 6123 (uint64_t) readl(hdspm->iobase + 6124 HDSPM_MADI_INPUT_RMS_L + i*4); 6125 levels->playback_rms[i] = 6126 ((uint64_t)readl(hdspm->iobase + 6127 HDSPM_MADI_PLAYBACK_RMS_H+i*4) << 32) | 6128 (uint64_t)readl(hdspm->iobase + 6129 HDSPM_MADI_PLAYBACK_RMS_L + i*4); 6130 levels->output_rms[i] = 6131 ((uint64_t)readl(hdspm->iobase + 6132 HDSPM_MADI_OUTPUT_RMS_H + i*4) << 32) | 6133 (uint64_t)readl(hdspm->iobase + 6134 HDSPM_MADI_OUTPUT_RMS_L + i*4); 6135 } 6136 6137 if (hdspm->system_sample_rate > 96000) { 6138 levels->speed = qs; 6139 } else if (hdspm->system_sample_rate > 48000) { 6140 levels->speed = ds; 6141 } else { 6142 levels->speed = ss; 6143 } 6144 levels->status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 6145 6146 s = copy_to_user(argp, levels, sizeof(struct hdspm_peak_rms)); 6147 if (0 != s) { 6148 /* snd_printk(KERN_ERR "copy_to_user(.., .., %lu): %lu 6149 [Levels]\n", sizeof(struct hdspm_peak_rms), s); 6150 */ 6151 return -EFAULT; 6152 } 6153 break; 6154 6155 case SNDRV_HDSPM_IOCTL_GET_LTC: 6156 ltc.ltc = hdspm_read(hdspm, HDSPM_RD_TCO); 6157 i = hdspm_read(hdspm, HDSPM_RD_TCO + 4); 6158 if (i & HDSPM_TCO1_LTC_Input_valid) { 6159 switch (i & (HDSPM_TCO1_LTC_Format_LSB | 6160 HDSPM_TCO1_LTC_Format_MSB)) { 6161 case 0: 6162 ltc.format = fps_24; 6163 break; 6164 case HDSPM_TCO1_LTC_Format_LSB: 6165 ltc.format = fps_25; 6166 break; 6167 case HDSPM_TCO1_LTC_Format_MSB: 6168 ltc.format = fps_2997; 6169 break; 6170 default: 6171 ltc.format = 30; 6172 break; 6173 } 6174 if (i & HDSPM_TCO1_set_drop_frame_flag) { 6175 ltc.frame = drop_frame; 6176 } else { 6177 ltc.frame = full_frame; 6178 } 6179 } else { 6180 ltc.format = format_invalid; 6181 ltc.frame = frame_invalid; 6182 } 6183 if (i & HDSPM_TCO1_Video_Input_Format_NTSC) { 6184 ltc.input_format = ntsc; 6185 } else if (i & HDSPM_TCO1_Video_Input_Format_PAL) { 6186 ltc.input_format = pal; 6187 } else { 6188 ltc.input_format = no_video; 6189 } 6190 6191 s = copy_to_user(argp, <c, sizeof(struct hdspm_ltc)); 6192 if (0 != s) { 6193 /* 6194 snd_printk(KERN_ERR "copy_to_user(.., .., %lu): %lu [LTC]\n", sizeof(struct hdspm_ltc), s); */ 6195 return -EFAULT; 6196 } 6197 6198 break; 6199 6200 case SNDRV_HDSPM_IOCTL_GET_CONFIG: 6201 6202 memset(&info, 0, sizeof(info)); 6203 spin_lock_irq(&hdspm->lock); 6204 info.pref_sync_ref = hdspm_pref_sync_ref(hdspm); 6205 info.wordclock_sync_check = hdspm_wc_sync_check(hdspm); 6206 6207 info.system_sample_rate = hdspm->system_sample_rate; 6208 info.autosync_sample_rate = 6209 hdspm_external_sample_rate(hdspm); 6210 info.system_clock_mode = hdspm_system_clock_mode(hdspm); 6211 info.clock_source = hdspm_clock_source(hdspm); 6212 info.autosync_ref = hdspm_autosync_ref(hdspm); 6213 info.line_out = hdspm_line_out(hdspm); 6214 info.passthru = 0; 6215 spin_unlock_irq(&hdspm->lock); 6216 if (copy_to_user((void __user *) arg, &info, sizeof(info))) 6217 return -EFAULT; 6218 break; 6219 6220 case SNDRV_HDSPM_IOCTL_GET_STATUS: 6221 status.card_type = hdspm->io_type; 6222 6223 status.autosync_source = hdspm_autosync_ref(hdspm); 6224 6225 status.card_clock = 110069313433624ULL; 6226 status.master_period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ); 6227 6228 switch (hdspm->io_type) { 6229 case MADI: 6230 case MADIface: 6231 status.card_specific.madi.sync_wc = 6232 hdspm_wc_sync_check(hdspm); 6233 status.card_specific.madi.sync_madi = 6234 hdspm_madi_sync_check(hdspm); 6235 status.card_specific.madi.sync_tco = 6236 hdspm_tco_sync_check(hdspm); 6237 status.card_specific.madi.sync_in = 6238 hdspm_sync_in_sync_check(hdspm); 6239 6240 statusregister = 6241 hdspm_read(hdspm, HDSPM_statusRegister); 6242 status.card_specific.madi.madi_input = 6243 (statusregister & HDSPM_AB_int) ? 1 : 0; 6244 status.card_specific.madi.channel_format = 6245 (statusregister & HDSPM_TX_64ch) ? 1 : 0; 6246 /* TODO: Mac driver sets it when f_s>48kHz */ 6247 status.card_specific.madi.frame_format = 0; 6248 6249 default: 6250 break; 6251 } 6252 6253 if (copy_to_user((void __user *) arg, &status, sizeof(status))) 6254 return -EFAULT; 6255 6256 6257 break; 6258 6259 case SNDRV_HDSPM_IOCTL_GET_VERSION: 6260 hdspm_version.card_type = hdspm->io_type; 6261 strncpy(hdspm_version.cardname, hdspm->card_name, 6262 sizeof(hdspm_version.cardname)); 6263 hdspm_version.serial = (hdspm_read(hdspm, 6264 HDSPM_midiStatusIn0)>>8) & 0xFFFFFF; 6265 hdspm_version.firmware_rev = hdspm->firmware_rev; 6266 hdspm_version.addons = 0; 6267 if (hdspm->tco) 6268 hdspm_version.addons |= HDSPM_ADDON_TCO; 6269 6270 if (copy_to_user((void __user *) arg, &hdspm_version, 6271 sizeof(hdspm_version))) 6272 return -EFAULT; 6273 break; 6274 6275 case SNDRV_HDSPM_IOCTL_GET_MIXER: 6276 if (copy_from_user(&mixer, (void __user *)arg, sizeof(mixer))) 6277 return -EFAULT; 6278 if (copy_to_user((void __user *)mixer.mixer, hdspm->mixer, 6279 sizeof(struct hdspm_mixer))) 6280 return -EFAULT; 6281 break; 6282 6283 default: 6284 return -EINVAL; 6285 } 6286 return 0; 6287 } 6288 6289 static struct snd_pcm_ops snd_hdspm_playback_ops = { 6290 .open = snd_hdspm_playback_open, 6291 .close = snd_hdspm_playback_release, 6292 .ioctl = snd_hdspm_ioctl, 6293 .hw_params = snd_hdspm_hw_params, 6294 .hw_free = snd_hdspm_hw_free, 6295 .prepare = snd_hdspm_prepare, 6296 .trigger = snd_hdspm_trigger, 6297 .pointer = snd_hdspm_hw_pointer, 6298 .page = snd_pcm_sgbuf_ops_page, 6299 }; 6300 6301 static struct snd_pcm_ops snd_hdspm_capture_ops = { 6302 .open = snd_hdspm_capture_open, 6303 .close = snd_hdspm_capture_release, 6304 .ioctl = snd_hdspm_ioctl, 6305 .hw_params = snd_hdspm_hw_params, 6306 .hw_free = snd_hdspm_hw_free, 6307 .prepare = snd_hdspm_prepare, 6308 .trigger = snd_hdspm_trigger, 6309 .pointer = snd_hdspm_hw_pointer, 6310 .page = snd_pcm_sgbuf_ops_page, 6311 }; 6312 6313 static int __devinit snd_hdspm_create_hwdep(struct snd_card *card, 6314 struct hdspm * hdspm) 6315 { 6316 struct snd_hwdep *hw; 6317 int err; 6318 6319 err = snd_hwdep_new(card, "HDSPM hwdep", 0, &hw); 6320 if (err < 0) 6321 return err; 6322 6323 hdspm->hwdep = hw; 6324 hw->private_data = hdspm; 6325 strcpy(hw->name, "HDSPM hwdep interface"); 6326 6327 hw->ops.open = snd_hdspm_hwdep_dummy_op; 6328 hw->ops.ioctl = snd_hdspm_hwdep_ioctl; 6329 hw->ops.release = snd_hdspm_hwdep_dummy_op; 6330 6331 return 0; 6332 } 6333 6334 6335 /*------------------------------------------------------------ 6336 memory interface 6337 ------------------------------------------------------------*/ 6338 static int __devinit snd_hdspm_preallocate_memory(struct hdspm *hdspm) 6339 { 6340 int err; 6341 struct snd_pcm *pcm; 6342 size_t wanted; 6343 6344 pcm = hdspm->pcm; 6345 6346 wanted = HDSPM_DMA_AREA_BYTES; 6347 6348 err = 6349 snd_pcm_lib_preallocate_pages_for_all(pcm, 6350 SNDRV_DMA_TYPE_DEV_SG, 6351 snd_dma_pci_data(hdspm->pci), 6352 wanted, 6353 wanted); 6354 if (err < 0) { 6355 snd_printdd("Could not preallocate %zd Bytes\n", wanted); 6356 6357 return err; 6358 } else 6359 snd_printdd(" Preallocated %zd Bytes\n", wanted); 6360 6361 return 0; 6362 } 6363 6364 6365 static void hdspm_set_sgbuf(struct hdspm *hdspm, 6366 struct snd_pcm_substream *substream, 6367 unsigned int reg, int channels) 6368 { 6369 int i; 6370 6371 /* continuous memory segment */ 6372 for (i = 0; i < (channels * 16); i++) 6373 hdspm_write(hdspm, reg + 4 * i, 6374 snd_pcm_sgbuf_get_addr(substream, 4096 * i)); 6375 } 6376 6377 6378 /* ------------- ALSA Devices ---------------------------- */ 6379 static int __devinit snd_hdspm_create_pcm(struct snd_card *card, 6380 struct hdspm *hdspm) 6381 { 6382 struct snd_pcm *pcm; 6383 int err; 6384 6385 err = snd_pcm_new(card, hdspm->card_name, 0, 1, 1, &pcm); 6386 if (err < 0) 6387 return err; 6388 6389 hdspm->pcm = pcm; 6390 pcm->private_data = hdspm; 6391 strcpy(pcm->name, hdspm->card_name); 6392 6393 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, 6394 &snd_hdspm_playback_ops); 6395 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, 6396 &snd_hdspm_capture_ops); 6397 6398 pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX; 6399 6400 err = snd_hdspm_preallocate_memory(hdspm); 6401 if (err < 0) 6402 return err; 6403 6404 return 0; 6405 } 6406 6407 static inline void snd_hdspm_initialize_midi_flush(struct hdspm * hdspm) 6408 { 6409 int i; 6410 6411 for (i = 0; i < hdspm->midiPorts; i++) 6412 snd_hdspm_flush_midi_input(hdspm, i); 6413 } 6414 6415 static int __devinit snd_hdspm_create_alsa_devices(struct snd_card *card, 6416 struct hdspm * hdspm) 6417 { 6418 int err, i; 6419 6420 snd_printdd("Create card...\n"); 6421 err = snd_hdspm_create_pcm(card, hdspm); 6422 if (err < 0) 6423 return err; 6424 6425 i = 0; 6426 while (i < hdspm->midiPorts) { 6427 err = snd_hdspm_create_midi(card, hdspm, i); 6428 if (err < 0) { 6429 return err; 6430 } 6431 i++; 6432 } 6433 6434 err = snd_hdspm_create_controls(card, hdspm); 6435 if (err < 0) 6436 return err; 6437 6438 err = snd_hdspm_create_hwdep(card, hdspm); 6439 if (err < 0) 6440 return err; 6441 6442 snd_printdd("proc init...\n"); 6443 snd_hdspm_proc_init(hdspm); 6444 6445 hdspm->system_sample_rate = -1; 6446 hdspm->last_external_sample_rate = -1; 6447 hdspm->last_internal_sample_rate = -1; 6448 hdspm->playback_pid = -1; 6449 hdspm->capture_pid = -1; 6450 hdspm->capture_substream = NULL; 6451 hdspm->playback_substream = NULL; 6452 6453 snd_printdd("Set defaults...\n"); 6454 err = snd_hdspm_set_defaults(hdspm); 6455 if (err < 0) 6456 return err; 6457 6458 snd_printdd("Update mixer controls...\n"); 6459 hdspm_update_simple_mixer_controls(hdspm); 6460 6461 snd_printdd("Initializeing complete ???\n"); 6462 6463 err = snd_card_register(card); 6464 if (err < 0) { 6465 snd_printk(KERN_ERR "HDSPM: error registering card\n"); 6466 return err; 6467 } 6468 6469 snd_printdd("... yes now\n"); 6470 6471 return 0; 6472 } 6473 6474 static int __devinit snd_hdspm_create(struct snd_card *card, 6475 struct hdspm *hdspm) { 6476 6477 struct pci_dev *pci = hdspm->pci; 6478 int err; 6479 unsigned long io_extent; 6480 6481 hdspm->irq = -1; 6482 hdspm->card = card; 6483 6484 spin_lock_init(&hdspm->lock); 6485 6486 pci_read_config_word(hdspm->pci, 6487 PCI_CLASS_REVISION, &hdspm->firmware_rev); 6488 6489 strcpy(card->mixername, "Xilinx FPGA"); 6490 strcpy(card->driver, "HDSPM"); 6491 6492 switch (hdspm->firmware_rev) { 6493 case HDSPM_MADI_REV: 6494 case HDSPM_MADI_OLD_REV: 6495 case HDSPM_MADI_ANCIENT_REV: 6496 hdspm->io_type = MADI; 6497 hdspm->card_name = "RME MADI"; 6498 hdspm->midiPorts = 3; 6499 break; 6500 case HDSPM_RAYDAT_REV: 6501 hdspm->io_type = RayDAT; 6502 hdspm->card_name = "RME RayDAT"; 6503 hdspm->midiPorts = 2; 6504 break; 6505 case HDSPM_AIO_REV: 6506 hdspm->io_type = AIO; 6507 hdspm->card_name = "RME AIO"; 6508 hdspm->midiPorts = 1; 6509 break; 6510 case HDSPM_MADIFACE_REV: 6511 hdspm->io_type = MADIface; 6512 hdspm->card_name = "RME MADIface"; 6513 hdspm->midiPorts = 1; 6514 break; 6515 case HDSPM_AES_REV: 6516 case HDSPM_AES32_REV: 6517 case HDSPM_AES32_OLD_REV: 6518 hdspm->io_type = AES32; 6519 hdspm->card_name = "RME AES32"; 6520 hdspm->midiPorts = 2; 6521 break; 6522 default: 6523 snd_printk(KERN_ERR "HDSPM: unknown firmware revision %x\n", 6524 hdspm->firmware_rev); 6525 return -ENODEV; 6526 } 6527 6528 err = pci_enable_device(pci); 6529 if (err < 0) 6530 return err; 6531 6532 pci_set_master(hdspm->pci); 6533 6534 err = pci_request_regions(pci, "hdspm"); 6535 if (err < 0) 6536 return err; 6537 6538 hdspm->port = pci_resource_start(pci, 0); 6539 io_extent = pci_resource_len(pci, 0); 6540 6541 snd_printdd("grabbed memory region 0x%lx-0x%lx\n", 6542 hdspm->port, hdspm->port + io_extent - 1); 6543 6544 hdspm->iobase = ioremap_nocache(hdspm->port, io_extent); 6545 if (!hdspm->iobase) { 6546 snd_printk(KERN_ERR "HDSPM: " 6547 "unable to remap region 0x%lx-0x%lx\n", 6548 hdspm->port, hdspm->port + io_extent - 1); 6549 return -EBUSY; 6550 } 6551 snd_printdd("remapped region (0x%lx) 0x%lx-0x%lx\n", 6552 (unsigned long)hdspm->iobase, hdspm->port, 6553 hdspm->port + io_extent - 1); 6554 6555 if (request_irq(pci->irq, snd_hdspm_interrupt, 6556 IRQF_SHARED, KBUILD_MODNAME, hdspm)) { 6557 snd_printk(KERN_ERR "HDSPM: unable to use IRQ %d\n", pci->irq); 6558 return -EBUSY; 6559 } 6560 6561 snd_printdd("use IRQ %d\n", pci->irq); 6562 6563 hdspm->irq = pci->irq; 6564 6565 snd_printdd("kmalloc Mixer memory of %zd Bytes\n", 6566 sizeof(struct hdspm_mixer)); 6567 hdspm->mixer = kzalloc(sizeof(struct hdspm_mixer), GFP_KERNEL); 6568 if (!hdspm->mixer) { 6569 snd_printk(KERN_ERR "HDSPM: " 6570 "unable to kmalloc Mixer memory of %d Bytes\n", 6571 (int)sizeof(struct hdspm_mixer)); 6572 return err; 6573 } 6574 6575 hdspm->port_names_in = NULL; 6576 hdspm->port_names_out = NULL; 6577 6578 switch (hdspm->io_type) { 6579 case AES32: 6580 hdspm->ss_in_channels = hdspm->ss_out_channels = AES32_CHANNELS; 6581 hdspm->ds_in_channels = hdspm->ds_out_channels = AES32_CHANNELS; 6582 hdspm->qs_in_channels = hdspm->qs_out_channels = AES32_CHANNELS; 6583 6584 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss = 6585 channel_map_aes32; 6586 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds = 6587 channel_map_aes32; 6588 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs = 6589 channel_map_aes32; 6590 hdspm->port_names_in_ss = hdspm->port_names_out_ss = 6591 texts_ports_aes32; 6592 hdspm->port_names_in_ds = hdspm->port_names_out_ds = 6593 texts_ports_aes32; 6594 hdspm->port_names_in_qs = hdspm->port_names_out_qs = 6595 texts_ports_aes32; 6596 6597 hdspm->max_channels_out = hdspm->max_channels_in = 6598 AES32_CHANNELS; 6599 hdspm->port_names_in = hdspm->port_names_out = 6600 texts_ports_aes32; 6601 hdspm->channel_map_in = hdspm->channel_map_out = 6602 channel_map_aes32; 6603 6604 break; 6605 6606 case MADI: 6607 case MADIface: 6608 hdspm->ss_in_channels = hdspm->ss_out_channels = 6609 MADI_SS_CHANNELS; 6610 hdspm->ds_in_channels = hdspm->ds_out_channels = 6611 MADI_DS_CHANNELS; 6612 hdspm->qs_in_channels = hdspm->qs_out_channels = 6613 MADI_QS_CHANNELS; 6614 6615 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss = 6616 channel_map_unity_ss; 6617 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds = 6618 channel_map_unity_ss; 6619 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs = 6620 channel_map_unity_ss; 6621 6622 hdspm->port_names_in_ss = hdspm->port_names_out_ss = 6623 texts_ports_madi; 6624 hdspm->port_names_in_ds = hdspm->port_names_out_ds = 6625 texts_ports_madi; 6626 hdspm->port_names_in_qs = hdspm->port_names_out_qs = 6627 texts_ports_madi; 6628 break; 6629 6630 case AIO: 6631 if (0 == (hdspm_read(hdspm, HDSPM_statusRegister2) & HDSPM_s2_AEBI_D)) { 6632 snd_printk(KERN_INFO "HDSPM: AEB input board found, but not supported\n"); 6633 } 6634 6635 hdspm->ss_in_channels = AIO_IN_SS_CHANNELS; 6636 hdspm->ds_in_channels = AIO_IN_DS_CHANNELS; 6637 hdspm->qs_in_channels = AIO_IN_QS_CHANNELS; 6638 hdspm->ss_out_channels = AIO_OUT_SS_CHANNELS; 6639 hdspm->ds_out_channels = AIO_OUT_DS_CHANNELS; 6640 hdspm->qs_out_channels = AIO_OUT_QS_CHANNELS; 6641 6642 hdspm->channel_map_out_ss = channel_map_aio_out_ss; 6643 hdspm->channel_map_out_ds = channel_map_aio_out_ds; 6644 hdspm->channel_map_out_qs = channel_map_aio_out_qs; 6645 6646 hdspm->channel_map_in_ss = channel_map_aio_in_ss; 6647 hdspm->channel_map_in_ds = channel_map_aio_in_ds; 6648 hdspm->channel_map_in_qs = channel_map_aio_in_qs; 6649 6650 hdspm->port_names_in_ss = texts_ports_aio_in_ss; 6651 hdspm->port_names_out_ss = texts_ports_aio_out_ss; 6652 hdspm->port_names_in_ds = texts_ports_aio_in_ds; 6653 hdspm->port_names_out_ds = texts_ports_aio_out_ds; 6654 hdspm->port_names_in_qs = texts_ports_aio_in_qs; 6655 hdspm->port_names_out_qs = texts_ports_aio_out_qs; 6656 6657 break; 6658 6659 case RayDAT: 6660 hdspm->ss_in_channels = hdspm->ss_out_channels = 6661 RAYDAT_SS_CHANNELS; 6662 hdspm->ds_in_channels = hdspm->ds_out_channels = 6663 RAYDAT_DS_CHANNELS; 6664 hdspm->qs_in_channels = hdspm->qs_out_channels = 6665 RAYDAT_QS_CHANNELS; 6666 6667 hdspm->max_channels_in = RAYDAT_SS_CHANNELS; 6668 hdspm->max_channels_out = RAYDAT_SS_CHANNELS; 6669 6670 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss = 6671 channel_map_raydat_ss; 6672 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds = 6673 channel_map_raydat_ds; 6674 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs = 6675 channel_map_raydat_qs; 6676 hdspm->channel_map_in = hdspm->channel_map_out = 6677 channel_map_raydat_ss; 6678 6679 hdspm->port_names_in_ss = hdspm->port_names_out_ss = 6680 texts_ports_raydat_ss; 6681 hdspm->port_names_in_ds = hdspm->port_names_out_ds = 6682 texts_ports_raydat_ds; 6683 hdspm->port_names_in_qs = hdspm->port_names_out_qs = 6684 texts_ports_raydat_qs; 6685 6686 6687 break; 6688 6689 } 6690 6691 /* TCO detection */ 6692 switch (hdspm->io_type) { 6693 case AIO: 6694 case RayDAT: 6695 if (hdspm_read(hdspm, HDSPM_statusRegister2) & 6696 HDSPM_s2_tco_detect) { 6697 hdspm->midiPorts++; 6698 hdspm->tco = kzalloc(sizeof(struct hdspm_tco), 6699 GFP_KERNEL); 6700 if (NULL != hdspm->tco) { 6701 hdspm_tco_write(hdspm); 6702 } 6703 snd_printk(KERN_INFO "HDSPM: AIO/RayDAT TCO module found\n"); 6704 } else { 6705 hdspm->tco = NULL; 6706 } 6707 break; 6708 6709 case MADI: 6710 if (hdspm_read(hdspm, HDSPM_statusRegister) & HDSPM_tco_detect) { 6711 hdspm->midiPorts++; 6712 hdspm->tco = kzalloc(sizeof(struct hdspm_tco), 6713 GFP_KERNEL); 6714 if (NULL != hdspm->tco) { 6715 hdspm_tco_write(hdspm); 6716 } 6717 snd_printk(KERN_INFO "HDSPM: MADI TCO module found\n"); 6718 } else { 6719 hdspm->tco = NULL; 6720 } 6721 break; 6722 6723 default: 6724 hdspm->tco = NULL; 6725 } 6726 6727 /* texts */ 6728 switch (hdspm->io_type) { 6729 case AES32: 6730 if (hdspm->tco) { 6731 hdspm->texts_autosync = texts_autosync_aes_tco; 6732 hdspm->texts_autosync_items = 10; 6733 } else { 6734 hdspm->texts_autosync = texts_autosync_aes; 6735 hdspm->texts_autosync_items = 9; 6736 } 6737 break; 6738 6739 case MADI: 6740 if (hdspm->tco) { 6741 hdspm->texts_autosync = texts_autosync_madi_tco; 6742 hdspm->texts_autosync_items = 4; 6743 } else { 6744 hdspm->texts_autosync = texts_autosync_madi; 6745 hdspm->texts_autosync_items = 3; 6746 } 6747 break; 6748 6749 case MADIface: 6750 6751 break; 6752 6753 case RayDAT: 6754 if (hdspm->tco) { 6755 hdspm->texts_autosync = texts_autosync_raydat_tco; 6756 hdspm->texts_autosync_items = 9; 6757 } else { 6758 hdspm->texts_autosync = texts_autosync_raydat; 6759 hdspm->texts_autosync_items = 8; 6760 } 6761 break; 6762 6763 case AIO: 6764 if (hdspm->tco) { 6765 hdspm->texts_autosync = texts_autosync_aio_tco; 6766 hdspm->texts_autosync_items = 6; 6767 } else { 6768 hdspm->texts_autosync = texts_autosync_aio; 6769 hdspm->texts_autosync_items = 5; 6770 } 6771 break; 6772 6773 } 6774 6775 tasklet_init(&hdspm->midi_tasklet, 6776 hdspm_midi_tasklet, (unsigned long) hdspm); 6777 6778 snd_printdd("create alsa devices.\n"); 6779 err = snd_hdspm_create_alsa_devices(card, hdspm); 6780 if (err < 0) 6781 return err; 6782 6783 snd_hdspm_initialize_midi_flush(hdspm); 6784 6785 return 0; 6786 } 6787 6788 6789 static int snd_hdspm_free(struct hdspm * hdspm) 6790 { 6791 6792 if (hdspm->port) { 6793 6794 /* stop th audio, and cancel all interrupts */ 6795 hdspm->control_register &= 6796 ~(HDSPM_Start | HDSPM_AudioInterruptEnable | 6797 HDSPM_Midi0InterruptEnable | HDSPM_Midi1InterruptEnable | 6798 HDSPM_Midi2InterruptEnable | HDSPM_Midi3InterruptEnable); 6799 hdspm_write(hdspm, HDSPM_controlRegister, 6800 hdspm->control_register); 6801 } 6802 6803 if (hdspm->irq >= 0) 6804 free_irq(hdspm->irq, (void *) hdspm); 6805 6806 kfree(hdspm->mixer); 6807 6808 if (hdspm->iobase) 6809 iounmap(hdspm->iobase); 6810 6811 if (hdspm->port) 6812 pci_release_regions(hdspm->pci); 6813 6814 pci_disable_device(hdspm->pci); 6815 return 0; 6816 } 6817 6818 6819 static void snd_hdspm_card_free(struct snd_card *card) 6820 { 6821 struct hdspm *hdspm = card->private_data; 6822 6823 if (hdspm) 6824 snd_hdspm_free(hdspm); 6825 } 6826 6827 6828 static int __devinit snd_hdspm_probe(struct pci_dev *pci, 6829 const struct pci_device_id *pci_id) 6830 { 6831 static int dev; 6832 struct hdspm *hdspm; 6833 struct snd_card *card; 6834 int err; 6835 6836 if (dev >= SNDRV_CARDS) 6837 return -ENODEV; 6838 if (!enable[dev]) { 6839 dev++; 6840 return -ENOENT; 6841 } 6842 6843 err = snd_card_create(index[dev], id[dev], 6844 THIS_MODULE, sizeof(struct hdspm), &card); 6845 if (err < 0) 6846 return err; 6847 6848 hdspm = card->private_data; 6849 card->private_free = snd_hdspm_card_free; 6850 hdspm->dev = dev; 6851 hdspm->pci = pci; 6852 6853 snd_card_set_dev(card, &pci->dev); 6854 6855 err = snd_hdspm_create(card, hdspm); 6856 if (err < 0) { 6857 snd_card_free(card); 6858 return err; 6859 } 6860 6861 if (hdspm->io_type != MADIface) { 6862 sprintf(card->shortname, "%s_%x", 6863 hdspm->card_name, 6864 (hdspm_read(hdspm, HDSPM_midiStatusIn0)>>8) & 0xFFFFFF); 6865 sprintf(card->longname, "%s S/N 0x%x at 0x%lx, irq %d", 6866 hdspm->card_name, 6867 (hdspm_read(hdspm, HDSPM_midiStatusIn0)>>8) & 0xFFFFFF, 6868 hdspm->port, hdspm->irq); 6869 } else { 6870 sprintf(card->shortname, "%s", hdspm->card_name); 6871 sprintf(card->longname, "%s at 0x%lx, irq %d", 6872 hdspm->card_name, hdspm->port, hdspm->irq); 6873 } 6874 6875 err = snd_card_register(card); 6876 if (err < 0) { 6877 snd_card_free(card); 6878 return err; 6879 } 6880 6881 pci_set_drvdata(pci, card); 6882 6883 dev++; 6884 return 0; 6885 } 6886 6887 static void __devexit snd_hdspm_remove(struct pci_dev *pci) 6888 { 6889 snd_card_free(pci_get_drvdata(pci)); 6890 pci_set_drvdata(pci, NULL); 6891 } 6892 6893 static struct pci_driver driver = { 6894 .name = KBUILD_MODNAME, 6895 .id_table = snd_hdspm_ids, 6896 .probe = snd_hdspm_probe, 6897 .remove = __devexit_p(snd_hdspm_remove), 6898 }; 6899 6900 6901 static int __init alsa_card_hdspm_init(void) 6902 { 6903 return pci_register_driver(&driver); 6904 } 6905 6906 static void __exit alsa_card_hdspm_exit(void) 6907 { 6908 pci_unregister_driver(&driver); 6909 } 6910 6911 module_init(alsa_card_hdspm_init) 6912 module_exit(alsa_card_hdspm_exit) 6913