1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * ALSA driver for RME Hammerfall DSP audio interface(s) 4 * 5 * Copyright (c) 2002 Paul Davis 6 * Marcus Andersson 7 * Thomas Charbonnel 8 */ 9 10 #include <linux/init.h> 11 #include <linux/delay.h> 12 #include <linux/interrupt.h> 13 #include <linux/pci.h> 14 #include <linux/firmware.h> 15 #include <linux/module.h> 16 #include <linux/math64.h> 17 #include <linux/vmalloc.h> 18 #include <linux/io.h> 19 #include <linux/nospec.h> 20 21 #include <sound/core.h> 22 #include <sound/control.h> 23 #include <sound/pcm.h> 24 #include <sound/info.h> 25 #include <sound/asoundef.h> 26 #include <sound/rawmidi.h> 27 #include <sound/hwdep.h> 28 #include <sound/initval.h> 29 #include <sound/hdsp.h> 30 31 #include <asm/byteorder.h> 32 #include <asm/current.h> 33 34 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ 35 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ 36 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */ 37 38 module_param_array(index, int, NULL, 0444); 39 MODULE_PARM_DESC(index, "Index value for RME Hammerfall DSP interface."); 40 module_param_array(id, charp, NULL, 0444); 41 MODULE_PARM_DESC(id, "ID string for RME Hammerfall DSP interface."); 42 module_param_array(enable, bool, NULL, 0444); 43 MODULE_PARM_DESC(enable, "Enable/disable specific Hammerfall DSP soundcards."); 44 MODULE_AUTHOR("Paul Davis <paul@linuxaudiosystems.com>, Marcus Andersson, Thomas Charbonnel <thomas@undata.org>"); 45 MODULE_DESCRIPTION("RME Hammerfall DSP"); 46 MODULE_LICENSE("GPL"); 47 MODULE_FIRMWARE("rpm_firmware.bin"); 48 MODULE_FIRMWARE("multiface_firmware.bin"); 49 MODULE_FIRMWARE("multiface_firmware_rev11.bin"); 50 MODULE_FIRMWARE("digiface_firmware.bin"); 51 MODULE_FIRMWARE("digiface_firmware_rev11.bin"); 52 53 #define HDSP_MAX_CHANNELS 26 54 #define HDSP_MAX_DS_CHANNELS 14 55 #define HDSP_MAX_QS_CHANNELS 8 56 #define DIGIFACE_SS_CHANNELS 26 57 #define DIGIFACE_DS_CHANNELS 14 58 #define MULTIFACE_SS_CHANNELS 18 59 #define MULTIFACE_DS_CHANNELS 14 60 #define H9652_SS_CHANNELS 26 61 #define H9652_DS_CHANNELS 14 62 /* This does not include possible Analog Extension Boards 63 AEBs are detected at card initialization 64 */ 65 #define H9632_SS_CHANNELS 12 66 #define H9632_DS_CHANNELS 8 67 #define H9632_QS_CHANNELS 4 68 #define RPM_CHANNELS 6 69 70 /* Write registers. These are defined as byte-offsets from the iobase value. 71 */ 72 #define HDSP_resetPointer 0 73 #define HDSP_freqReg 0 74 #define HDSP_outputBufferAddress 32 75 #define HDSP_inputBufferAddress 36 76 #define HDSP_controlRegister 64 77 #define HDSP_interruptConfirmation 96 78 #define HDSP_outputEnable 128 79 #define HDSP_control2Reg 256 80 #define HDSP_midiDataOut0 352 81 #define HDSP_midiDataOut1 356 82 #define HDSP_fifoData 368 83 #define HDSP_inputEnable 384 84 85 /* Read registers. These are defined as byte-offsets from the iobase value 86 */ 87 88 #define HDSP_statusRegister 0 89 #define HDSP_timecode 128 90 #define HDSP_status2Register 192 91 #define HDSP_midiDataIn0 360 92 #define HDSP_midiDataIn1 364 93 #define HDSP_midiStatusOut0 384 94 #define HDSP_midiStatusOut1 388 95 #define HDSP_midiStatusIn0 392 96 #define HDSP_midiStatusIn1 396 97 #define HDSP_fifoStatus 400 98 99 /* the meters are regular i/o-mapped registers, but offset 100 considerably from the rest. the peak registers are reset 101 when read; the least-significant 4 bits are full-scale counters; 102 the actual peak value is in the most-significant 24 bits. 103 */ 104 105 #define HDSP_playbackPeakLevel 4096 /* 26 * 32 bit values */ 106 #define HDSP_inputPeakLevel 4224 /* 26 * 32 bit values */ 107 #define HDSP_outputPeakLevel 4352 /* (26+2) * 32 bit values */ 108 #define HDSP_playbackRmsLevel 4612 /* 26 * 64 bit values */ 109 #define HDSP_inputRmsLevel 4868 /* 26 * 64 bit values */ 110 111 112 /* This is for H9652 cards 113 Peak values are read downward from the base 114 Rms values are read upward 115 There are rms values for the outputs too 116 26*3 values are read in ss mode 117 14*3 in ds mode, with no gap between values 118 */ 119 #define HDSP_9652_peakBase 7164 120 #define HDSP_9652_rmsBase 4096 121 122 /* c.f. the hdsp_9632_meters_t struct */ 123 #define HDSP_9632_metersBase 4096 124 125 #define HDSP_IO_EXTENT 7168 126 127 /* control2 register bits */ 128 129 #define HDSP_TMS 0x01 130 #define HDSP_TCK 0x02 131 #define HDSP_TDI 0x04 132 #define HDSP_JTAG 0x08 133 #define HDSP_PWDN 0x10 134 #define HDSP_PROGRAM 0x020 135 #define HDSP_CONFIG_MODE_0 0x040 136 #define HDSP_CONFIG_MODE_1 0x080 137 #define HDSP_VERSION_BIT (0x100 | HDSP_S_LOAD) 138 #define HDSP_BIGENDIAN_MODE 0x200 139 #define HDSP_RD_MULTIPLE 0x400 140 #define HDSP_9652_ENABLE_MIXER 0x800 141 #define HDSP_S200 0x800 142 #define HDSP_S300 (0x100 | HDSP_S200) /* dummy, purpose of 0x100 unknown */ 143 #define HDSP_CYCLIC_MODE 0x1000 144 #define HDSP_TDO 0x10000000 145 146 #define HDSP_S_PROGRAM (HDSP_CYCLIC_MODE|HDSP_PROGRAM|HDSP_CONFIG_MODE_0) 147 #define HDSP_S_LOAD (HDSP_CYCLIC_MODE|HDSP_PROGRAM|HDSP_CONFIG_MODE_1) 148 149 /* Control Register bits */ 150 151 #define HDSP_Start (1<<0) /* start engine */ 152 #define HDSP_Latency0 (1<<1) /* buffer size = 2^n where n is defined by Latency{2,1,0} */ 153 #define HDSP_Latency1 (1<<2) /* [ see above ] */ 154 #define HDSP_Latency2 (1<<3) /* [ see above ] */ 155 #define HDSP_ClockModeMaster (1<<4) /* 1=Master, 0=Slave/Autosync */ 156 #define HDSP_AudioInterruptEnable (1<<5) /* what do you think ? */ 157 #define HDSP_Frequency0 (1<<6) /* 0=44.1kHz/88.2kHz/176.4kHz 1=48kHz/96kHz/192kHz */ 158 #define HDSP_Frequency1 (1<<7) /* 0=32kHz/64kHz/128kHz */ 159 #define HDSP_DoubleSpeed (1<<8) /* 0=normal speed, 1=double speed */ 160 #define HDSP_SPDIFProfessional (1<<9) /* 0=consumer, 1=professional */ 161 #define HDSP_SPDIFEmphasis (1<<10) /* 0=none, 1=on */ 162 #define HDSP_SPDIFNonAudio (1<<11) /* 0=off, 1=on */ 163 #define HDSP_SPDIFOpticalOut (1<<12) /* 1=use 1st ADAT connector for SPDIF, 0=do not */ 164 #define HDSP_SyncRef2 (1<<13) 165 #define HDSP_SPDIFInputSelect0 (1<<14) 166 #define HDSP_SPDIFInputSelect1 (1<<15) 167 #define HDSP_SyncRef0 (1<<16) 168 #define HDSP_SyncRef1 (1<<17) 169 #define HDSP_AnalogExtensionBoard (1<<18) /* For H9632 cards */ 170 #define HDSP_XLRBreakoutCable (1<<20) /* For H9632 cards */ 171 #define HDSP_Midi0InterruptEnable (1<<22) 172 #define HDSP_Midi1InterruptEnable (1<<23) 173 #define HDSP_LineOut (1<<24) 174 #define HDSP_ADGain0 (1<<25) /* From here : H9632 specific */ 175 #define HDSP_ADGain1 (1<<26) 176 #define HDSP_DAGain0 (1<<27) 177 #define HDSP_DAGain1 (1<<28) 178 #define HDSP_PhoneGain0 (1<<29) 179 #define HDSP_PhoneGain1 (1<<30) 180 #define HDSP_QuadSpeed (1<<31) 181 182 /* RPM uses some of the registers for special purposes */ 183 #define HDSP_RPM_Inp12 0x04A00 184 #define HDSP_RPM_Inp12_Phon_6dB 0x00800 /* Dolby */ 185 #define HDSP_RPM_Inp12_Phon_0dB 0x00000 /* .. */ 186 #define HDSP_RPM_Inp12_Phon_n6dB 0x04000 /* inp_0 */ 187 #define HDSP_RPM_Inp12_Line_0dB 0x04200 /* Dolby+PRO */ 188 #define HDSP_RPM_Inp12_Line_n6dB 0x00200 /* PRO */ 189 190 #define HDSP_RPM_Inp34 0x32000 191 #define HDSP_RPM_Inp34_Phon_6dB 0x20000 /* SyncRef1 */ 192 #define HDSP_RPM_Inp34_Phon_0dB 0x00000 /* .. */ 193 #define HDSP_RPM_Inp34_Phon_n6dB 0x02000 /* SyncRef2 */ 194 #define HDSP_RPM_Inp34_Line_0dB 0x30000 /* SyncRef1+SyncRef0 */ 195 #define HDSP_RPM_Inp34_Line_n6dB 0x10000 /* SyncRef0 */ 196 197 #define HDSP_RPM_Bypass 0x01000 198 199 #define HDSP_RPM_Disconnect 0x00001 200 201 #define HDSP_ADGainMask (HDSP_ADGain0|HDSP_ADGain1) 202 #define HDSP_ADGainMinus10dBV HDSP_ADGainMask 203 #define HDSP_ADGainPlus4dBu (HDSP_ADGain0) 204 #define HDSP_ADGainLowGain 0 205 206 #define HDSP_DAGainMask (HDSP_DAGain0|HDSP_DAGain1) 207 #define HDSP_DAGainHighGain HDSP_DAGainMask 208 #define HDSP_DAGainPlus4dBu (HDSP_DAGain0) 209 #define HDSP_DAGainMinus10dBV 0 210 211 #define HDSP_PhoneGainMask (HDSP_PhoneGain0|HDSP_PhoneGain1) 212 #define HDSP_PhoneGain0dB HDSP_PhoneGainMask 213 #define HDSP_PhoneGainMinus6dB (HDSP_PhoneGain0) 214 #define HDSP_PhoneGainMinus12dB 0 215 216 #define HDSP_LatencyMask (HDSP_Latency0|HDSP_Latency1|HDSP_Latency2) 217 #define HDSP_FrequencyMask (HDSP_Frequency0|HDSP_Frequency1|HDSP_DoubleSpeed|HDSP_QuadSpeed) 218 219 #define HDSP_SPDIFInputMask (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1) 220 #define HDSP_SPDIFInputADAT1 0 221 #define HDSP_SPDIFInputCoaxial (HDSP_SPDIFInputSelect0) 222 #define HDSP_SPDIFInputCdrom (HDSP_SPDIFInputSelect1) 223 #define HDSP_SPDIFInputAES (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1) 224 225 #define HDSP_SyncRefMask (HDSP_SyncRef0|HDSP_SyncRef1|HDSP_SyncRef2) 226 #define HDSP_SyncRef_ADAT1 0 227 #define HDSP_SyncRef_ADAT2 (HDSP_SyncRef0) 228 #define HDSP_SyncRef_ADAT3 (HDSP_SyncRef1) 229 #define HDSP_SyncRef_SPDIF (HDSP_SyncRef0|HDSP_SyncRef1) 230 #define HDSP_SyncRef_WORD (HDSP_SyncRef2) 231 #define HDSP_SyncRef_ADAT_SYNC (HDSP_SyncRef0|HDSP_SyncRef2) 232 233 /* Sample Clock Sources */ 234 235 #define HDSP_CLOCK_SOURCE_AUTOSYNC 0 236 #define HDSP_CLOCK_SOURCE_INTERNAL_32KHZ 1 237 #define HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ 2 238 #define HDSP_CLOCK_SOURCE_INTERNAL_48KHZ 3 239 #define HDSP_CLOCK_SOURCE_INTERNAL_64KHZ 4 240 #define HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ 5 241 #define HDSP_CLOCK_SOURCE_INTERNAL_96KHZ 6 242 #define HDSP_CLOCK_SOURCE_INTERNAL_128KHZ 7 243 #define HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ 8 244 #define HDSP_CLOCK_SOURCE_INTERNAL_192KHZ 9 245 246 /* Preferred sync reference choices - used by "pref_sync_ref" control switch */ 247 248 #define HDSP_SYNC_FROM_WORD 0 249 #define HDSP_SYNC_FROM_SPDIF 1 250 #define HDSP_SYNC_FROM_ADAT1 2 251 #define HDSP_SYNC_FROM_ADAT_SYNC 3 252 #define HDSP_SYNC_FROM_ADAT2 4 253 #define HDSP_SYNC_FROM_ADAT3 5 254 255 /* SyncCheck status */ 256 257 #define HDSP_SYNC_CHECK_NO_LOCK 0 258 #define HDSP_SYNC_CHECK_LOCK 1 259 #define HDSP_SYNC_CHECK_SYNC 2 260 261 /* AutoSync references - used by "autosync_ref" control switch */ 262 263 #define HDSP_AUTOSYNC_FROM_WORD 0 264 #define HDSP_AUTOSYNC_FROM_ADAT_SYNC 1 265 #define HDSP_AUTOSYNC_FROM_SPDIF 2 266 #define HDSP_AUTOSYNC_FROM_NONE 3 267 #define HDSP_AUTOSYNC_FROM_ADAT1 4 268 #define HDSP_AUTOSYNC_FROM_ADAT2 5 269 #define HDSP_AUTOSYNC_FROM_ADAT3 6 270 271 /* Possible sources of S/PDIF input */ 272 273 #define HDSP_SPDIFIN_OPTICAL 0 /* optical (ADAT1) */ 274 #define HDSP_SPDIFIN_COAXIAL 1 /* coaxial (RCA) */ 275 #define HDSP_SPDIFIN_INTERNAL 2 /* internal (CDROM) */ 276 #define HDSP_SPDIFIN_AES 3 /* xlr for H9632 (AES)*/ 277 278 #define HDSP_Frequency32KHz HDSP_Frequency0 279 #define HDSP_Frequency44_1KHz HDSP_Frequency1 280 #define HDSP_Frequency48KHz (HDSP_Frequency1|HDSP_Frequency0) 281 #define HDSP_Frequency64KHz (HDSP_DoubleSpeed|HDSP_Frequency0) 282 #define HDSP_Frequency88_2KHz (HDSP_DoubleSpeed|HDSP_Frequency1) 283 #define HDSP_Frequency96KHz (HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0) 284 /* For H9632 cards */ 285 #define HDSP_Frequency128KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency0) 286 #define HDSP_Frequency176_4KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1) 287 #define HDSP_Frequency192KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0) 288 /* RME says n = 104857600000000, but in the windows MADI driver, I see: 289 return 104857600000000 / rate; // 100 MHz 290 return 110100480000000 / rate; // 105 MHz 291 */ 292 #define DDS_NUMERATOR 104857600000000ULL /* = 2^20 * 10^8 */ 293 294 #define hdsp_encode_latency(x) (((x)<<1) & HDSP_LatencyMask) 295 #define hdsp_decode_latency(x) (((x) & HDSP_LatencyMask)>>1) 296 297 #define hdsp_encode_spdif_in(x) (((x)&0x3)<<14) 298 #define hdsp_decode_spdif_in(x) (((x)>>14)&0x3) 299 300 /* Status Register bits */ 301 302 #define HDSP_audioIRQPending (1<<0) 303 #define HDSP_Lock2 (1<<1) /* this is for Digiface and H9652 */ 304 #define HDSP_spdifFrequency3 HDSP_Lock2 /* this is for H9632 only */ 305 #define HDSP_Lock1 (1<<2) 306 #define HDSP_Lock0 (1<<3) 307 #define HDSP_SPDIFSync (1<<4) 308 #define HDSP_TimecodeLock (1<<5) 309 #define HDSP_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */ 310 #define HDSP_Sync2 (1<<16) 311 #define HDSP_Sync1 (1<<17) 312 #define HDSP_Sync0 (1<<18) 313 #define HDSP_DoubleSpeedStatus (1<<19) 314 #define HDSP_ConfigError (1<<20) 315 #define HDSP_DllError (1<<21) 316 #define HDSP_spdifFrequency0 (1<<22) 317 #define HDSP_spdifFrequency1 (1<<23) 318 #define HDSP_spdifFrequency2 (1<<24) 319 #define HDSP_SPDIFErrorFlag (1<<25) 320 #define HDSP_BufferID (1<<26) 321 #define HDSP_TimecodeSync (1<<27) 322 #define HDSP_AEBO (1<<28) /* H9632 specific Analog Extension Boards */ 323 #define HDSP_AEBI (1<<29) /* 0 = present, 1 = absent */ 324 #define HDSP_midi0IRQPending (1<<30) 325 #define HDSP_midi1IRQPending (1<<31) 326 327 #define HDSP_spdifFrequencyMask (HDSP_spdifFrequency0|HDSP_spdifFrequency1|HDSP_spdifFrequency2) 328 #define HDSP_spdifFrequencyMask_9632 (HDSP_spdifFrequency0|\ 329 HDSP_spdifFrequency1|\ 330 HDSP_spdifFrequency2|\ 331 HDSP_spdifFrequency3) 332 333 #define HDSP_spdifFrequency32KHz (HDSP_spdifFrequency0) 334 #define HDSP_spdifFrequency44_1KHz (HDSP_spdifFrequency1) 335 #define HDSP_spdifFrequency48KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency1) 336 337 #define HDSP_spdifFrequency64KHz (HDSP_spdifFrequency2) 338 #define HDSP_spdifFrequency88_2KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency2) 339 #define HDSP_spdifFrequency96KHz (HDSP_spdifFrequency2|HDSP_spdifFrequency1) 340 341 /* This is for H9632 cards */ 342 #define HDSP_spdifFrequency128KHz (HDSP_spdifFrequency0|\ 343 HDSP_spdifFrequency1|\ 344 HDSP_spdifFrequency2) 345 #define HDSP_spdifFrequency176_4KHz HDSP_spdifFrequency3 346 #define HDSP_spdifFrequency192KHz (HDSP_spdifFrequency3|HDSP_spdifFrequency0) 347 348 /* Status2 Register bits */ 349 350 #define HDSP_version0 (1<<0) 351 #define HDSP_version1 (1<<1) 352 #define HDSP_version2 (1<<2) 353 #define HDSP_wc_lock (1<<3) 354 #define HDSP_wc_sync (1<<4) 355 #define HDSP_inp_freq0 (1<<5) 356 #define HDSP_inp_freq1 (1<<6) 357 #define HDSP_inp_freq2 (1<<7) 358 #define HDSP_SelSyncRef0 (1<<8) 359 #define HDSP_SelSyncRef1 (1<<9) 360 #define HDSP_SelSyncRef2 (1<<10) 361 362 #define HDSP_wc_valid (HDSP_wc_lock|HDSP_wc_sync) 363 364 #define HDSP_systemFrequencyMask (HDSP_inp_freq0|HDSP_inp_freq1|HDSP_inp_freq2) 365 #define HDSP_systemFrequency32 (HDSP_inp_freq0) 366 #define HDSP_systemFrequency44_1 (HDSP_inp_freq1) 367 #define HDSP_systemFrequency48 (HDSP_inp_freq0|HDSP_inp_freq1) 368 #define HDSP_systemFrequency64 (HDSP_inp_freq2) 369 #define HDSP_systemFrequency88_2 (HDSP_inp_freq0|HDSP_inp_freq2) 370 #define HDSP_systemFrequency96 (HDSP_inp_freq1|HDSP_inp_freq2) 371 /* FIXME : more values for 9632 cards ? */ 372 373 #define HDSP_SelSyncRefMask (HDSP_SelSyncRef0|HDSP_SelSyncRef1|HDSP_SelSyncRef2) 374 #define HDSP_SelSyncRef_ADAT1 0 375 #define HDSP_SelSyncRef_ADAT2 (HDSP_SelSyncRef0) 376 #define HDSP_SelSyncRef_ADAT3 (HDSP_SelSyncRef1) 377 #define HDSP_SelSyncRef_SPDIF (HDSP_SelSyncRef0|HDSP_SelSyncRef1) 378 #define HDSP_SelSyncRef_WORD (HDSP_SelSyncRef2) 379 #define HDSP_SelSyncRef_ADAT_SYNC (HDSP_SelSyncRef0|HDSP_SelSyncRef2) 380 381 /* Card state flags */ 382 383 #define HDSP_InitializationComplete (1<<0) 384 #define HDSP_FirmwareLoaded (1<<1) 385 #define HDSP_FirmwareCached (1<<2) 386 387 /* FIFO wait times, defined in terms of 1/10ths of msecs */ 388 389 #define HDSP_LONG_WAIT 5000 390 #define HDSP_SHORT_WAIT 30 391 392 #define UNITY_GAIN 32768 393 #define MINUS_INFINITY_GAIN 0 394 395 /* the size of a substream (1 mono data stream) */ 396 397 #define HDSP_CHANNEL_BUFFER_SAMPLES (16*1024) 398 #define HDSP_CHANNEL_BUFFER_BYTES (4*HDSP_CHANNEL_BUFFER_SAMPLES) 399 400 /* the size of the area we need to allocate for DMA transfers. the 401 size is the same regardless of the number of channels - the 402 Multiface still uses the same memory area. 403 404 Note that we allocate 1 more channel than is apparently needed 405 because the h/w seems to write 1 byte beyond the end of the last 406 page. Sigh. 407 */ 408 409 #define HDSP_DMA_AREA_BYTES ((HDSP_MAX_CHANNELS+1) * HDSP_CHANNEL_BUFFER_BYTES) 410 #define HDSP_DMA_AREA_KILOBYTES (HDSP_DMA_AREA_BYTES/1024) 411 412 #define HDSP_FIRMWARE_SIZE (24413 * 4) 413 414 struct hdsp_9632_meters { 415 u32 input_peak[16]; 416 u32 playback_peak[16]; 417 u32 output_peak[16]; 418 u32 xxx_peak[16]; 419 u32 padding[64]; 420 u32 input_rms_low[16]; 421 u32 playback_rms_low[16]; 422 u32 output_rms_low[16]; 423 u32 xxx_rms_low[16]; 424 u32 input_rms_high[16]; 425 u32 playback_rms_high[16]; 426 u32 output_rms_high[16]; 427 u32 xxx_rms_high[16]; 428 }; 429 430 struct hdsp_midi { 431 struct hdsp *hdsp; 432 int id; 433 struct snd_rawmidi *rmidi; 434 struct snd_rawmidi_substream *input; 435 struct snd_rawmidi_substream *output; 436 char istimer; /* timer in use */ 437 struct timer_list timer; 438 spinlock_t lock; 439 int pending; 440 }; 441 442 struct hdsp { 443 spinlock_t lock; 444 struct snd_pcm_substream *capture_substream; 445 struct snd_pcm_substream *playback_substream; 446 struct hdsp_midi midi[2]; 447 struct work_struct midi_work; 448 int use_midi_work; 449 int precise_ptr; 450 u32 control_register; /* cached value */ 451 u32 control2_register; /* cached value */ 452 u32 creg_spdif; 453 u32 creg_spdif_stream; 454 int clock_source_locked; 455 char *card_name; /* digiface/multiface/rpm */ 456 enum HDSP_IO_Type io_type; /* ditto, but for code use */ 457 unsigned short firmware_rev; 458 unsigned short state; /* stores state bits */ 459 const struct firmware *firmware; 460 u32 *fw_uploaded; 461 size_t period_bytes; /* guess what this is */ 462 unsigned char max_channels; 463 unsigned char qs_in_channels; /* quad speed mode for H9632 */ 464 unsigned char ds_in_channels; 465 unsigned char ss_in_channels; /* different for multiface/digiface */ 466 unsigned char qs_out_channels; 467 unsigned char ds_out_channels; 468 unsigned char ss_out_channels; 469 u32 io_loopback; /* output loopback channel states*/ 470 471 struct snd_dma_buffer capture_dma_buf; 472 struct snd_dma_buffer playback_dma_buf; 473 unsigned char *capture_buffer; /* suitably aligned address */ 474 unsigned char *playback_buffer; /* suitably aligned address */ 475 476 pid_t capture_pid; 477 pid_t playback_pid; 478 int running; 479 int system_sample_rate; 480 const char *channel_map; 481 int dev; 482 int irq; 483 unsigned long port; 484 void __iomem *iobase; 485 struct snd_card *card; 486 struct snd_pcm *pcm; 487 struct snd_hwdep *hwdep; 488 struct pci_dev *pci; 489 struct snd_kcontrol *spdif_ctl; 490 unsigned short mixer_matrix[HDSP_MATRIX_MIXER_SIZE]; 491 unsigned int dds_value; /* last value written to freq register */ 492 }; 493 494 /* These tables map the ALSA channels 1..N to the channels that we 495 need to use in order to find the relevant channel buffer. RME 496 refer to this kind of mapping as between "the ADAT channel and 497 the DMA channel." We index it using the logical audio channel, 498 and the value is the DMA channel (i.e. channel buffer number) 499 where the data for that channel can be read/written from/to. 500 */ 501 502 static const char channel_map_df_ss[HDSP_MAX_CHANNELS] = { 503 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 504 18, 19, 20, 21, 22, 23, 24, 25 505 }; 506 507 static const char channel_map_mf_ss[HDSP_MAX_CHANNELS] = { /* Multiface */ 508 /* Analog */ 509 0, 1, 2, 3, 4, 5, 6, 7, 510 /* ADAT 2 */ 511 16, 17, 18, 19, 20, 21, 22, 23, 512 /* SPDIF */ 513 24, 25, 514 -1, -1, -1, -1, -1, -1, -1, -1 515 }; 516 517 static const char channel_map_ds[HDSP_MAX_CHANNELS] = { 518 /* ADAT channels are remapped */ 519 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 520 /* channels 12 and 13 are S/PDIF */ 521 24, 25, 522 /* others don't exist */ 523 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 524 }; 525 526 static const char channel_map_H9632_ss[HDSP_MAX_CHANNELS] = { 527 /* ADAT channels */ 528 0, 1, 2, 3, 4, 5, 6, 7, 529 /* SPDIF */ 530 8, 9, 531 /* Analog */ 532 10, 11, 533 /* AO4S-192 and AI4S-192 extension boards */ 534 12, 13, 14, 15, 535 /* others don't exist */ 536 -1, -1, -1, -1, -1, -1, -1, -1, 537 -1, -1 538 }; 539 540 static const char channel_map_H9632_ds[HDSP_MAX_CHANNELS] = { 541 /* ADAT */ 542 1, 3, 5, 7, 543 /* SPDIF */ 544 8, 9, 545 /* Analog */ 546 10, 11, 547 /* AO4S-192 and AI4S-192 extension boards */ 548 12, 13, 14, 15, 549 /* others don't exist */ 550 -1, -1, -1, -1, -1, -1, -1, -1, 551 -1, -1, -1, -1, -1, -1 552 }; 553 554 static const char channel_map_H9632_qs[HDSP_MAX_CHANNELS] = { 555 /* ADAT is disabled in this mode */ 556 /* SPDIF */ 557 8, 9, 558 /* Analog */ 559 10, 11, 560 /* AO4S-192 and AI4S-192 extension boards */ 561 12, 13, 14, 15, 562 /* others don't exist */ 563 -1, -1, -1, -1, -1, -1, -1, -1, 564 -1, -1, -1, -1, -1, -1, -1, -1, 565 -1, -1 566 }; 567 568 static int snd_hammerfall_get_buffer(struct pci_dev *pci, struct snd_dma_buffer *dmab, size_t size) 569 { 570 return snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &pci->dev, size, dmab); 571 } 572 573 static void snd_hammerfall_free_buffer(struct snd_dma_buffer *dmab, struct pci_dev *pci) 574 { 575 if (dmab->area) 576 snd_dma_free_pages(dmab); 577 } 578 579 580 static const struct pci_device_id snd_hdsp_ids[] = { 581 { 582 .vendor = PCI_VENDOR_ID_XILINX, 583 .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP, 584 .subvendor = PCI_ANY_ID, 585 .subdevice = PCI_ANY_ID, 586 }, /* RME Hammerfall-DSP */ 587 { 0, }, 588 }; 589 590 MODULE_DEVICE_TABLE(pci, snd_hdsp_ids); 591 592 /* prototypes */ 593 static int snd_hdsp_create_alsa_devices(struct snd_card *card, struct hdsp *hdsp); 594 static int snd_hdsp_create_pcm(struct snd_card *card, struct hdsp *hdsp); 595 static int snd_hdsp_enable_io (struct hdsp *hdsp); 596 static void snd_hdsp_initialize_midi_flush (struct hdsp *hdsp); 597 static void snd_hdsp_initialize_channels (struct hdsp *hdsp); 598 static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout); 599 static int hdsp_autosync_ref(struct hdsp *hdsp); 600 static int snd_hdsp_set_defaults(struct hdsp *hdsp); 601 static void snd_hdsp_9652_enable_mixer (struct hdsp *hdsp); 602 603 static int hdsp_playback_to_output_key (struct hdsp *hdsp, int in, int out) 604 { 605 switch (hdsp->io_type) { 606 case Multiface: 607 case Digiface: 608 case RPM: 609 default: 610 if (hdsp->firmware_rev == 0xa) 611 return (64 * out) + (32 + (in)); 612 else 613 return (52 * out) + (26 + (in)); 614 case H9632: 615 return (32 * out) + (16 + (in)); 616 case H9652: 617 return (52 * out) + (26 + (in)); 618 } 619 } 620 621 static int hdsp_input_to_output_key (struct hdsp *hdsp, int in, int out) 622 { 623 switch (hdsp->io_type) { 624 case Multiface: 625 case Digiface: 626 case RPM: 627 default: 628 if (hdsp->firmware_rev == 0xa) 629 return (64 * out) + in; 630 else 631 return (52 * out) + in; 632 case H9632: 633 return (32 * out) + in; 634 case H9652: 635 return (52 * out) + in; 636 } 637 } 638 639 static void hdsp_write(struct hdsp *hdsp, int reg, int val) 640 { 641 writel(val, hdsp->iobase + reg); 642 } 643 644 static unsigned int hdsp_read(struct hdsp *hdsp, int reg) 645 { 646 return readl (hdsp->iobase + reg); 647 } 648 649 static int hdsp_check_for_iobox (struct hdsp *hdsp) 650 { 651 int i; 652 653 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return 0; 654 for (i = 0; i < 500; i++) { 655 if (0 == (hdsp_read(hdsp, HDSP_statusRegister) & 656 HDSP_ConfigError)) { 657 if (i) { 658 dev_dbg(hdsp->card->dev, 659 "IO box found after %d ms\n", 660 (20 * i)); 661 } 662 return 0; 663 } 664 msleep(20); 665 } 666 dev_err(hdsp->card->dev, "no IO box connected!\n"); 667 hdsp->state &= ~HDSP_FirmwareLoaded; 668 return -EIO; 669 } 670 671 static int hdsp_wait_for_iobox(struct hdsp *hdsp, unsigned int loops, 672 unsigned int delay) 673 { 674 unsigned int i; 675 676 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) 677 return 0; 678 679 for (i = 0; i != loops; ++i) { 680 if (hdsp_read(hdsp, HDSP_statusRegister) & HDSP_ConfigError) 681 msleep(delay); 682 else { 683 dev_dbg(hdsp->card->dev, "iobox found after %ums!\n", 684 i * delay); 685 return 0; 686 } 687 } 688 689 dev_info(hdsp->card->dev, "no IO box connected!\n"); 690 hdsp->state &= ~HDSP_FirmwareLoaded; 691 return -EIO; 692 } 693 694 static int snd_hdsp_load_firmware_from_cache(struct hdsp *hdsp) { 695 696 int i; 697 unsigned long flags; 698 const u32 *cache; 699 700 if (hdsp->fw_uploaded) 701 cache = hdsp->fw_uploaded; 702 else { 703 if (!hdsp->firmware) 704 return -ENODEV; 705 cache = (u32 *)hdsp->firmware->data; 706 if (!cache) 707 return -ENODEV; 708 } 709 710 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) { 711 712 dev_info(hdsp->card->dev, "loading firmware\n"); 713 714 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_PROGRAM); 715 hdsp_write (hdsp, HDSP_fifoData, 0); 716 717 if (hdsp_fifo_wait (hdsp, 0, HDSP_LONG_WAIT)) { 718 dev_info(hdsp->card->dev, 719 "timeout waiting for download preparation\n"); 720 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200); 721 return -EIO; 722 } 723 724 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD); 725 726 for (i = 0; i < HDSP_FIRMWARE_SIZE / 4; ++i) { 727 hdsp_write(hdsp, HDSP_fifoData, cache[i]); 728 if (hdsp_fifo_wait (hdsp, 127, HDSP_LONG_WAIT)) { 729 dev_info(hdsp->card->dev, 730 "timeout during firmware loading\n"); 731 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200); 732 return -EIO; 733 } 734 } 735 736 hdsp_fifo_wait(hdsp, 3, HDSP_LONG_WAIT); 737 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200); 738 739 ssleep(3); 740 #ifdef SNDRV_BIG_ENDIAN 741 hdsp->control2_register = HDSP_BIGENDIAN_MODE; 742 #else 743 hdsp->control2_register = 0; 744 #endif 745 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register); 746 dev_info(hdsp->card->dev, "finished firmware loading\n"); 747 748 } 749 if (hdsp->state & HDSP_InitializationComplete) { 750 dev_info(hdsp->card->dev, 751 "firmware loaded from cache, restoring defaults\n"); 752 spin_lock_irqsave(&hdsp->lock, flags); 753 snd_hdsp_set_defaults(hdsp); 754 spin_unlock_irqrestore(&hdsp->lock, flags); 755 } 756 757 hdsp->state |= HDSP_FirmwareLoaded; 758 759 return 0; 760 } 761 762 static int hdsp_get_iobox_version (struct hdsp *hdsp) 763 { 764 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) { 765 766 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD); 767 hdsp_write(hdsp, HDSP_fifoData, 0); 768 769 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0) { 770 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300); 771 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD); 772 } 773 774 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200 | HDSP_PROGRAM); 775 hdsp_write (hdsp, HDSP_fifoData, 0); 776 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0) 777 goto set_multi; 778 779 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD); 780 hdsp_write(hdsp, HDSP_fifoData, 0); 781 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) == 0) { 782 hdsp->io_type = Digiface; 783 dev_info(hdsp->card->dev, "Digiface found\n"); 784 return 0; 785 } 786 787 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300); 788 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD); 789 hdsp_write(hdsp, HDSP_fifoData, 0); 790 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) == 0) 791 goto set_multi; 792 793 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300); 794 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD); 795 hdsp_write(hdsp, HDSP_fifoData, 0); 796 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0) 797 goto set_multi; 798 799 hdsp->io_type = RPM; 800 dev_info(hdsp->card->dev, "RPM found\n"); 801 return 0; 802 } else { 803 /* firmware was already loaded, get iobox type */ 804 if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version2) 805 hdsp->io_type = RPM; 806 else if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1) 807 hdsp->io_type = Multiface; 808 else 809 hdsp->io_type = Digiface; 810 } 811 return 0; 812 813 set_multi: 814 hdsp->io_type = Multiface; 815 dev_info(hdsp->card->dev, "Multiface found\n"); 816 return 0; 817 } 818 819 820 static int hdsp_request_fw_loader(struct hdsp *hdsp); 821 822 static int hdsp_check_for_firmware (struct hdsp *hdsp, int load_on_demand) 823 { 824 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) 825 return 0; 826 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) { 827 hdsp->state &= ~HDSP_FirmwareLoaded; 828 if (! load_on_demand) 829 return -EIO; 830 dev_err(hdsp->card->dev, "firmware not present.\n"); 831 /* try to load firmware */ 832 if (! (hdsp->state & HDSP_FirmwareCached)) { 833 if (! hdsp_request_fw_loader(hdsp)) 834 return 0; 835 dev_err(hdsp->card->dev, 836 "No firmware loaded nor cached, please upload firmware.\n"); 837 return -EIO; 838 } 839 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) { 840 dev_err(hdsp->card->dev, 841 "Firmware loading from cache failed, please upload manually.\n"); 842 return -EIO; 843 } 844 } 845 return 0; 846 } 847 848 849 static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout) 850 { 851 int i; 852 853 /* the fifoStatus registers reports on how many words 854 are available in the command FIFO. 855 */ 856 857 for (i = 0; i < timeout; i++) { 858 859 if ((int)(hdsp_read (hdsp, HDSP_fifoStatus) & 0xff) <= count) 860 return 0; 861 862 /* not very friendly, but we only do this during a firmware 863 load and changing the mixer, so we just put up with it. 864 */ 865 866 udelay (100); 867 } 868 869 dev_warn(hdsp->card->dev, 870 "wait for FIFO status <= %d failed after %d iterations\n", 871 count, timeout); 872 return -1; 873 } 874 875 static int hdsp_read_gain (struct hdsp *hdsp, unsigned int addr) 876 { 877 if (addr >= HDSP_MATRIX_MIXER_SIZE) 878 return 0; 879 880 return hdsp->mixer_matrix[addr]; 881 } 882 883 static int hdsp_write_gain(struct hdsp *hdsp, unsigned int addr, unsigned short data) 884 { 885 unsigned int ad; 886 887 if (addr >= HDSP_MATRIX_MIXER_SIZE) 888 return -1; 889 890 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) { 891 892 /* from martin bjornsen: 893 894 "You can only write dwords to the 895 mixer memory which contain two 896 mixer values in the low and high 897 word. So if you want to change 898 value 0 you have to read value 1 899 from the cache and write both to 900 the first dword in the mixer 901 memory." 902 */ 903 904 if (hdsp->io_type == H9632 && addr >= 512) 905 return 0; 906 907 if (hdsp->io_type == H9652 && addr >= 1352) 908 return 0; 909 910 hdsp->mixer_matrix[addr] = data; 911 912 913 /* `addr' addresses a 16-bit wide address, but 914 the address space accessed via hdsp_write 915 uses byte offsets. put another way, addr 916 varies from 0 to 1351, but to access the 917 corresponding memory location, we need 918 to access 0 to 2703 ... 919 */ 920 ad = addr/2; 921 922 hdsp_write (hdsp, 4096 + (ad*4), 923 (hdsp->mixer_matrix[(addr&0x7fe)+1] << 16) + 924 hdsp->mixer_matrix[addr&0x7fe]); 925 926 return 0; 927 928 } else { 929 930 ad = (addr << 16) + data; 931 932 if (hdsp_fifo_wait(hdsp, 127, HDSP_LONG_WAIT)) 933 return -1; 934 935 hdsp_write (hdsp, HDSP_fifoData, ad); 936 hdsp->mixer_matrix[addr] = data; 937 938 } 939 940 return 0; 941 } 942 943 static int snd_hdsp_use_is_exclusive(struct hdsp *hdsp) 944 { 945 unsigned long flags; 946 int ret = 1; 947 948 spin_lock_irqsave(&hdsp->lock, flags); 949 if ((hdsp->playback_pid != hdsp->capture_pid) && 950 (hdsp->playback_pid >= 0) && (hdsp->capture_pid >= 0)) 951 ret = 0; 952 spin_unlock_irqrestore(&hdsp->lock, flags); 953 return ret; 954 } 955 956 static int hdsp_spdif_sample_rate(struct hdsp *hdsp) 957 { 958 unsigned int status = hdsp_read(hdsp, HDSP_statusRegister); 959 unsigned int rate_bits = (status & HDSP_spdifFrequencyMask); 960 961 /* For the 9632, the mask is different */ 962 if (hdsp->io_type == H9632) 963 rate_bits = (status & HDSP_spdifFrequencyMask_9632); 964 965 if (status & HDSP_SPDIFErrorFlag) 966 return 0; 967 968 switch (rate_bits) { 969 case HDSP_spdifFrequency32KHz: return 32000; 970 case HDSP_spdifFrequency44_1KHz: return 44100; 971 case HDSP_spdifFrequency48KHz: return 48000; 972 case HDSP_spdifFrequency64KHz: return 64000; 973 case HDSP_spdifFrequency88_2KHz: return 88200; 974 case HDSP_spdifFrequency96KHz: return 96000; 975 case HDSP_spdifFrequency128KHz: 976 if (hdsp->io_type == H9632) return 128000; 977 break; 978 case HDSP_spdifFrequency176_4KHz: 979 if (hdsp->io_type == H9632) return 176400; 980 break; 981 case HDSP_spdifFrequency192KHz: 982 if (hdsp->io_type == H9632) return 192000; 983 break; 984 default: 985 break; 986 } 987 dev_warn(hdsp->card->dev, 988 "unknown spdif frequency status; bits = 0x%x, status = 0x%x\n", 989 rate_bits, status); 990 return 0; 991 } 992 993 static int hdsp_external_sample_rate(struct hdsp *hdsp) 994 { 995 unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register); 996 unsigned int rate_bits = status2 & HDSP_systemFrequencyMask; 997 998 /* For the 9632 card, there seems to be no bit for indicating external 999 * sample rate greater than 96kHz. The card reports the corresponding 1000 * single speed. So the best means seems to get spdif rate when 1001 * autosync reference is spdif */ 1002 if (hdsp->io_type == H9632 && 1003 hdsp_autosync_ref(hdsp) == HDSP_AUTOSYNC_FROM_SPDIF) 1004 return hdsp_spdif_sample_rate(hdsp); 1005 1006 switch (rate_bits) { 1007 case HDSP_systemFrequency32: return 32000; 1008 case HDSP_systemFrequency44_1: return 44100; 1009 case HDSP_systemFrequency48: return 48000; 1010 case HDSP_systemFrequency64: return 64000; 1011 case HDSP_systemFrequency88_2: return 88200; 1012 case HDSP_systemFrequency96: return 96000; 1013 default: 1014 return 0; 1015 } 1016 } 1017 1018 static void hdsp_compute_period_size(struct hdsp *hdsp) 1019 { 1020 hdsp->period_bytes = 1 << ((hdsp_decode_latency(hdsp->control_register) + 8)); 1021 } 1022 1023 static snd_pcm_uframes_t hdsp_hw_pointer(struct hdsp *hdsp) 1024 { 1025 int position; 1026 1027 position = hdsp_read(hdsp, HDSP_statusRegister); 1028 1029 if (!hdsp->precise_ptr) 1030 return (position & HDSP_BufferID) ? (hdsp->period_bytes / 4) : 0; 1031 1032 position &= HDSP_BufferPositionMask; 1033 position /= 4; 1034 position &= (hdsp->period_bytes/2) - 1; 1035 return position; 1036 } 1037 1038 static void hdsp_reset_hw_pointer(struct hdsp *hdsp) 1039 { 1040 hdsp_write (hdsp, HDSP_resetPointer, 0); 1041 if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152) 1042 /* HDSP_resetPointer = HDSP_freqReg, which is strange and 1043 * requires (?) to write again DDS value after a reset pointer 1044 * (at least, it works like this) */ 1045 hdsp_write (hdsp, HDSP_freqReg, hdsp->dds_value); 1046 } 1047 1048 static void hdsp_start_audio(struct hdsp *s) 1049 { 1050 s->control_register |= (HDSP_AudioInterruptEnable | HDSP_Start); 1051 hdsp_write(s, HDSP_controlRegister, s->control_register); 1052 } 1053 1054 static void hdsp_stop_audio(struct hdsp *s) 1055 { 1056 s->control_register &= ~(HDSP_Start | HDSP_AudioInterruptEnable); 1057 hdsp_write(s, HDSP_controlRegister, s->control_register); 1058 } 1059 1060 static void hdsp_silence_playback(struct hdsp *hdsp) 1061 { 1062 memset(hdsp->playback_buffer, 0, HDSP_DMA_AREA_BYTES); 1063 } 1064 1065 static int hdsp_set_interrupt_interval(struct hdsp *s, unsigned int frames) 1066 { 1067 int n; 1068 1069 spin_lock_irq(&s->lock); 1070 1071 frames >>= 7; 1072 n = 0; 1073 while (frames) { 1074 n++; 1075 frames >>= 1; 1076 } 1077 1078 s->control_register &= ~HDSP_LatencyMask; 1079 s->control_register |= hdsp_encode_latency(n); 1080 1081 hdsp_write(s, HDSP_controlRegister, s->control_register); 1082 1083 hdsp_compute_period_size(s); 1084 1085 spin_unlock_irq(&s->lock); 1086 1087 return 0; 1088 } 1089 1090 static void hdsp_set_dds_value(struct hdsp *hdsp, int rate) 1091 { 1092 u64 n; 1093 1094 if (rate >= 112000) 1095 rate /= 4; 1096 else if (rate >= 56000) 1097 rate /= 2; 1098 1099 n = DDS_NUMERATOR; 1100 n = div_u64(n, rate); 1101 /* n should be less than 2^32 for being written to FREQ register */ 1102 snd_BUG_ON(n >> 32); 1103 /* HDSP_freqReg and HDSP_resetPointer are the same, so keep the DDS 1104 value to write it after a reset */ 1105 hdsp->dds_value = n; 1106 hdsp_write(hdsp, HDSP_freqReg, hdsp->dds_value); 1107 } 1108 1109 static int hdsp_set_rate(struct hdsp *hdsp, int rate, int called_internally) 1110 { 1111 int reject_if_open = 0; 1112 int current_rate; 1113 int rate_bits; 1114 1115 /* ASSUMPTION: hdsp->lock is either held, or 1116 there is no need for it (e.g. during module 1117 initialization). 1118 */ 1119 1120 if (!(hdsp->control_register & HDSP_ClockModeMaster)) { 1121 if (called_internally) { 1122 /* request from ctl or card initialization */ 1123 dev_err(hdsp->card->dev, 1124 "device is not running as a clock master: cannot set sample rate.\n"); 1125 return -1; 1126 } else { 1127 /* hw_param request while in AutoSync mode */ 1128 int external_freq = hdsp_external_sample_rate(hdsp); 1129 int spdif_freq = hdsp_spdif_sample_rate(hdsp); 1130 1131 if ((spdif_freq == external_freq*2) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1)) 1132 dev_info(hdsp->card->dev, 1133 "Detected ADAT in double speed mode\n"); 1134 else if (hdsp->io_type == H9632 && (spdif_freq == external_freq*4) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1)) 1135 dev_info(hdsp->card->dev, 1136 "Detected ADAT in quad speed mode\n"); 1137 else if (rate != external_freq) { 1138 dev_info(hdsp->card->dev, 1139 "No AutoSync source for requested rate\n"); 1140 return -1; 1141 } 1142 } 1143 } 1144 1145 current_rate = hdsp->system_sample_rate; 1146 1147 /* Changing from a "single speed" to a "double speed" rate is 1148 not allowed if any substreams are open. This is because 1149 such a change causes a shift in the location of 1150 the DMA buffers and a reduction in the number of available 1151 buffers. 1152 1153 Note that a similar but essentially insoluble problem 1154 exists for externally-driven rate changes. All we can do 1155 is to flag rate changes in the read/write routines. */ 1156 1157 if (rate > 96000 && hdsp->io_type != H9632) 1158 return -EINVAL; 1159 1160 switch (rate) { 1161 case 32000: 1162 if (current_rate > 48000) 1163 reject_if_open = 1; 1164 rate_bits = HDSP_Frequency32KHz; 1165 break; 1166 case 44100: 1167 if (current_rate > 48000) 1168 reject_if_open = 1; 1169 rate_bits = HDSP_Frequency44_1KHz; 1170 break; 1171 case 48000: 1172 if (current_rate > 48000) 1173 reject_if_open = 1; 1174 rate_bits = HDSP_Frequency48KHz; 1175 break; 1176 case 64000: 1177 if (current_rate <= 48000 || current_rate > 96000) 1178 reject_if_open = 1; 1179 rate_bits = HDSP_Frequency64KHz; 1180 break; 1181 case 88200: 1182 if (current_rate <= 48000 || current_rate > 96000) 1183 reject_if_open = 1; 1184 rate_bits = HDSP_Frequency88_2KHz; 1185 break; 1186 case 96000: 1187 if (current_rate <= 48000 || current_rate > 96000) 1188 reject_if_open = 1; 1189 rate_bits = HDSP_Frequency96KHz; 1190 break; 1191 case 128000: 1192 if (current_rate < 128000) 1193 reject_if_open = 1; 1194 rate_bits = HDSP_Frequency128KHz; 1195 break; 1196 case 176400: 1197 if (current_rate < 128000) 1198 reject_if_open = 1; 1199 rate_bits = HDSP_Frequency176_4KHz; 1200 break; 1201 case 192000: 1202 if (current_rate < 128000) 1203 reject_if_open = 1; 1204 rate_bits = HDSP_Frequency192KHz; 1205 break; 1206 default: 1207 return -EINVAL; 1208 } 1209 1210 if (reject_if_open && (hdsp->capture_pid >= 0 || hdsp->playback_pid >= 0)) { 1211 dev_warn(hdsp->card->dev, 1212 "cannot change speed mode (capture PID = %d, playback PID = %d)\n", 1213 hdsp->capture_pid, 1214 hdsp->playback_pid); 1215 return -EBUSY; 1216 } 1217 1218 hdsp->control_register &= ~HDSP_FrequencyMask; 1219 hdsp->control_register |= rate_bits; 1220 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 1221 1222 /* For HDSP9632 rev 152, need to set DDS value in FREQ register */ 1223 if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152) 1224 hdsp_set_dds_value(hdsp, rate); 1225 1226 if (rate >= 128000) { 1227 hdsp->channel_map = channel_map_H9632_qs; 1228 } else if (rate > 48000) { 1229 if (hdsp->io_type == H9632) 1230 hdsp->channel_map = channel_map_H9632_ds; 1231 else 1232 hdsp->channel_map = channel_map_ds; 1233 } else { 1234 switch (hdsp->io_type) { 1235 case RPM: 1236 case Multiface: 1237 hdsp->channel_map = channel_map_mf_ss; 1238 break; 1239 case Digiface: 1240 case H9652: 1241 hdsp->channel_map = channel_map_df_ss; 1242 break; 1243 case H9632: 1244 hdsp->channel_map = channel_map_H9632_ss; 1245 break; 1246 default: 1247 /* should never happen */ 1248 break; 1249 } 1250 } 1251 1252 hdsp->system_sample_rate = rate; 1253 1254 return 0; 1255 } 1256 1257 /*---------------------------------------------------------------------------- 1258 MIDI 1259 ----------------------------------------------------------------------------*/ 1260 1261 static unsigned char snd_hdsp_midi_read_byte (struct hdsp *hdsp, int id) 1262 { 1263 /* the hardware already does the relevant bit-mask with 0xff */ 1264 if (id) 1265 return hdsp_read(hdsp, HDSP_midiDataIn1); 1266 else 1267 return hdsp_read(hdsp, HDSP_midiDataIn0); 1268 } 1269 1270 static void snd_hdsp_midi_write_byte (struct hdsp *hdsp, int id, int val) 1271 { 1272 /* the hardware already does the relevant bit-mask with 0xff */ 1273 if (id) 1274 hdsp_write(hdsp, HDSP_midiDataOut1, val); 1275 else 1276 hdsp_write(hdsp, HDSP_midiDataOut0, val); 1277 } 1278 1279 static int snd_hdsp_midi_input_available (struct hdsp *hdsp, int id) 1280 { 1281 if (id) 1282 return (hdsp_read(hdsp, HDSP_midiStatusIn1) & 0xff); 1283 else 1284 return (hdsp_read(hdsp, HDSP_midiStatusIn0) & 0xff); 1285 } 1286 1287 static int snd_hdsp_midi_output_possible (struct hdsp *hdsp, int id) 1288 { 1289 int fifo_bytes_used; 1290 1291 if (id) 1292 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut1) & 0xff; 1293 else 1294 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut0) & 0xff; 1295 1296 if (fifo_bytes_used < 128) 1297 return 128 - fifo_bytes_used; 1298 else 1299 return 0; 1300 } 1301 1302 static void snd_hdsp_flush_midi_input (struct hdsp *hdsp, int id) 1303 { 1304 while (snd_hdsp_midi_input_available (hdsp, id)) 1305 snd_hdsp_midi_read_byte (hdsp, id); 1306 } 1307 1308 static int snd_hdsp_midi_output_write (struct hdsp_midi *hmidi) 1309 { 1310 unsigned long flags; 1311 int n_pending; 1312 int to_write; 1313 int i; 1314 unsigned char buf[128]; 1315 1316 /* Output is not interrupt driven */ 1317 1318 spin_lock_irqsave (&hmidi->lock, flags); 1319 if (hmidi->output) { 1320 if (!snd_rawmidi_transmit_empty (hmidi->output)) { 1321 n_pending = snd_hdsp_midi_output_possible(hmidi->hdsp, hmidi->id); 1322 if (n_pending > 0) { 1323 if (n_pending > (int)sizeof (buf)) 1324 n_pending = sizeof (buf); 1325 1326 to_write = snd_rawmidi_transmit(hmidi->output, buf, n_pending); 1327 if (to_write > 0) { 1328 for (i = 0; i < to_write; ++i) 1329 snd_hdsp_midi_write_byte (hmidi->hdsp, hmidi->id, buf[i]); 1330 } 1331 } 1332 } 1333 } 1334 spin_unlock_irqrestore (&hmidi->lock, flags); 1335 return 0; 1336 } 1337 1338 static int snd_hdsp_midi_input_read (struct hdsp_midi *hmidi) 1339 { 1340 unsigned char buf[128]; /* this buffer is designed to match the MIDI input FIFO size */ 1341 unsigned long flags; 1342 int n_pending; 1343 int i; 1344 1345 spin_lock_irqsave (&hmidi->lock, flags); 1346 n_pending = snd_hdsp_midi_input_available(hmidi->hdsp, hmidi->id); 1347 if (n_pending > 0) { 1348 if (hmidi->input) { 1349 if (n_pending > (int)sizeof (buf)) 1350 n_pending = sizeof (buf); 1351 for (i = 0; i < n_pending; ++i) 1352 buf[i] = snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id); 1353 if (n_pending) 1354 snd_rawmidi_receive (hmidi->input, buf, n_pending); 1355 } else { 1356 /* flush the MIDI input FIFO */ 1357 while (--n_pending) 1358 snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id); 1359 } 1360 } 1361 hmidi->pending = 0; 1362 if (hmidi->id) 1363 hmidi->hdsp->control_register |= HDSP_Midi1InterruptEnable; 1364 else 1365 hmidi->hdsp->control_register |= HDSP_Midi0InterruptEnable; 1366 hdsp_write(hmidi->hdsp, HDSP_controlRegister, hmidi->hdsp->control_register); 1367 spin_unlock_irqrestore (&hmidi->lock, flags); 1368 return snd_hdsp_midi_output_write (hmidi); 1369 } 1370 1371 static void snd_hdsp_midi_input_trigger(struct snd_rawmidi_substream *substream, int up) 1372 { 1373 struct hdsp *hdsp; 1374 struct hdsp_midi *hmidi; 1375 unsigned long flags; 1376 u32 ie; 1377 1378 hmidi = (struct hdsp_midi *) substream->rmidi->private_data; 1379 hdsp = hmidi->hdsp; 1380 ie = hmidi->id ? HDSP_Midi1InterruptEnable : HDSP_Midi0InterruptEnable; 1381 spin_lock_irqsave (&hdsp->lock, flags); 1382 if (up) { 1383 if (!(hdsp->control_register & ie)) { 1384 snd_hdsp_flush_midi_input (hdsp, hmidi->id); 1385 hdsp->control_register |= ie; 1386 } 1387 } else { 1388 hdsp->control_register &= ~ie; 1389 } 1390 1391 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 1392 spin_unlock_irqrestore (&hdsp->lock, flags); 1393 } 1394 1395 static void snd_hdsp_midi_output_timer(struct timer_list *t) 1396 { 1397 struct hdsp_midi *hmidi = from_timer(hmidi, t, timer); 1398 unsigned long flags; 1399 1400 snd_hdsp_midi_output_write(hmidi); 1401 spin_lock_irqsave (&hmidi->lock, flags); 1402 1403 /* this does not bump hmidi->istimer, because the 1404 kernel automatically removed the timer when it 1405 expired, and we are now adding it back, thus 1406 leaving istimer wherever it was set before. 1407 */ 1408 1409 if (hmidi->istimer) 1410 mod_timer(&hmidi->timer, 1 + jiffies); 1411 1412 spin_unlock_irqrestore (&hmidi->lock, flags); 1413 } 1414 1415 static void snd_hdsp_midi_output_trigger(struct snd_rawmidi_substream *substream, int up) 1416 { 1417 struct hdsp_midi *hmidi; 1418 unsigned long flags; 1419 1420 hmidi = (struct hdsp_midi *) substream->rmidi->private_data; 1421 spin_lock_irqsave (&hmidi->lock, flags); 1422 if (up) { 1423 if (!hmidi->istimer) { 1424 timer_setup(&hmidi->timer, snd_hdsp_midi_output_timer, 1425 0); 1426 mod_timer(&hmidi->timer, 1 + jiffies); 1427 hmidi->istimer++; 1428 } 1429 } else { 1430 if (hmidi->istimer && --hmidi->istimer <= 0) 1431 del_timer (&hmidi->timer); 1432 } 1433 spin_unlock_irqrestore (&hmidi->lock, flags); 1434 if (up) 1435 snd_hdsp_midi_output_write(hmidi); 1436 } 1437 1438 static int snd_hdsp_midi_input_open(struct snd_rawmidi_substream *substream) 1439 { 1440 struct hdsp_midi *hmidi; 1441 1442 hmidi = (struct hdsp_midi *) substream->rmidi->private_data; 1443 spin_lock_irq (&hmidi->lock); 1444 snd_hdsp_flush_midi_input (hmidi->hdsp, hmidi->id); 1445 hmidi->input = substream; 1446 spin_unlock_irq (&hmidi->lock); 1447 1448 return 0; 1449 } 1450 1451 static int snd_hdsp_midi_output_open(struct snd_rawmidi_substream *substream) 1452 { 1453 struct hdsp_midi *hmidi; 1454 1455 hmidi = (struct hdsp_midi *) substream->rmidi->private_data; 1456 spin_lock_irq (&hmidi->lock); 1457 hmidi->output = substream; 1458 spin_unlock_irq (&hmidi->lock); 1459 1460 return 0; 1461 } 1462 1463 static int snd_hdsp_midi_input_close(struct snd_rawmidi_substream *substream) 1464 { 1465 struct hdsp_midi *hmidi; 1466 1467 snd_hdsp_midi_input_trigger (substream, 0); 1468 1469 hmidi = (struct hdsp_midi *) substream->rmidi->private_data; 1470 spin_lock_irq (&hmidi->lock); 1471 hmidi->input = NULL; 1472 spin_unlock_irq (&hmidi->lock); 1473 1474 return 0; 1475 } 1476 1477 static int snd_hdsp_midi_output_close(struct snd_rawmidi_substream *substream) 1478 { 1479 struct hdsp_midi *hmidi; 1480 1481 snd_hdsp_midi_output_trigger (substream, 0); 1482 1483 hmidi = (struct hdsp_midi *) substream->rmidi->private_data; 1484 spin_lock_irq (&hmidi->lock); 1485 hmidi->output = NULL; 1486 spin_unlock_irq (&hmidi->lock); 1487 1488 return 0; 1489 } 1490 1491 static const struct snd_rawmidi_ops snd_hdsp_midi_output = 1492 { 1493 .open = snd_hdsp_midi_output_open, 1494 .close = snd_hdsp_midi_output_close, 1495 .trigger = snd_hdsp_midi_output_trigger, 1496 }; 1497 1498 static const struct snd_rawmidi_ops snd_hdsp_midi_input = 1499 { 1500 .open = snd_hdsp_midi_input_open, 1501 .close = snd_hdsp_midi_input_close, 1502 .trigger = snd_hdsp_midi_input_trigger, 1503 }; 1504 1505 static int snd_hdsp_create_midi (struct snd_card *card, struct hdsp *hdsp, int id) 1506 { 1507 char buf[40]; 1508 1509 hdsp->midi[id].id = id; 1510 hdsp->midi[id].rmidi = NULL; 1511 hdsp->midi[id].input = NULL; 1512 hdsp->midi[id].output = NULL; 1513 hdsp->midi[id].hdsp = hdsp; 1514 hdsp->midi[id].istimer = 0; 1515 hdsp->midi[id].pending = 0; 1516 spin_lock_init (&hdsp->midi[id].lock); 1517 1518 snprintf(buf, sizeof(buf), "%s MIDI %d", card->shortname, id + 1); 1519 if (snd_rawmidi_new (card, buf, id, 1, 1, &hdsp->midi[id].rmidi) < 0) 1520 return -1; 1521 1522 sprintf(hdsp->midi[id].rmidi->name, "HDSP MIDI %d", id+1); 1523 hdsp->midi[id].rmidi->private_data = &hdsp->midi[id]; 1524 1525 snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_hdsp_midi_output); 1526 snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_hdsp_midi_input); 1527 1528 hdsp->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | 1529 SNDRV_RAWMIDI_INFO_INPUT | 1530 SNDRV_RAWMIDI_INFO_DUPLEX; 1531 1532 return 0; 1533 } 1534 1535 /*----------------------------------------------------------------------------- 1536 Control Interface 1537 ----------------------------------------------------------------------------*/ 1538 1539 static u32 snd_hdsp_convert_from_aes(struct snd_aes_iec958 *aes) 1540 { 1541 u32 val = 0; 1542 val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? HDSP_SPDIFProfessional : 0; 1543 val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? HDSP_SPDIFNonAudio : 0; 1544 if (val & HDSP_SPDIFProfessional) 1545 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0; 1546 else 1547 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0; 1548 return val; 1549 } 1550 1551 static void snd_hdsp_convert_to_aes(struct snd_aes_iec958 *aes, u32 val) 1552 { 1553 aes->status[0] = ((val & HDSP_SPDIFProfessional) ? IEC958_AES0_PROFESSIONAL : 0) | 1554 ((val & HDSP_SPDIFNonAudio) ? IEC958_AES0_NONAUDIO : 0); 1555 if (val & HDSP_SPDIFProfessional) 1556 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0; 1557 else 1558 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_CON_EMPHASIS_5015 : 0; 1559 } 1560 1561 static int snd_hdsp_control_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 1562 { 1563 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 1564 uinfo->count = 1; 1565 return 0; 1566 } 1567 1568 static int snd_hdsp_control_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1569 { 1570 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1571 1572 snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif); 1573 return 0; 1574 } 1575 1576 static int snd_hdsp_control_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1577 { 1578 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1579 int change; 1580 u32 val; 1581 1582 val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958); 1583 spin_lock_irq(&hdsp->lock); 1584 change = val != hdsp->creg_spdif; 1585 hdsp->creg_spdif = val; 1586 spin_unlock_irq(&hdsp->lock); 1587 return change; 1588 } 1589 1590 static int snd_hdsp_control_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 1591 { 1592 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 1593 uinfo->count = 1; 1594 return 0; 1595 } 1596 1597 static int snd_hdsp_control_spdif_stream_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1598 { 1599 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1600 1601 snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif_stream); 1602 return 0; 1603 } 1604 1605 static int snd_hdsp_control_spdif_stream_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1606 { 1607 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1608 int change; 1609 u32 val; 1610 1611 val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958); 1612 spin_lock_irq(&hdsp->lock); 1613 change = val != hdsp->creg_spdif_stream; 1614 hdsp->creg_spdif_stream = val; 1615 hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis); 1616 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= val); 1617 spin_unlock_irq(&hdsp->lock); 1618 return change; 1619 } 1620 1621 static int snd_hdsp_control_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 1622 { 1623 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 1624 uinfo->count = 1; 1625 return 0; 1626 } 1627 1628 static int snd_hdsp_control_spdif_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1629 { 1630 ucontrol->value.iec958.status[0] = kcontrol->private_value; 1631 return 0; 1632 } 1633 1634 #define HDSP_SPDIF_IN(xname, xindex) \ 1635 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 1636 .name = xname, \ 1637 .index = xindex, \ 1638 .info = snd_hdsp_info_spdif_in, \ 1639 .get = snd_hdsp_get_spdif_in, \ 1640 .put = snd_hdsp_put_spdif_in } 1641 1642 static unsigned int hdsp_spdif_in(struct hdsp *hdsp) 1643 { 1644 return hdsp_decode_spdif_in(hdsp->control_register & HDSP_SPDIFInputMask); 1645 } 1646 1647 static int hdsp_set_spdif_input(struct hdsp *hdsp, int in) 1648 { 1649 hdsp->control_register &= ~HDSP_SPDIFInputMask; 1650 hdsp->control_register |= hdsp_encode_spdif_in(in); 1651 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 1652 return 0; 1653 } 1654 1655 static int snd_hdsp_info_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 1656 { 1657 static const char * const texts[4] = { 1658 "Optical", "Coaxial", "Internal", "AES" 1659 }; 1660 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1661 1662 return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 4 : 3, 1663 texts); 1664 } 1665 1666 static int snd_hdsp_get_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1667 { 1668 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1669 1670 ucontrol->value.enumerated.item[0] = hdsp_spdif_in(hdsp); 1671 return 0; 1672 } 1673 1674 static int snd_hdsp_put_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1675 { 1676 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1677 int change; 1678 unsigned int val; 1679 1680 if (!snd_hdsp_use_is_exclusive(hdsp)) 1681 return -EBUSY; 1682 val = ucontrol->value.enumerated.item[0] % ((hdsp->io_type == H9632) ? 4 : 3); 1683 spin_lock_irq(&hdsp->lock); 1684 change = val != hdsp_spdif_in(hdsp); 1685 if (change) 1686 hdsp_set_spdif_input(hdsp, val); 1687 spin_unlock_irq(&hdsp->lock); 1688 return change; 1689 } 1690 1691 #define HDSP_TOGGLE_SETTING(xname, xindex) \ 1692 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 1693 .name = xname, \ 1694 .private_value = xindex, \ 1695 .info = snd_hdsp_info_toggle_setting, \ 1696 .get = snd_hdsp_get_toggle_setting, \ 1697 .put = snd_hdsp_put_toggle_setting \ 1698 } 1699 1700 static int hdsp_toggle_setting(struct hdsp *hdsp, u32 regmask) 1701 { 1702 return (hdsp->control_register & regmask) ? 1 : 0; 1703 } 1704 1705 static int hdsp_set_toggle_setting(struct hdsp *hdsp, u32 regmask, int out) 1706 { 1707 if (out) 1708 hdsp->control_register |= regmask; 1709 else 1710 hdsp->control_register &= ~regmask; 1711 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 1712 1713 return 0; 1714 } 1715 1716 #define snd_hdsp_info_toggle_setting snd_ctl_boolean_mono_info 1717 1718 static int snd_hdsp_get_toggle_setting(struct snd_kcontrol *kcontrol, 1719 struct snd_ctl_elem_value *ucontrol) 1720 { 1721 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1722 u32 regmask = kcontrol->private_value; 1723 1724 spin_lock_irq(&hdsp->lock); 1725 ucontrol->value.integer.value[0] = hdsp_toggle_setting(hdsp, regmask); 1726 spin_unlock_irq(&hdsp->lock); 1727 return 0; 1728 } 1729 1730 static int snd_hdsp_put_toggle_setting(struct snd_kcontrol *kcontrol, 1731 struct snd_ctl_elem_value *ucontrol) 1732 { 1733 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1734 u32 regmask = kcontrol->private_value; 1735 int change; 1736 unsigned int val; 1737 1738 if (!snd_hdsp_use_is_exclusive(hdsp)) 1739 return -EBUSY; 1740 val = ucontrol->value.integer.value[0] & 1; 1741 spin_lock_irq(&hdsp->lock); 1742 change = (int) val != hdsp_toggle_setting(hdsp, regmask); 1743 if (change) 1744 hdsp_set_toggle_setting(hdsp, regmask, val); 1745 spin_unlock_irq(&hdsp->lock); 1746 return change; 1747 } 1748 1749 #define HDSP_SPDIF_SAMPLE_RATE(xname, xindex) \ 1750 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 1751 .name = xname, \ 1752 .index = xindex, \ 1753 .access = SNDRV_CTL_ELEM_ACCESS_READ, \ 1754 .info = snd_hdsp_info_spdif_sample_rate, \ 1755 .get = snd_hdsp_get_spdif_sample_rate \ 1756 } 1757 1758 static int snd_hdsp_info_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 1759 { 1760 static const char * const texts[] = { 1761 "32000", "44100", "48000", "64000", "88200", "96000", 1762 "None", "128000", "176400", "192000" 1763 }; 1764 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1765 1766 return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 10 : 7, 1767 texts); 1768 } 1769 1770 static int snd_hdsp_get_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1771 { 1772 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1773 1774 switch (hdsp_spdif_sample_rate(hdsp)) { 1775 case 32000: 1776 ucontrol->value.enumerated.item[0] = 0; 1777 break; 1778 case 44100: 1779 ucontrol->value.enumerated.item[0] = 1; 1780 break; 1781 case 48000: 1782 ucontrol->value.enumerated.item[0] = 2; 1783 break; 1784 case 64000: 1785 ucontrol->value.enumerated.item[0] = 3; 1786 break; 1787 case 88200: 1788 ucontrol->value.enumerated.item[0] = 4; 1789 break; 1790 case 96000: 1791 ucontrol->value.enumerated.item[0] = 5; 1792 break; 1793 case 128000: 1794 ucontrol->value.enumerated.item[0] = 7; 1795 break; 1796 case 176400: 1797 ucontrol->value.enumerated.item[0] = 8; 1798 break; 1799 case 192000: 1800 ucontrol->value.enumerated.item[0] = 9; 1801 break; 1802 default: 1803 ucontrol->value.enumerated.item[0] = 6; 1804 } 1805 return 0; 1806 } 1807 1808 #define HDSP_SYSTEM_SAMPLE_RATE(xname, xindex) \ 1809 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 1810 .name = xname, \ 1811 .index = xindex, \ 1812 .access = SNDRV_CTL_ELEM_ACCESS_READ, \ 1813 .info = snd_hdsp_info_system_sample_rate, \ 1814 .get = snd_hdsp_get_system_sample_rate \ 1815 } 1816 1817 static int snd_hdsp_info_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 1818 { 1819 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 1820 uinfo->count = 1; 1821 return 0; 1822 } 1823 1824 static int snd_hdsp_get_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1825 { 1826 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1827 1828 ucontrol->value.enumerated.item[0] = hdsp->system_sample_rate; 1829 return 0; 1830 } 1831 1832 #define HDSP_AUTOSYNC_SAMPLE_RATE(xname, xindex) \ 1833 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 1834 .name = xname, \ 1835 .index = xindex, \ 1836 .access = SNDRV_CTL_ELEM_ACCESS_READ, \ 1837 .info = snd_hdsp_info_autosync_sample_rate, \ 1838 .get = snd_hdsp_get_autosync_sample_rate \ 1839 } 1840 1841 static int snd_hdsp_info_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 1842 { 1843 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1844 static const char * const texts[] = { 1845 "32000", "44100", "48000", "64000", "88200", "96000", 1846 "None", "128000", "176400", "192000" 1847 }; 1848 1849 return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 10 : 7, 1850 texts); 1851 } 1852 1853 static int snd_hdsp_get_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1854 { 1855 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1856 1857 switch (hdsp_external_sample_rate(hdsp)) { 1858 case 32000: 1859 ucontrol->value.enumerated.item[0] = 0; 1860 break; 1861 case 44100: 1862 ucontrol->value.enumerated.item[0] = 1; 1863 break; 1864 case 48000: 1865 ucontrol->value.enumerated.item[0] = 2; 1866 break; 1867 case 64000: 1868 ucontrol->value.enumerated.item[0] = 3; 1869 break; 1870 case 88200: 1871 ucontrol->value.enumerated.item[0] = 4; 1872 break; 1873 case 96000: 1874 ucontrol->value.enumerated.item[0] = 5; 1875 break; 1876 case 128000: 1877 ucontrol->value.enumerated.item[0] = 7; 1878 break; 1879 case 176400: 1880 ucontrol->value.enumerated.item[0] = 8; 1881 break; 1882 case 192000: 1883 ucontrol->value.enumerated.item[0] = 9; 1884 break; 1885 default: 1886 ucontrol->value.enumerated.item[0] = 6; 1887 } 1888 return 0; 1889 } 1890 1891 #define HDSP_SYSTEM_CLOCK_MODE(xname, xindex) \ 1892 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 1893 .name = xname, \ 1894 .index = xindex, \ 1895 .access = SNDRV_CTL_ELEM_ACCESS_READ, \ 1896 .info = snd_hdsp_info_system_clock_mode, \ 1897 .get = snd_hdsp_get_system_clock_mode \ 1898 } 1899 1900 static int hdsp_system_clock_mode(struct hdsp *hdsp) 1901 { 1902 if (hdsp->control_register & HDSP_ClockModeMaster) 1903 return 0; 1904 else if (hdsp_external_sample_rate(hdsp) != hdsp->system_sample_rate) 1905 return 0; 1906 return 1; 1907 } 1908 1909 static int snd_hdsp_info_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 1910 { 1911 static const char * const texts[] = {"Master", "Slave" }; 1912 1913 return snd_ctl_enum_info(uinfo, 1, 2, texts); 1914 } 1915 1916 static int snd_hdsp_get_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1917 { 1918 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1919 1920 ucontrol->value.enumerated.item[0] = hdsp_system_clock_mode(hdsp); 1921 return 0; 1922 } 1923 1924 #define HDSP_CLOCK_SOURCE(xname, xindex) \ 1925 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 1926 .name = xname, \ 1927 .index = xindex, \ 1928 .info = snd_hdsp_info_clock_source, \ 1929 .get = snd_hdsp_get_clock_source, \ 1930 .put = snd_hdsp_put_clock_source \ 1931 } 1932 1933 static int hdsp_clock_source(struct hdsp *hdsp) 1934 { 1935 if (hdsp->control_register & HDSP_ClockModeMaster) { 1936 switch (hdsp->system_sample_rate) { 1937 case 32000: 1938 return 1; 1939 case 44100: 1940 return 2; 1941 case 48000: 1942 return 3; 1943 case 64000: 1944 return 4; 1945 case 88200: 1946 return 5; 1947 case 96000: 1948 return 6; 1949 case 128000: 1950 return 7; 1951 case 176400: 1952 return 8; 1953 case 192000: 1954 return 9; 1955 default: 1956 return 3; 1957 } 1958 } else { 1959 return 0; 1960 } 1961 } 1962 1963 static int hdsp_set_clock_source(struct hdsp *hdsp, int mode) 1964 { 1965 int rate; 1966 switch (mode) { 1967 case HDSP_CLOCK_SOURCE_AUTOSYNC: 1968 if (hdsp_external_sample_rate(hdsp) != 0) { 1969 if (!hdsp_set_rate(hdsp, hdsp_external_sample_rate(hdsp), 1)) { 1970 hdsp->control_register &= ~HDSP_ClockModeMaster; 1971 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 1972 return 0; 1973 } 1974 } 1975 return -1; 1976 case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ: 1977 rate = 32000; 1978 break; 1979 case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ: 1980 rate = 44100; 1981 break; 1982 case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ: 1983 rate = 48000; 1984 break; 1985 case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ: 1986 rate = 64000; 1987 break; 1988 case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ: 1989 rate = 88200; 1990 break; 1991 case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ: 1992 rate = 96000; 1993 break; 1994 case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ: 1995 rate = 128000; 1996 break; 1997 case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ: 1998 rate = 176400; 1999 break; 2000 case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ: 2001 rate = 192000; 2002 break; 2003 default: 2004 rate = 48000; 2005 } 2006 hdsp->control_register |= HDSP_ClockModeMaster; 2007 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 2008 hdsp_set_rate(hdsp, rate, 1); 2009 return 0; 2010 } 2011 2012 static int snd_hdsp_info_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2013 { 2014 static const char * const texts[] = { 2015 "AutoSync", "Internal 32.0 kHz", "Internal 44.1 kHz", 2016 "Internal 48.0 kHz", "Internal 64.0 kHz", "Internal 88.2 kHz", 2017 "Internal 96.0 kHz", "Internal 128 kHz", "Internal 176.4 kHz", 2018 "Internal 192.0 KHz" 2019 }; 2020 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2021 2022 return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 10 : 7, 2023 texts); 2024 } 2025 2026 static int snd_hdsp_get_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2027 { 2028 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2029 2030 ucontrol->value.enumerated.item[0] = hdsp_clock_source(hdsp); 2031 return 0; 2032 } 2033 2034 static int snd_hdsp_put_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2035 { 2036 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2037 int change; 2038 int val; 2039 2040 if (!snd_hdsp_use_is_exclusive(hdsp)) 2041 return -EBUSY; 2042 val = ucontrol->value.enumerated.item[0]; 2043 if (val < 0) val = 0; 2044 if (hdsp->io_type == H9632) { 2045 if (val > 9) 2046 val = 9; 2047 } else { 2048 if (val > 6) 2049 val = 6; 2050 } 2051 spin_lock_irq(&hdsp->lock); 2052 if (val != hdsp_clock_source(hdsp)) 2053 change = (hdsp_set_clock_source(hdsp, val) == 0) ? 1 : 0; 2054 else 2055 change = 0; 2056 spin_unlock_irq(&hdsp->lock); 2057 return change; 2058 } 2059 2060 #define snd_hdsp_info_clock_source_lock snd_ctl_boolean_mono_info 2061 2062 static int snd_hdsp_get_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2063 { 2064 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2065 2066 ucontrol->value.integer.value[0] = hdsp->clock_source_locked; 2067 return 0; 2068 } 2069 2070 static int snd_hdsp_put_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2071 { 2072 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2073 int change; 2074 2075 change = (int)ucontrol->value.integer.value[0] != hdsp->clock_source_locked; 2076 if (change) 2077 hdsp->clock_source_locked = !!ucontrol->value.integer.value[0]; 2078 return change; 2079 } 2080 2081 #define HDSP_DA_GAIN(xname, xindex) \ 2082 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2083 .name = xname, \ 2084 .index = xindex, \ 2085 .info = snd_hdsp_info_da_gain, \ 2086 .get = snd_hdsp_get_da_gain, \ 2087 .put = snd_hdsp_put_da_gain \ 2088 } 2089 2090 static int hdsp_da_gain(struct hdsp *hdsp) 2091 { 2092 switch (hdsp->control_register & HDSP_DAGainMask) { 2093 case HDSP_DAGainHighGain: 2094 return 0; 2095 case HDSP_DAGainPlus4dBu: 2096 return 1; 2097 case HDSP_DAGainMinus10dBV: 2098 return 2; 2099 default: 2100 return 1; 2101 } 2102 } 2103 2104 static int hdsp_set_da_gain(struct hdsp *hdsp, int mode) 2105 { 2106 hdsp->control_register &= ~HDSP_DAGainMask; 2107 switch (mode) { 2108 case 0: 2109 hdsp->control_register |= HDSP_DAGainHighGain; 2110 break; 2111 case 1: 2112 hdsp->control_register |= HDSP_DAGainPlus4dBu; 2113 break; 2114 case 2: 2115 hdsp->control_register |= HDSP_DAGainMinus10dBV; 2116 break; 2117 default: 2118 return -1; 2119 2120 } 2121 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 2122 return 0; 2123 } 2124 2125 static int snd_hdsp_info_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2126 { 2127 static const char * const texts[] = {"Hi Gain", "+4 dBu", "-10 dbV"}; 2128 2129 return snd_ctl_enum_info(uinfo, 1, 3, texts); 2130 } 2131 2132 static int snd_hdsp_get_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2133 { 2134 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2135 2136 ucontrol->value.enumerated.item[0] = hdsp_da_gain(hdsp); 2137 return 0; 2138 } 2139 2140 static int snd_hdsp_put_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2141 { 2142 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2143 int change; 2144 int val; 2145 2146 if (!snd_hdsp_use_is_exclusive(hdsp)) 2147 return -EBUSY; 2148 val = ucontrol->value.enumerated.item[0]; 2149 if (val < 0) val = 0; 2150 if (val > 2) val = 2; 2151 spin_lock_irq(&hdsp->lock); 2152 if (val != hdsp_da_gain(hdsp)) 2153 change = (hdsp_set_da_gain(hdsp, val) == 0) ? 1 : 0; 2154 else 2155 change = 0; 2156 spin_unlock_irq(&hdsp->lock); 2157 return change; 2158 } 2159 2160 #define HDSP_AD_GAIN(xname, xindex) \ 2161 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2162 .name = xname, \ 2163 .index = xindex, \ 2164 .info = snd_hdsp_info_ad_gain, \ 2165 .get = snd_hdsp_get_ad_gain, \ 2166 .put = snd_hdsp_put_ad_gain \ 2167 } 2168 2169 static int hdsp_ad_gain(struct hdsp *hdsp) 2170 { 2171 switch (hdsp->control_register & HDSP_ADGainMask) { 2172 case HDSP_ADGainMinus10dBV: 2173 return 0; 2174 case HDSP_ADGainPlus4dBu: 2175 return 1; 2176 case HDSP_ADGainLowGain: 2177 return 2; 2178 default: 2179 return 1; 2180 } 2181 } 2182 2183 static int hdsp_set_ad_gain(struct hdsp *hdsp, int mode) 2184 { 2185 hdsp->control_register &= ~HDSP_ADGainMask; 2186 switch (mode) { 2187 case 0: 2188 hdsp->control_register |= HDSP_ADGainMinus10dBV; 2189 break; 2190 case 1: 2191 hdsp->control_register |= HDSP_ADGainPlus4dBu; 2192 break; 2193 case 2: 2194 hdsp->control_register |= HDSP_ADGainLowGain; 2195 break; 2196 default: 2197 return -1; 2198 2199 } 2200 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 2201 return 0; 2202 } 2203 2204 static int snd_hdsp_info_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2205 { 2206 static const char * const texts[] = {"-10 dBV", "+4 dBu", "Lo Gain"}; 2207 2208 return snd_ctl_enum_info(uinfo, 1, 3, texts); 2209 } 2210 2211 static int snd_hdsp_get_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2212 { 2213 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2214 2215 ucontrol->value.enumerated.item[0] = hdsp_ad_gain(hdsp); 2216 return 0; 2217 } 2218 2219 static int snd_hdsp_put_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2220 { 2221 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2222 int change; 2223 int val; 2224 2225 if (!snd_hdsp_use_is_exclusive(hdsp)) 2226 return -EBUSY; 2227 val = ucontrol->value.enumerated.item[0]; 2228 if (val < 0) val = 0; 2229 if (val > 2) val = 2; 2230 spin_lock_irq(&hdsp->lock); 2231 if (val != hdsp_ad_gain(hdsp)) 2232 change = (hdsp_set_ad_gain(hdsp, val) == 0) ? 1 : 0; 2233 else 2234 change = 0; 2235 spin_unlock_irq(&hdsp->lock); 2236 return change; 2237 } 2238 2239 #define HDSP_PHONE_GAIN(xname, xindex) \ 2240 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2241 .name = xname, \ 2242 .index = xindex, \ 2243 .info = snd_hdsp_info_phone_gain, \ 2244 .get = snd_hdsp_get_phone_gain, \ 2245 .put = snd_hdsp_put_phone_gain \ 2246 } 2247 2248 static int hdsp_phone_gain(struct hdsp *hdsp) 2249 { 2250 switch (hdsp->control_register & HDSP_PhoneGainMask) { 2251 case HDSP_PhoneGain0dB: 2252 return 0; 2253 case HDSP_PhoneGainMinus6dB: 2254 return 1; 2255 case HDSP_PhoneGainMinus12dB: 2256 return 2; 2257 default: 2258 return 0; 2259 } 2260 } 2261 2262 static int hdsp_set_phone_gain(struct hdsp *hdsp, int mode) 2263 { 2264 hdsp->control_register &= ~HDSP_PhoneGainMask; 2265 switch (mode) { 2266 case 0: 2267 hdsp->control_register |= HDSP_PhoneGain0dB; 2268 break; 2269 case 1: 2270 hdsp->control_register |= HDSP_PhoneGainMinus6dB; 2271 break; 2272 case 2: 2273 hdsp->control_register |= HDSP_PhoneGainMinus12dB; 2274 break; 2275 default: 2276 return -1; 2277 2278 } 2279 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 2280 return 0; 2281 } 2282 2283 static int snd_hdsp_info_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2284 { 2285 static const char * const texts[] = {"0 dB", "-6 dB", "-12 dB"}; 2286 2287 return snd_ctl_enum_info(uinfo, 1, 3, texts); 2288 } 2289 2290 static int snd_hdsp_get_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2291 { 2292 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2293 2294 ucontrol->value.enumerated.item[0] = hdsp_phone_gain(hdsp); 2295 return 0; 2296 } 2297 2298 static int snd_hdsp_put_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2299 { 2300 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2301 int change; 2302 int val; 2303 2304 if (!snd_hdsp_use_is_exclusive(hdsp)) 2305 return -EBUSY; 2306 val = ucontrol->value.enumerated.item[0]; 2307 if (val < 0) val = 0; 2308 if (val > 2) val = 2; 2309 spin_lock_irq(&hdsp->lock); 2310 if (val != hdsp_phone_gain(hdsp)) 2311 change = (hdsp_set_phone_gain(hdsp, val) == 0) ? 1 : 0; 2312 else 2313 change = 0; 2314 spin_unlock_irq(&hdsp->lock); 2315 return change; 2316 } 2317 2318 #define HDSP_PREF_SYNC_REF(xname, xindex) \ 2319 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2320 .name = xname, \ 2321 .index = xindex, \ 2322 .info = snd_hdsp_info_pref_sync_ref, \ 2323 .get = snd_hdsp_get_pref_sync_ref, \ 2324 .put = snd_hdsp_put_pref_sync_ref \ 2325 } 2326 2327 static int hdsp_pref_sync_ref(struct hdsp *hdsp) 2328 { 2329 /* Notice that this looks at the requested sync source, 2330 not the one actually in use. 2331 */ 2332 2333 switch (hdsp->control_register & HDSP_SyncRefMask) { 2334 case HDSP_SyncRef_ADAT1: 2335 return HDSP_SYNC_FROM_ADAT1; 2336 case HDSP_SyncRef_ADAT2: 2337 return HDSP_SYNC_FROM_ADAT2; 2338 case HDSP_SyncRef_ADAT3: 2339 return HDSP_SYNC_FROM_ADAT3; 2340 case HDSP_SyncRef_SPDIF: 2341 return HDSP_SYNC_FROM_SPDIF; 2342 case HDSP_SyncRef_WORD: 2343 return HDSP_SYNC_FROM_WORD; 2344 case HDSP_SyncRef_ADAT_SYNC: 2345 return HDSP_SYNC_FROM_ADAT_SYNC; 2346 default: 2347 return HDSP_SYNC_FROM_WORD; 2348 } 2349 return 0; 2350 } 2351 2352 static int hdsp_set_pref_sync_ref(struct hdsp *hdsp, int pref) 2353 { 2354 hdsp->control_register &= ~HDSP_SyncRefMask; 2355 switch (pref) { 2356 case HDSP_SYNC_FROM_ADAT1: 2357 hdsp->control_register &= ~HDSP_SyncRefMask; /* clear SyncRef bits */ 2358 break; 2359 case HDSP_SYNC_FROM_ADAT2: 2360 hdsp->control_register |= HDSP_SyncRef_ADAT2; 2361 break; 2362 case HDSP_SYNC_FROM_ADAT3: 2363 hdsp->control_register |= HDSP_SyncRef_ADAT3; 2364 break; 2365 case HDSP_SYNC_FROM_SPDIF: 2366 hdsp->control_register |= HDSP_SyncRef_SPDIF; 2367 break; 2368 case HDSP_SYNC_FROM_WORD: 2369 hdsp->control_register |= HDSP_SyncRef_WORD; 2370 break; 2371 case HDSP_SYNC_FROM_ADAT_SYNC: 2372 hdsp->control_register |= HDSP_SyncRef_ADAT_SYNC; 2373 break; 2374 default: 2375 return -1; 2376 } 2377 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 2378 return 0; 2379 } 2380 2381 static int snd_hdsp_info_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2382 { 2383 static const char * const texts[] = { 2384 "Word", "IEC958", "ADAT1", "ADAT Sync", "ADAT2", "ADAT3" 2385 }; 2386 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2387 int num_items; 2388 2389 switch (hdsp->io_type) { 2390 case Digiface: 2391 case H9652: 2392 num_items = 6; 2393 break; 2394 case Multiface: 2395 num_items = 4; 2396 break; 2397 case H9632: 2398 num_items = 3; 2399 break; 2400 default: 2401 return -EINVAL; 2402 } 2403 2404 return snd_ctl_enum_info(uinfo, 1, num_items, texts); 2405 } 2406 2407 static int snd_hdsp_get_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2408 { 2409 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2410 2411 ucontrol->value.enumerated.item[0] = hdsp_pref_sync_ref(hdsp); 2412 return 0; 2413 } 2414 2415 static int snd_hdsp_put_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2416 { 2417 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2418 int change, max; 2419 unsigned int val; 2420 2421 if (!snd_hdsp_use_is_exclusive(hdsp)) 2422 return -EBUSY; 2423 2424 switch (hdsp->io_type) { 2425 case Digiface: 2426 case H9652: 2427 max = 6; 2428 break; 2429 case Multiface: 2430 max = 4; 2431 break; 2432 case H9632: 2433 max = 3; 2434 break; 2435 default: 2436 return -EIO; 2437 } 2438 2439 val = ucontrol->value.enumerated.item[0] % max; 2440 spin_lock_irq(&hdsp->lock); 2441 change = (int)val != hdsp_pref_sync_ref(hdsp); 2442 hdsp_set_pref_sync_ref(hdsp, val); 2443 spin_unlock_irq(&hdsp->lock); 2444 return change; 2445 } 2446 2447 #define HDSP_AUTOSYNC_REF(xname, xindex) \ 2448 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2449 .name = xname, \ 2450 .index = xindex, \ 2451 .access = SNDRV_CTL_ELEM_ACCESS_READ, \ 2452 .info = snd_hdsp_info_autosync_ref, \ 2453 .get = snd_hdsp_get_autosync_ref, \ 2454 } 2455 2456 static int hdsp_autosync_ref(struct hdsp *hdsp) 2457 { 2458 /* This looks at the autosync selected sync reference */ 2459 unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register); 2460 2461 switch (status2 & HDSP_SelSyncRefMask) { 2462 case HDSP_SelSyncRef_WORD: 2463 return HDSP_AUTOSYNC_FROM_WORD; 2464 case HDSP_SelSyncRef_ADAT_SYNC: 2465 return HDSP_AUTOSYNC_FROM_ADAT_SYNC; 2466 case HDSP_SelSyncRef_SPDIF: 2467 return HDSP_AUTOSYNC_FROM_SPDIF; 2468 case HDSP_SelSyncRefMask: 2469 return HDSP_AUTOSYNC_FROM_NONE; 2470 case HDSP_SelSyncRef_ADAT1: 2471 return HDSP_AUTOSYNC_FROM_ADAT1; 2472 case HDSP_SelSyncRef_ADAT2: 2473 return HDSP_AUTOSYNC_FROM_ADAT2; 2474 case HDSP_SelSyncRef_ADAT3: 2475 return HDSP_AUTOSYNC_FROM_ADAT3; 2476 default: 2477 return HDSP_AUTOSYNC_FROM_WORD; 2478 } 2479 return 0; 2480 } 2481 2482 static int snd_hdsp_info_autosync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2483 { 2484 static const char * const texts[] = { 2485 "Word", "ADAT Sync", "IEC958", "None", "ADAT1", "ADAT2", "ADAT3" 2486 }; 2487 2488 return snd_ctl_enum_info(uinfo, 1, 7, texts); 2489 } 2490 2491 static int snd_hdsp_get_autosync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2492 { 2493 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2494 2495 ucontrol->value.enumerated.item[0] = hdsp_autosync_ref(hdsp); 2496 return 0; 2497 } 2498 2499 #define HDSP_PRECISE_POINTER(xname, xindex) \ 2500 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, \ 2501 .name = xname, \ 2502 .index = xindex, \ 2503 .info = snd_hdsp_info_precise_pointer, \ 2504 .get = snd_hdsp_get_precise_pointer, \ 2505 .put = snd_hdsp_put_precise_pointer \ 2506 } 2507 2508 static int hdsp_set_precise_pointer(struct hdsp *hdsp, int precise) 2509 { 2510 if (precise) 2511 hdsp->precise_ptr = 1; 2512 else 2513 hdsp->precise_ptr = 0; 2514 return 0; 2515 } 2516 2517 #define snd_hdsp_info_precise_pointer snd_ctl_boolean_mono_info 2518 2519 static int snd_hdsp_get_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2520 { 2521 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2522 2523 spin_lock_irq(&hdsp->lock); 2524 ucontrol->value.integer.value[0] = hdsp->precise_ptr; 2525 spin_unlock_irq(&hdsp->lock); 2526 return 0; 2527 } 2528 2529 static int snd_hdsp_put_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2530 { 2531 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2532 int change; 2533 unsigned int val; 2534 2535 if (!snd_hdsp_use_is_exclusive(hdsp)) 2536 return -EBUSY; 2537 val = ucontrol->value.integer.value[0] & 1; 2538 spin_lock_irq(&hdsp->lock); 2539 change = (int)val != hdsp->precise_ptr; 2540 hdsp_set_precise_pointer(hdsp, val); 2541 spin_unlock_irq(&hdsp->lock); 2542 return change; 2543 } 2544 2545 #define HDSP_USE_MIDI_WORK(xname, xindex) \ 2546 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, \ 2547 .name = xname, \ 2548 .index = xindex, \ 2549 .info = snd_hdsp_info_use_midi_work, \ 2550 .get = snd_hdsp_get_use_midi_work, \ 2551 .put = snd_hdsp_put_use_midi_work \ 2552 } 2553 2554 static int hdsp_set_use_midi_work(struct hdsp *hdsp, int use_work) 2555 { 2556 if (use_work) 2557 hdsp->use_midi_work = 1; 2558 else 2559 hdsp->use_midi_work = 0; 2560 return 0; 2561 } 2562 2563 #define snd_hdsp_info_use_midi_work snd_ctl_boolean_mono_info 2564 2565 static int snd_hdsp_get_use_midi_work(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2566 { 2567 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2568 2569 spin_lock_irq(&hdsp->lock); 2570 ucontrol->value.integer.value[0] = hdsp->use_midi_work; 2571 spin_unlock_irq(&hdsp->lock); 2572 return 0; 2573 } 2574 2575 static int snd_hdsp_put_use_midi_work(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2576 { 2577 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2578 int change; 2579 unsigned int val; 2580 2581 if (!snd_hdsp_use_is_exclusive(hdsp)) 2582 return -EBUSY; 2583 val = ucontrol->value.integer.value[0] & 1; 2584 spin_lock_irq(&hdsp->lock); 2585 change = (int)val != hdsp->use_midi_work; 2586 hdsp_set_use_midi_work(hdsp, val); 2587 spin_unlock_irq(&hdsp->lock); 2588 return change; 2589 } 2590 2591 #define HDSP_MIXER(xname, xindex) \ 2592 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \ 2593 .name = xname, \ 2594 .index = xindex, \ 2595 .device = 0, \ 2596 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \ 2597 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 2598 .info = snd_hdsp_info_mixer, \ 2599 .get = snd_hdsp_get_mixer, \ 2600 .put = snd_hdsp_put_mixer \ 2601 } 2602 2603 static int snd_hdsp_info_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2604 { 2605 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 2606 uinfo->count = 3; 2607 uinfo->value.integer.min = 0; 2608 uinfo->value.integer.max = 65536; 2609 uinfo->value.integer.step = 1; 2610 return 0; 2611 } 2612 2613 static int snd_hdsp_get_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2614 { 2615 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2616 int source; 2617 int destination; 2618 int addr; 2619 2620 source = ucontrol->value.integer.value[0]; 2621 destination = ucontrol->value.integer.value[1]; 2622 2623 if (source >= hdsp->max_channels) 2624 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels,destination); 2625 else 2626 addr = hdsp_input_to_output_key(hdsp,source, destination); 2627 2628 spin_lock_irq(&hdsp->lock); 2629 ucontrol->value.integer.value[2] = hdsp_read_gain (hdsp, addr); 2630 spin_unlock_irq(&hdsp->lock); 2631 return 0; 2632 } 2633 2634 static int snd_hdsp_put_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2635 { 2636 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2637 int change; 2638 int source; 2639 int destination; 2640 int gain; 2641 int addr; 2642 2643 if (!snd_hdsp_use_is_exclusive(hdsp)) 2644 return -EBUSY; 2645 2646 source = ucontrol->value.integer.value[0]; 2647 destination = ucontrol->value.integer.value[1]; 2648 2649 if (source >= hdsp->max_channels) 2650 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels, destination); 2651 else 2652 addr = hdsp_input_to_output_key(hdsp,source, destination); 2653 2654 gain = ucontrol->value.integer.value[2]; 2655 2656 spin_lock_irq(&hdsp->lock); 2657 change = gain != hdsp_read_gain(hdsp, addr); 2658 if (change) 2659 hdsp_write_gain(hdsp, addr, gain); 2660 spin_unlock_irq(&hdsp->lock); 2661 return change; 2662 } 2663 2664 #define HDSP_WC_SYNC_CHECK(xname, xindex) \ 2665 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2666 .name = xname, \ 2667 .index = xindex, \ 2668 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 2669 .info = snd_hdsp_info_sync_check, \ 2670 .get = snd_hdsp_get_wc_sync_check \ 2671 } 2672 2673 static int snd_hdsp_info_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2674 { 2675 static const char * const texts[] = {"No Lock", "Lock", "Sync" }; 2676 2677 return snd_ctl_enum_info(uinfo, 1, 3, texts); 2678 } 2679 2680 static int hdsp_wc_sync_check(struct hdsp *hdsp) 2681 { 2682 int status2 = hdsp_read(hdsp, HDSP_status2Register); 2683 if (status2 & HDSP_wc_lock) { 2684 if (status2 & HDSP_wc_sync) 2685 return 2; 2686 else 2687 return 1; 2688 } else 2689 return 0; 2690 return 0; 2691 } 2692 2693 static int snd_hdsp_get_wc_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2694 { 2695 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2696 2697 ucontrol->value.enumerated.item[0] = hdsp_wc_sync_check(hdsp); 2698 return 0; 2699 } 2700 2701 #define HDSP_SPDIF_SYNC_CHECK(xname, xindex) \ 2702 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2703 .name = xname, \ 2704 .index = xindex, \ 2705 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 2706 .info = snd_hdsp_info_sync_check, \ 2707 .get = snd_hdsp_get_spdif_sync_check \ 2708 } 2709 2710 static int hdsp_spdif_sync_check(struct hdsp *hdsp) 2711 { 2712 int status = hdsp_read(hdsp, HDSP_statusRegister); 2713 if (status & HDSP_SPDIFErrorFlag) 2714 return 0; 2715 else { 2716 if (status & HDSP_SPDIFSync) 2717 return 2; 2718 else 2719 return 1; 2720 } 2721 return 0; 2722 } 2723 2724 static int snd_hdsp_get_spdif_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2725 { 2726 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2727 2728 ucontrol->value.enumerated.item[0] = hdsp_spdif_sync_check(hdsp); 2729 return 0; 2730 } 2731 2732 #define HDSP_ADATSYNC_SYNC_CHECK(xname, xindex) \ 2733 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2734 .name = xname, \ 2735 .index = xindex, \ 2736 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 2737 .info = snd_hdsp_info_sync_check, \ 2738 .get = snd_hdsp_get_adatsync_sync_check \ 2739 } 2740 2741 static int hdsp_adatsync_sync_check(struct hdsp *hdsp) 2742 { 2743 int status = hdsp_read(hdsp, HDSP_statusRegister); 2744 if (status & HDSP_TimecodeLock) { 2745 if (status & HDSP_TimecodeSync) 2746 return 2; 2747 else 2748 return 1; 2749 } else 2750 return 0; 2751 } 2752 2753 static int snd_hdsp_get_adatsync_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2754 { 2755 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2756 2757 ucontrol->value.enumerated.item[0] = hdsp_adatsync_sync_check(hdsp); 2758 return 0; 2759 } 2760 2761 #define HDSP_ADAT_SYNC_CHECK \ 2762 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2763 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 2764 .info = snd_hdsp_info_sync_check, \ 2765 .get = snd_hdsp_get_adat_sync_check \ 2766 } 2767 2768 static int hdsp_adat_sync_check(struct hdsp *hdsp, int idx) 2769 { 2770 int status = hdsp_read(hdsp, HDSP_statusRegister); 2771 2772 if (status & (HDSP_Lock0>>idx)) { 2773 if (status & (HDSP_Sync0>>idx)) 2774 return 2; 2775 else 2776 return 1; 2777 } else 2778 return 0; 2779 } 2780 2781 static int snd_hdsp_get_adat_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2782 { 2783 int offset; 2784 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2785 2786 offset = ucontrol->id.index - 1; 2787 if (snd_BUG_ON(offset < 0)) 2788 return -EINVAL; 2789 2790 switch (hdsp->io_type) { 2791 case Digiface: 2792 case H9652: 2793 if (offset >= 3) 2794 return -EINVAL; 2795 break; 2796 case Multiface: 2797 case H9632: 2798 if (offset >= 1) 2799 return -EINVAL; 2800 break; 2801 default: 2802 return -EIO; 2803 } 2804 2805 ucontrol->value.enumerated.item[0] = hdsp_adat_sync_check(hdsp, offset); 2806 return 0; 2807 } 2808 2809 #define HDSP_DDS_OFFSET(xname, xindex) \ 2810 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2811 .name = xname, \ 2812 .index = xindex, \ 2813 .info = snd_hdsp_info_dds_offset, \ 2814 .get = snd_hdsp_get_dds_offset, \ 2815 .put = snd_hdsp_put_dds_offset \ 2816 } 2817 2818 static int hdsp_dds_offset(struct hdsp *hdsp) 2819 { 2820 u64 n; 2821 unsigned int dds_value = hdsp->dds_value; 2822 int system_sample_rate = hdsp->system_sample_rate; 2823 2824 if (!dds_value) 2825 return 0; 2826 2827 n = DDS_NUMERATOR; 2828 /* 2829 * dds_value = n / rate 2830 * rate = n / dds_value 2831 */ 2832 n = div_u64(n, dds_value); 2833 if (system_sample_rate >= 112000) 2834 n *= 4; 2835 else if (system_sample_rate >= 56000) 2836 n *= 2; 2837 return ((int)n) - system_sample_rate; 2838 } 2839 2840 static int hdsp_set_dds_offset(struct hdsp *hdsp, int offset_hz) 2841 { 2842 int rate = hdsp->system_sample_rate + offset_hz; 2843 hdsp_set_dds_value(hdsp, rate); 2844 return 0; 2845 } 2846 2847 static int snd_hdsp_info_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2848 { 2849 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 2850 uinfo->count = 1; 2851 uinfo->value.integer.min = -5000; 2852 uinfo->value.integer.max = 5000; 2853 return 0; 2854 } 2855 2856 static int snd_hdsp_get_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2857 { 2858 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2859 2860 ucontrol->value.integer.value[0] = hdsp_dds_offset(hdsp); 2861 return 0; 2862 } 2863 2864 static int snd_hdsp_put_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2865 { 2866 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2867 int change; 2868 int val; 2869 2870 if (!snd_hdsp_use_is_exclusive(hdsp)) 2871 return -EBUSY; 2872 val = ucontrol->value.integer.value[0]; 2873 spin_lock_irq(&hdsp->lock); 2874 if (val != hdsp_dds_offset(hdsp)) 2875 change = (hdsp_set_dds_offset(hdsp, val) == 0) ? 1 : 0; 2876 else 2877 change = 0; 2878 spin_unlock_irq(&hdsp->lock); 2879 return change; 2880 } 2881 2882 static const struct snd_kcontrol_new snd_hdsp_9632_controls[] = { 2883 HDSP_DA_GAIN("DA Gain", 0), 2884 HDSP_AD_GAIN("AD Gain", 0), 2885 HDSP_PHONE_GAIN("Phones Gain", 0), 2886 HDSP_TOGGLE_SETTING("XLR Breakout Cable", HDSP_XLRBreakoutCable), 2887 HDSP_DDS_OFFSET("DDS Sample Rate Offset", 0) 2888 }; 2889 2890 static const struct snd_kcontrol_new snd_hdsp_controls[] = { 2891 { 2892 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 2893 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT), 2894 .info = snd_hdsp_control_spdif_info, 2895 .get = snd_hdsp_control_spdif_get, 2896 .put = snd_hdsp_control_spdif_put, 2897 }, 2898 { 2899 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE, 2900 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 2901 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM), 2902 .info = snd_hdsp_control_spdif_stream_info, 2903 .get = snd_hdsp_control_spdif_stream_get, 2904 .put = snd_hdsp_control_spdif_stream_put, 2905 }, 2906 { 2907 .access = SNDRV_CTL_ELEM_ACCESS_READ, 2908 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 2909 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK), 2910 .info = snd_hdsp_control_spdif_mask_info, 2911 .get = snd_hdsp_control_spdif_mask_get, 2912 .private_value = IEC958_AES0_NONAUDIO | 2913 IEC958_AES0_PROFESSIONAL | 2914 IEC958_AES0_CON_EMPHASIS, 2915 }, 2916 { 2917 .access = SNDRV_CTL_ELEM_ACCESS_READ, 2918 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 2919 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK), 2920 .info = snd_hdsp_control_spdif_mask_info, 2921 .get = snd_hdsp_control_spdif_mask_get, 2922 .private_value = IEC958_AES0_NONAUDIO | 2923 IEC958_AES0_PROFESSIONAL | 2924 IEC958_AES0_PRO_EMPHASIS, 2925 }, 2926 HDSP_MIXER("Mixer", 0), 2927 HDSP_SPDIF_IN("IEC958 Input Connector", 0), 2928 HDSP_TOGGLE_SETTING("IEC958 Output also on ADAT1", HDSP_SPDIFOpticalOut), 2929 HDSP_TOGGLE_SETTING("IEC958 Professional Bit", HDSP_SPDIFProfessional), 2930 HDSP_TOGGLE_SETTING("IEC958 Emphasis Bit", HDSP_SPDIFEmphasis), 2931 HDSP_TOGGLE_SETTING("IEC958 Non-audio Bit", HDSP_SPDIFNonAudio), 2932 /* 'Sample Clock Source' complies with the alsa control naming scheme */ 2933 HDSP_CLOCK_SOURCE("Sample Clock Source", 0), 2934 { 2935 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2936 .name = "Sample Clock Source Locking", 2937 .info = snd_hdsp_info_clock_source_lock, 2938 .get = snd_hdsp_get_clock_source_lock, 2939 .put = snd_hdsp_put_clock_source_lock, 2940 }, 2941 HDSP_SYSTEM_CLOCK_MODE("System Clock Mode", 0), 2942 HDSP_PREF_SYNC_REF("Preferred Sync Reference", 0), 2943 HDSP_AUTOSYNC_REF("AutoSync Reference", 0), 2944 HDSP_SPDIF_SAMPLE_RATE("SPDIF Sample Rate", 0), 2945 HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), 2946 /* 'External Rate' complies with the alsa control naming scheme */ 2947 HDSP_AUTOSYNC_SAMPLE_RATE("External Rate", 0), 2948 HDSP_WC_SYNC_CHECK("Word Clock Lock Status", 0), 2949 HDSP_SPDIF_SYNC_CHECK("SPDIF Lock Status", 0), 2950 HDSP_ADATSYNC_SYNC_CHECK("ADAT Sync Lock Status", 0), 2951 HDSP_TOGGLE_SETTING("Line Out", HDSP_LineOut), 2952 HDSP_PRECISE_POINTER("Precise Pointer", 0), 2953 HDSP_USE_MIDI_WORK("Use Midi Tasklet", 0), 2954 }; 2955 2956 2957 static int hdsp_rpm_input12(struct hdsp *hdsp) 2958 { 2959 switch (hdsp->control_register & HDSP_RPM_Inp12) { 2960 case HDSP_RPM_Inp12_Phon_6dB: 2961 return 0; 2962 case HDSP_RPM_Inp12_Phon_n6dB: 2963 return 2; 2964 case HDSP_RPM_Inp12_Line_0dB: 2965 return 3; 2966 case HDSP_RPM_Inp12_Line_n6dB: 2967 return 4; 2968 } 2969 return 1; 2970 } 2971 2972 2973 static int snd_hdsp_get_rpm_input12(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2974 { 2975 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2976 2977 ucontrol->value.enumerated.item[0] = hdsp_rpm_input12(hdsp); 2978 return 0; 2979 } 2980 2981 2982 static int hdsp_set_rpm_input12(struct hdsp *hdsp, int mode) 2983 { 2984 hdsp->control_register &= ~HDSP_RPM_Inp12; 2985 switch (mode) { 2986 case 0: 2987 hdsp->control_register |= HDSP_RPM_Inp12_Phon_6dB; 2988 break; 2989 case 1: 2990 break; 2991 case 2: 2992 hdsp->control_register |= HDSP_RPM_Inp12_Phon_n6dB; 2993 break; 2994 case 3: 2995 hdsp->control_register |= HDSP_RPM_Inp12_Line_0dB; 2996 break; 2997 case 4: 2998 hdsp->control_register |= HDSP_RPM_Inp12_Line_n6dB; 2999 break; 3000 default: 3001 return -1; 3002 } 3003 3004 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 3005 return 0; 3006 } 3007 3008 3009 static int snd_hdsp_put_rpm_input12(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 3010 { 3011 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 3012 int change; 3013 int val; 3014 3015 if (!snd_hdsp_use_is_exclusive(hdsp)) 3016 return -EBUSY; 3017 val = ucontrol->value.enumerated.item[0]; 3018 if (val < 0) 3019 val = 0; 3020 if (val > 4) 3021 val = 4; 3022 spin_lock_irq(&hdsp->lock); 3023 if (val != hdsp_rpm_input12(hdsp)) 3024 change = (hdsp_set_rpm_input12(hdsp, val) == 0) ? 1 : 0; 3025 else 3026 change = 0; 3027 spin_unlock_irq(&hdsp->lock); 3028 return change; 3029 } 3030 3031 3032 static int snd_hdsp_info_rpm_input(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 3033 { 3034 static const char * const texts[] = { 3035 "Phono +6dB", "Phono 0dB", "Phono -6dB", "Line 0dB", "Line -6dB" 3036 }; 3037 3038 return snd_ctl_enum_info(uinfo, 1, 5, texts); 3039 } 3040 3041 3042 static int hdsp_rpm_input34(struct hdsp *hdsp) 3043 { 3044 switch (hdsp->control_register & HDSP_RPM_Inp34) { 3045 case HDSP_RPM_Inp34_Phon_6dB: 3046 return 0; 3047 case HDSP_RPM_Inp34_Phon_n6dB: 3048 return 2; 3049 case HDSP_RPM_Inp34_Line_0dB: 3050 return 3; 3051 case HDSP_RPM_Inp34_Line_n6dB: 3052 return 4; 3053 } 3054 return 1; 3055 } 3056 3057 3058 static int snd_hdsp_get_rpm_input34(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 3059 { 3060 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 3061 3062 ucontrol->value.enumerated.item[0] = hdsp_rpm_input34(hdsp); 3063 return 0; 3064 } 3065 3066 3067 static int hdsp_set_rpm_input34(struct hdsp *hdsp, int mode) 3068 { 3069 hdsp->control_register &= ~HDSP_RPM_Inp34; 3070 switch (mode) { 3071 case 0: 3072 hdsp->control_register |= HDSP_RPM_Inp34_Phon_6dB; 3073 break; 3074 case 1: 3075 break; 3076 case 2: 3077 hdsp->control_register |= HDSP_RPM_Inp34_Phon_n6dB; 3078 break; 3079 case 3: 3080 hdsp->control_register |= HDSP_RPM_Inp34_Line_0dB; 3081 break; 3082 case 4: 3083 hdsp->control_register |= HDSP_RPM_Inp34_Line_n6dB; 3084 break; 3085 default: 3086 return -1; 3087 } 3088 3089 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 3090 return 0; 3091 } 3092 3093 3094 static int snd_hdsp_put_rpm_input34(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 3095 { 3096 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 3097 int change; 3098 int val; 3099 3100 if (!snd_hdsp_use_is_exclusive(hdsp)) 3101 return -EBUSY; 3102 val = ucontrol->value.enumerated.item[0]; 3103 if (val < 0) 3104 val = 0; 3105 if (val > 4) 3106 val = 4; 3107 spin_lock_irq(&hdsp->lock); 3108 if (val != hdsp_rpm_input34(hdsp)) 3109 change = (hdsp_set_rpm_input34(hdsp, val) == 0) ? 1 : 0; 3110 else 3111 change = 0; 3112 spin_unlock_irq(&hdsp->lock); 3113 return change; 3114 } 3115 3116 3117 /* RPM Bypass switch */ 3118 static int hdsp_rpm_bypass(struct hdsp *hdsp) 3119 { 3120 return (hdsp->control_register & HDSP_RPM_Bypass) ? 1 : 0; 3121 } 3122 3123 3124 static int snd_hdsp_get_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 3125 { 3126 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 3127 3128 ucontrol->value.integer.value[0] = hdsp_rpm_bypass(hdsp); 3129 return 0; 3130 } 3131 3132 3133 static int hdsp_set_rpm_bypass(struct hdsp *hdsp, int on) 3134 { 3135 if (on) 3136 hdsp->control_register |= HDSP_RPM_Bypass; 3137 else 3138 hdsp->control_register &= ~HDSP_RPM_Bypass; 3139 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 3140 return 0; 3141 } 3142 3143 3144 static int snd_hdsp_put_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 3145 { 3146 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 3147 int change; 3148 unsigned int val; 3149 3150 if (!snd_hdsp_use_is_exclusive(hdsp)) 3151 return -EBUSY; 3152 val = ucontrol->value.integer.value[0] & 1; 3153 spin_lock_irq(&hdsp->lock); 3154 change = (int)val != hdsp_rpm_bypass(hdsp); 3155 hdsp_set_rpm_bypass(hdsp, val); 3156 spin_unlock_irq(&hdsp->lock); 3157 return change; 3158 } 3159 3160 3161 static int snd_hdsp_info_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 3162 { 3163 static const char * const texts[] = {"On", "Off"}; 3164 3165 return snd_ctl_enum_info(uinfo, 1, 2, texts); 3166 } 3167 3168 3169 /* RPM Disconnect switch */ 3170 static int hdsp_rpm_disconnect(struct hdsp *hdsp) 3171 { 3172 return (hdsp->control_register & HDSP_RPM_Disconnect) ? 1 : 0; 3173 } 3174 3175 3176 static int snd_hdsp_get_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 3177 { 3178 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 3179 3180 ucontrol->value.integer.value[0] = hdsp_rpm_disconnect(hdsp); 3181 return 0; 3182 } 3183 3184 3185 static int hdsp_set_rpm_disconnect(struct hdsp *hdsp, int on) 3186 { 3187 if (on) 3188 hdsp->control_register |= HDSP_RPM_Disconnect; 3189 else 3190 hdsp->control_register &= ~HDSP_RPM_Disconnect; 3191 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 3192 return 0; 3193 } 3194 3195 3196 static int snd_hdsp_put_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 3197 { 3198 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 3199 int change; 3200 unsigned int val; 3201 3202 if (!snd_hdsp_use_is_exclusive(hdsp)) 3203 return -EBUSY; 3204 val = ucontrol->value.integer.value[0] & 1; 3205 spin_lock_irq(&hdsp->lock); 3206 change = (int)val != hdsp_rpm_disconnect(hdsp); 3207 hdsp_set_rpm_disconnect(hdsp, val); 3208 spin_unlock_irq(&hdsp->lock); 3209 return change; 3210 } 3211 3212 static int snd_hdsp_info_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 3213 { 3214 static const char * const texts[] = {"On", "Off"}; 3215 3216 return snd_ctl_enum_info(uinfo, 1, 2, texts); 3217 } 3218 3219 static const struct snd_kcontrol_new snd_hdsp_rpm_controls[] = { 3220 { 3221 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 3222 .name = "RPM Bypass", 3223 .get = snd_hdsp_get_rpm_bypass, 3224 .put = snd_hdsp_put_rpm_bypass, 3225 .info = snd_hdsp_info_rpm_bypass 3226 }, 3227 { 3228 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 3229 .name = "RPM Disconnect", 3230 .get = snd_hdsp_get_rpm_disconnect, 3231 .put = snd_hdsp_put_rpm_disconnect, 3232 .info = snd_hdsp_info_rpm_disconnect 3233 }, 3234 { 3235 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 3236 .name = "Input 1/2", 3237 .get = snd_hdsp_get_rpm_input12, 3238 .put = snd_hdsp_put_rpm_input12, 3239 .info = snd_hdsp_info_rpm_input 3240 }, 3241 { 3242 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 3243 .name = "Input 3/4", 3244 .get = snd_hdsp_get_rpm_input34, 3245 .put = snd_hdsp_put_rpm_input34, 3246 .info = snd_hdsp_info_rpm_input 3247 }, 3248 HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), 3249 HDSP_MIXER("Mixer", 0) 3250 }; 3251 3252 static const struct snd_kcontrol_new snd_hdsp_96xx_aeb = 3253 HDSP_TOGGLE_SETTING("Analog Extension Board", 3254 HDSP_AnalogExtensionBoard); 3255 static struct snd_kcontrol_new snd_hdsp_adat_sync_check = HDSP_ADAT_SYNC_CHECK; 3256 3257 3258 static bool hdsp_loopback_get(struct hdsp *const hdsp, const u8 channel) 3259 { 3260 return hdsp->io_loopback & (1 << channel); 3261 } 3262 3263 static int hdsp_loopback_set(struct hdsp *const hdsp, const u8 channel, const bool enable) 3264 { 3265 if (hdsp_loopback_get(hdsp, channel) == enable) 3266 return 0; 3267 3268 hdsp->io_loopback ^= (1 << channel); 3269 3270 hdsp_write(hdsp, HDSP_inputEnable + (4 * (hdsp->max_channels + channel)), enable); 3271 3272 return 1; 3273 } 3274 3275 static int snd_hdsp_loopback_get(struct snd_kcontrol *const kcontrol, 3276 struct snd_ctl_elem_value *const ucontrol) 3277 { 3278 struct hdsp *const hdsp = snd_kcontrol_chip(kcontrol); 3279 const u8 channel = snd_ctl_get_ioff(kcontrol, &ucontrol->id); 3280 3281 if (channel >= hdsp->max_channels) 3282 return -ENOENT; 3283 3284 ucontrol->value.integer.value[0] = hdsp_loopback_get(hdsp, channel); 3285 3286 return 0; 3287 } 3288 3289 static int snd_hdsp_loopback_put(struct snd_kcontrol *const kcontrol, 3290 struct snd_ctl_elem_value *const ucontrol) 3291 { 3292 struct hdsp *const hdsp = snd_kcontrol_chip(kcontrol); 3293 const u8 channel = snd_ctl_get_ioff(kcontrol, &ucontrol->id); 3294 const bool enable = ucontrol->value.integer.value[0] & 1; 3295 3296 if (channel >= hdsp->max_channels) 3297 return -ENOENT; 3298 3299 return hdsp_loopback_set(hdsp, channel, enable); 3300 } 3301 3302 static struct snd_kcontrol_new snd_hdsp_loopback_control = { 3303 .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, 3304 .name = "Output Loopback", 3305 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, 3306 .info = snd_ctl_boolean_mono_info, 3307 .get = snd_hdsp_loopback_get, 3308 .put = snd_hdsp_loopback_put 3309 }; 3310 3311 static int snd_hdsp_create_controls(struct snd_card *card, struct hdsp *hdsp) 3312 { 3313 unsigned int idx; 3314 int err; 3315 struct snd_kcontrol *kctl; 3316 3317 if (hdsp->io_type == RPM) { 3318 /* RPM Bypass, Disconnect and Input switches */ 3319 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_rpm_controls); idx++) { 3320 err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_rpm_controls[idx], hdsp)); 3321 if (err < 0) 3322 return err; 3323 } 3324 return 0; 3325 } 3326 3327 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_controls); idx++) { 3328 kctl = snd_ctl_new1(&snd_hdsp_controls[idx], hdsp); 3329 err = snd_ctl_add(card, kctl); 3330 if (err < 0) 3331 return err; 3332 if (idx == 1) /* IEC958 (S/PDIF) Stream */ 3333 hdsp->spdif_ctl = kctl; 3334 } 3335 3336 /* ADAT SyncCheck status */ 3337 snd_hdsp_adat_sync_check.name = "ADAT Lock Status"; 3338 snd_hdsp_adat_sync_check.index = 1; 3339 kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp); 3340 err = snd_ctl_add(card, kctl); 3341 if (err < 0) 3342 return err; 3343 if (hdsp->io_type == Digiface || hdsp->io_type == H9652) { 3344 for (idx = 1; idx < 3; ++idx) { 3345 snd_hdsp_adat_sync_check.index = idx+1; 3346 kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp); 3347 err = snd_ctl_add(card, kctl); 3348 if (err < 0) 3349 return err; 3350 } 3351 } 3352 3353 /* DA, AD and Phone gain and XLR breakout cable controls for H9632 cards */ 3354 if (hdsp->io_type == H9632) { 3355 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_9632_controls); idx++) { 3356 kctl = snd_ctl_new1(&snd_hdsp_9632_controls[idx], hdsp); 3357 err = snd_ctl_add(card, kctl); 3358 if (err < 0) 3359 return err; 3360 } 3361 } 3362 3363 /* Output loopback controls for H9632 cards */ 3364 if (hdsp->io_type == H9632) { 3365 snd_hdsp_loopback_control.count = hdsp->max_channels; 3366 kctl = snd_ctl_new1(&snd_hdsp_loopback_control, hdsp); 3367 if (kctl == NULL) 3368 return -ENOMEM; 3369 err = snd_ctl_add(card, kctl); 3370 if (err < 0) 3371 return err; 3372 } 3373 3374 /* AEB control for H96xx card */ 3375 if (hdsp->io_type == H9632 || hdsp->io_type == H9652) { 3376 kctl = snd_ctl_new1(&snd_hdsp_96xx_aeb, hdsp); 3377 err = snd_ctl_add(card, kctl); 3378 if (err < 0) 3379 return err; 3380 } 3381 3382 return 0; 3383 } 3384 3385 /*------------------------------------------------------------ 3386 /proc interface 3387 ------------------------------------------------------------*/ 3388 3389 static void 3390 snd_hdsp_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer) 3391 { 3392 struct hdsp *hdsp = entry->private_data; 3393 unsigned int status; 3394 unsigned int status2; 3395 char *pref_sync_ref; 3396 char *autosync_ref; 3397 char *system_clock_mode; 3398 char *clock_source; 3399 int x; 3400 3401 status = hdsp_read(hdsp, HDSP_statusRegister); 3402 status2 = hdsp_read(hdsp, HDSP_status2Register); 3403 3404 snd_iprintf(buffer, "%s (Card #%d)\n", hdsp->card_name, 3405 hdsp->card->number + 1); 3406 snd_iprintf(buffer, "Buffers: capture %p playback %p\n", 3407 hdsp->capture_buffer, hdsp->playback_buffer); 3408 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n", 3409 hdsp->irq, hdsp->port, (unsigned long)hdsp->iobase); 3410 snd_iprintf(buffer, "Control register: 0x%x\n", hdsp->control_register); 3411 snd_iprintf(buffer, "Control2 register: 0x%x\n", 3412 hdsp->control2_register); 3413 snd_iprintf(buffer, "Status register: 0x%x\n", status); 3414 snd_iprintf(buffer, "Status2 register: 0x%x\n", status2); 3415 3416 if (hdsp_check_for_iobox(hdsp)) { 3417 snd_iprintf(buffer, "No I/O box connected.\n" 3418 "Please connect one and upload firmware.\n"); 3419 return; 3420 } 3421 3422 if (hdsp_check_for_firmware(hdsp, 0)) { 3423 if (hdsp->state & HDSP_FirmwareCached) { 3424 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) { 3425 snd_iprintf(buffer, "Firmware loading from " 3426 "cache failed, " 3427 "please upload manually.\n"); 3428 return; 3429 } 3430 } else { 3431 int err; 3432 3433 err = hdsp_request_fw_loader(hdsp); 3434 if (err < 0) { 3435 snd_iprintf(buffer, 3436 "No firmware loaded nor cached, " 3437 "please upload firmware.\n"); 3438 return; 3439 } 3440 } 3441 } 3442 3443 snd_iprintf(buffer, "FIFO status: %d\n", hdsp_read(hdsp, HDSP_fifoStatus) & 0xff); 3444 snd_iprintf(buffer, "MIDI1 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut0)); 3445 snd_iprintf(buffer, "MIDI1 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn0)); 3446 snd_iprintf(buffer, "MIDI2 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut1)); 3447 snd_iprintf(buffer, "MIDI2 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn1)); 3448 snd_iprintf(buffer, "Use Midi Tasklet: %s\n", hdsp->use_midi_work ? "on" : "off"); 3449 3450 snd_iprintf(buffer, "\n"); 3451 3452 x = 1 << (6 + hdsp_decode_latency(hdsp->control_register & HDSP_LatencyMask)); 3453 3454 snd_iprintf(buffer, "Buffer Size (Latency): %d samples (2 periods of %lu bytes)\n", x, (unsigned long) hdsp->period_bytes); 3455 snd_iprintf(buffer, "Hardware pointer (frames): %ld\n", hdsp_hw_pointer(hdsp)); 3456 snd_iprintf(buffer, "Precise pointer: %s\n", hdsp->precise_ptr ? "on" : "off"); 3457 snd_iprintf(buffer, "Line out: %s\n", (hdsp->control_register & HDSP_LineOut) ? "on" : "off"); 3458 3459 snd_iprintf(buffer, "Firmware version: %d\n", (status2&HDSP_version0)|(status2&HDSP_version1)<<1|(status2&HDSP_version2)<<2); 3460 3461 snd_iprintf(buffer, "\n"); 3462 3463 switch (hdsp_clock_source(hdsp)) { 3464 case HDSP_CLOCK_SOURCE_AUTOSYNC: 3465 clock_source = "AutoSync"; 3466 break; 3467 case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ: 3468 clock_source = "Internal 32 kHz"; 3469 break; 3470 case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ: 3471 clock_source = "Internal 44.1 kHz"; 3472 break; 3473 case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ: 3474 clock_source = "Internal 48 kHz"; 3475 break; 3476 case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ: 3477 clock_source = "Internal 64 kHz"; 3478 break; 3479 case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ: 3480 clock_source = "Internal 88.2 kHz"; 3481 break; 3482 case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ: 3483 clock_source = "Internal 96 kHz"; 3484 break; 3485 case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ: 3486 clock_source = "Internal 128 kHz"; 3487 break; 3488 case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ: 3489 clock_source = "Internal 176.4 kHz"; 3490 break; 3491 case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ: 3492 clock_source = "Internal 192 kHz"; 3493 break; 3494 default: 3495 clock_source = "Error"; 3496 } 3497 snd_iprintf (buffer, "Sample Clock Source: %s\n", clock_source); 3498 3499 if (hdsp_system_clock_mode(hdsp)) 3500 system_clock_mode = "Slave"; 3501 else 3502 system_clock_mode = "Master"; 3503 3504 switch (hdsp_pref_sync_ref (hdsp)) { 3505 case HDSP_SYNC_FROM_WORD: 3506 pref_sync_ref = "Word Clock"; 3507 break; 3508 case HDSP_SYNC_FROM_ADAT_SYNC: 3509 pref_sync_ref = "ADAT Sync"; 3510 break; 3511 case HDSP_SYNC_FROM_SPDIF: 3512 pref_sync_ref = "SPDIF"; 3513 break; 3514 case HDSP_SYNC_FROM_ADAT1: 3515 pref_sync_ref = "ADAT1"; 3516 break; 3517 case HDSP_SYNC_FROM_ADAT2: 3518 pref_sync_ref = "ADAT2"; 3519 break; 3520 case HDSP_SYNC_FROM_ADAT3: 3521 pref_sync_ref = "ADAT3"; 3522 break; 3523 default: 3524 pref_sync_ref = "Word Clock"; 3525 break; 3526 } 3527 snd_iprintf (buffer, "Preferred Sync Reference: %s\n", pref_sync_ref); 3528 3529 switch (hdsp_autosync_ref (hdsp)) { 3530 case HDSP_AUTOSYNC_FROM_WORD: 3531 autosync_ref = "Word Clock"; 3532 break; 3533 case HDSP_AUTOSYNC_FROM_ADAT_SYNC: 3534 autosync_ref = "ADAT Sync"; 3535 break; 3536 case HDSP_AUTOSYNC_FROM_SPDIF: 3537 autosync_ref = "SPDIF"; 3538 break; 3539 case HDSP_AUTOSYNC_FROM_NONE: 3540 autosync_ref = "None"; 3541 break; 3542 case HDSP_AUTOSYNC_FROM_ADAT1: 3543 autosync_ref = "ADAT1"; 3544 break; 3545 case HDSP_AUTOSYNC_FROM_ADAT2: 3546 autosync_ref = "ADAT2"; 3547 break; 3548 case HDSP_AUTOSYNC_FROM_ADAT3: 3549 autosync_ref = "ADAT3"; 3550 break; 3551 default: 3552 autosync_ref = "---"; 3553 break; 3554 } 3555 snd_iprintf (buffer, "AutoSync Reference: %s\n", autosync_ref); 3556 3557 snd_iprintf (buffer, "AutoSync Frequency: %d\n", hdsp_external_sample_rate(hdsp)); 3558 3559 snd_iprintf (buffer, "System Clock Mode: %s\n", system_clock_mode); 3560 3561 snd_iprintf (buffer, "System Clock Frequency: %d\n", hdsp->system_sample_rate); 3562 snd_iprintf (buffer, "System Clock Locked: %s\n", hdsp->clock_source_locked ? "Yes" : "No"); 3563 3564 snd_iprintf(buffer, "\n"); 3565 3566 if (hdsp->io_type != RPM) { 3567 switch (hdsp_spdif_in(hdsp)) { 3568 case HDSP_SPDIFIN_OPTICAL: 3569 snd_iprintf(buffer, "IEC958 input: Optical\n"); 3570 break; 3571 case HDSP_SPDIFIN_COAXIAL: 3572 snd_iprintf(buffer, "IEC958 input: Coaxial\n"); 3573 break; 3574 case HDSP_SPDIFIN_INTERNAL: 3575 snd_iprintf(buffer, "IEC958 input: Internal\n"); 3576 break; 3577 case HDSP_SPDIFIN_AES: 3578 snd_iprintf(buffer, "IEC958 input: AES\n"); 3579 break; 3580 default: 3581 snd_iprintf(buffer, "IEC958 input: ???\n"); 3582 break; 3583 } 3584 } 3585 3586 if (RPM == hdsp->io_type) { 3587 if (hdsp->control_register & HDSP_RPM_Bypass) 3588 snd_iprintf(buffer, "RPM Bypass: disabled\n"); 3589 else 3590 snd_iprintf(buffer, "RPM Bypass: enabled\n"); 3591 if (hdsp->control_register & HDSP_RPM_Disconnect) 3592 snd_iprintf(buffer, "RPM disconnected\n"); 3593 else 3594 snd_iprintf(buffer, "RPM connected\n"); 3595 3596 switch (hdsp->control_register & HDSP_RPM_Inp12) { 3597 case HDSP_RPM_Inp12_Phon_6dB: 3598 snd_iprintf(buffer, "Input 1/2: Phono, 6dB\n"); 3599 break; 3600 case HDSP_RPM_Inp12_Phon_0dB: 3601 snd_iprintf(buffer, "Input 1/2: Phono, 0dB\n"); 3602 break; 3603 case HDSP_RPM_Inp12_Phon_n6dB: 3604 snd_iprintf(buffer, "Input 1/2: Phono, -6dB\n"); 3605 break; 3606 case HDSP_RPM_Inp12_Line_0dB: 3607 snd_iprintf(buffer, "Input 1/2: Line, 0dB\n"); 3608 break; 3609 case HDSP_RPM_Inp12_Line_n6dB: 3610 snd_iprintf(buffer, "Input 1/2: Line, -6dB\n"); 3611 break; 3612 default: 3613 snd_iprintf(buffer, "Input 1/2: ???\n"); 3614 } 3615 3616 switch (hdsp->control_register & HDSP_RPM_Inp34) { 3617 case HDSP_RPM_Inp34_Phon_6dB: 3618 snd_iprintf(buffer, "Input 3/4: Phono, 6dB\n"); 3619 break; 3620 case HDSP_RPM_Inp34_Phon_0dB: 3621 snd_iprintf(buffer, "Input 3/4: Phono, 0dB\n"); 3622 break; 3623 case HDSP_RPM_Inp34_Phon_n6dB: 3624 snd_iprintf(buffer, "Input 3/4: Phono, -6dB\n"); 3625 break; 3626 case HDSP_RPM_Inp34_Line_0dB: 3627 snd_iprintf(buffer, "Input 3/4: Line, 0dB\n"); 3628 break; 3629 case HDSP_RPM_Inp34_Line_n6dB: 3630 snd_iprintf(buffer, "Input 3/4: Line, -6dB\n"); 3631 break; 3632 default: 3633 snd_iprintf(buffer, "Input 3/4: ???\n"); 3634 } 3635 3636 } else { 3637 if (hdsp->control_register & HDSP_SPDIFOpticalOut) 3638 snd_iprintf(buffer, "IEC958 output: Coaxial & ADAT1\n"); 3639 else 3640 snd_iprintf(buffer, "IEC958 output: Coaxial only\n"); 3641 3642 if (hdsp->control_register & HDSP_SPDIFProfessional) 3643 snd_iprintf(buffer, "IEC958 quality: Professional\n"); 3644 else 3645 snd_iprintf(buffer, "IEC958 quality: Consumer\n"); 3646 3647 if (hdsp->control_register & HDSP_SPDIFEmphasis) 3648 snd_iprintf(buffer, "IEC958 emphasis: on\n"); 3649 else 3650 snd_iprintf(buffer, "IEC958 emphasis: off\n"); 3651 3652 if (hdsp->control_register & HDSP_SPDIFNonAudio) 3653 snd_iprintf(buffer, "IEC958 NonAudio: on\n"); 3654 else 3655 snd_iprintf(buffer, "IEC958 NonAudio: off\n"); 3656 x = hdsp_spdif_sample_rate(hdsp); 3657 if (x != 0) 3658 snd_iprintf(buffer, "IEC958 sample rate: %d\n", x); 3659 else 3660 snd_iprintf(buffer, "IEC958 sample rate: Error flag set\n"); 3661 } 3662 snd_iprintf(buffer, "\n"); 3663 3664 /* Sync Check */ 3665 x = status & HDSP_Sync0; 3666 if (status & HDSP_Lock0) 3667 snd_iprintf(buffer, "ADAT1: %s\n", x ? "Sync" : "Lock"); 3668 else 3669 snd_iprintf(buffer, "ADAT1: No Lock\n"); 3670 3671 switch (hdsp->io_type) { 3672 case Digiface: 3673 case H9652: 3674 x = status & HDSP_Sync1; 3675 if (status & HDSP_Lock1) 3676 snd_iprintf(buffer, "ADAT2: %s\n", x ? "Sync" : "Lock"); 3677 else 3678 snd_iprintf(buffer, "ADAT2: No Lock\n"); 3679 x = status & HDSP_Sync2; 3680 if (status & HDSP_Lock2) 3681 snd_iprintf(buffer, "ADAT3: %s\n", x ? "Sync" : "Lock"); 3682 else 3683 snd_iprintf(buffer, "ADAT3: No Lock\n"); 3684 break; 3685 default: 3686 /* relax */ 3687 break; 3688 } 3689 3690 x = status & HDSP_SPDIFSync; 3691 if (status & HDSP_SPDIFErrorFlag) 3692 snd_iprintf (buffer, "SPDIF: No Lock\n"); 3693 else 3694 snd_iprintf (buffer, "SPDIF: %s\n", x ? "Sync" : "Lock"); 3695 3696 x = status2 & HDSP_wc_sync; 3697 if (status2 & HDSP_wc_lock) 3698 snd_iprintf (buffer, "Word Clock: %s\n", x ? "Sync" : "Lock"); 3699 else 3700 snd_iprintf (buffer, "Word Clock: No Lock\n"); 3701 3702 x = status & HDSP_TimecodeSync; 3703 if (status & HDSP_TimecodeLock) 3704 snd_iprintf(buffer, "ADAT Sync: %s\n", x ? "Sync" : "Lock"); 3705 else 3706 snd_iprintf(buffer, "ADAT Sync: No Lock\n"); 3707 3708 snd_iprintf(buffer, "\n"); 3709 3710 /* Informations about H9632 specific controls */ 3711 if (hdsp->io_type == H9632) { 3712 char *tmp; 3713 3714 switch (hdsp_ad_gain(hdsp)) { 3715 case 0: 3716 tmp = "-10 dBV"; 3717 break; 3718 case 1: 3719 tmp = "+4 dBu"; 3720 break; 3721 default: 3722 tmp = "Lo Gain"; 3723 break; 3724 } 3725 snd_iprintf(buffer, "AD Gain : %s\n", tmp); 3726 3727 switch (hdsp_da_gain(hdsp)) { 3728 case 0: 3729 tmp = "Hi Gain"; 3730 break; 3731 case 1: 3732 tmp = "+4 dBu"; 3733 break; 3734 default: 3735 tmp = "-10 dBV"; 3736 break; 3737 } 3738 snd_iprintf(buffer, "DA Gain : %s\n", tmp); 3739 3740 switch (hdsp_phone_gain(hdsp)) { 3741 case 0: 3742 tmp = "0 dB"; 3743 break; 3744 case 1: 3745 tmp = "-6 dB"; 3746 break; 3747 default: 3748 tmp = "-12 dB"; 3749 break; 3750 } 3751 snd_iprintf(buffer, "Phones Gain : %s\n", tmp); 3752 3753 snd_iprintf(buffer, "XLR Breakout Cable : %s\n", 3754 hdsp_toggle_setting(hdsp, HDSP_XLRBreakoutCable) ? 3755 "yes" : "no"); 3756 3757 if (hdsp->control_register & HDSP_AnalogExtensionBoard) 3758 snd_iprintf(buffer, "AEB : on (ADAT1 internal)\n"); 3759 else 3760 snd_iprintf(buffer, "AEB : off (ADAT1 external)\n"); 3761 snd_iprintf(buffer, "\n"); 3762 } 3763 3764 } 3765 3766 static void snd_hdsp_proc_init(struct hdsp *hdsp) 3767 { 3768 snd_card_ro_proc_new(hdsp->card, "hdsp", hdsp, snd_hdsp_proc_read); 3769 } 3770 3771 static void snd_hdsp_free_buffers(struct hdsp *hdsp) 3772 { 3773 snd_hammerfall_free_buffer(&hdsp->capture_dma_buf, hdsp->pci); 3774 snd_hammerfall_free_buffer(&hdsp->playback_dma_buf, hdsp->pci); 3775 } 3776 3777 static int snd_hdsp_initialize_memory(struct hdsp *hdsp) 3778 { 3779 unsigned long pb_bus, cb_bus; 3780 3781 if (snd_hammerfall_get_buffer(hdsp->pci, &hdsp->capture_dma_buf, HDSP_DMA_AREA_BYTES) < 0 || 3782 snd_hammerfall_get_buffer(hdsp->pci, &hdsp->playback_dma_buf, HDSP_DMA_AREA_BYTES) < 0) { 3783 if (hdsp->capture_dma_buf.area) 3784 snd_dma_free_pages(&hdsp->capture_dma_buf); 3785 dev_err(hdsp->card->dev, 3786 "%s: no buffers available\n", hdsp->card_name); 3787 return -ENOMEM; 3788 } 3789 3790 /* Align to bus-space 64K boundary */ 3791 3792 cb_bus = ALIGN(hdsp->capture_dma_buf.addr, 0x10000ul); 3793 pb_bus = ALIGN(hdsp->playback_dma_buf.addr, 0x10000ul); 3794 3795 /* Tell the card where it is */ 3796 3797 hdsp_write(hdsp, HDSP_inputBufferAddress, cb_bus); 3798 hdsp_write(hdsp, HDSP_outputBufferAddress, pb_bus); 3799 3800 hdsp->capture_buffer = hdsp->capture_dma_buf.area + (cb_bus - hdsp->capture_dma_buf.addr); 3801 hdsp->playback_buffer = hdsp->playback_dma_buf.area + (pb_bus - hdsp->playback_dma_buf.addr); 3802 3803 return 0; 3804 } 3805 3806 static int snd_hdsp_set_defaults(struct hdsp *hdsp) 3807 { 3808 unsigned int i; 3809 3810 /* ASSUMPTION: hdsp->lock is either held, or 3811 there is no need to hold it (e.g. during module 3812 initialization). 3813 */ 3814 3815 /* set defaults: 3816 3817 SPDIF Input via Coax 3818 Master clock mode 3819 maximum latency (7 => 2^7 = 8192 samples, 64Kbyte buffer, 3820 which implies 2 4096 sample, 32Kbyte periods). 3821 Enable line out. 3822 */ 3823 3824 hdsp->control_register = HDSP_ClockModeMaster | 3825 HDSP_SPDIFInputCoaxial | 3826 hdsp_encode_latency(7) | 3827 HDSP_LineOut; 3828 3829 3830 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 3831 3832 #ifdef SNDRV_BIG_ENDIAN 3833 hdsp->control2_register = HDSP_BIGENDIAN_MODE; 3834 #else 3835 hdsp->control2_register = 0; 3836 #endif 3837 if (hdsp->io_type == H9652) 3838 snd_hdsp_9652_enable_mixer (hdsp); 3839 else 3840 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register); 3841 3842 hdsp_reset_hw_pointer(hdsp); 3843 hdsp_compute_period_size(hdsp); 3844 3845 /* silence everything */ 3846 3847 for (i = 0; i < HDSP_MATRIX_MIXER_SIZE; ++i) 3848 hdsp->mixer_matrix[i] = MINUS_INFINITY_GAIN; 3849 3850 for (i = 0; i < ((hdsp->io_type == H9652 || hdsp->io_type == H9632) ? 1352 : HDSP_MATRIX_MIXER_SIZE); ++i) { 3851 if (hdsp_write_gain (hdsp, i, MINUS_INFINITY_GAIN)) 3852 return -EIO; 3853 } 3854 3855 /* H9632 specific defaults */ 3856 if (hdsp->io_type == H9632) { 3857 hdsp->control_register |= (HDSP_DAGainPlus4dBu | HDSP_ADGainPlus4dBu | HDSP_PhoneGain0dB); 3858 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 3859 } 3860 3861 /* set a default rate so that the channel map is set up. 3862 */ 3863 3864 hdsp_set_rate(hdsp, 48000, 1); 3865 3866 return 0; 3867 } 3868 3869 static void hdsp_midi_work(struct work_struct *work) 3870 { 3871 struct hdsp *hdsp = container_of(work, struct hdsp, midi_work); 3872 3873 if (hdsp->midi[0].pending) 3874 snd_hdsp_midi_input_read (&hdsp->midi[0]); 3875 if (hdsp->midi[1].pending) 3876 snd_hdsp_midi_input_read (&hdsp->midi[1]); 3877 } 3878 3879 static irqreturn_t snd_hdsp_interrupt(int irq, void *dev_id) 3880 { 3881 struct hdsp *hdsp = (struct hdsp *) dev_id; 3882 unsigned int status; 3883 int audio; 3884 int midi0; 3885 int midi1; 3886 unsigned int midi0status; 3887 unsigned int midi1status; 3888 int schedule = 0; 3889 3890 status = hdsp_read(hdsp, HDSP_statusRegister); 3891 3892 audio = status & HDSP_audioIRQPending; 3893 midi0 = status & HDSP_midi0IRQPending; 3894 midi1 = status & HDSP_midi1IRQPending; 3895 3896 if (!audio && !midi0 && !midi1) 3897 return IRQ_NONE; 3898 3899 hdsp_write(hdsp, HDSP_interruptConfirmation, 0); 3900 3901 midi0status = hdsp_read (hdsp, HDSP_midiStatusIn0) & 0xff; 3902 midi1status = hdsp_read (hdsp, HDSP_midiStatusIn1) & 0xff; 3903 3904 if (!(hdsp->state & HDSP_InitializationComplete)) 3905 return IRQ_HANDLED; 3906 3907 if (audio) { 3908 if (hdsp->capture_substream) 3909 snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream); 3910 3911 if (hdsp->playback_substream) 3912 snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream); 3913 } 3914 3915 if (midi0 && midi0status) { 3916 if (hdsp->use_midi_work) { 3917 /* we disable interrupts for this input until processing is done */ 3918 hdsp->control_register &= ~HDSP_Midi0InterruptEnable; 3919 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 3920 hdsp->midi[0].pending = 1; 3921 schedule = 1; 3922 } else { 3923 snd_hdsp_midi_input_read (&hdsp->midi[0]); 3924 } 3925 } 3926 if (hdsp->io_type != Multiface && hdsp->io_type != RPM && hdsp->io_type != H9632 && midi1 && midi1status) { 3927 if (hdsp->use_midi_work) { 3928 /* we disable interrupts for this input until processing is done */ 3929 hdsp->control_register &= ~HDSP_Midi1InterruptEnable; 3930 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 3931 hdsp->midi[1].pending = 1; 3932 schedule = 1; 3933 } else { 3934 snd_hdsp_midi_input_read (&hdsp->midi[1]); 3935 } 3936 } 3937 if (hdsp->use_midi_work && schedule) 3938 queue_work(system_highpri_wq, &hdsp->midi_work); 3939 return IRQ_HANDLED; 3940 } 3941 3942 static snd_pcm_uframes_t snd_hdsp_hw_pointer(struct snd_pcm_substream *substream) 3943 { 3944 struct hdsp *hdsp = snd_pcm_substream_chip(substream); 3945 return hdsp_hw_pointer(hdsp); 3946 } 3947 3948 static char *hdsp_channel_buffer_location(struct hdsp *hdsp, 3949 int stream, 3950 int channel) 3951 3952 { 3953 int mapped_channel; 3954 3955 if (snd_BUG_ON(channel < 0 || channel >= hdsp->max_channels)) 3956 return NULL; 3957 3958 mapped_channel = hdsp->channel_map[channel]; 3959 if (mapped_channel < 0) 3960 return NULL; 3961 3962 if (stream == SNDRV_PCM_STREAM_CAPTURE) 3963 return hdsp->capture_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES); 3964 else 3965 return hdsp->playback_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES); 3966 } 3967 3968 static int snd_hdsp_playback_copy(struct snd_pcm_substream *substream, 3969 int channel, unsigned long pos, 3970 void __user *src, unsigned long count) 3971 { 3972 struct hdsp *hdsp = snd_pcm_substream_chip(substream); 3973 char *channel_buf; 3974 3975 if (snd_BUG_ON(pos + count > HDSP_CHANNEL_BUFFER_BYTES)) 3976 return -EINVAL; 3977 3978 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel); 3979 if (snd_BUG_ON(!channel_buf)) 3980 return -EIO; 3981 if (copy_from_user(channel_buf + pos, src, count)) 3982 return -EFAULT; 3983 return 0; 3984 } 3985 3986 static int snd_hdsp_playback_copy_kernel(struct snd_pcm_substream *substream, 3987 int channel, unsigned long pos, 3988 void *src, unsigned long count) 3989 { 3990 struct hdsp *hdsp = snd_pcm_substream_chip(substream); 3991 char *channel_buf; 3992 3993 channel_buf = hdsp_channel_buffer_location(hdsp, substream->pstr->stream, channel); 3994 if (snd_BUG_ON(!channel_buf)) 3995 return -EIO; 3996 memcpy(channel_buf + pos, src, count); 3997 return 0; 3998 } 3999 4000 static int snd_hdsp_capture_copy(struct snd_pcm_substream *substream, 4001 int channel, unsigned long pos, 4002 void __user *dst, unsigned long count) 4003 { 4004 struct hdsp *hdsp = snd_pcm_substream_chip(substream); 4005 char *channel_buf; 4006 4007 if (snd_BUG_ON(pos + count > HDSP_CHANNEL_BUFFER_BYTES)) 4008 return -EINVAL; 4009 4010 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel); 4011 if (snd_BUG_ON(!channel_buf)) 4012 return -EIO; 4013 if (copy_to_user(dst, channel_buf + pos, count)) 4014 return -EFAULT; 4015 return 0; 4016 } 4017 4018 static int snd_hdsp_capture_copy_kernel(struct snd_pcm_substream *substream, 4019 int channel, unsigned long pos, 4020 void *dst, unsigned long count) 4021 { 4022 struct hdsp *hdsp = snd_pcm_substream_chip(substream); 4023 char *channel_buf; 4024 4025 channel_buf = hdsp_channel_buffer_location(hdsp, substream->pstr->stream, channel); 4026 if (snd_BUG_ON(!channel_buf)) 4027 return -EIO; 4028 memcpy(dst, channel_buf + pos, count); 4029 return 0; 4030 } 4031 4032 static int snd_hdsp_hw_silence(struct snd_pcm_substream *substream, 4033 int channel, unsigned long pos, 4034 unsigned long count) 4035 { 4036 struct hdsp *hdsp = snd_pcm_substream_chip(substream); 4037 char *channel_buf; 4038 4039 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel); 4040 if (snd_BUG_ON(!channel_buf)) 4041 return -EIO; 4042 memset(channel_buf + pos, 0, count); 4043 return 0; 4044 } 4045 4046 static int snd_hdsp_reset(struct snd_pcm_substream *substream) 4047 { 4048 struct snd_pcm_runtime *runtime = substream->runtime; 4049 struct hdsp *hdsp = snd_pcm_substream_chip(substream); 4050 struct snd_pcm_substream *other; 4051 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 4052 other = hdsp->capture_substream; 4053 else 4054 other = hdsp->playback_substream; 4055 if (hdsp->running) 4056 runtime->status->hw_ptr = hdsp_hw_pointer(hdsp); 4057 else 4058 runtime->status->hw_ptr = 0; 4059 if (other) { 4060 struct snd_pcm_substream *s; 4061 struct snd_pcm_runtime *oruntime = other->runtime; 4062 snd_pcm_group_for_each_entry(s, substream) { 4063 if (s == other) { 4064 oruntime->status->hw_ptr = runtime->status->hw_ptr; 4065 break; 4066 } 4067 } 4068 } 4069 return 0; 4070 } 4071 4072 static int snd_hdsp_hw_params(struct snd_pcm_substream *substream, 4073 struct snd_pcm_hw_params *params) 4074 { 4075 struct hdsp *hdsp = snd_pcm_substream_chip(substream); 4076 int err; 4077 pid_t this_pid; 4078 pid_t other_pid; 4079 4080 if (hdsp_check_for_iobox (hdsp)) 4081 return -EIO; 4082 4083 if (hdsp_check_for_firmware(hdsp, 1)) 4084 return -EIO; 4085 4086 spin_lock_irq(&hdsp->lock); 4087 4088 if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) { 4089 hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis); 4090 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= hdsp->creg_spdif_stream); 4091 this_pid = hdsp->playback_pid; 4092 other_pid = hdsp->capture_pid; 4093 } else { 4094 this_pid = hdsp->capture_pid; 4095 other_pid = hdsp->playback_pid; 4096 } 4097 4098 if ((other_pid > 0) && (this_pid != other_pid)) { 4099 4100 /* The other stream is open, and not by the same 4101 task as this one. Make sure that the parameters 4102 that matter are the same. 4103 */ 4104 4105 if (params_rate(params) != hdsp->system_sample_rate) { 4106 spin_unlock_irq(&hdsp->lock); 4107 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE); 4108 return -EBUSY; 4109 } 4110 4111 if (params_period_size(params) != hdsp->period_bytes / 4) { 4112 spin_unlock_irq(&hdsp->lock); 4113 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE); 4114 return -EBUSY; 4115 } 4116 4117 /* We're fine. */ 4118 4119 spin_unlock_irq(&hdsp->lock); 4120 return 0; 4121 4122 } else { 4123 spin_unlock_irq(&hdsp->lock); 4124 } 4125 4126 /* how to make sure that the rate matches an externally-set one ? 4127 */ 4128 4129 spin_lock_irq(&hdsp->lock); 4130 if (! hdsp->clock_source_locked) { 4131 err = hdsp_set_rate(hdsp, params_rate(params), 0); 4132 if (err < 0) { 4133 spin_unlock_irq(&hdsp->lock); 4134 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE); 4135 return err; 4136 } 4137 } 4138 spin_unlock_irq(&hdsp->lock); 4139 4140 err = hdsp_set_interrupt_interval(hdsp, params_period_size(params)); 4141 if (err < 0) { 4142 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE); 4143 return err; 4144 } 4145 4146 return 0; 4147 } 4148 4149 static int snd_hdsp_channel_info(struct snd_pcm_substream *substream, 4150 struct snd_pcm_channel_info *info) 4151 { 4152 struct hdsp *hdsp = snd_pcm_substream_chip(substream); 4153 unsigned int channel = info->channel; 4154 4155 if (snd_BUG_ON(channel >= hdsp->max_channels)) 4156 return -EINVAL; 4157 channel = array_index_nospec(channel, hdsp->max_channels); 4158 4159 if (hdsp->channel_map[channel] < 0) 4160 return -EINVAL; 4161 4162 info->offset = hdsp->channel_map[channel] * HDSP_CHANNEL_BUFFER_BYTES; 4163 info->first = 0; 4164 info->step = 32; 4165 return 0; 4166 } 4167 4168 static int snd_hdsp_ioctl(struct snd_pcm_substream *substream, 4169 unsigned int cmd, void *arg) 4170 { 4171 switch (cmd) { 4172 case SNDRV_PCM_IOCTL1_RESET: 4173 return snd_hdsp_reset(substream); 4174 case SNDRV_PCM_IOCTL1_CHANNEL_INFO: 4175 return snd_hdsp_channel_info(substream, arg); 4176 default: 4177 break; 4178 } 4179 4180 return snd_pcm_lib_ioctl(substream, cmd, arg); 4181 } 4182 4183 static int snd_hdsp_trigger(struct snd_pcm_substream *substream, int cmd) 4184 { 4185 struct hdsp *hdsp = snd_pcm_substream_chip(substream); 4186 struct snd_pcm_substream *other; 4187 int running; 4188 4189 if (hdsp_check_for_iobox (hdsp)) 4190 return -EIO; 4191 4192 if (hdsp_check_for_firmware(hdsp, 0)) /* no auto-loading in trigger */ 4193 return -EIO; 4194 4195 spin_lock(&hdsp->lock); 4196 running = hdsp->running; 4197 switch (cmd) { 4198 case SNDRV_PCM_TRIGGER_START: 4199 running |= 1 << substream->stream; 4200 break; 4201 case SNDRV_PCM_TRIGGER_STOP: 4202 running &= ~(1 << substream->stream); 4203 break; 4204 default: 4205 snd_BUG(); 4206 spin_unlock(&hdsp->lock); 4207 return -EINVAL; 4208 } 4209 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 4210 other = hdsp->capture_substream; 4211 else 4212 other = hdsp->playback_substream; 4213 4214 if (other) { 4215 struct snd_pcm_substream *s; 4216 snd_pcm_group_for_each_entry(s, substream) { 4217 if (s == other) { 4218 snd_pcm_trigger_done(s, substream); 4219 if (cmd == SNDRV_PCM_TRIGGER_START) 4220 running |= 1 << s->stream; 4221 else 4222 running &= ~(1 << s->stream); 4223 goto _ok; 4224 } 4225 } 4226 if (cmd == SNDRV_PCM_TRIGGER_START) { 4227 if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK)) && 4228 substream->stream == SNDRV_PCM_STREAM_CAPTURE) 4229 hdsp_silence_playback(hdsp); 4230 } else { 4231 if (running && 4232 substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 4233 hdsp_silence_playback(hdsp); 4234 } 4235 } else { 4236 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 4237 hdsp_silence_playback(hdsp); 4238 } 4239 _ok: 4240 snd_pcm_trigger_done(substream, substream); 4241 if (!hdsp->running && running) 4242 hdsp_start_audio(hdsp); 4243 else if (hdsp->running && !running) 4244 hdsp_stop_audio(hdsp); 4245 hdsp->running = running; 4246 spin_unlock(&hdsp->lock); 4247 4248 return 0; 4249 } 4250 4251 static int snd_hdsp_prepare(struct snd_pcm_substream *substream) 4252 { 4253 struct hdsp *hdsp = snd_pcm_substream_chip(substream); 4254 int result = 0; 4255 4256 if (hdsp_check_for_iobox (hdsp)) 4257 return -EIO; 4258 4259 if (hdsp_check_for_firmware(hdsp, 1)) 4260 return -EIO; 4261 4262 spin_lock_irq(&hdsp->lock); 4263 if (!hdsp->running) 4264 hdsp_reset_hw_pointer(hdsp); 4265 spin_unlock_irq(&hdsp->lock); 4266 return result; 4267 } 4268 4269 static const struct snd_pcm_hardware snd_hdsp_playback_subinfo = 4270 { 4271 .info = (SNDRV_PCM_INFO_MMAP | 4272 SNDRV_PCM_INFO_MMAP_VALID | 4273 SNDRV_PCM_INFO_NONINTERLEAVED | 4274 SNDRV_PCM_INFO_SYNC_START | 4275 SNDRV_PCM_INFO_DOUBLE), 4276 #ifdef SNDRV_BIG_ENDIAN 4277 .formats = SNDRV_PCM_FMTBIT_S32_BE, 4278 #else 4279 .formats = SNDRV_PCM_FMTBIT_S32_LE, 4280 #endif 4281 .rates = (SNDRV_PCM_RATE_32000 | 4282 SNDRV_PCM_RATE_44100 | 4283 SNDRV_PCM_RATE_48000 | 4284 SNDRV_PCM_RATE_64000 | 4285 SNDRV_PCM_RATE_88200 | 4286 SNDRV_PCM_RATE_96000), 4287 .rate_min = 32000, 4288 .rate_max = 96000, 4289 .channels_min = 6, 4290 .channels_max = HDSP_MAX_CHANNELS, 4291 .buffer_bytes_max = HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS, 4292 .period_bytes_min = (64 * 4) * 10, 4293 .period_bytes_max = (8192 * 4) * HDSP_MAX_CHANNELS, 4294 .periods_min = 2, 4295 .periods_max = 2, 4296 .fifo_size = 0 4297 }; 4298 4299 static const struct snd_pcm_hardware snd_hdsp_capture_subinfo = 4300 { 4301 .info = (SNDRV_PCM_INFO_MMAP | 4302 SNDRV_PCM_INFO_MMAP_VALID | 4303 SNDRV_PCM_INFO_NONINTERLEAVED | 4304 SNDRV_PCM_INFO_SYNC_START), 4305 #ifdef SNDRV_BIG_ENDIAN 4306 .formats = SNDRV_PCM_FMTBIT_S32_BE, 4307 #else 4308 .formats = SNDRV_PCM_FMTBIT_S32_LE, 4309 #endif 4310 .rates = (SNDRV_PCM_RATE_32000 | 4311 SNDRV_PCM_RATE_44100 | 4312 SNDRV_PCM_RATE_48000 | 4313 SNDRV_PCM_RATE_64000 | 4314 SNDRV_PCM_RATE_88200 | 4315 SNDRV_PCM_RATE_96000), 4316 .rate_min = 32000, 4317 .rate_max = 96000, 4318 .channels_min = 5, 4319 .channels_max = HDSP_MAX_CHANNELS, 4320 .buffer_bytes_max = HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS, 4321 .period_bytes_min = (64 * 4) * 10, 4322 .period_bytes_max = (8192 * 4) * HDSP_MAX_CHANNELS, 4323 .periods_min = 2, 4324 .periods_max = 2, 4325 .fifo_size = 0 4326 }; 4327 4328 static const unsigned int hdsp_period_sizes[] = { 64, 128, 256, 512, 1024, 2048, 4096, 8192 }; 4329 4330 static const struct snd_pcm_hw_constraint_list hdsp_hw_constraints_period_sizes = { 4331 .count = ARRAY_SIZE(hdsp_period_sizes), 4332 .list = hdsp_period_sizes, 4333 .mask = 0 4334 }; 4335 4336 static const unsigned int hdsp_9632_sample_rates[] = { 32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000 }; 4337 4338 static const struct snd_pcm_hw_constraint_list hdsp_hw_constraints_9632_sample_rates = { 4339 .count = ARRAY_SIZE(hdsp_9632_sample_rates), 4340 .list = hdsp_9632_sample_rates, 4341 .mask = 0 4342 }; 4343 4344 static int snd_hdsp_hw_rule_in_channels(struct snd_pcm_hw_params *params, 4345 struct snd_pcm_hw_rule *rule) 4346 { 4347 struct hdsp *hdsp = rule->private; 4348 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 4349 if (hdsp->io_type == H9632) { 4350 unsigned int list[3]; 4351 list[0] = hdsp->qs_in_channels; 4352 list[1] = hdsp->ds_in_channels; 4353 list[2] = hdsp->ss_in_channels; 4354 return snd_interval_list(c, 3, list, 0); 4355 } else { 4356 unsigned int list[2]; 4357 list[0] = hdsp->ds_in_channels; 4358 list[1] = hdsp->ss_in_channels; 4359 return snd_interval_list(c, 2, list, 0); 4360 } 4361 } 4362 4363 static int snd_hdsp_hw_rule_out_channels(struct snd_pcm_hw_params *params, 4364 struct snd_pcm_hw_rule *rule) 4365 { 4366 unsigned int list[3]; 4367 struct hdsp *hdsp = rule->private; 4368 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 4369 if (hdsp->io_type == H9632) { 4370 list[0] = hdsp->qs_out_channels; 4371 list[1] = hdsp->ds_out_channels; 4372 list[2] = hdsp->ss_out_channels; 4373 return snd_interval_list(c, 3, list, 0); 4374 } else { 4375 list[0] = hdsp->ds_out_channels; 4376 list[1] = hdsp->ss_out_channels; 4377 } 4378 return snd_interval_list(c, 2, list, 0); 4379 } 4380 4381 static int snd_hdsp_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params, 4382 struct snd_pcm_hw_rule *rule) 4383 { 4384 struct hdsp *hdsp = rule->private; 4385 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 4386 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 4387 if (r->min > 96000 && hdsp->io_type == H9632) { 4388 struct snd_interval t = { 4389 .min = hdsp->qs_in_channels, 4390 .max = hdsp->qs_in_channels, 4391 .integer = 1, 4392 }; 4393 return snd_interval_refine(c, &t); 4394 } else if (r->min > 48000 && r->max <= 96000) { 4395 struct snd_interval t = { 4396 .min = hdsp->ds_in_channels, 4397 .max = hdsp->ds_in_channels, 4398 .integer = 1, 4399 }; 4400 return snd_interval_refine(c, &t); 4401 } else if (r->max < 64000) { 4402 struct snd_interval t = { 4403 .min = hdsp->ss_in_channels, 4404 .max = hdsp->ss_in_channels, 4405 .integer = 1, 4406 }; 4407 return snd_interval_refine(c, &t); 4408 } 4409 return 0; 4410 } 4411 4412 static int snd_hdsp_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params, 4413 struct snd_pcm_hw_rule *rule) 4414 { 4415 struct hdsp *hdsp = rule->private; 4416 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 4417 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 4418 if (r->min > 96000 && hdsp->io_type == H9632) { 4419 struct snd_interval t = { 4420 .min = hdsp->qs_out_channels, 4421 .max = hdsp->qs_out_channels, 4422 .integer = 1, 4423 }; 4424 return snd_interval_refine(c, &t); 4425 } else if (r->min > 48000 && r->max <= 96000) { 4426 struct snd_interval t = { 4427 .min = hdsp->ds_out_channels, 4428 .max = hdsp->ds_out_channels, 4429 .integer = 1, 4430 }; 4431 return snd_interval_refine(c, &t); 4432 } else if (r->max < 64000) { 4433 struct snd_interval t = { 4434 .min = hdsp->ss_out_channels, 4435 .max = hdsp->ss_out_channels, 4436 .integer = 1, 4437 }; 4438 return snd_interval_refine(c, &t); 4439 } 4440 return 0; 4441 } 4442 4443 static int snd_hdsp_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params, 4444 struct snd_pcm_hw_rule *rule) 4445 { 4446 struct hdsp *hdsp = rule->private; 4447 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 4448 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 4449 if (c->min >= hdsp->ss_out_channels) { 4450 struct snd_interval t = { 4451 .min = 32000, 4452 .max = 48000, 4453 .integer = 1, 4454 }; 4455 return snd_interval_refine(r, &t); 4456 } else if (c->max <= hdsp->qs_out_channels && hdsp->io_type == H9632) { 4457 struct snd_interval t = { 4458 .min = 128000, 4459 .max = 192000, 4460 .integer = 1, 4461 }; 4462 return snd_interval_refine(r, &t); 4463 } else if (c->max <= hdsp->ds_out_channels) { 4464 struct snd_interval t = { 4465 .min = 64000, 4466 .max = 96000, 4467 .integer = 1, 4468 }; 4469 return snd_interval_refine(r, &t); 4470 } 4471 return 0; 4472 } 4473 4474 static int snd_hdsp_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params, 4475 struct snd_pcm_hw_rule *rule) 4476 { 4477 struct hdsp *hdsp = rule->private; 4478 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 4479 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 4480 if (c->min >= hdsp->ss_in_channels) { 4481 struct snd_interval t = { 4482 .min = 32000, 4483 .max = 48000, 4484 .integer = 1, 4485 }; 4486 return snd_interval_refine(r, &t); 4487 } else if (c->max <= hdsp->qs_in_channels && hdsp->io_type == H9632) { 4488 struct snd_interval t = { 4489 .min = 128000, 4490 .max = 192000, 4491 .integer = 1, 4492 }; 4493 return snd_interval_refine(r, &t); 4494 } else if (c->max <= hdsp->ds_in_channels) { 4495 struct snd_interval t = { 4496 .min = 64000, 4497 .max = 96000, 4498 .integer = 1, 4499 }; 4500 return snd_interval_refine(r, &t); 4501 } 4502 return 0; 4503 } 4504 4505 static int snd_hdsp_playback_open(struct snd_pcm_substream *substream) 4506 { 4507 struct hdsp *hdsp = snd_pcm_substream_chip(substream); 4508 struct snd_pcm_runtime *runtime = substream->runtime; 4509 4510 if (hdsp_check_for_iobox (hdsp)) 4511 return -EIO; 4512 4513 if (hdsp_check_for_firmware(hdsp, 1)) 4514 return -EIO; 4515 4516 spin_lock_irq(&hdsp->lock); 4517 4518 snd_pcm_set_sync(substream); 4519 4520 runtime->hw = snd_hdsp_playback_subinfo; 4521 runtime->dma_area = hdsp->playback_buffer; 4522 runtime->dma_bytes = HDSP_DMA_AREA_BYTES; 4523 4524 hdsp->playback_pid = current->pid; 4525 hdsp->playback_substream = substream; 4526 4527 spin_unlock_irq(&hdsp->lock); 4528 4529 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24); 4530 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes); 4531 if (hdsp->clock_source_locked) { 4532 runtime->hw.rate_min = runtime->hw.rate_max = hdsp->system_sample_rate; 4533 } else if (hdsp->io_type == H9632) { 4534 runtime->hw.rate_max = 192000; 4535 runtime->hw.rates = SNDRV_PCM_RATE_KNOT; 4536 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates); 4537 } 4538 if (hdsp->io_type == H9632) { 4539 runtime->hw.channels_min = hdsp->qs_out_channels; 4540 runtime->hw.channels_max = hdsp->ss_out_channels; 4541 } 4542 4543 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 4544 snd_hdsp_hw_rule_out_channels, hdsp, 4545 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 4546 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 4547 snd_hdsp_hw_rule_out_channels_rate, hdsp, 4548 SNDRV_PCM_HW_PARAM_RATE, -1); 4549 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 4550 snd_hdsp_hw_rule_rate_out_channels, hdsp, 4551 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 4552 4553 if (RPM != hdsp->io_type) { 4554 hdsp->creg_spdif_stream = hdsp->creg_spdif; 4555 hdsp->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE; 4556 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE | 4557 SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id); 4558 } 4559 return 0; 4560 } 4561 4562 static int snd_hdsp_playback_release(struct snd_pcm_substream *substream) 4563 { 4564 struct hdsp *hdsp = snd_pcm_substream_chip(substream); 4565 4566 spin_lock_irq(&hdsp->lock); 4567 4568 hdsp->playback_pid = -1; 4569 hdsp->playback_substream = NULL; 4570 4571 spin_unlock_irq(&hdsp->lock); 4572 4573 if (RPM != hdsp->io_type) { 4574 hdsp->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE; 4575 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE | 4576 SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id); 4577 } 4578 return 0; 4579 } 4580 4581 4582 static int snd_hdsp_capture_open(struct snd_pcm_substream *substream) 4583 { 4584 struct hdsp *hdsp = snd_pcm_substream_chip(substream); 4585 struct snd_pcm_runtime *runtime = substream->runtime; 4586 4587 if (hdsp_check_for_iobox (hdsp)) 4588 return -EIO; 4589 4590 if (hdsp_check_for_firmware(hdsp, 1)) 4591 return -EIO; 4592 4593 spin_lock_irq(&hdsp->lock); 4594 4595 snd_pcm_set_sync(substream); 4596 4597 runtime->hw = snd_hdsp_capture_subinfo; 4598 runtime->dma_area = hdsp->capture_buffer; 4599 runtime->dma_bytes = HDSP_DMA_AREA_BYTES; 4600 4601 hdsp->capture_pid = current->pid; 4602 hdsp->capture_substream = substream; 4603 4604 spin_unlock_irq(&hdsp->lock); 4605 4606 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24); 4607 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes); 4608 if (hdsp->io_type == H9632) { 4609 runtime->hw.channels_min = hdsp->qs_in_channels; 4610 runtime->hw.channels_max = hdsp->ss_in_channels; 4611 runtime->hw.rate_max = 192000; 4612 runtime->hw.rates = SNDRV_PCM_RATE_KNOT; 4613 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates); 4614 } 4615 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 4616 snd_hdsp_hw_rule_in_channels, hdsp, 4617 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 4618 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 4619 snd_hdsp_hw_rule_in_channels_rate, hdsp, 4620 SNDRV_PCM_HW_PARAM_RATE, -1); 4621 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 4622 snd_hdsp_hw_rule_rate_in_channels, hdsp, 4623 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 4624 return 0; 4625 } 4626 4627 static int snd_hdsp_capture_release(struct snd_pcm_substream *substream) 4628 { 4629 struct hdsp *hdsp = snd_pcm_substream_chip(substream); 4630 4631 spin_lock_irq(&hdsp->lock); 4632 4633 hdsp->capture_pid = -1; 4634 hdsp->capture_substream = NULL; 4635 4636 spin_unlock_irq(&hdsp->lock); 4637 return 0; 4638 } 4639 4640 /* helper functions for copying meter values */ 4641 static inline int copy_u32_le(void __user *dest, void __iomem *src) 4642 { 4643 u32 val = readl(src); 4644 return copy_to_user(dest, &val, 4); 4645 } 4646 4647 static inline int copy_u64_le(void __user *dest, void __iomem *src_low, void __iomem *src_high) 4648 { 4649 u32 rms_low, rms_high; 4650 u64 rms; 4651 rms_low = readl(src_low); 4652 rms_high = readl(src_high); 4653 rms = ((u64)rms_high << 32) | rms_low; 4654 return copy_to_user(dest, &rms, 8); 4655 } 4656 4657 static inline int copy_u48_le(void __user *dest, void __iomem *src_low, void __iomem *src_high) 4658 { 4659 u32 rms_low, rms_high; 4660 u64 rms; 4661 rms_low = readl(src_low) & 0xffffff00; 4662 rms_high = readl(src_high) & 0xffffff00; 4663 rms = ((u64)rms_high << 32) | rms_low; 4664 return copy_to_user(dest, &rms, 8); 4665 } 4666 4667 static int hdsp_9652_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms) 4668 { 4669 int doublespeed = 0; 4670 int i, j, channels, ofs; 4671 4672 if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus) 4673 doublespeed = 1; 4674 channels = doublespeed ? 14 : 26; 4675 for (i = 0, j = 0; i < 26; ++i) { 4676 if (doublespeed && (i & 4)) 4677 continue; 4678 ofs = HDSP_9652_peakBase - j * 4; 4679 if (copy_u32_le(&peak_rms->input_peaks[i], hdsp->iobase + ofs)) 4680 return -EFAULT; 4681 ofs -= channels * 4; 4682 if (copy_u32_le(&peak_rms->playback_peaks[i], hdsp->iobase + ofs)) 4683 return -EFAULT; 4684 ofs -= channels * 4; 4685 if (copy_u32_le(&peak_rms->output_peaks[i], hdsp->iobase + ofs)) 4686 return -EFAULT; 4687 ofs = HDSP_9652_rmsBase + j * 8; 4688 if (copy_u48_le(&peak_rms->input_rms[i], hdsp->iobase + ofs, 4689 hdsp->iobase + ofs + 4)) 4690 return -EFAULT; 4691 ofs += channels * 8; 4692 if (copy_u48_le(&peak_rms->playback_rms[i], hdsp->iobase + ofs, 4693 hdsp->iobase + ofs + 4)) 4694 return -EFAULT; 4695 ofs += channels * 8; 4696 if (copy_u48_le(&peak_rms->output_rms[i], hdsp->iobase + ofs, 4697 hdsp->iobase + ofs + 4)) 4698 return -EFAULT; 4699 j++; 4700 } 4701 return 0; 4702 } 4703 4704 static int hdsp_9632_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms) 4705 { 4706 int i, j; 4707 struct hdsp_9632_meters __iomem *m; 4708 int doublespeed = 0; 4709 4710 if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus) 4711 doublespeed = 1; 4712 m = (struct hdsp_9632_meters __iomem *)(hdsp->iobase+HDSP_9632_metersBase); 4713 for (i = 0, j = 0; i < 16; ++i, ++j) { 4714 if (copy_u32_le(&peak_rms->input_peaks[i], &m->input_peak[j])) 4715 return -EFAULT; 4716 if (copy_u32_le(&peak_rms->playback_peaks[i], &m->playback_peak[j])) 4717 return -EFAULT; 4718 if (copy_u32_le(&peak_rms->output_peaks[i], &m->output_peak[j])) 4719 return -EFAULT; 4720 if (copy_u64_le(&peak_rms->input_rms[i], &m->input_rms_low[j], 4721 &m->input_rms_high[j])) 4722 return -EFAULT; 4723 if (copy_u64_le(&peak_rms->playback_rms[i], &m->playback_rms_low[j], 4724 &m->playback_rms_high[j])) 4725 return -EFAULT; 4726 if (copy_u64_le(&peak_rms->output_rms[i], &m->output_rms_low[j], 4727 &m->output_rms_high[j])) 4728 return -EFAULT; 4729 if (doublespeed && i == 3) i += 4; 4730 } 4731 return 0; 4732 } 4733 4734 static int hdsp_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms) 4735 { 4736 int i; 4737 4738 for (i = 0; i < 26; i++) { 4739 if (copy_u32_le(&peak_rms->playback_peaks[i], 4740 hdsp->iobase + HDSP_playbackPeakLevel + i * 4)) 4741 return -EFAULT; 4742 if (copy_u32_le(&peak_rms->input_peaks[i], 4743 hdsp->iobase + HDSP_inputPeakLevel + i * 4)) 4744 return -EFAULT; 4745 } 4746 for (i = 0; i < 28; i++) { 4747 if (copy_u32_le(&peak_rms->output_peaks[i], 4748 hdsp->iobase + HDSP_outputPeakLevel + i * 4)) 4749 return -EFAULT; 4750 } 4751 for (i = 0; i < 26; ++i) { 4752 if (copy_u64_le(&peak_rms->playback_rms[i], 4753 hdsp->iobase + HDSP_playbackRmsLevel + i * 8 + 4, 4754 hdsp->iobase + HDSP_playbackRmsLevel + i * 8)) 4755 return -EFAULT; 4756 if (copy_u64_le(&peak_rms->input_rms[i], 4757 hdsp->iobase + HDSP_inputRmsLevel + i * 8 + 4, 4758 hdsp->iobase + HDSP_inputRmsLevel + i * 8)) 4759 return -EFAULT; 4760 } 4761 return 0; 4762 } 4763 4764 static int snd_hdsp_hwdep_ioctl(struct snd_hwdep *hw, struct file *file, unsigned int cmd, unsigned long arg) 4765 { 4766 struct hdsp *hdsp = hw->private_data; 4767 void __user *argp = (void __user *)arg; 4768 int err; 4769 4770 switch (cmd) { 4771 case SNDRV_HDSP_IOCTL_GET_PEAK_RMS: { 4772 struct hdsp_peak_rms __user *peak_rms = (struct hdsp_peak_rms __user *)arg; 4773 4774 err = hdsp_check_for_iobox(hdsp); 4775 if (err < 0) 4776 return err; 4777 4778 err = hdsp_check_for_firmware(hdsp, 1); 4779 if (err < 0) 4780 return err; 4781 4782 if (!(hdsp->state & HDSP_FirmwareLoaded)) { 4783 dev_err(hdsp->card->dev, 4784 "firmware needs to be uploaded to the card.\n"); 4785 return -EINVAL; 4786 } 4787 4788 switch (hdsp->io_type) { 4789 case H9652: 4790 return hdsp_9652_get_peak(hdsp, peak_rms); 4791 case H9632: 4792 return hdsp_9632_get_peak(hdsp, peak_rms); 4793 default: 4794 return hdsp_get_peak(hdsp, peak_rms); 4795 } 4796 } 4797 case SNDRV_HDSP_IOCTL_GET_CONFIG_INFO: { 4798 struct hdsp_config_info info; 4799 unsigned long flags; 4800 int i; 4801 4802 err = hdsp_check_for_iobox(hdsp); 4803 if (err < 0) 4804 return err; 4805 4806 err = hdsp_check_for_firmware(hdsp, 1); 4807 if (err < 0) 4808 return err; 4809 4810 memset(&info, 0, sizeof(info)); 4811 spin_lock_irqsave(&hdsp->lock, flags); 4812 info.pref_sync_ref = (unsigned char)hdsp_pref_sync_ref(hdsp); 4813 info.wordclock_sync_check = (unsigned char)hdsp_wc_sync_check(hdsp); 4814 if (hdsp->io_type != H9632) 4815 info.adatsync_sync_check = (unsigned char)hdsp_adatsync_sync_check(hdsp); 4816 info.spdif_sync_check = (unsigned char)hdsp_spdif_sync_check(hdsp); 4817 for (i = 0; i < ((hdsp->io_type != Multiface && hdsp->io_type != RPM && hdsp->io_type != H9632) ? 3 : 1); ++i) 4818 info.adat_sync_check[i] = (unsigned char)hdsp_adat_sync_check(hdsp, i); 4819 info.spdif_in = (unsigned char)hdsp_spdif_in(hdsp); 4820 info.spdif_out = (unsigned char)hdsp_toggle_setting(hdsp, 4821 HDSP_SPDIFOpticalOut); 4822 info.spdif_professional = (unsigned char) 4823 hdsp_toggle_setting(hdsp, HDSP_SPDIFProfessional); 4824 info.spdif_emphasis = (unsigned char) 4825 hdsp_toggle_setting(hdsp, HDSP_SPDIFEmphasis); 4826 info.spdif_nonaudio = (unsigned char) 4827 hdsp_toggle_setting(hdsp, HDSP_SPDIFNonAudio); 4828 info.spdif_sample_rate = hdsp_spdif_sample_rate(hdsp); 4829 info.system_sample_rate = hdsp->system_sample_rate; 4830 info.autosync_sample_rate = hdsp_external_sample_rate(hdsp); 4831 info.system_clock_mode = (unsigned char)hdsp_system_clock_mode(hdsp); 4832 info.clock_source = (unsigned char)hdsp_clock_source(hdsp); 4833 info.autosync_ref = (unsigned char)hdsp_autosync_ref(hdsp); 4834 info.line_out = (unsigned char) 4835 hdsp_toggle_setting(hdsp, HDSP_LineOut); 4836 if (hdsp->io_type == H9632) { 4837 info.da_gain = (unsigned char)hdsp_da_gain(hdsp); 4838 info.ad_gain = (unsigned char)hdsp_ad_gain(hdsp); 4839 info.phone_gain = (unsigned char)hdsp_phone_gain(hdsp); 4840 info.xlr_breakout_cable = 4841 (unsigned char)hdsp_toggle_setting(hdsp, 4842 HDSP_XLRBreakoutCable); 4843 4844 } else if (hdsp->io_type == RPM) { 4845 info.da_gain = (unsigned char) hdsp_rpm_input12(hdsp); 4846 info.ad_gain = (unsigned char) hdsp_rpm_input34(hdsp); 4847 } 4848 if (hdsp->io_type == H9632 || hdsp->io_type == H9652) 4849 info.analog_extension_board = 4850 (unsigned char)hdsp_toggle_setting(hdsp, 4851 HDSP_AnalogExtensionBoard); 4852 spin_unlock_irqrestore(&hdsp->lock, flags); 4853 if (copy_to_user(argp, &info, sizeof(info))) 4854 return -EFAULT; 4855 break; 4856 } 4857 case SNDRV_HDSP_IOCTL_GET_9632_AEB: { 4858 struct hdsp_9632_aeb h9632_aeb; 4859 4860 if (hdsp->io_type != H9632) return -EINVAL; 4861 h9632_aeb.aebi = hdsp->ss_in_channels - H9632_SS_CHANNELS; 4862 h9632_aeb.aebo = hdsp->ss_out_channels - H9632_SS_CHANNELS; 4863 if (copy_to_user(argp, &h9632_aeb, sizeof(h9632_aeb))) 4864 return -EFAULT; 4865 break; 4866 } 4867 case SNDRV_HDSP_IOCTL_GET_VERSION: { 4868 struct hdsp_version hdsp_version; 4869 int err; 4870 4871 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL; 4872 if (hdsp->io_type == Undefined) { 4873 err = hdsp_get_iobox_version(hdsp); 4874 if (err < 0) 4875 return err; 4876 } 4877 memset(&hdsp_version, 0, sizeof(hdsp_version)); 4878 hdsp_version.io_type = hdsp->io_type; 4879 hdsp_version.firmware_rev = hdsp->firmware_rev; 4880 if (copy_to_user(argp, &hdsp_version, sizeof(hdsp_version))) 4881 return -EFAULT; 4882 break; 4883 } 4884 case SNDRV_HDSP_IOCTL_UPLOAD_FIRMWARE: { 4885 struct hdsp_firmware firmware; 4886 u32 __user *firmware_data; 4887 int err; 4888 4889 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL; 4890 /* SNDRV_HDSP_IOCTL_GET_VERSION must have been called */ 4891 if (hdsp->io_type == Undefined) return -EINVAL; 4892 4893 if (hdsp->state & (HDSP_FirmwareCached | HDSP_FirmwareLoaded)) 4894 return -EBUSY; 4895 4896 dev_info(hdsp->card->dev, 4897 "initializing firmware upload\n"); 4898 if (copy_from_user(&firmware, argp, sizeof(firmware))) 4899 return -EFAULT; 4900 firmware_data = (u32 __user *)firmware.firmware_data; 4901 4902 if (hdsp_check_for_iobox (hdsp)) 4903 return -EIO; 4904 4905 if (!hdsp->fw_uploaded) { 4906 hdsp->fw_uploaded = vmalloc(HDSP_FIRMWARE_SIZE); 4907 if (!hdsp->fw_uploaded) 4908 return -ENOMEM; 4909 } 4910 4911 if (copy_from_user(hdsp->fw_uploaded, firmware_data, 4912 HDSP_FIRMWARE_SIZE)) { 4913 vfree(hdsp->fw_uploaded); 4914 hdsp->fw_uploaded = NULL; 4915 return -EFAULT; 4916 } 4917 4918 hdsp->state |= HDSP_FirmwareCached; 4919 4920 err = snd_hdsp_load_firmware_from_cache(hdsp); 4921 if (err < 0) 4922 return err; 4923 4924 if (!(hdsp->state & HDSP_InitializationComplete)) { 4925 err = snd_hdsp_enable_io(hdsp); 4926 if (err < 0) 4927 return err; 4928 4929 snd_hdsp_initialize_channels(hdsp); 4930 snd_hdsp_initialize_midi_flush(hdsp); 4931 4932 err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp); 4933 if (err < 0) { 4934 dev_err(hdsp->card->dev, 4935 "error creating alsa devices\n"); 4936 return err; 4937 } 4938 } 4939 break; 4940 } 4941 case SNDRV_HDSP_IOCTL_GET_MIXER: { 4942 struct hdsp_mixer __user *mixer = (struct hdsp_mixer __user *)argp; 4943 if (copy_to_user(mixer->matrix, hdsp->mixer_matrix, sizeof(unsigned short)*HDSP_MATRIX_MIXER_SIZE)) 4944 return -EFAULT; 4945 break; 4946 } 4947 default: 4948 return -EINVAL; 4949 } 4950 return 0; 4951 } 4952 4953 static const struct snd_pcm_ops snd_hdsp_playback_ops = { 4954 .open = snd_hdsp_playback_open, 4955 .close = snd_hdsp_playback_release, 4956 .ioctl = snd_hdsp_ioctl, 4957 .hw_params = snd_hdsp_hw_params, 4958 .prepare = snd_hdsp_prepare, 4959 .trigger = snd_hdsp_trigger, 4960 .pointer = snd_hdsp_hw_pointer, 4961 .copy_user = snd_hdsp_playback_copy, 4962 .copy_kernel = snd_hdsp_playback_copy_kernel, 4963 .fill_silence = snd_hdsp_hw_silence, 4964 }; 4965 4966 static const struct snd_pcm_ops snd_hdsp_capture_ops = { 4967 .open = snd_hdsp_capture_open, 4968 .close = snd_hdsp_capture_release, 4969 .ioctl = snd_hdsp_ioctl, 4970 .hw_params = snd_hdsp_hw_params, 4971 .prepare = snd_hdsp_prepare, 4972 .trigger = snd_hdsp_trigger, 4973 .pointer = snd_hdsp_hw_pointer, 4974 .copy_user = snd_hdsp_capture_copy, 4975 .copy_kernel = snd_hdsp_capture_copy_kernel, 4976 }; 4977 4978 static int snd_hdsp_create_hwdep(struct snd_card *card, struct hdsp *hdsp) 4979 { 4980 struct snd_hwdep *hw; 4981 int err; 4982 4983 err = snd_hwdep_new(card, "HDSP hwdep", 0, &hw); 4984 if (err < 0) 4985 return err; 4986 4987 hdsp->hwdep = hw; 4988 hw->private_data = hdsp; 4989 strcpy(hw->name, "HDSP hwdep interface"); 4990 4991 hw->ops.ioctl = snd_hdsp_hwdep_ioctl; 4992 hw->ops.ioctl_compat = snd_hdsp_hwdep_ioctl; 4993 4994 return 0; 4995 } 4996 4997 static int snd_hdsp_create_pcm(struct snd_card *card, struct hdsp *hdsp) 4998 { 4999 struct snd_pcm *pcm; 5000 int err; 5001 5002 err = snd_pcm_new(card, hdsp->card_name, 0, 1, 1, &pcm); 5003 if (err < 0) 5004 return err; 5005 5006 hdsp->pcm = pcm; 5007 pcm->private_data = hdsp; 5008 strcpy(pcm->name, hdsp->card_name); 5009 5010 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_hdsp_playback_ops); 5011 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_hdsp_capture_ops); 5012 5013 pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX; 5014 5015 return 0; 5016 } 5017 5018 static void snd_hdsp_9652_enable_mixer (struct hdsp *hdsp) 5019 { 5020 hdsp->control2_register |= HDSP_9652_ENABLE_MIXER; 5021 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register); 5022 } 5023 5024 static int snd_hdsp_enable_io (struct hdsp *hdsp) 5025 { 5026 int i; 5027 5028 if (hdsp_fifo_wait (hdsp, 0, 100)) { 5029 dev_err(hdsp->card->dev, 5030 "enable_io fifo_wait failed\n"); 5031 return -EIO; 5032 } 5033 5034 for (i = 0; i < hdsp->max_channels; ++i) { 5035 hdsp_write (hdsp, HDSP_inputEnable + (4 * i), 1); 5036 hdsp_write (hdsp, HDSP_outputEnable + (4 * i), 1); 5037 } 5038 5039 return 0; 5040 } 5041 5042 static void snd_hdsp_initialize_channels(struct hdsp *hdsp) 5043 { 5044 int status, aebi_channels, aebo_channels, i; 5045 5046 switch (hdsp->io_type) { 5047 case Digiface: 5048 hdsp->card_name = "RME Hammerfall DSP + Digiface"; 5049 hdsp->ss_in_channels = hdsp->ss_out_channels = DIGIFACE_SS_CHANNELS; 5050 hdsp->ds_in_channels = hdsp->ds_out_channels = DIGIFACE_DS_CHANNELS; 5051 break; 5052 5053 case H9652: 5054 hdsp->card_name = "RME Hammerfall HDSP 9652"; 5055 hdsp->ss_in_channels = hdsp->ss_out_channels = H9652_SS_CHANNELS; 5056 hdsp->ds_in_channels = hdsp->ds_out_channels = H9652_DS_CHANNELS; 5057 break; 5058 5059 case H9632: 5060 status = hdsp_read(hdsp, HDSP_statusRegister); 5061 /* HDSP_AEBx bits are low when AEB are connected */ 5062 aebi_channels = (status & HDSP_AEBI) ? 0 : 4; 5063 aebo_channels = (status & HDSP_AEBO) ? 0 : 4; 5064 hdsp->card_name = "RME Hammerfall HDSP 9632"; 5065 hdsp->ss_in_channels = H9632_SS_CHANNELS+aebi_channels; 5066 hdsp->ds_in_channels = H9632_DS_CHANNELS+aebi_channels; 5067 hdsp->qs_in_channels = H9632_QS_CHANNELS+aebi_channels; 5068 hdsp->ss_out_channels = H9632_SS_CHANNELS+aebo_channels; 5069 hdsp->ds_out_channels = H9632_DS_CHANNELS+aebo_channels; 5070 hdsp->qs_out_channels = H9632_QS_CHANNELS+aebo_channels; 5071 /* Disable loopback of output channels, as the set function 5072 * only sets on a change we fake all bits (channels) as enabled. 5073 */ 5074 hdsp->io_loopback = 0xffffffff; 5075 for (i = 0; i < hdsp->max_channels; ++i) 5076 hdsp_loopback_set(hdsp, i, false); 5077 break; 5078 5079 case Multiface: 5080 hdsp->card_name = "RME Hammerfall DSP + Multiface"; 5081 hdsp->ss_in_channels = hdsp->ss_out_channels = MULTIFACE_SS_CHANNELS; 5082 hdsp->ds_in_channels = hdsp->ds_out_channels = MULTIFACE_DS_CHANNELS; 5083 break; 5084 5085 case RPM: 5086 hdsp->card_name = "RME Hammerfall DSP + RPM"; 5087 hdsp->ss_in_channels = RPM_CHANNELS-1; 5088 hdsp->ss_out_channels = RPM_CHANNELS; 5089 hdsp->ds_in_channels = RPM_CHANNELS-1; 5090 hdsp->ds_out_channels = RPM_CHANNELS; 5091 break; 5092 5093 default: 5094 /* should never get here */ 5095 break; 5096 } 5097 } 5098 5099 static void snd_hdsp_initialize_midi_flush (struct hdsp *hdsp) 5100 { 5101 snd_hdsp_flush_midi_input (hdsp, 0); 5102 snd_hdsp_flush_midi_input (hdsp, 1); 5103 } 5104 5105 static int snd_hdsp_create_alsa_devices(struct snd_card *card, struct hdsp *hdsp) 5106 { 5107 int err; 5108 5109 err = snd_hdsp_create_pcm(card, hdsp); 5110 if (err < 0) { 5111 dev_err(card->dev, 5112 "Error creating pcm interface\n"); 5113 return err; 5114 } 5115 5116 5117 err = snd_hdsp_create_midi(card, hdsp, 0); 5118 if (err < 0) { 5119 dev_err(card->dev, 5120 "Error creating first midi interface\n"); 5121 return err; 5122 } 5123 5124 if (hdsp->io_type == Digiface || hdsp->io_type == H9652) { 5125 err = snd_hdsp_create_midi(card, hdsp, 1); 5126 if (err < 0) { 5127 dev_err(card->dev, 5128 "Error creating second midi interface\n"); 5129 return err; 5130 } 5131 } 5132 5133 err = snd_hdsp_create_controls(card, hdsp); 5134 if (err < 0) { 5135 dev_err(card->dev, 5136 "Error creating ctl interface\n"); 5137 return err; 5138 } 5139 5140 snd_hdsp_proc_init(hdsp); 5141 5142 hdsp->system_sample_rate = -1; 5143 hdsp->playback_pid = -1; 5144 hdsp->capture_pid = -1; 5145 hdsp->capture_substream = NULL; 5146 hdsp->playback_substream = NULL; 5147 5148 err = snd_hdsp_set_defaults(hdsp); 5149 if (err < 0) { 5150 dev_err(card->dev, 5151 "Error setting default values\n"); 5152 return err; 5153 } 5154 5155 if (!(hdsp->state & HDSP_InitializationComplete)) { 5156 strcpy(card->shortname, "Hammerfall DSP"); 5157 sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name, 5158 hdsp->port, hdsp->irq); 5159 5160 err = snd_card_register(card); 5161 if (err < 0) { 5162 dev_err(card->dev, 5163 "error registering card\n"); 5164 return err; 5165 } 5166 hdsp->state |= HDSP_InitializationComplete; 5167 } 5168 5169 return 0; 5170 } 5171 5172 /* load firmware via hotplug fw loader */ 5173 static int hdsp_request_fw_loader(struct hdsp *hdsp) 5174 { 5175 const char *fwfile; 5176 const struct firmware *fw; 5177 int err; 5178 5179 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) 5180 return 0; 5181 if (hdsp->io_type == Undefined) { 5182 err = hdsp_get_iobox_version(hdsp); 5183 if (err < 0) 5184 return err; 5185 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) 5186 return 0; 5187 } 5188 5189 /* caution: max length of firmware filename is 30! */ 5190 switch (hdsp->io_type) { 5191 case RPM: 5192 fwfile = "rpm_firmware.bin"; 5193 break; 5194 case Multiface: 5195 if (hdsp->firmware_rev == 0xa) 5196 fwfile = "multiface_firmware.bin"; 5197 else 5198 fwfile = "multiface_firmware_rev11.bin"; 5199 break; 5200 case Digiface: 5201 if (hdsp->firmware_rev == 0xa) 5202 fwfile = "digiface_firmware.bin"; 5203 else 5204 fwfile = "digiface_firmware_rev11.bin"; 5205 break; 5206 default: 5207 dev_err(hdsp->card->dev, 5208 "invalid io_type %d\n", hdsp->io_type); 5209 return -EINVAL; 5210 } 5211 5212 if (request_firmware(&fw, fwfile, &hdsp->pci->dev)) { 5213 dev_err(hdsp->card->dev, 5214 "cannot load firmware %s\n", fwfile); 5215 return -ENOENT; 5216 } 5217 if (fw->size < HDSP_FIRMWARE_SIZE) { 5218 dev_err(hdsp->card->dev, 5219 "too short firmware size %d (expected %d)\n", 5220 (int)fw->size, HDSP_FIRMWARE_SIZE); 5221 release_firmware(fw); 5222 return -EINVAL; 5223 } 5224 5225 hdsp->firmware = fw; 5226 5227 hdsp->state |= HDSP_FirmwareCached; 5228 5229 err = snd_hdsp_load_firmware_from_cache(hdsp); 5230 if (err < 0) 5231 return err; 5232 5233 if (!(hdsp->state & HDSP_InitializationComplete)) { 5234 err = snd_hdsp_enable_io(hdsp); 5235 if (err < 0) 5236 return err; 5237 5238 err = snd_hdsp_create_hwdep(hdsp->card, hdsp); 5239 if (err < 0) { 5240 dev_err(hdsp->card->dev, 5241 "error creating hwdep device\n"); 5242 return err; 5243 } 5244 snd_hdsp_initialize_channels(hdsp); 5245 snd_hdsp_initialize_midi_flush(hdsp); 5246 err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp); 5247 if (err < 0) { 5248 dev_err(hdsp->card->dev, 5249 "error creating alsa devices\n"); 5250 return err; 5251 } 5252 } 5253 return 0; 5254 } 5255 5256 static int snd_hdsp_create(struct snd_card *card, 5257 struct hdsp *hdsp) 5258 { 5259 struct pci_dev *pci = hdsp->pci; 5260 int err; 5261 int is_9652 = 0; 5262 int is_9632 = 0; 5263 5264 hdsp->irq = -1; 5265 hdsp->state = 0; 5266 hdsp->midi[0].rmidi = NULL; 5267 hdsp->midi[1].rmidi = NULL; 5268 hdsp->midi[0].input = NULL; 5269 hdsp->midi[1].input = NULL; 5270 hdsp->midi[0].output = NULL; 5271 hdsp->midi[1].output = NULL; 5272 hdsp->midi[0].pending = 0; 5273 hdsp->midi[1].pending = 0; 5274 spin_lock_init(&hdsp->midi[0].lock); 5275 spin_lock_init(&hdsp->midi[1].lock); 5276 hdsp->iobase = NULL; 5277 hdsp->control_register = 0; 5278 hdsp->control2_register = 0; 5279 hdsp->io_type = Undefined; 5280 hdsp->max_channels = 26; 5281 5282 hdsp->card = card; 5283 5284 spin_lock_init(&hdsp->lock); 5285 5286 INIT_WORK(&hdsp->midi_work, hdsp_midi_work); 5287 5288 pci_read_config_word(hdsp->pci, PCI_CLASS_REVISION, &hdsp->firmware_rev); 5289 hdsp->firmware_rev &= 0xff; 5290 5291 /* From Martin Bjoernsen : 5292 "It is important that the card's latency timer register in 5293 the PCI configuration space is set to a value much larger 5294 than 0 by the computer's BIOS or the driver. 5295 The windows driver always sets this 8 bit register [...] 5296 to its maximum 255 to avoid problems with some computers." 5297 */ 5298 pci_write_config_byte(hdsp->pci, PCI_LATENCY_TIMER, 0xFF); 5299 5300 strcpy(card->driver, "H-DSP"); 5301 strcpy(card->mixername, "Xilinx FPGA"); 5302 5303 if (hdsp->firmware_rev < 0xa) 5304 return -ENODEV; 5305 else if (hdsp->firmware_rev < 0x64) 5306 hdsp->card_name = "RME Hammerfall DSP"; 5307 else if (hdsp->firmware_rev < 0x96) { 5308 hdsp->card_name = "RME HDSP 9652"; 5309 is_9652 = 1; 5310 } else { 5311 hdsp->card_name = "RME HDSP 9632"; 5312 hdsp->max_channels = 16; 5313 is_9632 = 1; 5314 } 5315 5316 err = pci_enable_device(pci); 5317 if (err < 0) 5318 return err; 5319 5320 pci_set_master(hdsp->pci); 5321 5322 err = pci_request_regions(pci, "hdsp"); 5323 if (err < 0) 5324 return err; 5325 hdsp->port = pci_resource_start(pci, 0); 5326 hdsp->iobase = ioremap(hdsp->port, HDSP_IO_EXTENT); 5327 if (!hdsp->iobase) { 5328 dev_err(hdsp->card->dev, "unable to remap region 0x%lx-0x%lx\n", 5329 hdsp->port, hdsp->port + HDSP_IO_EXTENT - 1); 5330 return -EBUSY; 5331 } 5332 5333 if (request_irq(pci->irq, snd_hdsp_interrupt, IRQF_SHARED, 5334 KBUILD_MODNAME, hdsp)) { 5335 dev_err(hdsp->card->dev, "unable to use IRQ %d\n", pci->irq); 5336 return -EBUSY; 5337 } 5338 5339 hdsp->irq = pci->irq; 5340 card->sync_irq = hdsp->irq; 5341 hdsp->precise_ptr = 0; 5342 hdsp->use_midi_work = 1; 5343 hdsp->dds_value = 0; 5344 5345 err = snd_hdsp_initialize_memory(hdsp); 5346 if (err < 0) 5347 return err; 5348 5349 if (!is_9652 && !is_9632) { 5350 /* we wait a maximum of 10 seconds to let freshly 5351 * inserted cardbus cards do their hardware init */ 5352 err = hdsp_wait_for_iobox(hdsp, 1000, 10); 5353 5354 if (err < 0) 5355 return err; 5356 5357 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) { 5358 err = hdsp_request_fw_loader(hdsp); 5359 if (err < 0) 5360 /* we don't fail as this can happen 5361 if userspace is not ready for 5362 firmware upload 5363 */ 5364 dev_err(hdsp->card->dev, 5365 "couldn't get firmware from userspace. try using hdsploader\n"); 5366 else 5367 /* init is complete, we return */ 5368 return 0; 5369 /* we defer initialization */ 5370 dev_info(hdsp->card->dev, 5371 "card initialization pending : waiting for firmware\n"); 5372 err = snd_hdsp_create_hwdep(card, hdsp); 5373 if (err < 0) 5374 return err; 5375 return 0; 5376 } else { 5377 dev_info(hdsp->card->dev, 5378 "Firmware already present, initializing card.\n"); 5379 if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version2) 5380 hdsp->io_type = RPM; 5381 else if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1) 5382 hdsp->io_type = Multiface; 5383 else 5384 hdsp->io_type = Digiface; 5385 } 5386 } 5387 5388 err = snd_hdsp_enable_io(hdsp); 5389 if (err) 5390 return err; 5391 5392 if (is_9652) 5393 hdsp->io_type = H9652; 5394 5395 if (is_9632) 5396 hdsp->io_type = H9632; 5397 5398 err = snd_hdsp_create_hwdep(card, hdsp); 5399 if (err < 0) 5400 return err; 5401 5402 snd_hdsp_initialize_channels(hdsp); 5403 snd_hdsp_initialize_midi_flush(hdsp); 5404 5405 hdsp->state |= HDSP_FirmwareLoaded; 5406 5407 err = snd_hdsp_create_alsa_devices(card, hdsp); 5408 if (err < 0) 5409 return err; 5410 5411 return 0; 5412 } 5413 5414 static int snd_hdsp_free(struct hdsp *hdsp) 5415 { 5416 if (hdsp->port) { 5417 /* stop the audio, and cancel all interrupts */ 5418 cancel_work_sync(&hdsp->midi_work); 5419 hdsp->control_register &= ~(HDSP_Start|HDSP_AudioInterruptEnable|HDSP_Midi0InterruptEnable|HDSP_Midi1InterruptEnable); 5420 hdsp_write (hdsp, HDSP_controlRegister, hdsp->control_register); 5421 } 5422 5423 if (hdsp->irq >= 0) 5424 free_irq(hdsp->irq, (void *)hdsp); 5425 5426 snd_hdsp_free_buffers(hdsp); 5427 5428 release_firmware(hdsp->firmware); 5429 vfree(hdsp->fw_uploaded); 5430 iounmap(hdsp->iobase); 5431 5432 if (hdsp->port) 5433 pci_release_regions(hdsp->pci); 5434 5435 if (pci_is_enabled(hdsp->pci)) 5436 pci_disable_device(hdsp->pci); 5437 return 0; 5438 } 5439 5440 static void snd_hdsp_card_free(struct snd_card *card) 5441 { 5442 struct hdsp *hdsp = card->private_data; 5443 5444 if (hdsp) 5445 snd_hdsp_free(hdsp); 5446 } 5447 5448 static int snd_hdsp_probe(struct pci_dev *pci, 5449 const struct pci_device_id *pci_id) 5450 { 5451 static int dev; 5452 struct hdsp *hdsp; 5453 struct snd_card *card; 5454 int err; 5455 5456 if (dev >= SNDRV_CARDS) 5457 return -ENODEV; 5458 if (!enable[dev]) { 5459 dev++; 5460 return -ENOENT; 5461 } 5462 5463 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE, 5464 sizeof(struct hdsp), &card); 5465 if (err < 0) 5466 return err; 5467 5468 hdsp = card->private_data; 5469 card->private_free = snd_hdsp_card_free; 5470 hdsp->dev = dev; 5471 hdsp->pci = pci; 5472 err = snd_hdsp_create(card, hdsp); 5473 if (err) 5474 goto free_card; 5475 5476 strcpy(card->shortname, "Hammerfall DSP"); 5477 sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name, 5478 hdsp->port, hdsp->irq); 5479 err = snd_card_register(card); 5480 if (err) { 5481 free_card: 5482 snd_card_free(card); 5483 return err; 5484 } 5485 pci_set_drvdata(pci, card); 5486 dev++; 5487 return 0; 5488 } 5489 5490 static void snd_hdsp_remove(struct pci_dev *pci) 5491 { 5492 snd_card_free(pci_get_drvdata(pci)); 5493 } 5494 5495 static struct pci_driver hdsp_driver = { 5496 .name = KBUILD_MODNAME, 5497 .id_table = snd_hdsp_ids, 5498 .probe = snd_hdsp_probe, 5499 .remove = snd_hdsp_remove, 5500 }; 5501 5502 module_pci_driver(hdsp_driver); 5503