1 /* 2 * ALSA driver for RME Hammerfall DSP audio interface(s) 3 * 4 * Copyright (c) 2002 Paul Davis 5 * Marcus Andersson 6 * Thomas Charbonnel 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 21 * 22 */ 23 24 #include <sound/driver.h> 25 #include <linux/init.h> 26 #include <linux/delay.h> 27 #include <linux/interrupt.h> 28 #include <linux/slab.h> 29 #include <linux/pci.h> 30 #include <linux/firmware.h> 31 #include <linux/moduleparam.h> 32 33 #include <sound/core.h> 34 #include <sound/control.h> 35 #include <sound/pcm.h> 36 #include <sound/info.h> 37 #include <sound/asoundef.h> 38 #include <sound/rawmidi.h> 39 #include <sound/hwdep.h> 40 #include <sound/initval.h> 41 #include <sound/hdsp.h> 42 43 #include <asm/byteorder.h> 44 #include <asm/current.h> 45 #include <asm/io.h> 46 47 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ 48 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ 49 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */ 50 51 module_param_array(index, int, NULL, 0444); 52 MODULE_PARM_DESC(index, "Index value for RME Hammerfall DSP interface."); 53 module_param_array(id, charp, NULL, 0444); 54 MODULE_PARM_DESC(id, "ID string for RME Hammerfall DSP interface."); 55 module_param_array(enable, bool, NULL, 0444); 56 MODULE_PARM_DESC(enable, "Enable/disable specific Hammerfall DSP soundcards."); 57 MODULE_AUTHOR("Paul Davis <paul@linuxaudiosystems.com>, Marcus Andersson, Thomas Charbonnel <thomas@undata.org>"); 58 MODULE_DESCRIPTION("RME Hammerfall DSP"); 59 MODULE_LICENSE("GPL"); 60 MODULE_SUPPORTED_DEVICE("{{RME Hammerfall-DSP}," 61 "{RME HDSP-9652}," 62 "{RME HDSP-9632}}"); 63 #ifdef HDSP_FW_LOADER 64 MODULE_FIRMWARE("multiface_firmware.bin"); 65 MODULE_FIRMWARE("multiface_firmware_rev11.bin"); 66 MODULE_FIRMWARE("digiface_firmware.bin"); 67 MODULE_FIRMWARE("digiface_firmware_rev11.bin"); 68 #endif 69 70 #define HDSP_MAX_CHANNELS 26 71 #define HDSP_MAX_DS_CHANNELS 14 72 #define HDSP_MAX_QS_CHANNELS 8 73 #define DIGIFACE_SS_CHANNELS 26 74 #define DIGIFACE_DS_CHANNELS 14 75 #define MULTIFACE_SS_CHANNELS 18 76 #define MULTIFACE_DS_CHANNELS 14 77 #define H9652_SS_CHANNELS 26 78 #define H9652_DS_CHANNELS 14 79 /* This does not include possible Analog Extension Boards 80 AEBs are detected at card initialization 81 */ 82 #define H9632_SS_CHANNELS 12 83 #define H9632_DS_CHANNELS 8 84 #define H9632_QS_CHANNELS 4 85 86 /* Write registers. These are defined as byte-offsets from the iobase value. 87 */ 88 #define HDSP_resetPointer 0 89 #define HDSP_freqReg 0 90 #define HDSP_outputBufferAddress 32 91 #define HDSP_inputBufferAddress 36 92 #define HDSP_controlRegister 64 93 #define HDSP_interruptConfirmation 96 94 #define HDSP_outputEnable 128 95 #define HDSP_control2Reg 256 96 #define HDSP_midiDataOut0 352 97 #define HDSP_midiDataOut1 356 98 #define HDSP_fifoData 368 99 #define HDSP_inputEnable 384 100 101 /* Read registers. These are defined as byte-offsets from the iobase value 102 */ 103 104 #define HDSP_statusRegister 0 105 #define HDSP_timecode 128 106 #define HDSP_status2Register 192 107 #define HDSP_midiDataOut0 352 108 #define HDSP_midiDataOut1 356 109 #define HDSP_midiDataIn0 360 110 #define HDSP_midiDataIn1 364 111 #define HDSP_midiStatusOut0 384 112 #define HDSP_midiStatusOut1 388 113 #define HDSP_midiStatusIn0 392 114 #define HDSP_midiStatusIn1 396 115 #define HDSP_fifoStatus 400 116 117 /* the meters are regular i/o-mapped registers, but offset 118 considerably from the rest. the peak registers are reset 119 when read; the least-significant 4 bits are full-scale counters; 120 the actual peak value is in the most-significant 24 bits. 121 */ 122 123 #define HDSP_playbackPeakLevel 4096 /* 26 * 32 bit values */ 124 #define HDSP_inputPeakLevel 4224 /* 26 * 32 bit values */ 125 #define HDSP_outputPeakLevel 4352 /* (26+2) * 32 bit values */ 126 #define HDSP_playbackRmsLevel 4612 /* 26 * 64 bit values */ 127 #define HDSP_inputRmsLevel 4868 /* 26 * 64 bit values */ 128 129 130 /* This is for H9652 cards 131 Peak values are read downward from the base 132 Rms values are read upward 133 There are rms values for the outputs too 134 26*3 values are read in ss mode 135 14*3 in ds mode, with no gap between values 136 */ 137 #define HDSP_9652_peakBase 7164 138 #define HDSP_9652_rmsBase 4096 139 140 /* c.f. the hdsp_9632_meters_t struct */ 141 #define HDSP_9632_metersBase 4096 142 143 #define HDSP_IO_EXTENT 7168 144 145 /* control2 register bits */ 146 147 #define HDSP_TMS 0x01 148 #define HDSP_TCK 0x02 149 #define HDSP_TDI 0x04 150 #define HDSP_JTAG 0x08 151 #define HDSP_PWDN 0x10 152 #define HDSP_PROGRAM 0x020 153 #define HDSP_CONFIG_MODE_0 0x040 154 #define HDSP_CONFIG_MODE_1 0x080 155 #define HDSP_VERSION_BIT 0x100 156 #define HDSP_BIGENDIAN_MODE 0x200 157 #define HDSP_RD_MULTIPLE 0x400 158 #define HDSP_9652_ENABLE_MIXER 0x800 159 #define HDSP_TDO 0x10000000 160 161 #define HDSP_S_PROGRAM (HDSP_PROGRAM|HDSP_CONFIG_MODE_0) 162 #define HDSP_S_LOAD (HDSP_PROGRAM|HDSP_CONFIG_MODE_1) 163 164 /* Control Register bits */ 165 166 #define HDSP_Start (1<<0) /* start engine */ 167 #define HDSP_Latency0 (1<<1) /* buffer size = 2^n where n is defined by Latency{2,1,0} */ 168 #define HDSP_Latency1 (1<<2) /* [ see above ] */ 169 #define HDSP_Latency2 (1<<3) /* [ see above ] */ 170 #define HDSP_ClockModeMaster (1<<4) /* 1=Master, 0=Slave/Autosync */ 171 #define HDSP_AudioInterruptEnable (1<<5) /* what do you think ? */ 172 #define HDSP_Frequency0 (1<<6) /* 0=44.1kHz/88.2kHz/176.4kHz 1=48kHz/96kHz/192kHz */ 173 #define HDSP_Frequency1 (1<<7) /* 0=32kHz/64kHz/128kHz */ 174 #define HDSP_DoubleSpeed (1<<8) /* 0=normal speed, 1=double speed */ 175 #define HDSP_SPDIFProfessional (1<<9) /* 0=consumer, 1=professional */ 176 #define HDSP_SPDIFEmphasis (1<<10) /* 0=none, 1=on */ 177 #define HDSP_SPDIFNonAudio (1<<11) /* 0=off, 1=on */ 178 #define HDSP_SPDIFOpticalOut (1<<12) /* 1=use 1st ADAT connector for SPDIF, 0=do not */ 179 #define HDSP_SyncRef2 (1<<13) 180 #define HDSP_SPDIFInputSelect0 (1<<14) 181 #define HDSP_SPDIFInputSelect1 (1<<15) 182 #define HDSP_SyncRef0 (1<<16) 183 #define HDSP_SyncRef1 (1<<17) 184 #define HDSP_AnalogExtensionBoard (1<<18) /* For H9632 cards */ 185 #define HDSP_XLRBreakoutCable (1<<20) /* For H9632 cards */ 186 #define HDSP_Midi0InterruptEnable (1<<22) 187 #define HDSP_Midi1InterruptEnable (1<<23) 188 #define HDSP_LineOut (1<<24) 189 #define HDSP_ADGain0 (1<<25) /* From here : H9632 specific */ 190 #define HDSP_ADGain1 (1<<26) 191 #define HDSP_DAGain0 (1<<27) 192 #define HDSP_DAGain1 (1<<28) 193 #define HDSP_PhoneGain0 (1<<29) 194 #define HDSP_PhoneGain1 (1<<30) 195 #define HDSP_QuadSpeed (1<<31) 196 197 #define HDSP_ADGainMask (HDSP_ADGain0|HDSP_ADGain1) 198 #define HDSP_ADGainMinus10dBV HDSP_ADGainMask 199 #define HDSP_ADGainPlus4dBu (HDSP_ADGain0) 200 #define HDSP_ADGainLowGain 0 201 202 #define HDSP_DAGainMask (HDSP_DAGain0|HDSP_DAGain1) 203 #define HDSP_DAGainHighGain HDSP_DAGainMask 204 #define HDSP_DAGainPlus4dBu (HDSP_DAGain0) 205 #define HDSP_DAGainMinus10dBV 0 206 207 #define HDSP_PhoneGainMask (HDSP_PhoneGain0|HDSP_PhoneGain1) 208 #define HDSP_PhoneGain0dB HDSP_PhoneGainMask 209 #define HDSP_PhoneGainMinus6dB (HDSP_PhoneGain0) 210 #define HDSP_PhoneGainMinus12dB 0 211 212 #define HDSP_LatencyMask (HDSP_Latency0|HDSP_Latency1|HDSP_Latency2) 213 #define HDSP_FrequencyMask (HDSP_Frequency0|HDSP_Frequency1|HDSP_DoubleSpeed|HDSP_QuadSpeed) 214 215 #define HDSP_SPDIFInputMask (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1) 216 #define HDSP_SPDIFInputADAT1 0 217 #define HDSP_SPDIFInputCoaxial (HDSP_SPDIFInputSelect0) 218 #define HDSP_SPDIFInputCdrom (HDSP_SPDIFInputSelect1) 219 #define HDSP_SPDIFInputAES (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1) 220 221 #define HDSP_SyncRefMask (HDSP_SyncRef0|HDSP_SyncRef1|HDSP_SyncRef2) 222 #define HDSP_SyncRef_ADAT1 0 223 #define HDSP_SyncRef_ADAT2 (HDSP_SyncRef0) 224 #define HDSP_SyncRef_ADAT3 (HDSP_SyncRef1) 225 #define HDSP_SyncRef_SPDIF (HDSP_SyncRef0|HDSP_SyncRef1) 226 #define HDSP_SyncRef_WORD (HDSP_SyncRef2) 227 #define HDSP_SyncRef_ADAT_SYNC (HDSP_SyncRef0|HDSP_SyncRef2) 228 229 /* Sample Clock Sources */ 230 231 #define HDSP_CLOCK_SOURCE_AUTOSYNC 0 232 #define HDSP_CLOCK_SOURCE_INTERNAL_32KHZ 1 233 #define HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ 2 234 #define HDSP_CLOCK_SOURCE_INTERNAL_48KHZ 3 235 #define HDSP_CLOCK_SOURCE_INTERNAL_64KHZ 4 236 #define HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ 5 237 #define HDSP_CLOCK_SOURCE_INTERNAL_96KHZ 6 238 #define HDSP_CLOCK_SOURCE_INTERNAL_128KHZ 7 239 #define HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ 8 240 #define HDSP_CLOCK_SOURCE_INTERNAL_192KHZ 9 241 242 /* Preferred sync reference choices - used by "pref_sync_ref" control switch */ 243 244 #define HDSP_SYNC_FROM_WORD 0 245 #define HDSP_SYNC_FROM_SPDIF 1 246 #define HDSP_SYNC_FROM_ADAT1 2 247 #define HDSP_SYNC_FROM_ADAT_SYNC 3 248 #define HDSP_SYNC_FROM_ADAT2 4 249 #define HDSP_SYNC_FROM_ADAT3 5 250 251 /* SyncCheck status */ 252 253 #define HDSP_SYNC_CHECK_NO_LOCK 0 254 #define HDSP_SYNC_CHECK_LOCK 1 255 #define HDSP_SYNC_CHECK_SYNC 2 256 257 /* AutoSync references - used by "autosync_ref" control switch */ 258 259 #define HDSP_AUTOSYNC_FROM_WORD 0 260 #define HDSP_AUTOSYNC_FROM_ADAT_SYNC 1 261 #define HDSP_AUTOSYNC_FROM_SPDIF 2 262 #define HDSP_AUTOSYNC_FROM_NONE 3 263 #define HDSP_AUTOSYNC_FROM_ADAT1 4 264 #define HDSP_AUTOSYNC_FROM_ADAT2 5 265 #define HDSP_AUTOSYNC_FROM_ADAT3 6 266 267 /* Possible sources of S/PDIF input */ 268 269 #define HDSP_SPDIFIN_OPTICAL 0 /* optical (ADAT1) */ 270 #define HDSP_SPDIFIN_COAXIAL 1 /* coaxial (RCA) */ 271 #define HDSP_SPDIFIN_INTERNAL 2 /* internal (CDROM) */ 272 #define HDSP_SPDIFIN_AES 3 /* xlr for H9632 (AES)*/ 273 274 #define HDSP_Frequency32KHz HDSP_Frequency0 275 #define HDSP_Frequency44_1KHz HDSP_Frequency1 276 #define HDSP_Frequency48KHz (HDSP_Frequency1|HDSP_Frequency0) 277 #define HDSP_Frequency64KHz (HDSP_DoubleSpeed|HDSP_Frequency0) 278 #define HDSP_Frequency88_2KHz (HDSP_DoubleSpeed|HDSP_Frequency1) 279 #define HDSP_Frequency96KHz (HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0) 280 /* For H9632 cards */ 281 #define HDSP_Frequency128KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency0) 282 #define HDSP_Frequency176_4KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1) 283 #define HDSP_Frequency192KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0) 284 /* RME says n = 104857600000000, but in the windows MADI driver, I see: 285 return 104857600000000 / rate; // 100 MHz 286 return 110100480000000 / rate; // 105 MHz 287 */ 288 #define DDS_NUMERATOR 104857600000000ULL; /* = 2^20 * 10^8 */ 289 290 #define hdsp_encode_latency(x) (((x)<<1) & HDSP_LatencyMask) 291 #define hdsp_decode_latency(x) (((x) & HDSP_LatencyMask)>>1) 292 293 #define hdsp_encode_spdif_in(x) (((x)&0x3)<<14) 294 #define hdsp_decode_spdif_in(x) (((x)>>14)&0x3) 295 296 /* Status Register bits */ 297 298 #define HDSP_audioIRQPending (1<<0) 299 #define HDSP_Lock2 (1<<1) /* this is for Digiface and H9652 */ 300 #define HDSP_spdifFrequency3 HDSP_Lock2 /* this is for H9632 only */ 301 #define HDSP_Lock1 (1<<2) 302 #define HDSP_Lock0 (1<<3) 303 #define HDSP_SPDIFSync (1<<4) 304 #define HDSP_TimecodeLock (1<<5) 305 #define HDSP_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */ 306 #define HDSP_Sync2 (1<<16) 307 #define HDSP_Sync1 (1<<17) 308 #define HDSP_Sync0 (1<<18) 309 #define HDSP_DoubleSpeedStatus (1<<19) 310 #define HDSP_ConfigError (1<<20) 311 #define HDSP_DllError (1<<21) 312 #define HDSP_spdifFrequency0 (1<<22) 313 #define HDSP_spdifFrequency1 (1<<23) 314 #define HDSP_spdifFrequency2 (1<<24) 315 #define HDSP_SPDIFErrorFlag (1<<25) 316 #define HDSP_BufferID (1<<26) 317 #define HDSP_TimecodeSync (1<<27) 318 #define HDSP_AEBO (1<<28) /* H9632 specific Analog Extension Boards */ 319 #define HDSP_AEBI (1<<29) /* 0 = present, 1 = absent */ 320 #define HDSP_midi0IRQPending (1<<30) 321 #define HDSP_midi1IRQPending (1<<31) 322 323 #define HDSP_spdifFrequencyMask (HDSP_spdifFrequency0|HDSP_spdifFrequency1|HDSP_spdifFrequency2) 324 325 #define HDSP_spdifFrequency32KHz (HDSP_spdifFrequency0) 326 #define HDSP_spdifFrequency44_1KHz (HDSP_spdifFrequency1) 327 #define HDSP_spdifFrequency48KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency1) 328 329 #define HDSP_spdifFrequency64KHz (HDSP_spdifFrequency2) 330 #define HDSP_spdifFrequency88_2KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency2) 331 #define HDSP_spdifFrequency96KHz (HDSP_spdifFrequency2|HDSP_spdifFrequency1) 332 333 /* This is for H9632 cards */ 334 #define HDSP_spdifFrequency128KHz HDSP_spdifFrequencyMask 335 #define HDSP_spdifFrequency176_4KHz HDSP_spdifFrequency3 336 #define HDSP_spdifFrequency192KHz (HDSP_spdifFrequency3|HDSP_spdifFrequency0) 337 338 /* Status2 Register bits */ 339 340 #define HDSP_version0 (1<<0) 341 #define HDSP_version1 (1<<1) 342 #define HDSP_version2 (1<<2) 343 #define HDSP_wc_lock (1<<3) 344 #define HDSP_wc_sync (1<<4) 345 #define HDSP_inp_freq0 (1<<5) 346 #define HDSP_inp_freq1 (1<<6) 347 #define HDSP_inp_freq2 (1<<7) 348 #define HDSP_SelSyncRef0 (1<<8) 349 #define HDSP_SelSyncRef1 (1<<9) 350 #define HDSP_SelSyncRef2 (1<<10) 351 352 #define HDSP_wc_valid (HDSP_wc_lock|HDSP_wc_sync) 353 354 #define HDSP_systemFrequencyMask (HDSP_inp_freq0|HDSP_inp_freq1|HDSP_inp_freq2) 355 #define HDSP_systemFrequency32 (HDSP_inp_freq0) 356 #define HDSP_systemFrequency44_1 (HDSP_inp_freq1) 357 #define HDSP_systemFrequency48 (HDSP_inp_freq0|HDSP_inp_freq1) 358 #define HDSP_systemFrequency64 (HDSP_inp_freq2) 359 #define HDSP_systemFrequency88_2 (HDSP_inp_freq0|HDSP_inp_freq2) 360 #define HDSP_systemFrequency96 (HDSP_inp_freq1|HDSP_inp_freq2) 361 /* FIXME : more values for 9632 cards ? */ 362 363 #define HDSP_SelSyncRefMask (HDSP_SelSyncRef0|HDSP_SelSyncRef1|HDSP_SelSyncRef2) 364 #define HDSP_SelSyncRef_ADAT1 0 365 #define HDSP_SelSyncRef_ADAT2 (HDSP_SelSyncRef0) 366 #define HDSP_SelSyncRef_ADAT3 (HDSP_SelSyncRef1) 367 #define HDSP_SelSyncRef_SPDIF (HDSP_SelSyncRef0|HDSP_SelSyncRef1) 368 #define HDSP_SelSyncRef_WORD (HDSP_SelSyncRef2) 369 #define HDSP_SelSyncRef_ADAT_SYNC (HDSP_SelSyncRef0|HDSP_SelSyncRef2) 370 371 /* Card state flags */ 372 373 #define HDSP_InitializationComplete (1<<0) 374 #define HDSP_FirmwareLoaded (1<<1) 375 #define HDSP_FirmwareCached (1<<2) 376 377 /* FIFO wait times, defined in terms of 1/10ths of msecs */ 378 379 #define HDSP_LONG_WAIT 5000 380 #define HDSP_SHORT_WAIT 30 381 382 #define UNITY_GAIN 32768 383 #define MINUS_INFINITY_GAIN 0 384 385 /* the size of a substream (1 mono data stream) */ 386 387 #define HDSP_CHANNEL_BUFFER_SAMPLES (16*1024) 388 #define HDSP_CHANNEL_BUFFER_BYTES (4*HDSP_CHANNEL_BUFFER_SAMPLES) 389 390 /* the size of the area we need to allocate for DMA transfers. the 391 size is the same regardless of the number of channels - the 392 Multiface still uses the same memory area. 393 394 Note that we allocate 1 more channel than is apparently needed 395 because the h/w seems to write 1 byte beyond the end of the last 396 page. Sigh. 397 */ 398 399 #define HDSP_DMA_AREA_BYTES ((HDSP_MAX_CHANNELS+1) * HDSP_CHANNEL_BUFFER_BYTES) 400 #define HDSP_DMA_AREA_KILOBYTES (HDSP_DMA_AREA_BYTES/1024) 401 402 /* use hotplug firmeare loader? */ 403 #if defined(CONFIG_FW_LOADER) || defined(CONFIG_FW_LOADER_MODULE) 404 #if !defined(HDSP_USE_HWDEP_LOADER) && !defined(CONFIG_SND_HDSP) 405 #define HDSP_FW_LOADER 406 #endif 407 #endif 408 409 struct hdsp_9632_meters { 410 u32 input_peak[16]; 411 u32 playback_peak[16]; 412 u32 output_peak[16]; 413 u32 xxx_peak[16]; 414 u32 padding[64]; 415 u32 input_rms_low[16]; 416 u32 playback_rms_low[16]; 417 u32 output_rms_low[16]; 418 u32 xxx_rms_low[16]; 419 u32 input_rms_high[16]; 420 u32 playback_rms_high[16]; 421 u32 output_rms_high[16]; 422 u32 xxx_rms_high[16]; 423 }; 424 425 struct hdsp_midi { 426 struct hdsp *hdsp; 427 int id; 428 struct snd_rawmidi *rmidi; 429 struct snd_rawmidi_substream *input; 430 struct snd_rawmidi_substream *output; 431 char istimer; /* timer in use */ 432 struct timer_list timer; 433 spinlock_t lock; 434 int pending; 435 }; 436 437 struct hdsp { 438 spinlock_t lock; 439 struct snd_pcm_substream *capture_substream; 440 struct snd_pcm_substream *playback_substream; 441 struct hdsp_midi midi[2]; 442 struct tasklet_struct midi_tasklet; 443 int use_midi_tasklet; 444 int precise_ptr; 445 u32 control_register; /* cached value */ 446 u32 control2_register; /* cached value */ 447 u32 creg_spdif; 448 u32 creg_spdif_stream; 449 int clock_source_locked; 450 char *card_name; /* digiface/multiface */ 451 enum HDSP_IO_Type io_type; /* ditto, but for code use */ 452 unsigned short firmware_rev; 453 unsigned short state; /* stores state bits */ 454 u32 firmware_cache[24413]; /* this helps recover from accidental iobox power failure */ 455 size_t period_bytes; /* guess what this is */ 456 unsigned char max_channels; 457 unsigned char qs_in_channels; /* quad speed mode for H9632 */ 458 unsigned char ds_in_channels; 459 unsigned char ss_in_channels; /* different for multiface/digiface */ 460 unsigned char qs_out_channels; 461 unsigned char ds_out_channels; 462 unsigned char ss_out_channels; 463 464 struct snd_dma_buffer capture_dma_buf; 465 struct snd_dma_buffer playback_dma_buf; 466 unsigned char *capture_buffer; /* suitably aligned address */ 467 unsigned char *playback_buffer; /* suitably aligned address */ 468 469 pid_t capture_pid; 470 pid_t playback_pid; 471 int running; 472 int system_sample_rate; 473 char *channel_map; 474 int dev; 475 int irq; 476 unsigned long port; 477 void __iomem *iobase; 478 struct snd_card *card; 479 struct snd_pcm *pcm; 480 struct snd_hwdep *hwdep; 481 struct pci_dev *pci; 482 struct snd_kcontrol *spdif_ctl; 483 unsigned short mixer_matrix[HDSP_MATRIX_MIXER_SIZE]; 484 unsigned int dds_value; /* last value written to freq register */ 485 }; 486 487 /* These tables map the ALSA channels 1..N to the channels that we 488 need to use in order to find the relevant channel buffer. RME 489 refer to this kind of mapping as between "the ADAT channel and 490 the DMA channel." We index it using the logical audio channel, 491 and the value is the DMA channel (i.e. channel buffer number) 492 where the data for that channel can be read/written from/to. 493 */ 494 495 static char channel_map_df_ss[HDSP_MAX_CHANNELS] = { 496 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 497 18, 19, 20, 21, 22, 23, 24, 25 498 }; 499 500 static char channel_map_mf_ss[HDSP_MAX_CHANNELS] = { /* Multiface */ 501 /* Analog */ 502 0, 1, 2, 3, 4, 5, 6, 7, 503 /* ADAT 2 */ 504 16, 17, 18, 19, 20, 21, 22, 23, 505 /* SPDIF */ 506 24, 25, 507 -1, -1, -1, -1, -1, -1, -1, -1 508 }; 509 510 static char channel_map_ds[HDSP_MAX_CHANNELS] = { 511 /* ADAT channels are remapped */ 512 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 513 /* channels 12 and 13 are S/PDIF */ 514 24, 25, 515 /* others don't exist */ 516 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 517 }; 518 519 static char channel_map_H9632_ss[HDSP_MAX_CHANNELS] = { 520 /* ADAT channels */ 521 0, 1, 2, 3, 4, 5, 6, 7, 522 /* SPDIF */ 523 8, 9, 524 /* Analog */ 525 10, 11, 526 /* AO4S-192 and AI4S-192 extension boards */ 527 12, 13, 14, 15, 528 /* others don't exist */ 529 -1, -1, -1, -1, -1, -1, -1, -1, 530 -1, -1 531 }; 532 533 static char channel_map_H9632_ds[HDSP_MAX_CHANNELS] = { 534 /* ADAT */ 535 1, 3, 5, 7, 536 /* SPDIF */ 537 8, 9, 538 /* Analog */ 539 10, 11, 540 /* AO4S-192 and AI4S-192 extension boards */ 541 12, 13, 14, 15, 542 /* others don't exist */ 543 -1, -1, -1, -1, -1, -1, -1, -1, 544 -1, -1, -1, -1, -1, -1 545 }; 546 547 static char channel_map_H9632_qs[HDSP_MAX_CHANNELS] = { 548 /* ADAT is disabled in this mode */ 549 /* SPDIF */ 550 8, 9, 551 /* Analog */ 552 10, 11, 553 /* AO4S-192 and AI4S-192 extension boards */ 554 12, 13, 14, 15, 555 /* others don't exist */ 556 -1, -1, -1, -1, -1, -1, -1, -1, 557 -1, -1, -1, -1, -1, -1, -1, -1, 558 -1, -1 559 }; 560 561 static int snd_hammerfall_get_buffer(struct pci_dev *pci, struct snd_dma_buffer *dmab, size_t size) 562 { 563 dmab->dev.type = SNDRV_DMA_TYPE_DEV; 564 dmab->dev.dev = snd_dma_pci_data(pci); 565 if (snd_dma_get_reserved_buf(dmab, snd_dma_pci_buf_id(pci))) { 566 if (dmab->bytes >= size) 567 return 0; 568 } 569 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci), 570 size, dmab) < 0) 571 return -ENOMEM; 572 return 0; 573 } 574 575 static void snd_hammerfall_free_buffer(struct snd_dma_buffer *dmab, struct pci_dev *pci) 576 { 577 if (dmab->area) { 578 dmab->dev.dev = NULL; /* make it anonymous */ 579 snd_dma_reserve_buf(dmab, snd_dma_pci_buf_id(pci)); 580 } 581 } 582 583 584 static struct pci_device_id snd_hdsp_ids[] = { 585 { 586 .vendor = PCI_VENDOR_ID_XILINX, 587 .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP, 588 .subvendor = PCI_ANY_ID, 589 .subdevice = PCI_ANY_ID, 590 }, /* RME Hammerfall-DSP */ 591 { 0, }, 592 }; 593 594 MODULE_DEVICE_TABLE(pci, snd_hdsp_ids); 595 596 /* prototypes */ 597 static int snd_hdsp_create_alsa_devices(struct snd_card *card, struct hdsp *hdsp); 598 static int snd_hdsp_create_pcm(struct snd_card *card, struct hdsp *hdsp); 599 static int snd_hdsp_enable_io (struct hdsp *hdsp); 600 static void snd_hdsp_initialize_midi_flush (struct hdsp *hdsp); 601 static void snd_hdsp_initialize_channels (struct hdsp *hdsp); 602 static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout); 603 static int hdsp_autosync_ref(struct hdsp *hdsp); 604 static int snd_hdsp_set_defaults(struct hdsp *hdsp); 605 static void snd_hdsp_9652_enable_mixer (struct hdsp *hdsp); 606 607 static int hdsp_playback_to_output_key (struct hdsp *hdsp, int in, int out) 608 { 609 switch (hdsp->firmware_rev) { 610 case 0xa: 611 return (64 * out) + (32 + (in)); 612 case 0x96: 613 case 0x97: 614 case 0x98: 615 return (32 * out) + (16 + (in)); 616 default: 617 return (52 * out) + (26 + (in)); 618 } 619 } 620 621 static int hdsp_input_to_output_key (struct hdsp *hdsp, int in, int out) 622 { 623 switch (hdsp->firmware_rev) { 624 case 0xa: 625 return (64 * out) + in; 626 case 0x96: 627 case 0x97: 628 case 0x98: 629 return (32 * out) + in; 630 default: 631 return (52 * out) + in; 632 } 633 } 634 635 static void hdsp_write(struct hdsp *hdsp, int reg, int val) 636 { 637 writel(val, hdsp->iobase + reg); 638 } 639 640 static unsigned int hdsp_read(struct hdsp *hdsp, int reg) 641 { 642 return readl (hdsp->iobase + reg); 643 } 644 645 static int hdsp_check_for_iobox (struct hdsp *hdsp) 646 { 647 648 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return 0; 649 if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_ConfigError) { 650 snd_printk ("Hammerfall-DSP: no Digiface or Multiface connected!\n"); 651 hdsp->state &= ~HDSP_FirmwareLoaded; 652 return -EIO; 653 } 654 return 0; 655 656 } 657 658 static int snd_hdsp_load_firmware_from_cache(struct hdsp *hdsp) { 659 660 int i; 661 unsigned long flags; 662 663 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) { 664 665 snd_printk ("Hammerfall-DSP: loading firmware\n"); 666 667 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_PROGRAM); 668 hdsp_write (hdsp, HDSP_fifoData, 0); 669 670 if (hdsp_fifo_wait (hdsp, 0, HDSP_LONG_WAIT)) { 671 snd_printk ("Hammerfall-DSP: timeout waiting for download preparation\n"); 672 return -EIO; 673 } 674 675 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD); 676 677 for (i = 0; i < 24413; ++i) { 678 hdsp_write(hdsp, HDSP_fifoData, hdsp->firmware_cache[i]); 679 if (hdsp_fifo_wait (hdsp, 127, HDSP_LONG_WAIT)) { 680 snd_printk ("Hammerfall-DSP: timeout during firmware loading\n"); 681 return -EIO; 682 } 683 } 684 685 ssleep(3); 686 687 if (hdsp_fifo_wait (hdsp, 0, HDSP_LONG_WAIT)) { 688 snd_printk ("Hammerfall-DSP: timeout at end of firmware loading\n"); 689 return -EIO; 690 } 691 692 #ifdef SNDRV_BIG_ENDIAN 693 hdsp->control2_register = HDSP_BIGENDIAN_MODE; 694 #else 695 hdsp->control2_register = 0; 696 #endif 697 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register); 698 snd_printk ("Hammerfall-DSP: finished firmware loading\n"); 699 700 } 701 if (hdsp->state & HDSP_InitializationComplete) { 702 snd_printk(KERN_INFO "Hammerfall-DSP: firmware loaded from cache, restoring defaults\n"); 703 spin_lock_irqsave(&hdsp->lock, flags); 704 snd_hdsp_set_defaults(hdsp); 705 spin_unlock_irqrestore(&hdsp->lock, flags); 706 } 707 708 hdsp->state |= HDSP_FirmwareLoaded; 709 710 return 0; 711 } 712 713 static int hdsp_get_iobox_version (struct hdsp *hdsp) 714 { 715 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) { 716 717 hdsp_write (hdsp, HDSP_control2Reg, HDSP_PROGRAM); 718 hdsp_write (hdsp, HDSP_fifoData, 0); 719 if (hdsp_fifo_wait (hdsp, 0, HDSP_SHORT_WAIT) < 0) 720 return -EIO; 721 722 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD); 723 hdsp_write (hdsp, HDSP_fifoData, 0); 724 725 if (hdsp_fifo_wait (hdsp, 0, HDSP_SHORT_WAIT)) { 726 hdsp->io_type = Multiface; 727 hdsp_write (hdsp, HDSP_control2Reg, HDSP_VERSION_BIT); 728 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD); 729 hdsp_fifo_wait (hdsp, 0, HDSP_SHORT_WAIT); 730 } else { 731 hdsp->io_type = Digiface; 732 } 733 } else { 734 /* firmware was already loaded, get iobox type */ 735 if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1) 736 hdsp->io_type = Multiface; 737 else 738 hdsp->io_type = Digiface; 739 } 740 return 0; 741 } 742 743 744 #ifdef HDSP_FW_LOADER 745 static int __devinit hdsp_request_fw_loader(struct hdsp *hdsp); 746 #endif 747 748 static int hdsp_check_for_firmware (struct hdsp *hdsp, int load_on_demand) 749 { 750 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) 751 return 0; 752 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) { 753 hdsp->state &= ~HDSP_FirmwareLoaded; 754 if (! load_on_demand) 755 return -EIO; 756 snd_printk(KERN_ERR "Hammerfall-DSP: firmware not present.\n"); 757 /* try to load firmware */ 758 if (! (hdsp->state & HDSP_FirmwareCached)) { 759 #ifdef HDSP_FW_LOADER 760 if (! hdsp_request_fw_loader(hdsp)) 761 return 0; 762 #endif 763 snd_printk(KERN_ERR 764 "Hammerfall-DSP: No firmware loaded nor " 765 "cached, please upload firmware.\n"); 766 return -EIO; 767 } 768 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) { 769 snd_printk(KERN_ERR 770 "Hammerfall-DSP: Firmware loading from " 771 "cache failed, please upload manually.\n"); 772 return -EIO; 773 } 774 } 775 return 0; 776 } 777 778 779 static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout) 780 { 781 int i; 782 783 /* the fifoStatus registers reports on how many words 784 are available in the command FIFO. 785 */ 786 787 for (i = 0; i < timeout; i++) { 788 789 if ((int)(hdsp_read (hdsp, HDSP_fifoStatus) & 0xff) <= count) 790 return 0; 791 792 /* not very friendly, but we only do this during a firmware 793 load and changing the mixer, so we just put up with it. 794 */ 795 796 udelay (100); 797 } 798 799 snd_printk ("Hammerfall-DSP: wait for FIFO status <= %d failed after %d iterations\n", 800 count, timeout); 801 return -1; 802 } 803 804 static int hdsp_read_gain (struct hdsp *hdsp, unsigned int addr) 805 { 806 if (addr >= HDSP_MATRIX_MIXER_SIZE) 807 return 0; 808 809 return hdsp->mixer_matrix[addr]; 810 } 811 812 static int hdsp_write_gain(struct hdsp *hdsp, unsigned int addr, unsigned short data) 813 { 814 unsigned int ad; 815 816 if (addr >= HDSP_MATRIX_MIXER_SIZE) 817 return -1; 818 819 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) { 820 821 /* from martin bjornsen: 822 823 "You can only write dwords to the 824 mixer memory which contain two 825 mixer values in the low and high 826 word. So if you want to change 827 value 0 you have to read value 1 828 from the cache and write both to 829 the first dword in the mixer 830 memory." 831 */ 832 833 if (hdsp->io_type == H9632 && addr >= 512) 834 return 0; 835 836 if (hdsp->io_type == H9652 && addr >= 1352) 837 return 0; 838 839 hdsp->mixer_matrix[addr] = data; 840 841 842 /* `addr' addresses a 16-bit wide address, but 843 the address space accessed via hdsp_write 844 uses byte offsets. put another way, addr 845 varies from 0 to 1351, but to access the 846 corresponding memory location, we need 847 to access 0 to 2703 ... 848 */ 849 ad = addr/2; 850 851 hdsp_write (hdsp, 4096 + (ad*4), 852 (hdsp->mixer_matrix[(addr&0x7fe)+1] << 16) + 853 hdsp->mixer_matrix[addr&0x7fe]); 854 855 return 0; 856 857 } else { 858 859 ad = (addr << 16) + data; 860 861 if (hdsp_fifo_wait(hdsp, 127, HDSP_LONG_WAIT)) 862 return -1; 863 864 hdsp_write (hdsp, HDSP_fifoData, ad); 865 hdsp->mixer_matrix[addr] = data; 866 867 } 868 869 return 0; 870 } 871 872 static int snd_hdsp_use_is_exclusive(struct hdsp *hdsp) 873 { 874 unsigned long flags; 875 int ret = 1; 876 877 spin_lock_irqsave(&hdsp->lock, flags); 878 if ((hdsp->playback_pid != hdsp->capture_pid) && 879 (hdsp->playback_pid >= 0) && (hdsp->capture_pid >= 0)) 880 ret = 0; 881 spin_unlock_irqrestore(&hdsp->lock, flags); 882 return ret; 883 } 884 885 static int hdsp_external_sample_rate (struct hdsp *hdsp) 886 { 887 unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register); 888 unsigned int rate_bits = status2 & HDSP_systemFrequencyMask; 889 890 switch (rate_bits) { 891 case HDSP_systemFrequency32: return 32000; 892 case HDSP_systemFrequency44_1: return 44100; 893 case HDSP_systemFrequency48: return 48000; 894 case HDSP_systemFrequency64: return 64000; 895 case HDSP_systemFrequency88_2: return 88200; 896 case HDSP_systemFrequency96: return 96000; 897 default: 898 return 0; 899 } 900 } 901 902 static int hdsp_spdif_sample_rate(struct hdsp *hdsp) 903 { 904 unsigned int status = hdsp_read(hdsp, HDSP_statusRegister); 905 unsigned int rate_bits = (status & HDSP_spdifFrequencyMask); 906 907 if (status & HDSP_SPDIFErrorFlag) 908 return 0; 909 910 switch (rate_bits) { 911 case HDSP_spdifFrequency32KHz: return 32000; 912 case HDSP_spdifFrequency44_1KHz: return 44100; 913 case HDSP_spdifFrequency48KHz: return 48000; 914 case HDSP_spdifFrequency64KHz: return 64000; 915 case HDSP_spdifFrequency88_2KHz: return 88200; 916 case HDSP_spdifFrequency96KHz: return 96000; 917 case HDSP_spdifFrequency128KHz: 918 if (hdsp->io_type == H9632) return 128000; 919 break; 920 case HDSP_spdifFrequency176_4KHz: 921 if (hdsp->io_type == H9632) return 176400; 922 break; 923 case HDSP_spdifFrequency192KHz: 924 if (hdsp->io_type == H9632) return 192000; 925 break; 926 default: 927 break; 928 } 929 snd_printk ("Hammerfall-DSP: unknown spdif frequency status; bits = 0x%x, status = 0x%x\n", rate_bits, status); 930 return 0; 931 } 932 933 static void hdsp_compute_period_size(struct hdsp *hdsp) 934 { 935 hdsp->period_bytes = 1 << ((hdsp_decode_latency(hdsp->control_register) + 8)); 936 } 937 938 static snd_pcm_uframes_t hdsp_hw_pointer(struct hdsp *hdsp) 939 { 940 int position; 941 942 position = hdsp_read(hdsp, HDSP_statusRegister); 943 944 if (!hdsp->precise_ptr) 945 return (position & HDSP_BufferID) ? (hdsp->period_bytes / 4) : 0; 946 947 position &= HDSP_BufferPositionMask; 948 position /= 4; 949 position &= (hdsp->period_bytes/2) - 1; 950 return position; 951 } 952 953 static void hdsp_reset_hw_pointer(struct hdsp *hdsp) 954 { 955 hdsp_write (hdsp, HDSP_resetPointer, 0); 956 if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152) 957 /* HDSP_resetPointer = HDSP_freqReg, which is strange and 958 * requires (?) to write again DDS value after a reset pointer 959 * (at least, it works like this) */ 960 hdsp_write (hdsp, HDSP_freqReg, hdsp->dds_value); 961 } 962 963 static void hdsp_start_audio(struct hdsp *s) 964 { 965 s->control_register |= (HDSP_AudioInterruptEnable | HDSP_Start); 966 hdsp_write(s, HDSP_controlRegister, s->control_register); 967 } 968 969 static void hdsp_stop_audio(struct hdsp *s) 970 { 971 s->control_register &= ~(HDSP_Start | HDSP_AudioInterruptEnable); 972 hdsp_write(s, HDSP_controlRegister, s->control_register); 973 } 974 975 static void hdsp_silence_playback(struct hdsp *hdsp) 976 { 977 memset(hdsp->playback_buffer, 0, HDSP_DMA_AREA_BYTES); 978 } 979 980 static int hdsp_set_interrupt_interval(struct hdsp *s, unsigned int frames) 981 { 982 int n; 983 984 spin_lock_irq(&s->lock); 985 986 frames >>= 7; 987 n = 0; 988 while (frames) { 989 n++; 990 frames >>= 1; 991 } 992 993 s->control_register &= ~HDSP_LatencyMask; 994 s->control_register |= hdsp_encode_latency(n); 995 996 hdsp_write(s, HDSP_controlRegister, s->control_register); 997 998 hdsp_compute_period_size(s); 999 1000 spin_unlock_irq(&s->lock); 1001 1002 return 0; 1003 } 1004 1005 static void hdsp_set_dds_value(struct hdsp *hdsp, int rate) 1006 { 1007 u64 n; 1008 u32 r; 1009 1010 if (rate >= 112000) 1011 rate /= 4; 1012 else if (rate >= 56000) 1013 rate /= 2; 1014 1015 n = DDS_NUMERATOR; 1016 div64_32(&n, rate, &r); 1017 /* n should be less than 2^32 for being written to FREQ register */ 1018 snd_assert((n >> 32) == 0); 1019 /* HDSP_freqReg and HDSP_resetPointer are the same, so keep the DDS 1020 value to write it after a reset */ 1021 hdsp->dds_value = n; 1022 hdsp_write(hdsp, HDSP_freqReg, hdsp->dds_value); 1023 } 1024 1025 static int hdsp_set_rate(struct hdsp *hdsp, int rate, int called_internally) 1026 { 1027 int reject_if_open = 0; 1028 int current_rate; 1029 int rate_bits; 1030 1031 /* ASSUMPTION: hdsp->lock is either held, or 1032 there is no need for it (e.g. during module 1033 initialization). 1034 */ 1035 1036 if (!(hdsp->control_register & HDSP_ClockModeMaster)) { 1037 if (called_internally) { 1038 /* request from ctl or card initialization */ 1039 snd_printk(KERN_ERR "Hammerfall-DSP: device is not running as a clock master: cannot set sample rate.\n"); 1040 return -1; 1041 } else { 1042 /* hw_param request while in AutoSync mode */ 1043 int external_freq = hdsp_external_sample_rate(hdsp); 1044 int spdif_freq = hdsp_spdif_sample_rate(hdsp); 1045 1046 if ((spdif_freq == external_freq*2) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1)) 1047 snd_printk(KERN_INFO "Hammerfall-DSP: Detected ADAT in double speed mode\n"); 1048 else if (hdsp->io_type == H9632 && (spdif_freq == external_freq*4) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1)) 1049 snd_printk(KERN_INFO "Hammerfall-DSP: Detected ADAT in quad speed mode\n"); 1050 else if (rate != external_freq) { 1051 snd_printk(KERN_INFO "Hammerfall-DSP: No AutoSync source for requested rate\n"); 1052 return -1; 1053 } 1054 } 1055 } 1056 1057 current_rate = hdsp->system_sample_rate; 1058 1059 /* Changing from a "single speed" to a "double speed" rate is 1060 not allowed if any substreams are open. This is because 1061 such a change causes a shift in the location of 1062 the DMA buffers and a reduction in the number of available 1063 buffers. 1064 1065 Note that a similar but essentially insoluble problem 1066 exists for externally-driven rate changes. All we can do 1067 is to flag rate changes in the read/write routines. */ 1068 1069 if (rate > 96000 && hdsp->io_type != H9632) 1070 return -EINVAL; 1071 1072 switch (rate) { 1073 case 32000: 1074 if (current_rate > 48000) 1075 reject_if_open = 1; 1076 rate_bits = HDSP_Frequency32KHz; 1077 break; 1078 case 44100: 1079 if (current_rate > 48000) 1080 reject_if_open = 1; 1081 rate_bits = HDSP_Frequency44_1KHz; 1082 break; 1083 case 48000: 1084 if (current_rate > 48000) 1085 reject_if_open = 1; 1086 rate_bits = HDSP_Frequency48KHz; 1087 break; 1088 case 64000: 1089 if (current_rate <= 48000 || current_rate > 96000) 1090 reject_if_open = 1; 1091 rate_bits = HDSP_Frequency64KHz; 1092 break; 1093 case 88200: 1094 if (current_rate <= 48000 || current_rate > 96000) 1095 reject_if_open = 1; 1096 rate_bits = HDSP_Frequency88_2KHz; 1097 break; 1098 case 96000: 1099 if (current_rate <= 48000 || current_rate > 96000) 1100 reject_if_open = 1; 1101 rate_bits = HDSP_Frequency96KHz; 1102 break; 1103 case 128000: 1104 if (current_rate < 128000) 1105 reject_if_open = 1; 1106 rate_bits = HDSP_Frequency128KHz; 1107 break; 1108 case 176400: 1109 if (current_rate < 128000) 1110 reject_if_open = 1; 1111 rate_bits = HDSP_Frequency176_4KHz; 1112 break; 1113 case 192000: 1114 if (current_rate < 128000) 1115 reject_if_open = 1; 1116 rate_bits = HDSP_Frequency192KHz; 1117 break; 1118 default: 1119 return -EINVAL; 1120 } 1121 1122 if (reject_if_open && (hdsp->capture_pid >= 0 || hdsp->playback_pid >= 0)) { 1123 snd_printk ("Hammerfall-DSP: cannot change speed mode (capture PID = %d, playback PID = %d)\n", 1124 hdsp->capture_pid, 1125 hdsp->playback_pid); 1126 return -EBUSY; 1127 } 1128 1129 hdsp->control_register &= ~HDSP_FrequencyMask; 1130 hdsp->control_register |= rate_bits; 1131 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 1132 1133 /* For HDSP9632 rev 152, need to set DDS value in FREQ register */ 1134 if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152) 1135 hdsp_set_dds_value(hdsp, rate); 1136 1137 if (rate >= 128000) { 1138 hdsp->channel_map = channel_map_H9632_qs; 1139 } else if (rate > 48000) { 1140 if (hdsp->io_type == H9632) 1141 hdsp->channel_map = channel_map_H9632_ds; 1142 else 1143 hdsp->channel_map = channel_map_ds; 1144 } else { 1145 switch (hdsp->io_type) { 1146 case Multiface: 1147 hdsp->channel_map = channel_map_mf_ss; 1148 break; 1149 case Digiface: 1150 case H9652: 1151 hdsp->channel_map = channel_map_df_ss; 1152 break; 1153 case H9632: 1154 hdsp->channel_map = channel_map_H9632_ss; 1155 break; 1156 default: 1157 /* should never happen */ 1158 break; 1159 } 1160 } 1161 1162 hdsp->system_sample_rate = rate; 1163 1164 return 0; 1165 } 1166 1167 /*---------------------------------------------------------------------------- 1168 MIDI 1169 ----------------------------------------------------------------------------*/ 1170 1171 static unsigned char snd_hdsp_midi_read_byte (struct hdsp *hdsp, int id) 1172 { 1173 /* the hardware already does the relevant bit-mask with 0xff */ 1174 if (id) 1175 return hdsp_read(hdsp, HDSP_midiDataIn1); 1176 else 1177 return hdsp_read(hdsp, HDSP_midiDataIn0); 1178 } 1179 1180 static void snd_hdsp_midi_write_byte (struct hdsp *hdsp, int id, int val) 1181 { 1182 /* the hardware already does the relevant bit-mask with 0xff */ 1183 if (id) 1184 hdsp_write(hdsp, HDSP_midiDataOut1, val); 1185 else 1186 hdsp_write(hdsp, HDSP_midiDataOut0, val); 1187 } 1188 1189 static int snd_hdsp_midi_input_available (struct hdsp *hdsp, int id) 1190 { 1191 if (id) 1192 return (hdsp_read(hdsp, HDSP_midiStatusIn1) & 0xff); 1193 else 1194 return (hdsp_read(hdsp, HDSP_midiStatusIn0) & 0xff); 1195 } 1196 1197 static int snd_hdsp_midi_output_possible (struct hdsp *hdsp, int id) 1198 { 1199 int fifo_bytes_used; 1200 1201 if (id) 1202 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut1) & 0xff; 1203 else 1204 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut0) & 0xff; 1205 1206 if (fifo_bytes_used < 128) 1207 return 128 - fifo_bytes_used; 1208 else 1209 return 0; 1210 } 1211 1212 static void snd_hdsp_flush_midi_input (struct hdsp *hdsp, int id) 1213 { 1214 while (snd_hdsp_midi_input_available (hdsp, id)) 1215 snd_hdsp_midi_read_byte (hdsp, id); 1216 } 1217 1218 static int snd_hdsp_midi_output_write (struct hdsp_midi *hmidi) 1219 { 1220 unsigned long flags; 1221 int n_pending; 1222 int to_write; 1223 int i; 1224 unsigned char buf[128]; 1225 1226 /* Output is not interrupt driven */ 1227 1228 spin_lock_irqsave (&hmidi->lock, flags); 1229 if (hmidi->output) { 1230 if (!snd_rawmidi_transmit_empty (hmidi->output)) { 1231 if ((n_pending = snd_hdsp_midi_output_possible (hmidi->hdsp, hmidi->id)) > 0) { 1232 if (n_pending > (int)sizeof (buf)) 1233 n_pending = sizeof (buf); 1234 1235 if ((to_write = snd_rawmidi_transmit (hmidi->output, buf, n_pending)) > 0) { 1236 for (i = 0; i < to_write; ++i) 1237 snd_hdsp_midi_write_byte (hmidi->hdsp, hmidi->id, buf[i]); 1238 } 1239 } 1240 } 1241 } 1242 spin_unlock_irqrestore (&hmidi->lock, flags); 1243 return 0; 1244 } 1245 1246 static int snd_hdsp_midi_input_read (struct hdsp_midi *hmidi) 1247 { 1248 unsigned char buf[128]; /* this buffer is designed to match the MIDI input FIFO size */ 1249 unsigned long flags; 1250 int n_pending; 1251 int i; 1252 1253 spin_lock_irqsave (&hmidi->lock, flags); 1254 if ((n_pending = snd_hdsp_midi_input_available (hmidi->hdsp, hmidi->id)) > 0) { 1255 if (hmidi->input) { 1256 if (n_pending > (int)sizeof (buf)) 1257 n_pending = sizeof (buf); 1258 for (i = 0; i < n_pending; ++i) 1259 buf[i] = snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id); 1260 if (n_pending) 1261 snd_rawmidi_receive (hmidi->input, buf, n_pending); 1262 } else { 1263 /* flush the MIDI input FIFO */ 1264 while (--n_pending) 1265 snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id); 1266 } 1267 } 1268 hmidi->pending = 0; 1269 if (hmidi->id) 1270 hmidi->hdsp->control_register |= HDSP_Midi1InterruptEnable; 1271 else 1272 hmidi->hdsp->control_register |= HDSP_Midi0InterruptEnable; 1273 hdsp_write(hmidi->hdsp, HDSP_controlRegister, hmidi->hdsp->control_register); 1274 spin_unlock_irqrestore (&hmidi->lock, flags); 1275 return snd_hdsp_midi_output_write (hmidi); 1276 } 1277 1278 static void snd_hdsp_midi_input_trigger(struct snd_rawmidi_substream *substream, int up) 1279 { 1280 struct hdsp *hdsp; 1281 struct hdsp_midi *hmidi; 1282 unsigned long flags; 1283 u32 ie; 1284 1285 hmidi = (struct hdsp_midi *) substream->rmidi->private_data; 1286 hdsp = hmidi->hdsp; 1287 ie = hmidi->id ? HDSP_Midi1InterruptEnable : HDSP_Midi0InterruptEnable; 1288 spin_lock_irqsave (&hdsp->lock, flags); 1289 if (up) { 1290 if (!(hdsp->control_register & ie)) { 1291 snd_hdsp_flush_midi_input (hdsp, hmidi->id); 1292 hdsp->control_register |= ie; 1293 } 1294 } else { 1295 hdsp->control_register &= ~ie; 1296 tasklet_kill(&hdsp->midi_tasklet); 1297 } 1298 1299 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 1300 spin_unlock_irqrestore (&hdsp->lock, flags); 1301 } 1302 1303 static void snd_hdsp_midi_output_timer(unsigned long data) 1304 { 1305 struct hdsp_midi *hmidi = (struct hdsp_midi *) data; 1306 unsigned long flags; 1307 1308 snd_hdsp_midi_output_write(hmidi); 1309 spin_lock_irqsave (&hmidi->lock, flags); 1310 1311 /* this does not bump hmidi->istimer, because the 1312 kernel automatically removed the timer when it 1313 expired, and we are now adding it back, thus 1314 leaving istimer wherever it was set before. 1315 */ 1316 1317 if (hmidi->istimer) { 1318 hmidi->timer.expires = 1 + jiffies; 1319 add_timer(&hmidi->timer); 1320 } 1321 1322 spin_unlock_irqrestore (&hmidi->lock, flags); 1323 } 1324 1325 static void snd_hdsp_midi_output_trigger(struct snd_rawmidi_substream *substream, int up) 1326 { 1327 struct hdsp_midi *hmidi; 1328 unsigned long flags; 1329 1330 hmidi = (struct hdsp_midi *) substream->rmidi->private_data; 1331 spin_lock_irqsave (&hmidi->lock, flags); 1332 if (up) { 1333 if (!hmidi->istimer) { 1334 init_timer(&hmidi->timer); 1335 hmidi->timer.function = snd_hdsp_midi_output_timer; 1336 hmidi->timer.data = (unsigned long) hmidi; 1337 hmidi->timer.expires = 1 + jiffies; 1338 add_timer(&hmidi->timer); 1339 hmidi->istimer++; 1340 } 1341 } else { 1342 if (hmidi->istimer && --hmidi->istimer <= 0) 1343 del_timer (&hmidi->timer); 1344 } 1345 spin_unlock_irqrestore (&hmidi->lock, flags); 1346 if (up) 1347 snd_hdsp_midi_output_write(hmidi); 1348 } 1349 1350 static int snd_hdsp_midi_input_open(struct snd_rawmidi_substream *substream) 1351 { 1352 struct hdsp_midi *hmidi; 1353 1354 hmidi = (struct hdsp_midi *) substream->rmidi->private_data; 1355 spin_lock_irq (&hmidi->lock); 1356 snd_hdsp_flush_midi_input (hmidi->hdsp, hmidi->id); 1357 hmidi->input = substream; 1358 spin_unlock_irq (&hmidi->lock); 1359 1360 return 0; 1361 } 1362 1363 static int snd_hdsp_midi_output_open(struct snd_rawmidi_substream *substream) 1364 { 1365 struct hdsp_midi *hmidi; 1366 1367 hmidi = (struct hdsp_midi *) substream->rmidi->private_data; 1368 spin_lock_irq (&hmidi->lock); 1369 hmidi->output = substream; 1370 spin_unlock_irq (&hmidi->lock); 1371 1372 return 0; 1373 } 1374 1375 static int snd_hdsp_midi_input_close(struct snd_rawmidi_substream *substream) 1376 { 1377 struct hdsp_midi *hmidi; 1378 1379 snd_hdsp_midi_input_trigger (substream, 0); 1380 1381 hmidi = (struct hdsp_midi *) substream->rmidi->private_data; 1382 spin_lock_irq (&hmidi->lock); 1383 hmidi->input = NULL; 1384 spin_unlock_irq (&hmidi->lock); 1385 1386 return 0; 1387 } 1388 1389 static int snd_hdsp_midi_output_close(struct snd_rawmidi_substream *substream) 1390 { 1391 struct hdsp_midi *hmidi; 1392 1393 snd_hdsp_midi_output_trigger (substream, 0); 1394 1395 hmidi = (struct hdsp_midi *) substream->rmidi->private_data; 1396 spin_lock_irq (&hmidi->lock); 1397 hmidi->output = NULL; 1398 spin_unlock_irq (&hmidi->lock); 1399 1400 return 0; 1401 } 1402 1403 static struct snd_rawmidi_ops snd_hdsp_midi_output = 1404 { 1405 .open = snd_hdsp_midi_output_open, 1406 .close = snd_hdsp_midi_output_close, 1407 .trigger = snd_hdsp_midi_output_trigger, 1408 }; 1409 1410 static struct snd_rawmidi_ops snd_hdsp_midi_input = 1411 { 1412 .open = snd_hdsp_midi_input_open, 1413 .close = snd_hdsp_midi_input_close, 1414 .trigger = snd_hdsp_midi_input_trigger, 1415 }; 1416 1417 static int snd_hdsp_create_midi (struct snd_card *card, struct hdsp *hdsp, int id) 1418 { 1419 char buf[32]; 1420 1421 hdsp->midi[id].id = id; 1422 hdsp->midi[id].rmidi = NULL; 1423 hdsp->midi[id].input = NULL; 1424 hdsp->midi[id].output = NULL; 1425 hdsp->midi[id].hdsp = hdsp; 1426 hdsp->midi[id].istimer = 0; 1427 hdsp->midi[id].pending = 0; 1428 spin_lock_init (&hdsp->midi[id].lock); 1429 1430 sprintf (buf, "%s MIDI %d", card->shortname, id+1); 1431 if (snd_rawmidi_new (card, buf, id, 1, 1, &hdsp->midi[id].rmidi) < 0) 1432 return -1; 1433 1434 sprintf (hdsp->midi[id].rmidi->name, "%s MIDI %d", card->id, id+1); 1435 hdsp->midi[id].rmidi->private_data = &hdsp->midi[id]; 1436 1437 snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_hdsp_midi_output); 1438 snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_hdsp_midi_input); 1439 1440 hdsp->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | 1441 SNDRV_RAWMIDI_INFO_INPUT | 1442 SNDRV_RAWMIDI_INFO_DUPLEX; 1443 1444 return 0; 1445 } 1446 1447 /*----------------------------------------------------------------------------- 1448 Control Interface 1449 ----------------------------------------------------------------------------*/ 1450 1451 static u32 snd_hdsp_convert_from_aes(struct snd_aes_iec958 *aes) 1452 { 1453 u32 val = 0; 1454 val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? HDSP_SPDIFProfessional : 0; 1455 val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? HDSP_SPDIFNonAudio : 0; 1456 if (val & HDSP_SPDIFProfessional) 1457 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0; 1458 else 1459 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0; 1460 return val; 1461 } 1462 1463 static void snd_hdsp_convert_to_aes(struct snd_aes_iec958 *aes, u32 val) 1464 { 1465 aes->status[0] = ((val & HDSP_SPDIFProfessional) ? IEC958_AES0_PROFESSIONAL : 0) | 1466 ((val & HDSP_SPDIFNonAudio) ? IEC958_AES0_NONAUDIO : 0); 1467 if (val & HDSP_SPDIFProfessional) 1468 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0; 1469 else 1470 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_CON_EMPHASIS_5015 : 0; 1471 } 1472 1473 static int snd_hdsp_control_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 1474 { 1475 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 1476 uinfo->count = 1; 1477 return 0; 1478 } 1479 1480 static int snd_hdsp_control_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1481 { 1482 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1483 1484 snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif); 1485 return 0; 1486 } 1487 1488 static int snd_hdsp_control_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1489 { 1490 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1491 int change; 1492 u32 val; 1493 1494 val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958); 1495 spin_lock_irq(&hdsp->lock); 1496 change = val != hdsp->creg_spdif; 1497 hdsp->creg_spdif = val; 1498 spin_unlock_irq(&hdsp->lock); 1499 return change; 1500 } 1501 1502 static int snd_hdsp_control_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 1503 { 1504 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 1505 uinfo->count = 1; 1506 return 0; 1507 } 1508 1509 static int snd_hdsp_control_spdif_stream_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1510 { 1511 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1512 1513 snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif_stream); 1514 return 0; 1515 } 1516 1517 static int snd_hdsp_control_spdif_stream_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1518 { 1519 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1520 int change; 1521 u32 val; 1522 1523 val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958); 1524 spin_lock_irq(&hdsp->lock); 1525 change = val != hdsp->creg_spdif_stream; 1526 hdsp->creg_spdif_stream = val; 1527 hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis); 1528 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= val); 1529 spin_unlock_irq(&hdsp->lock); 1530 return change; 1531 } 1532 1533 static int snd_hdsp_control_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 1534 { 1535 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 1536 uinfo->count = 1; 1537 return 0; 1538 } 1539 1540 static int snd_hdsp_control_spdif_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1541 { 1542 ucontrol->value.iec958.status[0] = kcontrol->private_value; 1543 return 0; 1544 } 1545 1546 #define HDSP_SPDIF_IN(xname, xindex) \ 1547 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 1548 .name = xname, \ 1549 .index = xindex, \ 1550 .info = snd_hdsp_info_spdif_in, \ 1551 .get = snd_hdsp_get_spdif_in, \ 1552 .put = snd_hdsp_put_spdif_in } 1553 1554 static unsigned int hdsp_spdif_in(struct hdsp *hdsp) 1555 { 1556 return hdsp_decode_spdif_in(hdsp->control_register & HDSP_SPDIFInputMask); 1557 } 1558 1559 static int hdsp_set_spdif_input(struct hdsp *hdsp, int in) 1560 { 1561 hdsp->control_register &= ~HDSP_SPDIFInputMask; 1562 hdsp->control_register |= hdsp_encode_spdif_in(in); 1563 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 1564 return 0; 1565 } 1566 1567 static int snd_hdsp_info_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 1568 { 1569 static char *texts[4] = {"Optical", "Coaxial", "Internal", "AES"}; 1570 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1571 1572 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 1573 uinfo->count = 1; 1574 uinfo->value.enumerated.items = ((hdsp->io_type == H9632) ? 4 : 3); 1575 if (uinfo->value.enumerated.item > ((hdsp->io_type == H9632) ? 3 : 2)) 1576 uinfo->value.enumerated.item = ((hdsp->io_type == H9632) ? 3 : 2); 1577 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); 1578 return 0; 1579 } 1580 1581 static int snd_hdsp_get_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1582 { 1583 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1584 1585 ucontrol->value.enumerated.item[0] = hdsp_spdif_in(hdsp); 1586 return 0; 1587 } 1588 1589 static int snd_hdsp_put_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1590 { 1591 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1592 int change; 1593 unsigned int val; 1594 1595 if (!snd_hdsp_use_is_exclusive(hdsp)) 1596 return -EBUSY; 1597 val = ucontrol->value.enumerated.item[0] % ((hdsp->io_type == H9632) ? 4 : 3); 1598 spin_lock_irq(&hdsp->lock); 1599 change = val != hdsp_spdif_in(hdsp); 1600 if (change) 1601 hdsp_set_spdif_input(hdsp, val); 1602 spin_unlock_irq(&hdsp->lock); 1603 return change; 1604 } 1605 1606 #define HDSP_SPDIF_OUT(xname, xindex) \ 1607 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \ 1608 .info = snd_hdsp_info_spdif_bits, \ 1609 .get = snd_hdsp_get_spdif_out, .put = snd_hdsp_put_spdif_out } 1610 1611 static int hdsp_spdif_out(struct hdsp *hdsp) 1612 { 1613 return (hdsp->control_register & HDSP_SPDIFOpticalOut) ? 1 : 0; 1614 } 1615 1616 static int hdsp_set_spdif_output(struct hdsp *hdsp, int out) 1617 { 1618 if (out) 1619 hdsp->control_register |= HDSP_SPDIFOpticalOut; 1620 else 1621 hdsp->control_register &= ~HDSP_SPDIFOpticalOut; 1622 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 1623 return 0; 1624 } 1625 1626 static int snd_hdsp_info_spdif_bits(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 1627 { 1628 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 1629 uinfo->count = 1; 1630 uinfo->value.integer.min = 0; 1631 uinfo->value.integer.max = 1; 1632 return 0; 1633 } 1634 1635 static int snd_hdsp_get_spdif_out(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1636 { 1637 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1638 1639 ucontrol->value.integer.value[0] = hdsp_spdif_out(hdsp); 1640 return 0; 1641 } 1642 1643 static int snd_hdsp_put_spdif_out(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1644 { 1645 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1646 int change; 1647 unsigned int val; 1648 1649 if (!snd_hdsp_use_is_exclusive(hdsp)) 1650 return -EBUSY; 1651 val = ucontrol->value.integer.value[0] & 1; 1652 spin_lock_irq(&hdsp->lock); 1653 change = (int)val != hdsp_spdif_out(hdsp); 1654 hdsp_set_spdif_output(hdsp, val); 1655 spin_unlock_irq(&hdsp->lock); 1656 return change; 1657 } 1658 1659 #define HDSP_SPDIF_PROFESSIONAL(xname, xindex) \ 1660 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \ 1661 .info = snd_hdsp_info_spdif_bits, \ 1662 .get = snd_hdsp_get_spdif_professional, .put = snd_hdsp_put_spdif_professional } 1663 1664 static int hdsp_spdif_professional(struct hdsp *hdsp) 1665 { 1666 return (hdsp->control_register & HDSP_SPDIFProfessional) ? 1 : 0; 1667 } 1668 1669 static int hdsp_set_spdif_professional(struct hdsp *hdsp, int val) 1670 { 1671 if (val) 1672 hdsp->control_register |= HDSP_SPDIFProfessional; 1673 else 1674 hdsp->control_register &= ~HDSP_SPDIFProfessional; 1675 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 1676 return 0; 1677 } 1678 1679 static int snd_hdsp_get_spdif_professional(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1680 { 1681 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1682 1683 ucontrol->value.integer.value[0] = hdsp_spdif_professional(hdsp); 1684 return 0; 1685 } 1686 1687 static int snd_hdsp_put_spdif_professional(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1688 { 1689 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1690 int change; 1691 unsigned int val; 1692 1693 if (!snd_hdsp_use_is_exclusive(hdsp)) 1694 return -EBUSY; 1695 val = ucontrol->value.integer.value[0] & 1; 1696 spin_lock_irq(&hdsp->lock); 1697 change = (int)val != hdsp_spdif_professional(hdsp); 1698 hdsp_set_spdif_professional(hdsp, val); 1699 spin_unlock_irq(&hdsp->lock); 1700 return change; 1701 } 1702 1703 #define HDSP_SPDIF_EMPHASIS(xname, xindex) \ 1704 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \ 1705 .info = snd_hdsp_info_spdif_bits, \ 1706 .get = snd_hdsp_get_spdif_emphasis, .put = snd_hdsp_put_spdif_emphasis } 1707 1708 static int hdsp_spdif_emphasis(struct hdsp *hdsp) 1709 { 1710 return (hdsp->control_register & HDSP_SPDIFEmphasis) ? 1 : 0; 1711 } 1712 1713 static int hdsp_set_spdif_emphasis(struct hdsp *hdsp, int val) 1714 { 1715 if (val) 1716 hdsp->control_register |= HDSP_SPDIFEmphasis; 1717 else 1718 hdsp->control_register &= ~HDSP_SPDIFEmphasis; 1719 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 1720 return 0; 1721 } 1722 1723 static int snd_hdsp_get_spdif_emphasis(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1724 { 1725 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1726 1727 ucontrol->value.integer.value[0] = hdsp_spdif_emphasis(hdsp); 1728 return 0; 1729 } 1730 1731 static int snd_hdsp_put_spdif_emphasis(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1732 { 1733 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1734 int change; 1735 unsigned int val; 1736 1737 if (!snd_hdsp_use_is_exclusive(hdsp)) 1738 return -EBUSY; 1739 val = ucontrol->value.integer.value[0] & 1; 1740 spin_lock_irq(&hdsp->lock); 1741 change = (int)val != hdsp_spdif_emphasis(hdsp); 1742 hdsp_set_spdif_emphasis(hdsp, val); 1743 spin_unlock_irq(&hdsp->lock); 1744 return change; 1745 } 1746 1747 #define HDSP_SPDIF_NON_AUDIO(xname, xindex) \ 1748 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \ 1749 .info = snd_hdsp_info_spdif_bits, \ 1750 .get = snd_hdsp_get_spdif_nonaudio, .put = snd_hdsp_put_spdif_nonaudio } 1751 1752 static int hdsp_spdif_nonaudio(struct hdsp *hdsp) 1753 { 1754 return (hdsp->control_register & HDSP_SPDIFNonAudio) ? 1 : 0; 1755 } 1756 1757 static int hdsp_set_spdif_nonaudio(struct hdsp *hdsp, int val) 1758 { 1759 if (val) 1760 hdsp->control_register |= HDSP_SPDIFNonAudio; 1761 else 1762 hdsp->control_register &= ~HDSP_SPDIFNonAudio; 1763 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 1764 return 0; 1765 } 1766 1767 static int snd_hdsp_get_spdif_nonaudio(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1768 { 1769 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1770 1771 ucontrol->value.integer.value[0] = hdsp_spdif_nonaudio(hdsp); 1772 return 0; 1773 } 1774 1775 static int snd_hdsp_put_spdif_nonaudio(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1776 { 1777 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1778 int change; 1779 unsigned int val; 1780 1781 if (!snd_hdsp_use_is_exclusive(hdsp)) 1782 return -EBUSY; 1783 val = ucontrol->value.integer.value[0] & 1; 1784 spin_lock_irq(&hdsp->lock); 1785 change = (int)val != hdsp_spdif_nonaudio(hdsp); 1786 hdsp_set_spdif_nonaudio(hdsp, val); 1787 spin_unlock_irq(&hdsp->lock); 1788 return change; 1789 } 1790 1791 #define HDSP_SPDIF_SAMPLE_RATE(xname, xindex) \ 1792 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 1793 .name = xname, \ 1794 .index = xindex, \ 1795 .access = SNDRV_CTL_ELEM_ACCESS_READ, \ 1796 .info = snd_hdsp_info_spdif_sample_rate, \ 1797 .get = snd_hdsp_get_spdif_sample_rate \ 1798 } 1799 1800 static int snd_hdsp_info_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 1801 { 1802 static char *texts[] = {"32000", "44100", "48000", "64000", "88200", "96000", "None", "128000", "176400", "192000"}; 1803 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1804 1805 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 1806 uinfo->count = 1; 1807 uinfo->value.enumerated.items = (hdsp->io_type == H9632) ? 10 : 7; 1808 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 1809 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; 1810 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); 1811 return 0; 1812 } 1813 1814 static int snd_hdsp_get_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1815 { 1816 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1817 1818 switch (hdsp_spdif_sample_rate(hdsp)) { 1819 case 32000: 1820 ucontrol->value.enumerated.item[0] = 0; 1821 break; 1822 case 44100: 1823 ucontrol->value.enumerated.item[0] = 1; 1824 break; 1825 case 48000: 1826 ucontrol->value.enumerated.item[0] = 2; 1827 break; 1828 case 64000: 1829 ucontrol->value.enumerated.item[0] = 3; 1830 break; 1831 case 88200: 1832 ucontrol->value.enumerated.item[0] = 4; 1833 break; 1834 case 96000: 1835 ucontrol->value.enumerated.item[0] = 5; 1836 break; 1837 case 128000: 1838 ucontrol->value.enumerated.item[0] = 7; 1839 break; 1840 case 176400: 1841 ucontrol->value.enumerated.item[0] = 8; 1842 break; 1843 case 192000: 1844 ucontrol->value.enumerated.item[0] = 9; 1845 break; 1846 default: 1847 ucontrol->value.enumerated.item[0] = 6; 1848 } 1849 return 0; 1850 } 1851 1852 #define HDSP_SYSTEM_SAMPLE_RATE(xname, xindex) \ 1853 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 1854 .name = xname, \ 1855 .index = xindex, \ 1856 .access = SNDRV_CTL_ELEM_ACCESS_READ, \ 1857 .info = snd_hdsp_info_system_sample_rate, \ 1858 .get = snd_hdsp_get_system_sample_rate \ 1859 } 1860 1861 static int snd_hdsp_info_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 1862 { 1863 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 1864 uinfo->count = 1; 1865 return 0; 1866 } 1867 1868 static int snd_hdsp_get_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1869 { 1870 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1871 1872 ucontrol->value.enumerated.item[0] = hdsp->system_sample_rate; 1873 return 0; 1874 } 1875 1876 #define HDSP_AUTOSYNC_SAMPLE_RATE(xname, xindex) \ 1877 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 1878 .name = xname, \ 1879 .index = xindex, \ 1880 .access = SNDRV_CTL_ELEM_ACCESS_READ, \ 1881 .info = snd_hdsp_info_autosync_sample_rate, \ 1882 .get = snd_hdsp_get_autosync_sample_rate \ 1883 } 1884 1885 static int snd_hdsp_info_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 1886 { 1887 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1888 static char *texts[] = {"32000", "44100", "48000", "64000", "88200", "96000", "None", "128000", "176400", "192000"}; 1889 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 1890 uinfo->count = 1; 1891 uinfo->value.enumerated.items = (hdsp->io_type == H9632) ? 10 : 7 ; 1892 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 1893 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; 1894 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); 1895 return 0; 1896 } 1897 1898 static int snd_hdsp_get_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1899 { 1900 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1901 1902 switch (hdsp_external_sample_rate(hdsp)) { 1903 case 32000: 1904 ucontrol->value.enumerated.item[0] = 0; 1905 break; 1906 case 44100: 1907 ucontrol->value.enumerated.item[0] = 1; 1908 break; 1909 case 48000: 1910 ucontrol->value.enumerated.item[0] = 2; 1911 break; 1912 case 64000: 1913 ucontrol->value.enumerated.item[0] = 3; 1914 break; 1915 case 88200: 1916 ucontrol->value.enumerated.item[0] = 4; 1917 break; 1918 case 96000: 1919 ucontrol->value.enumerated.item[0] = 5; 1920 break; 1921 case 128000: 1922 ucontrol->value.enumerated.item[0] = 7; 1923 break; 1924 case 176400: 1925 ucontrol->value.enumerated.item[0] = 8; 1926 break; 1927 case 192000: 1928 ucontrol->value.enumerated.item[0] = 9; 1929 break; 1930 default: 1931 ucontrol->value.enumerated.item[0] = 6; 1932 } 1933 return 0; 1934 } 1935 1936 #define HDSP_SYSTEM_CLOCK_MODE(xname, xindex) \ 1937 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 1938 .name = xname, \ 1939 .index = xindex, \ 1940 .access = SNDRV_CTL_ELEM_ACCESS_READ, \ 1941 .info = snd_hdsp_info_system_clock_mode, \ 1942 .get = snd_hdsp_get_system_clock_mode \ 1943 } 1944 1945 static int hdsp_system_clock_mode(struct hdsp *hdsp) 1946 { 1947 if (hdsp->control_register & HDSP_ClockModeMaster) 1948 return 0; 1949 else if (hdsp_external_sample_rate(hdsp) != hdsp->system_sample_rate) 1950 return 0; 1951 return 1; 1952 } 1953 1954 static int snd_hdsp_info_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 1955 { 1956 static char *texts[] = {"Master", "Slave" }; 1957 1958 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 1959 uinfo->count = 1; 1960 uinfo->value.enumerated.items = 2; 1961 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 1962 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; 1963 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); 1964 return 0; 1965 } 1966 1967 static int snd_hdsp_get_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1968 { 1969 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1970 1971 ucontrol->value.enumerated.item[0] = hdsp_system_clock_mode(hdsp); 1972 return 0; 1973 } 1974 1975 #define HDSP_CLOCK_SOURCE(xname, xindex) \ 1976 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 1977 .name = xname, \ 1978 .index = xindex, \ 1979 .info = snd_hdsp_info_clock_source, \ 1980 .get = snd_hdsp_get_clock_source, \ 1981 .put = snd_hdsp_put_clock_source \ 1982 } 1983 1984 static int hdsp_clock_source(struct hdsp *hdsp) 1985 { 1986 if (hdsp->control_register & HDSP_ClockModeMaster) { 1987 switch (hdsp->system_sample_rate) { 1988 case 32000: 1989 return 1; 1990 case 44100: 1991 return 2; 1992 case 48000: 1993 return 3; 1994 case 64000: 1995 return 4; 1996 case 88200: 1997 return 5; 1998 case 96000: 1999 return 6; 2000 case 128000: 2001 return 7; 2002 case 176400: 2003 return 8; 2004 case 192000: 2005 return 9; 2006 default: 2007 return 3; 2008 } 2009 } else { 2010 return 0; 2011 } 2012 } 2013 2014 static int hdsp_set_clock_source(struct hdsp *hdsp, int mode) 2015 { 2016 int rate; 2017 switch (mode) { 2018 case HDSP_CLOCK_SOURCE_AUTOSYNC: 2019 if (hdsp_external_sample_rate(hdsp) != 0) { 2020 if (!hdsp_set_rate(hdsp, hdsp_external_sample_rate(hdsp), 1)) { 2021 hdsp->control_register &= ~HDSP_ClockModeMaster; 2022 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 2023 return 0; 2024 } 2025 } 2026 return -1; 2027 case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ: 2028 rate = 32000; 2029 break; 2030 case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ: 2031 rate = 44100; 2032 break; 2033 case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ: 2034 rate = 48000; 2035 break; 2036 case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ: 2037 rate = 64000; 2038 break; 2039 case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ: 2040 rate = 88200; 2041 break; 2042 case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ: 2043 rate = 96000; 2044 break; 2045 case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ: 2046 rate = 128000; 2047 break; 2048 case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ: 2049 rate = 176400; 2050 break; 2051 case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ: 2052 rate = 192000; 2053 break; 2054 default: 2055 rate = 48000; 2056 } 2057 hdsp->control_register |= HDSP_ClockModeMaster; 2058 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 2059 hdsp_set_rate(hdsp, rate, 1); 2060 return 0; 2061 } 2062 2063 static int snd_hdsp_info_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2064 { 2065 static char *texts[] = {"AutoSync", "Internal 32.0 kHz", "Internal 44.1 kHz", "Internal 48.0 kHz", "Internal 64.0 kHz", "Internal 88.2 kHz", "Internal 96.0 kHz", "Internal 128 kHz", "Internal 176.4 kHz", "Internal 192.0 KHz" }; 2066 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2067 2068 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2069 uinfo->count = 1; 2070 if (hdsp->io_type == H9632) 2071 uinfo->value.enumerated.items = 10; 2072 else 2073 uinfo->value.enumerated.items = 7; 2074 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 2075 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; 2076 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); 2077 return 0; 2078 } 2079 2080 static int snd_hdsp_get_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2081 { 2082 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2083 2084 ucontrol->value.enumerated.item[0] = hdsp_clock_source(hdsp); 2085 return 0; 2086 } 2087 2088 static int snd_hdsp_put_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2089 { 2090 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2091 int change; 2092 int val; 2093 2094 if (!snd_hdsp_use_is_exclusive(hdsp)) 2095 return -EBUSY; 2096 val = ucontrol->value.enumerated.item[0]; 2097 if (val < 0) val = 0; 2098 if (hdsp->io_type == H9632) { 2099 if (val > 9) 2100 val = 9; 2101 } else { 2102 if (val > 6) 2103 val = 6; 2104 } 2105 spin_lock_irq(&hdsp->lock); 2106 if (val != hdsp_clock_source(hdsp)) 2107 change = (hdsp_set_clock_source(hdsp, val) == 0) ? 1 : 0; 2108 else 2109 change = 0; 2110 spin_unlock_irq(&hdsp->lock); 2111 return change; 2112 } 2113 2114 static int snd_hdsp_info_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2115 { 2116 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 2117 uinfo->count = 1; 2118 uinfo->value.integer.min = 0; 2119 uinfo->value.integer.max = 1; 2120 return 0; 2121 } 2122 2123 static int snd_hdsp_get_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2124 { 2125 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2126 2127 ucontrol->value.integer.value[0] = hdsp->clock_source_locked; 2128 return 0; 2129 } 2130 2131 static int snd_hdsp_put_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2132 { 2133 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2134 int change; 2135 2136 change = (int)ucontrol->value.integer.value[0] != hdsp->clock_source_locked; 2137 if (change) 2138 hdsp->clock_source_locked = ucontrol->value.integer.value[0]; 2139 return change; 2140 } 2141 2142 #define HDSP_DA_GAIN(xname, xindex) \ 2143 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2144 .name = xname, \ 2145 .index = xindex, \ 2146 .info = snd_hdsp_info_da_gain, \ 2147 .get = snd_hdsp_get_da_gain, \ 2148 .put = snd_hdsp_put_da_gain \ 2149 } 2150 2151 static int hdsp_da_gain(struct hdsp *hdsp) 2152 { 2153 switch (hdsp->control_register & HDSP_DAGainMask) { 2154 case HDSP_DAGainHighGain: 2155 return 0; 2156 case HDSP_DAGainPlus4dBu: 2157 return 1; 2158 case HDSP_DAGainMinus10dBV: 2159 return 2; 2160 default: 2161 return 1; 2162 } 2163 } 2164 2165 static int hdsp_set_da_gain(struct hdsp *hdsp, int mode) 2166 { 2167 hdsp->control_register &= ~HDSP_DAGainMask; 2168 switch (mode) { 2169 case 0: 2170 hdsp->control_register |= HDSP_DAGainHighGain; 2171 break; 2172 case 1: 2173 hdsp->control_register |= HDSP_DAGainPlus4dBu; 2174 break; 2175 case 2: 2176 hdsp->control_register |= HDSP_DAGainMinus10dBV; 2177 break; 2178 default: 2179 return -1; 2180 2181 } 2182 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 2183 return 0; 2184 } 2185 2186 static int snd_hdsp_info_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2187 { 2188 static char *texts[] = {"Hi Gain", "+4 dBu", "-10 dbV"}; 2189 2190 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2191 uinfo->count = 1; 2192 uinfo->value.enumerated.items = 3; 2193 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 2194 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; 2195 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); 2196 return 0; 2197 } 2198 2199 static int snd_hdsp_get_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2200 { 2201 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2202 2203 ucontrol->value.enumerated.item[0] = hdsp_da_gain(hdsp); 2204 return 0; 2205 } 2206 2207 static int snd_hdsp_put_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2208 { 2209 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2210 int change; 2211 int val; 2212 2213 if (!snd_hdsp_use_is_exclusive(hdsp)) 2214 return -EBUSY; 2215 val = ucontrol->value.enumerated.item[0]; 2216 if (val < 0) val = 0; 2217 if (val > 2) val = 2; 2218 spin_lock_irq(&hdsp->lock); 2219 if (val != hdsp_da_gain(hdsp)) 2220 change = (hdsp_set_da_gain(hdsp, val) == 0) ? 1 : 0; 2221 else 2222 change = 0; 2223 spin_unlock_irq(&hdsp->lock); 2224 return change; 2225 } 2226 2227 #define HDSP_AD_GAIN(xname, xindex) \ 2228 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2229 .name = xname, \ 2230 .index = xindex, \ 2231 .info = snd_hdsp_info_ad_gain, \ 2232 .get = snd_hdsp_get_ad_gain, \ 2233 .put = snd_hdsp_put_ad_gain \ 2234 } 2235 2236 static int hdsp_ad_gain(struct hdsp *hdsp) 2237 { 2238 switch (hdsp->control_register & HDSP_ADGainMask) { 2239 case HDSP_ADGainMinus10dBV: 2240 return 0; 2241 case HDSP_ADGainPlus4dBu: 2242 return 1; 2243 case HDSP_ADGainLowGain: 2244 return 2; 2245 default: 2246 return 1; 2247 } 2248 } 2249 2250 static int hdsp_set_ad_gain(struct hdsp *hdsp, int mode) 2251 { 2252 hdsp->control_register &= ~HDSP_ADGainMask; 2253 switch (mode) { 2254 case 0: 2255 hdsp->control_register |= HDSP_ADGainMinus10dBV; 2256 break; 2257 case 1: 2258 hdsp->control_register |= HDSP_ADGainPlus4dBu; 2259 break; 2260 case 2: 2261 hdsp->control_register |= HDSP_ADGainLowGain; 2262 break; 2263 default: 2264 return -1; 2265 2266 } 2267 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 2268 return 0; 2269 } 2270 2271 static int snd_hdsp_info_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2272 { 2273 static char *texts[] = {"-10 dBV", "+4 dBu", "Lo Gain"}; 2274 2275 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2276 uinfo->count = 1; 2277 uinfo->value.enumerated.items = 3; 2278 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 2279 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; 2280 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); 2281 return 0; 2282 } 2283 2284 static int snd_hdsp_get_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2285 { 2286 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2287 2288 ucontrol->value.enumerated.item[0] = hdsp_ad_gain(hdsp); 2289 return 0; 2290 } 2291 2292 static int snd_hdsp_put_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2293 { 2294 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2295 int change; 2296 int val; 2297 2298 if (!snd_hdsp_use_is_exclusive(hdsp)) 2299 return -EBUSY; 2300 val = ucontrol->value.enumerated.item[0]; 2301 if (val < 0) val = 0; 2302 if (val > 2) val = 2; 2303 spin_lock_irq(&hdsp->lock); 2304 if (val != hdsp_ad_gain(hdsp)) 2305 change = (hdsp_set_ad_gain(hdsp, val) == 0) ? 1 : 0; 2306 else 2307 change = 0; 2308 spin_unlock_irq(&hdsp->lock); 2309 return change; 2310 } 2311 2312 #define HDSP_PHONE_GAIN(xname, xindex) \ 2313 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2314 .name = xname, \ 2315 .index = xindex, \ 2316 .info = snd_hdsp_info_phone_gain, \ 2317 .get = snd_hdsp_get_phone_gain, \ 2318 .put = snd_hdsp_put_phone_gain \ 2319 } 2320 2321 static int hdsp_phone_gain(struct hdsp *hdsp) 2322 { 2323 switch (hdsp->control_register & HDSP_PhoneGainMask) { 2324 case HDSP_PhoneGain0dB: 2325 return 0; 2326 case HDSP_PhoneGainMinus6dB: 2327 return 1; 2328 case HDSP_PhoneGainMinus12dB: 2329 return 2; 2330 default: 2331 return 0; 2332 } 2333 } 2334 2335 static int hdsp_set_phone_gain(struct hdsp *hdsp, int mode) 2336 { 2337 hdsp->control_register &= ~HDSP_PhoneGainMask; 2338 switch (mode) { 2339 case 0: 2340 hdsp->control_register |= HDSP_PhoneGain0dB; 2341 break; 2342 case 1: 2343 hdsp->control_register |= HDSP_PhoneGainMinus6dB; 2344 break; 2345 case 2: 2346 hdsp->control_register |= HDSP_PhoneGainMinus12dB; 2347 break; 2348 default: 2349 return -1; 2350 2351 } 2352 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 2353 return 0; 2354 } 2355 2356 static int snd_hdsp_info_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2357 { 2358 static char *texts[] = {"0 dB", "-6 dB", "-12 dB"}; 2359 2360 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2361 uinfo->count = 1; 2362 uinfo->value.enumerated.items = 3; 2363 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 2364 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; 2365 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); 2366 return 0; 2367 } 2368 2369 static int snd_hdsp_get_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2370 { 2371 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2372 2373 ucontrol->value.enumerated.item[0] = hdsp_phone_gain(hdsp); 2374 return 0; 2375 } 2376 2377 static int snd_hdsp_put_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2378 { 2379 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2380 int change; 2381 int val; 2382 2383 if (!snd_hdsp_use_is_exclusive(hdsp)) 2384 return -EBUSY; 2385 val = ucontrol->value.enumerated.item[0]; 2386 if (val < 0) val = 0; 2387 if (val > 2) val = 2; 2388 spin_lock_irq(&hdsp->lock); 2389 if (val != hdsp_phone_gain(hdsp)) 2390 change = (hdsp_set_phone_gain(hdsp, val) == 0) ? 1 : 0; 2391 else 2392 change = 0; 2393 spin_unlock_irq(&hdsp->lock); 2394 return change; 2395 } 2396 2397 #define HDSP_XLR_BREAKOUT_CABLE(xname, xindex) \ 2398 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2399 .name = xname, \ 2400 .index = xindex, \ 2401 .info = snd_hdsp_info_xlr_breakout_cable, \ 2402 .get = snd_hdsp_get_xlr_breakout_cable, \ 2403 .put = snd_hdsp_put_xlr_breakout_cable \ 2404 } 2405 2406 static int hdsp_xlr_breakout_cable(struct hdsp *hdsp) 2407 { 2408 if (hdsp->control_register & HDSP_XLRBreakoutCable) 2409 return 1; 2410 return 0; 2411 } 2412 2413 static int hdsp_set_xlr_breakout_cable(struct hdsp *hdsp, int mode) 2414 { 2415 if (mode) 2416 hdsp->control_register |= HDSP_XLRBreakoutCable; 2417 else 2418 hdsp->control_register &= ~HDSP_XLRBreakoutCable; 2419 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 2420 return 0; 2421 } 2422 2423 static int snd_hdsp_info_xlr_breakout_cable(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2424 { 2425 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 2426 uinfo->count = 1; 2427 uinfo->value.integer.min = 0; 2428 uinfo->value.integer.max = 1; 2429 return 0; 2430 } 2431 2432 static int snd_hdsp_get_xlr_breakout_cable(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2433 { 2434 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2435 2436 ucontrol->value.enumerated.item[0] = hdsp_xlr_breakout_cable(hdsp); 2437 return 0; 2438 } 2439 2440 static int snd_hdsp_put_xlr_breakout_cable(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2441 { 2442 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2443 int change; 2444 int val; 2445 2446 if (!snd_hdsp_use_is_exclusive(hdsp)) 2447 return -EBUSY; 2448 val = ucontrol->value.integer.value[0] & 1; 2449 spin_lock_irq(&hdsp->lock); 2450 change = (int)val != hdsp_xlr_breakout_cable(hdsp); 2451 hdsp_set_xlr_breakout_cable(hdsp, val); 2452 spin_unlock_irq(&hdsp->lock); 2453 return change; 2454 } 2455 2456 /* (De)activates old RME Analog Extension Board 2457 These are connected to the internal ADAT connector 2458 Switching this on desactivates external ADAT 2459 */ 2460 #define HDSP_AEB(xname, xindex) \ 2461 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2462 .name = xname, \ 2463 .index = xindex, \ 2464 .info = snd_hdsp_info_aeb, \ 2465 .get = snd_hdsp_get_aeb, \ 2466 .put = snd_hdsp_put_aeb \ 2467 } 2468 2469 static int hdsp_aeb(struct hdsp *hdsp) 2470 { 2471 if (hdsp->control_register & HDSP_AnalogExtensionBoard) 2472 return 1; 2473 return 0; 2474 } 2475 2476 static int hdsp_set_aeb(struct hdsp *hdsp, int mode) 2477 { 2478 if (mode) 2479 hdsp->control_register |= HDSP_AnalogExtensionBoard; 2480 else 2481 hdsp->control_register &= ~HDSP_AnalogExtensionBoard; 2482 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 2483 return 0; 2484 } 2485 2486 static int snd_hdsp_info_aeb(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2487 { 2488 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 2489 uinfo->count = 1; 2490 uinfo->value.integer.min = 0; 2491 uinfo->value.integer.max = 1; 2492 return 0; 2493 } 2494 2495 static int snd_hdsp_get_aeb(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2496 { 2497 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2498 2499 ucontrol->value.enumerated.item[0] = hdsp_aeb(hdsp); 2500 return 0; 2501 } 2502 2503 static int snd_hdsp_put_aeb(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2504 { 2505 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2506 int change; 2507 int val; 2508 2509 if (!snd_hdsp_use_is_exclusive(hdsp)) 2510 return -EBUSY; 2511 val = ucontrol->value.integer.value[0] & 1; 2512 spin_lock_irq(&hdsp->lock); 2513 change = (int)val != hdsp_aeb(hdsp); 2514 hdsp_set_aeb(hdsp, val); 2515 spin_unlock_irq(&hdsp->lock); 2516 return change; 2517 } 2518 2519 #define HDSP_PREF_SYNC_REF(xname, xindex) \ 2520 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2521 .name = xname, \ 2522 .index = xindex, \ 2523 .info = snd_hdsp_info_pref_sync_ref, \ 2524 .get = snd_hdsp_get_pref_sync_ref, \ 2525 .put = snd_hdsp_put_pref_sync_ref \ 2526 } 2527 2528 static int hdsp_pref_sync_ref(struct hdsp *hdsp) 2529 { 2530 /* Notice that this looks at the requested sync source, 2531 not the one actually in use. 2532 */ 2533 2534 switch (hdsp->control_register & HDSP_SyncRefMask) { 2535 case HDSP_SyncRef_ADAT1: 2536 return HDSP_SYNC_FROM_ADAT1; 2537 case HDSP_SyncRef_ADAT2: 2538 return HDSP_SYNC_FROM_ADAT2; 2539 case HDSP_SyncRef_ADAT3: 2540 return HDSP_SYNC_FROM_ADAT3; 2541 case HDSP_SyncRef_SPDIF: 2542 return HDSP_SYNC_FROM_SPDIF; 2543 case HDSP_SyncRef_WORD: 2544 return HDSP_SYNC_FROM_WORD; 2545 case HDSP_SyncRef_ADAT_SYNC: 2546 return HDSP_SYNC_FROM_ADAT_SYNC; 2547 default: 2548 return HDSP_SYNC_FROM_WORD; 2549 } 2550 return 0; 2551 } 2552 2553 static int hdsp_set_pref_sync_ref(struct hdsp *hdsp, int pref) 2554 { 2555 hdsp->control_register &= ~HDSP_SyncRefMask; 2556 switch (pref) { 2557 case HDSP_SYNC_FROM_ADAT1: 2558 hdsp->control_register &= ~HDSP_SyncRefMask; /* clear SyncRef bits */ 2559 break; 2560 case HDSP_SYNC_FROM_ADAT2: 2561 hdsp->control_register |= HDSP_SyncRef_ADAT2; 2562 break; 2563 case HDSP_SYNC_FROM_ADAT3: 2564 hdsp->control_register |= HDSP_SyncRef_ADAT3; 2565 break; 2566 case HDSP_SYNC_FROM_SPDIF: 2567 hdsp->control_register |= HDSP_SyncRef_SPDIF; 2568 break; 2569 case HDSP_SYNC_FROM_WORD: 2570 hdsp->control_register |= HDSP_SyncRef_WORD; 2571 break; 2572 case HDSP_SYNC_FROM_ADAT_SYNC: 2573 hdsp->control_register |= HDSP_SyncRef_ADAT_SYNC; 2574 break; 2575 default: 2576 return -1; 2577 } 2578 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 2579 return 0; 2580 } 2581 2582 static int snd_hdsp_info_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2583 { 2584 static char *texts[] = {"Word", "IEC958", "ADAT1", "ADAT Sync", "ADAT2", "ADAT3" }; 2585 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2586 2587 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2588 uinfo->count = 1; 2589 2590 switch (hdsp->io_type) { 2591 case Digiface: 2592 case H9652: 2593 uinfo->value.enumerated.items = 6; 2594 break; 2595 case Multiface: 2596 uinfo->value.enumerated.items = 4; 2597 break; 2598 case H9632: 2599 uinfo->value.enumerated.items = 3; 2600 break; 2601 default: 2602 uinfo->value.enumerated.items = 0; 2603 break; 2604 } 2605 2606 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 2607 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; 2608 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); 2609 return 0; 2610 } 2611 2612 static int snd_hdsp_get_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2613 { 2614 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2615 2616 ucontrol->value.enumerated.item[0] = hdsp_pref_sync_ref(hdsp); 2617 return 0; 2618 } 2619 2620 static int snd_hdsp_put_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2621 { 2622 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2623 int change, max; 2624 unsigned int val; 2625 2626 if (!snd_hdsp_use_is_exclusive(hdsp)) 2627 return -EBUSY; 2628 2629 switch (hdsp->io_type) { 2630 case Digiface: 2631 case H9652: 2632 max = 6; 2633 break; 2634 case Multiface: 2635 max = 4; 2636 break; 2637 case H9632: 2638 max = 3; 2639 break; 2640 default: 2641 return -EIO; 2642 } 2643 2644 val = ucontrol->value.enumerated.item[0] % max; 2645 spin_lock_irq(&hdsp->lock); 2646 change = (int)val != hdsp_pref_sync_ref(hdsp); 2647 hdsp_set_pref_sync_ref(hdsp, val); 2648 spin_unlock_irq(&hdsp->lock); 2649 return change; 2650 } 2651 2652 #define HDSP_AUTOSYNC_REF(xname, xindex) \ 2653 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2654 .name = xname, \ 2655 .index = xindex, \ 2656 .access = SNDRV_CTL_ELEM_ACCESS_READ, \ 2657 .info = snd_hdsp_info_autosync_ref, \ 2658 .get = snd_hdsp_get_autosync_ref, \ 2659 } 2660 2661 static int hdsp_autosync_ref(struct hdsp *hdsp) 2662 { 2663 /* This looks at the autosync selected sync reference */ 2664 unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register); 2665 2666 switch (status2 & HDSP_SelSyncRefMask) { 2667 case HDSP_SelSyncRef_WORD: 2668 return HDSP_AUTOSYNC_FROM_WORD; 2669 case HDSP_SelSyncRef_ADAT_SYNC: 2670 return HDSP_AUTOSYNC_FROM_ADAT_SYNC; 2671 case HDSP_SelSyncRef_SPDIF: 2672 return HDSP_AUTOSYNC_FROM_SPDIF; 2673 case HDSP_SelSyncRefMask: 2674 return HDSP_AUTOSYNC_FROM_NONE; 2675 case HDSP_SelSyncRef_ADAT1: 2676 return HDSP_AUTOSYNC_FROM_ADAT1; 2677 case HDSP_SelSyncRef_ADAT2: 2678 return HDSP_AUTOSYNC_FROM_ADAT2; 2679 case HDSP_SelSyncRef_ADAT3: 2680 return HDSP_AUTOSYNC_FROM_ADAT3; 2681 default: 2682 return HDSP_AUTOSYNC_FROM_WORD; 2683 } 2684 return 0; 2685 } 2686 2687 static int snd_hdsp_info_autosync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2688 { 2689 static char *texts[] = {"Word", "ADAT Sync", "IEC958", "None", "ADAT1", "ADAT2", "ADAT3" }; 2690 2691 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2692 uinfo->count = 1; 2693 uinfo->value.enumerated.items = 7; 2694 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 2695 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; 2696 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); 2697 return 0; 2698 } 2699 2700 static int snd_hdsp_get_autosync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2701 { 2702 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2703 2704 ucontrol->value.enumerated.item[0] = hdsp_autosync_ref(hdsp); 2705 return 0; 2706 } 2707 2708 #define HDSP_LINE_OUT(xname, xindex) \ 2709 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2710 .name = xname, \ 2711 .index = xindex, \ 2712 .info = snd_hdsp_info_line_out, \ 2713 .get = snd_hdsp_get_line_out, \ 2714 .put = snd_hdsp_put_line_out \ 2715 } 2716 2717 static int hdsp_line_out(struct hdsp *hdsp) 2718 { 2719 return (hdsp->control_register & HDSP_LineOut) ? 1 : 0; 2720 } 2721 2722 static int hdsp_set_line_output(struct hdsp *hdsp, int out) 2723 { 2724 if (out) 2725 hdsp->control_register |= HDSP_LineOut; 2726 else 2727 hdsp->control_register &= ~HDSP_LineOut; 2728 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 2729 return 0; 2730 } 2731 2732 static int snd_hdsp_info_line_out(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2733 { 2734 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 2735 uinfo->count = 1; 2736 uinfo->value.integer.min = 0; 2737 uinfo->value.integer.max = 1; 2738 return 0; 2739 } 2740 2741 static int snd_hdsp_get_line_out(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2742 { 2743 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2744 2745 spin_lock_irq(&hdsp->lock); 2746 ucontrol->value.integer.value[0] = hdsp_line_out(hdsp); 2747 spin_unlock_irq(&hdsp->lock); 2748 return 0; 2749 } 2750 2751 static int snd_hdsp_put_line_out(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2752 { 2753 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2754 int change; 2755 unsigned int val; 2756 2757 if (!snd_hdsp_use_is_exclusive(hdsp)) 2758 return -EBUSY; 2759 val = ucontrol->value.integer.value[0] & 1; 2760 spin_lock_irq(&hdsp->lock); 2761 change = (int)val != hdsp_line_out(hdsp); 2762 hdsp_set_line_output(hdsp, val); 2763 spin_unlock_irq(&hdsp->lock); 2764 return change; 2765 } 2766 2767 #define HDSP_PRECISE_POINTER(xname, xindex) \ 2768 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, \ 2769 .name = xname, \ 2770 .index = xindex, \ 2771 .info = snd_hdsp_info_precise_pointer, \ 2772 .get = snd_hdsp_get_precise_pointer, \ 2773 .put = snd_hdsp_put_precise_pointer \ 2774 } 2775 2776 static int hdsp_set_precise_pointer(struct hdsp *hdsp, int precise) 2777 { 2778 if (precise) 2779 hdsp->precise_ptr = 1; 2780 else 2781 hdsp->precise_ptr = 0; 2782 return 0; 2783 } 2784 2785 static int snd_hdsp_info_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2786 { 2787 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 2788 uinfo->count = 1; 2789 uinfo->value.integer.min = 0; 2790 uinfo->value.integer.max = 1; 2791 return 0; 2792 } 2793 2794 static int snd_hdsp_get_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2795 { 2796 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2797 2798 spin_lock_irq(&hdsp->lock); 2799 ucontrol->value.integer.value[0] = hdsp->precise_ptr; 2800 spin_unlock_irq(&hdsp->lock); 2801 return 0; 2802 } 2803 2804 static int snd_hdsp_put_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2805 { 2806 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2807 int change; 2808 unsigned int val; 2809 2810 if (!snd_hdsp_use_is_exclusive(hdsp)) 2811 return -EBUSY; 2812 val = ucontrol->value.integer.value[0] & 1; 2813 spin_lock_irq(&hdsp->lock); 2814 change = (int)val != hdsp->precise_ptr; 2815 hdsp_set_precise_pointer(hdsp, val); 2816 spin_unlock_irq(&hdsp->lock); 2817 return change; 2818 } 2819 2820 #define HDSP_USE_MIDI_TASKLET(xname, xindex) \ 2821 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, \ 2822 .name = xname, \ 2823 .index = xindex, \ 2824 .info = snd_hdsp_info_use_midi_tasklet, \ 2825 .get = snd_hdsp_get_use_midi_tasklet, \ 2826 .put = snd_hdsp_put_use_midi_tasklet \ 2827 } 2828 2829 static int hdsp_set_use_midi_tasklet(struct hdsp *hdsp, int use_tasklet) 2830 { 2831 if (use_tasklet) 2832 hdsp->use_midi_tasklet = 1; 2833 else 2834 hdsp->use_midi_tasklet = 0; 2835 return 0; 2836 } 2837 2838 static int snd_hdsp_info_use_midi_tasklet(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2839 { 2840 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 2841 uinfo->count = 1; 2842 uinfo->value.integer.min = 0; 2843 uinfo->value.integer.max = 1; 2844 return 0; 2845 } 2846 2847 static int snd_hdsp_get_use_midi_tasklet(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2848 { 2849 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2850 2851 spin_lock_irq(&hdsp->lock); 2852 ucontrol->value.integer.value[0] = hdsp->use_midi_tasklet; 2853 spin_unlock_irq(&hdsp->lock); 2854 return 0; 2855 } 2856 2857 static int snd_hdsp_put_use_midi_tasklet(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2858 { 2859 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2860 int change; 2861 unsigned int val; 2862 2863 if (!snd_hdsp_use_is_exclusive(hdsp)) 2864 return -EBUSY; 2865 val = ucontrol->value.integer.value[0] & 1; 2866 spin_lock_irq(&hdsp->lock); 2867 change = (int)val != hdsp->use_midi_tasklet; 2868 hdsp_set_use_midi_tasklet(hdsp, val); 2869 spin_unlock_irq(&hdsp->lock); 2870 return change; 2871 } 2872 2873 #define HDSP_MIXER(xname, xindex) \ 2874 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \ 2875 .name = xname, \ 2876 .index = xindex, \ 2877 .device = 0, \ 2878 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \ 2879 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 2880 .info = snd_hdsp_info_mixer, \ 2881 .get = snd_hdsp_get_mixer, \ 2882 .put = snd_hdsp_put_mixer \ 2883 } 2884 2885 static int snd_hdsp_info_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2886 { 2887 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 2888 uinfo->count = 3; 2889 uinfo->value.integer.min = 0; 2890 uinfo->value.integer.max = 65536; 2891 uinfo->value.integer.step = 1; 2892 return 0; 2893 } 2894 2895 static int snd_hdsp_get_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2896 { 2897 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2898 int source; 2899 int destination; 2900 int addr; 2901 2902 source = ucontrol->value.integer.value[0]; 2903 destination = ucontrol->value.integer.value[1]; 2904 2905 if (source >= hdsp->max_channels) 2906 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels,destination); 2907 else 2908 addr = hdsp_input_to_output_key(hdsp,source, destination); 2909 2910 spin_lock_irq(&hdsp->lock); 2911 ucontrol->value.integer.value[2] = hdsp_read_gain (hdsp, addr); 2912 spin_unlock_irq(&hdsp->lock); 2913 return 0; 2914 } 2915 2916 static int snd_hdsp_put_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2917 { 2918 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2919 int change; 2920 int source; 2921 int destination; 2922 int gain; 2923 int addr; 2924 2925 if (!snd_hdsp_use_is_exclusive(hdsp)) 2926 return -EBUSY; 2927 2928 source = ucontrol->value.integer.value[0]; 2929 destination = ucontrol->value.integer.value[1]; 2930 2931 if (source >= hdsp->max_channels) 2932 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels, destination); 2933 else 2934 addr = hdsp_input_to_output_key(hdsp,source, destination); 2935 2936 gain = ucontrol->value.integer.value[2]; 2937 2938 spin_lock_irq(&hdsp->lock); 2939 change = gain != hdsp_read_gain(hdsp, addr); 2940 if (change) 2941 hdsp_write_gain(hdsp, addr, gain); 2942 spin_unlock_irq(&hdsp->lock); 2943 return change; 2944 } 2945 2946 #define HDSP_WC_SYNC_CHECK(xname, xindex) \ 2947 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2948 .name = xname, \ 2949 .index = xindex, \ 2950 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 2951 .info = snd_hdsp_info_sync_check, \ 2952 .get = snd_hdsp_get_wc_sync_check \ 2953 } 2954 2955 static int snd_hdsp_info_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2956 { 2957 static char *texts[] = {"No Lock", "Lock", "Sync" }; 2958 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2959 uinfo->count = 1; 2960 uinfo->value.enumerated.items = 3; 2961 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 2962 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; 2963 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); 2964 return 0; 2965 } 2966 2967 static int hdsp_wc_sync_check(struct hdsp *hdsp) 2968 { 2969 int status2 = hdsp_read(hdsp, HDSP_status2Register); 2970 if (status2 & HDSP_wc_lock) { 2971 if (status2 & HDSP_wc_sync) 2972 return 2; 2973 else 2974 return 1; 2975 } else 2976 return 0; 2977 return 0; 2978 } 2979 2980 static int snd_hdsp_get_wc_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2981 { 2982 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2983 2984 ucontrol->value.enumerated.item[0] = hdsp_wc_sync_check(hdsp); 2985 return 0; 2986 } 2987 2988 #define HDSP_SPDIF_SYNC_CHECK(xname, xindex) \ 2989 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2990 .name = xname, \ 2991 .index = xindex, \ 2992 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 2993 .info = snd_hdsp_info_sync_check, \ 2994 .get = snd_hdsp_get_spdif_sync_check \ 2995 } 2996 2997 static int hdsp_spdif_sync_check(struct hdsp *hdsp) 2998 { 2999 int status = hdsp_read(hdsp, HDSP_statusRegister); 3000 if (status & HDSP_SPDIFErrorFlag) 3001 return 0; 3002 else { 3003 if (status & HDSP_SPDIFSync) 3004 return 2; 3005 else 3006 return 1; 3007 } 3008 return 0; 3009 } 3010 3011 static int snd_hdsp_get_spdif_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 3012 { 3013 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 3014 3015 ucontrol->value.enumerated.item[0] = hdsp_spdif_sync_check(hdsp); 3016 return 0; 3017 } 3018 3019 #define HDSP_ADATSYNC_SYNC_CHECK(xname, xindex) \ 3020 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3021 .name = xname, \ 3022 .index = xindex, \ 3023 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3024 .info = snd_hdsp_info_sync_check, \ 3025 .get = snd_hdsp_get_adatsync_sync_check \ 3026 } 3027 3028 static int hdsp_adatsync_sync_check(struct hdsp *hdsp) 3029 { 3030 int status = hdsp_read(hdsp, HDSP_statusRegister); 3031 if (status & HDSP_TimecodeLock) { 3032 if (status & HDSP_TimecodeSync) 3033 return 2; 3034 else 3035 return 1; 3036 } else 3037 return 0; 3038 } 3039 3040 static int snd_hdsp_get_adatsync_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 3041 { 3042 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 3043 3044 ucontrol->value.enumerated.item[0] = hdsp_adatsync_sync_check(hdsp); 3045 return 0; 3046 } 3047 3048 #define HDSP_ADAT_SYNC_CHECK \ 3049 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3050 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3051 .info = snd_hdsp_info_sync_check, \ 3052 .get = snd_hdsp_get_adat_sync_check \ 3053 } 3054 3055 static int hdsp_adat_sync_check(struct hdsp *hdsp, int idx) 3056 { 3057 int status = hdsp_read(hdsp, HDSP_statusRegister); 3058 3059 if (status & (HDSP_Lock0>>idx)) { 3060 if (status & (HDSP_Sync0>>idx)) 3061 return 2; 3062 else 3063 return 1; 3064 } else 3065 return 0; 3066 } 3067 3068 static int snd_hdsp_get_adat_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 3069 { 3070 int offset; 3071 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 3072 3073 offset = ucontrol->id.index - 1; 3074 snd_assert(offset >= 0); 3075 3076 switch (hdsp->io_type) { 3077 case Digiface: 3078 case H9652: 3079 if (offset >= 3) 3080 return -EINVAL; 3081 break; 3082 case Multiface: 3083 case H9632: 3084 if (offset >= 1) 3085 return -EINVAL; 3086 break; 3087 default: 3088 return -EIO; 3089 } 3090 3091 ucontrol->value.enumerated.item[0] = hdsp_adat_sync_check(hdsp, offset); 3092 return 0; 3093 } 3094 3095 #define HDSP_DDS_OFFSET(xname, xindex) \ 3096 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3097 .name = xname, \ 3098 .index = xindex, \ 3099 .info = snd_hdsp_info_dds_offset, \ 3100 .get = snd_hdsp_get_dds_offset, \ 3101 .put = snd_hdsp_put_dds_offset \ 3102 } 3103 3104 static int hdsp_dds_offset(struct hdsp *hdsp) 3105 { 3106 u64 n; 3107 u32 r; 3108 unsigned int dds_value = hdsp->dds_value; 3109 int system_sample_rate = hdsp->system_sample_rate; 3110 3111 n = DDS_NUMERATOR; 3112 /* 3113 * dds_value = n / rate 3114 * rate = n / dds_value 3115 */ 3116 div64_32(&n, dds_value, &r); 3117 if (system_sample_rate >= 112000) 3118 n *= 4; 3119 else if (system_sample_rate >= 56000) 3120 n *= 2; 3121 return ((int)n) - system_sample_rate; 3122 } 3123 3124 static int hdsp_set_dds_offset(struct hdsp *hdsp, int offset_hz) 3125 { 3126 int rate = hdsp->system_sample_rate + offset_hz; 3127 hdsp_set_dds_value(hdsp, rate); 3128 return 0; 3129 } 3130 3131 static int snd_hdsp_info_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 3132 { 3133 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 3134 uinfo->count = 1; 3135 uinfo->value.integer.min = -5000; 3136 uinfo->value.integer.max = 5000; 3137 return 0; 3138 } 3139 3140 static int snd_hdsp_get_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 3141 { 3142 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 3143 3144 ucontrol->value.enumerated.item[0] = hdsp_dds_offset(hdsp); 3145 return 0; 3146 } 3147 3148 static int snd_hdsp_put_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 3149 { 3150 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 3151 int change; 3152 int val; 3153 3154 if (!snd_hdsp_use_is_exclusive(hdsp)) 3155 return -EBUSY; 3156 val = ucontrol->value.enumerated.item[0]; 3157 spin_lock_irq(&hdsp->lock); 3158 if (val != hdsp_dds_offset(hdsp)) 3159 change = (hdsp_set_dds_offset(hdsp, val) == 0) ? 1 : 0; 3160 else 3161 change = 0; 3162 spin_unlock_irq(&hdsp->lock); 3163 return change; 3164 } 3165 3166 static struct snd_kcontrol_new snd_hdsp_9632_controls[] = { 3167 HDSP_DA_GAIN("DA Gain", 0), 3168 HDSP_AD_GAIN("AD Gain", 0), 3169 HDSP_PHONE_GAIN("Phones Gain", 0), 3170 HDSP_XLR_BREAKOUT_CABLE("XLR Breakout Cable", 0), 3171 HDSP_DDS_OFFSET("DDS Sample Rate Offset", 0) 3172 }; 3173 3174 static struct snd_kcontrol_new snd_hdsp_controls[] = { 3175 { 3176 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 3177 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT), 3178 .info = snd_hdsp_control_spdif_info, 3179 .get = snd_hdsp_control_spdif_get, 3180 .put = snd_hdsp_control_spdif_put, 3181 }, 3182 { 3183 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE, 3184 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 3185 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM), 3186 .info = snd_hdsp_control_spdif_stream_info, 3187 .get = snd_hdsp_control_spdif_stream_get, 3188 .put = snd_hdsp_control_spdif_stream_put, 3189 }, 3190 { 3191 .access = SNDRV_CTL_ELEM_ACCESS_READ, 3192 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 3193 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK), 3194 .info = snd_hdsp_control_spdif_mask_info, 3195 .get = snd_hdsp_control_spdif_mask_get, 3196 .private_value = IEC958_AES0_NONAUDIO | 3197 IEC958_AES0_PROFESSIONAL | 3198 IEC958_AES0_CON_EMPHASIS, 3199 }, 3200 { 3201 .access = SNDRV_CTL_ELEM_ACCESS_READ, 3202 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 3203 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK), 3204 .info = snd_hdsp_control_spdif_mask_info, 3205 .get = snd_hdsp_control_spdif_mask_get, 3206 .private_value = IEC958_AES0_NONAUDIO | 3207 IEC958_AES0_PROFESSIONAL | 3208 IEC958_AES0_PRO_EMPHASIS, 3209 }, 3210 HDSP_MIXER("Mixer", 0), 3211 HDSP_SPDIF_IN("IEC958 Input Connector", 0), 3212 HDSP_SPDIF_OUT("IEC958 Output also on ADAT1", 0), 3213 HDSP_SPDIF_PROFESSIONAL("IEC958 Professional Bit", 0), 3214 HDSP_SPDIF_EMPHASIS("IEC958 Emphasis Bit", 0), 3215 HDSP_SPDIF_NON_AUDIO("IEC958 Non-audio Bit", 0), 3216 /* 'Sample Clock Source' complies with the alsa control naming scheme */ 3217 HDSP_CLOCK_SOURCE("Sample Clock Source", 0), 3218 { 3219 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 3220 .name = "Sample Clock Source Locking", 3221 .info = snd_hdsp_info_clock_source_lock, 3222 .get = snd_hdsp_get_clock_source_lock, 3223 .put = snd_hdsp_put_clock_source_lock, 3224 }, 3225 HDSP_SYSTEM_CLOCK_MODE("System Clock Mode", 0), 3226 HDSP_PREF_SYNC_REF("Preferred Sync Reference", 0), 3227 HDSP_AUTOSYNC_REF("AutoSync Reference", 0), 3228 HDSP_SPDIF_SAMPLE_RATE("SPDIF Sample Rate", 0), 3229 HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), 3230 /* 'External Rate' complies with the alsa control naming scheme */ 3231 HDSP_AUTOSYNC_SAMPLE_RATE("External Rate", 0), 3232 HDSP_WC_SYNC_CHECK("Word Clock Lock Status", 0), 3233 HDSP_SPDIF_SYNC_CHECK("SPDIF Lock Status", 0), 3234 HDSP_ADATSYNC_SYNC_CHECK("ADAT Sync Lock Status", 0), 3235 HDSP_LINE_OUT("Line Out", 0), 3236 HDSP_PRECISE_POINTER("Precise Pointer", 0), 3237 HDSP_USE_MIDI_TASKLET("Use Midi Tasklet", 0), 3238 }; 3239 3240 static struct snd_kcontrol_new snd_hdsp_96xx_aeb = HDSP_AEB("Analog Extension Board", 0); 3241 static struct snd_kcontrol_new snd_hdsp_adat_sync_check = HDSP_ADAT_SYNC_CHECK; 3242 3243 static int snd_hdsp_create_controls(struct snd_card *card, struct hdsp *hdsp) 3244 { 3245 unsigned int idx; 3246 int err; 3247 struct snd_kcontrol *kctl; 3248 3249 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_controls); idx++) { 3250 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_controls[idx], hdsp))) < 0) 3251 return err; 3252 if (idx == 1) /* IEC958 (S/PDIF) Stream */ 3253 hdsp->spdif_ctl = kctl; 3254 } 3255 3256 /* ADAT SyncCheck status */ 3257 snd_hdsp_adat_sync_check.name = "ADAT Lock Status"; 3258 snd_hdsp_adat_sync_check.index = 1; 3259 if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp)))) 3260 return err; 3261 if (hdsp->io_type == Digiface || hdsp->io_type == H9652) { 3262 for (idx = 1; idx < 3; ++idx) { 3263 snd_hdsp_adat_sync_check.index = idx+1; 3264 if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp)))) 3265 return err; 3266 } 3267 } 3268 3269 /* DA, AD and Phone gain and XLR breakout cable controls for H9632 cards */ 3270 if (hdsp->io_type == H9632) { 3271 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_9632_controls); idx++) { 3272 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_9632_controls[idx], hdsp))) < 0) 3273 return err; 3274 } 3275 } 3276 3277 /* AEB control for H96xx card */ 3278 if (hdsp->io_type == H9632 || hdsp->io_type == H9652) { 3279 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_96xx_aeb, hdsp))) < 0) 3280 return err; 3281 } 3282 3283 return 0; 3284 } 3285 3286 /*------------------------------------------------------------ 3287 /proc interface 3288 ------------------------------------------------------------*/ 3289 3290 static void 3291 snd_hdsp_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer) 3292 { 3293 struct hdsp *hdsp = (struct hdsp *) entry->private_data; 3294 unsigned int status; 3295 unsigned int status2; 3296 char *pref_sync_ref; 3297 char *autosync_ref; 3298 char *system_clock_mode; 3299 char *clock_source; 3300 int x; 3301 3302 if (hdsp_check_for_iobox (hdsp)) { 3303 snd_iprintf(buffer, "No I/O box connected.\nPlease connect one and upload firmware.\n"); 3304 return; 3305 } 3306 3307 if (hdsp_check_for_firmware(hdsp, 0)) { 3308 if (hdsp->state & HDSP_FirmwareCached) { 3309 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) { 3310 snd_iprintf(buffer, "Firmware loading from cache failed, please upload manually.\n"); 3311 return; 3312 } 3313 } else { 3314 int err = -EINVAL; 3315 #ifdef HDSP_FW_LOADER 3316 err = hdsp_request_fw_loader(hdsp); 3317 #endif 3318 if (err < 0) { 3319 snd_iprintf(buffer, 3320 "No firmware loaded nor cached, " 3321 "please upload firmware.\n"); 3322 return; 3323 } 3324 } 3325 } 3326 3327 status = hdsp_read(hdsp, HDSP_statusRegister); 3328 status2 = hdsp_read(hdsp, HDSP_status2Register); 3329 3330 snd_iprintf(buffer, "%s (Card #%d)\n", hdsp->card_name, hdsp->card->number + 1); 3331 snd_iprintf(buffer, "Buffers: capture %p playback %p\n", 3332 hdsp->capture_buffer, hdsp->playback_buffer); 3333 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n", 3334 hdsp->irq, hdsp->port, (unsigned long)hdsp->iobase); 3335 snd_iprintf(buffer, "Control register: 0x%x\n", hdsp->control_register); 3336 snd_iprintf(buffer, "Control2 register: 0x%x\n", hdsp->control2_register); 3337 snd_iprintf(buffer, "Status register: 0x%x\n", status); 3338 snd_iprintf(buffer, "Status2 register: 0x%x\n", status2); 3339 snd_iprintf(buffer, "FIFO status: %d\n", hdsp_read(hdsp, HDSP_fifoStatus) & 0xff); 3340 snd_iprintf(buffer, "MIDI1 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut0)); 3341 snd_iprintf(buffer, "MIDI1 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn0)); 3342 snd_iprintf(buffer, "MIDI2 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut1)); 3343 snd_iprintf(buffer, "MIDI2 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn1)); 3344 snd_iprintf(buffer, "Use Midi Tasklet: %s\n", hdsp->use_midi_tasklet ? "on" : "off"); 3345 3346 snd_iprintf(buffer, "\n"); 3347 3348 x = 1 << (6 + hdsp_decode_latency(hdsp->control_register & HDSP_LatencyMask)); 3349 3350 snd_iprintf(buffer, "Buffer Size (Latency): %d samples (2 periods of %lu bytes)\n", x, (unsigned long) hdsp->period_bytes); 3351 snd_iprintf(buffer, "Hardware pointer (frames): %ld\n", hdsp_hw_pointer(hdsp)); 3352 snd_iprintf(buffer, "Precise pointer: %s\n", hdsp->precise_ptr ? "on" : "off"); 3353 snd_iprintf(buffer, "Line out: %s\n", (hdsp->control_register & HDSP_LineOut) ? "on" : "off"); 3354 3355 snd_iprintf(buffer, "Firmware version: %d\n", (status2&HDSP_version0)|(status2&HDSP_version1)<<1|(status2&HDSP_version2)<<2); 3356 3357 snd_iprintf(buffer, "\n"); 3358 3359 3360 switch (hdsp_clock_source(hdsp)) { 3361 case HDSP_CLOCK_SOURCE_AUTOSYNC: 3362 clock_source = "AutoSync"; 3363 break; 3364 case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ: 3365 clock_source = "Internal 32 kHz"; 3366 break; 3367 case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ: 3368 clock_source = "Internal 44.1 kHz"; 3369 break; 3370 case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ: 3371 clock_source = "Internal 48 kHz"; 3372 break; 3373 case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ: 3374 clock_source = "Internal 64 kHz"; 3375 break; 3376 case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ: 3377 clock_source = "Internal 88.2 kHz"; 3378 break; 3379 case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ: 3380 clock_source = "Internal 96 kHz"; 3381 break; 3382 case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ: 3383 clock_source = "Internal 128 kHz"; 3384 break; 3385 case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ: 3386 clock_source = "Internal 176.4 kHz"; 3387 break; 3388 case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ: 3389 clock_source = "Internal 192 kHz"; 3390 break; 3391 default: 3392 clock_source = "Error"; 3393 } 3394 snd_iprintf (buffer, "Sample Clock Source: %s\n", clock_source); 3395 3396 if (hdsp_system_clock_mode(hdsp)) 3397 system_clock_mode = "Slave"; 3398 else 3399 system_clock_mode = "Master"; 3400 3401 switch (hdsp_pref_sync_ref (hdsp)) { 3402 case HDSP_SYNC_FROM_WORD: 3403 pref_sync_ref = "Word Clock"; 3404 break; 3405 case HDSP_SYNC_FROM_ADAT_SYNC: 3406 pref_sync_ref = "ADAT Sync"; 3407 break; 3408 case HDSP_SYNC_FROM_SPDIF: 3409 pref_sync_ref = "SPDIF"; 3410 break; 3411 case HDSP_SYNC_FROM_ADAT1: 3412 pref_sync_ref = "ADAT1"; 3413 break; 3414 case HDSP_SYNC_FROM_ADAT2: 3415 pref_sync_ref = "ADAT2"; 3416 break; 3417 case HDSP_SYNC_FROM_ADAT3: 3418 pref_sync_ref = "ADAT3"; 3419 break; 3420 default: 3421 pref_sync_ref = "Word Clock"; 3422 break; 3423 } 3424 snd_iprintf (buffer, "Preferred Sync Reference: %s\n", pref_sync_ref); 3425 3426 switch (hdsp_autosync_ref (hdsp)) { 3427 case HDSP_AUTOSYNC_FROM_WORD: 3428 autosync_ref = "Word Clock"; 3429 break; 3430 case HDSP_AUTOSYNC_FROM_ADAT_SYNC: 3431 autosync_ref = "ADAT Sync"; 3432 break; 3433 case HDSP_AUTOSYNC_FROM_SPDIF: 3434 autosync_ref = "SPDIF"; 3435 break; 3436 case HDSP_AUTOSYNC_FROM_NONE: 3437 autosync_ref = "None"; 3438 break; 3439 case HDSP_AUTOSYNC_FROM_ADAT1: 3440 autosync_ref = "ADAT1"; 3441 break; 3442 case HDSP_AUTOSYNC_FROM_ADAT2: 3443 autosync_ref = "ADAT2"; 3444 break; 3445 case HDSP_AUTOSYNC_FROM_ADAT3: 3446 autosync_ref = "ADAT3"; 3447 break; 3448 default: 3449 autosync_ref = "---"; 3450 break; 3451 } 3452 snd_iprintf (buffer, "AutoSync Reference: %s\n", autosync_ref); 3453 3454 snd_iprintf (buffer, "AutoSync Frequency: %d\n", hdsp_external_sample_rate(hdsp)); 3455 3456 snd_iprintf (buffer, "System Clock Mode: %s\n", system_clock_mode); 3457 3458 snd_iprintf (buffer, "System Clock Frequency: %d\n", hdsp->system_sample_rate); 3459 snd_iprintf (buffer, "System Clock Locked: %s\n", hdsp->clock_source_locked ? "Yes" : "No"); 3460 3461 snd_iprintf(buffer, "\n"); 3462 3463 switch (hdsp_spdif_in(hdsp)) { 3464 case HDSP_SPDIFIN_OPTICAL: 3465 snd_iprintf(buffer, "IEC958 input: Optical\n"); 3466 break; 3467 case HDSP_SPDIFIN_COAXIAL: 3468 snd_iprintf(buffer, "IEC958 input: Coaxial\n"); 3469 break; 3470 case HDSP_SPDIFIN_INTERNAL: 3471 snd_iprintf(buffer, "IEC958 input: Internal\n"); 3472 break; 3473 case HDSP_SPDIFIN_AES: 3474 snd_iprintf(buffer, "IEC958 input: AES\n"); 3475 break; 3476 default: 3477 snd_iprintf(buffer, "IEC958 input: ???\n"); 3478 break; 3479 } 3480 3481 if (hdsp->control_register & HDSP_SPDIFOpticalOut) 3482 snd_iprintf(buffer, "IEC958 output: Coaxial & ADAT1\n"); 3483 else 3484 snd_iprintf(buffer, "IEC958 output: Coaxial only\n"); 3485 3486 if (hdsp->control_register & HDSP_SPDIFProfessional) 3487 snd_iprintf(buffer, "IEC958 quality: Professional\n"); 3488 else 3489 snd_iprintf(buffer, "IEC958 quality: Consumer\n"); 3490 3491 if (hdsp->control_register & HDSP_SPDIFEmphasis) 3492 snd_iprintf(buffer, "IEC958 emphasis: on\n"); 3493 else 3494 snd_iprintf(buffer, "IEC958 emphasis: off\n"); 3495 3496 if (hdsp->control_register & HDSP_SPDIFNonAudio) 3497 snd_iprintf(buffer, "IEC958 NonAudio: on\n"); 3498 else 3499 snd_iprintf(buffer, "IEC958 NonAudio: off\n"); 3500 if ((x = hdsp_spdif_sample_rate (hdsp)) != 0) 3501 snd_iprintf (buffer, "IEC958 sample rate: %d\n", x); 3502 else 3503 snd_iprintf (buffer, "IEC958 sample rate: Error flag set\n"); 3504 3505 snd_iprintf(buffer, "\n"); 3506 3507 /* Sync Check */ 3508 x = status & HDSP_Sync0; 3509 if (status & HDSP_Lock0) 3510 snd_iprintf(buffer, "ADAT1: %s\n", x ? "Sync" : "Lock"); 3511 else 3512 snd_iprintf(buffer, "ADAT1: No Lock\n"); 3513 3514 switch (hdsp->io_type) { 3515 case Digiface: 3516 case H9652: 3517 x = status & HDSP_Sync1; 3518 if (status & HDSP_Lock1) 3519 snd_iprintf(buffer, "ADAT2: %s\n", x ? "Sync" : "Lock"); 3520 else 3521 snd_iprintf(buffer, "ADAT2: No Lock\n"); 3522 x = status & HDSP_Sync2; 3523 if (status & HDSP_Lock2) 3524 snd_iprintf(buffer, "ADAT3: %s\n", x ? "Sync" : "Lock"); 3525 else 3526 snd_iprintf(buffer, "ADAT3: No Lock\n"); 3527 break; 3528 default: 3529 /* relax */ 3530 break; 3531 } 3532 3533 x = status & HDSP_SPDIFSync; 3534 if (status & HDSP_SPDIFErrorFlag) 3535 snd_iprintf (buffer, "SPDIF: No Lock\n"); 3536 else 3537 snd_iprintf (buffer, "SPDIF: %s\n", x ? "Sync" : "Lock"); 3538 3539 x = status2 & HDSP_wc_sync; 3540 if (status2 & HDSP_wc_lock) 3541 snd_iprintf (buffer, "Word Clock: %s\n", x ? "Sync" : "Lock"); 3542 else 3543 snd_iprintf (buffer, "Word Clock: No Lock\n"); 3544 3545 x = status & HDSP_TimecodeSync; 3546 if (status & HDSP_TimecodeLock) 3547 snd_iprintf(buffer, "ADAT Sync: %s\n", x ? "Sync" : "Lock"); 3548 else 3549 snd_iprintf(buffer, "ADAT Sync: No Lock\n"); 3550 3551 snd_iprintf(buffer, "\n"); 3552 3553 /* Informations about H9632 specific controls */ 3554 if (hdsp->io_type == H9632) { 3555 char *tmp; 3556 3557 switch (hdsp_ad_gain(hdsp)) { 3558 case 0: 3559 tmp = "-10 dBV"; 3560 break; 3561 case 1: 3562 tmp = "+4 dBu"; 3563 break; 3564 default: 3565 tmp = "Lo Gain"; 3566 break; 3567 } 3568 snd_iprintf(buffer, "AD Gain : %s\n", tmp); 3569 3570 switch (hdsp_da_gain(hdsp)) { 3571 case 0: 3572 tmp = "Hi Gain"; 3573 break; 3574 case 1: 3575 tmp = "+4 dBu"; 3576 break; 3577 default: 3578 tmp = "-10 dBV"; 3579 break; 3580 } 3581 snd_iprintf(buffer, "DA Gain : %s\n", tmp); 3582 3583 switch (hdsp_phone_gain(hdsp)) { 3584 case 0: 3585 tmp = "0 dB"; 3586 break; 3587 case 1: 3588 tmp = "-6 dB"; 3589 break; 3590 default: 3591 tmp = "-12 dB"; 3592 break; 3593 } 3594 snd_iprintf(buffer, "Phones Gain : %s\n", tmp); 3595 3596 snd_iprintf(buffer, "XLR Breakout Cable : %s\n", hdsp_xlr_breakout_cable(hdsp) ? "yes" : "no"); 3597 3598 if (hdsp->control_register & HDSP_AnalogExtensionBoard) 3599 snd_iprintf(buffer, "AEB : on (ADAT1 internal)\n"); 3600 else 3601 snd_iprintf(buffer, "AEB : off (ADAT1 external)\n"); 3602 snd_iprintf(buffer, "\n"); 3603 } 3604 3605 } 3606 3607 static void __devinit snd_hdsp_proc_init(struct hdsp *hdsp) 3608 { 3609 struct snd_info_entry *entry; 3610 3611 if (! snd_card_proc_new(hdsp->card, "hdsp", &entry)) 3612 snd_info_set_text_ops(entry, hdsp, snd_hdsp_proc_read); 3613 } 3614 3615 static void snd_hdsp_free_buffers(struct hdsp *hdsp) 3616 { 3617 snd_hammerfall_free_buffer(&hdsp->capture_dma_buf, hdsp->pci); 3618 snd_hammerfall_free_buffer(&hdsp->playback_dma_buf, hdsp->pci); 3619 } 3620 3621 static int __devinit snd_hdsp_initialize_memory(struct hdsp *hdsp) 3622 { 3623 unsigned long pb_bus, cb_bus; 3624 3625 if (snd_hammerfall_get_buffer(hdsp->pci, &hdsp->capture_dma_buf, HDSP_DMA_AREA_BYTES) < 0 || 3626 snd_hammerfall_get_buffer(hdsp->pci, &hdsp->playback_dma_buf, HDSP_DMA_AREA_BYTES) < 0) { 3627 if (hdsp->capture_dma_buf.area) 3628 snd_dma_free_pages(&hdsp->capture_dma_buf); 3629 printk(KERN_ERR "%s: no buffers available\n", hdsp->card_name); 3630 return -ENOMEM; 3631 } 3632 3633 /* Align to bus-space 64K boundary */ 3634 3635 cb_bus = ALIGN(hdsp->capture_dma_buf.addr, 0x10000ul); 3636 pb_bus = ALIGN(hdsp->playback_dma_buf.addr, 0x10000ul); 3637 3638 /* Tell the card where it is */ 3639 3640 hdsp_write(hdsp, HDSP_inputBufferAddress, cb_bus); 3641 hdsp_write(hdsp, HDSP_outputBufferAddress, pb_bus); 3642 3643 hdsp->capture_buffer = hdsp->capture_dma_buf.area + (cb_bus - hdsp->capture_dma_buf.addr); 3644 hdsp->playback_buffer = hdsp->playback_dma_buf.area + (pb_bus - hdsp->playback_dma_buf.addr); 3645 3646 return 0; 3647 } 3648 3649 static int snd_hdsp_set_defaults(struct hdsp *hdsp) 3650 { 3651 unsigned int i; 3652 3653 /* ASSUMPTION: hdsp->lock is either held, or 3654 there is no need to hold it (e.g. during module 3655 initalization). 3656 */ 3657 3658 /* set defaults: 3659 3660 SPDIF Input via Coax 3661 Master clock mode 3662 maximum latency (7 => 2^7 = 8192 samples, 64Kbyte buffer, 3663 which implies 2 4096 sample, 32Kbyte periods). 3664 Enable line out. 3665 */ 3666 3667 hdsp->control_register = HDSP_ClockModeMaster | 3668 HDSP_SPDIFInputCoaxial | 3669 hdsp_encode_latency(7) | 3670 HDSP_LineOut; 3671 3672 3673 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 3674 3675 #ifdef SNDRV_BIG_ENDIAN 3676 hdsp->control2_register = HDSP_BIGENDIAN_MODE; 3677 #else 3678 hdsp->control2_register = 0; 3679 #endif 3680 if (hdsp->io_type == H9652) 3681 snd_hdsp_9652_enable_mixer (hdsp); 3682 else 3683 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register); 3684 3685 hdsp_reset_hw_pointer(hdsp); 3686 hdsp_compute_period_size(hdsp); 3687 3688 /* silence everything */ 3689 3690 for (i = 0; i < HDSP_MATRIX_MIXER_SIZE; ++i) 3691 hdsp->mixer_matrix[i] = MINUS_INFINITY_GAIN; 3692 3693 for (i = 0; i < ((hdsp->io_type == H9652 || hdsp->io_type == H9632) ? 1352 : HDSP_MATRIX_MIXER_SIZE); ++i) { 3694 if (hdsp_write_gain (hdsp, i, MINUS_INFINITY_GAIN)) 3695 return -EIO; 3696 } 3697 3698 /* H9632 specific defaults */ 3699 if (hdsp->io_type == H9632) { 3700 hdsp->control_register |= (HDSP_DAGainPlus4dBu | HDSP_ADGainPlus4dBu | HDSP_PhoneGain0dB); 3701 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 3702 } 3703 3704 /* set a default rate so that the channel map is set up. 3705 */ 3706 3707 hdsp_set_rate(hdsp, 48000, 1); 3708 3709 return 0; 3710 } 3711 3712 static void hdsp_midi_tasklet(unsigned long arg) 3713 { 3714 struct hdsp *hdsp = (struct hdsp *)arg; 3715 3716 if (hdsp->midi[0].pending) 3717 snd_hdsp_midi_input_read (&hdsp->midi[0]); 3718 if (hdsp->midi[1].pending) 3719 snd_hdsp_midi_input_read (&hdsp->midi[1]); 3720 } 3721 3722 static irqreturn_t snd_hdsp_interrupt(int irq, void *dev_id) 3723 { 3724 struct hdsp *hdsp = (struct hdsp *) dev_id; 3725 unsigned int status; 3726 int audio; 3727 int midi0; 3728 int midi1; 3729 unsigned int midi0status; 3730 unsigned int midi1status; 3731 int schedule = 0; 3732 3733 status = hdsp_read(hdsp, HDSP_statusRegister); 3734 3735 audio = status & HDSP_audioIRQPending; 3736 midi0 = status & HDSP_midi0IRQPending; 3737 midi1 = status & HDSP_midi1IRQPending; 3738 3739 if (!audio && !midi0 && !midi1) 3740 return IRQ_NONE; 3741 3742 hdsp_write(hdsp, HDSP_interruptConfirmation, 0); 3743 3744 midi0status = hdsp_read (hdsp, HDSP_midiStatusIn0) & 0xff; 3745 midi1status = hdsp_read (hdsp, HDSP_midiStatusIn1) & 0xff; 3746 3747 if (audio) { 3748 if (hdsp->capture_substream) 3749 snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream); 3750 3751 if (hdsp->playback_substream) 3752 snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream); 3753 } 3754 3755 if (midi0 && midi0status) { 3756 if (hdsp->use_midi_tasklet) { 3757 /* we disable interrupts for this input until processing is done */ 3758 hdsp->control_register &= ~HDSP_Midi0InterruptEnable; 3759 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 3760 hdsp->midi[0].pending = 1; 3761 schedule = 1; 3762 } else { 3763 snd_hdsp_midi_input_read (&hdsp->midi[0]); 3764 } 3765 } 3766 if (hdsp->io_type != Multiface && hdsp->io_type != H9632 && midi1 && midi1status) { 3767 if (hdsp->use_midi_tasklet) { 3768 /* we disable interrupts for this input until processing is done */ 3769 hdsp->control_register &= ~HDSP_Midi1InterruptEnable; 3770 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 3771 hdsp->midi[1].pending = 1; 3772 schedule = 1; 3773 } else { 3774 snd_hdsp_midi_input_read (&hdsp->midi[1]); 3775 } 3776 } 3777 if (hdsp->use_midi_tasklet && schedule) 3778 tasklet_hi_schedule(&hdsp->midi_tasklet); 3779 return IRQ_HANDLED; 3780 } 3781 3782 static snd_pcm_uframes_t snd_hdsp_hw_pointer(struct snd_pcm_substream *substream) 3783 { 3784 struct hdsp *hdsp = snd_pcm_substream_chip(substream); 3785 return hdsp_hw_pointer(hdsp); 3786 } 3787 3788 static char *hdsp_channel_buffer_location(struct hdsp *hdsp, 3789 int stream, 3790 int channel) 3791 3792 { 3793 int mapped_channel; 3794 3795 snd_assert(channel >= 0 && channel < hdsp->max_channels, return NULL); 3796 3797 if ((mapped_channel = hdsp->channel_map[channel]) < 0) 3798 return NULL; 3799 3800 if (stream == SNDRV_PCM_STREAM_CAPTURE) 3801 return hdsp->capture_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES); 3802 else 3803 return hdsp->playback_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES); 3804 } 3805 3806 static int snd_hdsp_playback_copy(struct snd_pcm_substream *substream, int channel, 3807 snd_pcm_uframes_t pos, void __user *src, snd_pcm_uframes_t count) 3808 { 3809 struct hdsp *hdsp = snd_pcm_substream_chip(substream); 3810 char *channel_buf; 3811 3812 snd_assert(pos + count <= HDSP_CHANNEL_BUFFER_BYTES / 4, return -EINVAL); 3813 3814 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel); 3815 snd_assert(channel_buf != NULL, return -EIO); 3816 if (copy_from_user(channel_buf + pos * 4, src, count * 4)) 3817 return -EFAULT; 3818 return count; 3819 } 3820 3821 static int snd_hdsp_capture_copy(struct snd_pcm_substream *substream, int channel, 3822 snd_pcm_uframes_t pos, void __user *dst, snd_pcm_uframes_t count) 3823 { 3824 struct hdsp *hdsp = snd_pcm_substream_chip(substream); 3825 char *channel_buf; 3826 3827 snd_assert(pos + count <= HDSP_CHANNEL_BUFFER_BYTES / 4, return -EINVAL); 3828 3829 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel); 3830 snd_assert(channel_buf != NULL, return -EIO); 3831 if (copy_to_user(dst, channel_buf + pos * 4, count * 4)) 3832 return -EFAULT; 3833 return count; 3834 } 3835 3836 static int snd_hdsp_hw_silence(struct snd_pcm_substream *substream, int channel, 3837 snd_pcm_uframes_t pos, snd_pcm_uframes_t count) 3838 { 3839 struct hdsp *hdsp = snd_pcm_substream_chip(substream); 3840 char *channel_buf; 3841 3842 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel); 3843 snd_assert(channel_buf != NULL, return -EIO); 3844 memset(channel_buf + pos * 4, 0, count * 4); 3845 return count; 3846 } 3847 3848 static int snd_hdsp_reset(struct snd_pcm_substream *substream) 3849 { 3850 struct snd_pcm_runtime *runtime = substream->runtime; 3851 struct hdsp *hdsp = snd_pcm_substream_chip(substream); 3852 struct snd_pcm_substream *other; 3853 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 3854 other = hdsp->capture_substream; 3855 else 3856 other = hdsp->playback_substream; 3857 if (hdsp->running) 3858 runtime->status->hw_ptr = hdsp_hw_pointer(hdsp); 3859 else 3860 runtime->status->hw_ptr = 0; 3861 if (other) { 3862 struct snd_pcm_substream *s; 3863 struct snd_pcm_runtime *oruntime = other->runtime; 3864 snd_pcm_group_for_each_entry(s, substream) { 3865 if (s == other) { 3866 oruntime->status->hw_ptr = runtime->status->hw_ptr; 3867 break; 3868 } 3869 } 3870 } 3871 return 0; 3872 } 3873 3874 static int snd_hdsp_hw_params(struct snd_pcm_substream *substream, 3875 struct snd_pcm_hw_params *params) 3876 { 3877 struct hdsp *hdsp = snd_pcm_substream_chip(substream); 3878 int err; 3879 pid_t this_pid; 3880 pid_t other_pid; 3881 3882 if (hdsp_check_for_iobox (hdsp)) 3883 return -EIO; 3884 3885 if (hdsp_check_for_firmware(hdsp, 1)) 3886 return -EIO; 3887 3888 spin_lock_irq(&hdsp->lock); 3889 3890 if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) { 3891 hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis); 3892 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= hdsp->creg_spdif_stream); 3893 this_pid = hdsp->playback_pid; 3894 other_pid = hdsp->capture_pid; 3895 } else { 3896 this_pid = hdsp->capture_pid; 3897 other_pid = hdsp->playback_pid; 3898 } 3899 3900 if ((other_pid > 0) && (this_pid != other_pid)) { 3901 3902 /* The other stream is open, and not by the same 3903 task as this one. Make sure that the parameters 3904 that matter are the same. 3905 */ 3906 3907 if (params_rate(params) != hdsp->system_sample_rate) { 3908 spin_unlock_irq(&hdsp->lock); 3909 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE); 3910 return -EBUSY; 3911 } 3912 3913 if (params_period_size(params) != hdsp->period_bytes / 4) { 3914 spin_unlock_irq(&hdsp->lock); 3915 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE); 3916 return -EBUSY; 3917 } 3918 3919 /* We're fine. */ 3920 3921 spin_unlock_irq(&hdsp->lock); 3922 return 0; 3923 3924 } else { 3925 spin_unlock_irq(&hdsp->lock); 3926 } 3927 3928 /* how to make sure that the rate matches an externally-set one ? 3929 */ 3930 3931 spin_lock_irq(&hdsp->lock); 3932 if (! hdsp->clock_source_locked) { 3933 if ((err = hdsp_set_rate(hdsp, params_rate(params), 0)) < 0) { 3934 spin_unlock_irq(&hdsp->lock); 3935 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE); 3936 return err; 3937 } 3938 } 3939 spin_unlock_irq(&hdsp->lock); 3940 3941 if ((err = hdsp_set_interrupt_interval(hdsp, params_period_size(params))) < 0) { 3942 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE); 3943 return err; 3944 } 3945 3946 return 0; 3947 } 3948 3949 static int snd_hdsp_channel_info(struct snd_pcm_substream *substream, 3950 struct snd_pcm_channel_info *info) 3951 { 3952 struct hdsp *hdsp = snd_pcm_substream_chip(substream); 3953 int mapped_channel; 3954 3955 snd_assert(info->channel < hdsp->max_channels, return -EINVAL); 3956 3957 if ((mapped_channel = hdsp->channel_map[info->channel]) < 0) 3958 return -EINVAL; 3959 3960 info->offset = mapped_channel * HDSP_CHANNEL_BUFFER_BYTES; 3961 info->first = 0; 3962 info->step = 32; 3963 return 0; 3964 } 3965 3966 static int snd_hdsp_ioctl(struct snd_pcm_substream *substream, 3967 unsigned int cmd, void *arg) 3968 { 3969 switch (cmd) { 3970 case SNDRV_PCM_IOCTL1_RESET: 3971 return snd_hdsp_reset(substream); 3972 case SNDRV_PCM_IOCTL1_CHANNEL_INFO: 3973 return snd_hdsp_channel_info(substream, arg); 3974 default: 3975 break; 3976 } 3977 3978 return snd_pcm_lib_ioctl(substream, cmd, arg); 3979 } 3980 3981 static int snd_hdsp_trigger(struct snd_pcm_substream *substream, int cmd) 3982 { 3983 struct hdsp *hdsp = snd_pcm_substream_chip(substream); 3984 struct snd_pcm_substream *other; 3985 int running; 3986 3987 if (hdsp_check_for_iobox (hdsp)) 3988 return -EIO; 3989 3990 if (hdsp_check_for_firmware(hdsp, 0)) /* no auto-loading in trigger */ 3991 return -EIO; 3992 3993 spin_lock(&hdsp->lock); 3994 running = hdsp->running; 3995 switch (cmd) { 3996 case SNDRV_PCM_TRIGGER_START: 3997 running |= 1 << substream->stream; 3998 break; 3999 case SNDRV_PCM_TRIGGER_STOP: 4000 running &= ~(1 << substream->stream); 4001 break; 4002 default: 4003 snd_BUG(); 4004 spin_unlock(&hdsp->lock); 4005 return -EINVAL; 4006 } 4007 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 4008 other = hdsp->capture_substream; 4009 else 4010 other = hdsp->playback_substream; 4011 4012 if (other) { 4013 struct snd_pcm_substream *s; 4014 snd_pcm_group_for_each_entry(s, substream) { 4015 if (s == other) { 4016 snd_pcm_trigger_done(s, substream); 4017 if (cmd == SNDRV_PCM_TRIGGER_START) 4018 running |= 1 << s->stream; 4019 else 4020 running &= ~(1 << s->stream); 4021 goto _ok; 4022 } 4023 } 4024 if (cmd == SNDRV_PCM_TRIGGER_START) { 4025 if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK)) && 4026 substream->stream == SNDRV_PCM_STREAM_CAPTURE) 4027 hdsp_silence_playback(hdsp); 4028 } else { 4029 if (running && 4030 substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 4031 hdsp_silence_playback(hdsp); 4032 } 4033 } else { 4034 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 4035 hdsp_silence_playback(hdsp); 4036 } 4037 _ok: 4038 snd_pcm_trigger_done(substream, substream); 4039 if (!hdsp->running && running) 4040 hdsp_start_audio(hdsp); 4041 else if (hdsp->running && !running) 4042 hdsp_stop_audio(hdsp); 4043 hdsp->running = running; 4044 spin_unlock(&hdsp->lock); 4045 4046 return 0; 4047 } 4048 4049 static int snd_hdsp_prepare(struct snd_pcm_substream *substream) 4050 { 4051 struct hdsp *hdsp = snd_pcm_substream_chip(substream); 4052 int result = 0; 4053 4054 if (hdsp_check_for_iobox (hdsp)) 4055 return -EIO; 4056 4057 if (hdsp_check_for_firmware(hdsp, 1)) 4058 return -EIO; 4059 4060 spin_lock_irq(&hdsp->lock); 4061 if (!hdsp->running) 4062 hdsp_reset_hw_pointer(hdsp); 4063 spin_unlock_irq(&hdsp->lock); 4064 return result; 4065 } 4066 4067 static struct snd_pcm_hardware snd_hdsp_playback_subinfo = 4068 { 4069 .info = (SNDRV_PCM_INFO_MMAP | 4070 SNDRV_PCM_INFO_MMAP_VALID | 4071 SNDRV_PCM_INFO_NONINTERLEAVED | 4072 SNDRV_PCM_INFO_SYNC_START | 4073 SNDRV_PCM_INFO_DOUBLE), 4074 #ifdef SNDRV_BIG_ENDIAN 4075 .formats = SNDRV_PCM_FMTBIT_S32_BE, 4076 #else 4077 .formats = SNDRV_PCM_FMTBIT_S32_LE, 4078 #endif 4079 .rates = (SNDRV_PCM_RATE_32000 | 4080 SNDRV_PCM_RATE_44100 | 4081 SNDRV_PCM_RATE_48000 | 4082 SNDRV_PCM_RATE_64000 | 4083 SNDRV_PCM_RATE_88200 | 4084 SNDRV_PCM_RATE_96000), 4085 .rate_min = 32000, 4086 .rate_max = 96000, 4087 .channels_min = 14, 4088 .channels_max = HDSP_MAX_CHANNELS, 4089 .buffer_bytes_max = HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS, 4090 .period_bytes_min = (64 * 4) * 10, 4091 .period_bytes_max = (8192 * 4) * HDSP_MAX_CHANNELS, 4092 .periods_min = 2, 4093 .periods_max = 2, 4094 .fifo_size = 0 4095 }; 4096 4097 static struct snd_pcm_hardware snd_hdsp_capture_subinfo = 4098 { 4099 .info = (SNDRV_PCM_INFO_MMAP | 4100 SNDRV_PCM_INFO_MMAP_VALID | 4101 SNDRV_PCM_INFO_NONINTERLEAVED | 4102 SNDRV_PCM_INFO_SYNC_START), 4103 #ifdef SNDRV_BIG_ENDIAN 4104 .formats = SNDRV_PCM_FMTBIT_S32_BE, 4105 #else 4106 .formats = SNDRV_PCM_FMTBIT_S32_LE, 4107 #endif 4108 .rates = (SNDRV_PCM_RATE_32000 | 4109 SNDRV_PCM_RATE_44100 | 4110 SNDRV_PCM_RATE_48000 | 4111 SNDRV_PCM_RATE_64000 | 4112 SNDRV_PCM_RATE_88200 | 4113 SNDRV_PCM_RATE_96000), 4114 .rate_min = 32000, 4115 .rate_max = 96000, 4116 .channels_min = 14, 4117 .channels_max = HDSP_MAX_CHANNELS, 4118 .buffer_bytes_max = HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS, 4119 .period_bytes_min = (64 * 4) * 10, 4120 .period_bytes_max = (8192 * 4) * HDSP_MAX_CHANNELS, 4121 .periods_min = 2, 4122 .periods_max = 2, 4123 .fifo_size = 0 4124 }; 4125 4126 static unsigned int hdsp_period_sizes[] = { 64, 128, 256, 512, 1024, 2048, 4096, 8192 }; 4127 4128 static struct snd_pcm_hw_constraint_list hdsp_hw_constraints_period_sizes = { 4129 .count = ARRAY_SIZE(hdsp_period_sizes), 4130 .list = hdsp_period_sizes, 4131 .mask = 0 4132 }; 4133 4134 static unsigned int hdsp_9632_sample_rates[] = { 32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000 }; 4135 4136 static struct snd_pcm_hw_constraint_list hdsp_hw_constraints_9632_sample_rates = { 4137 .count = ARRAY_SIZE(hdsp_9632_sample_rates), 4138 .list = hdsp_9632_sample_rates, 4139 .mask = 0 4140 }; 4141 4142 static int snd_hdsp_hw_rule_in_channels(struct snd_pcm_hw_params *params, 4143 struct snd_pcm_hw_rule *rule) 4144 { 4145 struct hdsp *hdsp = rule->private; 4146 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 4147 if (hdsp->io_type == H9632) { 4148 unsigned int list[3]; 4149 list[0] = hdsp->qs_in_channels; 4150 list[1] = hdsp->ds_in_channels; 4151 list[2] = hdsp->ss_in_channels; 4152 return snd_interval_list(c, 3, list, 0); 4153 } else { 4154 unsigned int list[2]; 4155 list[0] = hdsp->ds_in_channels; 4156 list[1] = hdsp->ss_in_channels; 4157 return snd_interval_list(c, 2, list, 0); 4158 } 4159 } 4160 4161 static int snd_hdsp_hw_rule_out_channels(struct snd_pcm_hw_params *params, 4162 struct snd_pcm_hw_rule *rule) 4163 { 4164 unsigned int list[3]; 4165 struct hdsp *hdsp = rule->private; 4166 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 4167 if (hdsp->io_type == H9632) { 4168 list[0] = hdsp->qs_out_channels; 4169 list[1] = hdsp->ds_out_channels; 4170 list[2] = hdsp->ss_out_channels; 4171 return snd_interval_list(c, 3, list, 0); 4172 } else { 4173 list[0] = hdsp->ds_out_channels; 4174 list[1] = hdsp->ss_out_channels; 4175 } 4176 return snd_interval_list(c, 2, list, 0); 4177 } 4178 4179 static int snd_hdsp_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params, 4180 struct snd_pcm_hw_rule *rule) 4181 { 4182 struct hdsp *hdsp = rule->private; 4183 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 4184 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 4185 if (r->min > 96000 && hdsp->io_type == H9632) { 4186 struct snd_interval t = { 4187 .min = hdsp->qs_in_channels, 4188 .max = hdsp->qs_in_channels, 4189 .integer = 1, 4190 }; 4191 return snd_interval_refine(c, &t); 4192 } else if (r->min > 48000 && r->max <= 96000) { 4193 struct snd_interval t = { 4194 .min = hdsp->ds_in_channels, 4195 .max = hdsp->ds_in_channels, 4196 .integer = 1, 4197 }; 4198 return snd_interval_refine(c, &t); 4199 } else if (r->max < 64000) { 4200 struct snd_interval t = { 4201 .min = hdsp->ss_in_channels, 4202 .max = hdsp->ss_in_channels, 4203 .integer = 1, 4204 }; 4205 return snd_interval_refine(c, &t); 4206 } 4207 return 0; 4208 } 4209 4210 static int snd_hdsp_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params, 4211 struct snd_pcm_hw_rule *rule) 4212 { 4213 struct hdsp *hdsp = rule->private; 4214 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 4215 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 4216 if (r->min > 96000 && hdsp->io_type == H9632) { 4217 struct snd_interval t = { 4218 .min = hdsp->qs_out_channels, 4219 .max = hdsp->qs_out_channels, 4220 .integer = 1, 4221 }; 4222 return snd_interval_refine(c, &t); 4223 } else if (r->min > 48000 && r->max <= 96000) { 4224 struct snd_interval t = { 4225 .min = hdsp->ds_out_channels, 4226 .max = hdsp->ds_out_channels, 4227 .integer = 1, 4228 }; 4229 return snd_interval_refine(c, &t); 4230 } else if (r->max < 64000) { 4231 struct snd_interval t = { 4232 .min = hdsp->ss_out_channels, 4233 .max = hdsp->ss_out_channels, 4234 .integer = 1, 4235 }; 4236 return snd_interval_refine(c, &t); 4237 } 4238 return 0; 4239 } 4240 4241 static int snd_hdsp_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params, 4242 struct snd_pcm_hw_rule *rule) 4243 { 4244 struct hdsp *hdsp = rule->private; 4245 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 4246 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 4247 if (c->min >= hdsp->ss_out_channels) { 4248 struct snd_interval t = { 4249 .min = 32000, 4250 .max = 48000, 4251 .integer = 1, 4252 }; 4253 return snd_interval_refine(r, &t); 4254 } else if (c->max <= hdsp->qs_out_channels && hdsp->io_type == H9632) { 4255 struct snd_interval t = { 4256 .min = 128000, 4257 .max = 192000, 4258 .integer = 1, 4259 }; 4260 return snd_interval_refine(r, &t); 4261 } else if (c->max <= hdsp->ds_out_channels) { 4262 struct snd_interval t = { 4263 .min = 64000, 4264 .max = 96000, 4265 .integer = 1, 4266 }; 4267 return snd_interval_refine(r, &t); 4268 } 4269 return 0; 4270 } 4271 4272 static int snd_hdsp_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params, 4273 struct snd_pcm_hw_rule *rule) 4274 { 4275 struct hdsp *hdsp = rule->private; 4276 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 4277 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 4278 if (c->min >= hdsp->ss_in_channels) { 4279 struct snd_interval t = { 4280 .min = 32000, 4281 .max = 48000, 4282 .integer = 1, 4283 }; 4284 return snd_interval_refine(r, &t); 4285 } else if (c->max <= hdsp->qs_in_channels && hdsp->io_type == H9632) { 4286 struct snd_interval t = { 4287 .min = 128000, 4288 .max = 192000, 4289 .integer = 1, 4290 }; 4291 return snd_interval_refine(r, &t); 4292 } else if (c->max <= hdsp->ds_in_channels) { 4293 struct snd_interval t = { 4294 .min = 64000, 4295 .max = 96000, 4296 .integer = 1, 4297 }; 4298 return snd_interval_refine(r, &t); 4299 } 4300 return 0; 4301 } 4302 4303 static int snd_hdsp_playback_open(struct snd_pcm_substream *substream) 4304 { 4305 struct hdsp *hdsp = snd_pcm_substream_chip(substream); 4306 struct snd_pcm_runtime *runtime = substream->runtime; 4307 4308 if (hdsp_check_for_iobox (hdsp)) 4309 return -EIO; 4310 4311 if (hdsp_check_for_firmware(hdsp, 1)) 4312 return -EIO; 4313 4314 spin_lock_irq(&hdsp->lock); 4315 4316 snd_pcm_set_sync(substream); 4317 4318 runtime->hw = snd_hdsp_playback_subinfo; 4319 runtime->dma_area = hdsp->playback_buffer; 4320 runtime->dma_bytes = HDSP_DMA_AREA_BYTES; 4321 4322 hdsp->playback_pid = current->pid; 4323 hdsp->playback_substream = substream; 4324 4325 spin_unlock_irq(&hdsp->lock); 4326 4327 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24); 4328 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes); 4329 if (hdsp->clock_source_locked) { 4330 runtime->hw.rate_min = runtime->hw.rate_max = hdsp->system_sample_rate; 4331 } else if (hdsp->io_type == H9632) { 4332 runtime->hw.rate_max = 192000; 4333 runtime->hw.rates = SNDRV_PCM_RATE_KNOT; 4334 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates); 4335 } 4336 if (hdsp->io_type == H9632) { 4337 runtime->hw.channels_min = hdsp->qs_out_channels; 4338 runtime->hw.channels_max = hdsp->ss_out_channels; 4339 } 4340 4341 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 4342 snd_hdsp_hw_rule_out_channels, hdsp, 4343 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 4344 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 4345 snd_hdsp_hw_rule_out_channels_rate, hdsp, 4346 SNDRV_PCM_HW_PARAM_RATE, -1); 4347 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 4348 snd_hdsp_hw_rule_rate_out_channels, hdsp, 4349 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 4350 4351 hdsp->creg_spdif_stream = hdsp->creg_spdif; 4352 hdsp->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE; 4353 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE | 4354 SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id); 4355 return 0; 4356 } 4357 4358 static int snd_hdsp_playback_release(struct snd_pcm_substream *substream) 4359 { 4360 struct hdsp *hdsp = snd_pcm_substream_chip(substream); 4361 4362 spin_lock_irq(&hdsp->lock); 4363 4364 hdsp->playback_pid = -1; 4365 hdsp->playback_substream = NULL; 4366 4367 spin_unlock_irq(&hdsp->lock); 4368 4369 hdsp->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE; 4370 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE | 4371 SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id); 4372 return 0; 4373 } 4374 4375 4376 static int snd_hdsp_capture_open(struct snd_pcm_substream *substream) 4377 { 4378 struct hdsp *hdsp = snd_pcm_substream_chip(substream); 4379 struct snd_pcm_runtime *runtime = substream->runtime; 4380 4381 if (hdsp_check_for_iobox (hdsp)) 4382 return -EIO; 4383 4384 if (hdsp_check_for_firmware(hdsp, 1)) 4385 return -EIO; 4386 4387 spin_lock_irq(&hdsp->lock); 4388 4389 snd_pcm_set_sync(substream); 4390 4391 runtime->hw = snd_hdsp_capture_subinfo; 4392 runtime->dma_area = hdsp->capture_buffer; 4393 runtime->dma_bytes = HDSP_DMA_AREA_BYTES; 4394 4395 hdsp->capture_pid = current->pid; 4396 hdsp->capture_substream = substream; 4397 4398 spin_unlock_irq(&hdsp->lock); 4399 4400 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24); 4401 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes); 4402 if (hdsp->io_type == H9632) { 4403 runtime->hw.channels_min = hdsp->qs_in_channels; 4404 runtime->hw.channels_max = hdsp->ss_in_channels; 4405 runtime->hw.rate_max = 192000; 4406 runtime->hw.rates = SNDRV_PCM_RATE_KNOT; 4407 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates); 4408 } 4409 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 4410 snd_hdsp_hw_rule_in_channels, hdsp, 4411 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 4412 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 4413 snd_hdsp_hw_rule_in_channels_rate, hdsp, 4414 SNDRV_PCM_HW_PARAM_RATE, -1); 4415 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 4416 snd_hdsp_hw_rule_rate_in_channels, hdsp, 4417 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 4418 return 0; 4419 } 4420 4421 static int snd_hdsp_capture_release(struct snd_pcm_substream *substream) 4422 { 4423 struct hdsp *hdsp = snd_pcm_substream_chip(substream); 4424 4425 spin_lock_irq(&hdsp->lock); 4426 4427 hdsp->capture_pid = -1; 4428 hdsp->capture_substream = NULL; 4429 4430 spin_unlock_irq(&hdsp->lock); 4431 return 0; 4432 } 4433 4434 static int snd_hdsp_hwdep_dummy_op(struct snd_hwdep *hw, struct file *file) 4435 { 4436 /* we have nothing to initialize but the call is required */ 4437 return 0; 4438 } 4439 4440 4441 /* helper functions for copying meter values */ 4442 static inline int copy_u32_le(void __user *dest, void __iomem *src) 4443 { 4444 u32 val = readl(src); 4445 return copy_to_user(dest, &val, 4); 4446 } 4447 4448 static inline int copy_u64_le(void __user *dest, void __iomem *src_low, void __iomem *src_high) 4449 { 4450 u32 rms_low, rms_high; 4451 u64 rms; 4452 rms_low = readl(src_low); 4453 rms_high = readl(src_high); 4454 rms = ((u64)rms_high << 32) | rms_low; 4455 return copy_to_user(dest, &rms, 8); 4456 } 4457 4458 static inline int copy_u48_le(void __user *dest, void __iomem *src_low, void __iomem *src_high) 4459 { 4460 u32 rms_low, rms_high; 4461 u64 rms; 4462 rms_low = readl(src_low) & 0xffffff00; 4463 rms_high = readl(src_high) & 0xffffff00; 4464 rms = ((u64)rms_high << 32) | rms_low; 4465 return copy_to_user(dest, &rms, 8); 4466 } 4467 4468 static int hdsp_9652_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms) 4469 { 4470 int doublespeed = 0; 4471 int i, j, channels, ofs; 4472 4473 if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus) 4474 doublespeed = 1; 4475 channels = doublespeed ? 14 : 26; 4476 for (i = 0, j = 0; i < 26; ++i) { 4477 if (doublespeed && (i & 4)) 4478 continue; 4479 ofs = HDSP_9652_peakBase - j * 4; 4480 if (copy_u32_le(&peak_rms->input_peaks[i], hdsp->iobase + ofs)) 4481 return -EFAULT; 4482 ofs -= channels * 4; 4483 if (copy_u32_le(&peak_rms->playback_peaks[i], hdsp->iobase + ofs)) 4484 return -EFAULT; 4485 ofs -= channels * 4; 4486 if (copy_u32_le(&peak_rms->output_peaks[i], hdsp->iobase + ofs)) 4487 return -EFAULT; 4488 ofs = HDSP_9652_rmsBase + j * 8; 4489 if (copy_u48_le(&peak_rms->input_rms[i], hdsp->iobase + ofs, 4490 hdsp->iobase + ofs + 4)) 4491 return -EFAULT; 4492 ofs += channels * 8; 4493 if (copy_u48_le(&peak_rms->playback_rms[i], hdsp->iobase + ofs, 4494 hdsp->iobase + ofs + 4)) 4495 return -EFAULT; 4496 ofs += channels * 8; 4497 if (copy_u48_le(&peak_rms->output_rms[i], hdsp->iobase + ofs, 4498 hdsp->iobase + ofs + 4)) 4499 return -EFAULT; 4500 j++; 4501 } 4502 return 0; 4503 } 4504 4505 static int hdsp_9632_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms) 4506 { 4507 int i, j; 4508 struct hdsp_9632_meters __iomem *m; 4509 int doublespeed = 0; 4510 4511 if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus) 4512 doublespeed = 1; 4513 m = (struct hdsp_9632_meters __iomem *)(hdsp->iobase+HDSP_9632_metersBase); 4514 for (i = 0, j = 0; i < 16; ++i, ++j) { 4515 if (copy_u32_le(&peak_rms->input_peaks[i], &m->input_peak[j])) 4516 return -EFAULT; 4517 if (copy_u32_le(&peak_rms->playback_peaks[i], &m->playback_peak[j])) 4518 return -EFAULT; 4519 if (copy_u32_le(&peak_rms->output_peaks[i], &m->output_peak[j])) 4520 return -EFAULT; 4521 if (copy_u64_le(&peak_rms->input_rms[i], &m->input_rms_low[j], 4522 &m->input_rms_high[j])) 4523 return -EFAULT; 4524 if (copy_u64_le(&peak_rms->playback_rms[i], &m->playback_rms_low[j], 4525 &m->playback_rms_high[j])) 4526 return -EFAULT; 4527 if (copy_u64_le(&peak_rms->output_rms[i], &m->output_rms_low[j], 4528 &m->output_rms_high[j])) 4529 return -EFAULT; 4530 if (doublespeed && i == 3) i += 4; 4531 } 4532 return 0; 4533 } 4534 4535 static int hdsp_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms) 4536 { 4537 int i; 4538 4539 for (i = 0; i < 26; i++) { 4540 if (copy_u32_le(&peak_rms->playback_peaks[i], 4541 hdsp->iobase + HDSP_playbackPeakLevel + i * 4)) 4542 return -EFAULT; 4543 if (copy_u32_le(&peak_rms->input_peaks[i], 4544 hdsp->iobase + HDSP_inputPeakLevel + i * 4)) 4545 return -EFAULT; 4546 } 4547 for (i = 0; i < 28; i++) { 4548 if (copy_u32_le(&peak_rms->output_peaks[i], 4549 hdsp->iobase + HDSP_outputPeakLevel + i * 4)) 4550 return -EFAULT; 4551 } 4552 for (i = 0; i < 26; ++i) { 4553 if (copy_u64_le(&peak_rms->playback_rms[i], 4554 hdsp->iobase + HDSP_playbackRmsLevel + i * 8 + 4, 4555 hdsp->iobase + HDSP_playbackRmsLevel + i * 8)) 4556 return -EFAULT; 4557 if (copy_u64_le(&peak_rms->input_rms[i], 4558 hdsp->iobase + HDSP_inputRmsLevel + i * 8 + 4, 4559 hdsp->iobase + HDSP_inputRmsLevel + i * 8)) 4560 return -EFAULT; 4561 } 4562 return 0; 4563 } 4564 4565 static int snd_hdsp_hwdep_ioctl(struct snd_hwdep *hw, struct file *file, unsigned int cmd, unsigned long arg) 4566 { 4567 struct hdsp *hdsp = (struct hdsp *)hw->private_data; 4568 void __user *argp = (void __user *)arg; 4569 4570 switch (cmd) { 4571 case SNDRV_HDSP_IOCTL_GET_PEAK_RMS: { 4572 struct hdsp_peak_rms __user *peak_rms = (struct hdsp_peak_rms __user *)arg; 4573 4574 if (!(hdsp->state & HDSP_FirmwareLoaded)) { 4575 snd_printk(KERN_ERR "Hammerfall-DSP: firmware needs to be uploaded to the card.\n"); 4576 return -EINVAL; 4577 } 4578 4579 switch (hdsp->io_type) { 4580 case H9652: 4581 return hdsp_9652_get_peak(hdsp, peak_rms); 4582 case H9632: 4583 return hdsp_9632_get_peak(hdsp, peak_rms); 4584 default: 4585 return hdsp_get_peak(hdsp, peak_rms); 4586 } 4587 } 4588 case SNDRV_HDSP_IOCTL_GET_CONFIG_INFO: { 4589 struct hdsp_config_info info; 4590 unsigned long flags; 4591 int i; 4592 4593 if (!(hdsp->state & HDSP_FirmwareLoaded)) { 4594 snd_printk(KERN_ERR "Hammerfall-DSP: Firmware needs to be uploaded to the card.\n"); 4595 return -EINVAL; 4596 } 4597 spin_lock_irqsave(&hdsp->lock, flags); 4598 info.pref_sync_ref = (unsigned char)hdsp_pref_sync_ref(hdsp); 4599 info.wordclock_sync_check = (unsigned char)hdsp_wc_sync_check(hdsp); 4600 if (hdsp->io_type != H9632) 4601 info.adatsync_sync_check = (unsigned char)hdsp_adatsync_sync_check(hdsp); 4602 info.spdif_sync_check = (unsigned char)hdsp_spdif_sync_check(hdsp); 4603 for (i = 0; i < ((hdsp->io_type != Multiface && hdsp->io_type != H9632) ? 3 : 1); ++i) 4604 info.adat_sync_check[i] = (unsigned char)hdsp_adat_sync_check(hdsp, i); 4605 info.spdif_in = (unsigned char)hdsp_spdif_in(hdsp); 4606 info.spdif_out = (unsigned char)hdsp_spdif_out(hdsp); 4607 info.spdif_professional = (unsigned char)hdsp_spdif_professional(hdsp); 4608 info.spdif_emphasis = (unsigned char)hdsp_spdif_emphasis(hdsp); 4609 info.spdif_nonaudio = (unsigned char)hdsp_spdif_nonaudio(hdsp); 4610 info.spdif_sample_rate = hdsp_spdif_sample_rate(hdsp); 4611 info.system_sample_rate = hdsp->system_sample_rate; 4612 info.autosync_sample_rate = hdsp_external_sample_rate(hdsp); 4613 info.system_clock_mode = (unsigned char)hdsp_system_clock_mode(hdsp); 4614 info.clock_source = (unsigned char)hdsp_clock_source(hdsp); 4615 info.autosync_ref = (unsigned char)hdsp_autosync_ref(hdsp); 4616 info.line_out = (unsigned char)hdsp_line_out(hdsp); 4617 if (hdsp->io_type == H9632) { 4618 info.da_gain = (unsigned char)hdsp_da_gain(hdsp); 4619 info.ad_gain = (unsigned char)hdsp_ad_gain(hdsp); 4620 info.phone_gain = (unsigned char)hdsp_phone_gain(hdsp); 4621 info.xlr_breakout_cable = (unsigned char)hdsp_xlr_breakout_cable(hdsp); 4622 4623 } 4624 if (hdsp->io_type == H9632 || hdsp->io_type == H9652) 4625 info.analog_extension_board = (unsigned char)hdsp_aeb(hdsp); 4626 spin_unlock_irqrestore(&hdsp->lock, flags); 4627 if (copy_to_user(argp, &info, sizeof(info))) 4628 return -EFAULT; 4629 break; 4630 } 4631 case SNDRV_HDSP_IOCTL_GET_9632_AEB: { 4632 struct hdsp_9632_aeb h9632_aeb; 4633 4634 if (hdsp->io_type != H9632) return -EINVAL; 4635 h9632_aeb.aebi = hdsp->ss_in_channels - H9632_SS_CHANNELS; 4636 h9632_aeb.aebo = hdsp->ss_out_channels - H9632_SS_CHANNELS; 4637 if (copy_to_user(argp, &h9632_aeb, sizeof(h9632_aeb))) 4638 return -EFAULT; 4639 break; 4640 } 4641 case SNDRV_HDSP_IOCTL_GET_VERSION: { 4642 struct hdsp_version hdsp_version; 4643 int err; 4644 4645 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL; 4646 if (hdsp->io_type == Undefined) { 4647 if ((err = hdsp_get_iobox_version(hdsp)) < 0) 4648 return err; 4649 } 4650 hdsp_version.io_type = hdsp->io_type; 4651 hdsp_version.firmware_rev = hdsp->firmware_rev; 4652 if ((err = copy_to_user(argp, &hdsp_version, sizeof(hdsp_version)))) 4653 return -EFAULT; 4654 break; 4655 } 4656 case SNDRV_HDSP_IOCTL_UPLOAD_FIRMWARE: { 4657 struct hdsp_firmware __user *firmware; 4658 u32 __user *firmware_data; 4659 int err; 4660 4661 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL; 4662 /* SNDRV_HDSP_IOCTL_GET_VERSION must have been called */ 4663 if (hdsp->io_type == Undefined) return -EINVAL; 4664 4665 if (hdsp->state & (HDSP_FirmwareCached | HDSP_FirmwareLoaded)) 4666 return -EBUSY; 4667 4668 snd_printk(KERN_INFO "Hammerfall-DSP: initializing firmware upload\n"); 4669 firmware = (struct hdsp_firmware __user *)argp; 4670 4671 if (get_user(firmware_data, &firmware->firmware_data)) 4672 return -EFAULT; 4673 4674 if (hdsp_check_for_iobox (hdsp)) 4675 return -EIO; 4676 4677 if (copy_from_user(hdsp->firmware_cache, firmware_data, sizeof(hdsp->firmware_cache)) != 0) 4678 return -EFAULT; 4679 4680 hdsp->state |= HDSP_FirmwareCached; 4681 4682 if ((err = snd_hdsp_load_firmware_from_cache(hdsp)) < 0) 4683 return err; 4684 4685 if (!(hdsp->state & HDSP_InitializationComplete)) { 4686 if ((err = snd_hdsp_enable_io(hdsp)) < 0) 4687 return err; 4688 4689 snd_hdsp_initialize_channels(hdsp); 4690 snd_hdsp_initialize_midi_flush(hdsp); 4691 4692 if ((err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp)) < 0) { 4693 snd_printk(KERN_ERR "Hammerfall-DSP: error creating alsa devices\n"); 4694 return err; 4695 } 4696 } 4697 break; 4698 } 4699 case SNDRV_HDSP_IOCTL_GET_MIXER: { 4700 struct hdsp_mixer __user *mixer = (struct hdsp_mixer __user *)argp; 4701 if (copy_to_user(mixer->matrix, hdsp->mixer_matrix, sizeof(unsigned short)*HDSP_MATRIX_MIXER_SIZE)) 4702 return -EFAULT; 4703 break; 4704 } 4705 default: 4706 return -EINVAL; 4707 } 4708 return 0; 4709 } 4710 4711 static struct snd_pcm_ops snd_hdsp_playback_ops = { 4712 .open = snd_hdsp_playback_open, 4713 .close = snd_hdsp_playback_release, 4714 .ioctl = snd_hdsp_ioctl, 4715 .hw_params = snd_hdsp_hw_params, 4716 .prepare = snd_hdsp_prepare, 4717 .trigger = snd_hdsp_trigger, 4718 .pointer = snd_hdsp_hw_pointer, 4719 .copy = snd_hdsp_playback_copy, 4720 .silence = snd_hdsp_hw_silence, 4721 }; 4722 4723 static struct snd_pcm_ops snd_hdsp_capture_ops = { 4724 .open = snd_hdsp_capture_open, 4725 .close = snd_hdsp_capture_release, 4726 .ioctl = snd_hdsp_ioctl, 4727 .hw_params = snd_hdsp_hw_params, 4728 .prepare = snd_hdsp_prepare, 4729 .trigger = snd_hdsp_trigger, 4730 .pointer = snd_hdsp_hw_pointer, 4731 .copy = snd_hdsp_capture_copy, 4732 }; 4733 4734 static int __devinit snd_hdsp_create_hwdep(struct snd_card *card, 4735 struct hdsp *hdsp) 4736 { 4737 struct snd_hwdep *hw; 4738 int err; 4739 4740 if ((err = snd_hwdep_new(card, "HDSP hwdep", 0, &hw)) < 0) 4741 return err; 4742 4743 hdsp->hwdep = hw; 4744 hw->private_data = hdsp; 4745 strcpy(hw->name, "HDSP hwdep interface"); 4746 4747 hw->ops.open = snd_hdsp_hwdep_dummy_op; 4748 hw->ops.ioctl = snd_hdsp_hwdep_ioctl; 4749 hw->ops.release = snd_hdsp_hwdep_dummy_op; 4750 4751 return 0; 4752 } 4753 4754 static int snd_hdsp_create_pcm(struct snd_card *card, struct hdsp *hdsp) 4755 { 4756 struct snd_pcm *pcm; 4757 int err; 4758 4759 if ((err = snd_pcm_new(card, hdsp->card_name, 0, 1, 1, &pcm)) < 0) 4760 return err; 4761 4762 hdsp->pcm = pcm; 4763 pcm->private_data = hdsp; 4764 strcpy(pcm->name, hdsp->card_name); 4765 4766 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_hdsp_playback_ops); 4767 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_hdsp_capture_ops); 4768 4769 pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX; 4770 4771 return 0; 4772 } 4773 4774 static void snd_hdsp_9652_enable_mixer (struct hdsp *hdsp) 4775 { 4776 hdsp->control2_register |= HDSP_9652_ENABLE_MIXER; 4777 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register); 4778 } 4779 4780 static int snd_hdsp_enable_io (struct hdsp *hdsp) 4781 { 4782 int i; 4783 4784 if (hdsp_fifo_wait (hdsp, 0, 100)) { 4785 snd_printk(KERN_ERR "Hammerfall-DSP: enable_io fifo_wait failed\n"); 4786 return -EIO; 4787 } 4788 4789 for (i = 0; i < hdsp->max_channels; ++i) { 4790 hdsp_write (hdsp, HDSP_inputEnable + (4 * i), 1); 4791 hdsp_write (hdsp, HDSP_outputEnable + (4 * i), 1); 4792 } 4793 4794 return 0; 4795 } 4796 4797 static void snd_hdsp_initialize_channels(struct hdsp *hdsp) 4798 { 4799 int status, aebi_channels, aebo_channels; 4800 4801 switch (hdsp->io_type) { 4802 case Digiface: 4803 hdsp->card_name = "RME Hammerfall DSP + Digiface"; 4804 hdsp->ss_in_channels = hdsp->ss_out_channels = DIGIFACE_SS_CHANNELS; 4805 hdsp->ds_in_channels = hdsp->ds_out_channels = DIGIFACE_DS_CHANNELS; 4806 break; 4807 4808 case H9652: 4809 hdsp->card_name = "RME Hammerfall HDSP 9652"; 4810 hdsp->ss_in_channels = hdsp->ss_out_channels = H9652_SS_CHANNELS; 4811 hdsp->ds_in_channels = hdsp->ds_out_channels = H9652_DS_CHANNELS; 4812 break; 4813 4814 case H9632: 4815 status = hdsp_read(hdsp, HDSP_statusRegister); 4816 /* HDSP_AEBx bits are low when AEB are connected */ 4817 aebi_channels = (status & HDSP_AEBI) ? 0 : 4; 4818 aebo_channels = (status & HDSP_AEBO) ? 0 : 4; 4819 hdsp->card_name = "RME Hammerfall HDSP 9632"; 4820 hdsp->ss_in_channels = H9632_SS_CHANNELS+aebi_channels; 4821 hdsp->ds_in_channels = H9632_DS_CHANNELS+aebi_channels; 4822 hdsp->qs_in_channels = H9632_QS_CHANNELS+aebi_channels; 4823 hdsp->ss_out_channels = H9632_SS_CHANNELS+aebo_channels; 4824 hdsp->ds_out_channels = H9632_DS_CHANNELS+aebo_channels; 4825 hdsp->qs_out_channels = H9632_QS_CHANNELS+aebo_channels; 4826 break; 4827 4828 case Multiface: 4829 hdsp->card_name = "RME Hammerfall DSP + Multiface"; 4830 hdsp->ss_in_channels = hdsp->ss_out_channels = MULTIFACE_SS_CHANNELS; 4831 hdsp->ds_in_channels = hdsp->ds_out_channels = MULTIFACE_DS_CHANNELS; 4832 break; 4833 4834 default: 4835 /* should never get here */ 4836 break; 4837 } 4838 } 4839 4840 static void snd_hdsp_initialize_midi_flush (struct hdsp *hdsp) 4841 { 4842 snd_hdsp_flush_midi_input (hdsp, 0); 4843 snd_hdsp_flush_midi_input (hdsp, 1); 4844 } 4845 4846 static int snd_hdsp_create_alsa_devices(struct snd_card *card, struct hdsp *hdsp) 4847 { 4848 int err; 4849 4850 if ((err = snd_hdsp_create_pcm(card, hdsp)) < 0) { 4851 snd_printk(KERN_ERR "Hammerfall-DSP: Error creating pcm interface\n"); 4852 return err; 4853 } 4854 4855 4856 if ((err = snd_hdsp_create_midi(card, hdsp, 0)) < 0) { 4857 snd_printk(KERN_ERR "Hammerfall-DSP: Error creating first midi interface\n"); 4858 return err; 4859 } 4860 4861 if (hdsp->io_type == Digiface || hdsp->io_type == H9652) { 4862 if ((err = snd_hdsp_create_midi(card, hdsp, 1)) < 0) { 4863 snd_printk(KERN_ERR "Hammerfall-DSP: Error creating second midi interface\n"); 4864 return err; 4865 } 4866 } 4867 4868 if ((err = snd_hdsp_create_controls(card, hdsp)) < 0) { 4869 snd_printk(KERN_ERR "Hammerfall-DSP: Error creating ctl interface\n"); 4870 return err; 4871 } 4872 4873 snd_hdsp_proc_init(hdsp); 4874 4875 hdsp->system_sample_rate = -1; 4876 hdsp->playback_pid = -1; 4877 hdsp->capture_pid = -1; 4878 hdsp->capture_substream = NULL; 4879 hdsp->playback_substream = NULL; 4880 4881 if ((err = snd_hdsp_set_defaults(hdsp)) < 0) { 4882 snd_printk(KERN_ERR "Hammerfall-DSP: Error setting default values\n"); 4883 return err; 4884 } 4885 4886 if (!(hdsp->state & HDSP_InitializationComplete)) { 4887 strcpy(card->shortname, "Hammerfall DSP"); 4888 sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name, 4889 hdsp->port, hdsp->irq); 4890 4891 if ((err = snd_card_register(card)) < 0) { 4892 snd_printk(KERN_ERR "Hammerfall-DSP: error registering card\n"); 4893 return err; 4894 } 4895 hdsp->state |= HDSP_InitializationComplete; 4896 } 4897 4898 return 0; 4899 } 4900 4901 #ifdef HDSP_FW_LOADER 4902 /* load firmware via hotplug fw loader */ 4903 static int __devinit hdsp_request_fw_loader(struct hdsp *hdsp) 4904 { 4905 const char *fwfile; 4906 const struct firmware *fw; 4907 int err; 4908 4909 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) 4910 return 0; 4911 if (hdsp->io_type == Undefined) { 4912 if ((err = hdsp_get_iobox_version(hdsp)) < 0) 4913 return err; 4914 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) 4915 return 0; 4916 } 4917 4918 /* caution: max length of firmware filename is 30! */ 4919 switch (hdsp->io_type) { 4920 case Multiface: 4921 if (hdsp->firmware_rev == 0xa) 4922 fwfile = "multiface_firmware.bin"; 4923 else 4924 fwfile = "multiface_firmware_rev11.bin"; 4925 break; 4926 case Digiface: 4927 if (hdsp->firmware_rev == 0xa) 4928 fwfile = "digiface_firmware.bin"; 4929 else 4930 fwfile = "digiface_firmware_rev11.bin"; 4931 break; 4932 default: 4933 snd_printk(KERN_ERR "Hammerfall-DSP: invalid io_type %d\n", hdsp->io_type); 4934 return -EINVAL; 4935 } 4936 4937 if (request_firmware(&fw, fwfile, &hdsp->pci->dev)) { 4938 snd_printk(KERN_ERR "Hammerfall-DSP: cannot load firmware %s\n", fwfile); 4939 return -ENOENT; 4940 } 4941 if (fw->size < sizeof(hdsp->firmware_cache)) { 4942 snd_printk(KERN_ERR "Hammerfall-DSP: too short firmware size %d (expected %d)\n", 4943 (int)fw->size, (int)sizeof(hdsp->firmware_cache)); 4944 release_firmware(fw); 4945 return -EINVAL; 4946 } 4947 4948 memcpy(hdsp->firmware_cache, fw->data, sizeof(hdsp->firmware_cache)); 4949 4950 release_firmware(fw); 4951 4952 hdsp->state |= HDSP_FirmwareCached; 4953 4954 if ((err = snd_hdsp_load_firmware_from_cache(hdsp)) < 0) 4955 return err; 4956 4957 if (!(hdsp->state & HDSP_InitializationComplete)) { 4958 if ((err = snd_hdsp_enable_io(hdsp)) < 0) 4959 return err; 4960 4961 if ((err = snd_hdsp_create_hwdep(hdsp->card, hdsp)) < 0) { 4962 snd_printk(KERN_ERR "Hammerfall-DSP: error creating hwdep device\n"); 4963 return err; 4964 } 4965 snd_hdsp_initialize_channels(hdsp); 4966 snd_hdsp_initialize_midi_flush(hdsp); 4967 if ((err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp)) < 0) { 4968 snd_printk(KERN_ERR "Hammerfall-DSP: error creating alsa devices\n"); 4969 return err; 4970 } 4971 } 4972 return 0; 4973 } 4974 #endif 4975 4976 static int __devinit snd_hdsp_create(struct snd_card *card, 4977 struct hdsp *hdsp) 4978 { 4979 struct pci_dev *pci = hdsp->pci; 4980 int err; 4981 int is_9652 = 0; 4982 int is_9632 = 0; 4983 4984 hdsp->irq = -1; 4985 hdsp->state = 0; 4986 hdsp->midi[0].rmidi = NULL; 4987 hdsp->midi[1].rmidi = NULL; 4988 hdsp->midi[0].input = NULL; 4989 hdsp->midi[1].input = NULL; 4990 hdsp->midi[0].output = NULL; 4991 hdsp->midi[1].output = NULL; 4992 hdsp->midi[0].pending = 0; 4993 hdsp->midi[1].pending = 0; 4994 spin_lock_init(&hdsp->midi[0].lock); 4995 spin_lock_init(&hdsp->midi[1].lock); 4996 hdsp->iobase = NULL; 4997 hdsp->control_register = 0; 4998 hdsp->control2_register = 0; 4999 hdsp->io_type = Undefined; 5000 hdsp->max_channels = 26; 5001 5002 hdsp->card = card; 5003 5004 spin_lock_init(&hdsp->lock); 5005 5006 tasklet_init(&hdsp->midi_tasklet, hdsp_midi_tasklet, (unsigned long)hdsp); 5007 5008 pci_read_config_word(hdsp->pci, PCI_CLASS_REVISION, &hdsp->firmware_rev); 5009 hdsp->firmware_rev &= 0xff; 5010 5011 /* From Martin Bjoernsen : 5012 "It is important that the card's latency timer register in 5013 the PCI configuration space is set to a value much larger 5014 than 0 by the computer's BIOS or the driver. 5015 The windows driver always sets this 8 bit register [...] 5016 to its maximum 255 to avoid problems with some computers." 5017 */ 5018 pci_write_config_byte(hdsp->pci, PCI_LATENCY_TIMER, 0xFF); 5019 5020 strcpy(card->driver, "H-DSP"); 5021 strcpy(card->mixername, "Xilinx FPGA"); 5022 5023 if (hdsp->firmware_rev < 0xa) 5024 return -ENODEV; 5025 else if (hdsp->firmware_rev < 0x64) 5026 hdsp->card_name = "RME Hammerfall DSP"; 5027 else if (hdsp->firmware_rev < 0x96) { 5028 hdsp->card_name = "RME HDSP 9652"; 5029 is_9652 = 1; 5030 } else { 5031 hdsp->card_name = "RME HDSP 9632"; 5032 hdsp->max_channels = 16; 5033 is_9632 = 1; 5034 } 5035 5036 if ((err = pci_enable_device(pci)) < 0) 5037 return err; 5038 5039 pci_set_master(hdsp->pci); 5040 5041 if ((err = pci_request_regions(pci, "hdsp")) < 0) 5042 return err; 5043 hdsp->port = pci_resource_start(pci, 0); 5044 if ((hdsp->iobase = ioremap_nocache(hdsp->port, HDSP_IO_EXTENT)) == NULL) { 5045 snd_printk(KERN_ERR "Hammerfall-DSP: unable to remap region 0x%lx-0x%lx\n", hdsp->port, hdsp->port + HDSP_IO_EXTENT - 1); 5046 return -EBUSY; 5047 } 5048 5049 if (request_irq(pci->irq, snd_hdsp_interrupt, IRQF_SHARED, 5050 "hdsp", hdsp)) { 5051 snd_printk(KERN_ERR "Hammerfall-DSP: unable to use IRQ %d\n", pci->irq); 5052 return -EBUSY; 5053 } 5054 5055 hdsp->irq = pci->irq; 5056 hdsp->precise_ptr = 0; 5057 hdsp->use_midi_tasklet = 1; 5058 hdsp->dds_value = 0; 5059 5060 if ((err = snd_hdsp_initialize_memory(hdsp)) < 0) 5061 return err; 5062 5063 if (!is_9652 && !is_9632) { 5064 /* we wait 2 seconds to let freshly inserted cardbus cards do their hardware init */ 5065 ssleep(2); 5066 5067 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) { 5068 #ifdef HDSP_FW_LOADER 5069 if ((err = hdsp_request_fw_loader(hdsp)) < 0) 5070 /* we don't fail as this can happen 5071 if userspace is not ready for 5072 firmware upload 5073 */ 5074 snd_printk(KERN_ERR "Hammerfall-DSP: couldn't get firmware from userspace. try using hdsploader\n"); 5075 else 5076 /* init is complete, we return */ 5077 return 0; 5078 #endif 5079 /* no iobox connected, we defer initialization */ 5080 snd_printk(KERN_INFO "Hammerfall-DSP: card initialization pending : waiting for firmware\n"); 5081 if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0) 5082 return err; 5083 return 0; 5084 } else { 5085 snd_printk(KERN_INFO "Hammerfall-DSP: Firmware already present, initializing card.\n"); 5086 if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1) 5087 hdsp->io_type = Multiface; 5088 else 5089 hdsp->io_type = Digiface; 5090 } 5091 } 5092 5093 if ((err = snd_hdsp_enable_io(hdsp)) != 0) 5094 return err; 5095 5096 if (is_9652) 5097 hdsp->io_type = H9652; 5098 5099 if (is_9632) 5100 hdsp->io_type = H9632; 5101 5102 if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0) 5103 return err; 5104 5105 snd_hdsp_initialize_channels(hdsp); 5106 snd_hdsp_initialize_midi_flush(hdsp); 5107 5108 hdsp->state |= HDSP_FirmwareLoaded; 5109 5110 if ((err = snd_hdsp_create_alsa_devices(card, hdsp)) < 0) 5111 return err; 5112 5113 return 0; 5114 } 5115 5116 static int snd_hdsp_free(struct hdsp *hdsp) 5117 { 5118 if (hdsp->port) { 5119 /* stop the audio, and cancel all interrupts */ 5120 tasklet_kill(&hdsp->midi_tasklet); 5121 hdsp->control_register &= ~(HDSP_Start|HDSP_AudioInterruptEnable|HDSP_Midi0InterruptEnable|HDSP_Midi1InterruptEnable); 5122 hdsp_write (hdsp, HDSP_controlRegister, hdsp->control_register); 5123 } 5124 5125 if (hdsp->irq >= 0) 5126 free_irq(hdsp->irq, (void *)hdsp); 5127 5128 snd_hdsp_free_buffers(hdsp); 5129 5130 if (hdsp->iobase) 5131 iounmap(hdsp->iobase); 5132 5133 if (hdsp->port) 5134 pci_release_regions(hdsp->pci); 5135 5136 pci_disable_device(hdsp->pci); 5137 return 0; 5138 } 5139 5140 static void snd_hdsp_card_free(struct snd_card *card) 5141 { 5142 struct hdsp *hdsp = (struct hdsp *) card->private_data; 5143 5144 if (hdsp) 5145 snd_hdsp_free(hdsp); 5146 } 5147 5148 static int __devinit snd_hdsp_probe(struct pci_dev *pci, 5149 const struct pci_device_id *pci_id) 5150 { 5151 static int dev; 5152 struct hdsp *hdsp; 5153 struct snd_card *card; 5154 int err; 5155 5156 if (dev >= SNDRV_CARDS) 5157 return -ENODEV; 5158 if (!enable[dev]) { 5159 dev++; 5160 return -ENOENT; 5161 } 5162 5163 if (!(card = snd_card_new(index[dev], id[dev], THIS_MODULE, sizeof(struct hdsp)))) 5164 return -ENOMEM; 5165 5166 hdsp = (struct hdsp *) card->private_data; 5167 card->private_free = snd_hdsp_card_free; 5168 hdsp->dev = dev; 5169 hdsp->pci = pci; 5170 snd_card_set_dev(card, &pci->dev); 5171 5172 if ((err = snd_hdsp_create(card, hdsp)) < 0) { 5173 snd_card_free(card); 5174 return err; 5175 } 5176 5177 strcpy(card->shortname, "Hammerfall DSP"); 5178 sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name, 5179 hdsp->port, hdsp->irq); 5180 5181 if ((err = snd_card_register(card)) < 0) { 5182 snd_card_free(card); 5183 return err; 5184 } 5185 pci_set_drvdata(pci, card); 5186 dev++; 5187 return 0; 5188 } 5189 5190 static void __devexit snd_hdsp_remove(struct pci_dev *pci) 5191 { 5192 snd_card_free(pci_get_drvdata(pci)); 5193 pci_set_drvdata(pci, NULL); 5194 } 5195 5196 static struct pci_driver driver = { 5197 .name = "RME Hammerfall DSP", 5198 .id_table = snd_hdsp_ids, 5199 .probe = snd_hdsp_probe, 5200 .remove = __devexit_p(snd_hdsp_remove), 5201 }; 5202 5203 static int __init alsa_card_hdsp_init(void) 5204 { 5205 return pci_register_driver(&driver); 5206 } 5207 5208 static void __exit alsa_card_hdsp_exit(void) 5209 { 5210 pci_unregister_driver(&driver); 5211 } 5212 5213 module_init(alsa_card_hdsp_init) 5214 module_exit(alsa_card_hdsp_exit) 5215