1 /* 2 * ALSA driver for RME Digi96, Digi96/8 and Digi96/8 PRO/PAD/PST audio 3 * interfaces 4 * 5 * Copyright (c) 2000, 2001 Anders Torger <torger@ludd.luth.se> 6 * 7 * Thanks to Henk Hesselink <henk@anda.nl> for the analog volume control 8 * code. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 23 * 24 */ 25 26 #include <linux/delay.h> 27 #include <linux/init.h> 28 #include <linux/interrupt.h> 29 #include <linux/pci.h> 30 #include <linux/slab.h> 31 #include <linux/moduleparam.h> 32 33 #include <sound/core.h> 34 #include <sound/info.h> 35 #include <sound/control.h> 36 #include <sound/pcm.h> 37 #include <sound/pcm_params.h> 38 #include <sound/asoundef.h> 39 #include <sound/initval.h> 40 41 #include <asm/io.h> 42 43 /* note, two last pcis should be equal, it is not a bug */ 44 45 MODULE_AUTHOR("Anders Torger <torger@ludd.luth.se>"); 46 MODULE_DESCRIPTION("RME Digi96, Digi96/8, Digi96/8 PRO, Digi96/8 PST, " 47 "Digi96/8 PAD"); 48 MODULE_LICENSE("GPL"); 49 MODULE_SUPPORTED_DEVICE("{{RME,Digi96}," 50 "{RME,Digi96/8}," 51 "{RME,Digi96/8 PRO}," 52 "{RME,Digi96/8 PST}," 53 "{RME,Digi96/8 PAD}}"); 54 55 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ 56 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ 57 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */ 58 59 module_param_array(index, int, NULL, 0444); 60 MODULE_PARM_DESC(index, "Index value for RME Digi96 soundcard."); 61 module_param_array(id, charp, NULL, 0444); 62 MODULE_PARM_DESC(id, "ID string for RME Digi96 soundcard."); 63 module_param_array(enable, bool, NULL, 0444); 64 MODULE_PARM_DESC(enable, "Enable RME Digi96 soundcard."); 65 66 /* 67 * Defines for RME Digi96 series, from internal RME reference documents 68 * dated 12.01.00 69 */ 70 71 #define RME96_SPDIF_NCHANNELS 2 72 73 /* Playback and capture buffer size */ 74 #define RME96_BUFFER_SIZE 0x10000 75 76 /* IO area size */ 77 #define RME96_IO_SIZE 0x60000 78 79 /* IO area offsets */ 80 #define RME96_IO_PLAY_BUFFER 0x0 81 #define RME96_IO_REC_BUFFER 0x10000 82 #define RME96_IO_CONTROL_REGISTER 0x20000 83 #define RME96_IO_ADDITIONAL_REG 0x20004 84 #define RME96_IO_CONFIRM_PLAY_IRQ 0x20008 85 #define RME96_IO_CONFIRM_REC_IRQ 0x2000C 86 #define RME96_IO_SET_PLAY_POS 0x40000 87 #define RME96_IO_RESET_PLAY_POS 0x4FFFC 88 #define RME96_IO_SET_REC_POS 0x50000 89 #define RME96_IO_RESET_REC_POS 0x5FFFC 90 #define RME96_IO_GET_PLAY_POS 0x20000 91 #define RME96_IO_GET_REC_POS 0x30000 92 93 /* Write control register bits */ 94 #define RME96_WCR_START (1 << 0) 95 #define RME96_WCR_START_2 (1 << 1) 96 #define RME96_WCR_GAIN_0 (1 << 2) 97 #define RME96_WCR_GAIN_1 (1 << 3) 98 #define RME96_WCR_MODE24 (1 << 4) 99 #define RME96_WCR_MODE24_2 (1 << 5) 100 #define RME96_WCR_BM (1 << 6) 101 #define RME96_WCR_BM_2 (1 << 7) 102 #define RME96_WCR_ADAT (1 << 8) 103 #define RME96_WCR_FREQ_0 (1 << 9) 104 #define RME96_WCR_FREQ_1 (1 << 10) 105 #define RME96_WCR_DS (1 << 11) 106 #define RME96_WCR_PRO (1 << 12) 107 #define RME96_WCR_EMP (1 << 13) 108 #define RME96_WCR_SEL (1 << 14) 109 #define RME96_WCR_MASTER (1 << 15) 110 #define RME96_WCR_PD (1 << 16) 111 #define RME96_WCR_INP_0 (1 << 17) 112 #define RME96_WCR_INP_1 (1 << 18) 113 #define RME96_WCR_THRU_0 (1 << 19) 114 #define RME96_WCR_THRU_1 (1 << 20) 115 #define RME96_WCR_THRU_2 (1 << 21) 116 #define RME96_WCR_THRU_3 (1 << 22) 117 #define RME96_WCR_THRU_4 (1 << 23) 118 #define RME96_WCR_THRU_5 (1 << 24) 119 #define RME96_WCR_THRU_6 (1 << 25) 120 #define RME96_WCR_THRU_7 (1 << 26) 121 #define RME96_WCR_DOLBY (1 << 27) 122 #define RME96_WCR_MONITOR_0 (1 << 28) 123 #define RME96_WCR_MONITOR_1 (1 << 29) 124 #define RME96_WCR_ISEL (1 << 30) 125 #define RME96_WCR_IDIS (1 << 31) 126 127 #define RME96_WCR_BITPOS_GAIN_0 2 128 #define RME96_WCR_BITPOS_GAIN_1 3 129 #define RME96_WCR_BITPOS_FREQ_0 9 130 #define RME96_WCR_BITPOS_FREQ_1 10 131 #define RME96_WCR_BITPOS_INP_0 17 132 #define RME96_WCR_BITPOS_INP_1 18 133 #define RME96_WCR_BITPOS_MONITOR_0 28 134 #define RME96_WCR_BITPOS_MONITOR_1 29 135 136 /* Read control register bits */ 137 #define RME96_RCR_AUDIO_ADDR_MASK 0xFFFF 138 #define RME96_RCR_IRQ_2 (1 << 16) 139 #define RME96_RCR_T_OUT (1 << 17) 140 #define RME96_RCR_DEV_ID_0 (1 << 21) 141 #define RME96_RCR_DEV_ID_1 (1 << 22) 142 #define RME96_RCR_LOCK (1 << 23) 143 #define RME96_RCR_VERF (1 << 26) 144 #define RME96_RCR_F0 (1 << 27) 145 #define RME96_RCR_F1 (1 << 28) 146 #define RME96_RCR_F2 (1 << 29) 147 #define RME96_RCR_AUTOSYNC (1 << 30) 148 #define RME96_RCR_IRQ (1 << 31) 149 150 #define RME96_RCR_BITPOS_F0 27 151 #define RME96_RCR_BITPOS_F1 28 152 #define RME96_RCR_BITPOS_F2 29 153 154 /* Additonal register bits */ 155 #define RME96_AR_WSEL (1 << 0) 156 #define RME96_AR_ANALOG (1 << 1) 157 #define RME96_AR_FREQPAD_0 (1 << 2) 158 #define RME96_AR_FREQPAD_1 (1 << 3) 159 #define RME96_AR_FREQPAD_2 (1 << 4) 160 #define RME96_AR_PD2 (1 << 5) 161 #define RME96_AR_DAC_EN (1 << 6) 162 #define RME96_AR_CLATCH (1 << 7) 163 #define RME96_AR_CCLK (1 << 8) 164 #define RME96_AR_CDATA (1 << 9) 165 166 #define RME96_AR_BITPOS_F0 2 167 #define RME96_AR_BITPOS_F1 3 168 #define RME96_AR_BITPOS_F2 4 169 170 /* Monitor tracks */ 171 #define RME96_MONITOR_TRACKS_1_2 0 172 #define RME96_MONITOR_TRACKS_3_4 1 173 #define RME96_MONITOR_TRACKS_5_6 2 174 #define RME96_MONITOR_TRACKS_7_8 3 175 176 /* Attenuation */ 177 #define RME96_ATTENUATION_0 0 178 #define RME96_ATTENUATION_6 1 179 #define RME96_ATTENUATION_12 2 180 #define RME96_ATTENUATION_18 3 181 182 /* Input types */ 183 #define RME96_INPUT_OPTICAL 0 184 #define RME96_INPUT_COAXIAL 1 185 #define RME96_INPUT_INTERNAL 2 186 #define RME96_INPUT_XLR 3 187 #define RME96_INPUT_ANALOG 4 188 189 /* Clock modes */ 190 #define RME96_CLOCKMODE_SLAVE 0 191 #define RME96_CLOCKMODE_MASTER 1 192 #define RME96_CLOCKMODE_WORDCLOCK 2 193 194 /* Block sizes in bytes */ 195 #define RME96_SMALL_BLOCK_SIZE 2048 196 #define RME96_LARGE_BLOCK_SIZE 8192 197 198 /* Volume control */ 199 #define RME96_AD1852_VOL_BITS 14 200 #define RME96_AD1855_VOL_BITS 10 201 202 203 struct rme96 { 204 spinlock_t lock; 205 int irq; 206 unsigned long port; 207 void __iomem *iobase; 208 209 u32 wcreg; /* cached write control register value */ 210 u32 wcreg_spdif; /* S/PDIF setup */ 211 u32 wcreg_spdif_stream; /* S/PDIF setup (temporary) */ 212 u32 rcreg; /* cached read control register value */ 213 u32 areg; /* cached additional register value */ 214 u16 vol[2]; /* cached volume of analog output */ 215 216 u8 rev; /* card revision number */ 217 218 struct snd_pcm_substream *playback_substream; 219 struct snd_pcm_substream *capture_substream; 220 221 int playback_frlog; /* log2 of framesize */ 222 int capture_frlog; 223 224 size_t playback_periodsize; /* in bytes, zero if not used */ 225 size_t capture_periodsize; /* in bytes, zero if not used */ 226 227 struct snd_card *card; 228 struct snd_pcm *spdif_pcm; 229 struct snd_pcm *adat_pcm; 230 struct pci_dev *pci; 231 struct snd_kcontrol *spdif_ctl; 232 }; 233 234 static struct pci_device_id snd_rme96_ids[] = { 235 { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96), 0, }, 236 { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96_8), 0, }, 237 { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96_8_PRO), 0, }, 238 { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST), 0, }, 239 { 0, } 240 }; 241 242 MODULE_DEVICE_TABLE(pci, snd_rme96_ids); 243 244 #define RME96_ISPLAYING(rme96) ((rme96)->wcreg & RME96_WCR_START) 245 #define RME96_ISRECORDING(rme96) ((rme96)->wcreg & RME96_WCR_START_2) 246 #define RME96_HAS_ANALOG_IN(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST) 247 #define RME96_HAS_ANALOG_OUT(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PRO || \ 248 (rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST) 249 #define RME96_DAC_IS_1852(rme96) (RME96_HAS_ANALOG_OUT(rme96) && (rme96)->rev >= 4) 250 #define RME96_DAC_IS_1855(rme96) (((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && (rme96)->rev < 4) || \ 251 ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PRO && (rme96)->rev == 2)) 252 #define RME96_185X_MAX_OUT(rme96) ((1 << (RME96_DAC_IS_1852(rme96) ? RME96_AD1852_VOL_BITS : RME96_AD1855_VOL_BITS)) - 1) 253 254 static int 255 snd_rme96_playback_prepare(struct snd_pcm_substream *substream); 256 257 static int 258 snd_rme96_capture_prepare(struct snd_pcm_substream *substream); 259 260 static int 261 snd_rme96_playback_trigger(struct snd_pcm_substream *substream, 262 int cmd); 263 264 static int 265 snd_rme96_capture_trigger(struct snd_pcm_substream *substream, 266 int cmd); 267 268 static snd_pcm_uframes_t 269 snd_rme96_playback_pointer(struct snd_pcm_substream *substream); 270 271 static snd_pcm_uframes_t 272 snd_rme96_capture_pointer(struct snd_pcm_substream *substream); 273 274 static void __devinit 275 snd_rme96_proc_init(struct rme96 *rme96); 276 277 static int 278 snd_rme96_create_switches(struct snd_card *card, 279 struct rme96 *rme96); 280 281 static int 282 snd_rme96_getinputtype(struct rme96 *rme96); 283 284 static inline unsigned int 285 snd_rme96_playback_ptr(struct rme96 *rme96) 286 { 287 return (readl(rme96->iobase + RME96_IO_GET_PLAY_POS) 288 & RME96_RCR_AUDIO_ADDR_MASK) >> rme96->playback_frlog; 289 } 290 291 static inline unsigned int 292 snd_rme96_capture_ptr(struct rme96 *rme96) 293 { 294 return (readl(rme96->iobase + RME96_IO_GET_REC_POS) 295 & RME96_RCR_AUDIO_ADDR_MASK) >> rme96->capture_frlog; 296 } 297 298 static int 299 snd_rme96_playback_silence(struct snd_pcm_substream *substream, 300 int channel, /* not used (interleaved data) */ 301 snd_pcm_uframes_t pos, 302 snd_pcm_uframes_t count) 303 { 304 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 305 count <<= rme96->playback_frlog; 306 pos <<= rme96->playback_frlog; 307 memset_io(rme96->iobase + RME96_IO_PLAY_BUFFER + pos, 308 0, count); 309 return 0; 310 } 311 312 static int 313 snd_rme96_playback_copy(struct snd_pcm_substream *substream, 314 int channel, /* not used (interleaved data) */ 315 snd_pcm_uframes_t pos, 316 void __user *src, 317 snd_pcm_uframes_t count) 318 { 319 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 320 count <<= rme96->playback_frlog; 321 pos <<= rme96->playback_frlog; 322 copy_from_user_toio(rme96->iobase + RME96_IO_PLAY_BUFFER + pos, src, 323 count); 324 return 0; 325 } 326 327 static int 328 snd_rme96_capture_copy(struct snd_pcm_substream *substream, 329 int channel, /* not used (interleaved data) */ 330 snd_pcm_uframes_t pos, 331 void __user *dst, 332 snd_pcm_uframes_t count) 333 { 334 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 335 count <<= rme96->capture_frlog; 336 pos <<= rme96->capture_frlog; 337 copy_to_user_fromio(dst, rme96->iobase + RME96_IO_REC_BUFFER + pos, 338 count); 339 return 0; 340 } 341 342 /* 343 * Digital output capabilities (S/PDIF) 344 */ 345 static struct snd_pcm_hardware snd_rme96_playback_spdif_info = 346 { 347 .info = (SNDRV_PCM_INFO_MMAP_IOMEM | 348 SNDRV_PCM_INFO_MMAP_VALID | 349 SNDRV_PCM_INFO_INTERLEAVED | 350 SNDRV_PCM_INFO_PAUSE), 351 .formats = (SNDRV_PCM_FMTBIT_S16_LE | 352 SNDRV_PCM_FMTBIT_S32_LE), 353 .rates = (SNDRV_PCM_RATE_32000 | 354 SNDRV_PCM_RATE_44100 | 355 SNDRV_PCM_RATE_48000 | 356 SNDRV_PCM_RATE_64000 | 357 SNDRV_PCM_RATE_88200 | 358 SNDRV_PCM_RATE_96000), 359 .rate_min = 32000, 360 .rate_max = 96000, 361 .channels_min = 2, 362 .channels_max = 2, 363 .buffer_bytes_max = RME96_BUFFER_SIZE, 364 .period_bytes_min = RME96_SMALL_BLOCK_SIZE, 365 .period_bytes_max = RME96_LARGE_BLOCK_SIZE, 366 .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE, 367 .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE, 368 .fifo_size = 0, 369 }; 370 371 /* 372 * Digital input capabilities (S/PDIF) 373 */ 374 static struct snd_pcm_hardware snd_rme96_capture_spdif_info = 375 { 376 .info = (SNDRV_PCM_INFO_MMAP_IOMEM | 377 SNDRV_PCM_INFO_MMAP_VALID | 378 SNDRV_PCM_INFO_INTERLEAVED | 379 SNDRV_PCM_INFO_PAUSE), 380 .formats = (SNDRV_PCM_FMTBIT_S16_LE | 381 SNDRV_PCM_FMTBIT_S32_LE), 382 .rates = (SNDRV_PCM_RATE_32000 | 383 SNDRV_PCM_RATE_44100 | 384 SNDRV_PCM_RATE_48000 | 385 SNDRV_PCM_RATE_64000 | 386 SNDRV_PCM_RATE_88200 | 387 SNDRV_PCM_RATE_96000), 388 .rate_min = 32000, 389 .rate_max = 96000, 390 .channels_min = 2, 391 .channels_max = 2, 392 .buffer_bytes_max = RME96_BUFFER_SIZE, 393 .period_bytes_min = RME96_SMALL_BLOCK_SIZE, 394 .period_bytes_max = RME96_LARGE_BLOCK_SIZE, 395 .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE, 396 .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE, 397 .fifo_size = 0, 398 }; 399 400 /* 401 * Digital output capabilities (ADAT) 402 */ 403 static struct snd_pcm_hardware snd_rme96_playback_adat_info = 404 { 405 .info = (SNDRV_PCM_INFO_MMAP_IOMEM | 406 SNDRV_PCM_INFO_MMAP_VALID | 407 SNDRV_PCM_INFO_INTERLEAVED | 408 SNDRV_PCM_INFO_PAUSE), 409 .formats = (SNDRV_PCM_FMTBIT_S16_LE | 410 SNDRV_PCM_FMTBIT_S32_LE), 411 .rates = (SNDRV_PCM_RATE_44100 | 412 SNDRV_PCM_RATE_48000), 413 .rate_min = 44100, 414 .rate_max = 48000, 415 .channels_min = 8, 416 .channels_max = 8, 417 .buffer_bytes_max = RME96_BUFFER_SIZE, 418 .period_bytes_min = RME96_SMALL_BLOCK_SIZE, 419 .period_bytes_max = RME96_LARGE_BLOCK_SIZE, 420 .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE, 421 .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE, 422 .fifo_size = 0, 423 }; 424 425 /* 426 * Digital input capabilities (ADAT) 427 */ 428 static struct snd_pcm_hardware snd_rme96_capture_adat_info = 429 { 430 .info = (SNDRV_PCM_INFO_MMAP_IOMEM | 431 SNDRV_PCM_INFO_MMAP_VALID | 432 SNDRV_PCM_INFO_INTERLEAVED | 433 SNDRV_PCM_INFO_PAUSE), 434 .formats = (SNDRV_PCM_FMTBIT_S16_LE | 435 SNDRV_PCM_FMTBIT_S32_LE), 436 .rates = (SNDRV_PCM_RATE_44100 | 437 SNDRV_PCM_RATE_48000), 438 .rate_min = 44100, 439 .rate_max = 48000, 440 .channels_min = 8, 441 .channels_max = 8, 442 .buffer_bytes_max = RME96_BUFFER_SIZE, 443 .period_bytes_min = RME96_SMALL_BLOCK_SIZE, 444 .period_bytes_max = RME96_LARGE_BLOCK_SIZE, 445 .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE, 446 .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE, 447 .fifo_size = 0, 448 }; 449 450 /* 451 * The CDATA, CCLK and CLATCH bits can be used to write to the SPI interface 452 * of the AD1852 or AD1852 D/A converter on the board. CDATA must be set up 453 * on the falling edge of CCLK and be stable on the rising edge. The rising 454 * edge of CLATCH after the last data bit clocks in the whole data word. 455 * A fast processor could probably drive the SPI interface faster than the 456 * DAC can handle (3MHz for the 1855, unknown for the 1852). The udelay(1) 457 * limits the data rate to 500KHz and only causes a delay of 33 microsecs. 458 * 459 * NOTE: increased delay from 1 to 10, since there where problems setting 460 * the volume. 461 */ 462 static void 463 snd_rme96_write_SPI(struct rme96 *rme96, u16 val) 464 { 465 int i; 466 467 for (i = 0; i < 16; i++) { 468 if (val & 0x8000) { 469 rme96->areg |= RME96_AR_CDATA; 470 } else { 471 rme96->areg &= ~RME96_AR_CDATA; 472 } 473 rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CLATCH); 474 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 475 udelay(10); 476 rme96->areg |= RME96_AR_CCLK; 477 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 478 udelay(10); 479 val <<= 1; 480 } 481 rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CDATA); 482 rme96->areg |= RME96_AR_CLATCH; 483 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 484 udelay(10); 485 rme96->areg &= ~RME96_AR_CLATCH; 486 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 487 } 488 489 static void 490 snd_rme96_apply_dac_volume(struct rme96 *rme96) 491 { 492 if (RME96_DAC_IS_1852(rme96)) { 493 snd_rme96_write_SPI(rme96, (rme96->vol[0] << 2) | 0x0); 494 snd_rme96_write_SPI(rme96, (rme96->vol[1] << 2) | 0x2); 495 } else if (RME96_DAC_IS_1855(rme96)) { 496 snd_rme96_write_SPI(rme96, (rme96->vol[0] & 0x3FF) | 0x000); 497 snd_rme96_write_SPI(rme96, (rme96->vol[1] & 0x3FF) | 0x400); 498 } 499 } 500 501 static void 502 snd_rme96_reset_dac(struct rme96 *rme96) 503 { 504 writel(rme96->wcreg | RME96_WCR_PD, 505 rme96->iobase + RME96_IO_CONTROL_REGISTER); 506 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 507 } 508 509 static int 510 snd_rme96_getmontracks(struct rme96 *rme96) 511 { 512 return ((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_0) & 1) + 513 (((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_1) & 1) << 1); 514 } 515 516 static int 517 snd_rme96_setmontracks(struct rme96 *rme96, 518 int montracks) 519 { 520 if (montracks & 1) { 521 rme96->wcreg |= RME96_WCR_MONITOR_0; 522 } else { 523 rme96->wcreg &= ~RME96_WCR_MONITOR_0; 524 } 525 if (montracks & 2) { 526 rme96->wcreg |= RME96_WCR_MONITOR_1; 527 } else { 528 rme96->wcreg &= ~RME96_WCR_MONITOR_1; 529 } 530 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 531 return 0; 532 } 533 534 static int 535 snd_rme96_getattenuation(struct rme96 *rme96) 536 { 537 return ((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_0) & 1) + 538 (((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_1) & 1) << 1); 539 } 540 541 static int 542 snd_rme96_setattenuation(struct rme96 *rme96, 543 int attenuation) 544 { 545 switch (attenuation) { 546 case 0: 547 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) & 548 ~RME96_WCR_GAIN_1; 549 break; 550 case 1: 551 rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) & 552 ~RME96_WCR_GAIN_1; 553 break; 554 case 2: 555 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) | 556 RME96_WCR_GAIN_1; 557 break; 558 case 3: 559 rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) | 560 RME96_WCR_GAIN_1; 561 break; 562 default: 563 return -EINVAL; 564 } 565 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 566 return 0; 567 } 568 569 static int 570 snd_rme96_capture_getrate(struct rme96 *rme96, 571 int *is_adat) 572 { 573 int n, rate; 574 575 *is_adat = 0; 576 if (rme96->areg & RME96_AR_ANALOG) { 577 /* Analog input, overrides S/PDIF setting */ 578 n = ((rme96->areg >> RME96_AR_BITPOS_F0) & 1) + 579 (((rme96->areg >> RME96_AR_BITPOS_F1) & 1) << 1); 580 switch (n) { 581 case 1: 582 rate = 32000; 583 break; 584 case 2: 585 rate = 44100; 586 break; 587 case 3: 588 rate = 48000; 589 break; 590 default: 591 return -1; 592 } 593 return (rme96->areg & RME96_AR_BITPOS_F2) ? rate << 1 : rate; 594 } 595 596 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER); 597 if (rme96->rcreg & RME96_RCR_LOCK) { 598 /* ADAT rate */ 599 *is_adat = 1; 600 if (rme96->rcreg & RME96_RCR_T_OUT) { 601 return 48000; 602 } 603 return 44100; 604 } 605 606 if (rme96->rcreg & RME96_RCR_VERF) { 607 return -1; 608 } 609 610 /* S/PDIF rate */ 611 n = ((rme96->rcreg >> RME96_RCR_BITPOS_F0) & 1) + 612 (((rme96->rcreg >> RME96_RCR_BITPOS_F1) & 1) << 1) + 613 (((rme96->rcreg >> RME96_RCR_BITPOS_F2) & 1) << 2); 614 615 switch (n) { 616 case 0: 617 if (rme96->rcreg & RME96_RCR_T_OUT) { 618 return 64000; 619 } 620 return -1; 621 case 3: return 96000; 622 case 4: return 88200; 623 case 5: return 48000; 624 case 6: return 44100; 625 case 7: return 32000; 626 default: 627 break; 628 } 629 return -1; 630 } 631 632 static int 633 snd_rme96_playback_getrate(struct rme96 *rme96) 634 { 635 int rate, dummy; 636 637 if (!(rme96->wcreg & RME96_WCR_MASTER) && 638 snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG && 639 (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0) 640 { 641 /* slave clock */ 642 return rate; 643 } 644 rate = ((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_0) & 1) + 645 (((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_1) & 1) << 1); 646 switch (rate) { 647 case 1: 648 rate = 32000; 649 break; 650 case 2: 651 rate = 44100; 652 break; 653 case 3: 654 rate = 48000; 655 break; 656 default: 657 return -1; 658 } 659 return (rme96->wcreg & RME96_WCR_DS) ? rate << 1 : rate; 660 } 661 662 static int 663 snd_rme96_playback_setrate(struct rme96 *rme96, 664 int rate) 665 { 666 int ds; 667 668 ds = rme96->wcreg & RME96_WCR_DS; 669 switch (rate) { 670 case 32000: 671 rme96->wcreg &= ~RME96_WCR_DS; 672 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) & 673 ~RME96_WCR_FREQ_1; 674 break; 675 case 44100: 676 rme96->wcreg &= ~RME96_WCR_DS; 677 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) & 678 ~RME96_WCR_FREQ_0; 679 break; 680 case 48000: 681 rme96->wcreg &= ~RME96_WCR_DS; 682 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) | 683 RME96_WCR_FREQ_1; 684 break; 685 case 64000: 686 rme96->wcreg |= RME96_WCR_DS; 687 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) & 688 ~RME96_WCR_FREQ_1; 689 break; 690 case 88200: 691 rme96->wcreg |= RME96_WCR_DS; 692 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) & 693 ~RME96_WCR_FREQ_0; 694 break; 695 case 96000: 696 rme96->wcreg |= RME96_WCR_DS; 697 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) | 698 RME96_WCR_FREQ_1; 699 break; 700 default: 701 return -EINVAL; 702 } 703 if ((!ds && rme96->wcreg & RME96_WCR_DS) || 704 (ds && !(rme96->wcreg & RME96_WCR_DS))) 705 { 706 /* change to/from double-speed: reset the DAC (if available) */ 707 snd_rme96_reset_dac(rme96); 708 } else { 709 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 710 } 711 return 0; 712 } 713 714 static int 715 snd_rme96_capture_analog_setrate(struct rme96 *rme96, 716 int rate) 717 { 718 switch (rate) { 719 case 32000: 720 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) & 721 ~RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2; 722 break; 723 case 44100: 724 rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) | 725 RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2; 726 break; 727 case 48000: 728 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) | 729 RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2; 730 break; 731 case 64000: 732 if (rme96->rev < 4) { 733 return -EINVAL; 734 } 735 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) & 736 ~RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2; 737 break; 738 case 88200: 739 if (rme96->rev < 4) { 740 return -EINVAL; 741 } 742 rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) | 743 RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2; 744 break; 745 case 96000: 746 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) | 747 RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2; 748 break; 749 default: 750 return -EINVAL; 751 } 752 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 753 return 0; 754 } 755 756 static int 757 snd_rme96_setclockmode(struct rme96 *rme96, 758 int mode) 759 { 760 switch (mode) { 761 case RME96_CLOCKMODE_SLAVE: 762 /* AutoSync */ 763 rme96->wcreg &= ~RME96_WCR_MASTER; 764 rme96->areg &= ~RME96_AR_WSEL; 765 break; 766 case RME96_CLOCKMODE_MASTER: 767 /* Internal */ 768 rme96->wcreg |= RME96_WCR_MASTER; 769 rme96->areg &= ~RME96_AR_WSEL; 770 break; 771 case RME96_CLOCKMODE_WORDCLOCK: 772 /* Word clock is a master mode */ 773 rme96->wcreg |= RME96_WCR_MASTER; 774 rme96->areg |= RME96_AR_WSEL; 775 break; 776 default: 777 return -EINVAL; 778 } 779 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 780 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 781 return 0; 782 } 783 784 static int 785 snd_rme96_getclockmode(struct rme96 *rme96) 786 { 787 if (rme96->areg & RME96_AR_WSEL) { 788 return RME96_CLOCKMODE_WORDCLOCK; 789 } 790 return (rme96->wcreg & RME96_WCR_MASTER) ? RME96_CLOCKMODE_MASTER : 791 RME96_CLOCKMODE_SLAVE; 792 } 793 794 static int 795 snd_rme96_setinputtype(struct rme96 *rme96, 796 int type) 797 { 798 int n; 799 800 switch (type) { 801 case RME96_INPUT_OPTICAL: 802 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) & 803 ~RME96_WCR_INP_1; 804 break; 805 case RME96_INPUT_COAXIAL: 806 rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) & 807 ~RME96_WCR_INP_1; 808 break; 809 case RME96_INPUT_INTERNAL: 810 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) | 811 RME96_WCR_INP_1; 812 break; 813 case RME96_INPUT_XLR: 814 if ((rme96->pci->device != PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && 815 rme96->pci->device != PCI_DEVICE_ID_RME_DIGI96_8_PRO) || 816 (rme96->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && 817 rme96->rev > 4)) 818 { 819 /* Only Digi96/8 PRO and Digi96/8 PAD supports XLR */ 820 return -EINVAL; 821 } 822 rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) | 823 RME96_WCR_INP_1; 824 break; 825 case RME96_INPUT_ANALOG: 826 if (!RME96_HAS_ANALOG_IN(rme96)) { 827 return -EINVAL; 828 } 829 rme96->areg |= RME96_AR_ANALOG; 830 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 831 if (rme96->rev < 4) { 832 /* 833 * Revision less than 004 does not support 64 and 834 * 88.2 kHz 835 */ 836 if (snd_rme96_capture_getrate(rme96, &n) == 88200) { 837 snd_rme96_capture_analog_setrate(rme96, 44100); 838 } 839 if (snd_rme96_capture_getrate(rme96, &n) == 64000) { 840 snd_rme96_capture_analog_setrate(rme96, 32000); 841 } 842 } 843 return 0; 844 default: 845 return -EINVAL; 846 } 847 if (type != RME96_INPUT_ANALOG && RME96_HAS_ANALOG_IN(rme96)) { 848 rme96->areg &= ~RME96_AR_ANALOG; 849 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 850 } 851 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 852 return 0; 853 } 854 855 static int 856 snd_rme96_getinputtype(struct rme96 *rme96) 857 { 858 if (rme96->areg & RME96_AR_ANALOG) { 859 return RME96_INPUT_ANALOG; 860 } 861 return ((rme96->wcreg >> RME96_WCR_BITPOS_INP_0) & 1) + 862 (((rme96->wcreg >> RME96_WCR_BITPOS_INP_1) & 1) << 1); 863 } 864 865 static void 866 snd_rme96_setframelog(struct rme96 *rme96, 867 int n_channels, 868 int is_playback) 869 { 870 int frlog; 871 872 if (n_channels == 2) { 873 frlog = 1; 874 } else { 875 /* assume 8 channels */ 876 frlog = 3; 877 } 878 if (is_playback) { 879 frlog += (rme96->wcreg & RME96_WCR_MODE24) ? 2 : 1; 880 rme96->playback_frlog = frlog; 881 } else { 882 frlog += (rme96->wcreg & RME96_WCR_MODE24_2) ? 2 : 1; 883 rme96->capture_frlog = frlog; 884 } 885 } 886 887 static int 888 snd_rme96_playback_setformat(struct rme96 *rme96, 889 int format) 890 { 891 switch (format) { 892 case SNDRV_PCM_FORMAT_S16_LE: 893 rme96->wcreg &= ~RME96_WCR_MODE24; 894 break; 895 case SNDRV_PCM_FORMAT_S32_LE: 896 rme96->wcreg |= RME96_WCR_MODE24; 897 break; 898 default: 899 return -EINVAL; 900 } 901 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 902 return 0; 903 } 904 905 static int 906 snd_rme96_capture_setformat(struct rme96 *rme96, 907 int format) 908 { 909 switch (format) { 910 case SNDRV_PCM_FORMAT_S16_LE: 911 rme96->wcreg &= ~RME96_WCR_MODE24_2; 912 break; 913 case SNDRV_PCM_FORMAT_S32_LE: 914 rme96->wcreg |= RME96_WCR_MODE24_2; 915 break; 916 default: 917 return -EINVAL; 918 } 919 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 920 return 0; 921 } 922 923 static void 924 snd_rme96_set_period_properties(struct rme96 *rme96, 925 size_t period_bytes) 926 { 927 switch (period_bytes) { 928 case RME96_LARGE_BLOCK_SIZE: 929 rme96->wcreg &= ~RME96_WCR_ISEL; 930 break; 931 case RME96_SMALL_BLOCK_SIZE: 932 rme96->wcreg |= RME96_WCR_ISEL; 933 break; 934 default: 935 snd_BUG(); 936 break; 937 } 938 rme96->wcreg &= ~RME96_WCR_IDIS; 939 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 940 } 941 942 static int 943 snd_rme96_playback_hw_params(struct snd_pcm_substream *substream, 944 struct snd_pcm_hw_params *params) 945 { 946 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 947 struct snd_pcm_runtime *runtime = substream->runtime; 948 int err, rate, dummy; 949 950 runtime->dma_area = (void __force *)(rme96->iobase + 951 RME96_IO_PLAY_BUFFER); 952 runtime->dma_addr = rme96->port + RME96_IO_PLAY_BUFFER; 953 runtime->dma_bytes = RME96_BUFFER_SIZE; 954 955 spin_lock_irq(&rme96->lock); 956 if (!(rme96->wcreg & RME96_WCR_MASTER) && 957 snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG && 958 (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0) 959 { 960 /* slave clock */ 961 if ((int)params_rate(params) != rate) { 962 spin_unlock_irq(&rme96->lock); 963 return -EIO; 964 } 965 } else if ((err = snd_rme96_playback_setrate(rme96, params_rate(params))) < 0) { 966 spin_unlock_irq(&rme96->lock); 967 return err; 968 } 969 if ((err = snd_rme96_playback_setformat(rme96, params_format(params))) < 0) { 970 spin_unlock_irq(&rme96->lock); 971 return err; 972 } 973 snd_rme96_setframelog(rme96, params_channels(params), 1); 974 if (rme96->capture_periodsize != 0) { 975 if (params_period_size(params) << rme96->playback_frlog != 976 rme96->capture_periodsize) 977 { 978 spin_unlock_irq(&rme96->lock); 979 return -EBUSY; 980 } 981 } 982 rme96->playback_periodsize = 983 params_period_size(params) << rme96->playback_frlog; 984 snd_rme96_set_period_properties(rme96, rme96->playback_periodsize); 985 /* S/PDIF setup */ 986 if ((rme96->wcreg & RME96_WCR_ADAT) == 0) { 987 rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP); 988 writel(rme96->wcreg |= rme96->wcreg_spdif_stream, rme96->iobase + RME96_IO_CONTROL_REGISTER); 989 } 990 spin_unlock_irq(&rme96->lock); 991 992 return 0; 993 } 994 995 static int 996 snd_rme96_capture_hw_params(struct snd_pcm_substream *substream, 997 struct snd_pcm_hw_params *params) 998 { 999 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 1000 struct snd_pcm_runtime *runtime = substream->runtime; 1001 int err, isadat, rate; 1002 1003 runtime->dma_area = (void __force *)(rme96->iobase + 1004 RME96_IO_REC_BUFFER); 1005 runtime->dma_addr = rme96->port + RME96_IO_REC_BUFFER; 1006 runtime->dma_bytes = RME96_BUFFER_SIZE; 1007 1008 spin_lock_irq(&rme96->lock); 1009 if ((err = snd_rme96_capture_setformat(rme96, params_format(params))) < 0) { 1010 spin_unlock_irq(&rme96->lock); 1011 return err; 1012 } 1013 if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) { 1014 if ((err = snd_rme96_capture_analog_setrate(rme96, 1015 params_rate(params))) < 0) 1016 { 1017 spin_unlock_irq(&rme96->lock); 1018 return err; 1019 } 1020 } else if ((rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0) { 1021 if ((int)params_rate(params) != rate) { 1022 spin_unlock_irq(&rme96->lock); 1023 return -EIO; 1024 } 1025 if ((isadat && runtime->hw.channels_min == 2) || 1026 (!isadat && runtime->hw.channels_min == 8)) 1027 { 1028 spin_unlock_irq(&rme96->lock); 1029 return -EIO; 1030 } 1031 } 1032 snd_rme96_setframelog(rme96, params_channels(params), 0); 1033 if (rme96->playback_periodsize != 0) { 1034 if (params_period_size(params) << rme96->capture_frlog != 1035 rme96->playback_periodsize) 1036 { 1037 spin_unlock_irq(&rme96->lock); 1038 return -EBUSY; 1039 } 1040 } 1041 rme96->capture_periodsize = 1042 params_period_size(params) << rme96->capture_frlog; 1043 snd_rme96_set_period_properties(rme96, rme96->capture_periodsize); 1044 spin_unlock_irq(&rme96->lock); 1045 1046 return 0; 1047 } 1048 1049 static void 1050 snd_rme96_playback_start(struct rme96 *rme96, 1051 int from_pause) 1052 { 1053 if (!from_pause) { 1054 writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS); 1055 } 1056 1057 rme96->wcreg |= RME96_WCR_START; 1058 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 1059 } 1060 1061 static void 1062 snd_rme96_capture_start(struct rme96 *rme96, 1063 int from_pause) 1064 { 1065 if (!from_pause) { 1066 writel(0, rme96->iobase + RME96_IO_RESET_REC_POS); 1067 } 1068 1069 rme96->wcreg |= RME96_WCR_START_2; 1070 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 1071 } 1072 1073 static void 1074 snd_rme96_playback_stop(struct rme96 *rme96) 1075 { 1076 /* 1077 * Check if there is an unconfirmed IRQ, if so confirm it, or else 1078 * the hardware will not stop generating interrupts 1079 */ 1080 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER); 1081 if (rme96->rcreg & RME96_RCR_IRQ) { 1082 writel(0, rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ); 1083 } 1084 rme96->wcreg &= ~RME96_WCR_START; 1085 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 1086 } 1087 1088 static void 1089 snd_rme96_capture_stop(struct rme96 *rme96) 1090 { 1091 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER); 1092 if (rme96->rcreg & RME96_RCR_IRQ_2) { 1093 writel(0, rme96->iobase + RME96_IO_CONFIRM_REC_IRQ); 1094 } 1095 rme96->wcreg &= ~RME96_WCR_START_2; 1096 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 1097 } 1098 1099 static irqreturn_t 1100 snd_rme96_interrupt(int irq, 1101 void *dev_id) 1102 { 1103 struct rme96 *rme96 = (struct rme96 *)dev_id; 1104 1105 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER); 1106 /* fastpath out, to ease interrupt sharing */ 1107 if (!((rme96->rcreg & RME96_RCR_IRQ) || 1108 (rme96->rcreg & RME96_RCR_IRQ_2))) 1109 { 1110 return IRQ_NONE; 1111 } 1112 1113 if (rme96->rcreg & RME96_RCR_IRQ) { 1114 /* playback */ 1115 snd_pcm_period_elapsed(rme96->playback_substream); 1116 writel(0, rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ); 1117 } 1118 if (rme96->rcreg & RME96_RCR_IRQ_2) { 1119 /* capture */ 1120 snd_pcm_period_elapsed(rme96->capture_substream); 1121 writel(0, rme96->iobase + RME96_IO_CONFIRM_REC_IRQ); 1122 } 1123 return IRQ_HANDLED; 1124 } 1125 1126 static unsigned int period_bytes[] = { RME96_SMALL_BLOCK_SIZE, RME96_LARGE_BLOCK_SIZE }; 1127 1128 static struct snd_pcm_hw_constraint_list hw_constraints_period_bytes = { 1129 .count = ARRAY_SIZE(period_bytes), 1130 .list = period_bytes, 1131 .mask = 0 1132 }; 1133 1134 static void 1135 rme96_set_buffer_size_constraint(struct rme96 *rme96, 1136 struct snd_pcm_runtime *runtime) 1137 { 1138 unsigned int size; 1139 1140 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 1141 RME96_BUFFER_SIZE, RME96_BUFFER_SIZE); 1142 if ((size = rme96->playback_periodsize) != 0 || 1143 (size = rme96->capture_periodsize) != 0) 1144 snd_pcm_hw_constraint_minmax(runtime, 1145 SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 1146 size, size); 1147 else 1148 snd_pcm_hw_constraint_list(runtime, 0, 1149 SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 1150 &hw_constraints_period_bytes); 1151 } 1152 1153 static int 1154 snd_rme96_playback_spdif_open(struct snd_pcm_substream *substream) 1155 { 1156 int rate, dummy; 1157 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 1158 struct snd_pcm_runtime *runtime = substream->runtime; 1159 1160 spin_lock_irq(&rme96->lock); 1161 if (rme96->playback_substream != NULL) { 1162 spin_unlock_irq(&rme96->lock); 1163 return -EBUSY; 1164 } 1165 rme96->wcreg &= ~RME96_WCR_ADAT; 1166 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 1167 rme96->playback_substream = substream; 1168 spin_unlock_irq(&rme96->lock); 1169 1170 runtime->hw = snd_rme96_playback_spdif_info; 1171 if (!(rme96->wcreg & RME96_WCR_MASTER) && 1172 snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG && 1173 (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0) 1174 { 1175 /* slave clock */ 1176 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate); 1177 runtime->hw.rate_min = rate; 1178 runtime->hw.rate_max = rate; 1179 } 1180 rme96_set_buffer_size_constraint(rme96, runtime); 1181 1182 rme96->wcreg_spdif_stream = rme96->wcreg_spdif; 1183 rme96->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE; 1184 snd_ctl_notify(rme96->card, SNDRV_CTL_EVENT_MASK_VALUE | 1185 SNDRV_CTL_EVENT_MASK_INFO, &rme96->spdif_ctl->id); 1186 return 0; 1187 } 1188 1189 static int 1190 snd_rme96_capture_spdif_open(struct snd_pcm_substream *substream) 1191 { 1192 int isadat, rate; 1193 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 1194 struct snd_pcm_runtime *runtime = substream->runtime; 1195 1196 runtime->hw = snd_rme96_capture_spdif_info; 1197 if (snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG && 1198 (rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0) 1199 { 1200 if (isadat) { 1201 return -EIO; 1202 } 1203 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate); 1204 runtime->hw.rate_min = rate; 1205 runtime->hw.rate_max = rate; 1206 } 1207 1208 spin_lock_irq(&rme96->lock); 1209 if (rme96->capture_substream != NULL) { 1210 spin_unlock_irq(&rme96->lock); 1211 return -EBUSY; 1212 } 1213 rme96->capture_substream = substream; 1214 spin_unlock_irq(&rme96->lock); 1215 1216 rme96_set_buffer_size_constraint(rme96, runtime); 1217 return 0; 1218 } 1219 1220 static int 1221 snd_rme96_playback_adat_open(struct snd_pcm_substream *substream) 1222 { 1223 int rate, dummy; 1224 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 1225 struct snd_pcm_runtime *runtime = substream->runtime; 1226 1227 spin_lock_irq(&rme96->lock); 1228 if (rme96->playback_substream != NULL) { 1229 spin_unlock_irq(&rme96->lock); 1230 return -EBUSY; 1231 } 1232 rme96->wcreg |= RME96_WCR_ADAT; 1233 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 1234 rme96->playback_substream = substream; 1235 spin_unlock_irq(&rme96->lock); 1236 1237 runtime->hw = snd_rme96_playback_adat_info; 1238 if (!(rme96->wcreg & RME96_WCR_MASTER) && 1239 snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG && 1240 (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0) 1241 { 1242 /* slave clock */ 1243 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate); 1244 runtime->hw.rate_min = rate; 1245 runtime->hw.rate_max = rate; 1246 } 1247 rme96_set_buffer_size_constraint(rme96, runtime); 1248 return 0; 1249 } 1250 1251 static int 1252 snd_rme96_capture_adat_open(struct snd_pcm_substream *substream) 1253 { 1254 int isadat, rate; 1255 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 1256 struct snd_pcm_runtime *runtime = substream->runtime; 1257 1258 runtime->hw = snd_rme96_capture_adat_info; 1259 if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) { 1260 /* makes no sense to use analog input. Note that analog 1261 expension cards AEB4/8-I are RME96_INPUT_INTERNAL */ 1262 return -EIO; 1263 } 1264 if ((rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0) { 1265 if (!isadat) { 1266 return -EIO; 1267 } 1268 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate); 1269 runtime->hw.rate_min = rate; 1270 runtime->hw.rate_max = rate; 1271 } 1272 1273 spin_lock_irq(&rme96->lock); 1274 if (rme96->capture_substream != NULL) { 1275 spin_unlock_irq(&rme96->lock); 1276 return -EBUSY; 1277 } 1278 rme96->capture_substream = substream; 1279 spin_unlock_irq(&rme96->lock); 1280 1281 rme96_set_buffer_size_constraint(rme96, runtime); 1282 return 0; 1283 } 1284 1285 static int 1286 snd_rme96_playback_close(struct snd_pcm_substream *substream) 1287 { 1288 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 1289 int spdif = 0; 1290 1291 spin_lock_irq(&rme96->lock); 1292 if (RME96_ISPLAYING(rme96)) { 1293 snd_rme96_playback_stop(rme96); 1294 } 1295 rme96->playback_substream = NULL; 1296 rme96->playback_periodsize = 0; 1297 spdif = (rme96->wcreg & RME96_WCR_ADAT) == 0; 1298 spin_unlock_irq(&rme96->lock); 1299 if (spdif) { 1300 rme96->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE; 1301 snd_ctl_notify(rme96->card, SNDRV_CTL_EVENT_MASK_VALUE | 1302 SNDRV_CTL_EVENT_MASK_INFO, &rme96->spdif_ctl->id); 1303 } 1304 return 0; 1305 } 1306 1307 static int 1308 snd_rme96_capture_close(struct snd_pcm_substream *substream) 1309 { 1310 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 1311 1312 spin_lock_irq(&rme96->lock); 1313 if (RME96_ISRECORDING(rme96)) { 1314 snd_rme96_capture_stop(rme96); 1315 } 1316 rme96->capture_substream = NULL; 1317 rme96->capture_periodsize = 0; 1318 spin_unlock_irq(&rme96->lock); 1319 return 0; 1320 } 1321 1322 static int 1323 snd_rme96_playback_prepare(struct snd_pcm_substream *substream) 1324 { 1325 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 1326 1327 spin_lock_irq(&rme96->lock); 1328 if (RME96_ISPLAYING(rme96)) { 1329 snd_rme96_playback_stop(rme96); 1330 } 1331 writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS); 1332 spin_unlock_irq(&rme96->lock); 1333 return 0; 1334 } 1335 1336 static int 1337 snd_rme96_capture_prepare(struct snd_pcm_substream *substream) 1338 { 1339 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 1340 1341 spin_lock_irq(&rme96->lock); 1342 if (RME96_ISRECORDING(rme96)) { 1343 snd_rme96_capture_stop(rme96); 1344 } 1345 writel(0, rme96->iobase + RME96_IO_RESET_REC_POS); 1346 spin_unlock_irq(&rme96->lock); 1347 return 0; 1348 } 1349 1350 static int 1351 snd_rme96_playback_trigger(struct snd_pcm_substream *substream, 1352 int cmd) 1353 { 1354 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 1355 1356 switch (cmd) { 1357 case SNDRV_PCM_TRIGGER_START: 1358 if (!RME96_ISPLAYING(rme96)) { 1359 if (substream != rme96->playback_substream) { 1360 return -EBUSY; 1361 } 1362 snd_rme96_playback_start(rme96, 0); 1363 } 1364 break; 1365 1366 case SNDRV_PCM_TRIGGER_STOP: 1367 if (RME96_ISPLAYING(rme96)) { 1368 if (substream != rme96->playback_substream) { 1369 return -EBUSY; 1370 } 1371 snd_rme96_playback_stop(rme96); 1372 } 1373 break; 1374 1375 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1376 if (RME96_ISPLAYING(rme96)) { 1377 snd_rme96_playback_stop(rme96); 1378 } 1379 break; 1380 1381 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1382 if (!RME96_ISPLAYING(rme96)) { 1383 snd_rme96_playback_start(rme96, 1); 1384 } 1385 break; 1386 1387 default: 1388 return -EINVAL; 1389 } 1390 return 0; 1391 } 1392 1393 static int 1394 snd_rme96_capture_trigger(struct snd_pcm_substream *substream, 1395 int cmd) 1396 { 1397 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 1398 1399 switch (cmd) { 1400 case SNDRV_PCM_TRIGGER_START: 1401 if (!RME96_ISRECORDING(rme96)) { 1402 if (substream != rme96->capture_substream) { 1403 return -EBUSY; 1404 } 1405 snd_rme96_capture_start(rme96, 0); 1406 } 1407 break; 1408 1409 case SNDRV_PCM_TRIGGER_STOP: 1410 if (RME96_ISRECORDING(rme96)) { 1411 if (substream != rme96->capture_substream) { 1412 return -EBUSY; 1413 } 1414 snd_rme96_capture_stop(rme96); 1415 } 1416 break; 1417 1418 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1419 if (RME96_ISRECORDING(rme96)) { 1420 snd_rme96_capture_stop(rme96); 1421 } 1422 break; 1423 1424 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1425 if (!RME96_ISRECORDING(rme96)) { 1426 snd_rme96_capture_start(rme96, 1); 1427 } 1428 break; 1429 1430 default: 1431 return -EINVAL; 1432 } 1433 1434 return 0; 1435 } 1436 1437 static snd_pcm_uframes_t 1438 snd_rme96_playback_pointer(struct snd_pcm_substream *substream) 1439 { 1440 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 1441 return snd_rme96_playback_ptr(rme96); 1442 } 1443 1444 static snd_pcm_uframes_t 1445 snd_rme96_capture_pointer(struct snd_pcm_substream *substream) 1446 { 1447 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 1448 return snd_rme96_capture_ptr(rme96); 1449 } 1450 1451 static struct snd_pcm_ops snd_rme96_playback_spdif_ops = { 1452 .open = snd_rme96_playback_spdif_open, 1453 .close = snd_rme96_playback_close, 1454 .ioctl = snd_pcm_lib_ioctl, 1455 .hw_params = snd_rme96_playback_hw_params, 1456 .prepare = snd_rme96_playback_prepare, 1457 .trigger = snd_rme96_playback_trigger, 1458 .pointer = snd_rme96_playback_pointer, 1459 .copy = snd_rme96_playback_copy, 1460 .silence = snd_rme96_playback_silence, 1461 .mmap = snd_pcm_lib_mmap_iomem, 1462 }; 1463 1464 static struct snd_pcm_ops snd_rme96_capture_spdif_ops = { 1465 .open = snd_rme96_capture_spdif_open, 1466 .close = snd_rme96_capture_close, 1467 .ioctl = snd_pcm_lib_ioctl, 1468 .hw_params = snd_rme96_capture_hw_params, 1469 .prepare = snd_rme96_capture_prepare, 1470 .trigger = snd_rme96_capture_trigger, 1471 .pointer = snd_rme96_capture_pointer, 1472 .copy = snd_rme96_capture_copy, 1473 .mmap = snd_pcm_lib_mmap_iomem, 1474 }; 1475 1476 static struct snd_pcm_ops snd_rme96_playback_adat_ops = { 1477 .open = snd_rme96_playback_adat_open, 1478 .close = snd_rme96_playback_close, 1479 .ioctl = snd_pcm_lib_ioctl, 1480 .hw_params = snd_rme96_playback_hw_params, 1481 .prepare = snd_rme96_playback_prepare, 1482 .trigger = snd_rme96_playback_trigger, 1483 .pointer = snd_rme96_playback_pointer, 1484 .copy = snd_rme96_playback_copy, 1485 .silence = snd_rme96_playback_silence, 1486 .mmap = snd_pcm_lib_mmap_iomem, 1487 }; 1488 1489 static struct snd_pcm_ops snd_rme96_capture_adat_ops = { 1490 .open = snd_rme96_capture_adat_open, 1491 .close = snd_rme96_capture_close, 1492 .ioctl = snd_pcm_lib_ioctl, 1493 .hw_params = snd_rme96_capture_hw_params, 1494 .prepare = snd_rme96_capture_prepare, 1495 .trigger = snd_rme96_capture_trigger, 1496 .pointer = snd_rme96_capture_pointer, 1497 .copy = snd_rme96_capture_copy, 1498 .mmap = snd_pcm_lib_mmap_iomem, 1499 }; 1500 1501 static void 1502 snd_rme96_free(void *private_data) 1503 { 1504 struct rme96 *rme96 = (struct rme96 *)private_data; 1505 1506 if (rme96 == NULL) { 1507 return; 1508 } 1509 if (rme96->irq >= 0) { 1510 snd_rme96_playback_stop(rme96); 1511 snd_rme96_capture_stop(rme96); 1512 rme96->areg &= ~RME96_AR_DAC_EN; 1513 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 1514 free_irq(rme96->irq, (void *)rme96); 1515 rme96->irq = -1; 1516 } 1517 if (rme96->iobase) { 1518 iounmap(rme96->iobase); 1519 rme96->iobase = NULL; 1520 } 1521 if (rme96->port) { 1522 pci_release_regions(rme96->pci); 1523 rme96->port = 0; 1524 } 1525 pci_disable_device(rme96->pci); 1526 } 1527 1528 static void 1529 snd_rme96_free_spdif_pcm(struct snd_pcm *pcm) 1530 { 1531 struct rme96 *rme96 = (struct rme96 *) pcm->private_data; 1532 rme96->spdif_pcm = NULL; 1533 } 1534 1535 static void 1536 snd_rme96_free_adat_pcm(struct snd_pcm *pcm) 1537 { 1538 struct rme96 *rme96 = (struct rme96 *) pcm->private_data; 1539 rme96->adat_pcm = NULL; 1540 } 1541 1542 static int __devinit 1543 snd_rme96_create(struct rme96 *rme96) 1544 { 1545 struct pci_dev *pci = rme96->pci; 1546 int err; 1547 1548 rme96->irq = -1; 1549 spin_lock_init(&rme96->lock); 1550 1551 if ((err = pci_enable_device(pci)) < 0) 1552 return err; 1553 1554 if ((err = pci_request_regions(pci, "RME96")) < 0) 1555 return err; 1556 rme96->port = pci_resource_start(rme96->pci, 0); 1557 1558 rme96->iobase = ioremap_nocache(rme96->port, RME96_IO_SIZE); 1559 if (!rme96->iobase) { 1560 snd_printk(KERN_ERR "unable to remap memory region 0x%lx-0x%lx\n", rme96->port, rme96->port + RME96_IO_SIZE - 1); 1561 return -ENOMEM; 1562 } 1563 1564 if (request_irq(pci->irq, snd_rme96_interrupt, IRQF_SHARED, 1565 "RME96", rme96)) { 1566 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq); 1567 return -EBUSY; 1568 } 1569 rme96->irq = pci->irq; 1570 1571 /* read the card's revision number */ 1572 pci_read_config_byte(pci, 8, &rme96->rev); 1573 1574 /* set up ALSA pcm device for S/PDIF */ 1575 if ((err = snd_pcm_new(rme96->card, "Digi96 IEC958", 0, 1576 1, 1, &rme96->spdif_pcm)) < 0) 1577 { 1578 return err; 1579 } 1580 rme96->spdif_pcm->private_data = rme96; 1581 rme96->spdif_pcm->private_free = snd_rme96_free_spdif_pcm; 1582 strcpy(rme96->spdif_pcm->name, "Digi96 IEC958"); 1583 snd_pcm_set_ops(rme96->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme96_playback_spdif_ops); 1584 snd_pcm_set_ops(rme96->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme96_capture_spdif_ops); 1585 1586 rme96->spdif_pcm->info_flags = 0; 1587 1588 /* set up ALSA pcm device for ADAT */ 1589 if (pci->device == PCI_DEVICE_ID_RME_DIGI96) { 1590 /* ADAT is not available on the base model */ 1591 rme96->adat_pcm = NULL; 1592 } else { 1593 if ((err = snd_pcm_new(rme96->card, "Digi96 ADAT", 1, 1594 1, 1, &rme96->adat_pcm)) < 0) 1595 { 1596 return err; 1597 } 1598 rme96->adat_pcm->private_data = rme96; 1599 rme96->adat_pcm->private_free = snd_rme96_free_adat_pcm; 1600 strcpy(rme96->adat_pcm->name, "Digi96 ADAT"); 1601 snd_pcm_set_ops(rme96->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme96_playback_adat_ops); 1602 snd_pcm_set_ops(rme96->adat_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme96_capture_adat_ops); 1603 1604 rme96->adat_pcm->info_flags = 0; 1605 } 1606 1607 rme96->playback_periodsize = 0; 1608 rme96->capture_periodsize = 0; 1609 1610 /* make sure playback/capture is stopped, if by some reason active */ 1611 snd_rme96_playback_stop(rme96); 1612 snd_rme96_capture_stop(rme96); 1613 1614 /* set default values in registers */ 1615 rme96->wcreg = 1616 RME96_WCR_FREQ_1 | /* set 44.1 kHz playback */ 1617 RME96_WCR_SEL | /* normal playback */ 1618 RME96_WCR_MASTER | /* set to master clock mode */ 1619 RME96_WCR_INP_0; /* set coaxial input */ 1620 1621 rme96->areg = RME96_AR_FREQPAD_1; /* set 44.1 kHz analog capture */ 1622 1623 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 1624 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 1625 1626 /* reset the ADC */ 1627 writel(rme96->areg | RME96_AR_PD2, 1628 rme96->iobase + RME96_IO_ADDITIONAL_REG); 1629 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 1630 1631 /* reset and enable the DAC (order is important). */ 1632 snd_rme96_reset_dac(rme96); 1633 rme96->areg |= RME96_AR_DAC_EN; 1634 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 1635 1636 /* reset playback and record buffer pointers */ 1637 writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS); 1638 writel(0, rme96->iobase + RME96_IO_RESET_REC_POS); 1639 1640 /* reset volume */ 1641 rme96->vol[0] = rme96->vol[1] = 0; 1642 if (RME96_HAS_ANALOG_OUT(rme96)) { 1643 snd_rme96_apply_dac_volume(rme96); 1644 } 1645 1646 /* init switch interface */ 1647 if ((err = snd_rme96_create_switches(rme96->card, rme96)) < 0) { 1648 return err; 1649 } 1650 1651 /* init proc interface */ 1652 snd_rme96_proc_init(rme96); 1653 1654 return 0; 1655 } 1656 1657 /* 1658 * proc interface 1659 */ 1660 1661 static void 1662 snd_rme96_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer) 1663 { 1664 int n; 1665 struct rme96 *rme96 = (struct rme96 *)entry->private_data; 1666 1667 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER); 1668 1669 snd_iprintf(buffer, rme96->card->longname); 1670 snd_iprintf(buffer, " (index #%d)\n", rme96->card->number + 1); 1671 1672 snd_iprintf(buffer, "\nGeneral settings\n"); 1673 if (rme96->wcreg & RME96_WCR_IDIS) { 1674 snd_iprintf(buffer, " period size: N/A (interrupts " 1675 "disabled)\n"); 1676 } else if (rme96->wcreg & RME96_WCR_ISEL) { 1677 snd_iprintf(buffer, " period size: 2048 bytes\n"); 1678 } else { 1679 snd_iprintf(buffer, " period size: 8192 bytes\n"); 1680 } 1681 snd_iprintf(buffer, "\nInput settings\n"); 1682 switch (snd_rme96_getinputtype(rme96)) { 1683 case RME96_INPUT_OPTICAL: 1684 snd_iprintf(buffer, " input: optical"); 1685 break; 1686 case RME96_INPUT_COAXIAL: 1687 snd_iprintf(buffer, " input: coaxial"); 1688 break; 1689 case RME96_INPUT_INTERNAL: 1690 snd_iprintf(buffer, " input: internal"); 1691 break; 1692 case RME96_INPUT_XLR: 1693 snd_iprintf(buffer, " input: XLR"); 1694 break; 1695 case RME96_INPUT_ANALOG: 1696 snd_iprintf(buffer, " input: analog"); 1697 break; 1698 } 1699 if (snd_rme96_capture_getrate(rme96, &n) < 0) { 1700 snd_iprintf(buffer, "\n sample rate: no valid signal\n"); 1701 } else { 1702 if (n) { 1703 snd_iprintf(buffer, " (8 channels)\n"); 1704 } else { 1705 snd_iprintf(buffer, " (2 channels)\n"); 1706 } 1707 snd_iprintf(buffer, " sample rate: %d Hz\n", 1708 snd_rme96_capture_getrate(rme96, &n)); 1709 } 1710 if (rme96->wcreg & RME96_WCR_MODE24_2) { 1711 snd_iprintf(buffer, " sample format: 24 bit\n"); 1712 } else { 1713 snd_iprintf(buffer, " sample format: 16 bit\n"); 1714 } 1715 1716 snd_iprintf(buffer, "\nOutput settings\n"); 1717 if (rme96->wcreg & RME96_WCR_SEL) { 1718 snd_iprintf(buffer, " output signal: normal playback\n"); 1719 } else { 1720 snd_iprintf(buffer, " output signal: same as input\n"); 1721 } 1722 snd_iprintf(buffer, " sample rate: %d Hz\n", 1723 snd_rme96_playback_getrate(rme96)); 1724 if (rme96->wcreg & RME96_WCR_MODE24) { 1725 snd_iprintf(buffer, " sample format: 24 bit\n"); 1726 } else { 1727 snd_iprintf(buffer, " sample format: 16 bit\n"); 1728 } 1729 if (rme96->areg & RME96_AR_WSEL) { 1730 snd_iprintf(buffer, " sample clock source: word clock\n"); 1731 } else if (rme96->wcreg & RME96_WCR_MASTER) { 1732 snd_iprintf(buffer, " sample clock source: internal\n"); 1733 } else if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) { 1734 snd_iprintf(buffer, " sample clock source: autosync (internal anyway due to analog input setting)\n"); 1735 } else if (snd_rme96_capture_getrate(rme96, &n) < 0) { 1736 snd_iprintf(buffer, " sample clock source: autosync (internal anyway due to no valid signal)\n"); 1737 } else { 1738 snd_iprintf(buffer, " sample clock source: autosync\n"); 1739 } 1740 if (rme96->wcreg & RME96_WCR_PRO) { 1741 snd_iprintf(buffer, " format: AES/EBU (professional)\n"); 1742 } else { 1743 snd_iprintf(buffer, " format: IEC958 (consumer)\n"); 1744 } 1745 if (rme96->wcreg & RME96_WCR_EMP) { 1746 snd_iprintf(buffer, " emphasis: on\n"); 1747 } else { 1748 snd_iprintf(buffer, " emphasis: off\n"); 1749 } 1750 if (rme96->wcreg & RME96_WCR_DOLBY) { 1751 snd_iprintf(buffer, " non-audio (dolby): on\n"); 1752 } else { 1753 snd_iprintf(buffer, " non-audio (dolby): off\n"); 1754 } 1755 if (RME96_HAS_ANALOG_IN(rme96)) { 1756 snd_iprintf(buffer, "\nAnalog output settings\n"); 1757 switch (snd_rme96_getmontracks(rme96)) { 1758 case RME96_MONITOR_TRACKS_1_2: 1759 snd_iprintf(buffer, " monitored ADAT tracks: 1+2\n"); 1760 break; 1761 case RME96_MONITOR_TRACKS_3_4: 1762 snd_iprintf(buffer, " monitored ADAT tracks: 3+4\n"); 1763 break; 1764 case RME96_MONITOR_TRACKS_5_6: 1765 snd_iprintf(buffer, " monitored ADAT tracks: 5+6\n"); 1766 break; 1767 case RME96_MONITOR_TRACKS_7_8: 1768 snd_iprintf(buffer, " monitored ADAT tracks: 7+8\n"); 1769 break; 1770 } 1771 switch (snd_rme96_getattenuation(rme96)) { 1772 case RME96_ATTENUATION_0: 1773 snd_iprintf(buffer, " attenuation: 0 dB\n"); 1774 break; 1775 case RME96_ATTENUATION_6: 1776 snd_iprintf(buffer, " attenuation: -6 dB\n"); 1777 break; 1778 case RME96_ATTENUATION_12: 1779 snd_iprintf(buffer, " attenuation: -12 dB\n"); 1780 break; 1781 case RME96_ATTENUATION_18: 1782 snd_iprintf(buffer, " attenuation: -18 dB\n"); 1783 break; 1784 } 1785 snd_iprintf(buffer, " volume left: %u\n", rme96->vol[0]); 1786 snd_iprintf(buffer, " volume right: %u\n", rme96->vol[1]); 1787 } 1788 } 1789 1790 static void __devinit 1791 snd_rme96_proc_init(struct rme96 *rme96) 1792 { 1793 struct snd_info_entry *entry; 1794 1795 if (! snd_card_proc_new(rme96->card, "rme96", &entry)) 1796 snd_info_set_text_ops(entry, rme96, snd_rme96_proc_read); 1797 } 1798 1799 /* 1800 * control interface 1801 */ 1802 1803 #define snd_rme96_info_loopback_control snd_ctl_boolean_mono_info 1804 1805 static int 1806 snd_rme96_get_loopback_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1807 { 1808 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 1809 1810 spin_lock_irq(&rme96->lock); 1811 ucontrol->value.integer.value[0] = rme96->wcreg & RME96_WCR_SEL ? 0 : 1; 1812 spin_unlock_irq(&rme96->lock); 1813 return 0; 1814 } 1815 static int 1816 snd_rme96_put_loopback_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1817 { 1818 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 1819 unsigned int val; 1820 int change; 1821 1822 val = ucontrol->value.integer.value[0] ? 0 : RME96_WCR_SEL; 1823 spin_lock_irq(&rme96->lock); 1824 val = (rme96->wcreg & ~RME96_WCR_SEL) | val; 1825 change = val != rme96->wcreg; 1826 rme96->wcreg = val; 1827 writel(val, rme96->iobase + RME96_IO_CONTROL_REGISTER); 1828 spin_unlock_irq(&rme96->lock); 1829 return change; 1830 } 1831 1832 static int 1833 snd_rme96_info_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 1834 { 1835 static char *_texts[5] = { "Optical", "Coaxial", "Internal", "XLR", "Analog" }; 1836 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 1837 char *texts[5] = { _texts[0], _texts[1], _texts[2], _texts[3], _texts[4] }; 1838 1839 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 1840 uinfo->count = 1; 1841 switch (rme96->pci->device) { 1842 case PCI_DEVICE_ID_RME_DIGI96: 1843 case PCI_DEVICE_ID_RME_DIGI96_8: 1844 uinfo->value.enumerated.items = 3; 1845 break; 1846 case PCI_DEVICE_ID_RME_DIGI96_8_PRO: 1847 uinfo->value.enumerated.items = 4; 1848 break; 1849 case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST: 1850 if (rme96->rev > 4) { 1851 /* PST */ 1852 uinfo->value.enumerated.items = 4; 1853 texts[3] = _texts[4]; /* Analog instead of XLR */ 1854 } else { 1855 /* PAD */ 1856 uinfo->value.enumerated.items = 5; 1857 } 1858 break; 1859 default: 1860 snd_BUG(); 1861 break; 1862 } 1863 if (uinfo->value.enumerated.item > uinfo->value.enumerated.items - 1) { 1864 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; 1865 } 1866 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); 1867 return 0; 1868 } 1869 static int 1870 snd_rme96_get_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1871 { 1872 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 1873 unsigned int items = 3; 1874 1875 spin_lock_irq(&rme96->lock); 1876 ucontrol->value.enumerated.item[0] = snd_rme96_getinputtype(rme96); 1877 1878 switch (rme96->pci->device) { 1879 case PCI_DEVICE_ID_RME_DIGI96: 1880 case PCI_DEVICE_ID_RME_DIGI96_8: 1881 items = 3; 1882 break; 1883 case PCI_DEVICE_ID_RME_DIGI96_8_PRO: 1884 items = 4; 1885 break; 1886 case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST: 1887 if (rme96->rev > 4) { 1888 /* for handling PST case, (INPUT_ANALOG is moved to INPUT_XLR */ 1889 if (ucontrol->value.enumerated.item[0] == RME96_INPUT_ANALOG) { 1890 ucontrol->value.enumerated.item[0] = RME96_INPUT_XLR; 1891 } 1892 items = 4; 1893 } else { 1894 items = 5; 1895 } 1896 break; 1897 default: 1898 snd_BUG(); 1899 break; 1900 } 1901 if (ucontrol->value.enumerated.item[0] >= items) { 1902 ucontrol->value.enumerated.item[0] = items - 1; 1903 } 1904 1905 spin_unlock_irq(&rme96->lock); 1906 return 0; 1907 } 1908 static int 1909 snd_rme96_put_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1910 { 1911 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 1912 unsigned int val; 1913 int change, items = 3; 1914 1915 switch (rme96->pci->device) { 1916 case PCI_DEVICE_ID_RME_DIGI96: 1917 case PCI_DEVICE_ID_RME_DIGI96_8: 1918 items = 3; 1919 break; 1920 case PCI_DEVICE_ID_RME_DIGI96_8_PRO: 1921 items = 4; 1922 break; 1923 case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST: 1924 if (rme96->rev > 4) { 1925 items = 4; 1926 } else { 1927 items = 5; 1928 } 1929 break; 1930 default: 1931 snd_BUG(); 1932 break; 1933 } 1934 val = ucontrol->value.enumerated.item[0] % items; 1935 1936 /* special case for PST */ 1937 if (rme96->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && rme96->rev > 4) { 1938 if (val == RME96_INPUT_XLR) { 1939 val = RME96_INPUT_ANALOG; 1940 } 1941 } 1942 1943 spin_lock_irq(&rme96->lock); 1944 change = (int)val != snd_rme96_getinputtype(rme96); 1945 snd_rme96_setinputtype(rme96, val); 1946 spin_unlock_irq(&rme96->lock); 1947 return change; 1948 } 1949 1950 static int 1951 snd_rme96_info_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 1952 { 1953 static char *texts[3] = { "AutoSync", "Internal", "Word" }; 1954 1955 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 1956 uinfo->count = 1; 1957 uinfo->value.enumerated.items = 3; 1958 if (uinfo->value.enumerated.item > 2) { 1959 uinfo->value.enumerated.item = 2; 1960 } 1961 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); 1962 return 0; 1963 } 1964 static int 1965 snd_rme96_get_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1966 { 1967 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 1968 1969 spin_lock_irq(&rme96->lock); 1970 ucontrol->value.enumerated.item[0] = snd_rme96_getclockmode(rme96); 1971 spin_unlock_irq(&rme96->lock); 1972 return 0; 1973 } 1974 static int 1975 snd_rme96_put_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1976 { 1977 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 1978 unsigned int val; 1979 int change; 1980 1981 val = ucontrol->value.enumerated.item[0] % 3; 1982 spin_lock_irq(&rme96->lock); 1983 change = (int)val != snd_rme96_getclockmode(rme96); 1984 snd_rme96_setclockmode(rme96, val); 1985 spin_unlock_irq(&rme96->lock); 1986 return change; 1987 } 1988 1989 static int 1990 snd_rme96_info_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 1991 { 1992 static char *texts[4] = { "0 dB", "-6 dB", "-12 dB", "-18 dB" }; 1993 1994 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 1995 uinfo->count = 1; 1996 uinfo->value.enumerated.items = 4; 1997 if (uinfo->value.enumerated.item > 3) { 1998 uinfo->value.enumerated.item = 3; 1999 } 2000 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); 2001 return 0; 2002 } 2003 static int 2004 snd_rme96_get_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2005 { 2006 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 2007 2008 spin_lock_irq(&rme96->lock); 2009 ucontrol->value.enumerated.item[0] = snd_rme96_getattenuation(rme96); 2010 spin_unlock_irq(&rme96->lock); 2011 return 0; 2012 } 2013 static int 2014 snd_rme96_put_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2015 { 2016 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 2017 unsigned int val; 2018 int change; 2019 2020 val = ucontrol->value.enumerated.item[0] % 4; 2021 spin_lock_irq(&rme96->lock); 2022 2023 change = (int)val != snd_rme96_getattenuation(rme96); 2024 snd_rme96_setattenuation(rme96, val); 2025 spin_unlock_irq(&rme96->lock); 2026 return change; 2027 } 2028 2029 static int 2030 snd_rme96_info_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2031 { 2032 static char *texts[4] = { "1+2", "3+4", "5+6", "7+8" }; 2033 2034 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2035 uinfo->count = 1; 2036 uinfo->value.enumerated.items = 4; 2037 if (uinfo->value.enumerated.item > 3) { 2038 uinfo->value.enumerated.item = 3; 2039 } 2040 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); 2041 return 0; 2042 } 2043 static int 2044 snd_rme96_get_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2045 { 2046 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 2047 2048 spin_lock_irq(&rme96->lock); 2049 ucontrol->value.enumerated.item[0] = snd_rme96_getmontracks(rme96); 2050 spin_unlock_irq(&rme96->lock); 2051 return 0; 2052 } 2053 static int 2054 snd_rme96_put_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2055 { 2056 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 2057 unsigned int val; 2058 int change; 2059 2060 val = ucontrol->value.enumerated.item[0] % 4; 2061 spin_lock_irq(&rme96->lock); 2062 change = (int)val != snd_rme96_getmontracks(rme96); 2063 snd_rme96_setmontracks(rme96, val); 2064 spin_unlock_irq(&rme96->lock); 2065 return change; 2066 } 2067 2068 static u32 snd_rme96_convert_from_aes(struct snd_aes_iec958 *aes) 2069 { 2070 u32 val = 0; 2071 val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? RME96_WCR_PRO : 0; 2072 val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? RME96_WCR_DOLBY : 0; 2073 if (val & RME96_WCR_PRO) 2074 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? RME96_WCR_EMP : 0; 2075 else 2076 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? RME96_WCR_EMP : 0; 2077 return val; 2078 } 2079 2080 static void snd_rme96_convert_to_aes(struct snd_aes_iec958 *aes, u32 val) 2081 { 2082 aes->status[0] = ((val & RME96_WCR_PRO) ? IEC958_AES0_PROFESSIONAL : 0) | 2083 ((val & RME96_WCR_DOLBY) ? IEC958_AES0_NONAUDIO : 0); 2084 if (val & RME96_WCR_PRO) 2085 aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0; 2086 else 2087 aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_CON_EMPHASIS_5015 : 0; 2088 } 2089 2090 static int snd_rme96_control_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2091 { 2092 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 2093 uinfo->count = 1; 2094 return 0; 2095 } 2096 2097 static int snd_rme96_control_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2098 { 2099 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 2100 2101 snd_rme96_convert_to_aes(&ucontrol->value.iec958, rme96->wcreg_spdif); 2102 return 0; 2103 } 2104 2105 static int snd_rme96_control_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2106 { 2107 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 2108 int change; 2109 u32 val; 2110 2111 val = snd_rme96_convert_from_aes(&ucontrol->value.iec958); 2112 spin_lock_irq(&rme96->lock); 2113 change = val != rme96->wcreg_spdif; 2114 rme96->wcreg_spdif = val; 2115 spin_unlock_irq(&rme96->lock); 2116 return change; 2117 } 2118 2119 static int snd_rme96_control_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2120 { 2121 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 2122 uinfo->count = 1; 2123 return 0; 2124 } 2125 2126 static int snd_rme96_control_spdif_stream_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2127 { 2128 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 2129 2130 snd_rme96_convert_to_aes(&ucontrol->value.iec958, rme96->wcreg_spdif_stream); 2131 return 0; 2132 } 2133 2134 static int snd_rme96_control_spdif_stream_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2135 { 2136 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 2137 int change; 2138 u32 val; 2139 2140 val = snd_rme96_convert_from_aes(&ucontrol->value.iec958); 2141 spin_lock_irq(&rme96->lock); 2142 change = val != rme96->wcreg_spdif_stream; 2143 rme96->wcreg_spdif_stream = val; 2144 rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP); 2145 rme96->wcreg |= val; 2146 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 2147 spin_unlock_irq(&rme96->lock); 2148 return change; 2149 } 2150 2151 static int snd_rme96_control_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2152 { 2153 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 2154 uinfo->count = 1; 2155 return 0; 2156 } 2157 2158 static int snd_rme96_control_spdif_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2159 { 2160 ucontrol->value.iec958.status[0] = kcontrol->private_value; 2161 return 0; 2162 } 2163 2164 static int 2165 snd_rme96_dac_volume_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2166 { 2167 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 2168 2169 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 2170 uinfo->count = 2; 2171 uinfo->value.integer.min = 0; 2172 uinfo->value.integer.max = RME96_185X_MAX_OUT(rme96); 2173 return 0; 2174 } 2175 2176 static int 2177 snd_rme96_dac_volume_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *u) 2178 { 2179 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 2180 2181 spin_lock_irq(&rme96->lock); 2182 u->value.integer.value[0] = rme96->vol[0]; 2183 u->value.integer.value[1] = rme96->vol[1]; 2184 spin_unlock_irq(&rme96->lock); 2185 2186 return 0; 2187 } 2188 2189 static int 2190 snd_rme96_dac_volume_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *u) 2191 { 2192 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 2193 int change = 0; 2194 unsigned int vol, maxvol; 2195 2196 2197 if (!RME96_HAS_ANALOG_OUT(rme96)) 2198 return -EINVAL; 2199 maxvol = RME96_185X_MAX_OUT(rme96); 2200 spin_lock_irq(&rme96->lock); 2201 vol = u->value.integer.value[0]; 2202 if (vol != rme96->vol[0] && vol <= maxvol) { 2203 rme96->vol[0] = vol; 2204 change = 1; 2205 } 2206 vol = u->value.integer.value[1]; 2207 if (vol != rme96->vol[1] && vol <= maxvol) { 2208 rme96->vol[1] = vol; 2209 change = 1; 2210 } 2211 if (change) 2212 snd_rme96_apply_dac_volume(rme96); 2213 spin_unlock_irq(&rme96->lock); 2214 2215 return change; 2216 } 2217 2218 static struct snd_kcontrol_new snd_rme96_controls[] = { 2219 { 2220 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 2221 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT), 2222 .info = snd_rme96_control_spdif_info, 2223 .get = snd_rme96_control_spdif_get, 2224 .put = snd_rme96_control_spdif_put 2225 }, 2226 { 2227 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE, 2228 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 2229 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM), 2230 .info = snd_rme96_control_spdif_stream_info, 2231 .get = snd_rme96_control_spdif_stream_get, 2232 .put = snd_rme96_control_spdif_stream_put 2233 }, 2234 { 2235 .access = SNDRV_CTL_ELEM_ACCESS_READ, 2236 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 2237 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK), 2238 .info = snd_rme96_control_spdif_mask_info, 2239 .get = snd_rme96_control_spdif_mask_get, 2240 .private_value = IEC958_AES0_NONAUDIO | 2241 IEC958_AES0_PROFESSIONAL | 2242 IEC958_AES0_CON_EMPHASIS 2243 }, 2244 { 2245 .access = SNDRV_CTL_ELEM_ACCESS_READ, 2246 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 2247 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK), 2248 .info = snd_rme96_control_spdif_mask_info, 2249 .get = snd_rme96_control_spdif_mask_get, 2250 .private_value = IEC958_AES0_NONAUDIO | 2251 IEC958_AES0_PROFESSIONAL | 2252 IEC958_AES0_PRO_EMPHASIS 2253 }, 2254 { 2255 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2256 .name = "Input Connector", 2257 .info = snd_rme96_info_inputtype_control, 2258 .get = snd_rme96_get_inputtype_control, 2259 .put = snd_rme96_put_inputtype_control 2260 }, 2261 { 2262 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2263 .name = "Loopback Input", 2264 .info = snd_rme96_info_loopback_control, 2265 .get = snd_rme96_get_loopback_control, 2266 .put = snd_rme96_put_loopback_control 2267 }, 2268 { 2269 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2270 .name = "Sample Clock Source", 2271 .info = snd_rme96_info_clockmode_control, 2272 .get = snd_rme96_get_clockmode_control, 2273 .put = snd_rme96_put_clockmode_control 2274 }, 2275 { 2276 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2277 .name = "Monitor Tracks", 2278 .info = snd_rme96_info_montracks_control, 2279 .get = snd_rme96_get_montracks_control, 2280 .put = snd_rme96_put_montracks_control 2281 }, 2282 { 2283 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2284 .name = "Attenuation", 2285 .info = snd_rme96_info_attenuation_control, 2286 .get = snd_rme96_get_attenuation_control, 2287 .put = snd_rme96_put_attenuation_control 2288 }, 2289 { 2290 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2291 .name = "DAC Playback Volume", 2292 .info = snd_rme96_dac_volume_info, 2293 .get = snd_rme96_dac_volume_get, 2294 .put = snd_rme96_dac_volume_put 2295 } 2296 }; 2297 2298 static int 2299 snd_rme96_create_switches(struct snd_card *card, 2300 struct rme96 *rme96) 2301 { 2302 int idx, err; 2303 struct snd_kcontrol *kctl; 2304 2305 for (idx = 0; idx < 7; idx++) { 2306 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_rme96_controls[idx], rme96))) < 0) 2307 return err; 2308 if (idx == 1) /* IEC958 (S/PDIF) Stream */ 2309 rme96->spdif_ctl = kctl; 2310 } 2311 2312 if (RME96_HAS_ANALOG_OUT(rme96)) { 2313 for (idx = 7; idx < 10; idx++) 2314 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_rme96_controls[idx], rme96))) < 0) 2315 return err; 2316 } 2317 2318 return 0; 2319 } 2320 2321 /* 2322 * Card initialisation 2323 */ 2324 2325 static void snd_rme96_card_free(struct snd_card *card) 2326 { 2327 snd_rme96_free(card->private_data); 2328 } 2329 2330 static int __devinit 2331 snd_rme96_probe(struct pci_dev *pci, 2332 const struct pci_device_id *pci_id) 2333 { 2334 static int dev; 2335 struct rme96 *rme96; 2336 struct snd_card *card; 2337 int err; 2338 u8 val; 2339 2340 if (dev >= SNDRV_CARDS) { 2341 return -ENODEV; 2342 } 2343 if (!enable[dev]) { 2344 dev++; 2345 return -ENOENT; 2346 } 2347 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 2348 sizeof(struct rme96), &card); 2349 if (err < 0) 2350 return err; 2351 card->private_free = snd_rme96_card_free; 2352 rme96 = (struct rme96 *)card->private_data; 2353 rme96->card = card; 2354 rme96->pci = pci; 2355 snd_card_set_dev(card, &pci->dev); 2356 if ((err = snd_rme96_create(rme96)) < 0) { 2357 snd_card_free(card); 2358 return err; 2359 } 2360 2361 strcpy(card->driver, "Digi96"); 2362 switch (rme96->pci->device) { 2363 case PCI_DEVICE_ID_RME_DIGI96: 2364 strcpy(card->shortname, "RME Digi96"); 2365 break; 2366 case PCI_DEVICE_ID_RME_DIGI96_8: 2367 strcpy(card->shortname, "RME Digi96/8"); 2368 break; 2369 case PCI_DEVICE_ID_RME_DIGI96_8_PRO: 2370 strcpy(card->shortname, "RME Digi96/8 PRO"); 2371 break; 2372 case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST: 2373 pci_read_config_byte(rme96->pci, 8, &val); 2374 if (val < 5) { 2375 strcpy(card->shortname, "RME Digi96/8 PAD"); 2376 } else { 2377 strcpy(card->shortname, "RME Digi96/8 PST"); 2378 } 2379 break; 2380 } 2381 sprintf(card->longname, "%s at 0x%lx, irq %d", card->shortname, 2382 rme96->port, rme96->irq); 2383 2384 if ((err = snd_card_register(card)) < 0) { 2385 snd_card_free(card); 2386 return err; 2387 } 2388 pci_set_drvdata(pci, card); 2389 dev++; 2390 return 0; 2391 } 2392 2393 static void __devexit snd_rme96_remove(struct pci_dev *pci) 2394 { 2395 snd_card_free(pci_get_drvdata(pci)); 2396 pci_set_drvdata(pci, NULL); 2397 } 2398 2399 static struct pci_driver driver = { 2400 .name = "RME Digi96", 2401 .id_table = snd_rme96_ids, 2402 .probe = snd_rme96_probe, 2403 .remove = __devexit_p(snd_rme96_remove), 2404 }; 2405 2406 static int __init alsa_card_rme96_init(void) 2407 { 2408 return pci_register_driver(&driver); 2409 } 2410 2411 static void __exit alsa_card_rme96_exit(void) 2412 { 2413 pci_unregister_driver(&driver); 2414 } 2415 2416 module_init(alsa_card_rme96_init) 2417 module_exit(alsa_card_rme96_exit) 2418