1 #define CS4245_CHIP_ID 0x01 2 #define CS4245_POWER_CTRL 0x02 3 #define CS4245_DAC_CTRL_1 0x03 4 #define CS4245_ADC_CTRL 0x04 5 #define CS4245_MCLK_FREQ 0x05 6 #define CS4245_SIGNAL_SEL 0x06 7 #define CS4245_PGA_B_CTRL 0x07 8 #define CS4245_PGA_A_CTRL 0x08 9 #define CS4245_ANALOG_IN 0x09 10 #define CS4245_DAC_A_CTRL 0x0a 11 #define CS4245_DAC_B_CTRL 0x0b 12 #define CS4245_DAC_CTRL_2 0x0c 13 #define CS4245_INT_STATUS 0x0d 14 #define CS4245_INT_MASK 0x0e 15 #define CS4245_INT_MODE_MSB 0x0f 16 #define CS4245_INT_MODE_LSB 0x10 17 18 /* Chip ID */ 19 #define CS4245_CHIP_PART_MASK 0xf0 20 #define CS4245_CHIP_REV_MASK 0x0f 21 22 /* Power Control */ 23 #define CS4245_FREEZE 0x80 24 #define CS4245_PDN_MIC 0x08 25 #define CS4245_PDN_ADC 0x04 26 #define CS4245_PDN_DAC 0x02 27 #define CS4245_PDN 0x01 28 29 /* DAC Control */ 30 #define CS4245_DAC_FM_MASK 0xc0 31 #define CS4245_DAC_FM_SINGLE 0x00 32 #define CS4245_DAC_FM_DOUBLE 0x40 33 #define CS4245_DAC_FM_QUAD 0x80 34 #define CS4245_DAC_DIF_MASK 0x30 35 #define CS4245_DAC_DIF_LJUST 0x00 36 #define CS4245_DAC_DIF_I2S 0x10 37 #define CS4245_DAC_DIF_RJUST_16 0x20 38 #define CS4245_DAC_DIF_RJUST_24 0x30 39 #define CS4245_RESERVED_1 0x08 40 #define CS4245_MUTE_DAC 0x04 41 #define CS4245_DEEMPH 0x02 42 #define CS4245_DAC_MASTER 0x01 43 44 /* ADC Control */ 45 #define CS4245_ADC_FM_MASK 0xc0 46 #define CS4245_ADC_FM_SINGLE 0x00 47 #define CS4245_ADC_FM_DOUBLE 0x40 48 #define CS4245_ADC_FM_QUAD 0x80 49 #define CS4245_ADC_DIF_MASK 0x10 50 #define CS4245_ADC_DIF_LJUST 0x00 51 #define CS4245_ADC_DIF_I2S 0x10 52 #define CS4245_MUTE_ADC 0x04 53 #define CS4245_HPF_FREEZE 0x02 54 #define CS4245_ADC_MASTER 0x01 55 56 /* MCLK Frequency */ 57 #define CS4245_MCLK1_MASK 0x70 58 #define CS4245_MCLK1_SHIFT 4 59 #define CS4245_MCLK2_MASK 0x07 60 #define CS4245_MCLK2_SHIFT 0 61 #define CS4245_MCLK_1 0 62 #define CS4245_MCLK_1_5 1 63 #define CS4245_MCLK_2 2 64 #define CS4245_MCLK_3 3 65 #define CS4245_MCLK_4 4 66 67 /* Signal Selection */ 68 #define CS4245_A_OUT_SEL_MASK 0x60 69 #define CS4245_A_OUT_SEL_HIZ 0x00 70 #define CS4245_A_OUT_SEL_DAC 0x20 71 #define CS4245_A_OUT_SEL_PGA 0x40 72 #define CS4245_LOOP 0x02 73 #define CS4245_ASYNCH 0x01 74 75 /* Channel B/A PGA Control */ 76 #define CS4245_PGA_GAIN_MASK 0x3f 77 78 /* ADC Input Control */ 79 #define CS4245_PGA_SOFT 0x10 80 #define CS4245_PGA_ZERO 0x08 81 #define CS4245_SEL_MASK 0x07 82 #define CS4245_SEL_MIC 0x00 83 #define CS4245_SEL_INPUT_1 0x01 84 #define CS4245_SEL_INPUT_2 0x02 85 #define CS4245_SEL_INPUT_3 0x03 86 #define CS4245_SEL_INPUT_4 0x04 87 #define CS4245_SEL_INPUT_5 0x05 88 #define CS4245_SEL_INPUT_6 0x06 89 90 /* DAC Channel A/B Volume Control */ 91 #define CS4245_VOL_MASK 0xff 92 93 /* DAC Control 2 */ 94 #define CS4245_DAC_SOFT 0x80 95 #define CS4245_DAC_ZERO 0x40 96 #define CS4245_INVERT_DAC 0x20 97 #define CS4245_INT_ACTIVE_HIGH 0x01 98 99 /* Interrupt Status/Mask/Mode */ 100 #define CS4245_ADC_CLK_ERR 0x08 101 #define CS4245_DAC_CLK_ERR 0x04 102 #define CS4245_ADC_OVFL 0x02 103 #define CS4245_ADC_UNDRFL 0x01 104 105 #define CS4245_SPI_ADDRESS_S (0x9e << 16) 106 #define CS4245_SPI_WRITE_S (0 << 16) 107 108 #define CS4245_SPI_ADDRESS 0x9e 109 #define CS4245_SPI_WRITE 0 110 #define CS4245_SPI_READ 1 111