1 /* 2 * ALSA modem driver for Intel ICH (i8x0) chipsets 3 * 4 * Copyright (c) 2000 Jaroslav Kysela <perex@suse.cz> 5 * 6 * This is modified (by Sasha Khapyorsky <sashak@smlink.com>) version 7 * of ALSA ICH sound driver intel8x0.c . 8 * 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 23 * 24 */ 25 26 #include <sound/driver.h> 27 #include <asm/io.h> 28 #include <linux/delay.h> 29 #include <linux/interrupt.h> 30 #include <linux/init.h> 31 #include <linux/pci.h> 32 #include <linux/slab.h> 33 #include <linux/moduleparam.h> 34 #include <sound/core.h> 35 #include <sound/pcm.h> 36 #include <sound/ac97_codec.h> 37 #include <sound/info.h> 38 #include <sound/initval.h> 39 40 MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>"); 41 MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; SiS 7013; NVidia MCP/2/2S/3 modems"); 42 MODULE_LICENSE("GPL"); 43 MODULE_SUPPORTED_DEVICE("{{Intel,82801AA-ICH}," 44 "{Intel,82901AB-ICH0}," 45 "{Intel,82801BA-ICH2}," 46 "{Intel,82801CA-ICH3}," 47 "{Intel,82801DB-ICH4}," 48 "{Intel,ICH5}," 49 "{Intel,ICH6}," 50 "{Intel,ICH7}," 51 "{Intel,MX440}," 52 "{SiS,7013}," 53 "{NVidia,NForce Modem}," 54 "{NVidia,NForce2 Modem}," 55 "{NVidia,NForce2s Modem}," 56 "{NVidia,NForce3 Modem}," 57 "{AMD,AMD768}}"); 58 59 static int index[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = -2}; /* Exclude the first card */ 60 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ 61 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */ 62 static int ac97_clock[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 0}; 63 64 module_param_array(index, int, NULL, 0444); 65 MODULE_PARM_DESC(index, "Index value for Intel i8x0 modemcard."); 66 module_param_array(id, charp, NULL, 0444); 67 MODULE_PARM_DESC(id, "ID string for Intel i8x0 modemcard."); 68 module_param_array(enable, bool, NULL, 0444); 69 MODULE_PARM_DESC(enable, "Enable Intel i8x0 modemcard."); 70 module_param_array(ac97_clock, int, NULL, 0444); 71 MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = auto-detect)."); 72 73 /* 74 * Direct registers 75 */ 76 77 #ifndef PCI_DEVICE_ID_INTEL_82801_6 78 #define PCI_DEVICE_ID_INTEL_82801_6 0x2416 79 #endif 80 #ifndef PCI_DEVICE_ID_INTEL_82901_6 81 #define PCI_DEVICE_ID_INTEL_82901_6 0x2426 82 #endif 83 #ifndef PCI_DEVICE_ID_INTEL_82801BA_6 84 #define PCI_DEVICE_ID_INTEL_82801BA_6 0x2446 85 #endif 86 #ifndef PCI_DEVICE_ID_INTEL_440MX_6 87 #define PCI_DEVICE_ID_INTEL_440MX_6 0x7196 88 #endif 89 #ifndef PCI_DEVICE_ID_INTEL_ICH3_6 90 #define PCI_DEVICE_ID_INTEL_ICH3_6 0x2486 91 #endif 92 #ifndef PCI_DEVICE_ID_INTEL_ICH4_6 93 #define PCI_DEVICE_ID_INTEL_ICH4_6 0x24c6 94 #endif 95 #ifndef PCI_DEVICE_ID_INTEL_ICH5_6 96 #define PCI_DEVICE_ID_INTEL_ICH5_6 0x24d6 97 #endif 98 #ifndef PCI_DEVICE_ID_INTEL_ICH6_6 99 #define PCI_DEVICE_ID_INTEL_ICH6_6 0x266d 100 #endif 101 #ifndef PCI_DEVICE_ID_INTEL_ICH7_6 102 #define PCI_DEVICE_ID_INTEL_ICH7_6 0x27dd 103 #endif 104 #ifndef PCI_DEVICE_ID_SI_7013 105 #define PCI_DEVICE_ID_SI_7013 0x7013 106 #endif 107 #ifndef PCI_DEVICE_ID_NVIDIA_MCP_MODEM 108 #define PCI_DEVICE_ID_NVIDIA_MCP_MODEM 0x01c1 109 #endif 110 #ifndef PCI_DEVICE_ID_NVIDIA_MCP2_MODEM 111 #define PCI_DEVICE_ID_NVIDIA_MCP2_MODEM 0x0069 112 #endif 113 #ifndef PCI_DEVICE_ID_NVIDIA_MCP2S_MODEM 114 #define PCI_DEVICE_ID_NVIDIA_MCP2S_MODEM 0x0089 115 #endif 116 #ifndef PCI_DEVICE_ID_NVIDIA_MCP3_MODEM 117 #define PCI_DEVICE_ID_NVIDIA_MCP3_MODEM 0x00d9 118 #endif 119 120 121 enum { DEVICE_INTEL, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE }; 122 123 #define ICHREG(x) ICH_REG_##x 124 125 #define DEFINE_REGSET(name,base) \ 126 enum { \ 127 ICH_REG_##name##_BDBAR = base + 0x0, /* dword - buffer descriptor list base address */ \ 128 ICH_REG_##name##_CIV = base + 0x04, /* byte - current index value */ \ 129 ICH_REG_##name##_LVI = base + 0x05, /* byte - last valid index */ \ 130 ICH_REG_##name##_SR = base + 0x06, /* byte - status register */ \ 131 ICH_REG_##name##_PICB = base + 0x08, /* word - position in current buffer */ \ 132 ICH_REG_##name##_PIV = base + 0x0a, /* byte - prefetched index value */ \ 133 ICH_REG_##name##_CR = base + 0x0b, /* byte - control register */ \ 134 }; 135 136 /* busmaster blocks */ 137 DEFINE_REGSET(OFF, 0); /* offset */ 138 139 /* values for each busmaster block */ 140 141 /* LVI */ 142 #define ICH_REG_LVI_MASK 0x1f 143 144 /* SR */ 145 #define ICH_FIFOE 0x10 /* FIFO error */ 146 #define ICH_BCIS 0x08 /* buffer completion interrupt status */ 147 #define ICH_LVBCI 0x04 /* last valid buffer completion interrupt */ 148 #define ICH_CELV 0x02 /* current equals last valid */ 149 #define ICH_DCH 0x01 /* DMA controller halted */ 150 151 /* PIV */ 152 #define ICH_REG_PIV_MASK 0x1f /* mask */ 153 154 /* CR */ 155 #define ICH_IOCE 0x10 /* interrupt on completion enable */ 156 #define ICH_FEIE 0x08 /* fifo error interrupt enable */ 157 #define ICH_LVBIE 0x04 /* last valid buffer interrupt enable */ 158 #define ICH_RESETREGS 0x02 /* reset busmaster registers */ 159 #define ICH_STARTBM 0x01 /* start busmaster operation */ 160 161 162 /* global block */ 163 #define ICH_REG_GLOB_CNT 0x3c /* dword - global control */ 164 #define ICH_TRIE 0x00000040 /* tertiary resume interrupt enable */ 165 #define ICH_SRIE 0x00000020 /* secondary resume interrupt enable */ 166 #define ICH_PRIE 0x00000010 /* primary resume interrupt enable */ 167 #define ICH_ACLINK 0x00000008 /* AClink shut off */ 168 #define ICH_AC97WARM 0x00000004 /* AC'97 warm reset */ 169 #define ICH_AC97COLD 0x00000002 /* AC'97 cold reset */ 170 #define ICH_GIE 0x00000001 /* GPI interrupt enable */ 171 #define ICH_REG_GLOB_STA 0x40 /* dword - global status */ 172 #define ICH_TRI 0x20000000 /* ICH4: tertiary (AC_SDIN2) resume interrupt */ 173 #define ICH_TCR 0x10000000 /* ICH4: tertiary (AC_SDIN2) codec ready */ 174 #define ICH_BCS 0x08000000 /* ICH4: bit clock stopped */ 175 #define ICH_SPINT 0x04000000 /* ICH4: S/PDIF interrupt */ 176 #define ICH_P2INT 0x02000000 /* ICH4: PCM2-In interrupt */ 177 #define ICH_M2INT 0x01000000 /* ICH4: Mic2-In interrupt */ 178 #define ICH_SAMPLE_CAP 0x00c00000 /* ICH4: sample capability bits (RO) */ 179 #define ICH_MULTICHAN_CAP 0x00300000 /* ICH4: multi-channel capability bits (RO) */ 180 #define ICH_MD3 0x00020000 /* modem power down semaphore */ 181 #define ICH_AD3 0x00010000 /* audio power down semaphore */ 182 #define ICH_RCS 0x00008000 /* read completion status */ 183 #define ICH_BIT3 0x00004000 /* bit 3 slot 12 */ 184 #define ICH_BIT2 0x00002000 /* bit 2 slot 12 */ 185 #define ICH_BIT1 0x00001000 /* bit 1 slot 12 */ 186 #define ICH_SRI 0x00000800 /* secondary (AC_SDIN1) resume interrupt */ 187 #define ICH_PRI 0x00000400 /* primary (AC_SDIN0) resume interrupt */ 188 #define ICH_SCR 0x00000200 /* secondary (AC_SDIN1) codec ready */ 189 #define ICH_PCR 0x00000100 /* primary (AC_SDIN0) codec ready */ 190 #define ICH_MCINT 0x00000080 /* MIC capture interrupt */ 191 #define ICH_POINT 0x00000040 /* playback interrupt */ 192 #define ICH_PIINT 0x00000020 /* capture interrupt */ 193 #define ICH_NVSPINT 0x00000010 /* nforce spdif interrupt */ 194 #define ICH_MOINT 0x00000004 /* modem playback interrupt */ 195 #define ICH_MIINT 0x00000002 /* modem capture interrupt */ 196 #define ICH_GSCI 0x00000001 /* GPI status change interrupt */ 197 #define ICH_REG_ACC_SEMA 0x44 /* byte - codec write semaphore */ 198 #define ICH_CAS 0x01 /* codec access semaphore */ 199 200 #define ICH_MAX_FRAGS 32 /* max hw frags */ 201 202 203 /* 204 * 205 */ 206 207 enum { ICHD_MDMIN, ICHD_MDMOUT, ICHD_MDMLAST = ICHD_MDMOUT }; 208 enum { ALID_MDMIN, ALID_MDMOUT, ALID_MDMLAST = ALID_MDMOUT }; 209 210 #define get_ichdev(substream) (ichdev_t *)(substream->runtime->private_data) 211 212 typedef struct { 213 unsigned int ichd; /* ich device number */ 214 unsigned long reg_offset; /* offset to bmaddr */ 215 u32 *bdbar; /* CPU address (32bit) */ 216 unsigned int bdbar_addr; /* PCI bus address (32bit) */ 217 snd_pcm_substream_t *substream; 218 unsigned int physbuf; /* physical address (32bit) */ 219 unsigned int size; 220 unsigned int fragsize; 221 unsigned int fragsize1; 222 unsigned int position; 223 int frags; 224 int lvi; 225 int lvi_frag; 226 int civ; 227 int ack; 228 int ack_reload; 229 unsigned int ack_bit; 230 unsigned int roff_sr; 231 unsigned int roff_picb; 232 unsigned int int_sta_mask; /* interrupt status mask */ 233 unsigned int ali_slot; /* ALI DMA slot */ 234 ac97_t *ac97; 235 } ichdev_t; 236 237 typedef struct _snd_intel8x0m intel8x0_t; 238 239 struct _snd_intel8x0m { 240 unsigned int device_type; 241 242 int irq; 243 244 unsigned int mmio; 245 unsigned long addr; 246 void __iomem *remap_addr; 247 unsigned int bm_mmio; 248 unsigned long bmaddr; 249 void __iomem *remap_bmaddr; 250 251 struct pci_dev *pci; 252 snd_card_t *card; 253 254 int pcm_devs; 255 snd_pcm_t *pcm[2]; 256 ichdev_t ichd[2]; 257 258 unsigned int in_ac97_init: 1; 259 260 ac97_bus_t *ac97_bus; 261 ac97_t *ac97; 262 263 spinlock_t reg_lock; 264 265 struct snd_dma_buffer bdbars; 266 u32 bdbars_count; 267 u32 int_sta_reg; /* interrupt status register */ 268 u32 int_sta_mask; /* interrupt status mask */ 269 unsigned int pcm_pos_shift; 270 }; 271 272 static struct pci_device_id snd_intel8x0m_ids[] = { 273 { 0x8086, 0x2416, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801AA */ 274 { 0x8086, 0x2426, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82901AB */ 275 { 0x8086, 0x2446, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801BA */ 276 { 0x8086, 0x2486, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH3 */ 277 { 0x8086, 0x24c6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH4 */ 278 { 0x8086, 0x24d6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH5 */ 279 { 0x8086, 0x266d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH6 */ 280 { 0x8086, 0x27dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH7 */ 281 { 0x8086, 0x7196, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 440MX */ 282 { 0x1022, 0x7446, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD768 */ 283 { 0x1039, 0x7013, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_SIS }, /* SI7013 */ 284 { 0x10de, 0x01c1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE */ 285 { 0x10de, 0x0069, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE2 */ 286 { 0x10de, 0x0089, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE2s */ 287 { 0x10de, 0x00d9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE3 */ 288 #if 0 289 { 0x1022, 0x746d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD8111 */ 290 { 0x10b9, 0x5455, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_ALI }, /* Ali5455 */ 291 #endif 292 { 0, } 293 }; 294 295 MODULE_DEVICE_TABLE(pci, snd_intel8x0m_ids); 296 297 /* 298 * Lowlevel I/O - busmaster 299 */ 300 301 static u8 igetbyte(intel8x0_t *chip, u32 offset) 302 { 303 if (chip->bm_mmio) 304 return readb(chip->remap_bmaddr + offset); 305 else 306 return inb(chip->bmaddr + offset); 307 } 308 309 static u16 igetword(intel8x0_t *chip, u32 offset) 310 { 311 if (chip->bm_mmio) 312 return readw(chip->remap_bmaddr + offset); 313 else 314 return inw(chip->bmaddr + offset); 315 } 316 317 static u32 igetdword(intel8x0_t *chip, u32 offset) 318 { 319 if (chip->bm_mmio) 320 return readl(chip->remap_bmaddr + offset); 321 else 322 return inl(chip->bmaddr + offset); 323 } 324 325 static void iputbyte(intel8x0_t *chip, u32 offset, u8 val) 326 { 327 if (chip->bm_mmio) 328 writeb(val, chip->remap_bmaddr + offset); 329 else 330 outb(val, chip->bmaddr + offset); 331 } 332 333 static void iputword(intel8x0_t *chip, u32 offset, u16 val) 334 { 335 if (chip->bm_mmio) 336 writew(val, chip->remap_bmaddr + offset); 337 else 338 outw(val, chip->bmaddr + offset); 339 } 340 341 static void iputdword(intel8x0_t *chip, u32 offset, u32 val) 342 { 343 if (chip->bm_mmio) 344 writel(val, chip->remap_bmaddr + offset); 345 else 346 outl(val, chip->bmaddr + offset); 347 } 348 349 /* 350 * Lowlevel I/O - AC'97 registers 351 */ 352 353 static u16 iagetword(intel8x0_t *chip, u32 offset) 354 { 355 if (chip->mmio) 356 return readw(chip->remap_addr + offset); 357 else 358 return inw(chip->addr + offset); 359 } 360 361 static void iaputword(intel8x0_t *chip, u32 offset, u16 val) 362 { 363 if (chip->mmio) 364 writew(val, chip->remap_addr + offset); 365 else 366 outw(val, chip->addr + offset); 367 } 368 369 /* 370 * Basic I/O 371 */ 372 373 /* 374 * access to AC97 codec via normal i/o (for ICH and SIS7013) 375 */ 376 377 /* return the GLOB_STA bit for the corresponding codec */ 378 static unsigned int get_ich_codec_bit(intel8x0_t *chip, unsigned int codec) 379 { 380 static unsigned int codec_bit[3] = { 381 ICH_PCR, ICH_SCR, ICH_TCR 382 }; 383 snd_assert(codec < 3, return ICH_PCR); 384 return codec_bit[codec]; 385 } 386 387 static int snd_intel8x0m_codec_semaphore(intel8x0_t *chip, unsigned int codec) 388 { 389 int time; 390 391 if (codec > 1) 392 return -EIO; 393 codec = get_ich_codec_bit(chip, codec); 394 395 /* codec ready ? */ 396 if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0) 397 return -EIO; 398 399 /* Anyone holding a semaphore for 1 msec should be shot... */ 400 time = 100; 401 do { 402 if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS)) 403 return 0; 404 udelay(10); 405 } while (time--); 406 407 /* access to some forbidden (non existant) ac97 registers will not 408 * reset the semaphore. So even if you don't get the semaphore, still 409 * continue the access. We don't need the semaphore anyway. */ 410 snd_printk("codec_semaphore: semaphore is not ready [0x%x][0x%x]\n", 411 igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA))); 412 iagetword(chip, 0); /* clear semaphore flag */ 413 /* I don't care about the semaphore */ 414 return -EBUSY; 415 } 416 417 static void snd_intel8x0_codec_write(ac97_t *ac97, 418 unsigned short reg, 419 unsigned short val) 420 { 421 intel8x0_t *chip = ac97->private_data; 422 423 if (snd_intel8x0m_codec_semaphore(chip, ac97->num) < 0) { 424 if (! chip->in_ac97_init) 425 snd_printk("codec_write %d: semaphore is not ready for register 0x%x\n", ac97->num, reg); 426 } 427 iaputword(chip, reg + ac97->num * 0x80, val); 428 } 429 430 static unsigned short snd_intel8x0_codec_read(ac97_t *ac97, 431 unsigned short reg) 432 { 433 intel8x0_t *chip = ac97->private_data; 434 unsigned short res; 435 unsigned int tmp; 436 437 if (snd_intel8x0m_codec_semaphore(chip, ac97->num) < 0) { 438 if (! chip->in_ac97_init) 439 snd_printk("codec_read %d: semaphore is not ready for register 0x%x\n", ac97->num, reg); 440 res = 0xffff; 441 } else { 442 res = iagetword(chip, reg + ac97->num * 0x80); 443 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) { 444 /* reset RCS and preserve other R/WC bits */ 445 iputdword(chip, ICHREG(GLOB_STA), tmp & ~(ICH_SRI|ICH_PRI|ICH_TRI|ICH_GSCI)); 446 if (! chip->in_ac97_init) 447 snd_printk("codec_read %d: read timeout for register 0x%x\n", ac97->num, reg); 448 res = 0xffff; 449 } 450 } 451 if (reg == AC97_GPIO_STATUS) 452 iagetword(chip, 0); /* clear semaphore */ 453 return res; 454 } 455 456 457 /* 458 * DMA I/O 459 */ 460 static void snd_intel8x0_setup_periods(intel8x0_t *chip, ichdev_t *ichdev) 461 { 462 int idx; 463 u32 *bdbar = ichdev->bdbar; 464 unsigned long port = ichdev->reg_offset; 465 466 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr); 467 if (ichdev->size == ichdev->fragsize) { 468 ichdev->ack_reload = ichdev->ack = 2; 469 ichdev->fragsize1 = ichdev->fragsize >> 1; 470 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) { 471 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf); 472 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */ 473 ichdev->fragsize1 >> chip->pcm_pos_shift); 474 bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1)); 475 bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */ 476 ichdev->fragsize1 >> chip->pcm_pos_shift); 477 } 478 ichdev->frags = 2; 479 } else { 480 ichdev->ack_reload = ichdev->ack = 1; 481 ichdev->fragsize1 = ichdev->fragsize; 482 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) { 483 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf + (((idx >> 1) * ichdev->fragsize) % ichdev->size)); 484 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */ 485 ichdev->fragsize >> chip->pcm_pos_shift); 486 // printk("bdbar[%i] = 0x%x [0x%x]\n", idx + 0, bdbar[idx + 0], bdbar[idx + 1]); 487 } 488 ichdev->frags = ichdev->size / ichdev->fragsize; 489 } 490 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK); 491 ichdev->civ = 0; 492 iputbyte(chip, port + ICH_REG_OFF_CIV, 0); 493 ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags; 494 ichdev->position = 0; 495 #if 0 496 printk("lvi_frag = %i, frags = %i, period_size = 0x%x, period_size1 = 0x%x\n", 497 ichdev->lvi_frag, ichdev->frags, ichdev->fragsize, ichdev->fragsize1); 498 #endif 499 /* clear interrupts */ 500 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI); 501 } 502 503 /* 504 * Interrupt handler 505 */ 506 507 static inline void snd_intel8x0_update(intel8x0_t *chip, ichdev_t *ichdev) 508 { 509 unsigned long port = ichdev->reg_offset; 510 int civ, i, step; 511 int ack = 0; 512 513 civ = igetbyte(chip, port + ICH_REG_OFF_CIV); 514 if (civ == ichdev->civ) { 515 // snd_printd("civ same %d\n", civ); 516 step = 1; 517 ichdev->civ++; 518 ichdev->civ &= ICH_REG_LVI_MASK; 519 } else { 520 step = civ - ichdev->civ; 521 if (step < 0) 522 step += ICH_REG_LVI_MASK + 1; 523 // if (step != 1) 524 // snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ); 525 ichdev->civ = civ; 526 } 527 528 ichdev->position += step * ichdev->fragsize1; 529 ichdev->position %= ichdev->size; 530 ichdev->lvi += step; 531 ichdev->lvi &= ICH_REG_LVI_MASK; 532 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi); 533 for (i = 0; i < step; i++) { 534 ichdev->lvi_frag++; 535 ichdev->lvi_frag %= ichdev->frags; 536 ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + ichdev->lvi_frag * ichdev->fragsize1); 537 // printk("new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, all = 0x%x, 0x%x\n", ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2], ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port), inl(port + 4), inb(port + ICH_REG_OFF_CR)); 538 if (--ichdev->ack == 0) { 539 ichdev->ack = ichdev->ack_reload; 540 ack = 1; 541 } 542 } 543 if (ack && ichdev->substream) { 544 spin_unlock(&chip->reg_lock); 545 snd_pcm_period_elapsed(ichdev->substream); 546 spin_lock(&chip->reg_lock); 547 } 548 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI); 549 } 550 551 static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id, struct pt_regs *regs) 552 { 553 intel8x0_t *chip = dev_id; 554 ichdev_t *ichdev; 555 unsigned int status; 556 unsigned int i; 557 558 spin_lock(&chip->reg_lock); 559 status = igetdword(chip, chip->int_sta_reg); 560 if (status == 0xffffffff) { /* we are not yet resumed */ 561 spin_unlock(&chip->reg_lock); 562 return IRQ_NONE; 563 } 564 if ((status & chip->int_sta_mask) == 0) { 565 if (status) 566 iputdword(chip, chip->int_sta_reg, status); 567 spin_unlock(&chip->reg_lock); 568 return IRQ_NONE; 569 } 570 571 for (i = 0; i < chip->bdbars_count; i++) { 572 ichdev = &chip->ichd[i]; 573 if (status & ichdev->int_sta_mask) 574 snd_intel8x0_update(chip, ichdev); 575 } 576 577 /* ack them */ 578 iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask); 579 spin_unlock(&chip->reg_lock); 580 581 return IRQ_HANDLED; 582 } 583 584 /* 585 * PCM part 586 */ 587 588 static int snd_intel8x0_pcm_trigger(snd_pcm_substream_t *substream, int cmd) 589 { 590 intel8x0_t *chip = snd_pcm_substream_chip(substream); 591 ichdev_t *ichdev = get_ichdev(substream); 592 unsigned char val = 0; 593 unsigned long port = ichdev->reg_offset; 594 595 switch (cmd) { 596 case SNDRV_PCM_TRIGGER_START: 597 case SNDRV_PCM_TRIGGER_RESUME: 598 val = ICH_IOCE | ICH_STARTBM; 599 break; 600 case SNDRV_PCM_TRIGGER_STOP: 601 case SNDRV_PCM_TRIGGER_SUSPEND: 602 val = 0; 603 break; 604 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 605 val = ICH_IOCE; 606 break; 607 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 608 val = ICH_IOCE | ICH_STARTBM; 609 break; 610 default: 611 return -EINVAL; 612 } 613 iputbyte(chip, port + ICH_REG_OFF_CR, val); 614 if (cmd == SNDRV_PCM_TRIGGER_STOP) { 615 /* wait until DMA stopped */ 616 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ; 617 /* reset whole DMA things */ 618 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS); 619 } 620 return 0; 621 } 622 623 static int snd_intel8x0_hw_params(snd_pcm_substream_t * substream, 624 snd_pcm_hw_params_t * hw_params) 625 { 626 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params)); 627 } 628 629 static int snd_intel8x0_hw_free(snd_pcm_substream_t * substream) 630 { 631 return snd_pcm_lib_free_pages(substream); 632 } 633 634 static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(snd_pcm_substream_t * substream) 635 { 636 intel8x0_t *chip = snd_pcm_substream_chip(substream); 637 ichdev_t *ichdev = get_ichdev(substream); 638 size_t ptr1, ptr; 639 640 ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb) << chip->pcm_pos_shift; 641 if (ptr1 != 0) 642 ptr = ichdev->fragsize1 - ptr1; 643 else 644 ptr = 0; 645 ptr += ichdev->position; 646 if (ptr >= ichdev->size) 647 return 0; 648 return bytes_to_frames(substream->runtime, ptr); 649 } 650 651 static int snd_intel8x0m_pcm_prepare(snd_pcm_substream_t * substream) 652 { 653 intel8x0_t *chip = snd_pcm_substream_chip(substream); 654 snd_pcm_runtime_t *runtime = substream->runtime; 655 ichdev_t *ichdev = get_ichdev(substream); 656 657 ichdev->physbuf = runtime->dma_addr; 658 ichdev->size = snd_pcm_lib_buffer_bytes(substream); 659 ichdev->fragsize = snd_pcm_lib_period_bytes(substream); 660 snd_ac97_write(ichdev->ac97, AC97_LINE1_RATE, runtime->rate); 661 snd_ac97_write(ichdev->ac97, AC97_LINE1_LEVEL, 0); 662 snd_intel8x0_setup_periods(chip, ichdev); 663 return 0; 664 } 665 666 static snd_pcm_hardware_t snd_intel8x0m_stream = 667 { 668 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 669 SNDRV_PCM_INFO_BLOCK_TRANSFER | 670 SNDRV_PCM_INFO_MMAP_VALID | 671 SNDRV_PCM_INFO_PAUSE | 672 SNDRV_PCM_INFO_RESUME), 673 .formats = SNDRV_PCM_FMTBIT_S16_LE, 674 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_KNOT, 675 .rate_min = 8000, 676 .rate_max = 16000, 677 .channels_min = 1, 678 .channels_max = 1, 679 .buffer_bytes_max = 64 * 1024, 680 .period_bytes_min = 32, 681 .period_bytes_max = 64 * 1024, 682 .periods_min = 1, 683 .periods_max = 1024, 684 .fifo_size = 0, 685 }; 686 687 688 static int snd_intel8x0m_pcm_open(snd_pcm_substream_t * substream, ichdev_t *ichdev) 689 { 690 static unsigned int rates[] = { 8000, 9600, 12000, 16000 }; 691 static snd_pcm_hw_constraint_list_t hw_constraints_rates = { 692 .count = ARRAY_SIZE(rates), 693 .list = rates, 694 .mask = 0, 695 }; 696 snd_pcm_runtime_t *runtime = substream->runtime; 697 int err; 698 699 ichdev->substream = substream; 700 runtime->hw = snd_intel8x0m_stream; 701 err = snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates); 702 if ( err < 0 ) 703 return err; 704 runtime->private_data = ichdev; 705 return 0; 706 } 707 708 static int snd_intel8x0m_playback_open(snd_pcm_substream_t * substream) 709 { 710 intel8x0_t *chip = snd_pcm_substream_chip(substream); 711 712 return snd_intel8x0m_pcm_open(substream, &chip->ichd[ICHD_MDMOUT]); 713 } 714 715 static int snd_intel8x0m_playback_close(snd_pcm_substream_t * substream) 716 { 717 intel8x0_t *chip = snd_pcm_substream_chip(substream); 718 719 chip->ichd[ICHD_MDMOUT].substream = NULL; 720 return 0; 721 } 722 723 static int snd_intel8x0m_capture_open(snd_pcm_substream_t * substream) 724 { 725 intel8x0_t *chip = snd_pcm_substream_chip(substream); 726 727 return snd_intel8x0m_pcm_open(substream, &chip->ichd[ICHD_MDMIN]); 728 } 729 730 static int snd_intel8x0m_capture_close(snd_pcm_substream_t * substream) 731 { 732 intel8x0_t *chip = snd_pcm_substream_chip(substream); 733 734 chip->ichd[ICHD_MDMIN].substream = NULL; 735 return 0; 736 } 737 738 739 static snd_pcm_ops_t snd_intel8x0m_playback_ops = { 740 .open = snd_intel8x0m_playback_open, 741 .close = snd_intel8x0m_playback_close, 742 .ioctl = snd_pcm_lib_ioctl, 743 .hw_params = snd_intel8x0_hw_params, 744 .hw_free = snd_intel8x0_hw_free, 745 .prepare = snd_intel8x0m_pcm_prepare, 746 .trigger = snd_intel8x0_pcm_trigger, 747 .pointer = snd_intel8x0_pcm_pointer, 748 }; 749 750 static snd_pcm_ops_t snd_intel8x0m_capture_ops = { 751 .open = snd_intel8x0m_capture_open, 752 .close = snd_intel8x0m_capture_close, 753 .ioctl = snd_pcm_lib_ioctl, 754 .hw_params = snd_intel8x0_hw_params, 755 .hw_free = snd_intel8x0_hw_free, 756 .prepare = snd_intel8x0m_pcm_prepare, 757 .trigger = snd_intel8x0_pcm_trigger, 758 .pointer = snd_intel8x0_pcm_pointer, 759 }; 760 761 762 struct ich_pcm_table { 763 char *suffix; 764 snd_pcm_ops_t *playback_ops; 765 snd_pcm_ops_t *capture_ops; 766 size_t prealloc_size; 767 size_t prealloc_max_size; 768 int ac97_idx; 769 }; 770 771 static int __devinit snd_intel8x0_pcm1(intel8x0_t *chip, int device, struct ich_pcm_table *rec) 772 { 773 snd_pcm_t *pcm; 774 int err; 775 char name[32]; 776 777 if (rec->suffix) 778 sprintf(name, "Intel ICH - %s", rec->suffix); 779 else 780 strcpy(name, "Intel ICH"); 781 err = snd_pcm_new(chip->card, name, device, 782 rec->playback_ops ? 1 : 0, 783 rec->capture_ops ? 1 : 0, &pcm); 784 if (err < 0) 785 return err; 786 787 if (rec->playback_ops) 788 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops); 789 if (rec->capture_ops) 790 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops); 791 792 pcm->private_data = chip; 793 pcm->info_flags = 0; 794 if (rec->suffix) 795 sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix); 796 else 797 strcpy(pcm->name, chip->card->shortname); 798 chip->pcm[device] = pcm; 799 800 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 801 snd_dma_pci_data(chip->pci), 802 rec->prealloc_size, 803 rec->prealloc_max_size); 804 805 return 0; 806 } 807 808 static struct ich_pcm_table intel_pcms[] __devinitdata = { 809 { 810 .suffix = "Modem", 811 .playback_ops = &snd_intel8x0m_playback_ops, 812 .capture_ops = &snd_intel8x0m_capture_ops, 813 .prealloc_size = 32 * 1024, 814 .prealloc_max_size = 64 * 1024, 815 }, 816 }; 817 818 static int __devinit snd_intel8x0_pcm(intel8x0_t *chip) 819 { 820 int i, tblsize, device, err; 821 struct ich_pcm_table *tbl, *rec; 822 823 #if 1 824 tbl = intel_pcms; 825 tblsize = 1; 826 #else 827 switch (chip->device_type) { 828 case DEVICE_NFORCE: 829 tbl = nforce_pcms; 830 tblsize = ARRAY_SIZE(nforce_pcms); 831 break; 832 case DEVICE_ALI: 833 tbl = ali_pcms; 834 tblsize = ARRAY_SIZE(ali_pcms); 835 break; 836 default: 837 tbl = intel_pcms; 838 tblsize = 2; 839 break; 840 } 841 #endif 842 device = 0; 843 for (i = 0; i < tblsize; i++) { 844 rec = tbl + i; 845 if (i > 0 && rec->ac97_idx) { 846 /* activate PCM only when associated AC'97 codec */ 847 if (! chip->ichd[rec->ac97_idx].ac97) 848 continue; 849 } 850 err = snd_intel8x0_pcm1(chip, device, rec); 851 if (err < 0) 852 return err; 853 device++; 854 } 855 856 chip->pcm_devs = device; 857 return 0; 858 } 859 860 861 /* 862 * Mixer part 863 */ 864 865 static void snd_intel8x0_mixer_free_ac97_bus(ac97_bus_t *bus) 866 { 867 intel8x0_t *chip = bus->private_data; 868 chip->ac97_bus = NULL; 869 } 870 871 static void snd_intel8x0_mixer_free_ac97(ac97_t *ac97) 872 { 873 intel8x0_t *chip = ac97->private_data; 874 chip->ac97 = NULL; 875 } 876 877 878 static int __devinit snd_intel8x0_mixer(intel8x0_t *chip, int ac97_clock) 879 { 880 ac97_bus_t *pbus; 881 ac97_template_t ac97; 882 ac97_t *x97; 883 int err; 884 unsigned int glob_sta = 0; 885 static ac97_bus_ops_t ops = { 886 .write = snd_intel8x0_codec_write, 887 .read = snd_intel8x0_codec_read, 888 }; 889 890 chip->in_ac97_init = 1; 891 892 memset(&ac97, 0, sizeof(ac97)); 893 ac97.private_data = chip; 894 ac97.private_free = snd_intel8x0_mixer_free_ac97; 895 ac97.scaps = AC97_SCAP_SKIP_AUDIO; 896 897 glob_sta = igetdword(chip, ICHREG(GLOB_STA)); 898 899 if ((err = snd_ac97_bus(chip->card, 0, &ops, chip, &pbus)) < 0) 900 goto __err; 901 pbus->private_free = snd_intel8x0_mixer_free_ac97_bus; 902 pbus->shared_type = AC97_SHARED_TYPE_ICH; /* shared with audio driver */ 903 if (ac97_clock >= 8000 && ac97_clock <= 48000) 904 pbus->clock = ac97_clock; 905 chip->ac97_bus = pbus; 906 907 ac97.pci = chip->pci; 908 ac97.num = glob_sta & ICH_SCR ? 1 : 0; 909 if ((err = snd_ac97_mixer(pbus, &ac97, &x97)) < 0) { 910 snd_printk(KERN_ERR "Unable to initialize codec #%d\n", ac97.num); 911 if (ac97.num == 0) 912 goto __err; 913 return err; 914 } 915 chip->ac97 = x97; 916 if(ac97_is_modem(x97) && !chip->ichd[ICHD_MDMIN].ac97) { 917 chip->ichd[ICHD_MDMIN].ac97 = x97; 918 chip->ichd[ICHD_MDMOUT].ac97 = x97; 919 } 920 921 chip->in_ac97_init = 0; 922 return 0; 923 924 __err: 925 /* clear the cold-reset bit for the next chance */ 926 if (chip->device_type != DEVICE_ALI) 927 iputdword(chip, ICHREG(GLOB_CNT), igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD); 928 return err; 929 } 930 931 932 /* 933 * 934 */ 935 936 #define do_delay(chip) do {\ 937 set_current_state(TASK_UNINTERRUPTIBLE);\ 938 schedule_timeout(1);\ 939 } while (0) 940 941 static int snd_intel8x0m_ich_chip_init(intel8x0_t *chip, int probing) 942 { 943 unsigned long end_time; 944 unsigned int cnt, status, nstatus; 945 946 /* put logic to right state */ 947 /* first clear status bits */ 948 status = ICH_RCS | ICH_MIINT | ICH_MOINT; 949 cnt = igetdword(chip, ICHREG(GLOB_STA)); 950 iputdword(chip, ICHREG(GLOB_STA), cnt & status); 951 952 /* ACLink on, 2 channels */ 953 cnt = igetdword(chip, ICHREG(GLOB_CNT)); 954 cnt &= ~(ICH_ACLINK); 955 /* finish cold or do warm reset */ 956 cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM; 957 iputdword(chip, ICHREG(GLOB_CNT), cnt); 958 end_time = (jiffies + (HZ / 4)) + 1; 959 do { 960 if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0) 961 goto __ok; 962 do_delay(chip); 963 } while (time_after_eq(end_time, jiffies)); 964 snd_printk("AC'97 warm reset still in progress? [0x%x]\n", igetdword(chip, ICHREG(GLOB_CNT))); 965 return -EIO; 966 967 __ok: 968 if (probing) { 969 /* wait for any codec ready status. 970 * Once it becomes ready it should remain ready 971 * as long as we do not disable the ac97 link. 972 */ 973 end_time = jiffies + HZ; 974 do { 975 status = igetdword(chip, ICHREG(GLOB_STA)) & (ICH_PCR | ICH_SCR | ICH_TCR); 976 if (status) 977 break; 978 do_delay(chip); 979 } while (time_after_eq(end_time, jiffies)); 980 if (! status) { 981 /* no codec is found */ 982 snd_printk(KERN_ERR "codec_ready: codec is not ready [0x%x]\n", igetdword(chip, ICHREG(GLOB_STA))); 983 return -EIO; 984 } 985 986 /* up to two codecs (modem cannot be tertiary with ICH4) */ 987 nstatus = ICH_PCR | ICH_SCR; 988 989 /* wait for other codecs ready status. */ 990 end_time = jiffies + HZ / 4; 991 while (status != nstatus && time_after_eq(end_time, jiffies)) { 992 do_delay(chip); 993 status |= igetdword(chip, ICHREG(GLOB_STA)) & nstatus; 994 } 995 996 } else { 997 /* resume phase */ 998 status = 0; 999 if (chip->ac97) 1000 status |= get_ich_codec_bit(chip, chip->ac97->num); 1001 /* wait until all the probed codecs are ready */ 1002 end_time = jiffies + HZ; 1003 do { 1004 nstatus = igetdword(chip, ICHREG(GLOB_STA)) & (ICH_PCR | ICH_SCR | ICH_TCR); 1005 if (status == nstatus) 1006 break; 1007 do_delay(chip); 1008 } while (time_after_eq(end_time, jiffies)); 1009 } 1010 1011 if (chip->device_type == DEVICE_SIS) { 1012 /* unmute the output on SIS7012 */ 1013 iputword(chip, 0x4c, igetword(chip, 0x4c) | 1); 1014 } 1015 1016 return 0; 1017 } 1018 1019 static int snd_intel8x0_chip_init(intel8x0_t *chip, int probing) 1020 { 1021 unsigned int i; 1022 int err; 1023 1024 if ((err = snd_intel8x0m_ich_chip_init(chip, probing)) < 0) 1025 return err; 1026 iagetword(chip, 0); /* clear semaphore flag */ 1027 1028 /* disable interrupts */ 1029 for (i = 0; i < chip->bdbars_count; i++) 1030 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00); 1031 /* reset channels */ 1032 for (i = 0; i < chip->bdbars_count; i++) 1033 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS); 1034 /* initialize Buffer Descriptor Lists */ 1035 for (i = 0; i < chip->bdbars_count; i++) 1036 iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset, chip->ichd[i].bdbar_addr); 1037 return 0; 1038 } 1039 1040 static int snd_intel8x0_free(intel8x0_t *chip) 1041 { 1042 unsigned int i; 1043 1044 if (chip->irq < 0) 1045 goto __hw_end; 1046 /* disable interrupts */ 1047 for (i = 0; i < chip->bdbars_count; i++) 1048 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00); 1049 /* reset channels */ 1050 for (i = 0; i < chip->bdbars_count; i++) 1051 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS); 1052 /* --- */ 1053 synchronize_irq(chip->irq); 1054 __hw_end: 1055 if (chip->bdbars.area) 1056 snd_dma_free_pages(&chip->bdbars); 1057 if (chip->remap_addr) 1058 iounmap(chip->remap_addr); 1059 if (chip->remap_bmaddr) 1060 iounmap(chip->remap_bmaddr); 1061 if (chip->irq >= 0) 1062 free_irq(chip->irq, (void *)chip); 1063 pci_release_regions(chip->pci); 1064 pci_disable_device(chip->pci); 1065 kfree(chip); 1066 return 0; 1067 } 1068 1069 #ifdef CONFIG_PM 1070 /* 1071 * power management 1072 */ 1073 static int intel8x0m_suspend(snd_card_t *card, pm_message_t state) 1074 { 1075 intel8x0_t *chip = card->pm_private_data; 1076 int i; 1077 1078 for (i = 0; i < chip->pcm_devs; i++) 1079 snd_pcm_suspend_all(chip->pcm[i]); 1080 if (chip->ac97) 1081 snd_ac97_suspend(chip->ac97); 1082 pci_disable_device(chip->pci); 1083 return 0; 1084 } 1085 1086 static int intel8x0m_resume(snd_card_t *card) 1087 { 1088 intel8x0_t *chip = card->pm_private_data; 1089 pci_enable_device(chip->pci); 1090 pci_set_master(chip->pci); 1091 snd_intel8x0_chip_init(chip, 0); 1092 if (chip->ac97) 1093 snd_ac97_resume(chip->ac97); 1094 1095 return 0; 1096 } 1097 #endif /* CONFIG_PM */ 1098 1099 static void snd_intel8x0m_proc_read(snd_info_entry_t * entry, 1100 snd_info_buffer_t * buffer) 1101 { 1102 intel8x0_t *chip = entry->private_data; 1103 unsigned int tmp; 1104 1105 snd_iprintf(buffer, "Intel8x0m\n\n"); 1106 if (chip->device_type == DEVICE_ALI) 1107 return; 1108 tmp = igetdword(chip, ICHREG(GLOB_STA)); 1109 snd_iprintf(buffer, "Global control : 0x%08x\n", igetdword(chip, ICHREG(GLOB_CNT))); 1110 snd_iprintf(buffer, "Global status : 0x%08x\n", tmp); 1111 snd_iprintf(buffer, "AC'97 codecs ready :%s%s%s%s\n", 1112 tmp & ICH_PCR ? " primary" : "", 1113 tmp & ICH_SCR ? " secondary" : "", 1114 tmp & ICH_TCR ? " tertiary" : "", 1115 (tmp & (ICH_PCR | ICH_SCR | ICH_TCR)) == 0 ? " none" : ""); 1116 } 1117 1118 static void __devinit snd_intel8x0m_proc_init(intel8x0_t * chip) 1119 { 1120 snd_info_entry_t *entry; 1121 1122 if (! snd_card_proc_new(chip->card, "intel8x0m", &entry)) 1123 snd_info_set_text_ops(entry, chip, 1024, snd_intel8x0m_proc_read); 1124 } 1125 1126 static int snd_intel8x0_dev_free(snd_device_t *device) 1127 { 1128 intel8x0_t *chip = device->device_data; 1129 return snd_intel8x0_free(chip); 1130 } 1131 1132 struct ich_reg_info { 1133 unsigned int int_sta_mask; 1134 unsigned int offset; 1135 }; 1136 1137 static int __devinit snd_intel8x0m_create(snd_card_t * card, 1138 struct pci_dev *pci, 1139 unsigned long device_type, 1140 intel8x0_t ** r_intel8x0) 1141 { 1142 intel8x0_t *chip; 1143 int err; 1144 unsigned int i; 1145 unsigned int int_sta_masks; 1146 ichdev_t *ichdev; 1147 static snd_device_ops_t ops = { 1148 .dev_free = snd_intel8x0_dev_free, 1149 }; 1150 static struct ich_reg_info intel_regs[2] = { 1151 { ICH_MIINT, 0 }, 1152 { ICH_MOINT, 0x10 }, 1153 }; 1154 struct ich_reg_info *tbl; 1155 1156 *r_intel8x0 = NULL; 1157 1158 if ((err = pci_enable_device(pci)) < 0) 1159 return err; 1160 1161 chip = kcalloc(1, sizeof(*chip), GFP_KERNEL); 1162 if (chip == NULL) { 1163 pci_disable_device(pci); 1164 return -ENOMEM; 1165 } 1166 spin_lock_init(&chip->reg_lock); 1167 chip->device_type = device_type; 1168 chip->card = card; 1169 chip->pci = pci; 1170 chip->irq = -1; 1171 1172 if ((err = pci_request_regions(pci, card->shortname)) < 0) { 1173 kfree(chip); 1174 pci_disable_device(pci); 1175 return err; 1176 } 1177 1178 if (device_type == DEVICE_ALI) { 1179 /* ALI5455 has no ac97 region */ 1180 chip->bmaddr = pci_resource_start(pci, 0); 1181 goto port_inited; 1182 } 1183 1184 if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) { /* ICH4 and Nforce */ 1185 chip->mmio = 1; 1186 chip->addr = pci_resource_start(pci, 2); 1187 chip->remap_addr = ioremap_nocache(chip->addr, 1188 pci_resource_len(pci, 2)); 1189 if (chip->remap_addr == NULL) { 1190 snd_printk("AC'97 space ioremap problem\n"); 1191 snd_intel8x0_free(chip); 1192 return -EIO; 1193 } 1194 } else { 1195 chip->addr = pci_resource_start(pci, 0); 1196 } 1197 if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) { /* ICH4 */ 1198 chip->bm_mmio = 1; 1199 chip->bmaddr = pci_resource_start(pci, 3); 1200 chip->remap_bmaddr = ioremap_nocache(chip->bmaddr, 1201 pci_resource_len(pci, 3)); 1202 if (chip->remap_bmaddr == NULL) { 1203 snd_printk("Controller space ioremap problem\n"); 1204 snd_intel8x0_free(chip); 1205 return -EIO; 1206 } 1207 } else { 1208 chip->bmaddr = pci_resource_start(pci, 1); 1209 } 1210 1211 port_inited: 1212 if (request_irq(pci->irq, snd_intel8x0_interrupt, SA_INTERRUPT|SA_SHIRQ, card->shortname, (void *)chip)) { 1213 snd_printk("unable to grab IRQ %d\n", pci->irq); 1214 snd_intel8x0_free(chip); 1215 return -EBUSY; 1216 } 1217 chip->irq = pci->irq; 1218 pci_set_master(pci); 1219 synchronize_irq(chip->irq); 1220 1221 /* initialize offsets */ 1222 chip->bdbars_count = 2; 1223 tbl = intel_regs; 1224 1225 for (i = 0; i < chip->bdbars_count; i++) { 1226 ichdev = &chip->ichd[i]; 1227 ichdev->ichd = i; 1228 ichdev->reg_offset = tbl[i].offset; 1229 ichdev->int_sta_mask = tbl[i].int_sta_mask; 1230 if (device_type == DEVICE_SIS) { 1231 /* SiS 7013 swaps the registers */ 1232 ichdev->roff_sr = ICH_REG_OFF_PICB; 1233 ichdev->roff_picb = ICH_REG_OFF_SR; 1234 } else { 1235 ichdev->roff_sr = ICH_REG_OFF_SR; 1236 ichdev->roff_picb = ICH_REG_OFF_PICB; 1237 } 1238 if (device_type == DEVICE_ALI) 1239 ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10; 1240 } 1241 /* SIS7013 handles the pcm data in bytes, others are in words */ 1242 chip->pcm_pos_shift = (device_type == DEVICE_SIS) ? 0 : 1; 1243 1244 /* allocate buffer descriptor lists */ 1245 /* the start of each lists must be aligned to 8 bytes */ 1246 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci), 1247 chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2, 1248 &chip->bdbars) < 0) { 1249 snd_intel8x0_free(chip); 1250 return -ENOMEM; 1251 } 1252 /* tables must be aligned to 8 bytes here, but the kernel pages 1253 are much bigger, so we don't care (on i386) */ 1254 int_sta_masks = 0; 1255 for (i = 0; i < chip->bdbars_count; i++) { 1256 ichdev = &chip->ichd[i]; 1257 ichdev->bdbar = ((u32 *)chip->bdbars.area) + (i * ICH_MAX_FRAGS * 2); 1258 ichdev->bdbar_addr = chip->bdbars.addr + (i * sizeof(u32) * ICH_MAX_FRAGS * 2); 1259 int_sta_masks |= ichdev->int_sta_mask; 1260 } 1261 chip->int_sta_reg = ICH_REG_GLOB_STA; 1262 chip->int_sta_mask = int_sta_masks; 1263 1264 if ((err = snd_intel8x0_chip_init(chip, 1)) < 0) { 1265 snd_intel8x0_free(chip); 1266 return err; 1267 } 1268 1269 snd_card_set_pm_callback(card, intel8x0m_suspend, intel8x0m_resume, chip); 1270 1271 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) { 1272 snd_intel8x0_free(chip); 1273 return err; 1274 } 1275 1276 snd_card_set_dev(card, &pci->dev); 1277 1278 *r_intel8x0 = chip; 1279 return 0; 1280 } 1281 1282 static struct shortname_table { 1283 unsigned int id; 1284 const char *s; 1285 } shortnames[] __devinitdata = { 1286 { PCI_DEVICE_ID_INTEL_82801_6, "Intel 82801AA-ICH" }, 1287 { PCI_DEVICE_ID_INTEL_82901_6, "Intel 82901AB-ICH0" }, 1288 { PCI_DEVICE_ID_INTEL_82801BA_6, "Intel 82801BA-ICH2" }, 1289 { PCI_DEVICE_ID_INTEL_440MX_6, "Intel 440MX" }, 1290 { PCI_DEVICE_ID_INTEL_ICH3_6, "Intel 82801CA-ICH3" }, 1291 { PCI_DEVICE_ID_INTEL_ICH4_6, "Intel 82801DB-ICH4" }, 1292 { PCI_DEVICE_ID_INTEL_ICH5_6, "Intel ICH5" }, 1293 { PCI_DEVICE_ID_INTEL_ICH6_6, "Intel ICH6" }, 1294 { PCI_DEVICE_ID_INTEL_ICH7_6, "Intel ICH7" }, 1295 { 0x7446, "AMD AMD768" }, 1296 { PCI_DEVICE_ID_SI_7013, "SiS SI7013" }, 1297 { PCI_DEVICE_ID_NVIDIA_MCP_MODEM, "NVidia nForce" }, 1298 { PCI_DEVICE_ID_NVIDIA_MCP2_MODEM, "NVidia nForce2" }, 1299 { PCI_DEVICE_ID_NVIDIA_MCP2S_MODEM, "NVidia nForce2s" }, 1300 { PCI_DEVICE_ID_NVIDIA_MCP3_MODEM, "NVidia nForce3" }, 1301 #if 0 1302 { 0x5455, "ALi M5455" }, 1303 { 0x746d, "AMD AMD8111" }, 1304 #endif 1305 { 0 }, 1306 }; 1307 1308 static int __devinit snd_intel8x0m_probe(struct pci_dev *pci, 1309 const struct pci_device_id *pci_id) 1310 { 1311 static int dev; 1312 snd_card_t *card; 1313 intel8x0_t *chip; 1314 int err; 1315 struct shortname_table *name; 1316 1317 if (dev >= SNDRV_CARDS) 1318 return -ENODEV; 1319 if (!enable[dev]) { 1320 dev++; 1321 return -ENOENT; 1322 } 1323 1324 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0); 1325 if (card == NULL) 1326 return -ENOMEM; 1327 1328 strcpy(card->driver, "ICH-MODEM"); 1329 strcpy(card->shortname, "Intel ICH"); 1330 for (name = shortnames; name->id; name++) { 1331 if (pci->device == name->id) { 1332 strcpy(card->shortname, name->s); 1333 break; 1334 } 1335 } 1336 strcat(card->shortname," Modem"); 1337 1338 if ((err = snd_intel8x0m_create(card, pci, pci_id->driver_data, &chip)) < 0) { 1339 snd_card_free(card); 1340 return err; 1341 } 1342 1343 if ((err = snd_intel8x0_mixer(chip, ac97_clock[dev])) < 0) { 1344 snd_card_free(card); 1345 return err; 1346 } 1347 if ((err = snd_intel8x0_pcm(chip)) < 0) { 1348 snd_card_free(card); 1349 return err; 1350 } 1351 1352 snd_intel8x0m_proc_init(chip); 1353 1354 sprintf(card->longname, "%s at 0x%lx, irq %i", 1355 card->shortname, chip->addr, chip->irq); 1356 1357 if ((err = snd_card_register(card)) < 0) { 1358 snd_card_free(card); 1359 return err; 1360 } 1361 pci_set_drvdata(pci, card); 1362 dev++; 1363 return 0; 1364 } 1365 1366 static void __devexit snd_intel8x0m_remove(struct pci_dev *pci) 1367 { 1368 snd_card_free(pci_get_drvdata(pci)); 1369 pci_set_drvdata(pci, NULL); 1370 } 1371 1372 static struct pci_driver driver = { 1373 .name = "Intel ICH Modem", 1374 .id_table = snd_intel8x0m_ids, 1375 .probe = snd_intel8x0m_probe, 1376 .remove = __devexit_p(snd_intel8x0m_remove), 1377 SND_PCI_PM_CALLBACKS 1378 }; 1379 1380 1381 static int __init alsa_card_intel8x0m_init(void) 1382 { 1383 return pci_register_driver(&driver); 1384 } 1385 1386 static void __exit alsa_card_intel8x0m_exit(void) 1387 { 1388 pci_unregister_driver(&driver); 1389 } 1390 1391 module_init(alsa_card_intel8x0m_init) 1392 module_exit(alsa_card_intel8x0m_exit) 1393