1 /* 2 * ALSA modem driver for Intel ICH (i8x0) chipsets 3 * 4 * Copyright (c) 2000 Jaroslav Kysela <perex@suse.cz> 5 * 6 * This is modified (by Sasha Khapyorsky <sashak@alsa-project.org>) version 7 * of ALSA ICH sound driver intel8x0.c . 8 * 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 23 * 24 */ 25 26 #include <sound/driver.h> 27 #include <asm/io.h> 28 #include <linux/delay.h> 29 #include <linux/interrupt.h> 30 #include <linux/init.h> 31 #include <linux/pci.h> 32 #include <linux/slab.h> 33 #include <linux/moduleparam.h> 34 #include <sound/core.h> 35 #include <sound/pcm.h> 36 #include <sound/ac97_codec.h> 37 #include <sound/info.h> 38 #include <sound/initval.h> 39 40 MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>"); 41 MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; SiS 7013; NVidia MCP/2/2S/3 modems"); 42 MODULE_LICENSE("GPL"); 43 MODULE_SUPPORTED_DEVICE("{{Intel,82801AA-ICH}," 44 "{Intel,82901AB-ICH0}," 45 "{Intel,82801BA-ICH2}," 46 "{Intel,82801CA-ICH3}," 47 "{Intel,82801DB-ICH4}," 48 "{Intel,ICH5}," 49 "{Intel,ICH6}," 50 "{Intel,ICH7}," 51 "{Intel,MX440}," 52 "{SiS,7013}," 53 "{NVidia,NForce Modem}," 54 "{NVidia,NForce2 Modem}," 55 "{NVidia,NForce2s Modem}," 56 "{NVidia,NForce3 Modem}," 57 "{AMD,AMD768}}"); 58 59 static int index = -2; /* Exclude the first card */ 60 static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */ 61 static int ac97_clock = 0; 62 63 module_param(index, int, 0444); 64 MODULE_PARM_DESC(index, "Index value for Intel i8x0 modemcard."); 65 module_param(id, charp, 0444); 66 MODULE_PARM_DESC(id, "ID string for Intel i8x0 modemcard."); 67 module_param(ac97_clock, int, 0444); 68 MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = auto-detect)."); 69 70 /* just for backward compatibility */ 71 static int enable; 72 module_param(enable, bool, 0444); 73 74 /* 75 * Direct registers 76 */ 77 enum { DEVICE_INTEL, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE }; 78 79 #define ICHREG(x) ICH_REG_##x 80 81 #define DEFINE_REGSET(name,base) \ 82 enum { \ 83 ICH_REG_##name##_BDBAR = base + 0x0, /* dword - buffer descriptor list base address */ \ 84 ICH_REG_##name##_CIV = base + 0x04, /* byte - current index value */ \ 85 ICH_REG_##name##_LVI = base + 0x05, /* byte - last valid index */ \ 86 ICH_REG_##name##_SR = base + 0x06, /* byte - status register */ \ 87 ICH_REG_##name##_PICB = base + 0x08, /* word - position in current buffer */ \ 88 ICH_REG_##name##_PIV = base + 0x0a, /* byte - prefetched index value */ \ 89 ICH_REG_##name##_CR = base + 0x0b, /* byte - control register */ \ 90 }; 91 92 /* busmaster blocks */ 93 DEFINE_REGSET(OFF, 0); /* offset */ 94 95 /* values for each busmaster block */ 96 97 /* LVI */ 98 #define ICH_REG_LVI_MASK 0x1f 99 100 /* SR */ 101 #define ICH_FIFOE 0x10 /* FIFO error */ 102 #define ICH_BCIS 0x08 /* buffer completion interrupt status */ 103 #define ICH_LVBCI 0x04 /* last valid buffer completion interrupt */ 104 #define ICH_CELV 0x02 /* current equals last valid */ 105 #define ICH_DCH 0x01 /* DMA controller halted */ 106 107 /* PIV */ 108 #define ICH_REG_PIV_MASK 0x1f /* mask */ 109 110 /* CR */ 111 #define ICH_IOCE 0x10 /* interrupt on completion enable */ 112 #define ICH_FEIE 0x08 /* fifo error interrupt enable */ 113 #define ICH_LVBIE 0x04 /* last valid buffer interrupt enable */ 114 #define ICH_RESETREGS 0x02 /* reset busmaster registers */ 115 #define ICH_STARTBM 0x01 /* start busmaster operation */ 116 117 118 /* global block */ 119 #define ICH_REG_GLOB_CNT 0x3c /* dword - global control */ 120 #define ICH_TRIE 0x00000040 /* tertiary resume interrupt enable */ 121 #define ICH_SRIE 0x00000020 /* secondary resume interrupt enable */ 122 #define ICH_PRIE 0x00000010 /* primary resume interrupt enable */ 123 #define ICH_ACLINK 0x00000008 /* AClink shut off */ 124 #define ICH_AC97WARM 0x00000004 /* AC'97 warm reset */ 125 #define ICH_AC97COLD 0x00000002 /* AC'97 cold reset */ 126 #define ICH_GIE 0x00000001 /* GPI interrupt enable */ 127 #define ICH_REG_GLOB_STA 0x40 /* dword - global status */ 128 #define ICH_TRI 0x20000000 /* ICH4: tertiary (AC_SDIN2) resume interrupt */ 129 #define ICH_TCR 0x10000000 /* ICH4: tertiary (AC_SDIN2) codec ready */ 130 #define ICH_BCS 0x08000000 /* ICH4: bit clock stopped */ 131 #define ICH_SPINT 0x04000000 /* ICH4: S/PDIF interrupt */ 132 #define ICH_P2INT 0x02000000 /* ICH4: PCM2-In interrupt */ 133 #define ICH_M2INT 0x01000000 /* ICH4: Mic2-In interrupt */ 134 #define ICH_SAMPLE_CAP 0x00c00000 /* ICH4: sample capability bits (RO) */ 135 #define ICH_MULTICHAN_CAP 0x00300000 /* ICH4: multi-channel capability bits (RO) */ 136 #define ICH_MD3 0x00020000 /* modem power down semaphore */ 137 #define ICH_AD3 0x00010000 /* audio power down semaphore */ 138 #define ICH_RCS 0x00008000 /* read completion status */ 139 #define ICH_BIT3 0x00004000 /* bit 3 slot 12 */ 140 #define ICH_BIT2 0x00002000 /* bit 2 slot 12 */ 141 #define ICH_BIT1 0x00001000 /* bit 1 slot 12 */ 142 #define ICH_SRI 0x00000800 /* secondary (AC_SDIN1) resume interrupt */ 143 #define ICH_PRI 0x00000400 /* primary (AC_SDIN0) resume interrupt */ 144 #define ICH_SCR 0x00000200 /* secondary (AC_SDIN1) codec ready */ 145 #define ICH_PCR 0x00000100 /* primary (AC_SDIN0) codec ready */ 146 #define ICH_MCINT 0x00000080 /* MIC capture interrupt */ 147 #define ICH_POINT 0x00000040 /* playback interrupt */ 148 #define ICH_PIINT 0x00000020 /* capture interrupt */ 149 #define ICH_NVSPINT 0x00000010 /* nforce spdif interrupt */ 150 #define ICH_MOINT 0x00000004 /* modem playback interrupt */ 151 #define ICH_MIINT 0x00000002 /* modem capture interrupt */ 152 #define ICH_GSCI 0x00000001 /* GPI status change interrupt */ 153 #define ICH_REG_ACC_SEMA 0x44 /* byte - codec write semaphore */ 154 #define ICH_CAS 0x01 /* codec access semaphore */ 155 156 #define ICH_MAX_FRAGS 32 /* max hw frags */ 157 158 159 /* 160 * 161 */ 162 163 enum { ICHD_MDMIN, ICHD_MDMOUT, ICHD_MDMLAST = ICHD_MDMOUT }; 164 enum { ALID_MDMIN, ALID_MDMOUT, ALID_MDMLAST = ALID_MDMOUT }; 165 166 #define get_ichdev(substream) (ichdev_t *)(substream->runtime->private_data) 167 168 typedef struct { 169 unsigned int ichd; /* ich device number */ 170 unsigned long reg_offset; /* offset to bmaddr */ 171 u32 *bdbar; /* CPU address (32bit) */ 172 unsigned int bdbar_addr; /* PCI bus address (32bit) */ 173 snd_pcm_substream_t *substream; 174 unsigned int physbuf; /* physical address (32bit) */ 175 unsigned int size; 176 unsigned int fragsize; 177 unsigned int fragsize1; 178 unsigned int position; 179 int frags; 180 int lvi; 181 int lvi_frag; 182 int civ; 183 int ack; 184 int ack_reload; 185 unsigned int ack_bit; 186 unsigned int roff_sr; 187 unsigned int roff_picb; 188 unsigned int int_sta_mask; /* interrupt status mask */ 189 unsigned int ali_slot; /* ALI DMA slot */ 190 ac97_t *ac97; 191 } ichdev_t; 192 193 typedef struct _snd_intel8x0m intel8x0_t; 194 195 struct _snd_intel8x0m { 196 unsigned int device_type; 197 198 int irq; 199 200 unsigned int mmio; 201 unsigned long addr; 202 void __iomem *remap_addr; 203 unsigned int bm_mmio; 204 unsigned long bmaddr; 205 void __iomem *remap_bmaddr; 206 207 struct pci_dev *pci; 208 snd_card_t *card; 209 210 int pcm_devs; 211 snd_pcm_t *pcm[2]; 212 ichdev_t ichd[2]; 213 214 unsigned int in_ac97_init: 1; 215 216 ac97_bus_t *ac97_bus; 217 ac97_t *ac97; 218 219 spinlock_t reg_lock; 220 221 struct snd_dma_buffer bdbars; 222 u32 bdbars_count; 223 u32 int_sta_reg; /* interrupt status register */ 224 u32 int_sta_mask; /* interrupt status mask */ 225 unsigned int pcm_pos_shift; 226 }; 227 228 static struct pci_device_id snd_intel8x0m_ids[] = { 229 { 0x8086, 0x2416, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801AA */ 230 { 0x8086, 0x2426, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82901AB */ 231 { 0x8086, 0x2446, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801BA */ 232 { 0x8086, 0x2486, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH3 */ 233 { 0x8086, 0x24c6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH4 */ 234 { 0x8086, 0x24d6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH5 */ 235 { 0x8086, 0x266d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH6 */ 236 { 0x8086, 0x27dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH7 */ 237 { 0x8086, 0x7196, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 440MX */ 238 { 0x1022, 0x7446, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD768 */ 239 { 0x1039, 0x7013, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_SIS }, /* SI7013 */ 240 { 0x10de, 0x01c1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE */ 241 { 0x10de, 0x0069, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE2 */ 242 { 0x10de, 0x0089, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE2s */ 243 { 0x10de, 0x00d9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE3 */ 244 #if 0 245 { 0x1022, 0x746d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD8111 */ 246 { 0x10b9, 0x5455, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_ALI }, /* Ali5455 */ 247 #endif 248 { 0, } 249 }; 250 251 MODULE_DEVICE_TABLE(pci, snd_intel8x0m_ids); 252 253 /* 254 * Lowlevel I/O - busmaster 255 */ 256 257 static u8 igetbyte(intel8x0_t *chip, u32 offset) 258 { 259 if (chip->bm_mmio) 260 return readb(chip->remap_bmaddr + offset); 261 else 262 return inb(chip->bmaddr + offset); 263 } 264 265 static u16 igetword(intel8x0_t *chip, u32 offset) 266 { 267 if (chip->bm_mmio) 268 return readw(chip->remap_bmaddr + offset); 269 else 270 return inw(chip->bmaddr + offset); 271 } 272 273 static u32 igetdword(intel8x0_t *chip, u32 offset) 274 { 275 if (chip->bm_mmio) 276 return readl(chip->remap_bmaddr + offset); 277 else 278 return inl(chip->bmaddr + offset); 279 } 280 281 static void iputbyte(intel8x0_t *chip, u32 offset, u8 val) 282 { 283 if (chip->bm_mmio) 284 writeb(val, chip->remap_bmaddr + offset); 285 else 286 outb(val, chip->bmaddr + offset); 287 } 288 289 static void iputword(intel8x0_t *chip, u32 offset, u16 val) 290 { 291 if (chip->bm_mmio) 292 writew(val, chip->remap_bmaddr + offset); 293 else 294 outw(val, chip->bmaddr + offset); 295 } 296 297 static void iputdword(intel8x0_t *chip, u32 offset, u32 val) 298 { 299 if (chip->bm_mmio) 300 writel(val, chip->remap_bmaddr + offset); 301 else 302 outl(val, chip->bmaddr + offset); 303 } 304 305 /* 306 * Lowlevel I/O - AC'97 registers 307 */ 308 309 static u16 iagetword(intel8x0_t *chip, u32 offset) 310 { 311 if (chip->mmio) 312 return readw(chip->remap_addr + offset); 313 else 314 return inw(chip->addr + offset); 315 } 316 317 static void iaputword(intel8x0_t *chip, u32 offset, u16 val) 318 { 319 if (chip->mmio) 320 writew(val, chip->remap_addr + offset); 321 else 322 outw(val, chip->addr + offset); 323 } 324 325 /* 326 * Basic I/O 327 */ 328 329 /* 330 * access to AC97 codec via normal i/o (for ICH and SIS7013) 331 */ 332 333 /* return the GLOB_STA bit for the corresponding codec */ 334 static unsigned int get_ich_codec_bit(intel8x0_t *chip, unsigned int codec) 335 { 336 static unsigned int codec_bit[3] = { 337 ICH_PCR, ICH_SCR, ICH_TCR 338 }; 339 snd_assert(codec < 3, return ICH_PCR); 340 return codec_bit[codec]; 341 } 342 343 static int snd_intel8x0m_codec_semaphore(intel8x0_t *chip, unsigned int codec) 344 { 345 int time; 346 347 if (codec > 1) 348 return -EIO; 349 codec = get_ich_codec_bit(chip, codec); 350 351 /* codec ready ? */ 352 if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0) 353 return -EIO; 354 355 /* Anyone holding a semaphore for 1 msec should be shot... */ 356 time = 100; 357 do { 358 if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS)) 359 return 0; 360 udelay(10); 361 } while (time--); 362 363 /* access to some forbidden (non existant) ac97 registers will not 364 * reset the semaphore. So even if you don't get the semaphore, still 365 * continue the access. We don't need the semaphore anyway. */ 366 snd_printk(KERN_ERR "codec_semaphore: semaphore is not ready [0x%x][0x%x]\n", 367 igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA))); 368 iagetword(chip, 0); /* clear semaphore flag */ 369 /* I don't care about the semaphore */ 370 return -EBUSY; 371 } 372 373 static void snd_intel8x0_codec_write(ac97_t *ac97, 374 unsigned short reg, 375 unsigned short val) 376 { 377 intel8x0_t *chip = ac97->private_data; 378 379 if (snd_intel8x0m_codec_semaphore(chip, ac97->num) < 0) { 380 if (! chip->in_ac97_init) 381 snd_printk(KERN_ERR "codec_write %d: semaphore is not ready for register 0x%x\n", ac97->num, reg); 382 } 383 iaputword(chip, reg + ac97->num * 0x80, val); 384 } 385 386 static unsigned short snd_intel8x0_codec_read(ac97_t *ac97, 387 unsigned short reg) 388 { 389 intel8x0_t *chip = ac97->private_data; 390 unsigned short res; 391 unsigned int tmp; 392 393 if (snd_intel8x0m_codec_semaphore(chip, ac97->num) < 0) { 394 if (! chip->in_ac97_init) 395 snd_printk(KERN_ERR "codec_read %d: semaphore is not ready for register 0x%x\n", ac97->num, reg); 396 res = 0xffff; 397 } else { 398 res = iagetword(chip, reg + ac97->num * 0x80); 399 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) { 400 /* reset RCS and preserve other R/WC bits */ 401 iputdword(chip, ICHREG(GLOB_STA), tmp & ~(ICH_SRI|ICH_PRI|ICH_TRI|ICH_GSCI)); 402 if (! chip->in_ac97_init) 403 snd_printk(KERN_ERR "codec_read %d: read timeout for register 0x%x\n", ac97->num, reg); 404 res = 0xffff; 405 } 406 } 407 if (reg == AC97_GPIO_STATUS) 408 iagetword(chip, 0); /* clear semaphore */ 409 return res; 410 } 411 412 413 /* 414 * DMA I/O 415 */ 416 static void snd_intel8x0_setup_periods(intel8x0_t *chip, ichdev_t *ichdev) 417 { 418 int idx; 419 u32 *bdbar = ichdev->bdbar; 420 unsigned long port = ichdev->reg_offset; 421 422 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr); 423 if (ichdev->size == ichdev->fragsize) { 424 ichdev->ack_reload = ichdev->ack = 2; 425 ichdev->fragsize1 = ichdev->fragsize >> 1; 426 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) { 427 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf); 428 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */ 429 ichdev->fragsize1 >> chip->pcm_pos_shift); 430 bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1)); 431 bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */ 432 ichdev->fragsize1 >> chip->pcm_pos_shift); 433 } 434 ichdev->frags = 2; 435 } else { 436 ichdev->ack_reload = ichdev->ack = 1; 437 ichdev->fragsize1 = ichdev->fragsize; 438 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) { 439 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf + (((idx >> 1) * ichdev->fragsize) % ichdev->size)); 440 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */ 441 ichdev->fragsize >> chip->pcm_pos_shift); 442 // printk("bdbar[%i] = 0x%x [0x%x]\n", idx + 0, bdbar[idx + 0], bdbar[idx + 1]); 443 } 444 ichdev->frags = ichdev->size / ichdev->fragsize; 445 } 446 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK); 447 ichdev->civ = 0; 448 iputbyte(chip, port + ICH_REG_OFF_CIV, 0); 449 ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags; 450 ichdev->position = 0; 451 #if 0 452 printk("lvi_frag = %i, frags = %i, period_size = 0x%x, period_size1 = 0x%x\n", 453 ichdev->lvi_frag, ichdev->frags, ichdev->fragsize, ichdev->fragsize1); 454 #endif 455 /* clear interrupts */ 456 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI); 457 } 458 459 /* 460 * Interrupt handler 461 */ 462 463 static inline void snd_intel8x0_update(intel8x0_t *chip, ichdev_t *ichdev) 464 { 465 unsigned long port = ichdev->reg_offset; 466 int civ, i, step; 467 int ack = 0; 468 469 civ = igetbyte(chip, port + ICH_REG_OFF_CIV); 470 if (civ == ichdev->civ) { 471 // snd_printd("civ same %d\n", civ); 472 step = 1; 473 ichdev->civ++; 474 ichdev->civ &= ICH_REG_LVI_MASK; 475 } else { 476 step = civ - ichdev->civ; 477 if (step < 0) 478 step += ICH_REG_LVI_MASK + 1; 479 // if (step != 1) 480 // snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ); 481 ichdev->civ = civ; 482 } 483 484 ichdev->position += step * ichdev->fragsize1; 485 ichdev->position %= ichdev->size; 486 ichdev->lvi += step; 487 ichdev->lvi &= ICH_REG_LVI_MASK; 488 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi); 489 for (i = 0; i < step; i++) { 490 ichdev->lvi_frag++; 491 ichdev->lvi_frag %= ichdev->frags; 492 ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + ichdev->lvi_frag * ichdev->fragsize1); 493 // printk("new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, all = 0x%x, 0x%x\n", ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2], ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port), inl(port + 4), inb(port + ICH_REG_OFF_CR)); 494 if (--ichdev->ack == 0) { 495 ichdev->ack = ichdev->ack_reload; 496 ack = 1; 497 } 498 } 499 if (ack && ichdev->substream) { 500 spin_unlock(&chip->reg_lock); 501 snd_pcm_period_elapsed(ichdev->substream); 502 spin_lock(&chip->reg_lock); 503 } 504 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI); 505 } 506 507 static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id, struct pt_regs *regs) 508 { 509 intel8x0_t *chip = dev_id; 510 ichdev_t *ichdev; 511 unsigned int status; 512 unsigned int i; 513 514 spin_lock(&chip->reg_lock); 515 status = igetdword(chip, chip->int_sta_reg); 516 if (status == 0xffffffff) { /* we are not yet resumed */ 517 spin_unlock(&chip->reg_lock); 518 return IRQ_NONE; 519 } 520 if ((status & chip->int_sta_mask) == 0) { 521 if (status) 522 iputdword(chip, chip->int_sta_reg, status); 523 spin_unlock(&chip->reg_lock); 524 return IRQ_NONE; 525 } 526 527 for (i = 0; i < chip->bdbars_count; i++) { 528 ichdev = &chip->ichd[i]; 529 if (status & ichdev->int_sta_mask) 530 snd_intel8x0_update(chip, ichdev); 531 } 532 533 /* ack them */ 534 iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask); 535 spin_unlock(&chip->reg_lock); 536 537 return IRQ_HANDLED; 538 } 539 540 /* 541 * PCM part 542 */ 543 544 static int snd_intel8x0_pcm_trigger(snd_pcm_substream_t *substream, int cmd) 545 { 546 intel8x0_t *chip = snd_pcm_substream_chip(substream); 547 ichdev_t *ichdev = get_ichdev(substream); 548 unsigned char val = 0; 549 unsigned long port = ichdev->reg_offset; 550 551 switch (cmd) { 552 case SNDRV_PCM_TRIGGER_START: 553 case SNDRV_PCM_TRIGGER_RESUME: 554 val = ICH_IOCE | ICH_STARTBM; 555 break; 556 case SNDRV_PCM_TRIGGER_STOP: 557 case SNDRV_PCM_TRIGGER_SUSPEND: 558 val = 0; 559 break; 560 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 561 val = ICH_IOCE; 562 break; 563 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 564 val = ICH_IOCE | ICH_STARTBM; 565 break; 566 default: 567 return -EINVAL; 568 } 569 iputbyte(chip, port + ICH_REG_OFF_CR, val); 570 if (cmd == SNDRV_PCM_TRIGGER_STOP) { 571 /* wait until DMA stopped */ 572 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ; 573 /* reset whole DMA things */ 574 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS); 575 } 576 return 0; 577 } 578 579 static int snd_intel8x0_hw_params(snd_pcm_substream_t * substream, 580 snd_pcm_hw_params_t * hw_params) 581 { 582 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params)); 583 } 584 585 static int snd_intel8x0_hw_free(snd_pcm_substream_t * substream) 586 { 587 return snd_pcm_lib_free_pages(substream); 588 } 589 590 static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(snd_pcm_substream_t * substream) 591 { 592 intel8x0_t *chip = snd_pcm_substream_chip(substream); 593 ichdev_t *ichdev = get_ichdev(substream); 594 size_t ptr1, ptr; 595 596 ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb) << chip->pcm_pos_shift; 597 if (ptr1 != 0) 598 ptr = ichdev->fragsize1 - ptr1; 599 else 600 ptr = 0; 601 ptr += ichdev->position; 602 if (ptr >= ichdev->size) 603 return 0; 604 return bytes_to_frames(substream->runtime, ptr); 605 } 606 607 static int snd_intel8x0m_pcm_prepare(snd_pcm_substream_t * substream) 608 { 609 intel8x0_t *chip = snd_pcm_substream_chip(substream); 610 snd_pcm_runtime_t *runtime = substream->runtime; 611 ichdev_t *ichdev = get_ichdev(substream); 612 613 ichdev->physbuf = runtime->dma_addr; 614 ichdev->size = snd_pcm_lib_buffer_bytes(substream); 615 ichdev->fragsize = snd_pcm_lib_period_bytes(substream); 616 snd_ac97_write(ichdev->ac97, AC97_LINE1_RATE, runtime->rate); 617 snd_ac97_write(ichdev->ac97, AC97_LINE1_LEVEL, 0); 618 snd_intel8x0_setup_periods(chip, ichdev); 619 return 0; 620 } 621 622 static snd_pcm_hardware_t snd_intel8x0m_stream = 623 { 624 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 625 SNDRV_PCM_INFO_BLOCK_TRANSFER | 626 SNDRV_PCM_INFO_MMAP_VALID | 627 SNDRV_PCM_INFO_PAUSE | 628 SNDRV_PCM_INFO_RESUME), 629 .formats = SNDRV_PCM_FMTBIT_S16_LE, 630 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_KNOT, 631 .rate_min = 8000, 632 .rate_max = 16000, 633 .channels_min = 1, 634 .channels_max = 1, 635 .buffer_bytes_max = 64 * 1024, 636 .period_bytes_min = 32, 637 .period_bytes_max = 64 * 1024, 638 .periods_min = 1, 639 .periods_max = 1024, 640 .fifo_size = 0, 641 }; 642 643 644 static int snd_intel8x0m_pcm_open(snd_pcm_substream_t * substream, ichdev_t *ichdev) 645 { 646 static unsigned int rates[] = { 8000, 9600, 12000, 16000 }; 647 static snd_pcm_hw_constraint_list_t hw_constraints_rates = { 648 .count = ARRAY_SIZE(rates), 649 .list = rates, 650 .mask = 0, 651 }; 652 snd_pcm_runtime_t *runtime = substream->runtime; 653 int err; 654 655 ichdev->substream = substream; 656 runtime->hw = snd_intel8x0m_stream; 657 err = snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates); 658 if ( err < 0 ) 659 return err; 660 runtime->private_data = ichdev; 661 return 0; 662 } 663 664 static int snd_intel8x0m_playback_open(snd_pcm_substream_t * substream) 665 { 666 intel8x0_t *chip = snd_pcm_substream_chip(substream); 667 668 return snd_intel8x0m_pcm_open(substream, &chip->ichd[ICHD_MDMOUT]); 669 } 670 671 static int snd_intel8x0m_playback_close(snd_pcm_substream_t * substream) 672 { 673 intel8x0_t *chip = snd_pcm_substream_chip(substream); 674 675 chip->ichd[ICHD_MDMOUT].substream = NULL; 676 return 0; 677 } 678 679 static int snd_intel8x0m_capture_open(snd_pcm_substream_t * substream) 680 { 681 intel8x0_t *chip = snd_pcm_substream_chip(substream); 682 683 return snd_intel8x0m_pcm_open(substream, &chip->ichd[ICHD_MDMIN]); 684 } 685 686 static int snd_intel8x0m_capture_close(snd_pcm_substream_t * substream) 687 { 688 intel8x0_t *chip = snd_pcm_substream_chip(substream); 689 690 chip->ichd[ICHD_MDMIN].substream = NULL; 691 return 0; 692 } 693 694 695 static snd_pcm_ops_t snd_intel8x0m_playback_ops = { 696 .open = snd_intel8x0m_playback_open, 697 .close = snd_intel8x0m_playback_close, 698 .ioctl = snd_pcm_lib_ioctl, 699 .hw_params = snd_intel8x0_hw_params, 700 .hw_free = snd_intel8x0_hw_free, 701 .prepare = snd_intel8x0m_pcm_prepare, 702 .trigger = snd_intel8x0_pcm_trigger, 703 .pointer = snd_intel8x0_pcm_pointer, 704 }; 705 706 static snd_pcm_ops_t snd_intel8x0m_capture_ops = { 707 .open = snd_intel8x0m_capture_open, 708 .close = snd_intel8x0m_capture_close, 709 .ioctl = snd_pcm_lib_ioctl, 710 .hw_params = snd_intel8x0_hw_params, 711 .hw_free = snd_intel8x0_hw_free, 712 .prepare = snd_intel8x0m_pcm_prepare, 713 .trigger = snd_intel8x0_pcm_trigger, 714 .pointer = snd_intel8x0_pcm_pointer, 715 }; 716 717 718 struct ich_pcm_table { 719 char *suffix; 720 snd_pcm_ops_t *playback_ops; 721 snd_pcm_ops_t *capture_ops; 722 size_t prealloc_size; 723 size_t prealloc_max_size; 724 int ac97_idx; 725 }; 726 727 static int __devinit snd_intel8x0_pcm1(intel8x0_t *chip, int device, struct ich_pcm_table *rec) 728 { 729 snd_pcm_t *pcm; 730 int err; 731 char name[32]; 732 733 if (rec->suffix) 734 sprintf(name, "Intel ICH - %s", rec->suffix); 735 else 736 strcpy(name, "Intel ICH"); 737 err = snd_pcm_new(chip->card, name, device, 738 rec->playback_ops ? 1 : 0, 739 rec->capture_ops ? 1 : 0, &pcm); 740 if (err < 0) 741 return err; 742 743 if (rec->playback_ops) 744 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops); 745 if (rec->capture_ops) 746 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops); 747 748 pcm->private_data = chip; 749 pcm->info_flags = 0; 750 pcm->dev_class = SNDRV_PCM_CLASS_MODEM; 751 if (rec->suffix) 752 sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix); 753 else 754 strcpy(pcm->name, chip->card->shortname); 755 chip->pcm[device] = pcm; 756 757 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 758 snd_dma_pci_data(chip->pci), 759 rec->prealloc_size, 760 rec->prealloc_max_size); 761 762 return 0; 763 } 764 765 static struct ich_pcm_table intel_pcms[] __devinitdata = { 766 { 767 .suffix = "Modem", 768 .playback_ops = &snd_intel8x0m_playback_ops, 769 .capture_ops = &snd_intel8x0m_capture_ops, 770 .prealloc_size = 32 * 1024, 771 .prealloc_max_size = 64 * 1024, 772 }, 773 }; 774 775 static int __devinit snd_intel8x0_pcm(intel8x0_t *chip) 776 { 777 int i, tblsize, device, err; 778 struct ich_pcm_table *tbl, *rec; 779 780 #if 1 781 tbl = intel_pcms; 782 tblsize = 1; 783 #else 784 switch (chip->device_type) { 785 case DEVICE_NFORCE: 786 tbl = nforce_pcms; 787 tblsize = ARRAY_SIZE(nforce_pcms); 788 break; 789 case DEVICE_ALI: 790 tbl = ali_pcms; 791 tblsize = ARRAY_SIZE(ali_pcms); 792 break; 793 default: 794 tbl = intel_pcms; 795 tblsize = 2; 796 break; 797 } 798 #endif 799 device = 0; 800 for (i = 0; i < tblsize; i++) { 801 rec = tbl + i; 802 if (i > 0 && rec->ac97_idx) { 803 /* activate PCM only when associated AC'97 codec */ 804 if (! chip->ichd[rec->ac97_idx].ac97) 805 continue; 806 } 807 err = snd_intel8x0_pcm1(chip, device, rec); 808 if (err < 0) 809 return err; 810 device++; 811 } 812 813 chip->pcm_devs = device; 814 return 0; 815 } 816 817 818 /* 819 * Mixer part 820 */ 821 822 static void snd_intel8x0_mixer_free_ac97_bus(ac97_bus_t *bus) 823 { 824 intel8x0_t *chip = bus->private_data; 825 chip->ac97_bus = NULL; 826 } 827 828 static void snd_intel8x0_mixer_free_ac97(ac97_t *ac97) 829 { 830 intel8x0_t *chip = ac97->private_data; 831 chip->ac97 = NULL; 832 } 833 834 835 static int __devinit snd_intel8x0_mixer(intel8x0_t *chip, int ac97_clock) 836 { 837 ac97_bus_t *pbus; 838 ac97_template_t ac97; 839 ac97_t *x97; 840 int err; 841 unsigned int glob_sta = 0; 842 static ac97_bus_ops_t ops = { 843 .write = snd_intel8x0_codec_write, 844 .read = snd_intel8x0_codec_read, 845 }; 846 847 chip->in_ac97_init = 1; 848 849 memset(&ac97, 0, sizeof(ac97)); 850 ac97.private_data = chip; 851 ac97.private_free = snd_intel8x0_mixer_free_ac97; 852 ac97.scaps = AC97_SCAP_SKIP_AUDIO; 853 854 glob_sta = igetdword(chip, ICHREG(GLOB_STA)); 855 856 if ((err = snd_ac97_bus(chip->card, 0, &ops, chip, &pbus)) < 0) 857 goto __err; 858 pbus->private_free = snd_intel8x0_mixer_free_ac97_bus; 859 if (ac97_clock >= 8000 && ac97_clock <= 48000) 860 pbus->clock = ac97_clock; 861 chip->ac97_bus = pbus; 862 863 ac97.pci = chip->pci; 864 ac97.num = glob_sta & ICH_SCR ? 1 : 0; 865 if ((err = snd_ac97_mixer(pbus, &ac97, &x97)) < 0) { 866 snd_printk(KERN_ERR "Unable to initialize codec #%d\n", ac97.num); 867 if (ac97.num == 0) 868 goto __err; 869 return err; 870 } 871 chip->ac97 = x97; 872 if(ac97_is_modem(x97) && !chip->ichd[ICHD_MDMIN].ac97) { 873 chip->ichd[ICHD_MDMIN].ac97 = x97; 874 chip->ichd[ICHD_MDMOUT].ac97 = x97; 875 } 876 877 chip->in_ac97_init = 0; 878 return 0; 879 880 __err: 881 /* clear the cold-reset bit for the next chance */ 882 if (chip->device_type != DEVICE_ALI) 883 iputdword(chip, ICHREG(GLOB_CNT), igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD); 884 return err; 885 } 886 887 888 /* 889 * 890 */ 891 892 #define do_delay(chip) do {\ 893 schedule_timeout_uninterruptible(1);\ 894 } while (0) 895 896 static int snd_intel8x0m_ich_chip_init(intel8x0_t *chip, int probing) 897 { 898 unsigned long end_time; 899 unsigned int cnt, status, nstatus; 900 901 /* put logic to right state */ 902 /* first clear status bits */ 903 status = ICH_RCS | ICH_MIINT | ICH_MOINT; 904 cnt = igetdword(chip, ICHREG(GLOB_STA)); 905 iputdword(chip, ICHREG(GLOB_STA), cnt & status); 906 907 /* ACLink on, 2 channels */ 908 cnt = igetdword(chip, ICHREG(GLOB_CNT)); 909 cnt &= ~(ICH_ACLINK); 910 /* finish cold or do warm reset */ 911 cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM; 912 iputdword(chip, ICHREG(GLOB_CNT), cnt); 913 end_time = (jiffies + (HZ / 4)) + 1; 914 do { 915 if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0) 916 goto __ok; 917 do_delay(chip); 918 } while (time_after_eq(end_time, jiffies)); 919 snd_printk(KERN_ERR "AC'97 warm reset still in progress? [0x%x]\n", igetdword(chip, ICHREG(GLOB_CNT))); 920 return -EIO; 921 922 __ok: 923 if (probing) { 924 /* wait for any codec ready status. 925 * Once it becomes ready it should remain ready 926 * as long as we do not disable the ac97 link. 927 */ 928 end_time = jiffies + HZ; 929 do { 930 status = igetdword(chip, ICHREG(GLOB_STA)) & (ICH_PCR | ICH_SCR | ICH_TCR); 931 if (status) 932 break; 933 do_delay(chip); 934 } while (time_after_eq(end_time, jiffies)); 935 if (! status) { 936 /* no codec is found */ 937 snd_printk(KERN_ERR "codec_ready: codec is not ready [0x%x]\n", igetdword(chip, ICHREG(GLOB_STA))); 938 return -EIO; 939 } 940 941 /* up to two codecs (modem cannot be tertiary with ICH4) */ 942 nstatus = ICH_PCR | ICH_SCR; 943 944 /* wait for other codecs ready status. */ 945 end_time = jiffies + HZ / 4; 946 while (status != nstatus && time_after_eq(end_time, jiffies)) { 947 do_delay(chip); 948 status |= igetdword(chip, ICHREG(GLOB_STA)) & nstatus; 949 } 950 951 } else { 952 /* resume phase */ 953 status = 0; 954 if (chip->ac97) 955 status |= get_ich_codec_bit(chip, chip->ac97->num); 956 /* wait until all the probed codecs are ready */ 957 end_time = jiffies + HZ; 958 do { 959 nstatus = igetdword(chip, ICHREG(GLOB_STA)) & (ICH_PCR | ICH_SCR | ICH_TCR); 960 if (status == nstatus) 961 break; 962 do_delay(chip); 963 } while (time_after_eq(end_time, jiffies)); 964 } 965 966 if (chip->device_type == DEVICE_SIS) { 967 /* unmute the output on SIS7012 */ 968 iputword(chip, 0x4c, igetword(chip, 0x4c) | 1); 969 } 970 971 return 0; 972 } 973 974 static int snd_intel8x0_chip_init(intel8x0_t *chip, int probing) 975 { 976 unsigned int i; 977 int err; 978 979 if ((err = snd_intel8x0m_ich_chip_init(chip, probing)) < 0) 980 return err; 981 iagetword(chip, 0); /* clear semaphore flag */ 982 983 /* disable interrupts */ 984 for (i = 0; i < chip->bdbars_count; i++) 985 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00); 986 /* reset channels */ 987 for (i = 0; i < chip->bdbars_count; i++) 988 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS); 989 /* initialize Buffer Descriptor Lists */ 990 for (i = 0; i < chip->bdbars_count; i++) 991 iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset, chip->ichd[i].bdbar_addr); 992 return 0; 993 } 994 995 static int snd_intel8x0_free(intel8x0_t *chip) 996 { 997 unsigned int i; 998 999 if (chip->irq < 0) 1000 goto __hw_end; 1001 /* disable interrupts */ 1002 for (i = 0; i < chip->bdbars_count; i++) 1003 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00); 1004 /* reset channels */ 1005 for (i = 0; i < chip->bdbars_count; i++) 1006 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS); 1007 /* --- */ 1008 synchronize_irq(chip->irq); 1009 __hw_end: 1010 if (chip->bdbars.area) 1011 snd_dma_free_pages(&chip->bdbars); 1012 if (chip->remap_addr) 1013 iounmap(chip->remap_addr); 1014 if (chip->remap_bmaddr) 1015 iounmap(chip->remap_bmaddr); 1016 if (chip->irq >= 0) 1017 free_irq(chip->irq, (void *)chip); 1018 pci_release_regions(chip->pci); 1019 pci_disable_device(chip->pci); 1020 kfree(chip); 1021 return 0; 1022 } 1023 1024 #ifdef CONFIG_PM 1025 /* 1026 * power management 1027 */ 1028 static int intel8x0m_suspend(snd_card_t *card, pm_message_t state) 1029 { 1030 intel8x0_t *chip = card->pm_private_data; 1031 int i; 1032 1033 for (i = 0; i < chip->pcm_devs; i++) 1034 snd_pcm_suspend_all(chip->pcm[i]); 1035 if (chip->ac97) 1036 snd_ac97_suspend(chip->ac97); 1037 pci_disable_device(chip->pci); 1038 return 0; 1039 } 1040 1041 static int intel8x0m_resume(snd_card_t *card) 1042 { 1043 intel8x0_t *chip = card->pm_private_data; 1044 pci_enable_device(chip->pci); 1045 pci_set_master(chip->pci); 1046 snd_intel8x0_chip_init(chip, 0); 1047 if (chip->ac97) 1048 snd_ac97_resume(chip->ac97); 1049 1050 return 0; 1051 } 1052 #endif /* CONFIG_PM */ 1053 1054 static void snd_intel8x0m_proc_read(snd_info_entry_t * entry, 1055 snd_info_buffer_t * buffer) 1056 { 1057 intel8x0_t *chip = entry->private_data; 1058 unsigned int tmp; 1059 1060 snd_iprintf(buffer, "Intel8x0m\n\n"); 1061 if (chip->device_type == DEVICE_ALI) 1062 return; 1063 tmp = igetdword(chip, ICHREG(GLOB_STA)); 1064 snd_iprintf(buffer, "Global control : 0x%08x\n", igetdword(chip, ICHREG(GLOB_CNT))); 1065 snd_iprintf(buffer, "Global status : 0x%08x\n", tmp); 1066 snd_iprintf(buffer, "AC'97 codecs ready :%s%s%s%s\n", 1067 tmp & ICH_PCR ? " primary" : "", 1068 tmp & ICH_SCR ? " secondary" : "", 1069 tmp & ICH_TCR ? " tertiary" : "", 1070 (tmp & (ICH_PCR | ICH_SCR | ICH_TCR)) == 0 ? " none" : ""); 1071 } 1072 1073 static void __devinit snd_intel8x0m_proc_init(intel8x0_t * chip) 1074 { 1075 snd_info_entry_t *entry; 1076 1077 if (! snd_card_proc_new(chip->card, "intel8x0m", &entry)) 1078 snd_info_set_text_ops(entry, chip, 1024, snd_intel8x0m_proc_read); 1079 } 1080 1081 static int snd_intel8x0_dev_free(snd_device_t *device) 1082 { 1083 intel8x0_t *chip = device->device_data; 1084 return snd_intel8x0_free(chip); 1085 } 1086 1087 struct ich_reg_info { 1088 unsigned int int_sta_mask; 1089 unsigned int offset; 1090 }; 1091 1092 static int __devinit snd_intel8x0m_create(snd_card_t * card, 1093 struct pci_dev *pci, 1094 unsigned long device_type, 1095 intel8x0_t ** r_intel8x0) 1096 { 1097 intel8x0_t *chip; 1098 int err; 1099 unsigned int i; 1100 unsigned int int_sta_masks; 1101 ichdev_t *ichdev; 1102 static snd_device_ops_t ops = { 1103 .dev_free = snd_intel8x0_dev_free, 1104 }; 1105 static struct ich_reg_info intel_regs[2] = { 1106 { ICH_MIINT, 0 }, 1107 { ICH_MOINT, 0x10 }, 1108 }; 1109 struct ich_reg_info *tbl; 1110 1111 *r_intel8x0 = NULL; 1112 1113 if ((err = pci_enable_device(pci)) < 0) 1114 return err; 1115 1116 chip = kzalloc(sizeof(*chip), GFP_KERNEL); 1117 if (chip == NULL) { 1118 pci_disable_device(pci); 1119 return -ENOMEM; 1120 } 1121 spin_lock_init(&chip->reg_lock); 1122 chip->device_type = device_type; 1123 chip->card = card; 1124 chip->pci = pci; 1125 chip->irq = -1; 1126 1127 if ((err = pci_request_regions(pci, card->shortname)) < 0) { 1128 kfree(chip); 1129 pci_disable_device(pci); 1130 return err; 1131 } 1132 1133 if (device_type == DEVICE_ALI) { 1134 /* ALI5455 has no ac97 region */ 1135 chip->bmaddr = pci_resource_start(pci, 0); 1136 goto port_inited; 1137 } 1138 1139 if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) { /* ICH4 and Nforce */ 1140 chip->mmio = 1; 1141 chip->addr = pci_resource_start(pci, 2); 1142 chip->remap_addr = ioremap_nocache(chip->addr, 1143 pci_resource_len(pci, 2)); 1144 if (chip->remap_addr == NULL) { 1145 snd_printk(KERN_ERR "AC'97 space ioremap problem\n"); 1146 snd_intel8x0_free(chip); 1147 return -EIO; 1148 } 1149 } else { 1150 chip->addr = pci_resource_start(pci, 0); 1151 } 1152 if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) { /* ICH4 */ 1153 chip->bm_mmio = 1; 1154 chip->bmaddr = pci_resource_start(pci, 3); 1155 chip->remap_bmaddr = ioremap_nocache(chip->bmaddr, 1156 pci_resource_len(pci, 3)); 1157 if (chip->remap_bmaddr == NULL) { 1158 snd_printk(KERN_ERR "Controller space ioremap problem\n"); 1159 snd_intel8x0_free(chip); 1160 return -EIO; 1161 } 1162 } else { 1163 chip->bmaddr = pci_resource_start(pci, 1); 1164 } 1165 1166 port_inited: 1167 if (request_irq(pci->irq, snd_intel8x0_interrupt, SA_INTERRUPT|SA_SHIRQ, card->shortname, (void *)chip)) { 1168 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq); 1169 snd_intel8x0_free(chip); 1170 return -EBUSY; 1171 } 1172 chip->irq = pci->irq; 1173 pci_set_master(pci); 1174 synchronize_irq(chip->irq); 1175 1176 /* initialize offsets */ 1177 chip->bdbars_count = 2; 1178 tbl = intel_regs; 1179 1180 for (i = 0; i < chip->bdbars_count; i++) { 1181 ichdev = &chip->ichd[i]; 1182 ichdev->ichd = i; 1183 ichdev->reg_offset = tbl[i].offset; 1184 ichdev->int_sta_mask = tbl[i].int_sta_mask; 1185 if (device_type == DEVICE_SIS) { 1186 /* SiS 7013 swaps the registers */ 1187 ichdev->roff_sr = ICH_REG_OFF_PICB; 1188 ichdev->roff_picb = ICH_REG_OFF_SR; 1189 } else { 1190 ichdev->roff_sr = ICH_REG_OFF_SR; 1191 ichdev->roff_picb = ICH_REG_OFF_PICB; 1192 } 1193 if (device_type == DEVICE_ALI) 1194 ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10; 1195 } 1196 /* SIS7013 handles the pcm data in bytes, others are in words */ 1197 chip->pcm_pos_shift = (device_type == DEVICE_SIS) ? 0 : 1; 1198 1199 /* allocate buffer descriptor lists */ 1200 /* the start of each lists must be aligned to 8 bytes */ 1201 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci), 1202 chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2, 1203 &chip->bdbars) < 0) { 1204 snd_intel8x0_free(chip); 1205 return -ENOMEM; 1206 } 1207 /* tables must be aligned to 8 bytes here, but the kernel pages 1208 are much bigger, so we don't care (on i386) */ 1209 int_sta_masks = 0; 1210 for (i = 0; i < chip->bdbars_count; i++) { 1211 ichdev = &chip->ichd[i]; 1212 ichdev->bdbar = ((u32 *)chip->bdbars.area) + (i * ICH_MAX_FRAGS * 2); 1213 ichdev->bdbar_addr = chip->bdbars.addr + (i * sizeof(u32) * ICH_MAX_FRAGS * 2); 1214 int_sta_masks |= ichdev->int_sta_mask; 1215 } 1216 chip->int_sta_reg = ICH_REG_GLOB_STA; 1217 chip->int_sta_mask = int_sta_masks; 1218 1219 if ((err = snd_intel8x0_chip_init(chip, 1)) < 0) { 1220 snd_intel8x0_free(chip); 1221 return err; 1222 } 1223 1224 snd_card_set_pm_callback(card, intel8x0m_suspend, intel8x0m_resume, chip); 1225 1226 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) { 1227 snd_intel8x0_free(chip); 1228 return err; 1229 } 1230 1231 snd_card_set_dev(card, &pci->dev); 1232 1233 *r_intel8x0 = chip; 1234 return 0; 1235 } 1236 1237 static struct shortname_table { 1238 unsigned int id; 1239 const char *s; 1240 } shortnames[] __devinitdata = { 1241 { PCI_DEVICE_ID_INTEL_82801AA_6, "Intel 82801AA-ICH" }, 1242 { PCI_DEVICE_ID_INTEL_82801AB_6, "Intel 82901AB-ICH0" }, 1243 { PCI_DEVICE_ID_INTEL_82801BA_6, "Intel 82801BA-ICH2" }, 1244 { PCI_DEVICE_ID_INTEL_440MX_6, "Intel 440MX" }, 1245 { PCI_DEVICE_ID_INTEL_82801CA_6, "Intel 82801CA-ICH3" }, 1246 { PCI_DEVICE_ID_INTEL_82801DB_6, "Intel 82801DB-ICH4" }, 1247 { PCI_DEVICE_ID_INTEL_82801EB_6, "Intel ICH5" }, 1248 { PCI_DEVICE_ID_INTEL_ICH6_17, "Intel ICH6" }, 1249 { PCI_DEVICE_ID_INTEL_ICH7_19, "Intel ICH7" }, 1250 { 0x7446, "AMD AMD768" }, 1251 { PCI_DEVICE_ID_SI_7013, "SiS SI7013" }, 1252 { PCI_DEVICE_ID_NVIDIA_MCP1_MODEM, "NVidia nForce" }, 1253 { PCI_DEVICE_ID_NVIDIA_MCP2_MODEM, "NVidia nForce2" }, 1254 { PCI_DEVICE_ID_NVIDIA_MCP2S_MODEM, "NVidia nForce2s" }, 1255 { PCI_DEVICE_ID_NVIDIA_MCP3_MODEM, "NVidia nForce3" }, 1256 #if 0 1257 { 0x5455, "ALi M5455" }, 1258 { 0x746d, "AMD AMD8111" }, 1259 #endif 1260 { 0 }, 1261 }; 1262 1263 static int __devinit snd_intel8x0m_probe(struct pci_dev *pci, 1264 const struct pci_device_id *pci_id) 1265 { 1266 snd_card_t *card; 1267 intel8x0_t *chip; 1268 int err; 1269 struct shortname_table *name; 1270 1271 card = snd_card_new(index, id, THIS_MODULE, 0); 1272 if (card == NULL) 1273 return -ENOMEM; 1274 1275 strcpy(card->driver, "ICH-MODEM"); 1276 strcpy(card->shortname, "Intel ICH"); 1277 for (name = shortnames; name->id; name++) { 1278 if (pci->device == name->id) { 1279 strcpy(card->shortname, name->s); 1280 break; 1281 } 1282 } 1283 strcat(card->shortname," Modem"); 1284 1285 if ((err = snd_intel8x0m_create(card, pci, pci_id->driver_data, &chip)) < 0) { 1286 snd_card_free(card); 1287 return err; 1288 } 1289 1290 if ((err = snd_intel8x0_mixer(chip, ac97_clock)) < 0) { 1291 snd_card_free(card); 1292 return err; 1293 } 1294 if ((err = snd_intel8x0_pcm(chip)) < 0) { 1295 snd_card_free(card); 1296 return err; 1297 } 1298 1299 snd_intel8x0m_proc_init(chip); 1300 1301 sprintf(card->longname, "%s at 0x%lx, irq %i", 1302 card->shortname, chip->addr, chip->irq); 1303 1304 if ((err = snd_card_register(card)) < 0) { 1305 snd_card_free(card); 1306 return err; 1307 } 1308 pci_set_drvdata(pci, card); 1309 return 0; 1310 } 1311 1312 static void __devexit snd_intel8x0m_remove(struct pci_dev *pci) 1313 { 1314 snd_card_free(pci_get_drvdata(pci)); 1315 pci_set_drvdata(pci, NULL); 1316 } 1317 1318 static struct pci_driver driver = { 1319 .name = "Intel ICH Modem", 1320 .id_table = snd_intel8x0m_ids, 1321 .probe = snd_intel8x0m_probe, 1322 .remove = __devexit_p(snd_intel8x0m_remove), 1323 SND_PCI_PM_CALLBACKS 1324 }; 1325 1326 1327 static int __init alsa_card_intel8x0m_init(void) 1328 { 1329 return pci_register_driver(&driver); 1330 } 1331 1332 static void __exit alsa_card_intel8x0m_exit(void) 1333 { 1334 pci_unregister_driver(&driver); 1335 } 1336 1337 module_init(alsa_card_intel8x0m_init) 1338 module_exit(alsa_card_intel8x0m_exit) 1339