1 /* 2 * ALSA driver for Intel ICH (i8x0) chipsets 3 * 4 * Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz> 5 * 6 * 7 * This code also contains alpha support for SiS 735 chipsets provided 8 * by Mike Pieper <mptei@users.sourceforge.net>. We have no datasheet 9 * for SiS735, so the code is not fully functional. 10 * 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License as published by 14 * the Free Software Foundation; either version 2 of the License, or 15 * (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 25 26 * 27 */ 28 29 #include <linux/io.h> 30 #include <linux/delay.h> 31 #include <linux/interrupt.h> 32 #include <linux/init.h> 33 #include <linux/pci.h> 34 #include <linux/slab.h> 35 #include <linux/module.h> 36 #include <sound/core.h> 37 #include <sound/pcm.h> 38 #include <sound/ac97_codec.h> 39 #include <sound/info.h> 40 #include <sound/initval.h> 41 /* for 440MX workaround */ 42 #include <asm/pgtable.h> 43 #include <asm/cacheflush.h> 44 45 MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>"); 46 MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; SiS 7012; Ali 5455"); 47 MODULE_LICENSE("GPL"); 48 MODULE_SUPPORTED_DEVICE("{{Intel,82801AA-ICH}," 49 "{Intel,82901AB-ICH0}," 50 "{Intel,82801BA-ICH2}," 51 "{Intel,82801CA-ICH3}," 52 "{Intel,82801DB-ICH4}," 53 "{Intel,ICH5}," 54 "{Intel,ICH6}," 55 "{Intel,ICH7}," 56 "{Intel,6300ESB}," 57 "{Intel,ESB2}," 58 "{Intel,MX440}," 59 "{SiS,SI7012}," 60 "{NVidia,nForce Audio}," 61 "{NVidia,nForce2 Audio}," 62 "{NVidia,nForce3 Audio}," 63 "{NVidia,MCP04}," 64 "{NVidia,MCP501}," 65 "{NVidia,CK804}," 66 "{NVidia,CK8}," 67 "{NVidia,CK8S}," 68 "{AMD,AMD768}," 69 "{AMD,AMD8111}," 70 "{ALI,M5455}}"); 71 72 static int index = SNDRV_DEFAULT_IDX1; /* Index 0-MAX */ 73 static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */ 74 static int ac97_clock; 75 static char *ac97_quirk; 76 static bool buggy_semaphore; 77 static int buggy_irq = -1; /* auto-check */ 78 static bool xbox; 79 static int spdif_aclink = -1; 80 static int inside_vm = -1; 81 82 module_param(index, int, 0444); 83 MODULE_PARM_DESC(index, "Index value for Intel i8x0 soundcard."); 84 module_param(id, charp, 0444); 85 MODULE_PARM_DESC(id, "ID string for Intel i8x0 soundcard."); 86 module_param(ac97_clock, int, 0444); 87 MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = whitelist + auto-detect, 1 = force autodetect)."); 88 module_param(ac97_quirk, charp, 0444); 89 MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware."); 90 module_param(buggy_semaphore, bool, 0444); 91 MODULE_PARM_DESC(buggy_semaphore, "Enable workaround for hardwares with problematic codec semaphores."); 92 module_param(buggy_irq, bint, 0444); 93 MODULE_PARM_DESC(buggy_irq, "Enable workaround for buggy interrupts on some motherboards."); 94 module_param(xbox, bool, 0444); 95 MODULE_PARM_DESC(xbox, "Set to 1 for Xbox, if you have problems with the AC'97 codec detection."); 96 module_param(spdif_aclink, int, 0444); 97 MODULE_PARM_DESC(spdif_aclink, "S/PDIF over AC-link."); 98 module_param(inside_vm, bint, 0444); 99 MODULE_PARM_DESC(inside_vm, "KVM/Parallels optimization."); 100 101 /* just for backward compatibility */ 102 static bool enable; 103 module_param(enable, bool, 0444); 104 static int joystick; 105 module_param(joystick, int, 0444); 106 107 /* 108 * Direct registers 109 */ 110 enum { DEVICE_INTEL, DEVICE_INTEL_ICH4, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE }; 111 112 #define ICHREG(x) ICH_REG_##x 113 114 #define DEFINE_REGSET(name,base) \ 115 enum { \ 116 ICH_REG_##name##_BDBAR = base + 0x0, /* dword - buffer descriptor list base address */ \ 117 ICH_REG_##name##_CIV = base + 0x04, /* byte - current index value */ \ 118 ICH_REG_##name##_LVI = base + 0x05, /* byte - last valid index */ \ 119 ICH_REG_##name##_SR = base + 0x06, /* byte - status register */ \ 120 ICH_REG_##name##_PICB = base + 0x08, /* word - position in current buffer */ \ 121 ICH_REG_##name##_PIV = base + 0x0a, /* byte - prefetched index value */ \ 122 ICH_REG_##name##_CR = base + 0x0b, /* byte - control register */ \ 123 }; 124 125 /* busmaster blocks */ 126 DEFINE_REGSET(OFF, 0); /* offset */ 127 DEFINE_REGSET(PI, 0x00); /* PCM in */ 128 DEFINE_REGSET(PO, 0x10); /* PCM out */ 129 DEFINE_REGSET(MC, 0x20); /* Mic in */ 130 131 /* ICH4 busmaster blocks */ 132 DEFINE_REGSET(MC2, 0x40); /* Mic in 2 */ 133 DEFINE_REGSET(PI2, 0x50); /* PCM in 2 */ 134 DEFINE_REGSET(SP, 0x60); /* SPDIF out */ 135 136 /* values for each busmaster block */ 137 138 /* LVI */ 139 #define ICH_REG_LVI_MASK 0x1f 140 141 /* SR */ 142 #define ICH_FIFOE 0x10 /* FIFO error */ 143 #define ICH_BCIS 0x08 /* buffer completion interrupt status */ 144 #define ICH_LVBCI 0x04 /* last valid buffer completion interrupt */ 145 #define ICH_CELV 0x02 /* current equals last valid */ 146 #define ICH_DCH 0x01 /* DMA controller halted */ 147 148 /* PIV */ 149 #define ICH_REG_PIV_MASK 0x1f /* mask */ 150 151 /* CR */ 152 #define ICH_IOCE 0x10 /* interrupt on completion enable */ 153 #define ICH_FEIE 0x08 /* fifo error interrupt enable */ 154 #define ICH_LVBIE 0x04 /* last valid buffer interrupt enable */ 155 #define ICH_RESETREGS 0x02 /* reset busmaster registers */ 156 #define ICH_STARTBM 0x01 /* start busmaster operation */ 157 158 159 /* global block */ 160 #define ICH_REG_GLOB_CNT 0x2c /* dword - global control */ 161 #define ICH_PCM_SPDIF_MASK 0xc0000000 /* s/pdif pcm slot mask (ICH4) */ 162 #define ICH_PCM_SPDIF_NONE 0x00000000 /* reserved - undefined */ 163 #define ICH_PCM_SPDIF_78 0x40000000 /* s/pdif pcm on slots 7&8 */ 164 #define ICH_PCM_SPDIF_69 0x80000000 /* s/pdif pcm on slots 6&9 */ 165 #define ICH_PCM_SPDIF_1011 0xc0000000 /* s/pdif pcm on slots 10&11 */ 166 #define ICH_PCM_20BIT 0x00400000 /* 20-bit samples (ICH4) */ 167 #define ICH_PCM_246_MASK 0x00300000 /* chan mask (not all chips) */ 168 #define ICH_PCM_8 0x00300000 /* 8 channels (not all chips) */ 169 #define ICH_PCM_6 0x00200000 /* 6 channels (not all chips) */ 170 #define ICH_PCM_4 0x00100000 /* 4 channels (not all chips) */ 171 #define ICH_PCM_2 0x00000000 /* 2 channels (stereo) */ 172 #define ICH_SIS_PCM_246_MASK 0x000000c0 /* 6 channels (SIS7012) */ 173 #define ICH_SIS_PCM_6 0x00000080 /* 6 channels (SIS7012) */ 174 #define ICH_SIS_PCM_4 0x00000040 /* 4 channels (SIS7012) */ 175 #define ICH_SIS_PCM_2 0x00000000 /* 2 channels (SIS7012) */ 176 #define ICH_TRIE 0x00000040 /* tertiary resume interrupt enable */ 177 #define ICH_SRIE 0x00000020 /* secondary resume interrupt enable */ 178 #define ICH_PRIE 0x00000010 /* primary resume interrupt enable */ 179 #define ICH_ACLINK 0x00000008 /* AClink shut off */ 180 #define ICH_AC97WARM 0x00000004 /* AC'97 warm reset */ 181 #define ICH_AC97COLD 0x00000002 /* AC'97 cold reset */ 182 #define ICH_GIE 0x00000001 /* GPI interrupt enable */ 183 #define ICH_REG_GLOB_STA 0x30 /* dword - global status */ 184 #define ICH_TRI 0x20000000 /* ICH4: tertiary (AC_SDIN2) resume interrupt */ 185 #define ICH_TCR 0x10000000 /* ICH4: tertiary (AC_SDIN2) codec ready */ 186 #define ICH_BCS 0x08000000 /* ICH4: bit clock stopped */ 187 #define ICH_SPINT 0x04000000 /* ICH4: S/PDIF interrupt */ 188 #define ICH_P2INT 0x02000000 /* ICH4: PCM2-In interrupt */ 189 #define ICH_M2INT 0x01000000 /* ICH4: Mic2-In interrupt */ 190 #define ICH_SAMPLE_CAP 0x00c00000 /* ICH4: sample capability bits (RO) */ 191 #define ICH_SAMPLE_16_20 0x00400000 /* ICH4: 16- and 20-bit samples */ 192 #define ICH_MULTICHAN_CAP 0x00300000 /* ICH4: multi-channel capability bits (RO) */ 193 #define ICH_SIS_TRI 0x00080000 /* SIS: tertiary resume irq */ 194 #define ICH_SIS_TCR 0x00040000 /* SIS: tertiary codec ready */ 195 #define ICH_MD3 0x00020000 /* modem power down semaphore */ 196 #define ICH_AD3 0x00010000 /* audio power down semaphore */ 197 #define ICH_RCS 0x00008000 /* read completion status */ 198 #define ICH_BIT3 0x00004000 /* bit 3 slot 12 */ 199 #define ICH_BIT2 0x00002000 /* bit 2 slot 12 */ 200 #define ICH_BIT1 0x00001000 /* bit 1 slot 12 */ 201 #define ICH_SRI 0x00000800 /* secondary (AC_SDIN1) resume interrupt */ 202 #define ICH_PRI 0x00000400 /* primary (AC_SDIN0) resume interrupt */ 203 #define ICH_SCR 0x00000200 /* secondary (AC_SDIN1) codec ready */ 204 #define ICH_PCR 0x00000100 /* primary (AC_SDIN0) codec ready */ 205 #define ICH_MCINT 0x00000080 /* MIC capture interrupt */ 206 #define ICH_POINT 0x00000040 /* playback interrupt */ 207 #define ICH_PIINT 0x00000020 /* capture interrupt */ 208 #define ICH_NVSPINT 0x00000010 /* nforce spdif interrupt */ 209 #define ICH_MOINT 0x00000004 /* modem playback interrupt */ 210 #define ICH_MIINT 0x00000002 /* modem capture interrupt */ 211 #define ICH_GSCI 0x00000001 /* GPI status change interrupt */ 212 #define ICH_REG_ACC_SEMA 0x34 /* byte - codec write semaphore */ 213 #define ICH_CAS 0x01 /* codec access semaphore */ 214 #define ICH_REG_SDM 0x80 215 #define ICH_DI2L_MASK 0x000000c0 /* PCM In 2, Mic In 2 data in line */ 216 #define ICH_DI2L_SHIFT 6 217 #define ICH_DI1L_MASK 0x00000030 /* PCM In 1, Mic In 1 data in line */ 218 #define ICH_DI1L_SHIFT 4 219 #define ICH_SE 0x00000008 /* steer enable */ 220 #define ICH_LDI_MASK 0x00000003 /* last codec read data input */ 221 222 #define ICH_MAX_FRAGS 32 /* max hw frags */ 223 224 225 /* 226 * registers for Ali5455 227 */ 228 229 /* ALi 5455 busmaster blocks */ 230 DEFINE_REGSET(AL_PI, 0x40); /* ALi PCM in */ 231 DEFINE_REGSET(AL_PO, 0x50); /* Ali PCM out */ 232 DEFINE_REGSET(AL_MC, 0x60); /* Ali Mic in */ 233 DEFINE_REGSET(AL_CDC_SPO, 0x70); /* Ali Codec SPDIF out */ 234 DEFINE_REGSET(AL_CENTER, 0x80); /* Ali center out */ 235 DEFINE_REGSET(AL_LFE, 0x90); /* Ali center out */ 236 DEFINE_REGSET(AL_CLR_SPI, 0xa0); /* Ali Controller SPDIF in */ 237 DEFINE_REGSET(AL_CLR_SPO, 0xb0); /* Ali Controller SPDIF out */ 238 DEFINE_REGSET(AL_I2S, 0xc0); /* Ali I2S in */ 239 DEFINE_REGSET(AL_PI2, 0xd0); /* Ali PCM2 in */ 240 DEFINE_REGSET(AL_MC2, 0xe0); /* Ali Mic2 in */ 241 242 enum { 243 ICH_REG_ALI_SCR = 0x00, /* System Control Register */ 244 ICH_REG_ALI_SSR = 0x04, /* System Status Register */ 245 ICH_REG_ALI_DMACR = 0x08, /* DMA Control Register */ 246 ICH_REG_ALI_FIFOCR1 = 0x0c, /* FIFO Control Register 1 */ 247 ICH_REG_ALI_INTERFACECR = 0x10, /* Interface Control Register */ 248 ICH_REG_ALI_INTERRUPTCR = 0x14, /* Interrupt control Register */ 249 ICH_REG_ALI_INTERRUPTSR = 0x18, /* Interrupt Status Register */ 250 ICH_REG_ALI_FIFOCR2 = 0x1c, /* FIFO Control Register 2 */ 251 ICH_REG_ALI_CPR = 0x20, /* Command Port Register */ 252 ICH_REG_ALI_CPR_ADDR = 0x22, /* ac97 addr write */ 253 ICH_REG_ALI_SPR = 0x24, /* Status Port Register */ 254 ICH_REG_ALI_SPR_ADDR = 0x26, /* ac97 addr read */ 255 ICH_REG_ALI_FIFOCR3 = 0x2c, /* FIFO Control Register 3 */ 256 ICH_REG_ALI_TTSR = 0x30, /* Transmit Tag Slot Register */ 257 ICH_REG_ALI_RTSR = 0x34, /* Receive Tag Slot Register */ 258 ICH_REG_ALI_CSPSR = 0x38, /* Command/Status Port Status Register */ 259 ICH_REG_ALI_CAS = 0x3c, /* Codec Write Semaphore Register */ 260 ICH_REG_ALI_HWVOL = 0xf0, /* hardware volume control/status */ 261 ICH_REG_ALI_I2SCR = 0xf4, /* I2S control/status */ 262 ICH_REG_ALI_SPDIFCSR = 0xf8, /* spdif channel status register */ 263 ICH_REG_ALI_SPDIFICS = 0xfc, /* spdif interface control/status */ 264 }; 265 266 #define ALI_CAS_SEM_BUSY 0x80000000 267 #define ALI_CPR_ADDR_SECONDARY 0x100 268 #define ALI_CPR_ADDR_READ 0x80 269 #define ALI_CSPSR_CODEC_READY 0x08 270 #define ALI_CSPSR_READ_OK 0x02 271 #define ALI_CSPSR_WRITE_OK 0x01 272 273 /* interrupts for the whole chip by interrupt status register finish */ 274 275 #define ALI_INT_MICIN2 (1<<26) 276 #define ALI_INT_PCMIN2 (1<<25) 277 #define ALI_INT_I2SIN (1<<24) 278 #define ALI_INT_SPDIFOUT (1<<23) /* controller spdif out INTERRUPT */ 279 #define ALI_INT_SPDIFIN (1<<22) 280 #define ALI_INT_LFEOUT (1<<21) 281 #define ALI_INT_CENTEROUT (1<<20) 282 #define ALI_INT_CODECSPDIFOUT (1<<19) 283 #define ALI_INT_MICIN (1<<18) 284 #define ALI_INT_PCMOUT (1<<17) 285 #define ALI_INT_PCMIN (1<<16) 286 #define ALI_INT_CPRAIS (1<<7) /* command port available */ 287 #define ALI_INT_SPRAIS (1<<5) /* status port available */ 288 #define ALI_INT_GPIO (1<<1) 289 #define ALI_INT_MASK (ALI_INT_SPDIFOUT|ALI_INT_CODECSPDIFOUT|\ 290 ALI_INT_MICIN|ALI_INT_PCMOUT|ALI_INT_PCMIN) 291 292 #define ICH_ALI_SC_RESET (1<<31) /* master reset */ 293 #define ICH_ALI_SC_AC97_DBL (1<<30) 294 #define ICH_ALI_SC_CODEC_SPDF (3<<20) /* 1=7/8, 2=6/9, 3=10/11 */ 295 #define ICH_ALI_SC_IN_BITS (3<<18) 296 #define ICH_ALI_SC_OUT_BITS (3<<16) 297 #define ICH_ALI_SC_6CH_CFG (3<<14) 298 #define ICH_ALI_SC_PCM_4 (1<<8) 299 #define ICH_ALI_SC_PCM_6 (2<<8) 300 #define ICH_ALI_SC_PCM_246_MASK (3<<8) 301 302 #define ICH_ALI_SS_SEC_ID (3<<5) 303 #define ICH_ALI_SS_PRI_ID (3<<3) 304 305 #define ICH_ALI_IF_AC97SP (1<<21) 306 #define ICH_ALI_IF_MC (1<<20) 307 #define ICH_ALI_IF_PI (1<<19) 308 #define ICH_ALI_IF_MC2 (1<<18) 309 #define ICH_ALI_IF_PI2 (1<<17) 310 #define ICH_ALI_IF_LINE_SRC (1<<15) /* 0/1 = slot 3/6 */ 311 #define ICH_ALI_IF_MIC_SRC (1<<14) /* 0/1 = slot 3/6 */ 312 #define ICH_ALI_IF_SPDF_SRC (3<<12) /* 00 = PCM, 01 = AC97-in, 10 = spdif-in, 11 = i2s */ 313 #define ICH_ALI_IF_AC97_OUT (3<<8) /* 00 = PCM, 10 = spdif-in, 11 = i2s */ 314 #define ICH_ALI_IF_PO_SPDF (1<<3) 315 #define ICH_ALI_IF_PO (1<<1) 316 317 /* 318 * 319 */ 320 321 enum { 322 ICHD_PCMIN, 323 ICHD_PCMOUT, 324 ICHD_MIC, 325 ICHD_MIC2, 326 ICHD_PCM2IN, 327 ICHD_SPBAR, 328 ICHD_LAST = ICHD_SPBAR 329 }; 330 enum { 331 NVD_PCMIN, 332 NVD_PCMOUT, 333 NVD_MIC, 334 NVD_SPBAR, 335 NVD_LAST = NVD_SPBAR 336 }; 337 enum { 338 ALID_PCMIN, 339 ALID_PCMOUT, 340 ALID_MIC, 341 ALID_AC97SPDIFOUT, 342 ALID_SPDIFIN, 343 ALID_SPDIFOUT, 344 ALID_LAST = ALID_SPDIFOUT 345 }; 346 347 #define get_ichdev(substream) (substream->runtime->private_data) 348 349 struct ichdev { 350 unsigned int ichd; /* ich device number */ 351 unsigned long reg_offset; /* offset to bmaddr */ 352 u32 *bdbar; /* CPU address (32bit) */ 353 unsigned int bdbar_addr; /* PCI bus address (32bit) */ 354 struct snd_pcm_substream *substream; 355 unsigned int physbuf; /* physical address (32bit) */ 356 unsigned int size; 357 unsigned int fragsize; 358 unsigned int fragsize1; 359 unsigned int position; 360 unsigned int pos_shift; 361 unsigned int last_pos; 362 int frags; 363 int lvi; 364 int lvi_frag; 365 int civ; 366 int ack; 367 int ack_reload; 368 unsigned int ack_bit; 369 unsigned int roff_sr; 370 unsigned int roff_picb; 371 unsigned int int_sta_mask; /* interrupt status mask */ 372 unsigned int ali_slot; /* ALI DMA slot */ 373 struct ac97_pcm *pcm; 374 int pcm_open_flag; 375 unsigned int page_attr_changed: 1; 376 unsigned int suspended: 1; 377 }; 378 379 struct intel8x0 { 380 unsigned int device_type; 381 382 int irq; 383 384 void __iomem *addr; 385 void __iomem *bmaddr; 386 387 struct pci_dev *pci; 388 struct snd_card *card; 389 390 int pcm_devs; 391 struct snd_pcm *pcm[6]; 392 struct ichdev ichd[6]; 393 394 unsigned multi4: 1, 395 multi6: 1, 396 multi8 :1, 397 dra: 1, 398 smp20bit: 1; 399 unsigned in_ac97_init: 1, 400 in_sdin_init: 1; 401 unsigned in_measurement: 1; /* during ac97 clock measurement */ 402 unsigned fix_nocache: 1; /* workaround for 440MX */ 403 unsigned buggy_irq: 1; /* workaround for buggy mobos */ 404 unsigned xbox: 1; /* workaround for Xbox AC'97 detection */ 405 unsigned buggy_semaphore: 1; /* workaround for buggy codec semaphore */ 406 unsigned inside_vm: 1; /* enable VM optimization */ 407 408 int spdif_idx; /* SPDIF BAR index; *_SPBAR or -1 if use PCMOUT */ 409 unsigned int sdm_saved; /* SDM reg value */ 410 411 struct snd_ac97_bus *ac97_bus; 412 struct snd_ac97 *ac97[3]; 413 unsigned int ac97_sdin[3]; 414 unsigned int max_codecs, ncodecs; 415 unsigned int *codec_bit; 416 unsigned int codec_isr_bits; 417 unsigned int codec_ready_bits; 418 419 spinlock_t reg_lock; 420 421 u32 bdbars_count; 422 struct snd_dma_buffer bdbars; 423 u32 int_sta_reg; /* interrupt status register */ 424 u32 int_sta_mask; /* interrupt status mask */ 425 }; 426 427 static const struct pci_device_id snd_intel8x0_ids[] = { 428 { PCI_VDEVICE(INTEL, 0x2415), DEVICE_INTEL }, /* 82801AA */ 429 { PCI_VDEVICE(INTEL, 0x2425), DEVICE_INTEL }, /* 82901AB */ 430 { PCI_VDEVICE(INTEL, 0x2445), DEVICE_INTEL }, /* 82801BA */ 431 { PCI_VDEVICE(INTEL, 0x2485), DEVICE_INTEL }, /* ICH3 */ 432 { PCI_VDEVICE(INTEL, 0x24c5), DEVICE_INTEL_ICH4 }, /* ICH4 */ 433 { PCI_VDEVICE(INTEL, 0x24d5), DEVICE_INTEL_ICH4 }, /* ICH5 */ 434 { PCI_VDEVICE(INTEL, 0x25a6), DEVICE_INTEL_ICH4 }, /* ESB */ 435 { PCI_VDEVICE(INTEL, 0x266e), DEVICE_INTEL_ICH4 }, /* ICH6 */ 436 { PCI_VDEVICE(INTEL, 0x27de), DEVICE_INTEL_ICH4 }, /* ICH7 */ 437 { PCI_VDEVICE(INTEL, 0x2698), DEVICE_INTEL_ICH4 }, /* ESB2 */ 438 { PCI_VDEVICE(INTEL, 0x7195), DEVICE_INTEL }, /* 440MX */ 439 { PCI_VDEVICE(SI, 0x7012), DEVICE_SIS }, /* SI7012 */ 440 { PCI_VDEVICE(NVIDIA, 0x01b1), DEVICE_NFORCE }, /* NFORCE */ 441 { PCI_VDEVICE(NVIDIA, 0x003a), DEVICE_NFORCE }, /* MCP04 */ 442 { PCI_VDEVICE(NVIDIA, 0x006a), DEVICE_NFORCE }, /* NFORCE2 */ 443 { PCI_VDEVICE(NVIDIA, 0x0059), DEVICE_NFORCE }, /* CK804 */ 444 { PCI_VDEVICE(NVIDIA, 0x008a), DEVICE_NFORCE }, /* CK8 */ 445 { PCI_VDEVICE(NVIDIA, 0x00da), DEVICE_NFORCE }, /* NFORCE3 */ 446 { PCI_VDEVICE(NVIDIA, 0x00ea), DEVICE_NFORCE }, /* CK8S */ 447 { PCI_VDEVICE(NVIDIA, 0x026b), DEVICE_NFORCE }, /* MCP51 */ 448 { PCI_VDEVICE(AMD, 0x746d), DEVICE_INTEL }, /* AMD8111 */ 449 { PCI_VDEVICE(AMD, 0x7445), DEVICE_INTEL }, /* AMD768 */ 450 { PCI_VDEVICE(AL, 0x5455), DEVICE_ALI }, /* Ali5455 */ 451 { 0, } 452 }; 453 454 MODULE_DEVICE_TABLE(pci, snd_intel8x0_ids); 455 456 /* 457 * Lowlevel I/O - busmaster 458 */ 459 460 static inline u8 igetbyte(struct intel8x0 *chip, u32 offset) 461 { 462 return ioread8(chip->bmaddr + offset); 463 } 464 465 static inline u16 igetword(struct intel8x0 *chip, u32 offset) 466 { 467 return ioread16(chip->bmaddr + offset); 468 } 469 470 static inline u32 igetdword(struct intel8x0 *chip, u32 offset) 471 { 472 return ioread32(chip->bmaddr + offset); 473 } 474 475 static inline void iputbyte(struct intel8x0 *chip, u32 offset, u8 val) 476 { 477 iowrite8(val, chip->bmaddr + offset); 478 } 479 480 static inline void iputword(struct intel8x0 *chip, u32 offset, u16 val) 481 { 482 iowrite16(val, chip->bmaddr + offset); 483 } 484 485 static inline void iputdword(struct intel8x0 *chip, u32 offset, u32 val) 486 { 487 iowrite32(val, chip->bmaddr + offset); 488 } 489 490 /* 491 * Lowlevel I/O - AC'97 registers 492 */ 493 494 static inline u16 iagetword(struct intel8x0 *chip, u32 offset) 495 { 496 return ioread16(chip->addr + offset); 497 } 498 499 static inline void iaputword(struct intel8x0 *chip, u32 offset, u16 val) 500 { 501 iowrite16(val, chip->addr + offset); 502 } 503 504 /* 505 * Basic I/O 506 */ 507 508 /* 509 * access to AC97 codec via normal i/o (for ICH and SIS7012) 510 */ 511 512 static int snd_intel8x0_codec_semaphore(struct intel8x0 *chip, unsigned int codec) 513 { 514 int time; 515 516 if (codec > 2) 517 return -EIO; 518 if (chip->in_sdin_init) { 519 /* we don't know the ready bit assignment at the moment */ 520 /* so we check any */ 521 codec = chip->codec_isr_bits; 522 } else { 523 codec = chip->codec_bit[chip->ac97_sdin[codec]]; 524 } 525 526 /* codec ready ? */ 527 if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0) 528 return -EIO; 529 530 if (chip->buggy_semaphore) 531 return 0; /* just ignore ... */ 532 533 /* Anyone holding a semaphore for 1 msec should be shot... */ 534 time = 100; 535 do { 536 if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS)) 537 return 0; 538 udelay(10); 539 } while (time--); 540 541 /* access to some forbidden (non existent) ac97 registers will not 542 * reset the semaphore. So even if you don't get the semaphore, still 543 * continue the access. We don't need the semaphore anyway. */ 544 dev_err(chip->card->dev, 545 "codec_semaphore: semaphore is not ready [0x%x][0x%x]\n", 546 igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA))); 547 iagetword(chip, 0); /* clear semaphore flag */ 548 /* I don't care about the semaphore */ 549 return -EBUSY; 550 } 551 552 static void snd_intel8x0_codec_write(struct snd_ac97 *ac97, 553 unsigned short reg, 554 unsigned short val) 555 { 556 struct intel8x0 *chip = ac97->private_data; 557 558 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) { 559 if (! chip->in_ac97_init) 560 dev_err(chip->card->dev, 561 "codec_write %d: semaphore is not ready for register 0x%x\n", 562 ac97->num, reg); 563 } 564 iaputword(chip, reg + ac97->num * 0x80, val); 565 } 566 567 static unsigned short snd_intel8x0_codec_read(struct snd_ac97 *ac97, 568 unsigned short reg) 569 { 570 struct intel8x0 *chip = ac97->private_data; 571 unsigned short res; 572 unsigned int tmp; 573 574 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) { 575 if (! chip->in_ac97_init) 576 dev_err(chip->card->dev, 577 "codec_read %d: semaphore is not ready for register 0x%x\n", 578 ac97->num, reg); 579 res = 0xffff; 580 } else { 581 res = iagetword(chip, reg + ac97->num * 0x80); 582 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) { 583 /* reset RCS and preserve other R/WC bits */ 584 iputdword(chip, ICHREG(GLOB_STA), tmp & 585 ~(chip->codec_ready_bits | ICH_GSCI)); 586 if (! chip->in_ac97_init) 587 dev_err(chip->card->dev, 588 "codec_read %d: read timeout for register 0x%x\n", 589 ac97->num, reg); 590 res = 0xffff; 591 } 592 } 593 return res; 594 } 595 596 static void snd_intel8x0_codec_read_test(struct intel8x0 *chip, 597 unsigned int codec) 598 { 599 unsigned int tmp; 600 601 if (snd_intel8x0_codec_semaphore(chip, codec) >= 0) { 602 iagetword(chip, codec * 0x80); 603 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) { 604 /* reset RCS and preserve other R/WC bits */ 605 iputdword(chip, ICHREG(GLOB_STA), tmp & 606 ~(chip->codec_ready_bits | ICH_GSCI)); 607 } 608 } 609 } 610 611 /* 612 * access to AC97 for Ali5455 613 */ 614 static int snd_intel8x0_ali_codec_ready(struct intel8x0 *chip, int mask) 615 { 616 int count = 0; 617 for (count = 0; count < 0x7f; count++) { 618 int val = igetbyte(chip, ICHREG(ALI_CSPSR)); 619 if (val & mask) 620 return 0; 621 } 622 if (! chip->in_ac97_init) 623 dev_warn(chip->card->dev, "AC97 codec ready timeout.\n"); 624 return -EBUSY; 625 } 626 627 static int snd_intel8x0_ali_codec_semaphore(struct intel8x0 *chip) 628 { 629 int time = 100; 630 if (chip->buggy_semaphore) 631 return 0; /* just ignore ... */ 632 while (--time && (igetdword(chip, ICHREG(ALI_CAS)) & ALI_CAS_SEM_BUSY)) 633 udelay(1); 634 if (! time && ! chip->in_ac97_init) 635 dev_warn(chip->card->dev, "ali_codec_semaphore timeout\n"); 636 return snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_CODEC_READY); 637 } 638 639 static unsigned short snd_intel8x0_ali_codec_read(struct snd_ac97 *ac97, unsigned short reg) 640 { 641 struct intel8x0 *chip = ac97->private_data; 642 unsigned short data = 0xffff; 643 644 if (snd_intel8x0_ali_codec_semaphore(chip)) 645 goto __err; 646 reg |= ALI_CPR_ADDR_READ; 647 if (ac97->num) 648 reg |= ALI_CPR_ADDR_SECONDARY; 649 iputword(chip, ICHREG(ALI_CPR_ADDR), reg); 650 if (snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_READ_OK)) 651 goto __err; 652 data = igetword(chip, ICHREG(ALI_SPR)); 653 __err: 654 return data; 655 } 656 657 static void snd_intel8x0_ali_codec_write(struct snd_ac97 *ac97, unsigned short reg, 658 unsigned short val) 659 { 660 struct intel8x0 *chip = ac97->private_data; 661 662 if (snd_intel8x0_ali_codec_semaphore(chip)) 663 return; 664 iputword(chip, ICHREG(ALI_CPR), val); 665 if (ac97->num) 666 reg |= ALI_CPR_ADDR_SECONDARY; 667 iputword(chip, ICHREG(ALI_CPR_ADDR), reg); 668 snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_WRITE_OK); 669 } 670 671 672 /* 673 * DMA I/O 674 */ 675 static void snd_intel8x0_setup_periods(struct intel8x0 *chip, struct ichdev *ichdev) 676 { 677 int idx; 678 u32 *bdbar = ichdev->bdbar; 679 unsigned long port = ichdev->reg_offset; 680 681 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr); 682 if (ichdev->size == ichdev->fragsize) { 683 ichdev->ack_reload = ichdev->ack = 2; 684 ichdev->fragsize1 = ichdev->fragsize >> 1; 685 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) { 686 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf); 687 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */ 688 ichdev->fragsize1 >> ichdev->pos_shift); 689 bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1)); 690 bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */ 691 ichdev->fragsize1 >> ichdev->pos_shift); 692 } 693 ichdev->frags = 2; 694 } else { 695 ichdev->ack_reload = ichdev->ack = 1; 696 ichdev->fragsize1 = ichdev->fragsize; 697 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) { 698 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf + 699 (((idx >> 1) * ichdev->fragsize) % 700 ichdev->size)); 701 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */ 702 ichdev->fragsize >> ichdev->pos_shift); 703 #if 0 704 dev_dbg(chip->card->dev, "bdbar[%i] = 0x%x [0x%x]\n", 705 idx + 0, bdbar[idx + 0], bdbar[idx + 1]); 706 #endif 707 } 708 ichdev->frags = ichdev->size / ichdev->fragsize; 709 } 710 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK); 711 ichdev->civ = 0; 712 iputbyte(chip, port + ICH_REG_OFF_CIV, 0); 713 ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags; 714 ichdev->position = 0; 715 #if 0 716 dev_dbg(chip->card->dev, 717 "lvi_frag = %i, frags = %i, period_size = 0x%x, period_size1 = 0x%x\n", 718 ichdev->lvi_frag, ichdev->frags, ichdev->fragsize, 719 ichdev->fragsize1); 720 #endif 721 /* clear interrupts */ 722 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI); 723 } 724 725 #ifdef __i386__ 726 /* 727 * Intel 82443MX running a 100MHz processor system bus has a hardware bug, 728 * which aborts PCI busmaster for audio transfer. A workaround is to set 729 * the pages as non-cached. For details, see the errata in 730 * http://download.intel.com/design/chipsets/specupdt/24505108.pdf 731 */ 732 static void fill_nocache(void *buf, int size, int nocache) 733 { 734 size = (size + PAGE_SIZE - 1) >> PAGE_SHIFT; 735 if (nocache) 736 set_pages_uc(virt_to_page(buf), size); 737 else 738 set_pages_wb(virt_to_page(buf), size); 739 } 740 #else 741 #define fill_nocache(buf, size, nocache) do { ; } while (0) 742 #endif 743 744 /* 745 * Interrupt handler 746 */ 747 748 static inline void snd_intel8x0_update(struct intel8x0 *chip, struct ichdev *ichdev) 749 { 750 unsigned long port = ichdev->reg_offset; 751 unsigned long flags; 752 int status, civ, i, step; 753 int ack = 0; 754 755 spin_lock_irqsave(&chip->reg_lock, flags); 756 status = igetbyte(chip, port + ichdev->roff_sr); 757 civ = igetbyte(chip, port + ICH_REG_OFF_CIV); 758 if (!(status & ICH_BCIS)) { 759 step = 0; 760 } else if (civ == ichdev->civ) { 761 // snd_printd("civ same %d\n", civ); 762 step = 1; 763 ichdev->civ++; 764 ichdev->civ &= ICH_REG_LVI_MASK; 765 } else { 766 step = civ - ichdev->civ; 767 if (step < 0) 768 step += ICH_REG_LVI_MASK + 1; 769 // if (step != 1) 770 // snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ); 771 ichdev->civ = civ; 772 } 773 774 ichdev->position += step * ichdev->fragsize1; 775 if (! chip->in_measurement) 776 ichdev->position %= ichdev->size; 777 ichdev->lvi += step; 778 ichdev->lvi &= ICH_REG_LVI_MASK; 779 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi); 780 for (i = 0; i < step; i++) { 781 ichdev->lvi_frag++; 782 ichdev->lvi_frag %= ichdev->frags; 783 ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + ichdev->lvi_frag * ichdev->fragsize1); 784 #if 0 785 dev_dbg(chip->card->dev, 786 "new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, all = 0x%x, 0x%x\n", 787 ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2], 788 ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port), 789 inl(port + 4), inb(port + ICH_REG_OFF_CR)); 790 #endif 791 if (--ichdev->ack == 0) { 792 ichdev->ack = ichdev->ack_reload; 793 ack = 1; 794 } 795 } 796 spin_unlock_irqrestore(&chip->reg_lock, flags); 797 if (ack && ichdev->substream) { 798 snd_pcm_period_elapsed(ichdev->substream); 799 } 800 iputbyte(chip, port + ichdev->roff_sr, 801 status & (ICH_FIFOE | ICH_BCIS | ICH_LVBCI)); 802 } 803 804 static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id) 805 { 806 struct intel8x0 *chip = dev_id; 807 struct ichdev *ichdev; 808 unsigned int status; 809 unsigned int i; 810 811 status = igetdword(chip, chip->int_sta_reg); 812 if (status == 0xffffffff) /* we are not yet resumed */ 813 return IRQ_NONE; 814 815 if ((status & chip->int_sta_mask) == 0) { 816 if (status) { 817 /* ack */ 818 iputdword(chip, chip->int_sta_reg, status); 819 if (! chip->buggy_irq) 820 status = 0; 821 } 822 return IRQ_RETVAL(status); 823 } 824 825 for (i = 0; i < chip->bdbars_count; i++) { 826 ichdev = &chip->ichd[i]; 827 if (status & ichdev->int_sta_mask) 828 snd_intel8x0_update(chip, ichdev); 829 } 830 831 /* ack them */ 832 iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask); 833 834 return IRQ_HANDLED; 835 } 836 837 /* 838 * PCM part 839 */ 840 841 static int snd_intel8x0_pcm_trigger(struct snd_pcm_substream *substream, int cmd) 842 { 843 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 844 struct ichdev *ichdev = get_ichdev(substream); 845 unsigned char val = 0; 846 unsigned long port = ichdev->reg_offset; 847 848 switch (cmd) { 849 case SNDRV_PCM_TRIGGER_RESUME: 850 ichdev->suspended = 0; 851 /* fallthru */ 852 case SNDRV_PCM_TRIGGER_START: 853 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 854 val = ICH_IOCE | ICH_STARTBM; 855 ichdev->last_pos = ichdev->position; 856 break; 857 case SNDRV_PCM_TRIGGER_SUSPEND: 858 ichdev->suspended = 1; 859 /* fallthru */ 860 case SNDRV_PCM_TRIGGER_STOP: 861 val = 0; 862 break; 863 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 864 val = ICH_IOCE; 865 break; 866 default: 867 return -EINVAL; 868 } 869 iputbyte(chip, port + ICH_REG_OFF_CR, val); 870 if (cmd == SNDRV_PCM_TRIGGER_STOP) { 871 /* wait until DMA stopped */ 872 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ; 873 /* reset whole DMA things */ 874 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS); 875 } 876 return 0; 877 } 878 879 static int snd_intel8x0_ali_trigger(struct snd_pcm_substream *substream, int cmd) 880 { 881 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 882 struct ichdev *ichdev = get_ichdev(substream); 883 unsigned long port = ichdev->reg_offset; 884 static int fiforeg[] = { 885 ICHREG(ALI_FIFOCR1), ICHREG(ALI_FIFOCR2), ICHREG(ALI_FIFOCR3) 886 }; 887 unsigned int val, fifo; 888 889 val = igetdword(chip, ICHREG(ALI_DMACR)); 890 switch (cmd) { 891 case SNDRV_PCM_TRIGGER_RESUME: 892 ichdev->suspended = 0; 893 /* fallthru */ 894 case SNDRV_PCM_TRIGGER_START: 895 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 896 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 897 /* clear FIFO for synchronization of channels */ 898 fifo = igetdword(chip, fiforeg[ichdev->ali_slot / 4]); 899 fifo &= ~(0xff << (ichdev->ali_slot % 4)); 900 fifo |= 0x83 << (ichdev->ali_slot % 4); 901 iputdword(chip, fiforeg[ichdev->ali_slot / 4], fifo); 902 } 903 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE); 904 val &= ~(1 << (ichdev->ali_slot + 16)); /* clear PAUSE flag */ 905 /* start DMA */ 906 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << ichdev->ali_slot)); 907 break; 908 case SNDRV_PCM_TRIGGER_SUSPEND: 909 ichdev->suspended = 1; 910 /* fallthru */ 911 case SNDRV_PCM_TRIGGER_STOP: 912 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 913 /* pause */ 914 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << (ichdev->ali_slot + 16))); 915 iputbyte(chip, port + ICH_REG_OFF_CR, 0); 916 while (igetbyte(chip, port + ICH_REG_OFF_CR)) 917 ; 918 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH) 919 break; 920 /* reset whole DMA things */ 921 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS); 922 /* clear interrupts */ 923 iputbyte(chip, port + ICH_REG_OFF_SR, 924 igetbyte(chip, port + ICH_REG_OFF_SR) | 0x1e); 925 iputdword(chip, ICHREG(ALI_INTERRUPTSR), 926 igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ichdev->int_sta_mask); 927 break; 928 default: 929 return -EINVAL; 930 } 931 return 0; 932 } 933 934 static int snd_intel8x0_hw_params(struct snd_pcm_substream *substream, 935 struct snd_pcm_hw_params *hw_params) 936 { 937 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 938 struct ichdev *ichdev = get_ichdev(substream); 939 struct snd_pcm_runtime *runtime = substream->runtime; 940 int dbl = params_rate(hw_params) > 48000; 941 int err; 942 943 if (chip->fix_nocache && ichdev->page_attr_changed) { 944 fill_nocache(runtime->dma_area, runtime->dma_bytes, 0); /* clear */ 945 ichdev->page_attr_changed = 0; 946 } 947 err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params)); 948 if (err < 0) 949 return err; 950 if (chip->fix_nocache) { 951 if (runtime->dma_area && ! ichdev->page_attr_changed) { 952 fill_nocache(runtime->dma_area, runtime->dma_bytes, 1); 953 ichdev->page_attr_changed = 1; 954 } 955 } 956 if (ichdev->pcm_open_flag) { 957 snd_ac97_pcm_close(ichdev->pcm); 958 ichdev->pcm_open_flag = 0; 959 } 960 err = snd_ac97_pcm_open(ichdev->pcm, params_rate(hw_params), 961 params_channels(hw_params), 962 ichdev->pcm->r[dbl].slots); 963 if (err >= 0) { 964 ichdev->pcm_open_flag = 1; 965 /* Force SPDIF setting */ 966 if (ichdev->ichd == ICHD_PCMOUT && chip->spdif_idx < 0) 967 snd_ac97_set_rate(ichdev->pcm->r[0].codec[0], AC97_SPDIF, 968 params_rate(hw_params)); 969 } 970 return err; 971 } 972 973 static int snd_intel8x0_hw_free(struct snd_pcm_substream *substream) 974 { 975 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 976 struct ichdev *ichdev = get_ichdev(substream); 977 978 if (ichdev->pcm_open_flag) { 979 snd_ac97_pcm_close(ichdev->pcm); 980 ichdev->pcm_open_flag = 0; 981 } 982 if (chip->fix_nocache && ichdev->page_attr_changed) { 983 fill_nocache(substream->runtime->dma_area, substream->runtime->dma_bytes, 0); 984 ichdev->page_attr_changed = 0; 985 } 986 return snd_pcm_lib_free_pages(substream); 987 } 988 989 static void snd_intel8x0_setup_pcm_out(struct intel8x0 *chip, 990 struct snd_pcm_runtime *runtime) 991 { 992 unsigned int cnt; 993 int dbl = runtime->rate > 48000; 994 995 spin_lock_irq(&chip->reg_lock); 996 switch (chip->device_type) { 997 case DEVICE_ALI: 998 cnt = igetdword(chip, ICHREG(ALI_SCR)); 999 cnt &= ~ICH_ALI_SC_PCM_246_MASK; 1000 if (runtime->channels == 4 || dbl) 1001 cnt |= ICH_ALI_SC_PCM_4; 1002 else if (runtime->channels == 6) 1003 cnt |= ICH_ALI_SC_PCM_6; 1004 iputdword(chip, ICHREG(ALI_SCR), cnt); 1005 break; 1006 case DEVICE_SIS: 1007 cnt = igetdword(chip, ICHREG(GLOB_CNT)); 1008 cnt &= ~ICH_SIS_PCM_246_MASK; 1009 if (runtime->channels == 4 || dbl) 1010 cnt |= ICH_SIS_PCM_4; 1011 else if (runtime->channels == 6) 1012 cnt |= ICH_SIS_PCM_6; 1013 iputdword(chip, ICHREG(GLOB_CNT), cnt); 1014 break; 1015 default: 1016 cnt = igetdword(chip, ICHREG(GLOB_CNT)); 1017 cnt &= ~(ICH_PCM_246_MASK | ICH_PCM_20BIT); 1018 if (runtime->channels == 4 || dbl) 1019 cnt |= ICH_PCM_4; 1020 else if (runtime->channels == 6) 1021 cnt |= ICH_PCM_6; 1022 else if (runtime->channels == 8) 1023 cnt |= ICH_PCM_8; 1024 if (chip->device_type == DEVICE_NFORCE) { 1025 /* reset to 2ch once to keep the 6 channel data in alignment, 1026 * to start from Front Left always 1027 */ 1028 if (cnt & ICH_PCM_246_MASK) { 1029 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_PCM_246_MASK); 1030 spin_unlock_irq(&chip->reg_lock); 1031 msleep(50); /* grrr... */ 1032 spin_lock_irq(&chip->reg_lock); 1033 } 1034 } else if (chip->device_type == DEVICE_INTEL_ICH4) { 1035 if (runtime->sample_bits > 16) 1036 cnt |= ICH_PCM_20BIT; 1037 } 1038 iputdword(chip, ICHREG(GLOB_CNT), cnt); 1039 break; 1040 } 1041 spin_unlock_irq(&chip->reg_lock); 1042 } 1043 1044 static int snd_intel8x0_pcm_prepare(struct snd_pcm_substream *substream) 1045 { 1046 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1047 struct snd_pcm_runtime *runtime = substream->runtime; 1048 struct ichdev *ichdev = get_ichdev(substream); 1049 1050 ichdev->physbuf = runtime->dma_addr; 1051 ichdev->size = snd_pcm_lib_buffer_bytes(substream); 1052 ichdev->fragsize = snd_pcm_lib_period_bytes(substream); 1053 if (ichdev->ichd == ICHD_PCMOUT) { 1054 snd_intel8x0_setup_pcm_out(chip, runtime); 1055 if (chip->device_type == DEVICE_INTEL_ICH4) 1056 ichdev->pos_shift = (runtime->sample_bits > 16) ? 2 : 1; 1057 } 1058 snd_intel8x0_setup_periods(chip, ichdev); 1059 return 0; 1060 } 1061 1062 static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(struct snd_pcm_substream *substream) 1063 { 1064 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1065 struct ichdev *ichdev = get_ichdev(substream); 1066 size_t ptr1, ptr; 1067 int civ, timeout = 10; 1068 unsigned int position; 1069 1070 spin_lock(&chip->reg_lock); 1071 do { 1072 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV); 1073 ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb); 1074 position = ichdev->position; 1075 if (ptr1 == 0) { 1076 udelay(10); 1077 continue; 1078 } 1079 if (civ != igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV)) 1080 continue; 1081 1082 /* IO read operation is very expensive inside virtual machine 1083 * as it is emulated. The probability that subsequent PICB read 1084 * will return different result is high enough to loop till 1085 * timeout here. 1086 * Same CIV is strict enough condition to be sure that PICB 1087 * is valid inside VM on emulated card. */ 1088 if (chip->inside_vm) 1089 break; 1090 if (ptr1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb)) 1091 break; 1092 } while (timeout--); 1093 ptr = ichdev->last_pos; 1094 if (ptr1 != 0) { 1095 ptr1 <<= ichdev->pos_shift; 1096 ptr = ichdev->fragsize1 - ptr1; 1097 ptr += position; 1098 if (ptr < ichdev->last_pos) { 1099 unsigned int pos_base, last_base; 1100 pos_base = position / ichdev->fragsize1; 1101 last_base = ichdev->last_pos / ichdev->fragsize1; 1102 /* another sanity check; ptr1 can go back to full 1103 * before the base position is updated 1104 */ 1105 if (pos_base == last_base) 1106 ptr = ichdev->last_pos; 1107 } 1108 } 1109 ichdev->last_pos = ptr; 1110 spin_unlock(&chip->reg_lock); 1111 if (ptr >= ichdev->size) 1112 return 0; 1113 return bytes_to_frames(substream->runtime, ptr); 1114 } 1115 1116 static struct snd_pcm_hardware snd_intel8x0_stream = 1117 { 1118 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 1119 SNDRV_PCM_INFO_BLOCK_TRANSFER | 1120 SNDRV_PCM_INFO_MMAP_VALID | 1121 SNDRV_PCM_INFO_PAUSE | 1122 SNDRV_PCM_INFO_RESUME), 1123 .formats = SNDRV_PCM_FMTBIT_S16_LE, 1124 .rates = SNDRV_PCM_RATE_48000, 1125 .rate_min = 48000, 1126 .rate_max = 48000, 1127 .channels_min = 2, 1128 .channels_max = 2, 1129 .buffer_bytes_max = 128 * 1024, 1130 .period_bytes_min = 32, 1131 .period_bytes_max = 128 * 1024, 1132 .periods_min = 1, 1133 .periods_max = 1024, 1134 .fifo_size = 0, 1135 }; 1136 1137 static unsigned int channels4[] = { 1138 2, 4, 1139 }; 1140 1141 static struct snd_pcm_hw_constraint_list hw_constraints_channels4 = { 1142 .count = ARRAY_SIZE(channels4), 1143 .list = channels4, 1144 .mask = 0, 1145 }; 1146 1147 static unsigned int channels6[] = { 1148 2, 4, 6, 1149 }; 1150 1151 static struct snd_pcm_hw_constraint_list hw_constraints_channels6 = { 1152 .count = ARRAY_SIZE(channels6), 1153 .list = channels6, 1154 .mask = 0, 1155 }; 1156 1157 static unsigned int channels8[] = { 1158 2, 4, 6, 8, 1159 }; 1160 1161 static struct snd_pcm_hw_constraint_list hw_constraints_channels8 = { 1162 .count = ARRAY_SIZE(channels8), 1163 .list = channels8, 1164 .mask = 0, 1165 }; 1166 1167 static int snd_intel8x0_pcm_open(struct snd_pcm_substream *substream, struct ichdev *ichdev) 1168 { 1169 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1170 struct snd_pcm_runtime *runtime = substream->runtime; 1171 int err; 1172 1173 ichdev->substream = substream; 1174 runtime->hw = snd_intel8x0_stream; 1175 runtime->hw.rates = ichdev->pcm->rates; 1176 snd_pcm_limit_hw_rates(runtime); 1177 if (chip->device_type == DEVICE_SIS) { 1178 runtime->hw.buffer_bytes_max = 64*1024; 1179 runtime->hw.period_bytes_max = 64*1024; 1180 } 1181 if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0) 1182 return err; 1183 runtime->private_data = ichdev; 1184 return 0; 1185 } 1186 1187 static int snd_intel8x0_playback_open(struct snd_pcm_substream *substream) 1188 { 1189 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1190 struct snd_pcm_runtime *runtime = substream->runtime; 1191 int err; 1192 1193 err = snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMOUT]); 1194 if (err < 0) 1195 return err; 1196 1197 if (chip->multi8) { 1198 runtime->hw.channels_max = 8; 1199 snd_pcm_hw_constraint_list(runtime, 0, 1200 SNDRV_PCM_HW_PARAM_CHANNELS, 1201 &hw_constraints_channels8); 1202 } else if (chip->multi6) { 1203 runtime->hw.channels_max = 6; 1204 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 1205 &hw_constraints_channels6); 1206 } else if (chip->multi4) { 1207 runtime->hw.channels_max = 4; 1208 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 1209 &hw_constraints_channels4); 1210 } 1211 if (chip->dra) { 1212 snd_ac97_pcm_double_rate_rules(runtime); 1213 } 1214 if (chip->smp20bit) { 1215 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE; 1216 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20); 1217 } 1218 return 0; 1219 } 1220 1221 static int snd_intel8x0_playback_close(struct snd_pcm_substream *substream) 1222 { 1223 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1224 1225 chip->ichd[ICHD_PCMOUT].substream = NULL; 1226 return 0; 1227 } 1228 1229 static int snd_intel8x0_capture_open(struct snd_pcm_substream *substream) 1230 { 1231 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1232 1233 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMIN]); 1234 } 1235 1236 static int snd_intel8x0_capture_close(struct snd_pcm_substream *substream) 1237 { 1238 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1239 1240 chip->ichd[ICHD_PCMIN].substream = NULL; 1241 return 0; 1242 } 1243 1244 static int snd_intel8x0_mic_open(struct snd_pcm_substream *substream) 1245 { 1246 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1247 1248 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC]); 1249 } 1250 1251 static int snd_intel8x0_mic_close(struct snd_pcm_substream *substream) 1252 { 1253 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1254 1255 chip->ichd[ICHD_MIC].substream = NULL; 1256 return 0; 1257 } 1258 1259 static int snd_intel8x0_mic2_open(struct snd_pcm_substream *substream) 1260 { 1261 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1262 1263 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC2]); 1264 } 1265 1266 static int snd_intel8x0_mic2_close(struct snd_pcm_substream *substream) 1267 { 1268 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1269 1270 chip->ichd[ICHD_MIC2].substream = NULL; 1271 return 0; 1272 } 1273 1274 static int snd_intel8x0_capture2_open(struct snd_pcm_substream *substream) 1275 { 1276 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1277 1278 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCM2IN]); 1279 } 1280 1281 static int snd_intel8x0_capture2_close(struct snd_pcm_substream *substream) 1282 { 1283 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1284 1285 chip->ichd[ICHD_PCM2IN].substream = NULL; 1286 return 0; 1287 } 1288 1289 static int snd_intel8x0_spdif_open(struct snd_pcm_substream *substream) 1290 { 1291 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1292 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR; 1293 1294 return snd_intel8x0_pcm_open(substream, &chip->ichd[idx]); 1295 } 1296 1297 static int snd_intel8x0_spdif_close(struct snd_pcm_substream *substream) 1298 { 1299 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1300 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR; 1301 1302 chip->ichd[idx].substream = NULL; 1303 return 0; 1304 } 1305 1306 static int snd_intel8x0_ali_ac97spdifout_open(struct snd_pcm_substream *substream) 1307 { 1308 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1309 unsigned int val; 1310 1311 spin_lock_irq(&chip->reg_lock); 1312 val = igetdword(chip, ICHREG(ALI_INTERFACECR)); 1313 val |= ICH_ALI_IF_AC97SP; 1314 iputdword(chip, ICHREG(ALI_INTERFACECR), val); 1315 /* also needs to set ALI_SC_CODEC_SPDF correctly */ 1316 spin_unlock_irq(&chip->reg_lock); 1317 1318 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_AC97SPDIFOUT]); 1319 } 1320 1321 static int snd_intel8x0_ali_ac97spdifout_close(struct snd_pcm_substream *substream) 1322 { 1323 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1324 unsigned int val; 1325 1326 chip->ichd[ALID_AC97SPDIFOUT].substream = NULL; 1327 spin_lock_irq(&chip->reg_lock); 1328 val = igetdword(chip, ICHREG(ALI_INTERFACECR)); 1329 val &= ~ICH_ALI_IF_AC97SP; 1330 iputdword(chip, ICHREG(ALI_INTERFACECR), val); 1331 spin_unlock_irq(&chip->reg_lock); 1332 1333 return 0; 1334 } 1335 1336 #if 0 // NYI 1337 static int snd_intel8x0_ali_spdifin_open(struct snd_pcm_substream *substream) 1338 { 1339 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1340 1341 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFIN]); 1342 } 1343 1344 static int snd_intel8x0_ali_spdifin_close(struct snd_pcm_substream *substream) 1345 { 1346 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1347 1348 chip->ichd[ALID_SPDIFIN].substream = NULL; 1349 return 0; 1350 } 1351 1352 static int snd_intel8x0_ali_spdifout_open(struct snd_pcm_substream *substream) 1353 { 1354 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1355 1356 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFOUT]); 1357 } 1358 1359 static int snd_intel8x0_ali_spdifout_close(struct snd_pcm_substream *substream) 1360 { 1361 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1362 1363 chip->ichd[ALID_SPDIFOUT].substream = NULL; 1364 return 0; 1365 } 1366 #endif 1367 1368 static struct snd_pcm_ops snd_intel8x0_playback_ops = { 1369 .open = snd_intel8x0_playback_open, 1370 .close = snd_intel8x0_playback_close, 1371 .ioctl = snd_pcm_lib_ioctl, 1372 .hw_params = snd_intel8x0_hw_params, 1373 .hw_free = snd_intel8x0_hw_free, 1374 .prepare = snd_intel8x0_pcm_prepare, 1375 .trigger = snd_intel8x0_pcm_trigger, 1376 .pointer = snd_intel8x0_pcm_pointer, 1377 }; 1378 1379 static struct snd_pcm_ops snd_intel8x0_capture_ops = { 1380 .open = snd_intel8x0_capture_open, 1381 .close = snd_intel8x0_capture_close, 1382 .ioctl = snd_pcm_lib_ioctl, 1383 .hw_params = snd_intel8x0_hw_params, 1384 .hw_free = snd_intel8x0_hw_free, 1385 .prepare = snd_intel8x0_pcm_prepare, 1386 .trigger = snd_intel8x0_pcm_trigger, 1387 .pointer = snd_intel8x0_pcm_pointer, 1388 }; 1389 1390 static struct snd_pcm_ops snd_intel8x0_capture_mic_ops = { 1391 .open = snd_intel8x0_mic_open, 1392 .close = snd_intel8x0_mic_close, 1393 .ioctl = snd_pcm_lib_ioctl, 1394 .hw_params = snd_intel8x0_hw_params, 1395 .hw_free = snd_intel8x0_hw_free, 1396 .prepare = snd_intel8x0_pcm_prepare, 1397 .trigger = snd_intel8x0_pcm_trigger, 1398 .pointer = snd_intel8x0_pcm_pointer, 1399 }; 1400 1401 static struct snd_pcm_ops snd_intel8x0_capture_mic2_ops = { 1402 .open = snd_intel8x0_mic2_open, 1403 .close = snd_intel8x0_mic2_close, 1404 .ioctl = snd_pcm_lib_ioctl, 1405 .hw_params = snd_intel8x0_hw_params, 1406 .hw_free = snd_intel8x0_hw_free, 1407 .prepare = snd_intel8x0_pcm_prepare, 1408 .trigger = snd_intel8x0_pcm_trigger, 1409 .pointer = snd_intel8x0_pcm_pointer, 1410 }; 1411 1412 static struct snd_pcm_ops snd_intel8x0_capture2_ops = { 1413 .open = snd_intel8x0_capture2_open, 1414 .close = snd_intel8x0_capture2_close, 1415 .ioctl = snd_pcm_lib_ioctl, 1416 .hw_params = snd_intel8x0_hw_params, 1417 .hw_free = snd_intel8x0_hw_free, 1418 .prepare = snd_intel8x0_pcm_prepare, 1419 .trigger = snd_intel8x0_pcm_trigger, 1420 .pointer = snd_intel8x0_pcm_pointer, 1421 }; 1422 1423 static struct snd_pcm_ops snd_intel8x0_spdif_ops = { 1424 .open = snd_intel8x0_spdif_open, 1425 .close = snd_intel8x0_spdif_close, 1426 .ioctl = snd_pcm_lib_ioctl, 1427 .hw_params = snd_intel8x0_hw_params, 1428 .hw_free = snd_intel8x0_hw_free, 1429 .prepare = snd_intel8x0_pcm_prepare, 1430 .trigger = snd_intel8x0_pcm_trigger, 1431 .pointer = snd_intel8x0_pcm_pointer, 1432 }; 1433 1434 static struct snd_pcm_ops snd_intel8x0_ali_playback_ops = { 1435 .open = snd_intel8x0_playback_open, 1436 .close = snd_intel8x0_playback_close, 1437 .ioctl = snd_pcm_lib_ioctl, 1438 .hw_params = snd_intel8x0_hw_params, 1439 .hw_free = snd_intel8x0_hw_free, 1440 .prepare = snd_intel8x0_pcm_prepare, 1441 .trigger = snd_intel8x0_ali_trigger, 1442 .pointer = snd_intel8x0_pcm_pointer, 1443 }; 1444 1445 static struct snd_pcm_ops snd_intel8x0_ali_capture_ops = { 1446 .open = snd_intel8x0_capture_open, 1447 .close = snd_intel8x0_capture_close, 1448 .ioctl = snd_pcm_lib_ioctl, 1449 .hw_params = snd_intel8x0_hw_params, 1450 .hw_free = snd_intel8x0_hw_free, 1451 .prepare = snd_intel8x0_pcm_prepare, 1452 .trigger = snd_intel8x0_ali_trigger, 1453 .pointer = snd_intel8x0_pcm_pointer, 1454 }; 1455 1456 static struct snd_pcm_ops snd_intel8x0_ali_capture_mic_ops = { 1457 .open = snd_intel8x0_mic_open, 1458 .close = snd_intel8x0_mic_close, 1459 .ioctl = snd_pcm_lib_ioctl, 1460 .hw_params = snd_intel8x0_hw_params, 1461 .hw_free = snd_intel8x0_hw_free, 1462 .prepare = snd_intel8x0_pcm_prepare, 1463 .trigger = snd_intel8x0_ali_trigger, 1464 .pointer = snd_intel8x0_pcm_pointer, 1465 }; 1466 1467 static struct snd_pcm_ops snd_intel8x0_ali_ac97spdifout_ops = { 1468 .open = snd_intel8x0_ali_ac97spdifout_open, 1469 .close = snd_intel8x0_ali_ac97spdifout_close, 1470 .ioctl = snd_pcm_lib_ioctl, 1471 .hw_params = snd_intel8x0_hw_params, 1472 .hw_free = snd_intel8x0_hw_free, 1473 .prepare = snd_intel8x0_pcm_prepare, 1474 .trigger = snd_intel8x0_ali_trigger, 1475 .pointer = snd_intel8x0_pcm_pointer, 1476 }; 1477 1478 #if 0 // NYI 1479 static struct snd_pcm_ops snd_intel8x0_ali_spdifin_ops = { 1480 .open = snd_intel8x0_ali_spdifin_open, 1481 .close = snd_intel8x0_ali_spdifin_close, 1482 .ioctl = snd_pcm_lib_ioctl, 1483 .hw_params = snd_intel8x0_hw_params, 1484 .hw_free = snd_intel8x0_hw_free, 1485 .prepare = snd_intel8x0_pcm_prepare, 1486 .trigger = snd_intel8x0_pcm_trigger, 1487 .pointer = snd_intel8x0_pcm_pointer, 1488 }; 1489 1490 static struct snd_pcm_ops snd_intel8x0_ali_spdifout_ops = { 1491 .open = snd_intel8x0_ali_spdifout_open, 1492 .close = snd_intel8x0_ali_spdifout_close, 1493 .ioctl = snd_pcm_lib_ioctl, 1494 .hw_params = snd_intel8x0_hw_params, 1495 .hw_free = snd_intel8x0_hw_free, 1496 .prepare = snd_intel8x0_pcm_prepare, 1497 .trigger = snd_intel8x0_pcm_trigger, 1498 .pointer = snd_intel8x0_pcm_pointer, 1499 }; 1500 #endif // NYI 1501 1502 struct ich_pcm_table { 1503 char *suffix; 1504 struct snd_pcm_ops *playback_ops; 1505 struct snd_pcm_ops *capture_ops; 1506 size_t prealloc_size; 1507 size_t prealloc_max_size; 1508 int ac97_idx; 1509 }; 1510 1511 static int snd_intel8x0_pcm1(struct intel8x0 *chip, int device, 1512 struct ich_pcm_table *rec) 1513 { 1514 struct snd_pcm *pcm; 1515 int err; 1516 char name[32]; 1517 1518 if (rec->suffix) 1519 sprintf(name, "Intel ICH - %s", rec->suffix); 1520 else 1521 strcpy(name, "Intel ICH"); 1522 err = snd_pcm_new(chip->card, name, device, 1523 rec->playback_ops ? 1 : 0, 1524 rec->capture_ops ? 1 : 0, &pcm); 1525 if (err < 0) 1526 return err; 1527 1528 if (rec->playback_ops) 1529 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops); 1530 if (rec->capture_ops) 1531 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops); 1532 1533 pcm->private_data = chip; 1534 pcm->info_flags = 0; 1535 if (rec->suffix) 1536 sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix); 1537 else 1538 strcpy(pcm->name, chip->card->shortname); 1539 chip->pcm[device] = pcm; 1540 1541 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 1542 snd_dma_pci_data(chip->pci), 1543 rec->prealloc_size, rec->prealloc_max_size); 1544 1545 if (rec->playback_ops && 1546 rec->playback_ops->open == snd_intel8x0_playback_open) { 1547 struct snd_pcm_chmap *chmap; 1548 int chs = 2; 1549 if (chip->multi8) 1550 chs = 8; 1551 else if (chip->multi6) 1552 chs = 6; 1553 else if (chip->multi4) 1554 chs = 4; 1555 err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK, 1556 snd_pcm_alt_chmaps, chs, 0, 1557 &chmap); 1558 if (err < 0) 1559 return err; 1560 chmap->channel_mask = SND_PCM_CHMAP_MASK_2468; 1561 chip->ac97[0]->chmaps[SNDRV_PCM_STREAM_PLAYBACK] = chmap; 1562 } 1563 1564 return 0; 1565 } 1566 1567 static struct ich_pcm_table intel_pcms[] = { 1568 { 1569 .playback_ops = &snd_intel8x0_playback_ops, 1570 .capture_ops = &snd_intel8x0_capture_ops, 1571 .prealloc_size = 64 * 1024, 1572 .prealloc_max_size = 128 * 1024, 1573 }, 1574 { 1575 .suffix = "MIC ADC", 1576 .capture_ops = &snd_intel8x0_capture_mic_ops, 1577 .prealloc_size = 0, 1578 .prealloc_max_size = 128 * 1024, 1579 .ac97_idx = ICHD_MIC, 1580 }, 1581 { 1582 .suffix = "MIC2 ADC", 1583 .capture_ops = &snd_intel8x0_capture_mic2_ops, 1584 .prealloc_size = 0, 1585 .prealloc_max_size = 128 * 1024, 1586 .ac97_idx = ICHD_MIC2, 1587 }, 1588 { 1589 .suffix = "ADC2", 1590 .capture_ops = &snd_intel8x0_capture2_ops, 1591 .prealloc_size = 0, 1592 .prealloc_max_size = 128 * 1024, 1593 .ac97_idx = ICHD_PCM2IN, 1594 }, 1595 { 1596 .suffix = "IEC958", 1597 .playback_ops = &snd_intel8x0_spdif_ops, 1598 .prealloc_size = 64 * 1024, 1599 .prealloc_max_size = 128 * 1024, 1600 .ac97_idx = ICHD_SPBAR, 1601 }, 1602 }; 1603 1604 static struct ich_pcm_table nforce_pcms[] = { 1605 { 1606 .playback_ops = &snd_intel8x0_playback_ops, 1607 .capture_ops = &snd_intel8x0_capture_ops, 1608 .prealloc_size = 64 * 1024, 1609 .prealloc_max_size = 128 * 1024, 1610 }, 1611 { 1612 .suffix = "MIC ADC", 1613 .capture_ops = &snd_intel8x0_capture_mic_ops, 1614 .prealloc_size = 0, 1615 .prealloc_max_size = 128 * 1024, 1616 .ac97_idx = NVD_MIC, 1617 }, 1618 { 1619 .suffix = "IEC958", 1620 .playback_ops = &snd_intel8x0_spdif_ops, 1621 .prealloc_size = 64 * 1024, 1622 .prealloc_max_size = 128 * 1024, 1623 .ac97_idx = NVD_SPBAR, 1624 }, 1625 }; 1626 1627 static struct ich_pcm_table ali_pcms[] = { 1628 { 1629 .playback_ops = &snd_intel8x0_ali_playback_ops, 1630 .capture_ops = &snd_intel8x0_ali_capture_ops, 1631 .prealloc_size = 64 * 1024, 1632 .prealloc_max_size = 128 * 1024, 1633 }, 1634 { 1635 .suffix = "MIC ADC", 1636 .capture_ops = &snd_intel8x0_ali_capture_mic_ops, 1637 .prealloc_size = 0, 1638 .prealloc_max_size = 128 * 1024, 1639 .ac97_idx = ALID_MIC, 1640 }, 1641 { 1642 .suffix = "IEC958", 1643 .playback_ops = &snd_intel8x0_ali_ac97spdifout_ops, 1644 /* .capture_ops = &snd_intel8x0_ali_spdifin_ops, */ 1645 .prealloc_size = 64 * 1024, 1646 .prealloc_max_size = 128 * 1024, 1647 .ac97_idx = ALID_AC97SPDIFOUT, 1648 }, 1649 #if 0 // NYI 1650 { 1651 .suffix = "HW IEC958", 1652 .playback_ops = &snd_intel8x0_ali_spdifout_ops, 1653 .prealloc_size = 64 * 1024, 1654 .prealloc_max_size = 128 * 1024, 1655 }, 1656 #endif 1657 }; 1658 1659 static int snd_intel8x0_pcm(struct intel8x0 *chip) 1660 { 1661 int i, tblsize, device, err; 1662 struct ich_pcm_table *tbl, *rec; 1663 1664 switch (chip->device_type) { 1665 case DEVICE_INTEL_ICH4: 1666 tbl = intel_pcms; 1667 tblsize = ARRAY_SIZE(intel_pcms); 1668 if (spdif_aclink) 1669 tblsize--; 1670 break; 1671 case DEVICE_NFORCE: 1672 tbl = nforce_pcms; 1673 tblsize = ARRAY_SIZE(nforce_pcms); 1674 if (spdif_aclink) 1675 tblsize--; 1676 break; 1677 case DEVICE_ALI: 1678 tbl = ali_pcms; 1679 tblsize = ARRAY_SIZE(ali_pcms); 1680 break; 1681 default: 1682 tbl = intel_pcms; 1683 tblsize = 2; 1684 break; 1685 } 1686 1687 device = 0; 1688 for (i = 0; i < tblsize; i++) { 1689 rec = tbl + i; 1690 if (i > 0 && rec->ac97_idx) { 1691 /* activate PCM only when associated AC'97 codec */ 1692 if (! chip->ichd[rec->ac97_idx].pcm) 1693 continue; 1694 } 1695 err = snd_intel8x0_pcm1(chip, device, rec); 1696 if (err < 0) 1697 return err; 1698 device++; 1699 } 1700 1701 chip->pcm_devs = device; 1702 return 0; 1703 } 1704 1705 1706 /* 1707 * Mixer part 1708 */ 1709 1710 static void snd_intel8x0_mixer_free_ac97_bus(struct snd_ac97_bus *bus) 1711 { 1712 struct intel8x0 *chip = bus->private_data; 1713 chip->ac97_bus = NULL; 1714 } 1715 1716 static void snd_intel8x0_mixer_free_ac97(struct snd_ac97 *ac97) 1717 { 1718 struct intel8x0 *chip = ac97->private_data; 1719 chip->ac97[ac97->num] = NULL; 1720 } 1721 1722 static struct ac97_pcm ac97_pcm_defs[] = { 1723 /* front PCM */ 1724 { 1725 .exclusive = 1, 1726 .r = { { 1727 .slots = (1 << AC97_SLOT_PCM_LEFT) | 1728 (1 << AC97_SLOT_PCM_RIGHT) | 1729 (1 << AC97_SLOT_PCM_CENTER) | 1730 (1 << AC97_SLOT_PCM_SLEFT) | 1731 (1 << AC97_SLOT_PCM_SRIGHT) | 1732 (1 << AC97_SLOT_LFE) 1733 }, 1734 { 1735 .slots = (1 << AC97_SLOT_PCM_LEFT) | 1736 (1 << AC97_SLOT_PCM_RIGHT) | 1737 (1 << AC97_SLOT_PCM_LEFT_0) | 1738 (1 << AC97_SLOT_PCM_RIGHT_0) 1739 } 1740 } 1741 }, 1742 /* PCM IN #1 */ 1743 { 1744 .stream = 1, 1745 .exclusive = 1, 1746 .r = { { 1747 .slots = (1 << AC97_SLOT_PCM_LEFT) | 1748 (1 << AC97_SLOT_PCM_RIGHT) 1749 } 1750 } 1751 }, 1752 /* MIC IN #1 */ 1753 { 1754 .stream = 1, 1755 .exclusive = 1, 1756 .r = { { 1757 .slots = (1 << AC97_SLOT_MIC) 1758 } 1759 } 1760 }, 1761 /* S/PDIF PCM */ 1762 { 1763 .exclusive = 1, 1764 .spdif = 1, 1765 .r = { { 1766 .slots = (1 << AC97_SLOT_SPDIF_LEFT2) | 1767 (1 << AC97_SLOT_SPDIF_RIGHT2) 1768 } 1769 } 1770 }, 1771 /* PCM IN #2 */ 1772 { 1773 .stream = 1, 1774 .exclusive = 1, 1775 .r = { { 1776 .slots = (1 << AC97_SLOT_PCM_LEFT) | 1777 (1 << AC97_SLOT_PCM_RIGHT) 1778 } 1779 } 1780 }, 1781 /* MIC IN #2 */ 1782 { 1783 .stream = 1, 1784 .exclusive = 1, 1785 .r = { { 1786 .slots = (1 << AC97_SLOT_MIC) 1787 } 1788 } 1789 }, 1790 }; 1791 1792 static const struct ac97_quirk ac97_quirks[] = { 1793 { 1794 .subvendor = 0x0e11, 1795 .subdevice = 0x000e, 1796 .name = "Compaq Deskpro EN", /* AD1885 */ 1797 .type = AC97_TUNE_HP_ONLY 1798 }, 1799 { 1800 .subvendor = 0x0e11, 1801 .subdevice = 0x008a, 1802 .name = "Compaq Evo W4000", /* AD1885 */ 1803 .type = AC97_TUNE_HP_ONLY 1804 }, 1805 { 1806 .subvendor = 0x0e11, 1807 .subdevice = 0x00b8, 1808 .name = "Compaq Evo D510C", 1809 .type = AC97_TUNE_HP_ONLY 1810 }, 1811 { 1812 .subvendor = 0x0e11, 1813 .subdevice = 0x0860, 1814 .name = "HP/Compaq nx7010", 1815 .type = AC97_TUNE_MUTE_LED 1816 }, 1817 { 1818 .subvendor = 0x1014, 1819 .subdevice = 0x0534, 1820 .name = "ThinkPad X31", 1821 .type = AC97_TUNE_INV_EAPD 1822 }, 1823 { 1824 .subvendor = 0x1014, 1825 .subdevice = 0x1f00, 1826 .name = "MS-9128", 1827 .type = AC97_TUNE_ALC_JACK 1828 }, 1829 { 1830 .subvendor = 0x1014, 1831 .subdevice = 0x0267, 1832 .name = "IBM NetVista A30p", /* AD1981B */ 1833 .type = AC97_TUNE_HP_ONLY 1834 }, 1835 { 1836 .subvendor = 0x1025, 1837 .subdevice = 0x0082, 1838 .name = "Acer Travelmate 2310", 1839 .type = AC97_TUNE_HP_ONLY 1840 }, 1841 { 1842 .subvendor = 0x1025, 1843 .subdevice = 0x0083, 1844 .name = "Acer Aspire 3003LCi", 1845 .type = AC97_TUNE_HP_ONLY 1846 }, 1847 { 1848 .subvendor = 0x1028, 1849 .subdevice = 0x00d8, 1850 .name = "Dell Precision 530", /* AD1885 */ 1851 .type = AC97_TUNE_HP_ONLY 1852 }, 1853 { 1854 .subvendor = 0x1028, 1855 .subdevice = 0x010d, 1856 .name = "Dell", /* which model? AD1885 */ 1857 .type = AC97_TUNE_HP_ONLY 1858 }, 1859 { 1860 .subvendor = 0x1028, 1861 .subdevice = 0x0126, 1862 .name = "Dell Optiplex GX260", /* AD1981A */ 1863 .type = AC97_TUNE_HP_ONLY 1864 }, 1865 { 1866 .subvendor = 0x1028, 1867 .subdevice = 0x012c, 1868 .name = "Dell Precision 650", /* AD1981A */ 1869 .type = AC97_TUNE_HP_ONLY 1870 }, 1871 { 1872 .subvendor = 0x1028, 1873 .subdevice = 0x012d, 1874 .name = "Dell Precision 450", /* AD1981B*/ 1875 .type = AC97_TUNE_HP_ONLY 1876 }, 1877 { 1878 .subvendor = 0x1028, 1879 .subdevice = 0x0147, 1880 .name = "Dell", /* which model? AD1981B*/ 1881 .type = AC97_TUNE_HP_ONLY 1882 }, 1883 { 1884 .subvendor = 0x1028, 1885 .subdevice = 0x0151, 1886 .name = "Dell Optiplex GX270", /* AD1981B */ 1887 .type = AC97_TUNE_HP_ONLY 1888 }, 1889 { 1890 .subvendor = 0x1028, 1891 .subdevice = 0x014e, 1892 .name = "Dell D800", /* STAC9750/51 */ 1893 .type = AC97_TUNE_HP_ONLY 1894 }, 1895 { 1896 .subvendor = 0x1028, 1897 .subdevice = 0x0163, 1898 .name = "Dell Unknown", /* STAC9750/51 */ 1899 .type = AC97_TUNE_HP_ONLY 1900 }, 1901 { 1902 .subvendor = 0x1028, 1903 .subdevice = 0x016a, 1904 .name = "Dell Inspiron 8600", /* STAC9750/51 */ 1905 .type = AC97_TUNE_HP_ONLY 1906 }, 1907 { 1908 .subvendor = 0x1028, 1909 .subdevice = 0x0182, 1910 .name = "Dell Latitude D610", /* STAC9750/51 */ 1911 .type = AC97_TUNE_HP_ONLY 1912 }, 1913 { 1914 .subvendor = 0x1028, 1915 .subdevice = 0x0186, 1916 .name = "Dell Latitude D810", /* cf. Malone #41015 */ 1917 .type = AC97_TUNE_HP_MUTE_LED 1918 }, 1919 { 1920 .subvendor = 0x1028, 1921 .subdevice = 0x0188, 1922 .name = "Dell Inspiron 6000", 1923 .type = AC97_TUNE_HP_MUTE_LED /* cf. Malone #41015 */ 1924 }, 1925 { 1926 .subvendor = 0x1028, 1927 .subdevice = 0x0189, 1928 .name = "Dell Inspiron 9300", 1929 .type = AC97_TUNE_HP_MUTE_LED 1930 }, 1931 { 1932 .subvendor = 0x1028, 1933 .subdevice = 0x0191, 1934 .name = "Dell Inspiron 8600", 1935 .type = AC97_TUNE_HP_ONLY 1936 }, 1937 { 1938 .subvendor = 0x103c, 1939 .subdevice = 0x006d, 1940 .name = "HP zv5000", 1941 .type = AC97_TUNE_MUTE_LED /*AD1981B*/ 1942 }, 1943 { /* FIXME: which codec? */ 1944 .subvendor = 0x103c, 1945 .subdevice = 0x00c3, 1946 .name = "HP xw6000", 1947 .type = AC97_TUNE_HP_ONLY 1948 }, 1949 { 1950 .subvendor = 0x103c, 1951 .subdevice = 0x088c, 1952 .name = "HP nc8000", 1953 .type = AC97_TUNE_HP_MUTE_LED 1954 }, 1955 { 1956 .subvendor = 0x103c, 1957 .subdevice = 0x0890, 1958 .name = "HP nc6000", 1959 .type = AC97_TUNE_MUTE_LED 1960 }, 1961 { 1962 .subvendor = 0x103c, 1963 .subdevice = 0x129d, 1964 .name = "HP xw8000", 1965 .type = AC97_TUNE_HP_ONLY 1966 }, 1967 { 1968 .subvendor = 0x103c, 1969 .subdevice = 0x0938, 1970 .name = "HP nc4200", 1971 .type = AC97_TUNE_HP_MUTE_LED 1972 }, 1973 { 1974 .subvendor = 0x103c, 1975 .subdevice = 0x099c, 1976 .name = "HP nx6110/nc6120", 1977 .type = AC97_TUNE_HP_MUTE_LED 1978 }, 1979 { 1980 .subvendor = 0x103c, 1981 .subdevice = 0x0944, 1982 .name = "HP nc6220", 1983 .type = AC97_TUNE_HP_MUTE_LED 1984 }, 1985 { 1986 .subvendor = 0x103c, 1987 .subdevice = 0x0934, 1988 .name = "HP nc8220", 1989 .type = AC97_TUNE_HP_MUTE_LED 1990 }, 1991 { 1992 .subvendor = 0x103c, 1993 .subdevice = 0x12f1, 1994 .name = "HP xw8200", /* AD1981B*/ 1995 .type = AC97_TUNE_HP_ONLY 1996 }, 1997 { 1998 .subvendor = 0x103c, 1999 .subdevice = 0x12f2, 2000 .name = "HP xw6200", 2001 .type = AC97_TUNE_HP_ONLY 2002 }, 2003 { 2004 .subvendor = 0x103c, 2005 .subdevice = 0x3008, 2006 .name = "HP xw4200", /* AD1981B*/ 2007 .type = AC97_TUNE_HP_ONLY 2008 }, 2009 { 2010 .subvendor = 0x104d, 2011 .subdevice = 0x8144, 2012 .name = "Sony", 2013 .type = AC97_TUNE_INV_EAPD 2014 }, 2015 { 2016 .subvendor = 0x104d, 2017 .subdevice = 0x8197, 2018 .name = "Sony S1XP", 2019 .type = AC97_TUNE_INV_EAPD 2020 }, 2021 { 2022 .subvendor = 0x104d, 2023 .subdevice = 0x81c0, 2024 .name = "Sony VAIO VGN-T350P", /*AD1981B*/ 2025 .type = AC97_TUNE_INV_EAPD 2026 }, 2027 { 2028 .subvendor = 0x104d, 2029 .subdevice = 0x81c5, 2030 .name = "Sony VAIO VGN-B1VP", /*AD1981B*/ 2031 .type = AC97_TUNE_INV_EAPD 2032 }, 2033 { 2034 .subvendor = 0x1043, 2035 .subdevice = 0x80f3, 2036 .name = "ASUS ICH5/AD1985", 2037 .type = AC97_TUNE_AD_SHARING 2038 }, 2039 { 2040 .subvendor = 0x10cf, 2041 .subdevice = 0x11c3, 2042 .name = "Fujitsu-Siemens E4010", 2043 .type = AC97_TUNE_HP_ONLY 2044 }, 2045 { 2046 .subvendor = 0x10cf, 2047 .subdevice = 0x1225, 2048 .name = "Fujitsu-Siemens T3010", 2049 .type = AC97_TUNE_HP_ONLY 2050 }, 2051 { 2052 .subvendor = 0x10cf, 2053 .subdevice = 0x1253, 2054 .name = "Fujitsu S6210", /* STAC9750/51 */ 2055 .type = AC97_TUNE_HP_ONLY 2056 }, 2057 { 2058 .subvendor = 0x10cf, 2059 .subdevice = 0x127d, 2060 .name = "Fujitsu Lifebook P7010", 2061 .type = AC97_TUNE_HP_ONLY 2062 }, 2063 { 2064 .subvendor = 0x10cf, 2065 .subdevice = 0x127e, 2066 .name = "Fujitsu Lifebook C1211D", 2067 .type = AC97_TUNE_HP_ONLY 2068 }, 2069 { 2070 .subvendor = 0x10cf, 2071 .subdevice = 0x12ec, 2072 .name = "Fujitsu-Siemens 4010", 2073 .type = AC97_TUNE_HP_ONLY 2074 }, 2075 { 2076 .subvendor = 0x10cf, 2077 .subdevice = 0x12f2, 2078 .name = "Fujitsu-Siemens Celsius H320", 2079 .type = AC97_TUNE_SWAP_HP 2080 }, 2081 { 2082 .subvendor = 0x10f1, 2083 .subdevice = 0x2665, 2084 .name = "Fujitsu-Siemens Celsius", /* AD1981? */ 2085 .type = AC97_TUNE_HP_ONLY 2086 }, 2087 { 2088 .subvendor = 0x10f1, 2089 .subdevice = 0x2885, 2090 .name = "AMD64 Mobo", /* ALC650 */ 2091 .type = AC97_TUNE_HP_ONLY 2092 }, 2093 { 2094 .subvendor = 0x10f1, 2095 .subdevice = 0x2895, 2096 .name = "Tyan Thunder K8WE", 2097 .type = AC97_TUNE_HP_ONLY 2098 }, 2099 { 2100 .subvendor = 0x10f7, 2101 .subdevice = 0x834c, 2102 .name = "Panasonic CF-R4", 2103 .type = AC97_TUNE_HP_ONLY, 2104 }, 2105 { 2106 .subvendor = 0x110a, 2107 .subdevice = 0x0056, 2108 .name = "Fujitsu-Siemens Scenic", /* AD1981? */ 2109 .type = AC97_TUNE_HP_ONLY 2110 }, 2111 { 2112 .subvendor = 0x11d4, 2113 .subdevice = 0x5375, 2114 .name = "ADI AD1985 (discrete)", 2115 .type = AC97_TUNE_HP_ONLY 2116 }, 2117 { 2118 .subvendor = 0x1462, 2119 .subdevice = 0x5470, 2120 .name = "MSI P4 ATX 645 Ultra", 2121 .type = AC97_TUNE_HP_ONLY 2122 }, 2123 { 2124 .subvendor = 0x161f, 2125 .subdevice = 0x202f, 2126 .name = "Gateway M520", 2127 .type = AC97_TUNE_INV_EAPD 2128 }, 2129 { 2130 .subvendor = 0x161f, 2131 .subdevice = 0x203a, 2132 .name = "Gateway 4525GZ", /* AD1981B */ 2133 .type = AC97_TUNE_INV_EAPD 2134 }, 2135 { 2136 .subvendor = 0x1734, 2137 .subdevice = 0x0088, 2138 .name = "Fujitsu-Siemens D1522", /* AD1981 */ 2139 .type = AC97_TUNE_HP_ONLY 2140 }, 2141 { 2142 .subvendor = 0x8086, 2143 .subdevice = 0x2000, 2144 .mask = 0xfff0, 2145 .name = "Intel ICH5/AD1985", 2146 .type = AC97_TUNE_AD_SHARING 2147 }, 2148 { 2149 .subvendor = 0x8086, 2150 .subdevice = 0x4000, 2151 .mask = 0xfff0, 2152 .name = "Intel ICH5/AD1985", 2153 .type = AC97_TUNE_AD_SHARING 2154 }, 2155 { 2156 .subvendor = 0x8086, 2157 .subdevice = 0x4856, 2158 .name = "Intel D845WN (82801BA)", 2159 .type = AC97_TUNE_SWAP_HP 2160 }, 2161 { 2162 .subvendor = 0x8086, 2163 .subdevice = 0x4d44, 2164 .name = "Intel D850EMV2", /* AD1885 */ 2165 .type = AC97_TUNE_HP_ONLY 2166 }, 2167 { 2168 .subvendor = 0x8086, 2169 .subdevice = 0x4d56, 2170 .name = "Intel ICH/AD1885", 2171 .type = AC97_TUNE_HP_ONLY 2172 }, 2173 { 2174 .subvendor = 0x8086, 2175 .subdevice = 0x6000, 2176 .mask = 0xfff0, 2177 .name = "Intel ICH5/AD1985", 2178 .type = AC97_TUNE_AD_SHARING 2179 }, 2180 { 2181 .subvendor = 0x8086, 2182 .subdevice = 0xe000, 2183 .mask = 0xfff0, 2184 .name = "Intel ICH5/AD1985", 2185 .type = AC97_TUNE_AD_SHARING 2186 }, 2187 #if 0 /* FIXME: this seems wrong on most boards */ 2188 { 2189 .subvendor = 0x8086, 2190 .subdevice = 0xa000, 2191 .mask = 0xfff0, 2192 .name = "Intel ICH5/AD1985", 2193 .type = AC97_TUNE_HP_ONLY 2194 }, 2195 #endif 2196 { } /* terminator */ 2197 }; 2198 2199 static int snd_intel8x0_mixer(struct intel8x0 *chip, int ac97_clock, 2200 const char *quirk_override) 2201 { 2202 struct snd_ac97_bus *pbus; 2203 struct snd_ac97_template ac97; 2204 int err; 2205 unsigned int i, codecs; 2206 unsigned int glob_sta = 0; 2207 struct snd_ac97_bus_ops *ops; 2208 static struct snd_ac97_bus_ops standard_bus_ops = { 2209 .write = snd_intel8x0_codec_write, 2210 .read = snd_intel8x0_codec_read, 2211 }; 2212 static struct snd_ac97_bus_ops ali_bus_ops = { 2213 .write = snd_intel8x0_ali_codec_write, 2214 .read = snd_intel8x0_ali_codec_read, 2215 }; 2216 2217 chip->spdif_idx = -1; /* use PCMOUT (or disabled) */ 2218 if (!spdif_aclink) { 2219 switch (chip->device_type) { 2220 case DEVICE_NFORCE: 2221 chip->spdif_idx = NVD_SPBAR; 2222 break; 2223 case DEVICE_ALI: 2224 chip->spdif_idx = ALID_AC97SPDIFOUT; 2225 break; 2226 case DEVICE_INTEL_ICH4: 2227 chip->spdif_idx = ICHD_SPBAR; 2228 break; 2229 } 2230 } 2231 2232 chip->in_ac97_init = 1; 2233 2234 memset(&ac97, 0, sizeof(ac97)); 2235 ac97.private_data = chip; 2236 ac97.private_free = snd_intel8x0_mixer_free_ac97; 2237 ac97.scaps = AC97_SCAP_SKIP_MODEM | AC97_SCAP_POWER_SAVE; 2238 if (chip->xbox) 2239 ac97.scaps |= AC97_SCAP_DETECT_BY_VENDOR; 2240 if (chip->device_type != DEVICE_ALI) { 2241 glob_sta = igetdword(chip, ICHREG(GLOB_STA)); 2242 ops = &standard_bus_ops; 2243 chip->in_sdin_init = 1; 2244 codecs = 0; 2245 for (i = 0; i < chip->max_codecs; i++) { 2246 if (! (glob_sta & chip->codec_bit[i])) 2247 continue; 2248 if (chip->device_type == DEVICE_INTEL_ICH4) { 2249 snd_intel8x0_codec_read_test(chip, codecs); 2250 chip->ac97_sdin[codecs] = 2251 igetbyte(chip, ICHREG(SDM)) & ICH_LDI_MASK; 2252 if (snd_BUG_ON(chip->ac97_sdin[codecs] >= 3)) 2253 chip->ac97_sdin[codecs] = 0; 2254 } else 2255 chip->ac97_sdin[codecs] = i; 2256 codecs++; 2257 } 2258 chip->in_sdin_init = 0; 2259 if (! codecs) 2260 codecs = 1; 2261 } else { 2262 ops = &ali_bus_ops; 2263 codecs = 1; 2264 /* detect the secondary codec */ 2265 for (i = 0; i < 100; i++) { 2266 unsigned int reg = igetdword(chip, ICHREG(ALI_RTSR)); 2267 if (reg & 0x40) { 2268 codecs = 2; 2269 break; 2270 } 2271 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x40); 2272 udelay(1); 2273 } 2274 } 2275 if ((err = snd_ac97_bus(chip->card, 0, ops, chip, &pbus)) < 0) 2276 goto __err; 2277 pbus->private_free = snd_intel8x0_mixer_free_ac97_bus; 2278 if (ac97_clock >= 8000 && ac97_clock <= 48000) 2279 pbus->clock = ac97_clock; 2280 /* FIXME: my test board doesn't work well with VRA... */ 2281 if (chip->device_type == DEVICE_ALI) 2282 pbus->no_vra = 1; 2283 else 2284 pbus->dra = 1; 2285 chip->ac97_bus = pbus; 2286 chip->ncodecs = codecs; 2287 2288 ac97.pci = chip->pci; 2289 for (i = 0; i < codecs; i++) { 2290 ac97.num = i; 2291 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i])) < 0) { 2292 if (err != -EACCES) 2293 dev_err(chip->card->dev, 2294 "Unable to initialize codec #%d\n", i); 2295 if (i == 0) 2296 goto __err; 2297 } 2298 } 2299 /* tune up the primary codec */ 2300 snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override); 2301 /* enable separate SDINs for ICH4 */ 2302 if (chip->device_type == DEVICE_INTEL_ICH4) 2303 pbus->isdin = 1; 2304 /* find the available PCM streams */ 2305 i = ARRAY_SIZE(ac97_pcm_defs); 2306 if (chip->device_type != DEVICE_INTEL_ICH4) 2307 i -= 2; /* do not allocate PCM2IN and MIC2 */ 2308 if (chip->spdif_idx < 0) 2309 i--; /* do not allocate S/PDIF */ 2310 err = snd_ac97_pcm_assign(pbus, i, ac97_pcm_defs); 2311 if (err < 0) 2312 goto __err; 2313 chip->ichd[ICHD_PCMOUT].pcm = &pbus->pcms[0]; 2314 chip->ichd[ICHD_PCMIN].pcm = &pbus->pcms[1]; 2315 chip->ichd[ICHD_MIC].pcm = &pbus->pcms[2]; 2316 if (chip->spdif_idx >= 0) 2317 chip->ichd[chip->spdif_idx].pcm = &pbus->pcms[3]; 2318 if (chip->device_type == DEVICE_INTEL_ICH4) { 2319 chip->ichd[ICHD_PCM2IN].pcm = &pbus->pcms[4]; 2320 chip->ichd[ICHD_MIC2].pcm = &pbus->pcms[5]; 2321 } 2322 /* enable separate SDINs for ICH4 */ 2323 if (chip->device_type == DEVICE_INTEL_ICH4) { 2324 struct ac97_pcm *pcm = chip->ichd[ICHD_PCM2IN].pcm; 2325 u8 tmp = igetbyte(chip, ICHREG(SDM)); 2326 tmp &= ~(ICH_DI2L_MASK|ICH_DI1L_MASK); 2327 if (pcm) { 2328 tmp |= ICH_SE; /* steer enable for multiple SDINs */ 2329 tmp |= chip->ac97_sdin[0] << ICH_DI1L_SHIFT; 2330 for (i = 1; i < 4; i++) { 2331 if (pcm->r[0].codec[i]) { 2332 tmp |= chip->ac97_sdin[pcm->r[0].codec[1]->num] << ICH_DI2L_SHIFT; 2333 break; 2334 } 2335 } 2336 } else { 2337 tmp &= ~ICH_SE; /* steer disable */ 2338 } 2339 iputbyte(chip, ICHREG(SDM), tmp); 2340 } 2341 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) { 2342 chip->multi4 = 1; 2343 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_LFE)) { 2344 chip->multi6 = 1; 2345 if (chip->ac97[0]->flags & AC97_HAS_8CH) 2346 chip->multi8 = 1; 2347 } 2348 } 2349 if (pbus->pcms[0].r[1].rslots[0]) { 2350 chip->dra = 1; 2351 } 2352 if (chip->device_type == DEVICE_INTEL_ICH4) { 2353 if ((igetdword(chip, ICHREG(GLOB_STA)) & ICH_SAMPLE_CAP) == ICH_SAMPLE_16_20) 2354 chip->smp20bit = 1; 2355 } 2356 if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) { 2357 /* 48kHz only */ 2358 chip->ichd[chip->spdif_idx].pcm->rates = SNDRV_PCM_RATE_48000; 2359 } 2360 if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) { 2361 /* use slot 10/11 for SPDIF */ 2362 u32 val; 2363 val = igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK; 2364 val |= ICH_PCM_SPDIF_1011; 2365 iputdword(chip, ICHREG(GLOB_CNT), val); 2366 snd_ac97_update_bits(chip->ac97[0], AC97_EXTENDED_STATUS, 0x03 << 4, 0x03 << 4); 2367 } 2368 chip->in_ac97_init = 0; 2369 return 0; 2370 2371 __err: 2372 /* clear the cold-reset bit for the next chance */ 2373 if (chip->device_type != DEVICE_ALI) 2374 iputdword(chip, ICHREG(GLOB_CNT), 2375 igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD); 2376 return err; 2377 } 2378 2379 2380 /* 2381 * 2382 */ 2383 2384 static void do_ali_reset(struct intel8x0 *chip) 2385 { 2386 iputdword(chip, ICHREG(ALI_SCR), ICH_ALI_SC_RESET); 2387 iputdword(chip, ICHREG(ALI_FIFOCR1), 0x83838383); 2388 iputdword(chip, ICHREG(ALI_FIFOCR2), 0x83838383); 2389 iputdword(chip, ICHREG(ALI_FIFOCR3), 0x83838383); 2390 iputdword(chip, ICHREG(ALI_INTERFACECR), 2391 ICH_ALI_IF_PI|ICH_ALI_IF_PO); 2392 iputdword(chip, ICHREG(ALI_INTERRUPTCR), 0x00000000); 2393 iputdword(chip, ICHREG(ALI_INTERRUPTSR), 0x00000000); 2394 } 2395 2396 #ifdef CONFIG_SND_AC97_POWER_SAVE 2397 static struct snd_pci_quirk ich_chip_reset_mode[] = { 2398 SND_PCI_QUIRK(0x1014, 0x051f, "Thinkpad R32", 1), 2399 { } /* end */ 2400 }; 2401 2402 static int snd_intel8x0_ich_chip_cold_reset(struct intel8x0 *chip) 2403 { 2404 unsigned int cnt; 2405 /* ACLink on, 2 channels */ 2406 2407 if (snd_pci_quirk_lookup(chip->pci, ich_chip_reset_mode)) 2408 return -EIO; 2409 2410 cnt = igetdword(chip, ICHREG(GLOB_CNT)); 2411 cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK); 2412 2413 /* do cold reset - the full ac97 powerdown may leave the controller 2414 * in a warm state but actually it cannot communicate with the codec. 2415 */ 2416 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_AC97COLD); 2417 cnt = igetdword(chip, ICHREG(GLOB_CNT)); 2418 udelay(10); 2419 iputdword(chip, ICHREG(GLOB_CNT), cnt | ICH_AC97COLD); 2420 msleep(1); 2421 return 0; 2422 } 2423 #define snd_intel8x0_ich_chip_can_cold_reset(chip) \ 2424 (!snd_pci_quirk_lookup(chip->pci, ich_chip_reset_mode)) 2425 #else 2426 #define snd_intel8x0_ich_chip_cold_reset(chip) 0 2427 #define snd_intel8x0_ich_chip_can_cold_reset(chip) (0) 2428 #endif 2429 2430 static int snd_intel8x0_ich_chip_reset(struct intel8x0 *chip) 2431 { 2432 unsigned long end_time; 2433 unsigned int cnt; 2434 /* ACLink on, 2 channels */ 2435 cnt = igetdword(chip, ICHREG(GLOB_CNT)); 2436 cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK); 2437 /* finish cold or do warm reset */ 2438 cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM; 2439 iputdword(chip, ICHREG(GLOB_CNT), cnt); 2440 end_time = (jiffies + (HZ / 4)) + 1; 2441 do { 2442 if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0) 2443 return 0; 2444 schedule_timeout_uninterruptible(1); 2445 } while (time_after_eq(end_time, jiffies)); 2446 dev_err(chip->card->dev, "AC'97 warm reset still in progress? [0x%x]\n", 2447 igetdword(chip, ICHREG(GLOB_CNT))); 2448 return -EIO; 2449 } 2450 2451 static int snd_intel8x0_ich_chip_init(struct intel8x0 *chip, int probing) 2452 { 2453 unsigned long end_time; 2454 unsigned int status, nstatus; 2455 unsigned int cnt; 2456 int err; 2457 2458 /* put logic to right state */ 2459 /* first clear status bits */ 2460 status = ICH_RCS | ICH_MCINT | ICH_POINT | ICH_PIINT; 2461 if (chip->device_type == DEVICE_NFORCE) 2462 status |= ICH_NVSPINT; 2463 cnt = igetdword(chip, ICHREG(GLOB_STA)); 2464 iputdword(chip, ICHREG(GLOB_STA), cnt & status); 2465 2466 if (snd_intel8x0_ich_chip_can_cold_reset(chip)) 2467 err = snd_intel8x0_ich_chip_cold_reset(chip); 2468 else 2469 err = snd_intel8x0_ich_chip_reset(chip); 2470 if (err < 0) 2471 return err; 2472 2473 if (probing) { 2474 /* wait for any codec ready status. 2475 * Once it becomes ready it should remain ready 2476 * as long as we do not disable the ac97 link. 2477 */ 2478 end_time = jiffies + HZ; 2479 do { 2480 status = igetdword(chip, ICHREG(GLOB_STA)) & 2481 chip->codec_isr_bits; 2482 if (status) 2483 break; 2484 schedule_timeout_uninterruptible(1); 2485 } while (time_after_eq(end_time, jiffies)); 2486 if (! status) { 2487 /* no codec is found */ 2488 dev_err(chip->card->dev, 2489 "codec_ready: codec is not ready [0x%x]\n", 2490 igetdword(chip, ICHREG(GLOB_STA))); 2491 return -EIO; 2492 } 2493 2494 /* wait for other codecs ready status. */ 2495 end_time = jiffies + HZ / 4; 2496 while (status != chip->codec_isr_bits && 2497 time_after_eq(end_time, jiffies)) { 2498 schedule_timeout_uninterruptible(1); 2499 status |= igetdword(chip, ICHREG(GLOB_STA)) & 2500 chip->codec_isr_bits; 2501 } 2502 2503 } else { 2504 /* resume phase */ 2505 int i; 2506 status = 0; 2507 for (i = 0; i < chip->ncodecs; i++) 2508 if (chip->ac97[i]) 2509 status |= chip->codec_bit[chip->ac97_sdin[i]]; 2510 /* wait until all the probed codecs are ready */ 2511 end_time = jiffies + HZ; 2512 do { 2513 nstatus = igetdword(chip, ICHREG(GLOB_STA)) & 2514 chip->codec_isr_bits; 2515 if (status == nstatus) 2516 break; 2517 schedule_timeout_uninterruptible(1); 2518 } while (time_after_eq(end_time, jiffies)); 2519 } 2520 2521 if (chip->device_type == DEVICE_SIS) { 2522 /* unmute the output on SIS7012 */ 2523 iputword(chip, 0x4c, igetword(chip, 0x4c) | 1); 2524 } 2525 if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) { 2526 /* enable SPDIF interrupt */ 2527 unsigned int val; 2528 pci_read_config_dword(chip->pci, 0x4c, &val); 2529 val |= 0x1000000; 2530 pci_write_config_dword(chip->pci, 0x4c, val); 2531 } 2532 return 0; 2533 } 2534 2535 static int snd_intel8x0_ali_chip_init(struct intel8x0 *chip, int probing) 2536 { 2537 u32 reg; 2538 int i = 0; 2539 2540 reg = igetdword(chip, ICHREG(ALI_SCR)); 2541 if ((reg & 2) == 0) /* Cold required */ 2542 reg |= 2; 2543 else 2544 reg |= 1; /* Warm */ 2545 reg &= ~0x80000000; /* ACLink on */ 2546 iputdword(chip, ICHREG(ALI_SCR), reg); 2547 2548 for (i = 0; i < HZ / 2; i++) { 2549 if (! (igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ALI_INT_GPIO)) 2550 goto __ok; 2551 schedule_timeout_uninterruptible(1); 2552 } 2553 dev_err(chip->card->dev, "AC'97 reset failed.\n"); 2554 if (probing) 2555 return -EIO; 2556 2557 __ok: 2558 for (i = 0; i < HZ / 2; i++) { 2559 reg = igetdword(chip, ICHREG(ALI_RTSR)); 2560 if (reg & 0x80) /* primary codec */ 2561 break; 2562 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x80); 2563 schedule_timeout_uninterruptible(1); 2564 } 2565 2566 do_ali_reset(chip); 2567 return 0; 2568 } 2569 2570 static int snd_intel8x0_chip_init(struct intel8x0 *chip, int probing) 2571 { 2572 unsigned int i, timeout; 2573 int err; 2574 2575 if (chip->device_type != DEVICE_ALI) { 2576 if ((err = snd_intel8x0_ich_chip_init(chip, probing)) < 0) 2577 return err; 2578 iagetword(chip, 0); /* clear semaphore flag */ 2579 } else { 2580 if ((err = snd_intel8x0_ali_chip_init(chip, probing)) < 0) 2581 return err; 2582 } 2583 2584 /* disable interrupts */ 2585 for (i = 0; i < chip->bdbars_count; i++) 2586 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00); 2587 /* reset channels */ 2588 for (i = 0; i < chip->bdbars_count; i++) 2589 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS); 2590 for (i = 0; i < chip->bdbars_count; i++) { 2591 timeout = 100000; 2592 while (--timeout != 0) { 2593 if ((igetbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset) & ICH_RESETREGS) == 0) 2594 break; 2595 } 2596 if (timeout == 0) 2597 dev_err(chip->card->dev, "reset of registers failed?\n"); 2598 } 2599 /* initialize Buffer Descriptor Lists */ 2600 for (i = 0; i < chip->bdbars_count; i++) 2601 iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset, 2602 chip->ichd[i].bdbar_addr); 2603 return 0; 2604 } 2605 2606 static int snd_intel8x0_free(struct intel8x0 *chip) 2607 { 2608 unsigned int i; 2609 2610 if (chip->irq < 0) 2611 goto __hw_end; 2612 /* disable interrupts */ 2613 for (i = 0; i < chip->bdbars_count; i++) 2614 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00); 2615 /* reset channels */ 2616 for (i = 0; i < chip->bdbars_count; i++) 2617 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS); 2618 if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) { 2619 /* stop the spdif interrupt */ 2620 unsigned int val; 2621 pci_read_config_dword(chip->pci, 0x4c, &val); 2622 val &= ~0x1000000; 2623 pci_write_config_dword(chip->pci, 0x4c, val); 2624 } 2625 /* --- */ 2626 2627 __hw_end: 2628 if (chip->irq >= 0) 2629 free_irq(chip->irq, chip); 2630 if (chip->bdbars.area) { 2631 if (chip->fix_nocache) 2632 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 0); 2633 snd_dma_free_pages(&chip->bdbars); 2634 } 2635 if (chip->addr) 2636 pci_iounmap(chip->pci, chip->addr); 2637 if (chip->bmaddr) 2638 pci_iounmap(chip->pci, chip->bmaddr); 2639 pci_release_regions(chip->pci); 2640 pci_disable_device(chip->pci); 2641 kfree(chip); 2642 return 0; 2643 } 2644 2645 #ifdef CONFIG_PM_SLEEP 2646 /* 2647 * power management 2648 */ 2649 static int intel8x0_suspend(struct device *dev) 2650 { 2651 struct snd_card *card = dev_get_drvdata(dev); 2652 struct intel8x0 *chip = card->private_data; 2653 int i; 2654 2655 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 2656 for (i = 0; i < chip->pcm_devs; i++) 2657 snd_pcm_suspend_all(chip->pcm[i]); 2658 /* clear nocache */ 2659 if (chip->fix_nocache) { 2660 for (i = 0; i < chip->bdbars_count; i++) { 2661 struct ichdev *ichdev = &chip->ichd[i]; 2662 if (ichdev->substream && ichdev->page_attr_changed) { 2663 struct snd_pcm_runtime *runtime = ichdev->substream->runtime; 2664 if (runtime->dma_area) 2665 fill_nocache(runtime->dma_area, runtime->dma_bytes, 0); 2666 } 2667 } 2668 } 2669 for (i = 0; i < chip->ncodecs; i++) 2670 snd_ac97_suspend(chip->ac97[i]); 2671 if (chip->device_type == DEVICE_INTEL_ICH4) 2672 chip->sdm_saved = igetbyte(chip, ICHREG(SDM)); 2673 2674 if (chip->irq >= 0) { 2675 free_irq(chip->irq, chip); 2676 chip->irq = -1; 2677 } 2678 return 0; 2679 } 2680 2681 static int intel8x0_resume(struct device *dev) 2682 { 2683 struct pci_dev *pci = to_pci_dev(dev); 2684 struct snd_card *card = dev_get_drvdata(dev); 2685 struct intel8x0 *chip = card->private_data; 2686 int i; 2687 2688 snd_intel8x0_chip_init(chip, 0); 2689 if (request_irq(pci->irq, snd_intel8x0_interrupt, 2690 IRQF_SHARED, KBUILD_MODNAME, chip)) { 2691 dev_err(dev, "unable to grab IRQ %d, disabling device\n", 2692 pci->irq); 2693 snd_card_disconnect(card); 2694 return -EIO; 2695 } 2696 chip->irq = pci->irq; 2697 synchronize_irq(chip->irq); 2698 2699 /* re-initialize mixer stuff */ 2700 if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) { 2701 /* enable separate SDINs for ICH4 */ 2702 iputbyte(chip, ICHREG(SDM), chip->sdm_saved); 2703 /* use slot 10/11 for SPDIF */ 2704 iputdword(chip, ICHREG(GLOB_CNT), 2705 (igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK) | 2706 ICH_PCM_SPDIF_1011); 2707 } 2708 2709 /* refill nocache */ 2710 if (chip->fix_nocache) 2711 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1); 2712 2713 for (i = 0; i < chip->ncodecs; i++) 2714 snd_ac97_resume(chip->ac97[i]); 2715 2716 /* refill nocache */ 2717 if (chip->fix_nocache) { 2718 for (i = 0; i < chip->bdbars_count; i++) { 2719 struct ichdev *ichdev = &chip->ichd[i]; 2720 if (ichdev->substream && ichdev->page_attr_changed) { 2721 struct snd_pcm_runtime *runtime = ichdev->substream->runtime; 2722 if (runtime->dma_area) 2723 fill_nocache(runtime->dma_area, runtime->dma_bytes, 1); 2724 } 2725 } 2726 } 2727 2728 /* resume status */ 2729 for (i = 0; i < chip->bdbars_count; i++) { 2730 struct ichdev *ichdev = &chip->ichd[i]; 2731 unsigned long port = ichdev->reg_offset; 2732 if (! ichdev->substream || ! ichdev->suspended) 2733 continue; 2734 if (ichdev->ichd == ICHD_PCMOUT) 2735 snd_intel8x0_setup_pcm_out(chip, ichdev->substream->runtime); 2736 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr); 2737 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi); 2738 iputbyte(chip, port + ICH_REG_OFF_CIV, ichdev->civ); 2739 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI); 2740 } 2741 2742 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 2743 return 0; 2744 } 2745 2746 static SIMPLE_DEV_PM_OPS(intel8x0_pm, intel8x0_suspend, intel8x0_resume); 2747 #define INTEL8X0_PM_OPS &intel8x0_pm 2748 #else 2749 #define INTEL8X0_PM_OPS NULL 2750 #endif /* CONFIG_PM_SLEEP */ 2751 2752 #define INTEL8X0_TESTBUF_SIZE 32768 /* enough large for one shot */ 2753 2754 static void intel8x0_measure_ac97_clock(struct intel8x0 *chip) 2755 { 2756 struct snd_pcm_substream *subs; 2757 struct ichdev *ichdev; 2758 unsigned long port; 2759 unsigned long pos, pos1, t; 2760 int civ, timeout = 1000, attempt = 1; 2761 ktime_t start_time, stop_time; 2762 2763 if (chip->ac97_bus->clock != 48000) 2764 return; /* specified in module option */ 2765 2766 __again: 2767 subs = chip->pcm[0]->streams[0].substream; 2768 if (! subs || subs->dma_buffer.bytes < INTEL8X0_TESTBUF_SIZE) { 2769 dev_warn(chip->card->dev, 2770 "no playback buffer allocated - aborting measure ac97 clock\n"); 2771 return; 2772 } 2773 ichdev = &chip->ichd[ICHD_PCMOUT]; 2774 ichdev->physbuf = subs->dma_buffer.addr; 2775 ichdev->size = ichdev->fragsize = INTEL8X0_TESTBUF_SIZE; 2776 ichdev->substream = NULL; /* don't process interrupts */ 2777 2778 /* set rate */ 2779 if (snd_ac97_set_rate(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 48000) < 0) { 2780 dev_err(chip->card->dev, "cannot set ac97 rate: clock = %d\n", 2781 chip->ac97_bus->clock); 2782 return; 2783 } 2784 snd_intel8x0_setup_periods(chip, ichdev); 2785 port = ichdev->reg_offset; 2786 spin_lock_irq(&chip->reg_lock); 2787 chip->in_measurement = 1; 2788 /* trigger */ 2789 if (chip->device_type != DEVICE_ALI) 2790 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE | ICH_STARTBM); 2791 else { 2792 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE); 2793 iputdword(chip, ICHREG(ALI_DMACR), 1 << ichdev->ali_slot); 2794 } 2795 start_time = ktime_get(); 2796 spin_unlock_irq(&chip->reg_lock); 2797 msleep(50); 2798 spin_lock_irq(&chip->reg_lock); 2799 /* check the position */ 2800 do { 2801 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV); 2802 pos1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb); 2803 if (pos1 == 0) { 2804 udelay(10); 2805 continue; 2806 } 2807 if (civ == igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV) && 2808 pos1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb)) 2809 break; 2810 } while (timeout--); 2811 if (pos1 == 0) { /* oops, this value is not reliable */ 2812 pos = 0; 2813 } else { 2814 pos = ichdev->fragsize1; 2815 pos -= pos1 << ichdev->pos_shift; 2816 pos += ichdev->position; 2817 } 2818 chip->in_measurement = 0; 2819 stop_time = ktime_get(); 2820 /* stop */ 2821 if (chip->device_type == DEVICE_ALI) { 2822 iputdword(chip, ICHREG(ALI_DMACR), 1 << (ichdev->ali_slot + 16)); 2823 iputbyte(chip, port + ICH_REG_OFF_CR, 0); 2824 while (igetbyte(chip, port + ICH_REG_OFF_CR)) 2825 ; 2826 } else { 2827 iputbyte(chip, port + ICH_REG_OFF_CR, 0); 2828 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) 2829 ; 2830 } 2831 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS); 2832 spin_unlock_irq(&chip->reg_lock); 2833 2834 if (pos == 0) { 2835 dev_err(chip->card->dev, 2836 "measure - unreliable DMA position..\n"); 2837 __retry: 2838 if (attempt < 3) { 2839 msleep(300); 2840 attempt++; 2841 goto __again; 2842 } 2843 goto __end; 2844 } 2845 2846 pos /= 4; 2847 t = ktime_us_delta(stop_time, start_time); 2848 dev_info(chip->card->dev, 2849 "%s: measured %lu usecs (%lu samples)\n", __func__, t, pos); 2850 if (t == 0) { 2851 dev_err(chip->card->dev, "?? calculation error..\n"); 2852 goto __retry; 2853 } 2854 pos *= 1000; 2855 pos = (pos / t) * 1000 + ((pos % t) * 1000) / t; 2856 if (pos < 40000 || pos >= 60000) { 2857 /* abnormal value. hw problem? */ 2858 dev_info(chip->card->dev, "measured clock %ld rejected\n", pos); 2859 goto __retry; 2860 } else if (pos > 40500 && pos < 41500) 2861 /* first exception - 41000Hz reference clock */ 2862 chip->ac97_bus->clock = 41000; 2863 else if (pos > 43600 && pos < 44600) 2864 /* second exception - 44100HZ reference clock */ 2865 chip->ac97_bus->clock = 44100; 2866 else if (pos < 47500 || pos > 48500) 2867 /* not 48000Hz, tuning the clock.. */ 2868 chip->ac97_bus->clock = (chip->ac97_bus->clock * 48000) / pos; 2869 __end: 2870 dev_info(chip->card->dev, "clocking to %d\n", chip->ac97_bus->clock); 2871 snd_ac97_update_power(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 0); 2872 } 2873 2874 static struct snd_pci_quirk intel8x0_clock_list[] = { 2875 SND_PCI_QUIRK(0x0e11, 0x008a, "AD1885", 41000), 2876 SND_PCI_QUIRK(0x1014, 0x0581, "AD1981B", 48000), 2877 SND_PCI_QUIRK(0x1028, 0x00be, "AD1885", 44100), 2878 SND_PCI_QUIRK(0x1028, 0x0177, "AD1980", 48000), 2879 SND_PCI_QUIRK(0x1028, 0x01ad, "AD1981B", 48000), 2880 SND_PCI_QUIRK(0x1043, 0x80f3, "AD1985", 48000), 2881 { } /* terminator */ 2882 }; 2883 2884 static int intel8x0_in_clock_list(struct intel8x0 *chip) 2885 { 2886 struct pci_dev *pci = chip->pci; 2887 const struct snd_pci_quirk *wl; 2888 2889 wl = snd_pci_quirk_lookup(pci, intel8x0_clock_list); 2890 if (!wl) 2891 return 0; 2892 dev_info(chip->card->dev, "white list rate for %04x:%04x is %i\n", 2893 pci->subsystem_vendor, pci->subsystem_device, wl->value); 2894 chip->ac97_bus->clock = wl->value; 2895 return 1; 2896 } 2897 2898 static void snd_intel8x0_proc_read(struct snd_info_entry * entry, 2899 struct snd_info_buffer *buffer) 2900 { 2901 struct intel8x0 *chip = entry->private_data; 2902 unsigned int tmp; 2903 2904 snd_iprintf(buffer, "Intel8x0\n\n"); 2905 if (chip->device_type == DEVICE_ALI) 2906 return; 2907 tmp = igetdword(chip, ICHREG(GLOB_STA)); 2908 snd_iprintf(buffer, "Global control : 0x%08x\n", igetdword(chip, ICHREG(GLOB_CNT))); 2909 snd_iprintf(buffer, "Global status : 0x%08x\n", tmp); 2910 if (chip->device_type == DEVICE_INTEL_ICH4) 2911 snd_iprintf(buffer, "SDM : 0x%08x\n", igetdword(chip, ICHREG(SDM))); 2912 snd_iprintf(buffer, "AC'97 codecs ready :"); 2913 if (tmp & chip->codec_isr_bits) { 2914 int i; 2915 static const char *codecs[3] = { 2916 "primary", "secondary", "tertiary" 2917 }; 2918 for (i = 0; i < chip->max_codecs; i++) 2919 if (tmp & chip->codec_bit[i]) 2920 snd_iprintf(buffer, " %s", codecs[i]); 2921 } else 2922 snd_iprintf(buffer, " none"); 2923 snd_iprintf(buffer, "\n"); 2924 if (chip->device_type == DEVICE_INTEL_ICH4 || 2925 chip->device_type == DEVICE_SIS) 2926 snd_iprintf(buffer, "AC'97 codecs SDIN : %i %i %i\n", 2927 chip->ac97_sdin[0], 2928 chip->ac97_sdin[1], 2929 chip->ac97_sdin[2]); 2930 } 2931 2932 static void snd_intel8x0_proc_init(struct intel8x0 *chip) 2933 { 2934 struct snd_info_entry *entry; 2935 2936 if (! snd_card_proc_new(chip->card, "intel8x0", &entry)) 2937 snd_info_set_text_ops(entry, chip, snd_intel8x0_proc_read); 2938 } 2939 2940 static int snd_intel8x0_dev_free(struct snd_device *device) 2941 { 2942 struct intel8x0 *chip = device->device_data; 2943 return snd_intel8x0_free(chip); 2944 } 2945 2946 struct ich_reg_info { 2947 unsigned int int_sta_mask; 2948 unsigned int offset; 2949 }; 2950 2951 static unsigned int ich_codec_bits[3] = { 2952 ICH_PCR, ICH_SCR, ICH_TCR 2953 }; 2954 static unsigned int sis_codec_bits[3] = { 2955 ICH_PCR, ICH_SCR, ICH_SIS_TCR 2956 }; 2957 2958 static int snd_intel8x0_inside_vm(struct pci_dev *pci) 2959 { 2960 int result = inside_vm; 2961 char *msg = NULL; 2962 2963 /* check module parameter first (override detection) */ 2964 if (result >= 0) { 2965 msg = result ? "enable (forced) VM" : "disable (forced) VM"; 2966 goto fini; 2967 } 2968 2969 /* check for known (emulated) devices */ 2970 result = 0; 2971 if (pci->subsystem_vendor == PCI_SUBVENDOR_ID_REDHAT_QUMRANET && 2972 pci->subsystem_device == PCI_SUBDEVICE_ID_QEMU) { 2973 /* KVM emulated sound, PCI SSID: 1af4:1100 */ 2974 msg = "enable KVM"; 2975 result = 1; 2976 } else if (pci->subsystem_vendor == 0x1ab8) { 2977 /* Parallels VM emulated sound, PCI SSID: 1ab8:xxxx */ 2978 msg = "enable Parallels VM"; 2979 result = 1; 2980 } 2981 2982 fini: 2983 if (msg != NULL) 2984 dev_info(&pci->dev, "%s optimization\n", msg); 2985 2986 return result; 2987 } 2988 2989 static int snd_intel8x0_create(struct snd_card *card, 2990 struct pci_dev *pci, 2991 unsigned long device_type, 2992 struct intel8x0 **r_intel8x0) 2993 { 2994 struct intel8x0 *chip; 2995 int err; 2996 unsigned int i; 2997 unsigned int int_sta_masks; 2998 struct ichdev *ichdev; 2999 static struct snd_device_ops ops = { 3000 .dev_free = snd_intel8x0_dev_free, 3001 }; 3002 3003 static unsigned int bdbars[] = { 3004 3, /* DEVICE_INTEL */ 3005 6, /* DEVICE_INTEL_ICH4 */ 3006 3, /* DEVICE_SIS */ 3007 6, /* DEVICE_ALI */ 3008 4, /* DEVICE_NFORCE */ 3009 }; 3010 static struct ich_reg_info intel_regs[6] = { 3011 { ICH_PIINT, 0 }, 3012 { ICH_POINT, 0x10 }, 3013 { ICH_MCINT, 0x20 }, 3014 { ICH_M2INT, 0x40 }, 3015 { ICH_P2INT, 0x50 }, 3016 { ICH_SPINT, 0x60 }, 3017 }; 3018 static struct ich_reg_info nforce_regs[4] = { 3019 { ICH_PIINT, 0 }, 3020 { ICH_POINT, 0x10 }, 3021 { ICH_MCINT, 0x20 }, 3022 { ICH_NVSPINT, 0x70 }, 3023 }; 3024 static struct ich_reg_info ali_regs[6] = { 3025 { ALI_INT_PCMIN, 0x40 }, 3026 { ALI_INT_PCMOUT, 0x50 }, 3027 { ALI_INT_MICIN, 0x60 }, 3028 { ALI_INT_CODECSPDIFOUT, 0x70 }, 3029 { ALI_INT_SPDIFIN, 0xa0 }, 3030 { ALI_INT_SPDIFOUT, 0xb0 }, 3031 }; 3032 struct ich_reg_info *tbl; 3033 3034 *r_intel8x0 = NULL; 3035 3036 if ((err = pci_enable_device(pci)) < 0) 3037 return err; 3038 3039 chip = kzalloc(sizeof(*chip), GFP_KERNEL); 3040 if (chip == NULL) { 3041 pci_disable_device(pci); 3042 return -ENOMEM; 3043 } 3044 spin_lock_init(&chip->reg_lock); 3045 chip->device_type = device_type; 3046 chip->card = card; 3047 chip->pci = pci; 3048 chip->irq = -1; 3049 3050 /* module parameters */ 3051 chip->buggy_irq = buggy_irq; 3052 chip->buggy_semaphore = buggy_semaphore; 3053 if (xbox) 3054 chip->xbox = 1; 3055 3056 chip->inside_vm = snd_intel8x0_inside_vm(pci); 3057 3058 if (pci->vendor == PCI_VENDOR_ID_INTEL && 3059 pci->device == PCI_DEVICE_ID_INTEL_440MX) 3060 chip->fix_nocache = 1; /* enable workaround */ 3061 3062 if ((err = pci_request_regions(pci, card->shortname)) < 0) { 3063 kfree(chip); 3064 pci_disable_device(pci); 3065 return err; 3066 } 3067 3068 if (device_type == DEVICE_ALI) { 3069 /* ALI5455 has no ac97 region */ 3070 chip->bmaddr = pci_iomap(pci, 0, 0); 3071 goto port_inited; 3072 } 3073 3074 if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) /* ICH4 and Nforce */ 3075 chip->addr = pci_iomap(pci, 2, 0); 3076 else 3077 chip->addr = pci_iomap(pci, 0, 0); 3078 if (!chip->addr) { 3079 dev_err(card->dev, "AC'97 space ioremap problem\n"); 3080 snd_intel8x0_free(chip); 3081 return -EIO; 3082 } 3083 if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) /* ICH4 */ 3084 chip->bmaddr = pci_iomap(pci, 3, 0); 3085 else 3086 chip->bmaddr = pci_iomap(pci, 1, 0); 3087 3088 port_inited: 3089 if (!chip->bmaddr) { 3090 dev_err(card->dev, "Controller space ioremap problem\n"); 3091 snd_intel8x0_free(chip); 3092 return -EIO; 3093 } 3094 chip->bdbars_count = bdbars[device_type]; 3095 3096 /* initialize offsets */ 3097 switch (device_type) { 3098 case DEVICE_NFORCE: 3099 tbl = nforce_regs; 3100 break; 3101 case DEVICE_ALI: 3102 tbl = ali_regs; 3103 break; 3104 default: 3105 tbl = intel_regs; 3106 break; 3107 } 3108 for (i = 0; i < chip->bdbars_count; i++) { 3109 ichdev = &chip->ichd[i]; 3110 ichdev->ichd = i; 3111 ichdev->reg_offset = tbl[i].offset; 3112 ichdev->int_sta_mask = tbl[i].int_sta_mask; 3113 if (device_type == DEVICE_SIS) { 3114 /* SiS 7012 swaps the registers */ 3115 ichdev->roff_sr = ICH_REG_OFF_PICB; 3116 ichdev->roff_picb = ICH_REG_OFF_SR; 3117 } else { 3118 ichdev->roff_sr = ICH_REG_OFF_SR; 3119 ichdev->roff_picb = ICH_REG_OFF_PICB; 3120 } 3121 if (device_type == DEVICE_ALI) 3122 ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10; 3123 /* SIS7012 handles the pcm data in bytes, others are in samples */ 3124 ichdev->pos_shift = (device_type == DEVICE_SIS) ? 0 : 1; 3125 } 3126 3127 /* allocate buffer descriptor lists */ 3128 /* the start of each lists must be aligned to 8 bytes */ 3129 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci), 3130 chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2, 3131 &chip->bdbars) < 0) { 3132 snd_intel8x0_free(chip); 3133 dev_err(card->dev, "cannot allocate buffer descriptors\n"); 3134 return -ENOMEM; 3135 } 3136 /* tables must be aligned to 8 bytes here, but the kernel pages 3137 are much bigger, so we don't care (on i386) */ 3138 /* workaround for 440MX */ 3139 if (chip->fix_nocache) 3140 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1); 3141 int_sta_masks = 0; 3142 for (i = 0; i < chip->bdbars_count; i++) { 3143 ichdev = &chip->ichd[i]; 3144 ichdev->bdbar = ((u32 *)chip->bdbars.area) + 3145 (i * ICH_MAX_FRAGS * 2); 3146 ichdev->bdbar_addr = chip->bdbars.addr + 3147 (i * sizeof(u32) * ICH_MAX_FRAGS * 2); 3148 int_sta_masks |= ichdev->int_sta_mask; 3149 } 3150 chip->int_sta_reg = device_type == DEVICE_ALI ? 3151 ICH_REG_ALI_INTERRUPTSR : ICH_REG_GLOB_STA; 3152 chip->int_sta_mask = int_sta_masks; 3153 3154 pci_set_master(pci); 3155 3156 switch(chip->device_type) { 3157 case DEVICE_INTEL_ICH4: 3158 /* ICH4 can have three codecs */ 3159 chip->max_codecs = 3; 3160 chip->codec_bit = ich_codec_bits; 3161 chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_TRI; 3162 break; 3163 case DEVICE_SIS: 3164 /* recent SIS7012 can have three codecs */ 3165 chip->max_codecs = 3; 3166 chip->codec_bit = sis_codec_bits; 3167 chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_SIS_TRI; 3168 break; 3169 default: 3170 /* others up to two codecs */ 3171 chip->max_codecs = 2; 3172 chip->codec_bit = ich_codec_bits; 3173 chip->codec_ready_bits = ICH_PRI | ICH_SRI; 3174 break; 3175 } 3176 for (i = 0; i < chip->max_codecs; i++) 3177 chip->codec_isr_bits |= chip->codec_bit[i]; 3178 3179 if ((err = snd_intel8x0_chip_init(chip, 1)) < 0) { 3180 snd_intel8x0_free(chip); 3181 return err; 3182 } 3183 3184 /* request irq after initializaing int_sta_mask, etc */ 3185 if (request_irq(pci->irq, snd_intel8x0_interrupt, 3186 IRQF_SHARED, KBUILD_MODNAME, chip)) { 3187 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq); 3188 snd_intel8x0_free(chip); 3189 return -EBUSY; 3190 } 3191 chip->irq = pci->irq; 3192 3193 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) { 3194 snd_intel8x0_free(chip); 3195 return err; 3196 } 3197 3198 *r_intel8x0 = chip; 3199 return 0; 3200 } 3201 3202 static struct shortname_table { 3203 unsigned int id; 3204 const char *s; 3205 } shortnames[] = { 3206 { PCI_DEVICE_ID_INTEL_82801AA_5, "Intel 82801AA-ICH" }, 3207 { PCI_DEVICE_ID_INTEL_82801AB_5, "Intel 82901AB-ICH0" }, 3208 { PCI_DEVICE_ID_INTEL_82801BA_4, "Intel 82801BA-ICH2" }, 3209 { PCI_DEVICE_ID_INTEL_440MX, "Intel 440MX" }, 3210 { PCI_DEVICE_ID_INTEL_82801CA_5, "Intel 82801CA-ICH3" }, 3211 { PCI_DEVICE_ID_INTEL_82801DB_5, "Intel 82801DB-ICH4" }, 3212 { PCI_DEVICE_ID_INTEL_82801EB_5, "Intel ICH5" }, 3213 { PCI_DEVICE_ID_INTEL_ESB_5, "Intel 6300ESB" }, 3214 { PCI_DEVICE_ID_INTEL_ICH6_18, "Intel ICH6" }, 3215 { PCI_DEVICE_ID_INTEL_ICH7_20, "Intel ICH7" }, 3216 { PCI_DEVICE_ID_INTEL_ESB2_14, "Intel ESB2" }, 3217 { PCI_DEVICE_ID_SI_7012, "SiS SI7012" }, 3218 { PCI_DEVICE_ID_NVIDIA_MCP1_AUDIO, "NVidia nForce" }, 3219 { PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO, "NVidia nForce2" }, 3220 { PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO, "NVidia nForce3" }, 3221 { PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO, "NVidia CK8S" }, 3222 { PCI_DEVICE_ID_NVIDIA_CK804_AUDIO, "NVidia CK804" }, 3223 { PCI_DEVICE_ID_NVIDIA_CK8_AUDIO, "NVidia CK8" }, 3224 { 0x003a, "NVidia MCP04" }, 3225 { 0x746d, "AMD AMD8111" }, 3226 { 0x7445, "AMD AMD768" }, 3227 { 0x5455, "ALi M5455" }, 3228 { 0, NULL }, 3229 }; 3230 3231 static struct snd_pci_quirk spdif_aclink_defaults[] = { 3232 SND_PCI_QUIRK(0x147b, 0x1c1a, "ASUS KN8", 1), 3233 { } /* end */ 3234 }; 3235 3236 /* look up white/black list for SPDIF over ac-link */ 3237 static int check_default_spdif_aclink(struct pci_dev *pci) 3238 { 3239 const struct snd_pci_quirk *w; 3240 3241 w = snd_pci_quirk_lookup(pci, spdif_aclink_defaults); 3242 if (w) { 3243 if (w->value) 3244 dev_dbg(&pci->dev, 3245 "Using SPDIF over AC-Link for %s\n", 3246 snd_pci_quirk_name(w)); 3247 else 3248 dev_dbg(&pci->dev, 3249 "Using integrated SPDIF DMA for %s\n", 3250 snd_pci_quirk_name(w)); 3251 return w->value; 3252 } 3253 return 0; 3254 } 3255 3256 static int snd_intel8x0_probe(struct pci_dev *pci, 3257 const struct pci_device_id *pci_id) 3258 { 3259 struct snd_card *card; 3260 struct intel8x0 *chip; 3261 int err; 3262 struct shortname_table *name; 3263 3264 err = snd_card_new(&pci->dev, index, id, THIS_MODULE, 0, &card); 3265 if (err < 0) 3266 return err; 3267 3268 if (spdif_aclink < 0) 3269 spdif_aclink = check_default_spdif_aclink(pci); 3270 3271 strcpy(card->driver, "ICH"); 3272 if (!spdif_aclink) { 3273 switch (pci_id->driver_data) { 3274 case DEVICE_NFORCE: 3275 strcpy(card->driver, "NFORCE"); 3276 break; 3277 case DEVICE_INTEL_ICH4: 3278 strcpy(card->driver, "ICH4"); 3279 } 3280 } 3281 3282 strcpy(card->shortname, "Intel ICH"); 3283 for (name = shortnames; name->id; name++) { 3284 if (pci->device == name->id) { 3285 strcpy(card->shortname, name->s); 3286 break; 3287 } 3288 } 3289 3290 if (buggy_irq < 0) { 3291 /* some Nforce[2] and ICH boards have problems with IRQ handling. 3292 * Needs to return IRQ_HANDLED for unknown irqs. 3293 */ 3294 if (pci_id->driver_data == DEVICE_NFORCE) 3295 buggy_irq = 1; 3296 else 3297 buggy_irq = 0; 3298 } 3299 3300 if ((err = snd_intel8x0_create(card, pci, pci_id->driver_data, 3301 &chip)) < 0) { 3302 snd_card_free(card); 3303 return err; 3304 } 3305 card->private_data = chip; 3306 3307 if ((err = snd_intel8x0_mixer(chip, ac97_clock, ac97_quirk)) < 0) { 3308 snd_card_free(card); 3309 return err; 3310 } 3311 if ((err = snd_intel8x0_pcm(chip)) < 0) { 3312 snd_card_free(card); 3313 return err; 3314 } 3315 3316 snd_intel8x0_proc_init(chip); 3317 3318 snprintf(card->longname, sizeof(card->longname), 3319 "%s with %s at irq %i", card->shortname, 3320 snd_ac97_get_short_name(chip->ac97[0]), chip->irq); 3321 3322 if (ac97_clock == 0 || ac97_clock == 1) { 3323 if (ac97_clock == 0) { 3324 if (intel8x0_in_clock_list(chip) == 0) 3325 intel8x0_measure_ac97_clock(chip); 3326 } else { 3327 intel8x0_measure_ac97_clock(chip); 3328 } 3329 } 3330 3331 if ((err = snd_card_register(card)) < 0) { 3332 snd_card_free(card); 3333 return err; 3334 } 3335 pci_set_drvdata(pci, card); 3336 return 0; 3337 } 3338 3339 static void snd_intel8x0_remove(struct pci_dev *pci) 3340 { 3341 snd_card_free(pci_get_drvdata(pci)); 3342 } 3343 3344 static struct pci_driver intel8x0_driver = { 3345 .name = KBUILD_MODNAME, 3346 .id_table = snd_intel8x0_ids, 3347 .probe = snd_intel8x0_probe, 3348 .remove = snd_intel8x0_remove, 3349 .driver = { 3350 .pm = INTEL8X0_PM_OPS, 3351 }, 3352 }; 3353 3354 module_pci_driver(intel8x0_driver); 3355