1 /* 2 * ALSA driver for Intel ICH (i8x0) chipsets 3 * 4 * Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz> 5 * 6 * 7 * This code also contains alpha support for SiS 735 chipsets provided 8 * by Mike Pieper <mptei@users.sourceforge.net>. We have no datasheet 9 * for SiS735, so the code is not fully functional. 10 * 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License as published by 14 * the Free Software Foundation; either version 2 of the License, or 15 * (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 25 26 * 27 */ 28 29 #include <asm/io.h> 30 #include <linux/delay.h> 31 #include <linux/interrupt.h> 32 #include <linux/init.h> 33 #include <linux/pci.h> 34 #include <linux/slab.h> 35 #include <linux/module.h> 36 #include <sound/core.h> 37 #include <sound/pcm.h> 38 #include <sound/ac97_codec.h> 39 #include <sound/info.h> 40 #include <sound/initval.h> 41 /* for 440MX workaround */ 42 #include <asm/pgtable.h> 43 #include <asm/cacheflush.h> 44 45 #ifdef CONFIG_KVM_GUEST 46 #include <linux/kvm_para.h> 47 #else 48 #define kvm_para_available() (0) 49 #endif 50 51 MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>"); 52 MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; SiS 7012; Ali 5455"); 53 MODULE_LICENSE("GPL"); 54 MODULE_SUPPORTED_DEVICE("{{Intel,82801AA-ICH}," 55 "{Intel,82901AB-ICH0}," 56 "{Intel,82801BA-ICH2}," 57 "{Intel,82801CA-ICH3}," 58 "{Intel,82801DB-ICH4}," 59 "{Intel,ICH5}," 60 "{Intel,ICH6}," 61 "{Intel,ICH7}," 62 "{Intel,6300ESB}," 63 "{Intel,ESB2}," 64 "{Intel,MX440}," 65 "{SiS,SI7012}," 66 "{NVidia,nForce Audio}," 67 "{NVidia,nForce2 Audio}," 68 "{NVidia,nForce3 Audio}," 69 "{NVidia,MCP04}," 70 "{NVidia,MCP501}," 71 "{NVidia,CK804}," 72 "{NVidia,CK8}," 73 "{NVidia,CK8S}," 74 "{AMD,AMD768}," 75 "{AMD,AMD8111}," 76 "{ALI,M5455}}"); 77 78 static int index = SNDRV_DEFAULT_IDX1; /* Index 0-MAX */ 79 static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */ 80 static int ac97_clock; 81 static char *ac97_quirk; 82 static int buggy_semaphore; 83 static int buggy_irq = -1; /* auto-check */ 84 static int xbox; 85 static int spdif_aclink = -1; 86 static int inside_vm = -1; 87 88 module_param(index, int, 0444); 89 MODULE_PARM_DESC(index, "Index value for Intel i8x0 soundcard."); 90 module_param(id, charp, 0444); 91 MODULE_PARM_DESC(id, "ID string for Intel i8x0 soundcard."); 92 module_param(ac97_clock, int, 0444); 93 MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = whitelist + auto-detect, 1 = force autodetect)."); 94 module_param(ac97_quirk, charp, 0444); 95 MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware."); 96 module_param(buggy_semaphore, bool, 0444); 97 MODULE_PARM_DESC(buggy_semaphore, "Enable workaround for hardwares with problematic codec semaphores."); 98 module_param(buggy_irq, bool, 0444); 99 MODULE_PARM_DESC(buggy_irq, "Enable workaround for buggy interrupts on some motherboards."); 100 module_param(xbox, bool, 0444); 101 MODULE_PARM_DESC(xbox, "Set to 1 for Xbox, if you have problems with the AC'97 codec detection."); 102 module_param(spdif_aclink, int, 0444); 103 MODULE_PARM_DESC(spdif_aclink, "S/PDIF over AC-link."); 104 module_param(inside_vm, bool, 0444); 105 MODULE_PARM_DESC(inside_vm, "KVM/Parallels optimization."); 106 107 /* just for backward compatibility */ 108 static int enable; 109 module_param(enable, bool, 0444); 110 static int joystick; 111 module_param(joystick, int, 0444); 112 113 /* 114 * Direct registers 115 */ 116 enum { DEVICE_INTEL, DEVICE_INTEL_ICH4, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE }; 117 118 #define ICHREG(x) ICH_REG_##x 119 120 #define DEFINE_REGSET(name,base) \ 121 enum { \ 122 ICH_REG_##name##_BDBAR = base + 0x0, /* dword - buffer descriptor list base address */ \ 123 ICH_REG_##name##_CIV = base + 0x04, /* byte - current index value */ \ 124 ICH_REG_##name##_LVI = base + 0x05, /* byte - last valid index */ \ 125 ICH_REG_##name##_SR = base + 0x06, /* byte - status register */ \ 126 ICH_REG_##name##_PICB = base + 0x08, /* word - position in current buffer */ \ 127 ICH_REG_##name##_PIV = base + 0x0a, /* byte - prefetched index value */ \ 128 ICH_REG_##name##_CR = base + 0x0b, /* byte - control register */ \ 129 }; 130 131 /* busmaster blocks */ 132 DEFINE_REGSET(OFF, 0); /* offset */ 133 DEFINE_REGSET(PI, 0x00); /* PCM in */ 134 DEFINE_REGSET(PO, 0x10); /* PCM out */ 135 DEFINE_REGSET(MC, 0x20); /* Mic in */ 136 137 /* ICH4 busmaster blocks */ 138 DEFINE_REGSET(MC2, 0x40); /* Mic in 2 */ 139 DEFINE_REGSET(PI2, 0x50); /* PCM in 2 */ 140 DEFINE_REGSET(SP, 0x60); /* SPDIF out */ 141 142 /* values for each busmaster block */ 143 144 /* LVI */ 145 #define ICH_REG_LVI_MASK 0x1f 146 147 /* SR */ 148 #define ICH_FIFOE 0x10 /* FIFO error */ 149 #define ICH_BCIS 0x08 /* buffer completion interrupt status */ 150 #define ICH_LVBCI 0x04 /* last valid buffer completion interrupt */ 151 #define ICH_CELV 0x02 /* current equals last valid */ 152 #define ICH_DCH 0x01 /* DMA controller halted */ 153 154 /* PIV */ 155 #define ICH_REG_PIV_MASK 0x1f /* mask */ 156 157 /* CR */ 158 #define ICH_IOCE 0x10 /* interrupt on completion enable */ 159 #define ICH_FEIE 0x08 /* fifo error interrupt enable */ 160 #define ICH_LVBIE 0x04 /* last valid buffer interrupt enable */ 161 #define ICH_RESETREGS 0x02 /* reset busmaster registers */ 162 #define ICH_STARTBM 0x01 /* start busmaster operation */ 163 164 165 /* global block */ 166 #define ICH_REG_GLOB_CNT 0x2c /* dword - global control */ 167 #define ICH_PCM_SPDIF_MASK 0xc0000000 /* s/pdif pcm slot mask (ICH4) */ 168 #define ICH_PCM_SPDIF_NONE 0x00000000 /* reserved - undefined */ 169 #define ICH_PCM_SPDIF_78 0x40000000 /* s/pdif pcm on slots 7&8 */ 170 #define ICH_PCM_SPDIF_69 0x80000000 /* s/pdif pcm on slots 6&9 */ 171 #define ICH_PCM_SPDIF_1011 0xc0000000 /* s/pdif pcm on slots 10&11 */ 172 #define ICH_PCM_20BIT 0x00400000 /* 20-bit samples (ICH4) */ 173 #define ICH_PCM_246_MASK 0x00300000 /* chan mask (not all chips) */ 174 #define ICH_PCM_8 0x00300000 /* 8 channels (not all chips) */ 175 #define ICH_PCM_6 0x00200000 /* 6 channels (not all chips) */ 176 #define ICH_PCM_4 0x00100000 /* 4 channels (not all chips) */ 177 #define ICH_PCM_2 0x00000000 /* 2 channels (stereo) */ 178 #define ICH_SIS_PCM_246_MASK 0x000000c0 /* 6 channels (SIS7012) */ 179 #define ICH_SIS_PCM_6 0x00000080 /* 6 channels (SIS7012) */ 180 #define ICH_SIS_PCM_4 0x00000040 /* 4 channels (SIS7012) */ 181 #define ICH_SIS_PCM_2 0x00000000 /* 2 channels (SIS7012) */ 182 #define ICH_TRIE 0x00000040 /* tertiary resume interrupt enable */ 183 #define ICH_SRIE 0x00000020 /* secondary resume interrupt enable */ 184 #define ICH_PRIE 0x00000010 /* primary resume interrupt enable */ 185 #define ICH_ACLINK 0x00000008 /* AClink shut off */ 186 #define ICH_AC97WARM 0x00000004 /* AC'97 warm reset */ 187 #define ICH_AC97COLD 0x00000002 /* AC'97 cold reset */ 188 #define ICH_GIE 0x00000001 /* GPI interrupt enable */ 189 #define ICH_REG_GLOB_STA 0x30 /* dword - global status */ 190 #define ICH_TRI 0x20000000 /* ICH4: tertiary (AC_SDIN2) resume interrupt */ 191 #define ICH_TCR 0x10000000 /* ICH4: tertiary (AC_SDIN2) codec ready */ 192 #define ICH_BCS 0x08000000 /* ICH4: bit clock stopped */ 193 #define ICH_SPINT 0x04000000 /* ICH4: S/PDIF interrupt */ 194 #define ICH_P2INT 0x02000000 /* ICH4: PCM2-In interrupt */ 195 #define ICH_M2INT 0x01000000 /* ICH4: Mic2-In interrupt */ 196 #define ICH_SAMPLE_CAP 0x00c00000 /* ICH4: sample capability bits (RO) */ 197 #define ICH_SAMPLE_16_20 0x00400000 /* ICH4: 16- and 20-bit samples */ 198 #define ICH_MULTICHAN_CAP 0x00300000 /* ICH4: multi-channel capability bits (RO) */ 199 #define ICH_SIS_TRI 0x00080000 /* SIS: tertiary resume irq */ 200 #define ICH_SIS_TCR 0x00040000 /* SIS: tertiary codec ready */ 201 #define ICH_MD3 0x00020000 /* modem power down semaphore */ 202 #define ICH_AD3 0x00010000 /* audio power down semaphore */ 203 #define ICH_RCS 0x00008000 /* read completion status */ 204 #define ICH_BIT3 0x00004000 /* bit 3 slot 12 */ 205 #define ICH_BIT2 0x00002000 /* bit 2 slot 12 */ 206 #define ICH_BIT1 0x00001000 /* bit 1 slot 12 */ 207 #define ICH_SRI 0x00000800 /* secondary (AC_SDIN1) resume interrupt */ 208 #define ICH_PRI 0x00000400 /* primary (AC_SDIN0) resume interrupt */ 209 #define ICH_SCR 0x00000200 /* secondary (AC_SDIN1) codec ready */ 210 #define ICH_PCR 0x00000100 /* primary (AC_SDIN0) codec ready */ 211 #define ICH_MCINT 0x00000080 /* MIC capture interrupt */ 212 #define ICH_POINT 0x00000040 /* playback interrupt */ 213 #define ICH_PIINT 0x00000020 /* capture interrupt */ 214 #define ICH_NVSPINT 0x00000010 /* nforce spdif interrupt */ 215 #define ICH_MOINT 0x00000004 /* modem playback interrupt */ 216 #define ICH_MIINT 0x00000002 /* modem capture interrupt */ 217 #define ICH_GSCI 0x00000001 /* GPI status change interrupt */ 218 #define ICH_REG_ACC_SEMA 0x34 /* byte - codec write semaphore */ 219 #define ICH_CAS 0x01 /* codec access semaphore */ 220 #define ICH_REG_SDM 0x80 221 #define ICH_DI2L_MASK 0x000000c0 /* PCM In 2, Mic In 2 data in line */ 222 #define ICH_DI2L_SHIFT 6 223 #define ICH_DI1L_MASK 0x00000030 /* PCM In 1, Mic In 1 data in line */ 224 #define ICH_DI1L_SHIFT 4 225 #define ICH_SE 0x00000008 /* steer enable */ 226 #define ICH_LDI_MASK 0x00000003 /* last codec read data input */ 227 228 #define ICH_MAX_FRAGS 32 /* max hw frags */ 229 230 231 /* 232 * registers for Ali5455 233 */ 234 235 /* ALi 5455 busmaster blocks */ 236 DEFINE_REGSET(AL_PI, 0x40); /* ALi PCM in */ 237 DEFINE_REGSET(AL_PO, 0x50); /* Ali PCM out */ 238 DEFINE_REGSET(AL_MC, 0x60); /* Ali Mic in */ 239 DEFINE_REGSET(AL_CDC_SPO, 0x70); /* Ali Codec SPDIF out */ 240 DEFINE_REGSET(AL_CENTER, 0x80); /* Ali center out */ 241 DEFINE_REGSET(AL_LFE, 0x90); /* Ali center out */ 242 DEFINE_REGSET(AL_CLR_SPI, 0xa0); /* Ali Controller SPDIF in */ 243 DEFINE_REGSET(AL_CLR_SPO, 0xb0); /* Ali Controller SPDIF out */ 244 DEFINE_REGSET(AL_I2S, 0xc0); /* Ali I2S in */ 245 DEFINE_REGSET(AL_PI2, 0xd0); /* Ali PCM2 in */ 246 DEFINE_REGSET(AL_MC2, 0xe0); /* Ali Mic2 in */ 247 248 enum { 249 ICH_REG_ALI_SCR = 0x00, /* System Control Register */ 250 ICH_REG_ALI_SSR = 0x04, /* System Status Register */ 251 ICH_REG_ALI_DMACR = 0x08, /* DMA Control Register */ 252 ICH_REG_ALI_FIFOCR1 = 0x0c, /* FIFO Control Register 1 */ 253 ICH_REG_ALI_INTERFACECR = 0x10, /* Interface Control Register */ 254 ICH_REG_ALI_INTERRUPTCR = 0x14, /* Interrupt control Register */ 255 ICH_REG_ALI_INTERRUPTSR = 0x18, /* Interrupt Status Register */ 256 ICH_REG_ALI_FIFOCR2 = 0x1c, /* FIFO Control Register 2 */ 257 ICH_REG_ALI_CPR = 0x20, /* Command Port Register */ 258 ICH_REG_ALI_CPR_ADDR = 0x22, /* ac97 addr write */ 259 ICH_REG_ALI_SPR = 0x24, /* Status Port Register */ 260 ICH_REG_ALI_SPR_ADDR = 0x26, /* ac97 addr read */ 261 ICH_REG_ALI_FIFOCR3 = 0x2c, /* FIFO Control Register 3 */ 262 ICH_REG_ALI_TTSR = 0x30, /* Transmit Tag Slot Register */ 263 ICH_REG_ALI_RTSR = 0x34, /* Receive Tag Slot Register */ 264 ICH_REG_ALI_CSPSR = 0x38, /* Command/Status Port Status Register */ 265 ICH_REG_ALI_CAS = 0x3c, /* Codec Write Semaphore Register */ 266 ICH_REG_ALI_HWVOL = 0xf0, /* hardware volume control/status */ 267 ICH_REG_ALI_I2SCR = 0xf4, /* I2S control/status */ 268 ICH_REG_ALI_SPDIFCSR = 0xf8, /* spdif channel status register */ 269 ICH_REG_ALI_SPDIFICS = 0xfc, /* spdif interface control/status */ 270 }; 271 272 #define ALI_CAS_SEM_BUSY 0x80000000 273 #define ALI_CPR_ADDR_SECONDARY 0x100 274 #define ALI_CPR_ADDR_READ 0x80 275 #define ALI_CSPSR_CODEC_READY 0x08 276 #define ALI_CSPSR_READ_OK 0x02 277 #define ALI_CSPSR_WRITE_OK 0x01 278 279 /* interrupts for the whole chip by interrupt status register finish */ 280 281 #define ALI_INT_MICIN2 (1<<26) 282 #define ALI_INT_PCMIN2 (1<<25) 283 #define ALI_INT_I2SIN (1<<24) 284 #define ALI_INT_SPDIFOUT (1<<23) /* controller spdif out INTERRUPT */ 285 #define ALI_INT_SPDIFIN (1<<22) 286 #define ALI_INT_LFEOUT (1<<21) 287 #define ALI_INT_CENTEROUT (1<<20) 288 #define ALI_INT_CODECSPDIFOUT (1<<19) 289 #define ALI_INT_MICIN (1<<18) 290 #define ALI_INT_PCMOUT (1<<17) 291 #define ALI_INT_PCMIN (1<<16) 292 #define ALI_INT_CPRAIS (1<<7) /* command port available */ 293 #define ALI_INT_SPRAIS (1<<5) /* status port available */ 294 #define ALI_INT_GPIO (1<<1) 295 #define ALI_INT_MASK (ALI_INT_SPDIFOUT|ALI_INT_CODECSPDIFOUT|\ 296 ALI_INT_MICIN|ALI_INT_PCMOUT|ALI_INT_PCMIN) 297 298 #define ICH_ALI_SC_RESET (1<<31) /* master reset */ 299 #define ICH_ALI_SC_AC97_DBL (1<<30) 300 #define ICH_ALI_SC_CODEC_SPDF (3<<20) /* 1=7/8, 2=6/9, 3=10/11 */ 301 #define ICH_ALI_SC_IN_BITS (3<<18) 302 #define ICH_ALI_SC_OUT_BITS (3<<16) 303 #define ICH_ALI_SC_6CH_CFG (3<<14) 304 #define ICH_ALI_SC_PCM_4 (1<<8) 305 #define ICH_ALI_SC_PCM_6 (2<<8) 306 #define ICH_ALI_SC_PCM_246_MASK (3<<8) 307 308 #define ICH_ALI_SS_SEC_ID (3<<5) 309 #define ICH_ALI_SS_PRI_ID (3<<3) 310 311 #define ICH_ALI_IF_AC97SP (1<<21) 312 #define ICH_ALI_IF_MC (1<<20) 313 #define ICH_ALI_IF_PI (1<<19) 314 #define ICH_ALI_IF_MC2 (1<<18) 315 #define ICH_ALI_IF_PI2 (1<<17) 316 #define ICH_ALI_IF_LINE_SRC (1<<15) /* 0/1 = slot 3/6 */ 317 #define ICH_ALI_IF_MIC_SRC (1<<14) /* 0/1 = slot 3/6 */ 318 #define ICH_ALI_IF_SPDF_SRC (3<<12) /* 00 = PCM, 01 = AC97-in, 10 = spdif-in, 11 = i2s */ 319 #define ICH_ALI_IF_AC97_OUT (3<<8) /* 00 = PCM, 10 = spdif-in, 11 = i2s */ 320 #define ICH_ALI_IF_PO_SPDF (1<<3) 321 #define ICH_ALI_IF_PO (1<<1) 322 323 /* 324 * 325 */ 326 327 enum { 328 ICHD_PCMIN, 329 ICHD_PCMOUT, 330 ICHD_MIC, 331 ICHD_MIC2, 332 ICHD_PCM2IN, 333 ICHD_SPBAR, 334 ICHD_LAST = ICHD_SPBAR 335 }; 336 enum { 337 NVD_PCMIN, 338 NVD_PCMOUT, 339 NVD_MIC, 340 NVD_SPBAR, 341 NVD_LAST = NVD_SPBAR 342 }; 343 enum { 344 ALID_PCMIN, 345 ALID_PCMOUT, 346 ALID_MIC, 347 ALID_AC97SPDIFOUT, 348 ALID_SPDIFIN, 349 ALID_SPDIFOUT, 350 ALID_LAST = ALID_SPDIFOUT 351 }; 352 353 #define get_ichdev(substream) (substream->runtime->private_data) 354 355 struct ichdev { 356 unsigned int ichd; /* ich device number */ 357 unsigned long reg_offset; /* offset to bmaddr */ 358 u32 *bdbar; /* CPU address (32bit) */ 359 unsigned int bdbar_addr; /* PCI bus address (32bit) */ 360 struct snd_pcm_substream *substream; 361 unsigned int physbuf; /* physical address (32bit) */ 362 unsigned int size; 363 unsigned int fragsize; 364 unsigned int fragsize1; 365 unsigned int position; 366 unsigned int pos_shift; 367 unsigned int last_pos; 368 int frags; 369 int lvi; 370 int lvi_frag; 371 int civ; 372 int ack; 373 int ack_reload; 374 unsigned int ack_bit; 375 unsigned int roff_sr; 376 unsigned int roff_picb; 377 unsigned int int_sta_mask; /* interrupt status mask */ 378 unsigned int ali_slot; /* ALI DMA slot */ 379 struct ac97_pcm *pcm; 380 int pcm_open_flag; 381 unsigned int page_attr_changed: 1; 382 unsigned int suspended: 1; 383 }; 384 385 struct intel8x0 { 386 unsigned int device_type; 387 388 int irq; 389 390 void __iomem *addr; 391 void __iomem *bmaddr; 392 393 struct pci_dev *pci; 394 struct snd_card *card; 395 396 int pcm_devs; 397 struct snd_pcm *pcm[6]; 398 struct ichdev ichd[6]; 399 400 unsigned multi4: 1, 401 multi6: 1, 402 multi8 :1, 403 dra: 1, 404 smp20bit: 1; 405 unsigned in_ac97_init: 1, 406 in_sdin_init: 1; 407 unsigned in_measurement: 1; /* during ac97 clock measurement */ 408 unsigned fix_nocache: 1; /* workaround for 440MX */ 409 unsigned buggy_irq: 1; /* workaround for buggy mobos */ 410 unsigned xbox: 1; /* workaround for Xbox AC'97 detection */ 411 unsigned buggy_semaphore: 1; /* workaround for buggy codec semaphore */ 412 unsigned inside_vm: 1; /* enable VM optimization */ 413 414 int spdif_idx; /* SPDIF BAR index; *_SPBAR or -1 if use PCMOUT */ 415 unsigned int sdm_saved; /* SDM reg value */ 416 417 struct snd_ac97_bus *ac97_bus; 418 struct snd_ac97 *ac97[3]; 419 unsigned int ac97_sdin[3]; 420 unsigned int max_codecs, ncodecs; 421 unsigned int *codec_bit; 422 unsigned int codec_isr_bits; 423 unsigned int codec_ready_bits; 424 425 spinlock_t reg_lock; 426 427 u32 bdbars_count; 428 struct snd_dma_buffer bdbars; 429 u32 int_sta_reg; /* interrupt status register */ 430 u32 int_sta_mask; /* interrupt status mask */ 431 }; 432 433 static DEFINE_PCI_DEVICE_TABLE(snd_intel8x0_ids) = { 434 { PCI_VDEVICE(INTEL, 0x2415), DEVICE_INTEL }, /* 82801AA */ 435 { PCI_VDEVICE(INTEL, 0x2425), DEVICE_INTEL }, /* 82901AB */ 436 { PCI_VDEVICE(INTEL, 0x2445), DEVICE_INTEL }, /* 82801BA */ 437 { PCI_VDEVICE(INTEL, 0x2485), DEVICE_INTEL }, /* ICH3 */ 438 { PCI_VDEVICE(INTEL, 0x24c5), DEVICE_INTEL_ICH4 }, /* ICH4 */ 439 { PCI_VDEVICE(INTEL, 0x24d5), DEVICE_INTEL_ICH4 }, /* ICH5 */ 440 { PCI_VDEVICE(INTEL, 0x25a6), DEVICE_INTEL_ICH4 }, /* ESB */ 441 { PCI_VDEVICE(INTEL, 0x266e), DEVICE_INTEL_ICH4 }, /* ICH6 */ 442 { PCI_VDEVICE(INTEL, 0x27de), DEVICE_INTEL_ICH4 }, /* ICH7 */ 443 { PCI_VDEVICE(INTEL, 0x2698), DEVICE_INTEL_ICH4 }, /* ESB2 */ 444 { PCI_VDEVICE(INTEL, 0x7195), DEVICE_INTEL }, /* 440MX */ 445 { PCI_VDEVICE(SI, 0x7012), DEVICE_SIS }, /* SI7012 */ 446 { PCI_VDEVICE(NVIDIA, 0x01b1), DEVICE_NFORCE }, /* NFORCE */ 447 { PCI_VDEVICE(NVIDIA, 0x003a), DEVICE_NFORCE }, /* MCP04 */ 448 { PCI_VDEVICE(NVIDIA, 0x006a), DEVICE_NFORCE }, /* NFORCE2 */ 449 { PCI_VDEVICE(NVIDIA, 0x0059), DEVICE_NFORCE }, /* CK804 */ 450 { PCI_VDEVICE(NVIDIA, 0x008a), DEVICE_NFORCE }, /* CK8 */ 451 { PCI_VDEVICE(NVIDIA, 0x00da), DEVICE_NFORCE }, /* NFORCE3 */ 452 { PCI_VDEVICE(NVIDIA, 0x00ea), DEVICE_NFORCE }, /* CK8S */ 453 { PCI_VDEVICE(NVIDIA, 0x026b), DEVICE_NFORCE }, /* MCP51 */ 454 { PCI_VDEVICE(AMD, 0x746d), DEVICE_INTEL }, /* AMD8111 */ 455 { PCI_VDEVICE(AMD, 0x7445), DEVICE_INTEL }, /* AMD768 */ 456 { PCI_VDEVICE(AL, 0x5455), DEVICE_ALI }, /* Ali5455 */ 457 { 0, } 458 }; 459 460 MODULE_DEVICE_TABLE(pci, snd_intel8x0_ids); 461 462 /* 463 * Lowlevel I/O - busmaster 464 */ 465 466 static inline u8 igetbyte(struct intel8x0 *chip, u32 offset) 467 { 468 return ioread8(chip->bmaddr + offset); 469 } 470 471 static inline u16 igetword(struct intel8x0 *chip, u32 offset) 472 { 473 return ioread16(chip->bmaddr + offset); 474 } 475 476 static inline u32 igetdword(struct intel8x0 *chip, u32 offset) 477 { 478 return ioread32(chip->bmaddr + offset); 479 } 480 481 static inline void iputbyte(struct intel8x0 *chip, u32 offset, u8 val) 482 { 483 iowrite8(val, chip->bmaddr + offset); 484 } 485 486 static inline void iputword(struct intel8x0 *chip, u32 offset, u16 val) 487 { 488 iowrite16(val, chip->bmaddr + offset); 489 } 490 491 static inline void iputdword(struct intel8x0 *chip, u32 offset, u32 val) 492 { 493 iowrite32(val, chip->bmaddr + offset); 494 } 495 496 /* 497 * Lowlevel I/O - AC'97 registers 498 */ 499 500 static inline u16 iagetword(struct intel8x0 *chip, u32 offset) 501 { 502 return ioread16(chip->addr + offset); 503 } 504 505 static inline void iaputword(struct intel8x0 *chip, u32 offset, u16 val) 506 { 507 iowrite16(val, chip->addr + offset); 508 } 509 510 /* 511 * Basic I/O 512 */ 513 514 /* 515 * access to AC97 codec via normal i/o (for ICH and SIS7012) 516 */ 517 518 static int snd_intel8x0_codec_semaphore(struct intel8x0 *chip, unsigned int codec) 519 { 520 int time; 521 522 if (codec > 2) 523 return -EIO; 524 if (chip->in_sdin_init) { 525 /* we don't know the ready bit assignment at the moment */ 526 /* so we check any */ 527 codec = chip->codec_isr_bits; 528 } else { 529 codec = chip->codec_bit[chip->ac97_sdin[codec]]; 530 } 531 532 /* codec ready ? */ 533 if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0) 534 return -EIO; 535 536 if (chip->buggy_semaphore) 537 return 0; /* just ignore ... */ 538 539 /* Anyone holding a semaphore for 1 msec should be shot... */ 540 time = 100; 541 do { 542 if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS)) 543 return 0; 544 udelay(10); 545 } while (time--); 546 547 /* access to some forbidden (non existent) ac97 registers will not 548 * reset the semaphore. So even if you don't get the semaphore, still 549 * continue the access. We don't need the semaphore anyway. */ 550 snd_printk(KERN_ERR "codec_semaphore: semaphore is not ready [0x%x][0x%x]\n", 551 igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA))); 552 iagetword(chip, 0); /* clear semaphore flag */ 553 /* I don't care about the semaphore */ 554 return -EBUSY; 555 } 556 557 static void snd_intel8x0_codec_write(struct snd_ac97 *ac97, 558 unsigned short reg, 559 unsigned short val) 560 { 561 struct intel8x0 *chip = ac97->private_data; 562 563 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) { 564 if (! chip->in_ac97_init) 565 snd_printk(KERN_ERR "codec_write %d: semaphore is not ready for register 0x%x\n", ac97->num, reg); 566 } 567 iaputword(chip, reg + ac97->num * 0x80, val); 568 } 569 570 static unsigned short snd_intel8x0_codec_read(struct snd_ac97 *ac97, 571 unsigned short reg) 572 { 573 struct intel8x0 *chip = ac97->private_data; 574 unsigned short res; 575 unsigned int tmp; 576 577 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) { 578 if (! chip->in_ac97_init) 579 snd_printk(KERN_ERR "codec_read %d: semaphore is not ready for register 0x%x\n", ac97->num, reg); 580 res = 0xffff; 581 } else { 582 res = iagetword(chip, reg + ac97->num * 0x80); 583 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) { 584 /* reset RCS and preserve other R/WC bits */ 585 iputdword(chip, ICHREG(GLOB_STA), tmp & 586 ~(chip->codec_ready_bits | ICH_GSCI)); 587 if (! chip->in_ac97_init) 588 snd_printk(KERN_ERR "codec_read %d: read timeout for register 0x%x\n", ac97->num, reg); 589 res = 0xffff; 590 } 591 } 592 return res; 593 } 594 595 static void __devinit snd_intel8x0_codec_read_test(struct intel8x0 *chip, 596 unsigned int codec) 597 { 598 unsigned int tmp; 599 600 if (snd_intel8x0_codec_semaphore(chip, codec) >= 0) { 601 iagetword(chip, codec * 0x80); 602 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) { 603 /* reset RCS and preserve other R/WC bits */ 604 iputdword(chip, ICHREG(GLOB_STA), tmp & 605 ~(chip->codec_ready_bits | ICH_GSCI)); 606 } 607 } 608 } 609 610 /* 611 * access to AC97 for Ali5455 612 */ 613 static int snd_intel8x0_ali_codec_ready(struct intel8x0 *chip, int mask) 614 { 615 int count = 0; 616 for (count = 0; count < 0x7f; count++) { 617 int val = igetbyte(chip, ICHREG(ALI_CSPSR)); 618 if (val & mask) 619 return 0; 620 } 621 if (! chip->in_ac97_init) 622 snd_printd(KERN_WARNING "intel8x0: AC97 codec ready timeout.\n"); 623 return -EBUSY; 624 } 625 626 static int snd_intel8x0_ali_codec_semaphore(struct intel8x0 *chip) 627 { 628 int time = 100; 629 if (chip->buggy_semaphore) 630 return 0; /* just ignore ... */ 631 while (--time && (igetdword(chip, ICHREG(ALI_CAS)) & ALI_CAS_SEM_BUSY)) 632 udelay(1); 633 if (! time && ! chip->in_ac97_init) 634 snd_printk(KERN_WARNING "ali_codec_semaphore timeout\n"); 635 return snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_CODEC_READY); 636 } 637 638 static unsigned short snd_intel8x0_ali_codec_read(struct snd_ac97 *ac97, unsigned short reg) 639 { 640 struct intel8x0 *chip = ac97->private_data; 641 unsigned short data = 0xffff; 642 643 if (snd_intel8x0_ali_codec_semaphore(chip)) 644 goto __err; 645 reg |= ALI_CPR_ADDR_READ; 646 if (ac97->num) 647 reg |= ALI_CPR_ADDR_SECONDARY; 648 iputword(chip, ICHREG(ALI_CPR_ADDR), reg); 649 if (snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_READ_OK)) 650 goto __err; 651 data = igetword(chip, ICHREG(ALI_SPR)); 652 __err: 653 return data; 654 } 655 656 static void snd_intel8x0_ali_codec_write(struct snd_ac97 *ac97, unsigned short reg, 657 unsigned short val) 658 { 659 struct intel8x0 *chip = ac97->private_data; 660 661 if (snd_intel8x0_ali_codec_semaphore(chip)) 662 return; 663 iputword(chip, ICHREG(ALI_CPR), val); 664 if (ac97->num) 665 reg |= ALI_CPR_ADDR_SECONDARY; 666 iputword(chip, ICHREG(ALI_CPR_ADDR), reg); 667 snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_WRITE_OK); 668 } 669 670 671 /* 672 * DMA I/O 673 */ 674 static void snd_intel8x0_setup_periods(struct intel8x0 *chip, struct ichdev *ichdev) 675 { 676 int idx; 677 u32 *bdbar = ichdev->bdbar; 678 unsigned long port = ichdev->reg_offset; 679 680 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr); 681 if (ichdev->size == ichdev->fragsize) { 682 ichdev->ack_reload = ichdev->ack = 2; 683 ichdev->fragsize1 = ichdev->fragsize >> 1; 684 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) { 685 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf); 686 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */ 687 ichdev->fragsize1 >> ichdev->pos_shift); 688 bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1)); 689 bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */ 690 ichdev->fragsize1 >> ichdev->pos_shift); 691 } 692 ichdev->frags = 2; 693 } else { 694 ichdev->ack_reload = ichdev->ack = 1; 695 ichdev->fragsize1 = ichdev->fragsize; 696 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) { 697 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf + 698 (((idx >> 1) * ichdev->fragsize) % 699 ichdev->size)); 700 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */ 701 ichdev->fragsize >> ichdev->pos_shift); 702 #if 0 703 printk(KERN_DEBUG "bdbar[%i] = 0x%x [0x%x]\n", 704 idx + 0, bdbar[idx + 0], bdbar[idx + 1]); 705 #endif 706 } 707 ichdev->frags = ichdev->size / ichdev->fragsize; 708 } 709 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK); 710 ichdev->civ = 0; 711 iputbyte(chip, port + ICH_REG_OFF_CIV, 0); 712 ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags; 713 ichdev->position = 0; 714 #if 0 715 printk(KERN_DEBUG "lvi_frag = %i, frags = %i, period_size = 0x%x, " 716 "period_size1 = 0x%x\n", 717 ichdev->lvi_frag, ichdev->frags, ichdev->fragsize, 718 ichdev->fragsize1); 719 #endif 720 /* clear interrupts */ 721 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI); 722 } 723 724 #ifdef __i386__ 725 /* 726 * Intel 82443MX running a 100MHz processor system bus has a hardware bug, 727 * which aborts PCI busmaster for audio transfer. A workaround is to set 728 * the pages as non-cached. For details, see the errata in 729 * http://download.intel.com/design/chipsets/specupdt/24505108.pdf 730 */ 731 static void fill_nocache(void *buf, int size, int nocache) 732 { 733 size = (size + PAGE_SIZE - 1) >> PAGE_SHIFT; 734 if (nocache) 735 set_pages_uc(virt_to_page(buf), size); 736 else 737 set_pages_wb(virt_to_page(buf), size); 738 } 739 #else 740 #define fill_nocache(buf, size, nocache) do { ; } while (0) 741 #endif 742 743 /* 744 * Interrupt handler 745 */ 746 747 static inline void snd_intel8x0_update(struct intel8x0 *chip, struct ichdev *ichdev) 748 { 749 unsigned long port = ichdev->reg_offset; 750 unsigned long flags; 751 int status, civ, i, step; 752 int ack = 0; 753 754 spin_lock_irqsave(&chip->reg_lock, flags); 755 status = igetbyte(chip, port + ichdev->roff_sr); 756 civ = igetbyte(chip, port + ICH_REG_OFF_CIV); 757 if (!(status & ICH_BCIS)) { 758 step = 0; 759 } else if (civ == ichdev->civ) { 760 // snd_printd("civ same %d\n", civ); 761 step = 1; 762 ichdev->civ++; 763 ichdev->civ &= ICH_REG_LVI_MASK; 764 } else { 765 step = civ - ichdev->civ; 766 if (step < 0) 767 step += ICH_REG_LVI_MASK + 1; 768 // if (step != 1) 769 // snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ); 770 ichdev->civ = civ; 771 } 772 773 ichdev->position += step * ichdev->fragsize1; 774 if (! chip->in_measurement) 775 ichdev->position %= ichdev->size; 776 ichdev->lvi += step; 777 ichdev->lvi &= ICH_REG_LVI_MASK; 778 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi); 779 for (i = 0; i < step; i++) { 780 ichdev->lvi_frag++; 781 ichdev->lvi_frag %= ichdev->frags; 782 ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + ichdev->lvi_frag * ichdev->fragsize1); 783 #if 0 784 printk(KERN_DEBUG "new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, " 785 "all = 0x%x, 0x%x\n", 786 ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2], 787 ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port), 788 inl(port + 4), inb(port + ICH_REG_OFF_CR)); 789 #endif 790 if (--ichdev->ack == 0) { 791 ichdev->ack = ichdev->ack_reload; 792 ack = 1; 793 } 794 } 795 spin_unlock_irqrestore(&chip->reg_lock, flags); 796 if (ack && ichdev->substream) { 797 snd_pcm_period_elapsed(ichdev->substream); 798 } 799 iputbyte(chip, port + ichdev->roff_sr, 800 status & (ICH_FIFOE | ICH_BCIS | ICH_LVBCI)); 801 } 802 803 static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id) 804 { 805 struct intel8x0 *chip = dev_id; 806 struct ichdev *ichdev; 807 unsigned int status; 808 unsigned int i; 809 810 status = igetdword(chip, chip->int_sta_reg); 811 if (status == 0xffffffff) /* we are not yet resumed */ 812 return IRQ_NONE; 813 814 if ((status & chip->int_sta_mask) == 0) { 815 if (status) { 816 /* ack */ 817 iputdword(chip, chip->int_sta_reg, status); 818 if (! chip->buggy_irq) 819 status = 0; 820 } 821 return IRQ_RETVAL(status); 822 } 823 824 for (i = 0; i < chip->bdbars_count; i++) { 825 ichdev = &chip->ichd[i]; 826 if (status & ichdev->int_sta_mask) 827 snd_intel8x0_update(chip, ichdev); 828 } 829 830 /* ack them */ 831 iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask); 832 833 return IRQ_HANDLED; 834 } 835 836 /* 837 * PCM part 838 */ 839 840 static int snd_intel8x0_pcm_trigger(struct snd_pcm_substream *substream, int cmd) 841 { 842 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 843 struct ichdev *ichdev = get_ichdev(substream); 844 unsigned char val = 0; 845 unsigned long port = ichdev->reg_offset; 846 847 switch (cmd) { 848 case SNDRV_PCM_TRIGGER_RESUME: 849 ichdev->suspended = 0; 850 /* fallthru */ 851 case SNDRV_PCM_TRIGGER_START: 852 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 853 val = ICH_IOCE | ICH_STARTBM; 854 ichdev->last_pos = ichdev->position; 855 break; 856 case SNDRV_PCM_TRIGGER_SUSPEND: 857 ichdev->suspended = 1; 858 /* fallthru */ 859 case SNDRV_PCM_TRIGGER_STOP: 860 val = 0; 861 break; 862 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 863 val = ICH_IOCE; 864 break; 865 default: 866 return -EINVAL; 867 } 868 iputbyte(chip, port + ICH_REG_OFF_CR, val); 869 if (cmd == SNDRV_PCM_TRIGGER_STOP) { 870 /* wait until DMA stopped */ 871 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ; 872 /* reset whole DMA things */ 873 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS); 874 } 875 return 0; 876 } 877 878 static int snd_intel8x0_ali_trigger(struct snd_pcm_substream *substream, int cmd) 879 { 880 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 881 struct ichdev *ichdev = get_ichdev(substream); 882 unsigned long port = ichdev->reg_offset; 883 static int fiforeg[] = { 884 ICHREG(ALI_FIFOCR1), ICHREG(ALI_FIFOCR2), ICHREG(ALI_FIFOCR3) 885 }; 886 unsigned int val, fifo; 887 888 val = igetdword(chip, ICHREG(ALI_DMACR)); 889 switch (cmd) { 890 case SNDRV_PCM_TRIGGER_RESUME: 891 ichdev->suspended = 0; 892 /* fallthru */ 893 case SNDRV_PCM_TRIGGER_START: 894 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 895 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 896 /* clear FIFO for synchronization of channels */ 897 fifo = igetdword(chip, fiforeg[ichdev->ali_slot / 4]); 898 fifo &= ~(0xff << (ichdev->ali_slot % 4)); 899 fifo |= 0x83 << (ichdev->ali_slot % 4); 900 iputdword(chip, fiforeg[ichdev->ali_slot / 4], fifo); 901 } 902 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE); 903 val &= ~(1 << (ichdev->ali_slot + 16)); /* clear PAUSE flag */ 904 /* start DMA */ 905 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << ichdev->ali_slot)); 906 break; 907 case SNDRV_PCM_TRIGGER_SUSPEND: 908 ichdev->suspended = 1; 909 /* fallthru */ 910 case SNDRV_PCM_TRIGGER_STOP: 911 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 912 /* pause */ 913 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << (ichdev->ali_slot + 16))); 914 iputbyte(chip, port + ICH_REG_OFF_CR, 0); 915 while (igetbyte(chip, port + ICH_REG_OFF_CR)) 916 ; 917 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH) 918 break; 919 /* reset whole DMA things */ 920 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS); 921 /* clear interrupts */ 922 iputbyte(chip, port + ICH_REG_OFF_SR, 923 igetbyte(chip, port + ICH_REG_OFF_SR) | 0x1e); 924 iputdword(chip, ICHREG(ALI_INTERRUPTSR), 925 igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ichdev->int_sta_mask); 926 break; 927 default: 928 return -EINVAL; 929 } 930 return 0; 931 } 932 933 static int snd_intel8x0_hw_params(struct snd_pcm_substream *substream, 934 struct snd_pcm_hw_params *hw_params) 935 { 936 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 937 struct ichdev *ichdev = get_ichdev(substream); 938 struct snd_pcm_runtime *runtime = substream->runtime; 939 int dbl = params_rate(hw_params) > 48000; 940 int err; 941 942 if (chip->fix_nocache && ichdev->page_attr_changed) { 943 fill_nocache(runtime->dma_area, runtime->dma_bytes, 0); /* clear */ 944 ichdev->page_attr_changed = 0; 945 } 946 err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params)); 947 if (err < 0) 948 return err; 949 if (chip->fix_nocache) { 950 if (runtime->dma_area && ! ichdev->page_attr_changed) { 951 fill_nocache(runtime->dma_area, runtime->dma_bytes, 1); 952 ichdev->page_attr_changed = 1; 953 } 954 } 955 if (ichdev->pcm_open_flag) { 956 snd_ac97_pcm_close(ichdev->pcm); 957 ichdev->pcm_open_flag = 0; 958 } 959 err = snd_ac97_pcm_open(ichdev->pcm, params_rate(hw_params), 960 params_channels(hw_params), 961 ichdev->pcm->r[dbl].slots); 962 if (err >= 0) { 963 ichdev->pcm_open_flag = 1; 964 /* Force SPDIF setting */ 965 if (ichdev->ichd == ICHD_PCMOUT && chip->spdif_idx < 0) 966 snd_ac97_set_rate(ichdev->pcm->r[0].codec[0], AC97_SPDIF, 967 params_rate(hw_params)); 968 } 969 return err; 970 } 971 972 static int snd_intel8x0_hw_free(struct snd_pcm_substream *substream) 973 { 974 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 975 struct ichdev *ichdev = get_ichdev(substream); 976 977 if (ichdev->pcm_open_flag) { 978 snd_ac97_pcm_close(ichdev->pcm); 979 ichdev->pcm_open_flag = 0; 980 } 981 if (chip->fix_nocache && ichdev->page_attr_changed) { 982 fill_nocache(substream->runtime->dma_area, substream->runtime->dma_bytes, 0); 983 ichdev->page_attr_changed = 0; 984 } 985 return snd_pcm_lib_free_pages(substream); 986 } 987 988 static void snd_intel8x0_setup_pcm_out(struct intel8x0 *chip, 989 struct snd_pcm_runtime *runtime) 990 { 991 unsigned int cnt; 992 int dbl = runtime->rate > 48000; 993 994 spin_lock_irq(&chip->reg_lock); 995 switch (chip->device_type) { 996 case DEVICE_ALI: 997 cnt = igetdword(chip, ICHREG(ALI_SCR)); 998 cnt &= ~ICH_ALI_SC_PCM_246_MASK; 999 if (runtime->channels == 4 || dbl) 1000 cnt |= ICH_ALI_SC_PCM_4; 1001 else if (runtime->channels == 6) 1002 cnt |= ICH_ALI_SC_PCM_6; 1003 iputdword(chip, ICHREG(ALI_SCR), cnt); 1004 break; 1005 case DEVICE_SIS: 1006 cnt = igetdword(chip, ICHREG(GLOB_CNT)); 1007 cnt &= ~ICH_SIS_PCM_246_MASK; 1008 if (runtime->channels == 4 || dbl) 1009 cnt |= ICH_SIS_PCM_4; 1010 else if (runtime->channels == 6) 1011 cnt |= ICH_SIS_PCM_6; 1012 iputdword(chip, ICHREG(GLOB_CNT), cnt); 1013 break; 1014 default: 1015 cnt = igetdword(chip, ICHREG(GLOB_CNT)); 1016 cnt &= ~(ICH_PCM_246_MASK | ICH_PCM_20BIT); 1017 if (runtime->channels == 4 || dbl) 1018 cnt |= ICH_PCM_4; 1019 else if (runtime->channels == 6) 1020 cnt |= ICH_PCM_6; 1021 else if (runtime->channels == 8) 1022 cnt |= ICH_PCM_8; 1023 if (chip->device_type == DEVICE_NFORCE) { 1024 /* reset to 2ch once to keep the 6 channel data in alignment, 1025 * to start from Front Left always 1026 */ 1027 if (cnt & ICH_PCM_246_MASK) { 1028 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_PCM_246_MASK); 1029 spin_unlock_irq(&chip->reg_lock); 1030 msleep(50); /* grrr... */ 1031 spin_lock_irq(&chip->reg_lock); 1032 } 1033 } else if (chip->device_type == DEVICE_INTEL_ICH4) { 1034 if (runtime->sample_bits > 16) 1035 cnt |= ICH_PCM_20BIT; 1036 } 1037 iputdword(chip, ICHREG(GLOB_CNT), cnt); 1038 break; 1039 } 1040 spin_unlock_irq(&chip->reg_lock); 1041 } 1042 1043 static int snd_intel8x0_pcm_prepare(struct snd_pcm_substream *substream) 1044 { 1045 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1046 struct snd_pcm_runtime *runtime = substream->runtime; 1047 struct ichdev *ichdev = get_ichdev(substream); 1048 1049 ichdev->physbuf = runtime->dma_addr; 1050 ichdev->size = snd_pcm_lib_buffer_bytes(substream); 1051 ichdev->fragsize = snd_pcm_lib_period_bytes(substream); 1052 if (ichdev->ichd == ICHD_PCMOUT) { 1053 snd_intel8x0_setup_pcm_out(chip, runtime); 1054 if (chip->device_type == DEVICE_INTEL_ICH4) 1055 ichdev->pos_shift = (runtime->sample_bits > 16) ? 2 : 1; 1056 } 1057 snd_intel8x0_setup_periods(chip, ichdev); 1058 return 0; 1059 } 1060 1061 static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(struct snd_pcm_substream *substream) 1062 { 1063 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1064 struct ichdev *ichdev = get_ichdev(substream); 1065 size_t ptr1, ptr; 1066 int civ, timeout = 10; 1067 unsigned int position; 1068 1069 spin_lock(&chip->reg_lock); 1070 do { 1071 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV); 1072 ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb); 1073 position = ichdev->position; 1074 if (ptr1 == 0) { 1075 udelay(10); 1076 continue; 1077 } 1078 if (civ != igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV)) 1079 continue; 1080 1081 /* IO read operation is very expensive inside virtual machine 1082 * as it is emulated. The probability that subsequent PICB read 1083 * will return different result is high enough to loop till 1084 * timeout here. 1085 * Same CIV is strict enough condition to be sure that PICB 1086 * is valid inside VM on emulated card. */ 1087 if (chip->inside_vm) 1088 break; 1089 if (ptr1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb)) 1090 break; 1091 } while (timeout--); 1092 ptr = ichdev->last_pos; 1093 if (ptr1 != 0) { 1094 ptr1 <<= ichdev->pos_shift; 1095 ptr = ichdev->fragsize1 - ptr1; 1096 ptr += position; 1097 if (ptr < ichdev->last_pos) { 1098 unsigned int pos_base, last_base; 1099 pos_base = position / ichdev->fragsize1; 1100 last_base = ichdev->last_pos / ichdev->fragsize1; 1101 /* another sanity check; ptr1 can go back to full 1102 * before the base position is updated 1103 */ 1104 if (pos_base == last_base) 1105 ptr = ichdev->last_pos; 1106 } 1107 } 1108 ichdev->last_pos = ptr; 1109 spin_unlock(&chip->reg_lock); 1110 if (ptr >= ichdev->size) 1111 return 0; 1112 return bytes_to_frames(substream->runtime, ptr); 1113 } 1114 1115 static struct snd_pcm_hardware snd_intel8x0_stream = 1116 { 1117 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 1118 SNDRV_PCM_INFO_BLOCK_TRANSFER | 1119 SNDRV_PCM_INFO_MMAP_VALID | 1120 SNDRV_PCM_INFO_PAUSE | 1121 SNDRV_PCM_INFO_RESUME), 1122 .formats = SNDRV_PCM_FMTBIT_S16_LE, 1123 .rates = SNDRV_PCM_RATE_48000, 1124 .rate_min = 48000, 1125 .rate_max = 48000, 1126 .channels_min = 2, 1127 .channels_max = 2, 1128 .buffer_bytes_max = 128 * 1024, 1129 .period_bytes_min = 32, 1130 .period_bytes_max = 128 * 1024, 1131 .periods_min = 1, 1132 .periods_max = 1024, 1133 .fifo_size = 0, 1134 }; 1135 1136 static unsigned int channels4[] = { 1137 2, 4, 1138 }; 1139 1140 static struct snd_pcm_hw_constraint_list hw_constraints_channels4 = { 1141 .count = ARRAY_SIZE(channels4), 1142 .list = channels4, 1143 .mask = 0, 1144 }; 1145 1146 static unsigned int channels6[] = { 1147 2, 4, 6, 1148 }; 1149 1150 static struct snd_pcm_hw_constraint_list hw_constraints_channels6 = { 1151 .count = ARRAY_SIZE(channels6), 1152 .list = channels6, 1153 .mask = 0, 1154 }; 1155 1156 static unsigned int channels8[] = { 1157 2, 4, 6, 8, 1158 }; 1159 1160 static struct snd_pcm_hw_constraint_list hw_constraints_channels8 = { 1161 .count = ARRAY_SIZE(channels8), 1162 .list = channels8, 1163 .mask = 0, 1164 }; 1165 1166 static int snd_intel8x0_pcm_open(struct snd_pcm_substream *substream, struct ichdev *ichdev) 1167 { 1168 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1169 struct snd_pcm_runtime *runtime = substream->runtime; 1170 int err; 1171 1172 ichdev->substream = substream; 1173 runtime->hw = snd_intel8x0_stream; 1174 runtime->hw.rates = ichdev->pcm->rates; 1175 snd_pcm_limit_hw_rates(runtime); 1176 if (chip->device_type == DEVICE_SIS) { 1177 runtime->hw.buffer_bytes_max = 64*1024; 1178 runtime->hw.period_bytes_max = 64*1024; 1179 } 1180 if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0) 1181 return err; 1182 runtime->private_data = ichdev; 1183 return 0; 1184 } 1185 1186 static int snd_intel8x0_playback_open(struct snd_pcm_substream *substream) 1187 { 1188 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1189 struct snd_pcm_runtime *runtime = substream->runtime; 1190 int err; 1191 1192 err = snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMOUT]); 1193 if (err < 0) 1194 return err; 1195 1196 if (chip->multi8) { 1197 runtime->hw.channels_max = 8; 1198 snd_pcm_hw_constraint_list(runtime, 0, 1199 SNDRV_PCM_HW_PARAM_CHANNELS, 1200 &hw_constraints_channels8); 1201 } else if (chip->multi6) { 1202 runtime->hw.channels_max = 6; 1203 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 1204 &hw_constraints_channels6); 1205 } else if (chip->multi4) { 1206 runtime->hw.channels_max = 4; 1207 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 1208 &hw_constraints_channels4); 1209 } 1210 if (chip->dra) { 1211 snd_ac97_pcm_double_rate_rules(runtime); 1212 } 1213 if (chip->smp20bit) { 1214 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE; 1215 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20); 1216 } 1217 return 0; 1218 } 1219 1220 static int snd_intel8x0_playback_close(struct snd_pcm_substream *substream) 1221 { 1222 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1223 1224 chip->ichd[ICHD_PCMOUT].substream = NULL; 1225 return 0; 1226 } 1227 1228 static int snd_intel8x0_capture_open(struct snd_pcm_substream *substream) 1229 { 1230 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1231 1232 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMIN]); 1233 } 1234 1235 static int snd_intel8x0_capture_close(struct snd_pcm_substream *substream) 1236 { 1237 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1238 1239 chip->ichd[ICHD_PCMIN].substream = NULL; 1240 return 0; 1241 } 1242 1243 static int snd_intel8x0_mic_open(struct snd_pcm_substream *substream) 1244 { 1245 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1246 1247 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC]); 1248 } 1249 1250 static int snd_intel8x0_mic_close(struct snd_pcm_substream *substream) 1251 { 1252 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1253 1254 chip->ichd[ICHD_MIC].substream = NULL; 1255 return 0; 1256 } 1257 1258 static int snd_intel8x0_mic2_open(struct snd_pcm_substream *substream) 1259 { 1260 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1261 1262 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC2]); 1263 } 1264 1265 static int snd_intel8x0_mic2_close(struct snd_pcm_substream *substream) 1266 { 1267 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1268 1269 chip->ichd[ICHD_MIC2].substream = NULL; 1270 return 0; 1271 } 1272 1273 static int snd_intel8x0_capture2_open(struct snd_pcm_substream *substream) 1274 { 1275 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1276 1277 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCM2IN]); 1278 } 1279 1280 static int snd_intel8x0_capture2_close(struct snd_pcm_substream *substream) 1281 { 1282 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1283 1284 chip->ichd[ICHD_PCM2IN].substream = NULL; 1285 return 0; 1286 } 1287 1288 static int snd_intel8x0_spdif_open(struct snd_pcm_substream *substream) 1289 { 1290 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1291 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR; 1292 1293 return snd_intel8x0_pcm_open(substream, &chip->ichd[idx]); 1294 } 1295 1296 static int snd_intel8x0_spdif_close(struct snd_pcm_substream *substream) 1297 { 1298 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1299 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR; 1300 1301 chip->ichd[idx].substream = NULL; 1302 return 0; 1303 } 1304 1305 static int snd_intel8x0_ali_ac97spdifout_open(struct snd_pcm_substream *substream) 1306 { 1307 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1308 unsigned int val; 1309 1310 spin_lock_irq(&chip->reg_lock); 1311 val = igetdword(chip, ICHREG(ALI_INTERFACECR)); 1312 val |= ICH_ALI_IF_AC97SP; 1313 iputdword(chip, ICHREG(ALI_INTERFACECR), val); 1314 /* also needs to set ALI_SC_CODEC_SPDF correctly */ 1315 spin_unlock_irq(&chip->reg_lock); 1316 1317 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_AC97SPDIFOUT]); 1318 } 1319 1320 static int snd_intel8x0_ali_ac97spdifout_close(struct snd_pcm_substream *substream) 1321 { 1322 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1323 unsigned int val; 1324 1325 chip->ichd[ALID_AC97SPDIFOUT].substream = NULL; 1326 spin_lock_irq(&chip->reg_lock); 1327 val = igetdword(chip, ICHREG(ALI_INTERFACECR)); 1328 val &= ~ICH_ALI_IF_AC97SP; 1329 iputdword(chip, ICHREG(ALI_INTERFACECR), val); 1330 spin_unlock_irq(&chip->reg_lock); 1331 1332 return 0; 1333 } 1334 1335 #if 0 // NYI 1336 static int snd_intel8x0_ali_spdifin_open(struct snd_pcm_substream *substream) 1337 { 1338 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1339 1340 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFIN]); 1341 } 1342 1343 static int snd_intel8x0_ali_spdifin_close(struct snd_pcm_substream *substream) 1344 { 1345 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1346 1347 chip->ichd[ALID_SPDIFIN].substream = NULL; 1348 return 0; 1349 } 1350 1351 static int snd_intel8x0_ali_spdifout_open(struct snd_pcm_substream *substream) 1352 { 1353 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1354 1355 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFOUT]); 1356 } 1357 1358 static int snd_intel8x0_ali_spdifout_close(struct snd_pcm_substream *substream) 1359 { 1360 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1361 1362 chip->ichd[ALID_SPDIFOUT].substream = NULL; 1363 return 0; 1364 } 1365 #endif 1366 1367 static struct snd_pcm_ops snd_intel8x0_playback_ops = { 1368 .open = snd_intel8x0_playback_open, 1369 .close = snd_intel8x0_playback_close, 1370 .ioctl = snd_pcm_lib_ioctl, 1371 .hw_params = snd_intel8x0_hw_params, 1372 .hw_free = snd_intel8x0_hw_free, 1373 .prepare = snd_intel8x0_pcm_prepare, 1374 .trigger = snd_intel8x0_pcm_trigger, 1375 .pointer = snd_intel8x0_pcm_pointer, 1376 }; 1377 1378 static struct snd_pcm_ops snd_intel8x0_capture_ops = { 1379 .open = snd_intel8x0_capture_open, 1380 .close = snd_intel8x0_capture_close, 1381 .ioctl = snd_pcm_lib_ioctl, 1382 .hw_params = snd_intel8x0_hw_params, 1383 .hw_free = snd_intel8x0_hw_free, 1384 .prepare = snd_intel8x0_pcm_prepare, 1385 .trigger = snd_intel8x0_pcm_trigger, 1386 .pointer = snd_intel8x0_pcm_pointer, 1387 }; 1388 1389 static struct snd_pcm_ops snd_intel8x0_capture_mic_ops = { 1390 .open = snd_intel8x0_mic_open, 1391 .close = snd_intel8x0_mic_close, 1392 .ioctl = snd_pcm_lib_ioctl, 1393 .hw_params = snd_intel8x0_hw_params, 1394 .hw_free = snd_intel8x0_hw_free, 1395 .prepare = snd_intel8x0_pcm_prepare, 1396 .trigger = snd_intel8x0_pcm_trigger, 1397 .pointer = snd_intel8x0_pcm_pointer, 1398 }; 1399 1400 static struct snd_pcm_ops snd_intel8x0_capture_mic2_ops = { 1401 .open = snd_intel8x0_mic2_open, 1402 .close = snd_intel8x0_mic2_close, 1403 .ioctl = snd_pcm_lib_ioctl, 1404 .hw_params = snd_intel8x0_hw_params, 1405 .hw_free = snd_intel8x0_hw_free, 1406 .prepare = snd_intel8x0_pcm_prepare, 1407 .trigger = snd_intel8x0_pcm_trigger, 1408 .pointer = snd_intel8x0_pcm_pointer, 1409 }; 1410 1411 static struct snd_pcm_ops snd_intel8x0_capture2_ops = { 1412 .open = snd_intel8x0_capture2_open, 1413 .close = snd_intel8x0_capture2_close, 1414 .ioctl = snd_pcm_lib_ioctl, 1415 .hw_params = snd_intel8x0_hw_params, 1416 .hw_free = snd_intel8x0_hw_free, 1417 .prepare = snd_intel8x0_pcm_prepare, 1418 .trigger = snd_intel8x0_pcm_trigger, 1419 .pointer = snd_intel8x0_pcm_pointer, 1420 }; 1421 1422 static struct snd_pcm_ops snd_intel8x0_spdif_ops = { 1423 .open = snd_intel8x0_spdif_open, 1424 .close = snd_intel8x0_spdif_close, 1425 .ioctl = snd_pcm_lib_ioctl, 1426 .hw_params = snd_intel8x0_hw_params, 1427 .hw_free = snd_intel8x0_hw_free, 1428 .prepare = snd_intel8x0_pcm_prepare, 1429 .trigger = snd_intel8x0_pcm_trigger, 1430 .pointer = snd_intel8x0_pcm_pointer, 1431 }; 1432 1433 static struct snd_pcm_ops snd_intel8x0_ali_playback_ops = { 1434 .open = snd_intel8x0_playback_open, 1435 .close = snd_intel8x0_playback_close, 1436 .ioctl = snd_pcm_lib_ioctl, 1437 .hw_params = snd_intel8x0_hw_params, 1438 .hw_free = snd_intel8x0_hw_free, 1439 .prepare = snd_intel8x0_pcm_prepare, 1440 .trigger = snd_intel8x0_ali_trigger, 1441 .pointer = snd_intel8x0_pcm_pointer, 1442 }; 1443 1444 static struct snd_pcm_ops snd_intel8x0_ali_capture_ops = { 1445 .open = snd_intel8x0_capture_open, 1446 .close = snd_intel8x0_capture_close, 1447 .ioctl = snd_pcm_lib_ioctl, 1448 .hw_params = snd_intel8x0_hw_params, 1449 .hw_free = snd_intel8x0_hw_free, 1450 .prepare = snd_intel8x0_pcm_prepare, 1451 .trigger = snd_intel8x0_ali_trigger, 1452 .pointer = snd_intel8x0_pcm_pointer, 1453 }; 1454 1455 static struct snd_pcm_ops snd_intel8x0_ali_capture_mic_ops = { 1456 .open = snd_intel8x0_mic_open, 1457 .close = snd_intel8x0_mic_close, 1458 .ioctl = snd_pcm_lib_ioctl, 1459 .hw_params = snd_intel8x0_hw_params, 1460 .hw_free = snd_intel8x0_hw_free, 1461 .prepare = snd_intel8x0_pcm_prepare, 1462 .trigger = snd_intel8x0_ali_trigger, 1463 .pointer = snd_intel8x0_pcm_pointer, 1464 }; 1465 1466 static struct snd_pcm_ops snd_intel8x0_ali_ac97spdifout_ops = { 1467 .open = snd_intel8x0_ali_ac97spdifout_open, 1468 .close = snd_intel8x0_ali_ac97spdifout_close, 1469 .ioctl = snd_pcm_lib_ioctl, 1470 .hw_params = snd_intel8x0_hw_params, 1471 .hw_free = snd_intel8x0_hw_free, 1472 .prepare = snd_intel8x0_pcm_prepare, 1473 .trigger = snd_intel8x0_ali_trigger, 1474 .pointer = snd_intel8x0_pcm_pointer, 1475 }; 1476 1477 #if 0 // NYI 1478 static struct snd_pcm_ops snd_intel8x0_ali_spdifin_ops = { 1479 .open = snd_intel8x0_ali_spdifin_open, 1480 .close = snd_intel8x0_ali_spdifin_close, 1481 .ioctl = snd_pcm_lib_ioctl, 1482 .hw_params = snd_intel8x0_hw_params, 1483 .hw_free = snd_intel8x0_hw_free, 1484 .prepare = snd_intel8x0_pcm_prepare, 1485 .trigger = snd_intel8x0_pcm_trigger, 1486 .pointer = snd_intel8x0_pcm_pointer, 1487 }; 1488 1489 static struct snd_pcm_ops snd_intel8x0_ali_spdifout_ops = { 1490 .open = snd_intel8x0_ali_spdifout_open, 1491 .close = snd_intel8x0_ali_spdifout_close, 1492 .ioctl = snd_pcm_lib_ioctl, 1493 .hw_params = snd_intel8x0_hw_params, 1494 .hw_free = snd_intel8x0_hw_free, 1495 .prepare = snd_intel8x0_pcm_prepare, 1496 .trigger = snd_intel8x0_pcm_trigger, 1497 .pointer = snd_intel8x0_pcm_pointer, 1498 }; 1499 #endif // NYI 1500 1501 struct ich_pcm_table { 1502 char *suffix; 1503 struct snd_pcm_ops *playback_ops; 1504 struct snd_pcm_ops *capture_ops; 1505 size_t prealloc_size; 1506 size_t prealloc_max_size; 1507 int ac97_idx; 1508 }; 1509 1510 static int __devinit snd_intel8x0_pcm1(struct intel8x0 *chip, int device, 1511 struct ich_pcm_table *rec) 1512 { 1513 struct snd_pcm *pcm; 1514 int err; 1515 char name[32]; 1516 1517 if (rec->suffix) 1518 sprintf(name, "Intel ICH - %s", rec->suffix); 1519 else 1520 strcpy(name, "Intel ICH"); 1521 err = snd_pcm_new(chip->card, name, device, 1522 rec->playback_ops ? 1 : 0, 1523 rec->capture_ops ? 1 : 0, &pcm); 1524 if (err < 0) 1525 return err; 1526 1527 if (rec->playback_ops) 1528 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops); 1529 if (rec->capture_ops) 1530 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops); 1531 1532 pcm->private_data = chip; 1533 pcm->info_flags = 0; 1534 if (rec->suffix) 1535 sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix); 1536 else 1537 strcpy(pcm->name, chip->card->shortname); 1538 chip->pcm[device] = pcm; 1539 1540 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 1541 snd_dma_pci_data(chip->pci), 1542 rec->prealloc_size, rec->prealloc_max_size); 1543 1544 return 0; 1545 } 1546 1547 static struct ich_pcm_table intel_pcms[] __devinitdata = { 1548 { 1549 .playback_ops = &snd_intel8x0_playback_ops, 1550 .capture_ops = &snd_intel8x0_capture_ops, 1551 .prealloc_size = 64 * 1024, 1552 .prealloc_max_size = 128 * 1024, 1553 }, 1554 { 1555 .suffix = "MIC ADC", 1556 .capture_ops = &snd_intel8x0_capture_mic_ops, 1557 .prealloc_size = 0, 1558 .prealloc_max_size = 128 * 1024, 1559 .ac97_idx = ICHD_MIC, 1560 }, 1561 { 1562 .suffix = "MIC2 ADC", 1563 .capture_ops = &snd_intel8x0_capture_mic2_ops, 1564 .prealloc_size = 0, 1565 .prealloc_max_size = 128 * 1024, 1566 .ac97_idx = ICHD_MIC2, 1567 }, 1568 { 1569 .suffix = "ADC2", 1570 .capture_ops = &snd_intel8x0_capture2_ops, 1571 .prealloc_size = 0, 1572 .prealloc_max_size = 128 * 1024, 1573 .ac97_idx = ICHD_PCM2IN, 1574 }, 1575 { 1576 .suffix = "IEC958", 1577 .playback_ops = &snd_intel8x0_spdif_ops, 1578 .prealloc_size = 64 * 1024, 1579 .prealloc_max_size = 128 * 1024, 1580 .ac97_idx = ICHD_SPBAR, 1581 }, 1582 }; 1583 1584 static struct ich_pcm_table nforce_pcms[] __devinitdata = { 1585 { 1586 .playback_ops = &snd_intel8x0_playback_ops, 1587 .capture_ops = &snd_intel8x0_capture_ops, 1588 .prealloc_size = 64 * 1024, 1589 .prealloc_max_size = 128 * 1024, 1590 }, 1591 { 1592 .suffix = "MIC ADC", 1593 .capture_ops = &snd_intel8x0_capture_mic_ops, 1594 .prealloc_size = 0, 1595 .prealloc_max_size = 128 * 1024, 1596 .ac97_idx = NVD_MIC, 1597 }, 1598 { 1599 .suffix = "IEC958", 1600 .playback_ops = &snd_intel8x0_spdif_ops, 1601 .prealloc_size = 64 * 1024, 1602 .prealloc_max_size = 128 * 1024, 1603 .ac97_idx = NVD_SPBAR, 1604 }, 1605 }; 1606 1607 static struct ich_pcm_table ali_pcms[] __devinitdata = { 1608 { 1609 .playback_ops = &snd_intel8x0_ali_playback_ops, 1610 .capture_ops = &snd_intel8x0_ali_capture_ops, 1611 .prealloc_size = 64 * 1024, 1612 .prealloc_max_size = 128 * 1024, 1613 }, 1614 { 1615 .suffix = "MIC ADC", 1616 .capture_ops = &snd_intel8x0_ali_capture_mic_ops, 1617 .prealloc_size = 0, 1618 .prealloc_max_size = 128 * 1024, 1619 .ac97_idx = ALID_MIC, 1620 }, 1621 { 1622 .suffix = "IEC958", 1623 .playback_ops = &snd_intel8x0_ali_ac97spdifout_ops, 1624 /* .capture_ops = &snd_intel8x0_ali_spdifin_ops, */ 1625 .prealloc_size = 64 * 1024, 1626 .prealloc_max_size = 128 * 1024, 1627 .ac97_idx = ALID_AC97SPDIFOUT, 1628 }, 1629 #if 0 // NYI 1630 { 1631 .suffix = "HW IEC958", 1632 .playback_ops = &snd_intel8x0_ali_spdifout_ops, 1633 .prealloc_size = 64 * 1024, 1634 .prealloc_max_size = 128 * 1024, 1635 }, 1636 #endif 1637 }; 1638 1639 static int __devinit snd_intel8x0_pcm(struct intel8x0 *chip) 1640 { 1641 int i, tblsize, device, err; 1642 struct ich_pcm_table *tbl, *rec; 1643 1644 switch (chip->device_type) { 1645 case DEVICE_INTEL_ICH4: 1646 tbl = intel_pcms; 1647 tblsize = ARRAY_SIZE(intel_pcms); 1648 if (spdif_aclink) 1649 tblsize--; 1650 break; 1651 case DEVICE_NFORCE: 1652 tbl = nforce_pcms; 1653 tblsize = ARRAY_SIZE(nforce_pcms); 1654 if (spdif_aclink) 1655 tblsize--; 1656 break; 1657 case DEVICE_ALI: 1658 tbl = ali_pcms; 1659 tblsize = ARRAY_SIZE(ali_pcms); 1660 break; 1661 default: 1662 tbl = intel_pcms; 1663 tblsize = 2; 1664 break; 1665 } 1666 1667 device = 0; 1668 for (i = 0; i < tblsize; i++) { 1669 rec = tbl + i; 1670 if (i > 0 && rec->ac97_idx) { 1671 /* activate PCM only when associated AC'97 codec */ 1672 if (! chip->ichd[rec->ac97_idx].pcm) 1673 continue; 1674 } 1675 err = snd_intel8x0_pcm1(chip, device, rec); 1676 if (err < 0) 1677 return err; 1678 device++; 1679 } 1680 1681 chip->pcm_devs = device; 1682 return 0; 1683 } 1684 1685 1686 /* 1687 * Mixer part 1688 */ 1689 1690 static void snd_intel8x0_mixer_free_ac97_bus(struct snd_ac97_bus *bus) 1691 { 1692 struct intel8x0 *chip = bus->private_data; 1693 chip->ac97_bus = NULL; 1694 } 1695 1696 static void snd_intel8x0_mixer_free_ac97(struct snd_ac97 *ac97) 1697 { 1698 struct intel8x0 *chip = ac97->private_data; 1699 chip->ac97[ac97->num] = NULL; 1700 } 1701 1702 static struct ac97_pcm ac97_pcm_defs[] __devinitdata = { 1703 /* front PCM */ 1704 { 1705 .exclusive = 1, 1706 .r = { { 1707 .slots = (1 << AC97_SLOT_PCM_LEFT) | 1708 (1 << AC97_SLOT_PCM_RIGHT) | 1709 (1 << AC97_SLOT_PCM_CENTER) | 1710 (1 << AC97_SLOT_PCM_SLEFT) | 1711 (1 << AC97_SLOT_PCM_SRIGHT) | 1712 (1 << AC97_SLOT_LFE) 1713 }, 1714 { 1715 .slots = (1 << AC97_SLOT_PCM_LEFT) | 1716 (1 << AC97_SLOT_PCM_RIGHT) | 1717 (1 << AC97_SLOT_PCM_LEFT_0) | 1718 (1 << AC97_SLOT_PCM_RIGHT_0) 1719 } 1720 } 1721 }, 1722 /* PCM IN #1 */ 1723 { 1724 .stream = 1, 1725 .exclusive = 1, 1726 .r = { { 1727 .slots = (1 << AC97_SLOT_PCM_LEFT) | 1728 (1 << AC97_SLOT_PCM_RIGHT) 1729 } 1730 } 1731 }, 1732 /* MIC IN #1 */ 1733 { 1734 .stream = 1, 1735 .exclusive = 1, 1736 .r = { { 1737 .slots = (1 << AC97_SLOT_MIC) 1738 } 1739 } 1740 }, 1741 /* S/PDIF PCM */ 1742 { 1743 .exclusive = 1, 1744 .spdif = 1, 1745 .r = { { 1746 .slots = (1 << AC97_SLOT_SPDIF_LEFT2) | 1747 (1 << AC97_SLOT_SPDIF_RIGHT2) 1748 } 1749 } 1750 }, 1751 /* PCM IN #2 */ 1752 { 1753 .stream = 1, 1754 .exclusive = 1, 1755 .r = { { 1756 .slots = (1 << AC97_SLOT_PCM_LEFT) | 1757 (1 << AC97_SLOT_PCM_RIGHT) 1758 } 1759 } 1760 }, 1761 /* MIC IN #2 */ 1762 { 1763 .stream = 1, 1764 .exclusive = 1, 1765 .r = { { 1766 .slots = (1 << AC97_SLOT_MIC) 1767 } 1768 } 1769 }, 1770 }; 1771 1772 static struct ac97_quirk ac97_quirks[] __devinitdata = { 1773 { 1774 .subvendor = 0x0e11, 1775 .subdevice = 0x000e, 1776 .name = "Compaq Deskpro EN", /* AD1885 */ 1777 .type = AC97_TUNE_HP_ONLY 1778 }, 1779 { 1780 .subvendor = 0x0e11, 1781 .subdevice = 0x008a, 1782 .name = "Compaq Evo W4000", /* AD1885 */ 1783 .type = AC97_TUNE_HP_ONLY 1784 }, 1785 { 1786 .subvendor = 0x0e11, 1787 .subdevice = 0x00b8, 1788 .name = "Compaq Evo D510C", 1789 .type = AC97_TUNE_HP_ONLY 1790 }, 1791 { 1792 .subvendor = 0x0e11, 1793 .subdevice = 0x0860, 1794 .name = "HP/Compaq nx7010", 1795 .type = AC97_TUNE_MUTE_LED 1796 }, 1797 { 1798 .subvendor = 0x1014, 1799 .subdevice = 0x0534, 1800 .name = "ThinkPad X31", 1801 .type = AC97_TUNE_INV_EAPD 1802 }, 1803 { 1804 .subvendor = 0x1014, 1805 .subdevice = 0x1f00, 1806 .name = "MS-9128", 1807 .type = AC97_TUNE_ALC_JACK 1808 }, 1809 { 1810 .subvendor = 0x1014, 1811 .subdevice = 0x0267, 1812 .name = "IBM NetVista A30p", /* AD1981B */ 1813 .type = AC97_TUNE_HP_ONLY 1814 }, 1815 { 1816 .subvendor = 0x1025, 1817 .subdevice = 0x0082, 1818 .name = "Acer Travelmate 2310", 1819 .type = AC97_TUNE_HP_ONLY 1820 }, 1821 { 1822 .subvendor = 0x1025, 1823 .subdevice = 0x0083, 1824 .name = "Acer Aspire 3003LCi", 1825 .type = AC97_TUNE_HP_ONLY 1826 }, 1827 { 1828 .subvendor = 0x1028, 1829 .subdevice = 0x00d8, 1830 .name = "Dell Precision 530", /* AD1885 */ 1831 .type = AC97_TUNE_HP_ONLY 1832 }, 1833 { 1834 .subvendor = 0x1028, 1835 .subdevice = 0x010d, 1836 .name = "Dell", /* which model? AD1885 */ 1837 .type = AC97_TUNE_HP_ONLY 1838 }, 1839 { 1840 .subvendor = 0x1028, 1841 .subdevice = 0x0126, 1842 .name = "Dell Optiplex GX260", /* AD1981A */ 1843 .type = AC97_TUNE_HP_ONLY 1844 }, 1845 { 1846 .subvendor = 0x1028, 1847 .subdevice = 0x012c, 1848 .name = "Dell Precision 650", /* AD1981A */ 1849 .type = AC97_TUNE_HP_ONLY 1850 }, 1851 { 1852 .subvendor = 0x1028, 1853 .subdevice = 0x012d, 1854 .name = "Dell Precision 450", /* AD1981B*/ 1855 .type = AC97_TUNE_HP_ONLY 1856 }, 1857 { 1858 .subvendor = 0x1028, 1859 .subdevice = 0x0147, 1860 .name = "Dell", /* which model? AD1981B*/ 1861 .type = AC97_TUNE_HP_ONLY 1862 }, 1863 { 1864 .subvendor = 0x1028, 1865 .subdevice = 0x0151, 1866 .name = "Dell Optiplex GX270", /* AD1981B */ 1867 .type = AC97_TUNE_HP_ONLY 1868 }, 1869 { 1870 .subvendor = 0x1028, 1871 .subdevice = 0x014e, 1872 .name = "Dell D800", /* STAC9750/51 */ 1873 .type = AC97_TUNE_HP_ONLY 1874 }, 1875 { 1876 .subvendor = 0x1028, 1877 .subdevice = 0x0163, 1878 .name = "Dell Unknown", /* STAC9750/51 */ 1879 .type = AC97_TUNE_HP_ONLY 1880 }, 1881 { 1882 .subvendor = 0x1028, 1883 .subdevice = 0x016a, 1884 .name = "Dell Inspiron 8600", /* STAC9750/51 */ 1885 .type = AC97_TUNE_HP_ONLY 1886 }, 1887 { 1888 .subvendor = 0x1028, 1889 .subdevice = 0x0182, 1890 .name = "Dell Latitude D610", /* STAC9750/51 */ 1891 .type = AC97_TUNE_HP_ONLY 1892 }, 1893 { 1894 .subvendor = 0x1028, 1895 .subdevice = 0x0186, 1896 .name = "Dell Latitude D810", /* cf. Malone #41015 */ 1897 .type = AC97_TUNE_HP_MUTE_LED 1898 }, 1899 { 1900 .subvendor = 0x1028, 1901 .subdevice = 0x0188, 1902 .name = "Dell Inspiron 6000", 1903 .type = AC97_TUNE_HP_MUTE_LED /* cf. Malone #41015 */ 1904 }, 1905 { 1906 .subvendor = 0x1028, 1907 .subdevice = 0x0189, 1908 .name = "Dell Inspiron 9300", 1909 .type = AC97_TUNE_HP_MUTE_LED 1910 }, 1911 { 1912 .subvendor = 0x1028, 1913 .subdevice = 0x0191, 1914 .name = "Dell Inspiron 8600", 1915 .type = AC97_TUNE_HP_ONLY 1916 }, 1917 { 1918 .subvendor = 0x103c, 1919 .subdevice = 0x006d, 1920 .name = "HP zv5000", 1921 .type = AC97_TUNE_MUTE_LED /*AD1981B*/ 1922 }, 1923 { /* FIXME: which codec? */ 1924 .subvendor = 0x103c, 1925 .subdevice = 0x00c3, 1926 .name = "HP xw6000", 1927 .type = AC97_TUNE_HP_ONLY 1928 }, 1929 { 1930 .subvendor = 0x103c, 1931 .subdevice = 0x088c, 1932 .name = "HP nc8000", 1933 .type = AC97_TUNE_HP_MUTE_LED 1934 }, 1935 { 1936 .subvendor = 0x103c, 1937 .subdevice = 0x0890, 1938 .name = "HP nc6000", 1939 .type = AC97_TUNE_MUTE_LED 1940 }, 1941 { 1942 .subvendor = 0x103c, 1943 .subdevice = 0x129d, 1944 .name = "HP xw8000", 1945 .type = AC97_TUNE_HP_ONLY 1946 }, 1947 { 1948 .subvendor = 0x103c, 1949 .subdevice = 0x0938, 1950 .name = "HP nc4200", 1951 .type = AC97_TUNE_HP_MUTE_LED 1952 }, 1953 { 1954 .subvendor = 0x103c, 1955 .subdevice = 0x099c, 1956 .name = "HP nx6110/nc6120", 1957 .type = AC97_TUNE_HP_MUTE_LED 1958 }, 1959 { 1960 .subvendor = 0x103c, 1961 .subdevice = 0x0944, 1962 .name = "HP nc6220", 1963 .type = AC97_TUNE_HP_MUTE_LED 1964 }, 1965 { 1966 .subvendor = 0x103c, 1967 .subdevice = 0x0934, 1968 .name = "HP nc8220", 1969 .type = AC97_TUNE_HP_MUTE_LED 1970 }, 1971 { 1972 .subvendor = 0x103c, 1973 .subdevice = 0x12f1, 1974 .name = "HP xw8200", /* AD1981B*/ 1975 .type = AC97_TUNE_HP_ONLY 1976 }, 1977 { 1978 .subvendor = 0x103c, 1979 .subdevice = 0x12f2, 1980 .name = "HP xw6200", 1981 .type = AC97_TUNE_HP_ONLY 1982 }, 1983 { 1984 .subvendor = 0x103c, 1985 .subdevice = 0x3008, 1986 .name = "HP xw4200", /* AD1981B*/ 1987 .type = AC97_TUNE_HP_ONLY 1988 }, 1989 { 1990 .subvendor = 0x104d, 1991 .subdevice = 0x8144, 1992 .name = "Sony", 1993 .type = AC97_TUNE_INV_EAPD 1994 }, 1995 { 1996 .subvendor = 0x104d, 1997 .subdevice = 0x8197, 1998 .name = "Sony S1XP", 1999 .type = AC97_TUNE_INV_EAPD 2000 }, 2001 { 2002 .subvendor = 0x104d, 2003 .subdevice = 0x81c0, 2004 .name = "Sony VAIO VGN-T350P", /*AD1981B*/ 2005 .type = AC97_TUNE_INV_EAPD 2006 }, 2007 { 2008 .subvendor = 0x104d, 2009 .subdevice = 0x81c5, 2010 .name = "Sony VAIO VGN-B1VP", /*AD1981B*/ 2011 .type = AC97_TUNE_INV_EAPD 2012 }, 2013 { 2014 .subvendor = 0x1043, 2015 .subdevice = 0x80f3, 2016 .name = "ASUS ICH5/AD1985", 2017 .type = AC97_TUNE_AD_SHARING 2018 }, 2019 { 2020 .subvendor = 0x10cf, 2021 .subdevice = 0x11c3, 2022 .name = "Fujitsu-Siemens E4010", 2023 .type = AC97_TUNE_HP_ONLY 2024 }, 2025 { 2026 .subvendor = 0x10cf, 2027 .subdevice = 0x1225, 2028 .name = "Fujitsu-Siemens T3010", 2029 .type = AC97_TUNE_HP_ONLY 2030 }, 2031 { 2032 .subvendor = 0x10cf, 2033 .subdevice = 0x1253, 2034 .name = "Fujitsu S6210", /* STAC9750/51 */ 2035 .type = AC97_TUNE_HP_ONLY 2036 }, 2037 { 2038 .subvendor = 0x10cf, 2039 .subdevice = 0x127d, 2040 .name = "Fujitsu Lifebook P7010", 2041 .type = AC97_TUNE_HP_ONLY 2042 }, 2043 { 2044 .subvendor = 0x10cf, 2045 .subdevice = 0x127e, 2046 .name = "Fujitsu Lifebook C1211D", 2047 .type = AC97_TUNE_HP_ONLY 2048 }, 2049 { 2050 .subvendor = 0x10cf, 2051 .subdevice = 0x12ec, 2052 .name = "Fujitsu-Siemens 4010", 2053 .type = AC97_TUNE_HP_ONLY 2054 }, 2055 { 2056 .subvendor = 0x10cf, 2057 .subdevice = 0x12f2, 2058 .name = "Fujitsu-Siemens Celsius H320", 2059 .type = AC97_TUNE_SWAP_HP 2060 }, 2061 { 2062 .subvendor = 0x10f1, 2063 .subdevice = 0x2665, 2064 .name = "Fujitsu-Siemens Celsius", /* AD1981? */ 2065 .type = AC97_TUNE_HP_ONLY 2066 }, 2067 { 2068 .subvendor = 0x10f1, 2069 .subdevice = 0x2885, 2070 .name = "AMD64 Mobo", /* ALC650 */ 2071 .type = AC97_TUNE_HP_ONLY 2072 }, 2073 { 2074 .subvendor = 0x10f1, 2075 .subdevice = 0x2895, 2076 .name = "Tyan Thunder K8WE", 2077 .type = AC97_TUNE_HP_ONLY 2078 }, 2079 { 2080 .subvendor = 0x10f7, 2081 .subdevice = 0x834c, 2082 .name = "Panasonic CF-R4", 2083 .type = AC97_TUNE_HP_ONLY, 2084 }, 2085 { 2086 .subvendor = 0x110a, 2087 .subdevice = 0x0056, 2088 .name = "Fujitsu-Siemens Scenic", /* AD1981? */ 2089 .type = AC97_TUNE_HP_ONLY 2090 }, 2091 { 2092 .subvendor = 0x11d4, 2093 .subdevice = 0x5375, 2094 .name = "ADI AD1985 (discrete)", 2095 .type = AC97_TUNE_HP_ONLY 2096 }, 2097 { 2098 .subvendor = 0x1462, 2099 .subdevice = 0x5470, 2100 .name = "MSI P4 ATX 645 Ultra", 2101 .type = AC97_TUNE_HP_ONLY 2102 }, 2103 { 2104 .subvendor = 0x161f, 2105 .subdevice = 0x203a, 2106 .name = "Gateway 4525GZ", /* AD1981B */ 2107 .type = AC97_TUNE_INV_EAPD 2108 }, 2109 { 2110 .subvendor = 0x1734, 2111 .subdevice = 0x0088, 2112 .name = "Fujitsu-Siemens D1522", /* AD1981 */ 2113 .type = AC97_TUNE_HP_ONLY 2114 }, 2115 { 2116 .subvendor = 0x8086, 2117 .subdevice = 0x2000, 2118 .mask = 0xfff0, 2119 .name = "Intel ICH5/AD1985", 2120 .type = AC97_TUNE_AD_SHARING 2121 }, 2122 { 2123 .subvendor = 0x8086, 2124 .subdevice = 0x4000, 2125 .mask = 0xfff0, 2126 .name = "Intel ICH5/AD1985", 2127 .type = AC97_TUNE_AD_SHARING 2128 }, 2129 { 2130 .subvendor = 0x8086, 2131 .subdevice = 0x4856, 2132 .name = "Intel D845WN (82801BA)", 2133 .type = AC97_TUNE_SWAP_HP 2134 }, 2135 { 2136 .subvendor = 0x8086, 2137 .subdevice = 0x4d44, 2138 .name = "Intel D850EMV2", /* AD1885 */ 2139 .type = AC97_TUNE_HP_ONLY 2140 }, 2141 { 2142 .subvendor = 0x8086, 2143 .subdevice = 0x4d56, 2144 .name = "Intel ICH/AD1885", 2145 .type = AC97_TUNE_HP_ONLY 2146 }, 2147 { 2148 .subvendor = 0x8086, 2149 .subdevice = 0x6000, 2150 .mask = 0xfff0, 2151 .name = "Intel ICH5/AD1985", 2152 .type = AC97_TUNE_AD_SHARING 2153 }, 2154 { 2155 .subvendor = 0x8086, 2156 .subdevice = 0xe000, 2157 .mask = 0xfff0, 2158 .name = "Intel ICH5/AD1985", 2159 .type = AC97_TUNE_AD_SHARING 2160 }, 2161 #if 0 /* FIXME: this seems wrong on most boards */ 2162 { 2163 .subvendor = 0x8086, 2164 .subdevice = 0xa000, 2165 .mask = 0xfff0, 2166 .name = "Intel ICH5/AD1985", 2167 .type = AC97_TUNE_HP_ONLY 2168 }, 2169 #endif 2170 { } /* terminator */ 2171 }; 2172 2173 static int __devinit snd_intel8x0_mixer(struct intel8x0 *chip, int ac97_clock, 2174 const char *quirk_override) 2175 { 2176 struct snd_ac97_bus *pbus; 2177 struct snd_ac97_template ac97; 2178 int err; 2179 unsigned int i, codecs; 2180 unsigned int glob_sta = 0; 2181 struct snd_ac97_bus_ops *ops; 2182 static struct snd_ac97_bus_ops standard_bus_ops = { 2183 .write = snd_intel8x0_codec_write, 2184 .read = snd_intel8x0_codec_read, 2185 }; 2186 static struct snd_ac97_bus_ops ali_bus_ops = { 2187 .write = snd_intel8x0_ali_codec_write, 2188 .read = snd_intel8x0_ali_codec_read, 2189 }; 2190 2191 chip->spdif_idx = -1; /* use PCMOUT (or disabled) */ 2192 if (!spdif_aclink) { 2193 switch (chip->device_type) { 2194 case DEVICE_NFORCE: 2195 chip->spdif_idx = NVD_SPBAR; 2196 break; 2197 case DEVICE_ALI: 2198 chip->spdif_idx = ALID_AC97SPDIFOUT; 2199 break; 2200 case DEVICE_INTEL_ICH4: 2201 chip->spdif_idx = ICHD_SPBAR; 2202 break; 2203 }; 2204 } 2205 2206 chip->in_ac97_init = 1; 2207 2208 memset(&ac97, 0, sizeof(ac97)); 2209 ac97.private_data = chip; 2210 ac97.private_free = snd_intel8x0_mixer_free_ac97; 2211 ac97.scaps = AC97_SCAP_SKIP_MODEM | AC97_SCAP_POWER_SAVE; 2212 if (chip->xbox) 2213 ac97.scaps |= AC97_SCAP_DETECT_BY_VENDOR; 2214 if (chip->device_type != DEVICE_ALI) { 2215 glob_sta = igetdword(chip, ICHREG(GLOB_STA)); 2216 ops = &standard_bus_ops; 2217 chip->in_sdin_init = 1; 2218 codecs = 0; 2219 for (i = 0; i < chip->max_codecs; i++) { 2220 if (! (glob_sta & chip->codec_bit[i])) 2221 continue; 2222 if (chip->device_type == DEVICE_INTEL_ICH4) { 2223 snd_intel8x0_codec_read_test(chip, codecs); 2224 chip->ac97_sdin[codecs] = 2225 igetbyte(chip, ICHREG(SDM)) & ICH_LDI_MASK; 2226 if (snd_BUG_ON(chip->ac97_sdin[codecs] >= 3)) 2227 chip->ac97_sdin[codecs] = 0; 2228 } else 2229 chip->ac97_sdin[codecs] = i; 2230 codecs++; 2231 } 2232 chip->in_sdin_init = 0; 2233 if (! codecs) 2234 codecs = 1; 2235 } else { 2236 ops = &ali_bus_ops; 2237 codecs = 1; 2238 /* detect the secondary codec */ 2239 for (i = 0; i < 100; i++) { 2240 unsigned int reg = igetdword(chip, ICHREG(ALI_RTSR)); 2241 if (reg & 0x40) { 2242 codecs = 2; 2243 break; 2244 } 2245 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x40); 2246 udelay(1); 2247 } 2248 } 2249 if ((err = snd_ac97_bus(chip->card, 0, ops, chip, &pbus)) < 0) 2250 goto __err; 2251 pbus->private_free = snd_intel8x0_mixer_free_ac97_bus; 2252 if (ac97_clock >= 8000 && ac97_clock <= 48000) 2253 pbus->clock = ac97_clock; 2254 /* FIXME: my test board doesn't work well with VRA... */ 2255 if (chip->device_type == DEVICE_ALI) 2256 pbus->no_vra = 1; 2257 else 2258 pbus->dra = 1; 2259 chip->ac97_bus = pbus; 2260 chip->ncodecs = codecs; 2261 2262 ac97.pci = chip->pci; 2263 for (i = 0; i < codecs; i++) { 2264 ac97.num = i; 2265 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i])) < 0) { 2266 if (err != -EACCES) 2267 snd_printk(KERN_ERR "Unable to initialize codec #%d\n", i); 2268 if (i == 0) 2269 goto __err; 2270 } 2271 } 2272 /* tune up the primary codec */ 2273 snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override); 2274 /* enable separate SDINs for ICH4 */ 2275 if (chip->device_type == DEVICE_INTEL_ICH4) 2276 pbus->isdin = 1; 2277 /* find the available PCM streams */ 2278 i = ARRAY_SIZE(ac97_pcm_defs); 2279 if (chip->device_type != DEVICE_INTEL_ICH4) 2280 i -= 2; /* do not allocate PCM2IN and MIC2 */ 2281 if (chip->spdif_idx < 0) 2282 i--; /* do not allocate S/PDIF */ 2283 err = snd_ac97_pcm_assign(pbus, i, ac97_pcm_defs); 2284 if (err < 0) 2285 goto __err; 2286 chip->ichd[ICHD_PCMOUT].pcm = &pbus->pcms[0]; 2287 chip->ichd[ICHD_PCMIN].pcm = &pbus->pcms[1]; 2288 chip->ichd[ICHD_MIC].pcm = &pbus->pcms[2]; 2289 if (chip->spdif_idx >= 0) 2290 chip->ichd[chip->spdif_idx].pcm = &pbus->pcms[3]; 2291 if (chip->device_type == DEVICE_INTEL_ICH4) { 2292 chip->ichd[ICHD_PCM2IN].pcm = &pbus->pcms[4]; 2293 chip->ichd[ICHD_MIC2].pcm = &pbus->pcms[5]; 2294 } 2295 /* enable separate SDINs for ICH4 */ 2296 if (chip->device_type == DEVICE_INTEL_ICH4) { 2297 struct ac97_pcm *pcm = chip->ichd[ICHD_PCM2IN].pcm; 2298 u8 tmp = igetbyte(chip, ICHREG(SDM)); 2299 tmp &= ~(ICH_DI2L_MASK|ICH_DI1L_MASK); 2300 if (pcm) { 2301 tmp |= ICH_SE; /* steer enable for multiple SDINs */ 2302 tmp |= chip->ac97_sdin[0] << ICH_DI1L_SHIFT; 2303 for (i = 1; i < 4; i++) { 2304 if (pcm->r[0].codec[i]) { 2305 tmp |= chip->ac97_sdin[pcm->r[0].codec[1]->num] << ICH_DI2L_SHIFT; 2306 break; 2307 } 2308 } 2309 } else { 2310 tmp &= ~ICH_SE; /* steer disable */ 2311 } 2312 iputbyte(chip, ICHREG(SDM), tmp); 2313 } 2314 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) { 2315 chip->multi4 = 1; 2316 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_LFE)) { 2317 chip->multi6 = 1; 2318 if (chip->ac97[0]->flags & AC97_HAS_8CH) 2319 chip->multi8 = 1; 2320 } 2321 } 2322 if (pbus->pcms[0].r[1].rslots[0]) { 2323 chip->dra = 1; 2324 } 2325 if (chip->device_type == DEVICE_INTEL_ICH4) { 2326 if ((igetdword(chip, ICHREG(GLOB_STA)) & ICH_SAMPLE_CAP) == ICH_SAMPLE_16_20) 2327 chip->smp20bit = 1; 2328 } 2329 if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) { 2330 /* 48kHz only */ 2331 chip->ichd[chip->spdif_idx].pcm->rates = SNDRV_PCM_RATE_48000; 2332 } 2333 if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) { 2334 /* use slot 10/11 for SPDIF */ 2335 u32 val; 2336 val = igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK; 2337 val |= ICH_PCM_SPDIF_1011; 2338 iputdword(chip, ICHREG(GLOB_CNT), val); 2339 snd_ac97_update_bits(chip->ac97[0], AC97_EXTENDED_STATUS, 0x03 << 4, 0x03 << 4); 2340 } 2341 chip->in_ac97_init = 0; 2342 return 0; 2343 2344 __err: 2345 /* clear the cold-reset bit for the next chance */ 2346 if (chip->device_type != DEVICE_ALI) 2347 iputdword(chip, ICHREG(GLOB_CNT), 2348 igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD); 2349 return err; 2350 } 2351 2352 2353 /* 2354 * 2355 */ 2356 2357 static void do_ali_reset(struct intel8x0 *chip) 2358 { 2359 iputdword(chip, ICHREG(ALI_SCR), ICH_ALI_SC_RESET); 2360 iputdword(chip, ICHREG(ALI_FIFOCR1), 0x83838383); 2361 iputdword(chip, ICHREG(ALI_FIFOCR2), 0x83838383); 2362 iputdword(chip, ICHREG(ALI_FIFOCR3), 0x83838383); 2363 iputdword(chip, ICHREG(ALI_INTERFACECR), 2364 ICH_ALI_IF_PI|ICH_ALI_IF_PO); 2365 iputdword(chip, ICHREG(ALI_INTERRUPTCR), 0x00000000); 2366 iputdword(chip, ICHREG(ALI_INTERRUPTSR), 0x00000000); 2367 } 2368 2369 #ifdef CONFIG_SND_AC97_POWER_SAVE 2370 static struct snd_pci_quirk ich_chip_reset_mode[] = { 2371 SND_PCI_QUIRK(0x1014, 0x051f, "Thinkpad R32", 1), 2372 { } /* end */ 2373 }; 2374 2375 static int snd_intel8x0_ich_chip_cold_reset(struct intel8x0 *chip) 2376 { 2377 unsigned int cnt; 2378 /* ACLink on, 2 channels */ 2379 2380 if (snd_pci_quirk_lookup(chip->pci, ich_chip_reset_mode)) 2381 return -EIO; 2382 2383 cnt = igetdword(chip, ICHREG(GLOB_CNT)); 2384 cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK); 2385 2386 /* do cold reset - the full ac97 powerdown may leave the controller 2387 * in a warm state but actually it cannot communicate with the codec. 2388 */ 2389 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_AC97COLD); 2390 cnt = igetdword(chip, ICHREG(GLOB_CNT)); 2391 udelay(10); 2392 iputdword(chip, ICHREG(GLOB_CNT), cnt | ICH_AC97COLD); 2393 msleep(1); 2394 return 0; 2395 } 2396 #define snd_intel8x0_ich_chip_can_cold_reset(chip) \ 2397 (!snd_pci_quirk_lookup(chip->pci, ich_chip_reset_mode)) 2398 #else 2399 #define snd_intel8x0_ich_chip_cold_reset(chip) 0 2400 #define snd_intel8x0_ich_chip_can_cold_reset(chip) (0) 2401 #endif 2402 2403 static int snd_intel8x0_ich_chip_reset(struct intel8x0 *chip) 2404 { 2405 unsigned long end_time; 2406 unsigned int cnt; 2407 /* ACLink on, 2 channels */ 2408 cnt = igetdword(chip, ICHREG(GLOB_CNT)); 2409 cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK); 2410 /* finish cold or do warm reset */ 2411 cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM; 2412 iputdword(chip, ICHREG(GLOB_CNT), cnt); 2413 end_time = (jiffies + (HZ / 4)) + 1; 2414 do { 2415 if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0) 2416 return 0; 2417 schedule_timeout_uninterruptible(1); 2418 } while (time_after_eq(end_time, jiffies)); 2419 snd_printk(KERN_ERR "AC'97 warm reset still in progress? [0x%x]\n", 2420 igetdword(chip, ICHREG(GLOB_CNT))); 2421 return -EIO; 2422 } 2423 2424 static int snd_intel8x0_ich_chip_init(struct intel8x0 *chip, int probing) 2425 { 2426 unsigned long end_time; 2427 unsigned int status, nstatus; 2428 unsigned int cnt; 2429 int err; 2430 2431 /* put logic to right state */ 2432 /* first clear status bits */ 2433 status = ICH_RCS | ICH_MCINT | ICH_POINT | ICH_PIINT; 2434 if (chip->device_type == DEVICE_NFORCE) 2435 status |= ICH_NVSPINT; 2436 cnt = igetdword(chip, ICHREG(GLOB_STA)); 2437 iputdword(chip, ICHREG(GLOB_STA), cnt & status); 2438 2439 if (snd_intel8x0_ich_chip_can_cold_reset(chip)) 2440 err = snd_intel8x0_ich_chip_cold_reset(chip); 2441 else 2442 err = snd_intel8x0_ich_chip_reset(chip); 2443 if (err < 0) 2444 return err; 2445 2446 if (probing) { 2447 /* wait for any codec ready status. 2448 * Once it becomes ready it should remain ready 2449 * as long as we do not disable the ac97 link. 2450 */ 2451 end_time = jiffies + HZ; 2452 do { 2453 status = igetdword(chip, ICHREG(GLOB_STA)) & 2454 chip->codec_isr_bits; 2455 if (status) 2456 break; 2457 schedule_timeout_uninterruptible(1); 2458 } while (time_after_eq(end_time, jiffies)); 2459 if (! status) { 2460 /* no codec is found */ 2461 snd_printk(KERN_ERR "codec_ready: codec is not ready [0x%x]\n", 2462 igetdword(chip, ICHREG(GLOB_STA))); 2463 return -EIO; 2464 } 2465 2466 /* wait for other codecs ready status. */ 2467 end_time = jiffies + HZ / 4; 2468 while (status != chip->codec_isr_bits && 2469 time_after_eq(end_time, jiffies)) { 2470 schedule_timeout_uninterruptible(1); 2471 status |= igetdword(chip, ICHREG(GLOB_STA)) & 2472 chip->codec_isr_bits; 2473 } 2474 2475 } else { 2476 /* resume phase */ 2477 int i; 2478 status = 0; 2479 for (i = 0; i < chip->ncodecs; i++) 2480 if (chip->ac97[i]) 2481 status |= chip->codec_bit[chip->ac97_sdin[i]]; 2482 /* wait until all the probed codecs are ready */ 2483 end_time = jiffies + HZ; 2484 do { 2485 nstatus = igetdword(chip, ICHREG(GLOB_STA)) & 2486 chip->codec_isr_bits; 2487 if (status == nstatus) 2488 break; 2489 schedule_timeout_uninterruptible(1); 2490 } while (time_after_eq(end_time, jiffies)); 2491 } 2492 2493 if (chip->device_type == DEVICE_SIS) { 2494 /* unmute the output on SIS7012 */ 2495 iputword(chip, 0x4c, igetword(chip, 0x4c) | 1); 2496 } 2497 if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) { 2498 /* enable SPDIF interrupt */ 2499 unsigned int val; 2500 pci_read_config_dword(chip->pci, 0x4c, &val); 2501 val |= 0x1000000; 2502 pci_write_config_dword(chip->pci, 0x4c, val); 2503 } 2504 return 0; 2505 } 2506 2507 static int snd_intel8x0_ali_chip_init(struct intel8x0 *chip, int probing) 2508 { 2509 u32 reg; 2510 int i = 0; 2511 2512 reg = igetdword(chip, ICHREG(ALI_SCR)); 2513 if ((reg & 2) == 0) /* Cold required */ 2514 reg |= 2; 2515 else 2516 reg |= 1; /* Warm */ 2517 reg &= ~0x80000000; /* ACLink on */ 2518 iputdword(chip, ICHREG(ALI_SCR), reg); 2519 2520 for (i = 0; i < HZ / 2; i++) { 2521 if (! (igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ALI_INT_GPIO)) 2522 goto __ok; 2523 schedule_timeout_uninterruptible(1); 2524 } 2525 snd_printk(KERN_ERR "AC'97 reset failed.\n"); 2526 if (probing) 2527 return -EIO; 2528 2529 __ok: 2530 for (i = 0; i < HZ / 2; i++) { 2531 reg = igetdword(chip, ICHREG(ALI_RTSR)); 2532 if (reg & 0x80) /* primary codec */ 2533 break; 2534 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x80); 2535 schedule_timeout_uninterruptible(1); 2536 } 2537 2538 do_ali_reset(chip); 2539 return 0; 2540 } 2541 2542 static int snd_intel8x0_chip_init(struct intel8x0 *chip, int probing) 2543 { 2544 unsigned int i, timeout; 2545 int err; 2546 2547 if (chip->device_type != DEVICE_ALI) { 2548 if ((err = snd_intel8x0_ich_chip_init(chip, probing)) < 0) 2549 return err; 2550 iagetword(chip, 0); /* clear semaphore flag */ 2551 } else { 2552 if ((err = snd_intel8x0_ali_chip_init(chip, probing)) < 0) 2553 return err; 2554 } 2555 2556 /* disable interrupts */ 2557 for (i = 0; i < chip->bdbars_count; i++) 2558 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00); 2559 /* reset channels */ 2560 for (i = 0; i < chip->bdbars_count; i++) 2561 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS); 2562 for (i = 0; i < chip->bdbars_count; i++) { 2563 timeout = 100000; 2564 while (--timeout != 0) { 2565 if ((igetbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset) & ICH_RESETREGS) == 0) 2566 break; 2567 } 2568 if (timeout == 0) 2569 printk(KERN_ERR "intel8x0: reset of registers failed?\n"); 2570 } 2571 /* initialize Buffer Descriptor Lists */ 2572 for (i = 0; i < chip->bdbars_count; i++) 2573 iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset, 2574 chip->ichd[i].bdbar_addr); 2575 return 0; 2576 } 2577 2578 static int snd_intel8x0_free(struct intel8x0 *chip) 2579 { 2580 unsigned int i; 2581 2582 if (chip->irq < 0) 2583 goto __hw_end; 2584 /* disable interrupts */ 2585 for (i = 0; i < chip->bdbars_count; i++) 2586 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00); 2587 /* reset channels */ 2588 for (i = 0; i < chip->bdbars_count; i++) 2589 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS); 2590 if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) { 2591 /* stop the spdif interrupt */ 2592 unsigned int val; 2593 pci_read_config_dword(chip->pci, 0x4c, &val); 2594 val &= ~0x1000000; 2595 pci_write_config_dword(chip->pci, 0x4c, val); 2596 } 2597 /* --- */ 2598 2599 __hw_end: 2600 if (chip->irq >= 0) 2601 free_irq(chip->irq, chip); 2602 if (chip->bdbars.area) { 2603 if (chip->fix_nocache) 2604 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 0); 2605 snd_dma_free_pages(&chip->bdbars); 2606 } 2607 if (chip->addr) 2608 pci_iounmap(chip->pci, chip->addr); 2609 if (chip->bmaddr) 2610 pci_iounmap(chip->pci, chip->bmaddr); 2611 pci_release_regions(chip->pci); 2612 pci_disable_device(chip->pci); 2613 kfree(chip); 2614 return 0; 2615 } 2616 2617 #ifdef CONFIG_PM 2618 /* 2619 * power management 2620 */ 2621 static int intel8x0_suspend(struct pci_dev *pci, pm_message_t state) 2622 { 2623 struct snd_card *card = pci_get_drvdata(pci); 2624 struct intel8x0 *chip = card->private_data; 2625 int i; 2626 2627 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 2628 for (i = 0; i < chip->pcm_devs; i++) 2629 snd_pcm_suspend_all(chip->pcm[i]); 2630 /* clear nocache */ 2631 if (chip->fix_nocache) { 2632 for (i = 0; i < chip->bdbars_count; i++) { 2633 struct ichdev *ichdev = &chip->ichd[i]; 2634 if (ichdev->substream && ichdev->page_attr_changed) { 2635 struct snd_pcm_runtime *runtime = ichdev->substream->runtime; 2636 if (runtime->dma_area) 2637 fill_nocache(runtime->dma_area, runtime->dma_bytes, 0); 2638 } 2639 } 2640 } 2641 for (i = 0; i < chip->ncodecs; i++) 2642 snd_ac97_suspend(chip->ac97[i]); 2643 if (chip->device_type == DEVICE_INTEL_ICH4) 2644 chip->sdm_saved = igetbyte(chip, ICHREG(SDM)); 2645 2646 if (chip->irq >= 0) { 2647 free_irq(chip->irq, chip); 2648 chip->irq = -1; 2649 } 2650 pci_disable_device(pci); 2651 pci_save_state(pci); 2652 /* The call below may disable built-in speaker on some laptops 2653 * after S2RAM. So, don't touch it. 2654 */ 2655 /* pci_set_power_state(pci, pci_choose_state(pci, state)); */ 2656 return 0; 2657 } 2658 2659 static int intel8x0_resume(struct pci_dev *pci) 2660 { 2661 struct snd_card *card = pci_get_drvdata(pci); 2662 struct intel8x0 *chip = card->private_data; 2663 int i; 2664 2665 pci_set_power_state(pci, PCI_D0); 2666 pci_restore_state(pci); 2667 if (pci_enable_device(pci) < 0) { 2668 printk(KERN_ERR "intel8x0: pci_enable_device failed, " 2669 "disabling device\n"); 2670 snd_card_disconnect(card); 2671 return -EIO; 2672 } 2673 pci_set_master(pci); 2674 snd_intel8x0_chip_init(chip, 0); 2675 if (request_irq(pci->irq, snd_intel8x0_interrupt, 2676 IRQF_SHARED, KBUILD_MODNAME, chip)) { 2677 printk(KERN_ERR "intel8x0: unable to grab IRQ %d, " 2678 "disabling device\n", pci->irq); 2679 snd_card_disconnect(card); 2680 return -EIO; 2681 } 2682 chip->irq = pci->irq; 2683 synchronize_irq(chip->irq); 2684 2685 /* re-initialize mixer stuff */ 2686 if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) { 2687 /* enable separate SDINs for ICH4 */ 2688 iputbyte(chip, ICHREG(SDM), chip->sdm_saved); 2689 /* use slot 10/11 for SPDIF */ 2690 iputdword(chip, ICHREG(GLOB_CNT), 2691 (igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK) | 2692 ICH_PCM_SPDIF_1011); 2693 } 2694 2695 /* refill nocache */ 2696 if (chip->fix_nocache) 2697 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1); 2698 2699 for (i = 0; i < chip->ncodecs; i++) 2700 snd_ac97_resume(chip->ac97[i]); 2701 2702 /* refill nocache */ 2703 if (chip->fix_nocache) { 2704 for (i = 0; i < chip->bdbars_count; i++) { 2705 struct ichdev *ichdev = &chip->ichd[i]; 2706 if (ichdev->substream && ichdev->page_attr_changed) { 2707 struct snd_pcm_runtime *runtime = ichdev->substream->runtime; 2708 if (runtime->dma_area) 2709 fill_nocache(runtime->dma_area, runtime->dma_bytes, 1); 2710 } 2711 } 2712 } 2713 2714 /* resume status */ 2715 for (i = 0; i < chip->bdbars_count; i++) { 2716 struct ichdev *ichdev = &chip->ichd[i]; 2717 unsigned long port = ichdev->reg_offset; 2718 if (! ichdev->substream || ! ichdev->suspended) 2719 continue; 2720 if (ichdev->ichd == ICHD_PCMOUT) 2721 snd_intel8x0_setup_pcm_out(chip, ichdev->substream->runtime); 2722 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr); 2723 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi); 2724 iputbyte(chip, port + ICH_REG_OFF_CIV, ichdev->civ); 2725 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI); 2726 } 2727 2728 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 2729 return 0; 2730 } 2731 #endif /* CONFIG_PM */ 2732 2733 #define INTEL8X0_TESTBUF_SIZE 32768 /* enough large for one shot */ 2734 2735 static void __devinit intel8x0_measure_ac97_clock(struct intel8x0 *chip) 2736 { 2737 struct snd_pcm_substream *subs; 2738 struct ichdev *ichdev; 2739 unsigned long port; 2740 unsigned long pos, pos1, t; 2741 int civ, timeout = 1000, attempt = 1; 2742 struct timespec start_time, stop_time; 2743 2744 if (chip->ac97_bus->clock != 48000) 2745 return; /* specified in module option */ 2746 2747 __again: 2748 subs = chip->pcm[0]->streams[0].substream; 2749 if (! subs || subs->dma_buffer.bytes < INTEL8X0_TESTBUF_SIZE) { 2750 snd_printk(KERN_WARNING "no playback buffer allocated - aborting measure ac97 clock\n"); 2751 return; 2752 } 2753 ichdev = &chip->ichd[ICHD_PCMOUT]; 2754 ichdev->physbuf = subs->dma_buffer.addr; 2755 ichdev->size = ichdev->fragsize = INTEL8X0_TESTBUF_SIZE; 2756 ichdev->substream = NULL; /* don't process interrupts */ 2757 2758 /* set rate */ 2759 if (snd_ac97_set_rate(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 48000) < 0) { 2760 snd_printk(KERN_ERR "cannot set ac97 rate: clock = %d\n", chip->ac97_bus->clock); 2761 return; 2762 } 2763 snd_intel8x0_setup_periods(chip, ichdev); 2764 port = ichdev->reg_offset; 2765 spin_lock_irq(&chip->reg_lock); 2766 chip->in_measurement = 1; 2767 /* trigger */ 2768 if (chip->device_type != DEVICE_ALI) 2769 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE | ICH_STARTBM); 2770 else { 2771 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE); 2772 iputdword(chip, ICHREG(ALI_DMACR), 1 << ichdev->ali_slot); 2773 } 2774 do_posix_clock_monotonic_gettime(&start_time); 2775 spin_unlock_irq(&chip->reg_lock); 2776 msleep(50); 2777 spin_lock_irq(&chip->reg_lock); 2778 /* check the position */ 2779 do { 2780 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV); 2781 pos1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb); 2782 if (pos1 == 0) { 2783 udelay(10); 2784 continue; 2785 } 2786 if (civ == igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV) && 2787 pos1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb)) 2788 break; 2789 } while (timeout--); 2790 if (pos1 == 0) { /* oops, this value is not reliable */ 2791 pos = 0; 2792 } else { 2793 pos = ichdev->fragsize1; 2794 pos -= pos1 << ichdev->pos_shift; 2795 pos += ichdev->position; 2796 } 2797 chip->in_measurement = 0; 2798 do_posix_clock_monotonic_gettime(&stop_time); 2799 /* stop */ 2800 if (chip->device_type == DEVICE_ALI) { 2801 iputdword(chip, ICHREG(ALI_DMACR), 1 << (ichdev->ali_slot + 16)); 2802 iputbyte(chip, port + ICH_REG_OFF_CR, 0); 2803 while (igetbyte(chip, port + ICH_REG_OFF_CR)) 2804 ; 2805 } else { 2806 iputbyte(chip, port + ICH_REG_OFF_CR, 0); 2807 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) 2808 ; 2809 } 2810 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS); 2811 spin_unlock_irq(&chip->reg_lock); 2812 2813 if (pos == 0) { 2814 snd_printk(KERN_ERR "intel8x0: measure - unreliable DMA position..\n"); 2815 __retry: 2816 if (attempt < 3) { 2817 msleep(300); 2818 attempt++; 2819 goto __again; 2820 } 2821 goto __end; 2822 } 2823 2824 pos /= 4; 2825 t = stop_time.tv_sec - start_time.tv_sec; 2826 t *= 1000000; 2827 t += (stop_time.tv_nsec - start_time.tv_nsec) / 1000; 2828 printk(KERN_INFO "%s: measured %lu usecs (%lu samples)\n", __func__, t, pos); 2829 if (t == 0) { 2830 snd_printk(KERN_ERR "intel8x0: ?? calculation error..\n"); 2831 goto __retry; 2832 } 2833 pos *= 1000; 2834 pos = (pos / t) * 1000 + ((pos % t) * 1000) / t; 2835 if (pos < 40000 || pos >= 60000) { 2836 /* abnormal value. hw problem? */ 2837 printk(KERN_INFO "intel8x0: measured clock %ld rejected\n", pos); 2838 goto __retry; 2839 } else if (pos > 40500 && pos < 41500) 2840 /* first exception - 41000Hz reference clock */ 2841 chip->ac97_bus->clock = 41000; 2842 else if (pos > 43600 && pos < 44600) 2843 /* second exception - 44100HZ reference clock */ 2844 chip->ac97_bus->clock = 44100; 2845 else if (pos < 47500 || pos > 48500) 2846 /* not 48000Hz, tuning the clock.. */ 2847 chip->ac97_bus->clock = (chip->ac97_bus->clock * 48000) / pos; 2848 __end: 2849 printk(KERN_INFO "intel8x0: clocking to %d\n", chip->ac97_bus->clock); 2850 snd_ac97_update_power(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 0); 2851 } 2852 2853 static struct snd_pci_quirk intel8x0_clock_list[] __devinitdata = { 2854 SND_PCI_QUIRK(0x0e11, 0x008a, "AD1885", 41000), 2855 SND_PCI_QUIRK(0x1028, 0x00be, "AD1885", 44100), 2856 SND_PCI_QUIRK(0x1028, 0x0177, "AD1980", 48000), 2857 SND_PCI_QUIRK(0x1028, 0x01ad, "AD1981B", 48000), 2858 SND_PCI_QUIRK(0x1043, 0x80f3, "AD1985", 48000), 2859 { } /* terminator */ 2860 }; 2861 2862 static int __devinit intel8x0_in_clock_list(struct intel8x0 *chip) 2863 { 2864 struct pci_dev *pci = chip->pci; 2865 const struct snd_pci_quirk *wl; 2866 2867 wl = snd_pci_quirk_lookup(pci, intel8x0_clock_list); 2868 if (!wl) 2869 return 0; 2870 printk(KERN_INFO "intel8x0: white list rate for %04x:%04x is %i\n", 2871 pci->subsystem_vendor, pci->subsystem_device, wl->value); 2872 chip->ac97_bus->clock = wl->value; 2873 return 1; 2874 } 2875 2876 #ifdef CONFIG_PROC_FS 2877 static void snd_intel8x0_proc_read(struct snd_info_entry * entry, 2878 struct snd_info_buffer *buffer) 2879 { 2880 struct intel8x0 *chip = entry->private_data; 2881 unsigned int tmp; 2882 2883 snd_iprintf(buffer, "Intel8x0\n\n"); 2884 if (chip->device_type == DEVICE_ALI) 2885 return; 2886 tmp = igetdword(chip, ICHREG(GLOB_STA)); 2887 snd_iprintf(buffer, "Global control : 0x%08x\n", igetdword(chip, ICHREG(GLOB_CNT))); 2888 snd_iprintf(buffer, "Global status : 0x%08x\n", tmp); 2889 if (chip->device_type == DEVICE_INTEL_ICH4) 2890 snd_iprintf(buffer, "SDM : 0x%08x\n", igetdword(chip, ICHREG(SDM))); 2891 snd_iprintf(buffer, "AC'97 codecs ready :"); 2892 if (tmp & chip->codec_isr_bits) { 2893 int i; 2894 static const char *codecs[3] = { 2895 "primary", "secondary", "tertiary" 2896 }; 2897 for (i = 0; i < chip->max_codecs; i++) 2898 if (tmp & chip->codec_bit[i]) 2899 snd_iprintf(buffer, " %s", codecs[i]); 2900 } else 2901 snd_iprintf(buffer, " none"); 2902 snd_iprintf(buffer, "\n"); 2903 if (chip->device_type == DEVICE_INTEL_ICH4 || 2904 chip->device_type == DEVICE_SIS) 2905 snd_iprintf(buffer, "AC'97 codecs SDIN : %i %i %i\n", 2906 chip->ac97_sdin[0], 2907 chip->ac97_sdin[1], 2908 chip->ac97_sdin[2]); 2909 } 2910 2911 static void __devinit snd_intel8x0_proc_init(struct intel8x0 * chip) 2912 { 2913 struct snd_info_entry *entry; 2914 2915 if (! snd_card_proc_new(chip->card, "intel8x0", &entry)) 2916 snd_info_set_text_ops(entry, chip, snd_intel8x0_proc_read); 2917 } 2918 #else 2919 #define snd_intel8x0_proc_init(x) 2920 #endif 2921 2922 static int snd_intel8x0_dev_free(struct snd_device *device) 2923 { 2924 struct intel8x0 *chip = device->device_data; 2925 return snd_intel8x0_free(chip); 2926 } 2927 2928 struct ich_reg_info { 2929 unsigned int int_sta_mask; 2930 unsigned int offset; 2931 }; 2932 2933 static unsigned int ich_codec_bits[3] = { 2934 ICH_PCR, ICH_SCR, ICH_TCR 2935 }; 2936 static unsigned int sis_codec_bits[3] = { 2937 ICH_PCR, ICH_SCR, ICH_SIS_TCR 2938 }; 2939 2940 static int __devinit snd_intel8x0_inside_vm(struct pci_dev *pci) 2941 { 2942 int result = inside_vm; 2943 char *msg = NULL; 2944 2945 /* check module parameter first (override detection) */ 2946 if (result >= 0) { 2947 msg = result ? "enable (forced) VM" : "disable (forced) VM"; 2948 goto fini; 2949 } 2950 2951 /* detect KVM and Parallels virtual environments */ 2952 result = kvm_para_available(); 2953 #ifdef X86_FEATURE_HYPERVISOR 2954 result = result || boot_cpu_has(X86_FEATURE_HYPERVISOR); 2955 #endif 2956 if (!result) 2957 goto fini; 2958 2959 /* check for known (emulated) devices */ 2960 if (pci->subsystem_vendor == 0x1af4 && 2961 pci->subsystem_device == 0x1100) { 2962 /* KVM emulated sound, PCI SSID: 1af4:1100 */ 2963 msg = "enable KVM"; 2964 } else if (pci->subsystem_vendor == 0x1ab8) { 2965 /* Parallels VM emulated sound, PCI SSID: 1ab8:xxxx */ 2966 msg = "enable Parallels VM"; 2967 } else { 2968 msg = "disable (unknown or VT-d) VM"; 2969 result = 0; 2970 } 2971 2972 fini: 2973 if (msg != NULL) 2974 printk(KERN_INFO "intel8x0: %s optimization\n", msg); 2975 2976 return result; 2977 } 2978 2979 static int __devinit snd_intel8x0_create(struct snd_card *card, 2980 struct pci_dev *pci, 2981 unsigned long device_type, 2982 struct intel8x0 ** r_intel8x0) 2983 { 2984 struct intel8x0 *chip; 2985 int err; 2986 unsigned int i; 2987 unsigned int int_sta_masks; 2988 struct ichdev *ichdev; 2989 static struct snd_device_ops ops = { 2990 .dev_free = snd_intel8x0_dev_free, 2991 }; 2992 2993 static unsigned int bdbars[] = { 2994 3, /* DEVICE_INTEL */ 2995 6, /* DEVICE_INTEL_ICH4 */ 2996 3, /* DEVICE_SIS */ 2997 6, /* DEVICE_ALI */ 2998 4, /* DEVICE_NFORCE */ 2999 }; 3000 static struct ich_reg_info intel_regs[6] = { 3001 { ICH_PIINT, 0 }, 3002 { ICH_POINT, 0x10 }, 3003 { ICH_MCINT, 0x20 }, 3004 { ICH_M2INT, 0x40 }, 3005 { ICH_P2INT, 0x50 }, 3006 { ICH_SPINT, 0x60 }, 3007 }; 3008 static struct ich_reg_info nforce_regs[4] = { 3009 { ICH_PIINT, 0 }, 3010 { ICH_POINT, 0x10 }, 3011 { ICH_MCINT, 0x20 }, 3012 { ICH_NVSPINT, 0x70 }, 3013 }; 3014 static struct ich_reg_info ali_regs[6] = { 3015 { ALI_INT_PCMIN, 0x40 }, 3016 { ALI_INT_PCMOUT, 0x50 }, 3017 { ALI_INT_MICIN, 0x60 }, 3018 { ALI_INT_CODECSPDIFOUT, 0x70 }, 3019 { ALI_INT_SPDIFIN, 0xa0 }, 3020 { ALI_INT_SPDIFOUT, 0xb0 }, 3021 }; 3022 struct ich_reg_info *tbl; 3023 3024 *r_intel8x0 = NULL; 3025 3026 if ((err = pci_enable_device(pci)) < 0) 3027 return err; 3028 3029 chip = kzalloc(sizeof(*chip), GFP_KERNEL); 3030 if (chip == NULL) { 3031 pci_disable_device(pci); 3032 return -ENOMEM; 3033 } 3034 spin_lock_init(&chip->reg_lock); 3035 chip->device_type = device_type; 3036 chip->card = card; 3037 chip->pci = pci; 3038 chip->irq = -1; 3039 3040 /* module parameters */ 3041 chip->buggy_irq = buggy_irq; 3042 chip->buggy_semaphore = buggy_semaphore; 3043 if (xbox) 3044 chip->xbox = 1; 3045 3046 chip->inside_vm = snd_intel8x0_inside_vm(pci); 3047 3048 if (pci->vendor == PCI_VENDOR_ID_INTEL && 3049 pci->device == PCI_DEVICE_ID_INTEL_440MX) 3050 chip->fix_nocache = 1; /* enable workaround */ 3051 3052 if ((err = pci_request_regions(pci, card->shortname)) < 0) { 3053 kfree(chip); 3054 pci_disable_device(pci); 3055 return err; 3056 } 3057 3058 if (device_type == DEVICE_ALI) { 3059 /* ALI5455 has no ac97 region */ 3060 chip->bmaddr = pci_iomap(pci, 0, 0); 3061 goto port_inited; 3062 } 3063 3064 if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) /* ICH4 and Nforce */ 3065 chip->addr = pci_iomap(pci, 2, 0); 3066 else 3067 chip->addr = pci_iomap(pci, 0, 0); 3068 if (!chip->addr) { 3069 snd_printk(KERN_ERR "AC'97 space ioremap problem\n"); 3070 snd_intel8x0_free(chip); 3071 return -EIO; 3072 } 3073 if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) /* ICH4 */ 3074 chip->bmaddr = pci_iomap(pci, 3, 0); 3075 else 3076 chip->bmaddr = pci_iomap(pci, 1, 0); 3077 if (!chip->bmaddr) { 3078 snd_printk(KERN_ERR "Controller space ioremap problem\n"); 3079 snd_intel8x0_free(chip); 3080 return -EIO; 3081 } 3082 3083 port_inited: 3084 chip->bdbars_count = bdbars[device_type]; 3085 3086 /* initialize offsets */ 3087 switch (device_type) { 3088 case DEVICE_NFORCE: 3089 tbl = nforce_regs; 3090 break; 3091 case DEVICE_ALI: 3092 tbl = ali_regs; 3093 break; 3094 default: 3095 tbl = intel_regs; 3096 break; 3097 } 3098 for (i = 0; i < chip->bdbars_count; i++) { 3099 ichdev = &chip->ichd[i]; 3100 ichdev->ichd = i; 3101 ichdev->reg_offset = tbl[i].offset; 3102 ichdev->int_sta_mask = tbl[i].int_sta_mask; 3103 if (device_type == DEVICE_SIS) { 3104 /* SiS 7012 swaps the registers */ 3105 ichdev->roff_sr = ICH_REG_OFF_PICB; 3106 ichdev->roff_picb = ICH_REG_OFF_SR; 3107 } else { 3108 ichdev->roff_sr = ICH_REG_OFF_SR; 3109 ichdev->roff_picb = ICH_REG_OFF_PICB; 3110 } 3111 if (device_type == DEVICE_ALI) 3112 ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10; 3113 /* SIS7012 handles the pcm data in bytes, others are in samples */ 3114 ichdev->pos_shift = (device_type == DEVICE_SIS) ? 0 : 1; 3115 } 3116 3117 /* allocate buffer descriptor lists */ 3118 /* the start of each lists must be aligned to 8 bytes */ 3119 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci), 3120 chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2, 3121 &chip->bdbars) < 0) { 3122 snd_intel8x0_free(chip); 3123 snd_printk(KERN_ERR "intel8x0: cannot allocate buffer descriptors\n"); 3124 return -ENOMEM; 3125 } 3126 /* tables must be aligned to 8 bytes here, but the kernel pages 3127 are much bigger, so we don't care (on i386) */ 3128 /* workaround for 440MX */ 3129 if (chip->fix_nocache) 3130 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1); 3131 int_sta_masks = 0; 3132 for (i = 0; i < chip->bdbars_count; i++) { 3133 ichdev = &chip->ichd[i]; 3134 ichdev->bdbar = ((u32 *)chip->bdbars.area) + 3135 (i * ICH_MAX_FRAGS * 2); 3136 ichdev->bdbar_addr = chip->bdbars.addr + 3137 (i * sizeof(u32) * ICH_MAX_FRAGS * 2); 3138 int_sta_masks |= ichdev->int_sta_mask; 3139 } 3140 chip->int_sta_reg = device_type == DEVICE_ALI ? 3141 ICH_REG_ALI_INTERRUPTSR : ICH_REG_GLOB_STA; 3142 chip->int_sta_mask = int_sta_masks; 3143 3144 pci_set_master(pci); 3145 3146 switch(chip->device_type) { 3147 case DEVICE_INTEL_ICH4: 3148 /* ICH4 can have three codecs */ 3149 chip->max_codecs = 3; 3150 chip->codec_bit = ich_codec_bits; 3151 chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_TRI; 3152 break; 3153 case DEVICE_SIS: 3154 /* recent SIS7012 can have three codecs */ 3155 chip->max_codecs = 3; 3156 chip->codec_bit = sis_codec_bits; 3157 chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_SIS_TRI; 3158 break; 3159 default: 3160 /* others up to two codecs */ 3161 chip->max_codecs = 2; 3162 chip->codec_bit = ich_codec_bits; 3163 chip->codec_ready_bits = ICH_PRI | ICH_SRI; 3164 break; 3165 } 3166 for (i = 0; i < chip->max_codecs; i++) 3167 chip->codec_isr_bits |= chip->codec_bit[i]; 3168 3169 if ((err = snd_intel8x0_chip_init(chip, 1)) < 0) { 3170 snd_intel8x0_free(chip); 3171 return err; 3172 } 3173 3174 /* request irq after initializaing int_sta_mask, etc */ 3175 if (request_irq(pci->irq, snd_intel8x0_interrupt, 3176 IRQF_SHARED, KBUILD_MODNAME, chip)) { 3177 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq); 3178 snd_intel8x0_free(chip); 3179 return -EBUSY; 3180 } 3181 chip->irq = pci->irq; 3182 3183 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) { 3184 snd_intel8x0_free(chip); 3185 return err; 3186 } 3187 3188 snd_card_set_dev(card, &pci->dev); 3189 3190 *r_intel8x0 = chip; 3191 return 0; 3192 } 3193 3194 static struct shortname_table { 3195 unsigned int id; 3196 const char *s; 3197 } shortnames[] __devinitdata = { 3198 { PCI_DEVICE_ID_INTEL_82801AA_5, "Intel 82801AA-ICH" }, 3199 { PCI_DEVICE_ID_INTEL_82801AB_5, "Intel 82901AB-ICH0" }, 3200 { PCI_DEVICE_ID_INTEL_82801BA_4, "Intel 82801BA-ICH2" }, 3201 { PCI_DEVICE_ID_INTEL_440MX, "Intel 440MX" }, 3202 { PCI_DEVICE_ID_INTEL_82801CA_5, "Intel 82801CA-ICH3" }, 3203 { PCI_DEVICE_ID_INTEL_82801DB_5, "Intel 82801DB-ICH4" }, 3204 { PCI_DEVICE_ID_INTEL_82801EB_5, "Intel ICH5" }, 3205 { PCI_DEVICE_ID_INTEL_ESB_5, "Intel 6300ESB" }, 3206 { PCI_DEVICE_ID_INTEL_ICH6_18, "Intel ICH6" }, 3207 { PCI_DEVICE_ID_INTEL_ICH7_20, "Intel ICH7" }, 3208 { PCI_DEVICE_ID_INTEL_ESB2_14, "Intel ESB2" }, 3209 { PCI_DEVICE_ID_SI_7012, "SiS SI7012" }, 3210 { PCI_DEVICE_ID_NVIDIA_MCP1_AUDIO, "NVidia nForce" }, 3211 { PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO, "NVidia nForce2" }, 3212 { PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO, "NVidia nForce3" }, 3213 { PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO, "NVidia CK8S" }, 3214 { PCI_DEVICE_ID_NVIDIA_CK804_AUDIO, "NVidia CK804" }, 3215 { PCI_DEVICE_ID_NVIDIA_CK8_AUDIO, "NVidia CK8" }, 3216 { 0x003a, "NVidia MCP04" }, 3217 { 0x746d, "AMD AMD8111" }, 3218 { 0x7445, "AMD AMD768" }, 3219 { 0x5455, "ALi M5455" }, 3220 { 0, NULL }, 3221 }; 3222 3223 static struct snd_pci_quirk spdif_aclink_defaults[] __devinitdata = { 3224 SND_PCI_QUIRK(0x147b, 0x1c1a, "ASUS KN8", 1), 3225 { } /* end */ 3226 }; 3227 3228 /* look up white/black list for SPDIF over ac-link */ 3229 static int __devinit check_default_spdif_aclink(struct pci_dev *pci) 3230 { 3231 const struct snd_pci_quirk *w; 3232 3233 w = snd_pci_quirk_lookup(pci, spdif_aclink_defaults); 3234 if (w) { 3235 if (w->value) 3236 snd_printdd(KERN_INFO "intel8x0: Using SPDIF over " 3237 "AC-Link for %s\n", w->name); 3238 else 3239 snd_printdd(KERN_INFO "intel8x0: Using integrated " 3240 "SPDIF DMA for %s\n", w->name); 3241 return w->value; 3242 } 3243 return 0; 3244 } 3245 3246 static int __devinit snd_intel8x0_probe(struct pci_dev *pci, 3247 const struct pci_device_id *pci_id) 3248 { 3249 struct snd_card *card; 3250 struct intel8x0 *chip; 3251 int err; 3252 struct shortname_table *name; 3253 3254 err = snd_card_create(index, id, THIS_MODULE, 0, &card); 3255 if (err < 0) 3256 return err; 3257 3258 if (spdif_aclink < 0) 3259 spdif_aclink = check_default_spdif_aclink(pci); 3260 3261 strcpy(card->driver, "ICH"); 3262 if (!spdif_aclink) { 3263 switch (pci_id->driver_data) { 3264 case DEVICE_NFORCE: 3265 strcpy(card->driver, "NFORCE"); 3266 break; 3267 case DEVICE_INTEL_ICH4: 3268 strcpy(card->driver, "ICH4"); 3269 } 3270 } 3271 3272 strcpy(card->shortname, "Intel ICH"); 3273 for (name = shortnames; name->id; name++) { 3274 if (pci->device == name->id) { 3275 strcpy(card->shortname, name->s); 3276 break; 3277 } 3278 } 3279 3280 if (buggy_irq < 0) { 3281 /* some Nforce[2] and ICH boards have problems with IRQ handling. 3282 * Needs to return IRQ_HANDLED for unknown irqs. 3283 */ 3284 if (pci_id->driver_data == DEVICE_NFORCE) 3285 buggy_irq = 1; 3286 else 3287 buggy_irq = 0; 3288 } 3289 3290 if ((err = snd_intel8x0_create(card, pci, pci_id->driver_data, 3291 &chip)) < 0) { 3292 snd_card_free(card); 3293 return err; 3294 } 3295 card->private_data = chip; 3296 3297 if ((err = snd_intel8x0_mixer(chip, ac97_clock, ac97_quirk)) < 0) { 3298 snd_card_free(card); 3299 return err; 3300 } 3301 if ((err = snd_intel8x0_pcm(chip)) < 0) { 3302 snd_card_free(card); 3303 return err; 3304 } 3305 3306 snd_intel8x0_proc_init(chip); 3307 3308 snprintf(card->longname, sizeof(card->longname), 3309 "%s with %s at irq %i", card->shortname, 3310 snd_ac97_get_short_name(chip->ac97[0]), chip->irq); 3311 3312 if (ac97_clock == 0 || ac97_clock == 1) { 3313 if (ac97_clock == 0) { 3314 if (intel8x0_in_clock_list(chip) == 0) 3315 intel8x0_measure_ac97_clock(chip); 3316 } else { 3317 intel8x0_measure_ac97_clock(chip); 3318 } 3319 } 3320 3321 if ((err = snd_card_register(card)) < 0) { 3322 snd_card_free(card); 3323 return err; 3324 } 3325 pci_set_drvdata(pci, card); 3326 return 0; 3327 } 3328 3329 static void __devexit snd_intel8x0_remove(struct pci_dev *pci) 3330 { 3331 snd_card_free(pci_get_drvdata(pci)); 3332 pci_set_drvdata(pci, NULL); 3333 } 3334 3335 static struct pci_driver driver = { 3336 .name = KBUILD_MODNAME, 3337 .id_table = snd_intel8x0_ids, 3338 .probe = snd_intel8x0_probe, 3339 .remove = __devexit_p(snd_intel8x0_remove), 3340 #ifdef CONFIG_PM 3341 .suspend = intel8x0_suspend, 3342 .resume = intel8x0_resume, 3343 #endif 3344 }; 3345 3346 3347 static int __init alsa_card_intel8x0_init(void) 3348 { 3349 return pci_register_driver(&driver); 3350 } 3351 3352 static void __exit alsa_card_intel8x0_exit(void) 3353 { 3354 pci_unregister_driver(&driver); 3355 } 3356 3357 module_init(alsa_card_intel8x0_init) 3358 module_exit(alsa_card_intel8x0_exit) 3359