1 /* 2 * 3 * patch_hdmi.c - routines for HDMI/DisplayPort codecs 4 * 5 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved. 6 * Copyright (c) 2006 ATI Technologies Inc. 7 * Copyright (c) 2008 NVIDIA Corp. All rights reserved. 8 * Copyright (c) 2008 Wei Ni <wni@nvidia.com> 9 * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi> 10 * 11 * Authors: 12 * Wu Fengguang <wfg@linux.intel.com> 13 * 14 * Maintained by: 15 * Wu Fengguang <wfg@linux.intel.com> 16 * 17 * This program is free software; you can redistribute it and/or modify it 18 * under the terms of the GNU General Public License as published by the Free 19 * Software Foundation; either version 2 of the License, or (at your option) 20 * any later version. 21 * 22 * This program is distributed in the hope that it will be useful, but 23 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 24 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 25 * for more details. 26 * 27 * You should have received a copy of the GNU General Public License 28 * along with this program; if not, write to the Free Software Foundation, 29 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 30 */ 31 32 #include <linux/init.h> 33 #include <linux/delay.h> 34 #include <linux/slab.h> 35 #include <linux/module.h> 36 #include <linux/pm_runtime.h> 37 #include <sound/core.h> 38 #include <sound/jack.h> 39 #include <sound/asoundef.h> 40 #include <sound/tlv.h> 41 #include <sound/hdaudio.h> 42 #include <sound/hda_i915.h> 43 #include <sound/hda_chmap.h> 44 #include "hda_codec.h" 45 #include "hda_local.h" 46 #include "hda_jack.h" 47 48 static bool static_hdmi_pcm; 49 module_param(static_hdmi_pcm, bool, 0644); 50 MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info"); 51 52 #define is_haswell(codec) ((codec)->core.vendor_id == 0x80862807) 53 #define is_broadwell(codec) ((codec)->core.vendor_id == 0x80862808) 54 #define is_skylake(codec) ((codec)->core.vendor_id == 0x80862809) 55 #define is_broxton(codec) ((codec)->core.vendor_id == 0x8086280a) 56 #define is_kabylake(codec) ((codec)->core.vendor_id == 0x8086280b) 57 #define is_geminilake(codec) (((codec)->core.vendor_id == 0x8086280d) || \ 58 ((codec)->core.vendor_id == 0x80862800)) 59 #define is_cannonlake(codec) ((codec)->core.vendor_id == 0x8086280c) 60 #define is_haswell_plus(codec) (is_haswell(codec) || is_broadwell(codec) \ 61 || is_skylake(codec) || is_broxton(codec) \ 62 || is_kabylake(codec)) || is_geminilake(codec) \ 63 || is_cannonlake(codec) 64 #define is_valleyview(codec) ((codec)->core.vendor_id == 0x80862882) 65 #define is_cherryview(codec) ((codec)->core.vendor_id == 0x80862883) 66 #define is_valleyview_plus(codec) (is_valleyview(codec) || is_cherryview(codec)) 67 68 struct hdmi_spec_per_cvt { 69 hda_nid_t cvt_nid; 70 int assigned; 71 unsigned int channels_min; 72 unsigned int channels_max; 73 u32 rates; 74 u64 formats; 75 unsigned int maxbps; 76 }; 77 78 /* max. connections to a widget */ 79 #define HDA_MAX_CONNECTIONS 32 80 81 struct hdmi_spec_per_pin { 82 hda_nid_t pin_nid; 83 int dev_id; 84 /* pin idx, different device entries on the same pin use the same idx */ 85 int pin_nid_idx; 86 int num_mux_nids; 87 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS]; 88 int mux_idx; 89 hda_nid_t cvt_nid; 90 91 struct hda_codec *codec; 92 struct hdmi_eld sink_eld; 93 struct mutex lock; 94 struct delayed_work work; 95 struct hdmi_pcm *pcm; /* pointer to spec->pcm_rec[n] dynamically*/ 96 int pcm_idx; /* which pcm is attached. -1 means no pcm is attached */ 97 int repoll_count; 98 bool setup; /* the stream has been set up by prepare callback */ 99 int channels; /* current number of channels */ 100 bool non_pcm; 101 bool chmap_set; /* channel-map override by ALSA API? */ 102 unsigned char chmap[8]; /* ALSA API channel-map */ 103 #ifdef CONFIG_SND_PROC_FS 104 struct snd_info_entry *proc_entry; 105 #endif 106 }; 107 108 /* operations used by generic code that can be overridden by patches */ 109 struct hdmi_ops { 110 int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid, 111 unsigned char *buf, int *eld_size); 112 113 void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid, 114 int ca, int active_channels, int conn_type); 115 116 /* enable/disable HBR (HD passthrough) */ 117 int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, bool hbr); 118 119 int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid, 120 hda_nid_t pin_nid, u32 stream_tag, int format); 121 122 void (*pin_cvt_fixup)(struct hda_codec *codec, 123 struct hdmi_spec_per_pin *per_pin, 124 hda_nid_t cvt_nid); 125 }; 126 127 struct hdmi_pcm { 128 struct hda_pcm *pcm; 129 struct snd_jack *jack; 130 struct snd_kcontrol *eld_ctl; 131 }; 132 133 struct hdmi_spec { 134 int num_cvts; 135 struct snd_array cvts; /* struct hdmi_spec_per_cvt */ 136 hda_nid_t cvt_nids[4]; /* only for haswell fix */ 137 138 /* 139 * num_pins is the number of virtual pins 140 * for example, there are 3 pins, and each pin 141 * has 4 device entries, then the num_pins is 12 142 */ 143 int num_pins; 144 /* 145 * num_nids is the number of real pins 146 * In the above example, num_nids is 3 147 */ 148 int num_nids; 149 /* 150 * dev_num is the number of device entries 151 * on each pin. 152 * In the above example, dev_num is 4 153 */ 154 int dev_num; 155 struct snd_array pins; /* struct hdmi_spec_per_pin */ 156 struct hdmi_pcm pcm_rec[16]; 157 struct mutex pcm_lock; 158 /* pcm_bitmap means which pcms have been assigned to pins*/ 159 unsigned long pcm_bitmap; 160 int pcm_used; /* counter of pcm_rec[] */ 161 /* bitmap shows whether the pcm is opened in user space 162 * bit 0 means the first playback PCM (PCM3); 163 * bit 1 means the second playback PCM, and so on. 164 */ 165 unsigned long pcm_in_use; 166 167 struct hdmi_eld temp_eld; 168 struct hdmi_ops ops; 169 170 bool dyn_pin_out; 171 bool dyn_pcm_assign; 172 /* 173 * Non-generic VIA/NVIDIA specific 174 */ 175 struct hda_multi_out multiout; 176 struct hda_pcm_stream pcm_playback; 177 178 /* i915/powerwell (Haswell+/Valleyview+) specific */ 179 bool use_acomp_notifier; /* use i915 eld_notify callback for hotplug */ 180 struct i915_audio_component_audio_ops i915_audio_ops; 181 182 struct hdac_chmap chmap; 183 hda_nid_t vendor_nid; 184 }; 185 186 #ifdef CONFIG_SND_HDA_I915 187 static inline bool codec_has_acomp(struct hda_codec *codec) 188 { 189 struct hdmi_spec *spec = codec->spec; 190 return spec->use_acomp_notifier; 191 } 192 #else 193 #define codec_has_acomp(codec) false 194 #endif 195 196 struct hdmi_audio_infoframe { 197 u8 type; /* 0x84 */ 198 u8 ver; /* 0x01 */ 199 u8 len; /* 0x0a */ 200 201 u8 checksum; 202 203 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */ 204 u8 SS01_SF24; 205 u8 CXT04; 206 u8 CA; 207 u8 LFEPBL01_LSV36_DM_INH7; 208 }; 209 210 struct dp_audio_infoframe { 211 u8 type; /* 0x84 */ 212 u8 len; /* 0x1b */ 213 u8 ver; /* 0x11 << 2 */ 214 215 u8 CC02_CT47; /* match with HDMI infoframe from this on */ 216 u8 SS01_SF24; 217 u8 CXT04; 218 u8 CA; 219 u8 LFEPBL01_LSV36_DM_INH7; 220 }; 221 222 union audio_infoframe { 223 struct hdmi_audio_infoframe hdmi; 224 struct dp_audio_infoframe dp; 225 u8 bytes[0]; 226 }; 227 228 /* 229 * HDMI routines 230 */ 231 232 #define get_pin(spec, idx) \ 233 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx)) 234 #define get_cvt(spec, idx) \ 235 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx)) 236 /* obtain hdmi_pcm object assigned to idx */ 237 #define get_hdmi_pcm(spec, idx) (&(spec)->pcm_rec[idx]) 238 /* obtain hda_pcm object assigned to idx */ 239 #define get_pcm_rec(spec, idx) (get_hdmi_pcm(spec, idx)->pcm) 240 241 static int pin_id_to_pin_index(struct hda_codec *codec, 242 hda_nid_t pin_nid, int dev_id) 243 { 244 struct hdmi_spec *spec = codec->spec; 245 int pin_idx; 246 struct hdmi_spec_per_pin *per_pin; 247 248 /* 249 * (dev_id == -1) means it is NON-MST pin 250 * return the first virtual pin on this port 251 */ 252 if (dev_id == -1) 253 dev_id = 0; 254 255 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 256 per_pin = get_pin(spec, pin_idx); 257 if ((per_pin->pin_nid == pin_nid) && 258 (per_pin->dev_id == dev_id)) 259 return pin_idx; 260 } 261 262 codec_warn(codec, "HDMI: pin nid %d not registered\n", pin_nid); 263 return -EINVAL; 264 } 265 266 static int hinfo_to_pcm_index(struct hda_codec *codec, 267 struct hda_pcm_stream *hinfo) 268 { 269 struct hdmi_spec *spec = codec->spec; 270 int pcm_idx; 271 272 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) 273 if (get_pcm_rec(spec, pcm_idx)->stream == hinfo) 274 return pcm_idx; 275 276 codec_warn(codec, "HDMI: hinfo %p not registered\n", hinfo); 277 return -EINVAL; 278 } 279 280 static int hinfo_to_pin_index(struct hda_codec *codec, 281 struct hda_pcm_stream *hinfo) 282 { 283 struct hdmi_spec *spec = codec->spec; 284 struct hdmi_spec_per_pin *per_pin; 285 int pin_idx; 286 287 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 288 per_pin = get_pin(spec, pin_idx); 289 if (per_pin->pcm && 290 per_pin->pcm->pcm->stream == hinfo) 291 return pin_idx; 292 } 293 294 codec_dbg(codec, "HDMI: hinfo %p not registered\n", hinfo); 295 return -EINVAL; 296 } 297 298 static struct hdmi_spec_per_pin *pcm_idx_to_pin(struct hdmi_spec *spec, 299 int pcm_idx) 300 { 301 int i; 302 struct hdmi_spec_per_pin *per_pin; 303 304 for (i = 0; i < spec->num_pins; i++) { 305 per_pin = get_pin(spec, i); 306 if (per_pin->pcm_idx == pcm_idx) 307 return per_pin; 308 } 309 return NULL; 310 } 311 312 static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid) 313 { 314 struct hdmi_spec *spec = codec->spec; 315 int cvt_idx; 316 317 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) 318 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid) 319 return cvt_idx; 320 321 codec_warn(codec, "HDMI: cvt nid %d not registered\n", cvt_nid); 322 return -EINVAL; 323 } 324 325 static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol, 326 struct snd_ctl_elem_info *uinfo) 327 { 328 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 329 struct hdmi_spec *spec = codec->spec; 330 struct hdmi_spec_per_pin *per_pin; 331 struct hdmi_eld *eld; 332 int pcm_idx; 333 334 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; 335 336 pcm_idx = kcontrol->private_value; 337 mutex_lock(&spec->pcm_lock); 338 per_pin = pcm_idx_to_pin(spec, pcm_idx); 339 if (!per_pin) { 340 /* no pin is bound to the pcm */ 341 uinfo->count = 0; 342 mutex_unlock(&spec->pcm_lock); 343 return 0; 344 } 345 eld = &per_pin->sink_eld; 346 uinfo->count = eld->eld_valid ? eld->eld_size : 0; 347 mutex_unlock(&spec->pcm_lock); 348 349 return 0; 350 } 351 352 static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol, 353 struct snd_ctl_elem_value *ucontrol) 354 { 355 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 356 struct hdmi_spec *spec = codec->spec; 357 struct hdmi_spec_per_pin *per_pin; 358 struct hdmi_eld *eld; 359 int pcm_idx; 360 361 pcm_idx = kcontrol->private_value; 362 mutex_lock(&spec->pcm_lock); 363 per_pin = pcm_idx_to_pin(spec, pcm_idx); 364 if (!per_pin) { 365 /* no pin is bound to the pcm */ 366 memset(ucontrol->value.bytes.data, 0, 367 ARRAY_SIZE(ucontrol->value.bytes.data)); 368 mutex_unlock(&spec->pcm_lock); 369 return 0; 370 } 371 eld = &per_pin->sink_eld; 372 373 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data) || 374 eld->eld_size > ELD_MAX_SIZE) { 375 mutex_unlock(&spec->pcm_lock); 376 snd_BUG(); 377 return -EINVAL; 378 } 379 380 memset(ucontrol->value.bytes.data, 0, 381 ARRAY_SIZE(ucontrol->value.bytes.data)); 382 if (eld->eld_valid) 383 memcpy(ucontrol->value.bytes.data, eld->eld_buffer, 384 eld->eld_size); 385 mutex_unlock(&spec->pcm_lock); 386 387 return 0; 388 } 389 390 static const struct snd_kcontrol_new eld_bytes_ctl = { 391 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, 392 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 393 .name = "ELD", 394 .info = hdmi_eld_ctl_info, 395 .get = hdmi_eld_ctl_get, 396 }; 397 398 static int hdmi_create_eld_ctl(struct hda_codec *codec, int pcm_idx, 399 int device) 400 { 401 struct snd_kcontrol *kctl; 402 struct hdmi_spec *spec = codec->spec; 403 int err; 404 405 kctl = snd_ctl_new1(&eld_bytes_ctl, codec); 406 if (!kctl) 407 return -ENOMEM; 408 kctl->private_value = pcm_idx; 409 kctl->id.device = device; 410 411 /* no pin nid is associated with the kctl now 412 * tbd: associate pin nid to eld ctl later 413 */ 414 err = snd_hda_ctl_add(codec, 0, kctl); 415 if (err < 0) 416 return err; 417 418 get_hdmi_pcm(spec, pcm_idx)->eld_ctl = kctl; 419 return 0; 420 } 421 422 #ifdef BE_PARANOID 423 static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid, 424 int *packet_index, int *byte_index) 425 { 426 int val; 427 428 val = snd_hda_codec_read(codec, pin_nid, 0, 429 AC_VERB_GET_HDMI_DIP_INDEX, 0); 430 431 *packet_index = val >> 5; 432 *byte_index = val & 0x1f; 433 } 434 #endif 435 436 static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid, 437 int packet_index, int byte_index) 438 { 439 int val; 440 441 val = (packet_index << 5) | (byte_index & 0x1f); 442 443 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val); 444 } 445 446 static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid, 447 unsigned char val) 448 { 449 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val); 450 } 451 452 static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid) 453 { 454 struct hdmi_spec *spec = codec->spec; 455 int pin_out; 456 457 /* Unmute */ 458 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP) 459 snd_hda_codec_write(codec, pin_nid, 0, 460 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE); 461 462 if (spec->dyn_pin_out) 463 /* Disable pin out until stream is active */ 464 pin_out = 0; 465 else 466 /* Enable pin out: some machines with GM965 gets broken output 467 * when the pin is disabled or changed while using with HDMI 468 */ 469 pin_out = PIN_OUT; 470 471 snd_hda_codec_write(codec, pin_nid, 0, 472 AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out); 473 } 474 475 /* 476 * ELD proc files 477 */ 478 479 #ifdef CONFIG_SND_PROC_FS 480 static void print_eld_info(struct snd_info_entry *entry, 481 struct snd_info_buffer *buffer) 482 { 483 struct hdmi_spec_per_pin *per_pin = entry->private_data; 484 485 mutex_lock(&per_pin->lock); 486 snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer); 487 mutex_unlock(&per_pin->lock); 488 } 489 490 static void write_eld_info(struct snd_info_entry *entry, 491 struct snd_info_buffer *buffer) 492 { 493 struct hdmi_spec_per_pin *per_pin = entry->private_data; 494 495 mutex_lock(&per_pin->lock); 496 snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer); 497 mutex_unlock(&per_pin->lock); 498 } 499 500 static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index) 501 { 502 char name[32]; 503 struct hda_codec *codec = per_pin->codec; 504 struct snd_info_entry *entry; 505 int err; 506 507 snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index); 508 err = snd_card_proc_new(codec->card, name, &entry); 509 if (err < 0) 510 return err; 511 512 snd_info_set_text_ops(entry, per_pin, print_eld_info); 513 entry->c.text.write = write_eld_info; 514 entry->mode |= 0200; 515 per_pin->proc_entry = entry; 516 517 return 0; 518 } 519 520 static void eld_proc_free(struct hdmi_spec_per_pin *per_pin) 521 { 522 if (!per_pin->codec->bus->shutdown) { 523 snd_info_free_entry(per_pin->proc_entry); 524 per_pin->proc_entry = NULL; 525 } 526 } 527 #else 528 static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin, 529 int index) 530 { 531 return 0; 532 } 533 static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin) 534 { 535 } 536 #endif 537 538 /* 539 * Audio InfoFrame routines 540 */ 541 542 /* 543 * Enable Audio InfoFrame Transmission 544 */ 545 static void hdmi_start_infoframe_trans(struct hda_codec *codec, 546 hda_nid_t pin_nid) 547 { 548 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 549 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT, 550 AC_DIPXMIT_BEST); 551 } 552 553 /* 554 * Disable Audio InfoFrame Transmission 555 */ 556 static void hdmi_stop_infoframe_trans(struct hda_codec *codec, 557 hda_nid_t pin_nid) 558 { 559 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 560 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT, 561 AC_DIPXMIT_DISABLE); 562 } 563 564 static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid) 565 { 566 #ifdef CONFIG_SND_DEBUG_VERBOSE 567 int i; 568 int size; 569 570 size = snd_hdmi_get_eld_size(codec, pin_nid); 571 codec_dbg(codec, "HDMI: ELD buf size is %d\n", size); 572 573 for (i = 0; i < 8; i++) { 574 size = snd_hda_codec_read(codec, pin_nid, 0, 575 AC_VERB_GET_HDMI_DIP_SIZE, i); 576 codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size); 577 } 578 #endif 579 } 580 581 static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid) 582 { 583 #ifdef BE_PARANOID 584 int i, j; 585 int size; 586 int pi, bi; 587 for (i = 0; i < 8; i++) { 588 size = snd_hda_codec_read(codec, pin_nid, 0, 589 AC_VERB_GET_HDMI_DIP_SIZE, i); 590 if (size == 0) 591 continue; 592 593 hdmi_set_dip_index(codec, pin_nid, i, 0x0); 594 for (j = 1; j < 1000; j++) { 595 hdmi_write_dip_byte(codec, pin_nid, 0x0); 596 hdmi_get_dip_index(codec, pin_nid, &pi, &bi); 597 if (pi != i) 598 codec_dbg(codec, "dip index %d: %d != %d\n", 599 bi, pi, i); 600 if (bi == 0) /* byte index wrapped around */ 601 break; 602 } 603 codec_dbg(codec, 604 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n", 605 i, size, j); 606 } 607 #endif 608 } 609 610 static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai) 611 { 612 u8 *bytes = (u8 *)hdmi_ai; 613 u8 sum = 0; 614 int i; 615 616 hdmi_ai->checksum = 0; 617 618 for (i = 0; i < sizeof(*hdmi_ai); i++) 619 sum += bytes[i]; 620 621 hdmi_ai->checksum = -sum; 622 } 623 624 static void hdmi_fill_audio_infoframe(struct hda_codec *codec, 625 hda_nid_t pin_nid, 626 u8 *dip, int size) 627 { 628 int i; 629 630 hdmi_debug_dip_size(codec, pin_nid); 631 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */ 632 633 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 634 for (i = 0; i < size; i++) 635 hdmi_write_dip_byte(codec, pin_nid, dip[i]); 636 } 637 638 static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid, 639 u8 *dip, int size) 640 { 641 u8 val; 642 int i; 643 644 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0) 645 != AC_DIPXMIT_BEST) 646 return false; 647 648 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 649 for (i = 0; i < size; i++) { 650 val = snd_hda_codec_read(codec, pin_nid, 0, 651 AC_VERB_GET_HDMI_DIP_DATA, 0); 652 if (val != dip[i]) 653 return false; 654 } 655 656 return true; 657 } 658 659 static void hdmi_pin_setup_infoframe(struct hda_codec *codec, 660 hda_nid_t pin_nid, 661 int ca, int active_channels, 662 int conn_type) 663 { 664 union audio_infoframe ai; 665 666 memset(&ai, 0, sizeof(ai)); 667 if (conn_type == 0) { /* HDMI */ 668 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi; 669 670 hdmi_ai->type = 0x84; 671 hdmi_ai->ver = 0x01; 672 hdmi_ai->len = 0x0a; 673 hdmi_ai->CC02_CT47 = active_channels - 1; 674 hdmi_ai->CA = ca; 675 hdmi_checksum_audio_infoframe(hdmi_ai); 676 } else if (conn_type == 1) { /* DisplayPort */ 677 struct dp_audio_infoframe *dp_ai = &ai.dp; 678 679 dp_ai->type = 0x84; 680 dp_ai->len = 0x1b; 681 dp_ai->ver = 0x11 << 2; 682 dp_ai->CC02_CT47 = active_channels - 1; 683 dp_ai->CA = ca; 684 } else { 685 codec_dbg(codec, "HDMI: unknown connection type at pin %d\n", 686 pin_nid); 687 return; 688 } 689 690 /* 691 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or 692 * sizeof(*dp_ai) to avoid partial match/update problems when 693 * the user switches between HDMI/DP monitors. 694 */ 695 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes, 696 sizeof(ai))) { 697 codec_dbg(codec, 698 "hdmi_pin_setup_infoframe: pin=%d channels=%d ca=0x%02x\n", 699 pin_nid, 700 active_channels, ca); 701 hdmi_stop_infoframe_trans(codec, pin_nid); 702 hdmi_fill_audio_infoframe(codec, pin_nid, 703 ai.bytes, sizeof(ai)); 704 hdmi_start_infoframe_trans(codec, pin_nid); 705 } 706 } 707 708 static void hdmi_setup_audio_infoframe(struct hda_codec *codec, 709 struct hdmi_spec_per_pin *per_pin, 710 bool non_pcm) 711 { 712 struct hdmi_spec *spec = codec->spec; 713 struct hdac_chmap *chmap = &spec->chmap; 714 hda_nid_t pin_nid = per_pin->pin_nid; 715 int channels = per_pin->channels; 716 int active_channels; 717 struct hdmi_eld *eld; 718 int ca; 719 720 if (!channels) 721 return; 722 723 /* some HW (e.g. HSW+) needs reprogramming the amp at each time */ 724 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP) 725 snd_hda_codec_write(codec, pin_nid, 0, 726 AC_VERB_SET_AMP_GAIN_MUTE, 727 AMP_OUT_UNMUTE); 728 729 eld = &per_pin->sink_eld; 730 731 ca = snd_hdac_channel_allocation(&codec->core, 732 eld->info.spk_alloc, channels, 733 per_pin->chmap_set, non_pcm, per_pin->chmap); 734 735 active_channels = snd_hdac_get_active_channels(ca); 736 737 chmap->ops.set_channel_count(&codec->core, per_pin->cvt_nid, 738 active_channels); 739 740 /* 741 * always configure channel mapping, it may have been changed by the 742 * user in the meantime 743 */ 744 snd_hdac_setup_channel_mapping(&spec->chmap, 745 pin_nid, non_pcm, ca, channels, 746 per_pin->chmap, per_pin->chmap_set); 747 748 spec->ops.pin_setup_infoframe(codec, pin_nid, ca, active_channels, 749 eld->info.conn_type); 750 751 per_pin->non_pcm = non_pcm; 752 } 753 754 /* 755 * Unsolicited events 756 */ 757 758 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll); 759 760 static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid, 761 int dev_id) 762 { 763 struct hdmi_spec *spec = codec->spec; 764 int pin_idx = pin_id_to_pin_index(codec, nid, dev_id); 765 766 if (pin_idx < 0) 767 return; 768 mutex_lock(&spec->pcm_lock); 769 if (hdmi_present_sense(get_pin(spec, pin_idx), 1)) 770 snd_hda_jack_report_sync(codec); 771 mutex_unlock(&spec->pcm_lock); 772 } 773 774 static void jack_callback(struct hda_codec *codec, 775 struct hda_jack_callback *jack) 776 { 777 /* hda_jack don't support DP MST */ 778 check_presence_and_report(codec, jack->nid, 0); 779 } 780 781 static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res) 782 { 783 int tag = res >> AC_UNSOL_RES_TAG_SHIFT; 784 struct hda_jack_tbl *jack; 785 int dev_entry = (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT; 786 787 /* 788 * assume DP MST uses dyn_pcm_assign and acomp and 789 * never comes here 790 * if DP MST supports unsol event, below code need 791 * consider dev_entry 792 */ 793 jack = snd_hda_jack_tbl_get_from_tag(codec, tag); 794 if (!jack) 795 return; 796 jack->jack_dirty = 1; 797 798 codec_dbg(codec, 799 "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n", 800 codec->addr, jack->nid, dev_entry, !!(res & AC_UNSOL_RES_IA), 801 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV)); 802 803 /* hda_jack don't support DP MST */ 804 check_presence_and_report(codec, jack->nid, 0); 805 } 806 807 static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res) 808 { 809 int tag = res >> AC_UNSOL_RES_TAG_SHIFT; 810 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT; 811 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE); 812 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY); 813 814 codec_info(codec, 815 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n", 816 codec->addr, 817 tag, 818 subtag, 819 cp_state, 820 cp_ready); 821 822 /* TODO */ 823 if (cp_state) 824 ; 825 if (cp_ready) 826 ; 827 } 828 829 830 static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res) 831 { 832 int tag = res >> AC_UNSOL_RES_TAG_SHIFT; 833 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT; 834 835 if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) { 836 codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag); 837 return; 838 } 839 840 if (subtag == 0) 841 hdmi_intrinsic_event(codec, res); 842 else 843 hdmi_non_intrinsic_event(codec, res); 844 } 845 846 static void haswell_verify_D0(struct hda_codec *codec, 847 hda_nid_t cvt_nid, hda_nid_t nid) 848 { 849 int pwr; 850 851 /* For Haswell, the converter 1/2 may keep in D3 state after bootup, 852 * thus pins could only choose converter 0 for use. Make sure the 853 * converters are in correct power state */ 854 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0)) 855 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0); 856 857 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) { 858 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE, 859 AC_PWRST_D0); 860 msleep(40); 861 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0); 862 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT; 863 codec_dbg(codec, "Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr); 864 } 865 } 866 867 /* 868 * Callbacks 869 */ 870 871 /* HBR should be Non-PCM, 8 channels */ 872 #define is_hbr_format(format) \ 873 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7) 874 875 static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid, 876 bool hbr) 877 { 878 int pinctl, new_pinctl; 879 880 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) { 881 pinctl = snd_hda_codec_read(codec, pin_nid, 0, 882 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 883 884 if (pinctl < 0) 885 return hbr ? -EINVAL : 0; 886 887 new_pinctl = pinctl & ~AC_PINCTL_EPT; 888 if (hbr) 889 new_pinctl |= AC_PINCTL_EPT_HBR; 890 else 891 new_pinctl |= AC_PINCTL_EPT_NATIVE; 892 893 codec_dbg(codec, 894 "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n", 895 pin_nid, 896 pinctl == new_pinctl ? "" : "new-", 897 new_pinctl); 898 899 if (pinctl != new_pinctl) 900 snd_hda_codec_write(codec, pin_nid, 0, 901 AC_VERB_SET_PIN_WIDGET_CONTROL, 902 new_pinctl); 903 } else if (hbr) 904 return -EINVAL; 905 906 return 0; 907 } 908 909 static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, 910 hda_nid_t pin_nid, u32 stream_tag, int format) 911 { 912 struct hdmi_spec *spec = codec->spec; 913 unsigned int param; 914 int err; 915 916 err = spec->ops.pin_hbr_setup(codec, pin_nid, is_hbr_format(format)); 917 918 if (err) { 919 codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n"); 920 return err; 921 } 922 923 if (is_haswell_plus(codec)) { 924 925 /* 926 * on recent platforms IEC Coding Type is required for HBR 927 * support, read current Digital Converter settings and set 928 * ICT bitfield if needed. 929 */ 930 param = snd_hda_codec_read(codec, cvt_nid, 0, 931 AC_VERB_GET_DIGI_CONVERT_1, 0); 932 933 param = (param >> 16) & ~(AC_DIG3_ICT); 934 935 /* on recent platforms ICT mode is required for HBR support */ 936 if (is_hbr_format(format)) 937 param |= 0x1; 938 939 snd_hda_codec_write(codec, cvt_nid, 0, 940 AC_VERB_SET_DIGI_CONVERT_3, param); 941 } 942 943 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format); 944 return 0; 945 } 946 947 /* Try to find an available converter 948 * If pin_idx is less then zero, just try to find an available converter. 949 * Otherwise, try to find an available converter and get the cvt mux index 950 * of the pin. 951 */ 952 static int hdmi_choose_cvt(struct hda_codec *codec, 953 int pin_idx, int *cvt_id) 954 { 955 struct hdmi_spec *spec = codec->spec; 956 struct hdmi_spec_per_pin *per_pin; 957 struct hdmi_spec_per_cvt *per_cvt = NULL; 958 int cvt_idx, mux_idx = 0; 959 960 /* pin_idx < 0 means no pin will be bound to the converter */ 961 if (pin_idx < 0) 962 per_pin = NULL; 963 else 964 per_pin = get_pin(spec, pin_idx); 965 966 /* Dynamically assign converter to stream */ 967 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { 968 per_cvt = get_cvt(spec, cvt_idx); 969 970 /* Must not already be assigned */ 971 if (per_cvt->assigned) 972 continue; 973 if (per_pin == NULL) 974 break; 975 /* Must be in pin's mux's list of converters */ 976 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++) 977 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid) 978 break; 979 /* Not in mux list */ 980 if (mux_idx == per_pin->num_mux_nids) 981 continue; 982 break; 983 } 984 985 /* No free converters */ 986 if (cvt_idx == spec->num_cvts) 987 return -EBUSY; 988 989 if (per_pin != NULL) 990 per_pin->mux_idx = mux_idx; 991 992 if (cvt_id) 993 *cvt_id = cvt_idx; 994 995 return 0; 996 } 997 998 /* Assure the pin select the right convetor */ 999 static void intel_verify_pin_cvt_connect(struct hda_codec *codec, 1000 struct hdmi_spec_per_pin *per_pin) 1001 { 1002 hda_nid_t pin_nid = per_pin->pin_nid; 1003 int mux_idx, curr; 1004 1005 mux_idx = per_pin->mux_idx; 1006 curr = snd_hda_codec_read(codec, pin_nid, 0, 1007 AC_VERB_GET_CONNECT_SEL, 0); 1008 if (curr != mux_idx) 1009 snd_hda_codec_write_cache(codec, pin_nid, 0, 1010 AC_VERB_SET_CONNECT_SEL, 1011 mux_idx); 1012 } 1013 1014 /* get the mux index for the converter of the pins 1015 * converter's mux index is the same for all pins on Intel platform 1016 */ 1017 static int intel_cvt_id_to_mux_idx(struct hdmi_spec *spec, 1018 hda_nid_t cvt_nid) 1019 { 1020 int i; 1021 1022 for (i = 0; i < spec->num_cvts; i++) 1023 if (spec->cvt_nids[i] == cvt_nid) 1024 return i; 1025 return -EINVAL; 1026 } 1027 1028 /* Intel HDMI workaround to fix audio routing issue: 1029 * For some Intel display codecs, pins share the same connection list. 1030 * So a conveter can be selected by multiple pins and playback on any of these 1031 * pins will generate sound on the external display, because audio flows from 1032 * the same converter to the display pipeline. Also muting one pin may make 1033 * other pins have no sound output. 1034 * So this function assures that an assigned converter for a pin is not selected 1035 * by any other pins. 1036 */ 1037 static void intel_not_share_assigned_cvt(struct hda_codec *codec, 1038 hda_nid_t pin_nid, 1039 int dev_id, int mux_idx) 1040 { 1041 struct hdmi_spec *spec = codec->spec; 1042 hda_nid_t nid; 1043 int cvt_idx, curr; 1044 struct hdmi_spec_per_cvt *per_cvt; 1045 struct hdmi_spec_per_pin *per_pin; 1046 int pin_idx; 1047 1048 /* configure the pins connections */ 1049 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 1050 int dev_id_saved; 1051 int dev_num; 1052 1053 per_pin = get_pin(spec, pin_idx); 1054 /* 1055 * pin not connected to monitor 1056 * no need to operate on it 1057 */ 1058 if (!per_pin->pcm) 1059 continue; 1060 1061 if ((per_pin->pin_nid == pin_nid) && 1062 (per_pin->dev_id == dev_id)) 1063 continue; 1064 1065 /* 1066 * if per_pin->dev_id >= dev_num, 1067 * snd_hda_get_dev_select() will fail, 1068 * and the following operation is unpredictable. 1069 * So skip this situation. 1070 */ 1071 dev_num = snd_hda_get_num_devices(codec, per_pin->pin_nid) + 1; 1072 if (per_pin->dev_id >= dev_num) 1073 continue; 1074 1075 nid = per_pin->pin_nid; 1076 1077 /* 1078 * Calling this function should not impact 1079 * on the device entry selection 1080 * So let's save the dev id for each pin, 1081 * and restore it when return 1082 */ 1083 dev_id_saved = snd_hda_get_dev_select(codec, nid); 1084 snd_hda_set_dev_select(codec, nid, per_pin->dev_id); 1085 curr = snd_hda_codec_read(codec, nid, 0, 1086 AC_VERB_GET_CONNECT_SEL, 0); 1087 if (curr != mux_idx) { 1088 snd_hda_set_dev_select(codec, nid, dev_id_saved); 1089 continue; 1090 } 1091 1092 1093 /* choose an unassigned converter. The conveters in the 1094 * connection list are in the same order as in the codec. 1095 */ 1096 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { 1097 per_cvt = get_cvt(spec, cvt_idx); 1098 if (!per_cvt->assigned) { 1099 codec_dbg(codec, 1100 "choose cvt %d for pin nid %d\n", 1101 cvt_idx, nid); 1102 snd_hda_codec_write_cache(codec, nid, 0, 1103 AC_VERB_SET_CONNECT_SEL, 1104 cvt_idx); 1105 break; 1106 } 1107 } 1108 snd_hda_set_dev_select(codec, nid, dev_id_saved); 1109 } 1110 } 1111 1112 /* A wrapper of intel_not_share_asigned_cvt() */ 1113 static void intel_not_share_assigned_cvt_nid(struct hda_codec *codec, 1114 hda_nid_t pin_nid, int dev_id, hda_nid_t cvt_nid) 1115 { 1116 int mux_idx; 1117 struct hdmi_spec *spec = codec->spec; 1118 1119 /* On Intel platform, the mapping of converter nid to 1120 * mux index of the pins are always the same. 1121 * The pin nid may be 0, this means all pins will not 1122 * share the converter. 1123 */ 1124 mux_idx = intel_cvt_id_to_mux_idx(spec, cvt_nid); 1125 if (mux_idx >= 0) 1126 intel_not_share_assigned_cvt(codec, pin_nid, dev_id, mux_idx); 1127 } 1128 1129 /* skeleton caller of pin_cvt_fixup ops */ 1130 static void pin_cvt_fixup(struct hda_codec *codec, 1131 struct hdmi_spec_per_pin *per_pin, 1132 hda_nid_t cvt_nid) 1133 { 1134 struct hdmi_spec *spec = codec->spec; 1135 1136 if (spec->ops.pin_cvt_fixup) 1137 spec->ops.pin_cvt_fixup(codec, per_pin, cvt_nid); 1138 } 1139 1140 /* called in hdmi_pcm_open when no pin is assigned to the PCM 1141 * in dyn_pcm_assign mode. 1142 */ 1143 static int hdmi_pcm_open_no_pin(struct hda_pcm_stream *hinfo, 1144 struct hda_codec *codec, 1145 struct snd_pcm_substream *substream) 1146 { 1147 struct hdmi_spec *spec = codec->spec; 1148 struct snd_pcm_runtime *runtime = substream->runtime; 1149 int cvt_idx, pcm_idx; 1150 struct hdmi_spec_per_cvt *per_cvt = NULL; 1151 int err; 1152 1153 pcm_idx = hinfo_to_pcm_index(codec, hinfo); 1154 if (pcm_idx < 0) 1155 return -EINVAL; 1156 1157 err = hdmi_choose_cvt(codec, -1, &cvt_idx); 1158 if (err) 1159 return err; 1160 1161 per_cvt = get_cvt(spec, cvt_idx); 1162 per_cvt->assigned = 1; 1163 hinfo->nid = per_cvt->cvt_nid; 1164 1165 pin_cvt_fixup(codec, NULL, per_cvt->cvt_nid); 1166 1167 set_bit(pcm_idx, &spec->pcm_in_use); 1168 /* todo: setup spdif ctls assign */ 1169 1170 /* Initially set the converter's capabilities */ 1171 hinfo->channels_min = per_cvt->channels_min; 1172 hinfo->channels_max = per_cvt->channels_max; 1173 hinfo->rates = per_cvt->rates; 1174 hinfo->formats = per_cvt->formats; 1175 hinfo->maxbps = per_cvt->maxbps; 1176 1177 /* Store the updated parameters */ 1178 runtime->hw.channels_min = hinfo->channels_min; 1179 runtime->hw.channels_max = hinfo->channels_max; 1180 runtime->hw.formats = hinfo->formats; 1181 runtime->hw.rates = hinfo->rates; 1182 1183 snd_pcm_hw_constraint_step(substream->runtime, 0, 1184 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 1185 return 0; 1186 } 1187 1188 /* 1189 * HDA PCM callbacks 1190 */ 1191 static int hdmi_pcm_open(struct hda_pcm_stream *hinfo, 1192 struct hda_codec *codec, 1193 struct snd_pcm_substream *substream) 1194 { 1195 struct hdmi_spec *spec = codec->spec; 1196 struct snd_pcm_runtime *runtime = substream->runtime; 1197 int pin_idx, cvt_idx, pcm_idx; 1198 struct hdmi_spec_per_pin *per_pin; 1199 struct hdmi_eld *eld; 1200 struct hdmi_spec_per_cvt *per_cvt = NULL; 1201 int err; 1202 1203 /* Validate hinfo */ 1204 pcm_idx = hinfo_to_pcm_index(codec, hinfo); 1205 if (pcm_idx < 0) 1206 return -EINVAL; 1207 1208 mutex_lock(&spec->pcm_lock); 1209 pin_idx = hinfo_to_pin_index(codec, hinfo); 1210 if (!spec->dyn_pcm_assign) { 1211 if (snd_BUG_ON(pin_idx < 0)) { 1212 mutex_unlock(&spec->pcm_lock); 1213 return -EINVAL; 1214 } 1215 } else { 1216 /* no pin is assigned to the PCM 1217 * PA need pcm open successfully when probe 1218 */ 1219 if (pin_idx < 0) { 1220 err = hdmi_pcm_open_no_pin(hinfo, codec, substream); 1221 mutex_unlock(&spec->pcm_lock); 1222 return err; 1223 } 1224 } 1225 1226 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx); 1227 if (err < 0) { 1228 mutex_unlock(&spec->pcm_lock); 1229 return err; 1230 } 1231 1232 per_cvt = get_cvt(spec, cvt_idx); 1233 /* Claim converter */ 1234 per_cvt->assigned = 1; 1235 1236 set_bit(pcm_idx, &spec->pcm_in_use); 1237 per_pin = get_pin(spec, pin_idx); 1238 per_pin->cvt_nid = per_cvt->cvt_nid; 1239 hinfo->nid = per_cvt->cvt_nid; 1240 1241 snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id); 1242 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0, 1243 AC_VERB_SET_CONNECT_SEL, 1244 per_pin->mux_idx); 1245 1246 /* configure unused pins to choose other converters */ 1247 pin_cvt_fixup(codec, per_pin, 0); 1248 1249 snd_hda_spdif_ctls_assign(codec, pcm_idx, per_cvt->cvt_nid); 1250 1251 /* Initially set the converter's capabilities */ 1252 hinfo->channels_min = per_cvt->channels_min; 1253 hinfo->channels_max = per_cvt->channels_max; 1254 hinfo->rates = per_cvt->rates; 1255 hinfo->formats = per_cvt->formats; 1256 hinfo->maxbps = per_cvt->maxbps; 1257 1258 eld = &per_pin->sink_eld; 1259 /* Restrict capabilities by ELD if this isn't disabled */ 1260 if (!static_hdmi_pcm && eld->eld_valid) { 1261 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo); 1262 if (hinfo->channels_min > hinfo->channels_max || 1263 !hinfo->rates || !hinfo->formats) { 1264 per_cvt->assigned = 0; 1265 hinfo->nid = 0; 1266 snd_hda_spdif_ctls_unassign(codec, pcm_idx); 1267 mutex_unlock(&spec->pcm_lock); 1268 return -ENODEV; 1269 } 1270 } 1271 1272 mutex_unlock(&spec->pcm_lock); 1273 /* Store the updated parameters */ 1274 runtime->hw.channels_min = hinfo->channels_min; 1275 runtime->hw.channels_max = hinfo->channels_max; 1276 runtime->hw.formats = hinfo->formats; 1277 runtime->hw.rates = hinfo->rates; 1278 1279 snd_pcm_hw_constraint_step(substream->runtime, 0, 1280 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 1281 return 0; 1282 } 1283 1284 /* 1285 * HDA/HDMI auto parsing 1286 */ 1287 static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx) 1288 { 1289 struct hdmi_spec *spec = codec->spec; 1290 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 1291 hda_nid_t pin_nid = per_pin->pin_nid; 1292 1293 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) { 1294 codec_warn(codec, 1295 "HDMI: pin %d wcaps %#x does not support connection list\n", 1296 pin_nid, get_wcaps(codec, pin_nid)); 1297 return -EINVAL; 1298 } 1299 1300 /* all the device entries on the same pin have the same conn list */ 1301 per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid, 1302 per_pin->mux_nids, 1303 HDA_MAX_CONNECTIONS); 1304 1305 return 0; 1306 } 1307 1308 static int hdmi_find_pcm_slot(struct hdmi_spec *spec, 1309 struct hdmi_spec_per_pin *per_pin) 1310 { 1311 int i; 1312 1313 /* try the prefer PCM */ 1314 if (!test_bit(per_pin->pin_nid_idx, &spec->pcm_bitmap)) 1315 return per_pin->pin_nid_idx; 1316 1317 /* have a second try; check the "reserved area" over num_pins */ 1318 for (i = spec->num_nids; i < spec->pcm_used; i++) { 1319 if (!test_bit(i, &spec->pcm_bitmap)) 1320 return i; 1321 } 1322 1323 /* the last try; check the empty slots in pins */ 1324 for (i = 0; i < spec->num_nids; i++) { 1325 if (!test_bit(i, &spec->pcm_bitmap)) 1326 return i; 1327 } 1328 return -EBUSY; 1329 } 1330 1331 static void hdmi_attach_hda_pcm(struct hdmi_spec *spec, 1332 struct hdmi_spec_per_pin *per_pin) 1333 { 1334 int idx; 1335 1336 /* pcm already be attached to the pin */ 1337 if (per_pin->pcm) 1338 return; 1339 idx = hdmi_find_pcm_slot(spec, per_pin); 1340 if (idx == -EBUSY) 1341 return; 1342 per_pin->pcm_idx = idx; 1343 per_pin->pcm = get_hdmi_pcm(spec, idx); 1344 set_bit(idx, &spec->pcm_bitmap); 1345 } 1346 1347 static void hdmi_detach_hda_pcm(struct hdmi_spec *spec, 1348 struct hdmi_spec_per_pin *per_pin) 1349 { 1350 int idx; 1351 1352 /* pcm already be detached from the pin */ 1353 if (!per_pin->pcm) 1354 return; 1355 idx = per_pin->pcm_idx; 1356 per_pin->pcm_idx = -1; 1357 per_pin->pcm = NULL; 1358 if (idx >= 0 && idx < spec->pcm_used) 1359 clear_bit(idx, &spec->pcm_bitmap); 1360 } 1361 1362 static int hdmi_get_pin_cvt_mux(struct hdmi_spec *spec, 1363 struct hdmi_spec_per_pin *per_pin, hda_nid_t cvt_nid) 1364 { 1365 int mux_idx; 1366 1367 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++) 1368 if (per_pin->mux_nids[mux_idx] == cvt_nid) 1369 break; 1370 return mux_idx; 1371 } 1372 1373 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid); 1374 1375 static void hdmi_pcm_setup_pin(struct hdmi_spec *spec, 1376 struct hdmi_spec_per_pin *per_pin) 1377 { 1378 struct hda_codec *codec = per_pin->codec; 1379 struct hda_pcm *pcm; 1380 struct hda_pcm_stream *hinfo; 1381 struct snd_pcm_substream *substream; 1382 int mux_idx; 1383 bool non_pcm; 1384 1385 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used) 1386 pcm = get_pcm_rec(spec, per_pin->pcm_idx); 1387 else 1388 return; 1389 if (!pcm->pcm) 1390 return; 1391 if (!test_bit(per_pin->pcm_idx, &spec->pcm_in_use)) 1392 return; 1393 1394 /* hdmi audio only uses playback and one substream */ 1395 hinfo = pcm->stream; 1396 substream = pcm->pcm->streams[0].substream; 1397 1398 per_pin->cvt_nid = hinfo->nid; 1399 1400 mux_idx = hdmi_get_pin_cvt_mux(spec, per_pin, hinfo->nid); 1401 if (mux_idx < per_pin->num_mux_nids) { 1402 snd_hda_set_dev_select(codec, per_pin->pin_nid, 1403 per_pin->dev_id); 1404 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0, 1405 AC_VERB_SET_CONNECT_SEL, 1406 mux_idx); 1407 } 1408 snd_hda_spdif_ctls_assign(codec, per_pin->pcm_idx, hinfo->nid); 1409 1410 non_pcm = check_non_pcm_per_cvt(codec, hinfo->nid); 1411 if (substream->runtime) 1412 per_pin->channels = substream->runtime->channels; 1413 per_pin->setup = true; 1414 per_pin->mux_idx = mux_idx; 1415 1416 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm); 1417 } 1418 1419 static void hdmi_pcm_reset_pin(struct hdmi_spec *spec, 1420 struct hdmi_spec_per_pin *per_pin) 1421 { 1422 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used) 1423 snd_hda_spdif_ctls_unassign(per_pin->codec, per_pin->pcm_idx); 1424 1425 per_pin->chmap_set = false; 1426 memset(per_pin->chmap, 0, sizeof(per_pin->chmap)); 1427 1428 per_pin->setup = false; 1429 per_pin->channels = 0; 1430 } 1431 1432 /* update per_pin ELD from the given new ELD; 1433 * setup info frame and notification accordingly 1434 */ 1435 static void update_eld(struct hda_codec *codec, 1436 struct hdmi_spec_per_pin *per_pin, 1437 struct hdmi_eld *eld) 1438 { 1439 struct hdmi_eld *pin_eld = &per_pin->sink_eld; 1440 struct hdmi_spec *spec = codec->spec; 1441 bool old_eld_valid = pin_eld->eld_valid; 1442 bool eld_changed; 1443 int pcm_idx = -1; 1444 1445 /* for monitor disconnection, save pcm_idx firstly */ 1446 pcm_idx = per_pin->pcm_idx; 1447 if (spec->dyn_pcm_assign) { 1448 if (eld->eld_valid) { 1449 hdmi_attach_hda_pcm(spec, per_pin); 1450 hdmi_pcm_setup_pin(spec, per_pin); 1451 } else { 1452 hdmi_pcm_reset_pin(spec, per_pin); 1453 hdmi_detach_hda_pcm(spec, per_pin); 1454 } 1455 } 1456 /* if pcm_idx == -1, it means this is in monitor connection event 1457 * we can get the correct pcm_idx now. 1458 */ 1459 if (pcm_idx == -1) 1460 pcm_idx = per_pin->pcm_idx; 1461 1462 if (eld->eld_valid) 1463 snd_hdmi_show_eld(codec, &eld->info); 1464 1465 eld_changed = (pin_eld->eld_valid != eld->eld_valid); 1466 if (eld->eld_valid && pin_eld->eld_valid) 1467 if (pin_eld->eld_size != eld->eld_size || 1468 memcmp(pin_eld->eld_buffer, eld->eld_buffer, 1469 eld->eld_size) != 0) 1470 eld_changed = true; 1471 1472 pin_eld->monitor_present = eld->monitor_present; 1473 pin_eld->eld_valid = eld->eld_valid; 1474 pin_eld->eld_size = eld->eld_size; 1475 if (eld->eld_valid) 1476 memcpy(pin_eld->eld_buffer, eld->eld_buffer, eld->eld_size); 1477 pin_eld->info = eld->info; 1478 1479 /* 1480 * Re-setup pin and infoframe. This is needed e.g. when 1481 * - sink is first plugged-in 1482 * - transcoder can change during stream playback on Haswell 1483 * and this can make HW reset converter selection on a pin. 1484 */ 1485 if (eld->eld_valid && !old_eld_valid && per_pin->setup) { 1486 pin_cvt_fixup(codec, per_pin, 0); 1487 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm); 1488 } 1489 1490 if (eld_changed && pcm_idx >= 0) 1491 snd_ctl_notify(codec->card, 1492 SNDRV_CTL_EVENT_MASK_VALUE | 1493 SNDRV_CTL_EVENT_MASK_INFO, 1494 &get_hdmi_pcm(spec, pcm_idx)->eld_ctl->id); 1495 } 1496 1497 /* update ELD and jack state via HD-audio verbs */ 1498 static bool hdmi_present_sense_via_verbs(struct hdmi_spec_per_pin *per_pin, 1499 int repoll) 1500 { 1501 struct hda_jack_tbl *jack; 1502 struct hda_codec *codec = per_pin->codec; 1503 struct hdmi_spec *spec = codec->spec; 1504 struct hdmi_eld *eld = &spec->temp_eld; 1505 hda_nid_t pin_nid = per_pin->pin_nid; 1506 /* 1507 * Always execute a GetPinSense verb here, even when called from 1508 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited 1509 * response's PD bit is not the real PD value, but indicates that 1510 * the real PD value changed. An older version of the HD-audio 1511 * specification worked this way. Hence, we just ignore the data in 1512 * the unsolicited response to avoid custom WARs. 1513 */ 1514 int present; 1515 bool ret; 1516 bool do_repoll = false; 1517 1518 present = snd_hda_pin_sense(codec, pin_nid); 1519 1520 mutex_lock(&per_pin->lock); 1521 eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE); 1522 if (eld->monitor_present) 1523 eld->eld_valid = !!(present & AC_PINSENSE_ELDV); 1524 else 1525 eld->eld_valid = false; 1526 1527 codec_dbg(codec, 1528 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n", 1529 codec->addr, pin_nid, eld->monitor_present, eld->eld_valid); 1530 1531 if (eld->eld_valid) { 1532 if (spec->ops.pin_get_eld(codec, pin_nid, eld->eld_buffer, 1533 &eld->eld_size) < 0) 1534 eld->eld_valid = false; 1535 else { 1536 if (snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer, 1537 eld->eld_size) < 0) 1538 eld->eld_valid = false; 1539 } 1540 if (!eld->eld_valid && repoll) 1541 do_repoll = true; 1542 } 1543 1544 if (do_repoll) 1545 schedule_delayed_work(&per_pin->work, msecs_to_jiffies(300)); 1546 else 1547 update_eld(codec, per_pin, eld); 1548 1549 ret = !repoll || !eld->monitor_present || eld->eld_valid; 1550 1551 jack = snd_hda_jack_tbl_get(codec, pin_nid); 1552 if (jack) 1553 jack->block_report = !ret; 1554 1555 mutex_unlock(&per_pin->lock); 1556 return ret; 1557 } 1558 1559 static struct snd_jack *pin_idx_to_jack(struct hda_codec *codec, 1560 struct hdmi_spec_per_pin *per_pin) 1561 { 1562 struct hdmi_spec *spec = codec->spec; 1563 struct snd_jack *jack = NULL; 1564 struct hda_jack_tbl *jack_tbl; 1565 1566 /* if !dyn_pcm_assign, get jack from hda_jack_tbl 1567 * in !dyn_pcm_assign case, spec->pcm_rec[].jack is not 1568 * NULL even after snd_hda_jack_tbl_clear() is called to 1569 * free snd_jack. This may cause access invalid memory 1570 * when calling snd_jack_report 1571 */ 1572 if (per_pin->pcm_idx >= 0 && spec->dyn_pcm_assign) 1573 jack = spec->pcm_rec[per_pin->pcm_idx].jack; 1574 else if (!spec->dyn_pcm_assign) { 1575 /* 1576 * jack tbl doesn't support DP MST 1577 * DP MST will use dyn_pcm_assign, 1578 * so DP MST will never come here 1579 */ 1580 jack_tbl = snd_hda_jack_tbl_get(codec, per_pin->pin_nid); 1581 if (jack_tbl) 1582 jack = jack_tbl->jack; 1583 } 1584 return jack; 1585 } 1586 1587 /* update ELD and jack state via audio component */ 1588 static void sync_eld_via_acomp(struct hda_codec *codec, 1589 struct hdmi_spec_per_pin *per_pin) 1590 { 1591 struct hdmi_spec *spec = codec->spec; 1592 struct hdmi_eld *eld = &spec->temp_eld; 1593 struct snd_jack *jack = NULL; 1594 int size; 1595 1596 mutex_lock(&per_pin->lock); 1597 eld->monitor_present = false; 1598 size = snd_hdac_acomp_get_eld(&codec->core, per_pin->pin_nid, 1599 per_pin->dev_id, &eld->monitor_present, 1600 eld->eld_buffer, ELD_MAX_SIZE); 1601 if (size > 0) { 1602 size = min(size, ELD_MAX_SIZE); 1603 if (snd_hdmi_parse_eld(codec, &eld->info, 1604 eld->eld_buffer, size) < 0) 1605 size = -EINVAL; 1606 } 1607 1608 if (size > 0) { 1609 eld->eld_valid = true; 1610 eld->eld_size = size; 1611 } else { 1612 eld->eld_valid = false; 1613 eld->eld_size = 0; 1614 } 1615 1616 /* pcm_idx >=0 before update_eld() means it is in monitor 1617 * disconnected event. Jack must be fetched before update_eld() 1618 */ 1619 jack = pin_idx_to_jack(codec, per_pin); 1620 update_eld(codec, per_pin, eld); 1621 if (jack == NULL) 1622 jack = pin_idx_to_jack(codec, per_pin); 1623 if (jack == NULL) 1624 goto unlock; 1625 snd_jack_report(jack, 1626 eld->monitor_present ? SND_JACK_AVOUT : 0); 1627 unlock: 1628 mutex_unlock(&per_pin->lock); 1629 } 1630 1631 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll) 1632 { 1633 struct hda_codec *codec = per_pin->codec; 1634 int ret; 1635 1636 /* no temporary power up/down needed for component notifier */ 1637 if (!codec_has_acomp(codec)) { 1638 ret = snd_hda_power_up_pm(codec); 1639 if (ret < 0 && pm_runtime_suspended(hda_codec_dev(codec))) { 1640 snd_hda_power_down_pm(codec); 1641 return false; 1642 } 1643 } 1644 1645 if (codec_has_acomp(codec)) { 1646 sync_eld_via_acomp(codec, per_pin); 1647 ret = false; /* don't call snd_hda_jack_report_sync() */ 1648 } else { 1649 ret = hdmi_present_sense_via_verbs(per_pin, repoll); 1650 } 1651 1652 if (!codec_has_acomp(codec)) 1653 snd_hda_power_down_pm(codec); 1654 1655 return ret; 1656 } 1657 1658 static void hdmi_repoll_eld(struct work_struct *work) 1659 { 1660 struct hdmi_spec_per_pin *per_pin = 1661 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work); 1662 struct hda_codec *codec = per_pin->codec; 1663 struct hdmi_spec *spec = codec->spec; 1664 1665 if (per_pin->repoll_count++ > 6) 1666 per_pin->repoll_count = 0; 1667 1668 mutex_lock(&spec->pcm_lock); 1669 if (hdmi_present_sense(per_pin, per_pin->repoll_count)) 1670 snd_hda_jack_report_sync(per_pin->codec); 1671 mutex_unlock(&spec->pcm_lock); 1672 } 1673 1674 static void intel_haswell_fixup_connect_list(struct hda_codec *codec, 1675 hda_nid_t nid); 1676 1677 static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid) 1678 { 1679 struct hdmi_spec *spec = codec->spec; 1680 unsigned int caps, config; 1681 int pin_idx; 1682 struct hdmi_spec_per_pin *per_pin; 1683 int err; 1684 int dev_num, i; 1685 1686 caps = snd_hda_query_pin_caps(codec, pin_nid); 1687 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP))) 1688 return 0; 1689 1690 /* 1691 * For DP MST audio, Configuration Default is the same for 1692 * all device entries on the same pin 1693 */ 1694 config = snd_hda_codec_get_pincfg(codec, pin_nid); 1695 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE) 1696 return 0; 1697 1698 /* 1699 * To simplify the implementation, malloc all 1700 * the virtual pins in the initialization statically 1701 */ 1702 if (is_haswell_plus(codec)) { 1703 /* 1704 * On Intel platforms, device entries number is 1705 * changed dynamically. If there is a DP MST 1706 * hub connected, the device entries number is 3. 1707 * Otherwise, it is 1. 1708 * Here we manually set dev_num to 3, so that 1709 * we can initialize all the device entries when 1710 * bootup statically. 1711 */ 1712 dev_num = 3; 1713 spec->dev_num = 3; 1714 } else if (spec->dyn_pcm_assign && codec->dp_mst) { 1715 dev_num = snd_hda_get_num_devices(codec, pin_nid) + 1; 1716 /* 1717 * spec->dev_num is the maxinum number of device entries 1718 * among all the pins 1719 */ 1720 spec->dev_num = (spec->dev_num > dev_num) ? 1721 spec->dev_num : dev_num; 1722 } else { 1723 /* 1724 * If the platform doesn't support DP MST, 1725 * manually set dev_num to 1. This means 1726 * the pin has only one device entry. 1727 */ 1728 dev_num = 1; 1729 spec->dev_num = 1; 1730 } 1731 1732 for (i = 0; i < dev_num; i++) { 1733 pin_idx = spec->num_pins; 1734 per_pin = snd_array_new(&spec->pins); 1735 1736 if (!per_pin) 1737 return -ENOMEM; 1738 1739 if (spec->dyn_pcm_assign) { 1740 per_pin->pcm = NULL; 1741 per_pin->pcm_idx = -1; 1742 } else { 1743 per_pin->pcm = get_hdmi_pcm(spec, pin_idx); 1744 per_pin->pcm_idx = pin_idx; 1745 } 1746 per_pin->pin_nid = pin_nid; 1747 per_pin->pin_nid_idx = spec->num_nids; 1748 per_pin->dev_id = i; 1749 per_pin->non_pcm = false; 1750 snd_hda_set_dev_select(codec, pin_nid, i); 1751 if (is_haswell_plus(codec)) 1752 intel_haswell_fixup_connect_list(codec, pin_nid); 1753 err = hdmi_read_pin_conn(codec, pin_idx); 1754 if (err < 0) 1755 return err; 1756 spec->num_pins++; 1757 } 1758 spec->num_nids++; 1759 1760 return 0; 1761 } 1762 1763 static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid) 1764 { 1765 struct hdmi_spec *spec = codec->spec; 1766 struct hdmi_spec_per_cvt *per_cvt; 1767 unsigned int chans; 1768 int err; 1769 1770 chans = get_wcaps(codec, cvt_nid); 1771 chans = get_wcaps_channels(chans); 1772 1773 per_cvt = snd_array_new(&spec->cvts); 1774 if (!per_cvt) 1775 return -ENOMEM; 1776 1777 per_cvt->cvt_nid = cvt_nid; 1778 per_cvt->channels_min = 2; 1779 if (chans <= 16) { 1780 per_cvt->channels_max = chans; 1781 if (chans > spec->chmap.channels_max) 1782 spec->chmap.channels_max = chans; 1783 } 1784 1785 err = snd_hda_query_supported_pcm(codec, cvt_nid, 1786 &per_cvt->rates, 1787 &per_cvt->formats, 1788 &per_cvt->maxbps); 1789 if (err < 0) 1790 return err; 1791 1792 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids)) 1793 spec->cvt_nids[spec->num_cvts] = cvt_nid; 1794 spec->num_cvts++; 1795 1796 return 0; 1797 } 1798 1799 static int hdmi_parse_codec(struct hda_codec *codec) 1800 { 1801 hda_nid_t nid; 1802 int i, nodes; 1803 1804 nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &nid); 1805 if (!nid || nodes < 0) { 1806 codec_warn(codec, "HDMI: failed to get afg sub nodes\n"); 1807 return -EINVAL; 1808 } 1809 1810 for (i = 0; i < nodes; i++, nid++) { 1811 unsigned int caps; 1812 unsigned int type; 1813 1814 caps = get_wcaps(codec, nid); 1815 type = get_wcaps_type(caps); 1816 1817 if (!(caps & AC_WCAP_DIGITAL)) 1818 continue; 1819 1820 switch (type) { 1821 case AC_WID_AUD_OUT: 1822 hdmi_add_cvt(codec, nid); 1823 break; 1824 case AC_WID_PIN: 1825 hdmi_add_pin(codec, nid); 1826 break; 1827 } 1828 } 1829 1830 return 0; 1831 } 1832 1833 /* 1834 */ 1835 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid) 1836 { 1837 struct hda_spdif_out *spdif; 1838 bool non_pcm; 1839 1840 mutex_lock(&codec->spdif_mutex); 1841 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid); 1842 /* Add sanity check to pass klockwork check. 1843 * This should never happen. 1844 */ 1845 if (WARN_ON(spdif == NULL)) 1846 return true; 1847 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO); 1848 mutex_unlock(&codec->spdif_mutex); 1849 return non_pcm; 1850 } 1851 1852 /* 1853 * HDMI callbacks 1854 */ 1855 1856 static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 1857 struct hda_codec *codec, 1858 unsigned int stream_tag, 1859 unsigned int format, 1860 struct snd_pcm_substream *substream) 1861 { 1862 hda_nid_t cvt_nid = hinfo->nid; 1863 struct hdmi_spec *spec = codec->spec; 1864 int pin_idx; 1865 struct hdmi_spec_per_pin *per_pin; 1866 hda_nid_t pin_nid; 1867 struct snd_pcm_runtime *runtime = substream->runtime; 1868 bool non_pcm; 1869 int pinctl; 1870 int err; 1871 1872 mutex_lock(&spec->pcm_lock); 1873 pin_idx = hinfo_to_pin_index(codec, hinfo); 1874 if (spec->dyn_pcm_assign && pin_idx < 0) { 1875 /* when dyn_pcm_assign and pcm is not bound to a pin 1876 * skip pin setup and return 0 to make audio playback 1877 * be ongoing 1878 */ 1879 pin_cvt_fixup(codec, NULL, cvt_nid); 1880 snd_hda_codec_setup_stream(codec, cvt_nid, 1881 stream_tag, 0, format); 1882 mutex_unlock(&spec->pcm_lock); 1883 return 0; 1884 } 1885 1886 if (snd_BUG_ON(pin_idx < 0)) { 1887 mutex_unlock(&spec->pcm_lock); 1888 return -EINVAL; 1889 } 1890 per_pin = get_pin(spec, pin_idx); 1891 pin_nid = per_pin->pin_nid; 1892 1893 /* Verify pin:cvt selections to avoid silent audio after S3. 1894 * After S3, the audio driver restores pin:cvt selections 1895 * but this can happen before gfx is ready and such selection 1896 * is overlooked by HW. Thus multiple pins can share a same 1897 * default convertor and mute control will affect each other, 1898 * which can cause a resumed audio playback become silent 1899 * after S3. 1900 */ 1901 pin_cvt_fixup(codec, per_pin, 0); 1902 1903 /* Call sync_audio_rate to set the N/CTS/M manually if necessary */ 1904 /* Todo: add DP1.2 MST audio support later */ 1905 if (codec_has_acomp(codec)) 1906 snd_hdac_sync_audio_rate(&codec->core, pin_nid, per_pin->dev_id, 1907 runtime->rate); 1908 1909 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid); 1910 mutex_lock(&per_pin->lock); 1911 per_pin->channels = substream->runtime->channels; 1912 per_pin->setup = true; 1913 1914 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm); 1915 mutex_unlock(&per_pin->lock); 1916 if (spec->dyn_pin_out) { 1917 pinctl = snd_hda_codec_read(codec, pin_nid, 0, 1918 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 1919 snd_hda_codec_write(codec, pin_nid, 0, 1920 AC_VERB_SET_PIN_WIDGET_CONTROL, 1921 pinctl | PIN_OUT); 1922 } 1923 1924 /* snd_hda_set_dev_select() has been called before */ 1925 err = spec->ops.setup_stream(codec, cvt_nid, pin_nid, 1926 stream_tag, format); 1927 mutex_unlock(&spec->pcm_lock); 1928 return err; 1929 } 1930 1931 static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo, 1932 struct hda_codec *codec, 1933 struct snd_pcm_substream *substream) 1934 { 1935 snd_hda_codec_cleanup_stream(codec, hinfo->nid); 1936 return 0; 1937 } 1938 1939 static int hdmi_pcm_close(struct hda_pcm_stream *hinfo, 1940 struct hda_codec *codec, 1941 struct snd_pcm_substream *substream) 1942 { 1943 struct hdmi_spec *spec = codec->spec; 1944 int cvt_idx, pin_idx, pcm_idx; 1945 struct hdmi_spec_per_cvt *per_cvt; 1946 struct hdmi_spec_per_pin *per_pin; 1947 int pinctl; 1948 1949 if (hinfo->nid) { 1950 pcm_idx = hinfo_to_pcm_index(codec, hinfo); 1951 if (snd_BUG_ON(pcm_idx < 0)) 1952 return -EINVAL; 1953 cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid); 1954 if (snd_BUG_ON(cvt_idx < 0)) 1955 return -EINVAL; 1956 per_cvt = get_cvt(spec, cvt_idx); 1957 1958 snd_BUG_ON(!per_cvt->assigned); 1959 per_cvt->assigned = 0; 1960 hinfo->nid = 0; 1961 1962 mutex_lock(&spec->pcm_lock); 1963 snd_hda_spdif_ctls_unassign(codec, pcm_idx); 1964 clear_bit(pcm_idx, &spec->pcm_in_use); 1965 pin_idx = hinfo_to_pin_index(codec, hinfo); 1966 if (spec->dyn_pcm_assign && pin_idx < 0) { 1967 mutex_unlock(&spec->pcm_lock); 1968 return 0; 1969 } 1970 1971 if (snd_BUG_ON(pin_idx < 0)) { 1972 mutex_unlock(&spec->pcm_lock); 1973 return -EINVAL; 1974 } 1975 per_pin = get_pin(spec, pin_idx); 1976 1977 if (spec->dyn_pin_out) { 1978 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0, 1979 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 1980 snd_hda_codec_write(codec, per_pin->pin_nid, 0, 1981 AC_VERB_SET_PIN_WIDGET_CONTROL, 1982 pinctl & ~PIN_OUT); 1983 } 1984 1985 mutex_lock(&per_pin->lock); 1986 per_pin->chmap_set = false; 1987 memset(per_pin->chmap, 0, sizeof(per_pin->chmap)); 1988 1989 per_pin->setup = false; 1990 per_pin->channels = 0; 1991 mutex_unlock(&per_pin->lock); 1992 mutex_unlock(&spec->pcm_lock); 1993 } 1994 1995 return 0; 1996 } 1997 1998 static const struct hda_pcm_ops generic_ops = { 1999 .open = hdmi_pcm_open, 2000 .close = hdmi_pcm_close, 2001 .prepare = generic_hdmi_playback_pcm_prepare, 2002 .cleanup = generic_hdmi_playback_pcm_cleanup, 2003 }; 2004 2005 static int hdmi_get_spk_alloc(struct hdac_device *hdac, int pcm_idx) 2006 { 2007 struct hda_codec *codec = container_of(hdac, struct hda_codec, core); 2008 struct hdmi_spec *spec = codec->spec; 2009 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2010 2011 if (!per_pin) 2012 return 0; 2013 2014 return per_pin->sink_eld.info.spk_alloc; 2015 } 2016 2017 static void hdmi_get_chmap(struct hdac_device *hdac, int pcm_idx, 2018 unsigned char *chmap) 2019 { 2020 struct hda_codec *codec = container_of(hdac, struct hda_codec, core); 2021 struct hdmi_spec *spec = codec->spec; 2022 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2023 2024 /* chmap is already set to 0 in caller */ 2025 if (!per_pin) 2026 return; 2027 2028 memcpy(chmap, per_pin->chmap, ARRAY_SIZE(per_pin->chmap)); 2029 } 2030 2031 static void hdmi_set_chmap(struct hdac_device *hdac, int pcm_idx, 2032 unsigned char *chmap, int prepared) 2033 { 2034 struct hda_codec *codec = container_of(hdac, struct hda_codec, core); 2035 struct hdmi_spec *spec = codec->spec; 2036 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2037 2038 if (!per_pin) 2039 return; 2040 mutex_lock(&per_pin->lock); 2041 per_pin->chmap_set = true; 2042 memcpy(per_pin->chmap, chmap, ARRAY_SIZE(per_pin->chmap)); 2043 if (prepared) 2044 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm); 2045 mutex_unlock(&per_pin->lock); 2046 } 2047 2048 static bool is_hdmi_pcm_attached(struct hdac_device *hdac, int pcm_idx) 2049 { 2050 struct hda_codec *codec = container_of(hdac, struct hda_codec, core); 2051 struct hdmi_spec *spec = codec->spec; 2052 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2053 2054 return per_pin ? true:false; 2055 } 2056 2057 static int generic_hdmi_build_pcms(struct hda_codec *codec) 2058 { 2059 struct hdmi_spec *spec = codec->spec; 2060 int idx; 2061 2062 /* 2063 * for non-mst mode, pcm number is the same as before 2064 * for DP MST mode, pcm number is (nid number + dev_num - 1) 2065 * dev_num is the device entry number in a pin 2066 * 2067 */ 2068 for (idx = 0; idx < spec->num_nids + spec->dev_num - 1; idx++) { 2069 struct hda_pcm *info; 2070 struct hda_pcm_stream *pstr; 2071 2072 info = snd_hda_codec_pcm_new(codec, "HDMI %d", idx); 2073 if (!info) 2074 return -ENOMEM; 2075 2076 spec->pcm_rec[idx].pcm = info; 2077 spec->pcm_used++; 2078 info->pcm_type = HDA_PCM_TYPE_HDMI; 2079 info->own_chmap = true; 2080 2081 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK]; 2082 pstr->substreams = 1; 2083 pstr->ops = generic_ops; 2084 /* pcm number is less than 16 */ 2085 if (spec->pcm_used >= 16) 2086 break; 2087 /* other pstr fields are set in open */ 2088 } 2089 2090 return 0; 2091 } 2092 2093 static void free_hdmi_jack_priv(struct snd_jack *jack) 2094 { 2095 struct hdmi_pcm *pcm = jack->private_data; 2096 2097 pcm->jack = NULL; 2098 } 2099 2100 static int add_hdmi_jack_kctl(struct hda_codec *codec, 2101 struct hdmi_spec *spec, 2102 int pcm_idx, 2103 const char *name) 2104 { 2105 struct snd_jack *jack; 2106 int err; 2107 2108 err = snd_jack_new(codec->card, name, SND_JACK_AVOUT, &jack, 2109 true, false); 2110 if (err < 0) 2111 return err; 2112 2113 spec->pcm_rec[pcm_idx].jack = jack; 2114 jack->private_data = &spec->pcm_rec[pcm_idx]; 2115 jack->private_free = free_hdmi_jack_priv; 2116 return 0; 2117 } 2118 2119 static int generic_hdmi_build_jack(struct hda_codec *codec, int pcm_idx) 2120 { 2121 char hdmi_str[32] = "HDMI/DP"; 2122 struct hdmi_spec *spec = codec->spec; 2123 struct hdmi_spec_per_pin *per_pin; 2124 struct hda_jack_tbl *jack; 2125 int pcmdev = get_pcm_rec(spec, pcm_idx)->device; 2126 bool phantom_jack; 2127 int ret; 2128 2129 if (pcmdev > 0) 2130 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev); 2131 2132 if (spec->dyn_pcm_assign) 2133 return add_hdmi_jack_kctl(codec, spec, pcm_idx, hdmi_str); 2134 2135 /* for !dyn_pcm_assign, we still use hda_jack for compatibility */ 2136 /* if !dyn_pcm_assign, it must be non-MST mode. 2137 * This means pcms and pins are statically mapped. 2138 * And pcm_idx is pin_idx. 2139 */ 2140 per_pin = get_pin(spec, pcm_idx); 2141 phantom_jack = !is_jack_detectable(codec, per_pin->pin_nid); 2142 if (phantom_jack) 2143 strncat(hdmi_str, " Phantom", 2144 sizeof(hdmi_str) - strlen(hdmi_str) - 1); 2145 ret = snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str, 2146 phantom_jack); 2147 if (ret < 0) 2148 return ret; 2149 jack = snd_hda_jack_tbl_get(codec, per_pin->pin_nid); 2150 if (jack == NULL) 2151 return 0; 2152 /* assign jack->jack to pcm_rec[].jack to 2153 * align with dyn_pcm_assign mode 2154 */ 2155 spec->pcm_rec[pcm_idx].jack = jack->jack; 2156 return 0; 2157 } 2158 2159 static int generic_hdmi_build_controls(struct hda_codec *codec) 2160 { 2161 struct hdmi_spec *spec = codec->spec; 2162 int dev, err; 2163 int pin_idx, pcm_idx; 2164 2165 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { 2166 if (!get_pcm_rec(spec, pcm_idx)->pcm) { 2167 /* no PCM: mark this for skipping permanently */ 2168 set_bit(pcm_idx, &spec->pcm_bitmap); 2169 continue; 2170 } 2171 2172 err = generic_hdmi_build_jack(codec, pcm_idx); 2173 if (err < 0) 2174 return err; 2175 2176 /* create the spdif for each pcm 2177 * pin will be bound when monitor is connected 2178 */ 2179 if (spec->dyn_pcm_assign) 2180 err = snd_hda_create_dig_out_ctls(codec, 2181 0, spec->cvt_nids[0], 2182 HDA_PCM_TYPE_HDMI); 2183 else { 2184 struct hdmi_spec_per_pin *per_pin = 2185 get_pin(spec, pcm_idx); 2186 err = snd_hda_create_dig_out_ctls(codec, 2187 per_pin->pin_nid, 2188 per_pin->mux_nids[0], 2189 HDA_PCM_TYPE_HDMI); 2190 } 2191 if (err < 0) 2192 return err; 2193 snd_hda_spdif_ctls_unassign(codec, pcm_idx); 2194 2195 dev = get_pcm_rec(spec, pcm_idx)->device; 2196 if (dev != SNDRV_PCM_INVALID_DEVICE) { 2197 /* add control for ELD Bytes */ 2198 err = hdmi_create_eld_ctl(codec, pcm_idx, dev); 2199 if (err < 0) 2200 return err; 2201 } 2202 } 2203 2204 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2205 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2206 2207 hdmi_present_sense(per_pin, 0); 2208 } 2209 2210 /* add channel maps */ 2211 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { 2212 struct hda_pcm *pcm; 2213 2214 pcm = get_pcm_rec(spec, pcm_idx); 2215 if (!pcm || !pcm->pcm) 2216 break; 2217 err = snd_hdac_add_chmap_ctls(pcm->pcm, pcm_idx, &spec->chmap); 2218 if (err < 0) 2219 return err; 2220 } 2221 2222 return 0; 2223 } 2224 2225 static int generic_hdmi_init_per_pins(struct hda_codec *codec) 2226 { 2227 struct hdmi_spec *spec = codec->spec; 2228 int pin_idx; 2229 2230 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2231 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2232 2233 per_pin->codec = codec; 2234 mutex_init(&per_pin->lock); 2235 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld); 2236 eld_proc_new(per_pin, pin_idx); 2237 } 2238 return 0; 2239 } 2240 2241 static int generic_hdmi_init(struct hda_codec *codec) 2242 { 2243 struct hdmi_spec *spec = codec->spec; 2244 int pin_idx; 2245 2246 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2247 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2248 hda_nid_t pin_nid = per_pin->pin_nid; 2249 int dev_id = per_pin->dev_id; 2250 2251 snd_hda_set_dev_select(codec, pin_nid, dev_id); 2252 hdmi_init_pin(codec, pin_nid); 2253 if (!codec_has_acomp(codec)) 2254 snd_hda_jack_detect_enable_callback(codec, pin_nid, 2255 codec->jackpoll_interval > 0 ? 2256 jack_callback : NULL); 2257 } 2258 return 0; 2259 } 2260 2261 static void hdmi_array_init(struct hdmi_spec *spec, int nums) 2262 { 2263 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums); 2264 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums); 2265 } 2266 2267 static void hdmi_array_free(struct hdmi_spec *spec) 2268 { 2269 snd_array_free(&spec->pins); 2270 snd_array_free(&spec->cvts); 2271 } 2272 2273 static void generic_spec_free(struct hda_codec *codec) 2274 { 2275 struct hdmi_spec *spec = codec->spec; 2276 2277 if (spec) { 2278 hdmi_array_free(spec); 2279 kfree(spec); 2280 codec->spec = NULL; 2281 } 2282 codec->dp_mst = false; 2283 } 2284 2285 static void generic_hdmi_free(struct hda_codec *codec) 2286 { 2287 struct hdmi_spec *spec = codec->spec; 2288 int pin_idx, pcm_idx; 2289 2290 if (codec_has_acomp(codec)) 2291 snd_hdac_i915_register_notifier(NULL); 2292 2293 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2294 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2295 cancel_delayed_work_sync(&per_pin->work); 2296 eld_proc_free(per_pin); 2297 } 2298 2299 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { 2300 if (spec->pcm_rec[pcm_idx].jack == NULL) 2301 continue; 2302 if (spec->dyn_pcm_assign) 2303 snd_device_free(codec->card, 2304 spec->pcm_rec[pcm_idx].jack); 2305 else 2306 spec->pcm_rec[pcm_idx].jack = NULL; 2307 } 2308 2309 generic_spec_free(codec); 2310 } 2311 2312 #ifdef CONFIG_PM 2313 static int generic_hdmi_resume(struct hda_codec *codec) 2314 { 2315 struct hdmi_spec *spec = codec->spec; 2316 int pin_idx; 2317 2318 codec->patch_ops.init(codec); 2319 regcache_sync(codec->core.regmap); 2320 2321 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2322 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2323 hdmi_present_sense(per_pin, 1); 2324 } 2325 return 0; 2326 } 2327 #endif 2328 2329 static const struct hda_codec_ops generic_hdmi_patch_ops = { 2330 .init = generic_hdmi_init, 2331 .free = generic_hdmi_free, 2332 .build_pcms = generic_hdmi_build_pcms, 2333 .build_controls = generic_hdmi_build_controls, 2334 .unsol_event = hdmi_unsol_event, 2335 #ifdef CONFIG_PM 2336 .resume = generic_hdmi_resume, 2337 #endif 2338 }; 2339 2340 static const struct hdmi_ops generic_standard_hdmi_ops = { 2341 .pin_get_eld = snd_hdmi_get_eld, 2342 .pin_setup_infoframe = hdmi_pin_setup_infoframe, 2343 .pin_hbr_setup = hdmi_pin_hbr_setup, 2344 .setup_stream = hdmi_setup_stream, 2345 }; 2346 2347 /* allocate codec->spec and assign/initialize generic parser ops */ 2348 static int alloc_generic_hdmi(struct hda_codec *codec) 2349 { 2350 struct hdmi_spec *spec; 2351 2352 spec = kzalloc(sizeof(*spec), GFP_KERNEL); 2353 if (!spec) 2354 return -ENOMEM; 2355 2356 spec->ops = generic_standard_hdmi_ops; 2357 spec->dev_num = 1; /* initialize to 1 */ 2358 mutex_init(&spec->pcm_lock); 2359 snd_hdac_register_chmap_ops(&codec->core, &spec->chmap); 2360 2361 spec->chmap.ops.get_chmap = hdmi_get_chmap; 2362 spec->chmap.ops.set_chmap = hdmi_set_chmap; 2363 spec->chmap.ops.is_pcm_attached = is_hdmi_pcm_attached; 2364 spec->chmap.ops.get_spk_alloc = hdmi_get_spk_alloc, 2365 2366 codec->spec = spec; 2367 hdmi_array_init(spec, 4); 2368 2369 codec->patch_ops = generic_hdmi_patch_ops; 2370 2371 return 0; 2372 } 2373 2374 /* generic HDMI parser */ 2375 static int patch_generic_hdmi(struct hda_codec *codec) 2376 { 2377 int err; 2378 2379 err = alloc_generic_hdmi(codec); 2380 if (err < 0) 2381 return err; 2382 2383 err = hdmi_parse_codec(codec); 2384 if (err < 0) { 2385 generic_spec_free(codec); 2386 return err; 2387 } 2388 2389 generic_hdmi_init_per_pins(codec); 2390 return 0; 2391 } 2392 2393 /* 2394 * Intel codec parsers and helpers 2395 */ 2396 2397 static void intel_haswell_fixup_connect_list(struct hda_codec *codec, 2398 hda_nid_t nid) 2399 { 2400 struct hdmi_spec *spec = codec->spec; 2401 hda_nid_t conns[4]; 2402 int nconns; 2403 2404 nconns = snd_hda_get_connections(codec, nid, conns, ARRAY_SIZE(conns)); 2405 if (nconns == spec->num_cvts && 2406 !memcmp(conns, spec->cvt_nids, spec->num_cvts * sizeof(hda_nid_t))) 2407 return; 2408 2409 /* override pins connection list */ 2410 codec_dbg(codec, "hdmi: haswell: override pin connection 0x%x\n", nid); 2411 snd_hda_override_conn_list(codec, nid, spec->num_cvts, spec->cvt_nids); 2412 } 2413 2414 #define INTEL_VENDOR_NID 0x08 2415 #define INTEL_GLK_VENDOR_NID 0x0B 2416 #define INTEL_GET_VENDOR_VERB 0xf81 2417 #define INTEL_SET_VENDOR_VERB 0x781 2418 #define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */ 2419 #define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */ 2420 2421 static void intel_haswell_enable_all_pins(struct hda_codec *codec, 2422 bool update_tree) 2423 { 2424 unsigned int vendor_param; 2425 struct hdmi_spec *spec = codec->spec; 2426 2427 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0, 2428 INTEL_GET_VENDOR_VERB, 0); 2429 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS) 2430 return; 2431 2432 vendor_param |= INTEL_EN_ALL_PIN_CVTS; 2433 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0, 2434 INTEL_SET_VENDOR_VERB, vendor_param); 2435 if (vendor_param == -1) 2436 return; 2437 2438 if (update_tree) 2439 snd_hda_codec_update_widgets(codec); 2440 } 2441 2442 static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec) 2443 { 2444 unsigned int vendor_param; 2445 struct hdmi_spec *spec = codec->spec; 2446 2447 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0, 2448 INTEL_GET_VENDOR_VERB, 0); 2449 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12) 2450 return; 2451 2452 /* enable DP1.2 mode */ 2453 vendor_param |= INTEL_EN_DP12; 2454 snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB); 2455 snd_hda_codec_write_cache(codec, spec->vendor_nid, 0, 2456 INTEL_SET_VENDOR_VERB, vendor_param); 2457 } 2458 2459 /* Haswell needs to re-issue the vendor-specific verbs before turning to D0. 2460 * Otherwise you may get severe h/w communication errors. 2461 */ 2462 static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg, 2463 unsigned int power_state) 2464 { 2465 if (power_state == AC_PWRST_D0) { 2466 intel_haswell_enable_all_pins(codec, false); 2467 intel_haswell_fixup_enable_dp12(codec); 2468 } 2469 2470 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state); 2471 snd_hda_codec_set_power_to_all(codec, fg, power_state); 2472 } 2473 2474 static void intel_pin_eld_notify(void *audio_ptr, int port, int pipe) 2475 { 2476 struct hda_codec *codec = audio_ptr; 2477 int pin_nid; 2478 int dev_id = pipe; 2479 2480 /* we assume only from port-B to port-D */ 2481 if (port < 1 || port > 3) 2482 return; 2483 2484 switch (codec->core.vendor_id) { 2485 case 0x80860054: /* ILK */ 2486 case 0x80862804: /* ILK */ 2487 case 0x80862882: /* VLV */ 2488 pin_nid = port + 0x03; 2489 break; 2490 default: 2491 pin_nid = port + 0x04; 2492 break; 2493 } 2494 2495 /* skip notification during system suspend (but not in runtime PM); 2496 * the state will be updated at resume 2497 */ 2498 if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0) 2499 return; 2500 /* ditto during suspend/resume process itself */ 2501 if (snd_hdac_is_in_pm(&codec->core)) 2502 return; 2503 2504 snd_hdac_i915_set_bclk(&codec->bus->core); 2505 check_presence_and_report(codec, pin_nid, dev_id); 2506 } 2507 2508 /* register i915 component pin_eld_notify callback */ 2509 static void register_i915_notifier(struct hda_codec *codec) 2510 { 2511 struct hdmi_spec *spec = codec->spec; 2512 2513 spec->use_acomp_notifier = true; 2514 spec->i915_audio_ops.audio_ptr = codec; 2515 /* intel_audio_codec_enable() or intel_audio_codec_disable() 2516 * will call pin_eld_notify with using audio_ptr pointer 2517 * We need make sure audio_ptr is really setup 2518 */ 2519 wmb(); 2520 spec->i915_audio_ops.pin_eld_notify = intel_pin_eld_notify; 2521 snd_hdac_i915_register_notifier(&spec->i915_audio_ops); 2522 } 2523 2524 /* setup_stream ops override for HSW+ */ 2525 static int i915_hsw_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, 2526 hda_nid_t pin_nid, u32 stream_tag, int format) 2527 { 2528 haswell_verify_D0(codec, cvt_nid, pin_nid); 2529 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format); 2530 } 2531 2532 /* pin_cvt_fixup ops override for HSW+ and VLV+ */ 2533 static void i915_pin_cvt_fixup(struct hda_codec *codec, 2534 struct hdmi_spec_per_pin *per_pin, 2535 hda_nid_t cvt_nid) 2536 { 2537 if (per_pin) { 2538 snd_hda_set_dev_select(codec, per_pin->pin_nid, 2539 per_pin->dev_id); 2540 intel_verify_pin_cvt_connect(codec, per_pin); 2541 intel_not_share_assigned_cvt(codec, per_pin->pin_nid, 2542 per_pin->dev_id, per_pin->mux_idx); 2543 } else { 2544 intel_not_share_assigned_cvt_nid(codec, 0, 0, cvt_nid); 2545 } 2546 } 2547 2548 /* precondition and allocation for Intel codecs */ 2549 static int alloc_intel_hdmi(struct hda_codec *codec) 2550 { 2551 /* requires i915 binding */ 2552 if (!codec->bus->core.audio_component) { 2553 codec_info(codec, "No i915 binding for Intel HDMI/DP codec\n"); 2554 /* set probe_id here to prevent generic fallback binding */ 2555 codec->probe_id = HDA_CODEC_ID_SKIP_PROBE; 2556 return -ENODEV; 2557 } 2558 2559 return alloc_generic_hdmi(codec); 2560 } 2561 2562 /* parse and post-process for Intel codecs */ 2563 static int parse_intel_hdmi(struct hda_codec *codec) 2564 { 2565 int err; 2566 2567 err = hdmi_parse_codec(codec); 2568 if (err < 0) { 2569 generic_spec_free(codec); 2570 return err; 2571 } 2572 2573 generic_hdmi_init_per_pins(codec); 2574 register_i915_notifier(codec); 2575 return 0; 2576 } 2577 2578 /* Intel Haswell and onwards; audio component with eld notifier */ 2579 static int intel_hsw_common_init(struct hda_codec *codec, hda_nid_t vendor_nid) 2580 { 2581 struct hdmi_spec *spec; 2582 int err; 2583 2584 err = alloc_intel_hdmi(codec); 2585 if (err < 0) 2586 return err; 2587 spec = codec->spec; 2588 codec->dp_mst = true; 2589 spec->dyn_pcm_assign = true; 2590 spec->vendor_nid = vendor_nid; 2591 2592 intel_haswell_enable_all_pins(codec, true); 2593 intel_haswell_fixup_enable_dp12(codec); 2594 2595 /* For Haswell/Broadwell, the controller is also in the power well and 2596 * can cover the codec power request, and so need not set this flag. 2597 */ 2598 if (!is_haswell(codec) && !is_broadwell(codec)) 2599 codec->core.link_power_control = 1; 2600 2601 codec->patch_ops.set_power_state = haswell_set_power_state; 2602 codec->depop_delay = 0; 2603 codec->auto_runtime_pm = 1; 2604 2605 spec->ops.setup_stream = i915_hsw_setup_stream; 2606 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup; 2607 2608 return parse_intel_hdmi(codec); 2609 } 2610 2611 static int patch_i915_hsw_hdmi(struct hda_codec *codec) 2612 { 2613 return intel_hsw_common_init(codec, INTEL_VENDOR_NID); 2614 } 2615 2616 static int patch_i915_glk_hdmi(struct hda_codec *codec) 2617 { 2618 return intel_hsw_common_init(codec, INTEL_GLK_VENDOR_NID); 2619 } 2620 2621 /* Intel Baytrail and Braswell; with eld notifier */ 2622 static int patch_i915_byt_hdmi(struct hda_codec *codec) 2623 { 2624 struct hdmi_spec *spec; 2625 int err; 2626 2627 err = alloc_intel_hdmi(codec); 2628 if (err < 0) 2629 return err; 2630 spec = codec->spec; 2631 2632 /* For Valleyview/Cherryview, only the display codec is in the display 2633 * power well and can use link_power ops to request/release the power. 2634 */ 2635 codec->core.link_power_control = 1; 2636 2637 codec->depop_delay = 0; 2638 codec->auto_runtime_pm = 1; 2639 2640 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup; 2641 2642 return parse_intel_hdmi(codec); 2643 } 2644 2645 /* Intel IronLake, SandyBridge and IvyBridge; with eld notifier */ 2646 static int patch_i915_cpt_hdmi(struct hda_codec *codec) 2647 { 2648 int err; 2649 2650 err = alloc_intel_hdmi(codec); 2651 if (err < 0) 2652 return err; 2653 return parse_intel_hdmi(codec); 2654 } 2655 2656 /* 2657 * Shared non-generic implementations 2658 */ 2659 2660 static int simple_playback_build_pcms(struct hda_codec *codec) 2661 { 2662 struct hdmi_spec *spec = codec->spec; 2663 struct hda_pcm *info; 2664 unsigned int chans; 2665 struct hda_pcm_stream *pstr; 2666 struct hdmi_spec_per_cvt *per_cvt; 2667 2668 per_cvt = get_cvt(spec, 0); 2669 chans = get_wcaps(codec, per_cvt->cvt_nid); 2670 chans = get_wcaps_channels(chans); 2671 2672 info = snd_hda_codec_pcm_new(codec, "HDMI 0"); 2673 if (!info) 2674 return -ENOMEM; 2675 spec->pcm_rec[0].pcm = info; 2676 info->pcm_type = HDA_PCM_TYPE_HDMI; 2677 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK]; 2678 *pstr = spec->pcm_playback; 2679 pstr->nid = per_cvt->cvt_nid; 2680 if (pstr->channels_max <= 2 && chans && chans <= 16) 2681 pstr->channels_max = chans; 2682 2683 return 0; 2684 } 2685 2686 /* unsolicited event for jack sensing */ 2687 static void simple_hdmi_unsol_event(struct hda_codec *codec, 2688 unsigned int res) 2689 { 2690 snd_hda_jack_set_dirty_all(codec); 2691 snd_hda_jack_report_sync(codec); 2692 } 2693 2694 /* generic_hdmi_build_jack can be used for simple_hdmi, too, 2695 * as long as spec->pins[] is set correctly 2696 */ 2697 #define simple_hdmi_build_jack generic_hdmi_build_jack 2698 2699 static int simple_playback_build_controls(struct hda_codec *codec) 2700 { 2701 struct hdmi_spec *spec = codec->spec; 2702 struct hdmi_spec_per_cvt *per_cvt; 2703 int err; 2704 2705 per_cvt = get_cvt(spec, 0); 2706 err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid, 2707 per_cvt->cvt_nid, 2708 HDA_PCM_TYPE_HDMI); 2709 if (err < 0) 2710 return err; 2711 return simple_hdmi_build_jack(codec, 0); 2712 } 2713 2714 static int simple_playback_init(struct hda_codec *codec) 2715 { 2716 struct hdmi_spec *spec = codec->spec; 2717 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0); 2718 hda_nid_t pin = per_pin->pin_nid; 2719 2720 snd_hda_codec_write(codec, pin, 0, 2721 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT); 2722 /* some codecs require to unmute the pin */ 2723 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP) 2724 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE, 2725 AMP_OUT_UNMUTE); 2726 snd_hda_jack_detect_enable(codec, pin); 2727 return 0; 2728 } 2729 2730 static void simple_playback_free(struct hda_codec *codec) 2731 { 2732 struct hdmi_spec *spec = codec->spec; 2733 2734 hdmi_array_free(spec); 2735 kfree(spec); 2736 } 2737 2738 /* 2739 * Nvidia specific implementations 2740 */ 2741 2742 #define Nv_VERB_SET_Channel_Allocation 0xF79 2743 #define Nv_VERB_SET_Info_Frame_Checksum 0xF7A 2744 #define Nv_VERB_SET_Audio_Protection_On 0xF98 2745 #define Nv_VERB_SET_Audio_Protection_Off 0xF99 2746 2747 #define nvhdmi_master_con_nid_7x 0x04 2748 #define nvhdmi_master_pin_nid_7x 0x05 2749 2750 static const hda_nid_t nvhdmi_con_nids_7x[4] = { 2751 /*front, rear, clfe, rear_surr */ 2752 0x6, 0x8, 0xa, 0xc, 2753 }; 2754 2755 static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = { 2756 /* set audio protect on */ 2757 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1}, 2758 /* enable digital output on pin widget */ 2759 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 2760 {} /* terminator */ 2761 }; 2762 2763 static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = { 2764 /* set audio protect on */ 2765 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1}, 2766 /* enable digital output on pin widget */ 2767 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 2768 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 2769 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 2770 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 2771 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 2772 {} /* terminator */ 2773 }; 2774 2775 #ifdef LIMITED_RATE_FMT_SUPPORT 2776 /* support only the safe format and rate */ 2777 #define SUPPORTED_RATES SNDRV_PCM_RATE_48000 2778 #define SUPPORTED_MAXBPS 16 2779 #define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE 2780 #else 2781 /* support all rates and formats */ 2782 #define SUPPORTED_RATES \ 2783 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\ 2784 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\ 2785 SNDRV_PCM_RATE_192000) 2786 #define SUPPORTED_MAXBPS 24 2787 #define SUPPORTED_FORMATS \ 2788 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE) 2789 #endif 2790 2791 static int nvhdmi_7x_init_2ch(struct hda_codec *codec) 2792 { 2793 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch); 2794 return 0; 2795 } 2796 2797 static int nvhdmi_7x_init_8ch(struct hda_codec *codec) 2798 { 2799 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch); 2800 return 0; 2801 } 2802 2803 static const unsigned int channels_2_6_8[] = { 2804 2, 6, 8 2805 }; 2806 2807 static const unsigned int channels_2_8[] = { 2808 2, 8 2809 }; 2810 2811 static const struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = { 2812 .count = ARRAY_SIZE(channels_2_6_8), 2813 .list = channels_2_6_8, 2814 .mask = 0, 2815 }; 2816 2817 static const struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = { 2818 .count = ARRAY_SIZE(channels_2_8), 2819 .list = channels_2_8, 2820 .mask = 0, 2821 }; 2822 2823 static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo, 2824 struct hda_codec *codec, 2825 struct snd_pcm_substream *substream) 2826 { 2827 struct hdmi_spec *spec = codec->spec; 2828 const struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL; 2829 2830 switch (codec->preset->vendor_id) { 2831 case 0x10de0002: 2832 case 0x10de0003: 2833 case 0x10de0005: 2834 case 0x10de0006: 2835 hw_constraints_channels = &hw_constraints_2_8_channels; 2836 break; 2837 case 0x10de0007: 2838 hw_constraints_channels = &hw_constraints_2_6_8_channels; 2839 break; 2840 default: 2841 break; 2842 } 2843 2844 if (hw_constraints_channels != NULL) { 2845 snd_pcm_hw_constraint_list(substream->runtime, 0, 2846 SNDRV_PCM_HW_PARAM_CHANNELS, 2847 hw_constraints_channels); 2848 } else { 2849 snd_pcm_hw_constraint_step(substream->runtime, 0, 2850 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 2851 } 2852 2853 return snd_hda_multi_out_dig_open(codec, &spec->multiout); 2854 } 2855 2856 static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo, 2857 struct hda_codec *codec, 2858 struct snd_pcm_substream *substream) 2859 { 2860 struct hdmi_spec *spec = codec->spec; 2861 return snd_hda_multi_out_dig_close(codec, &spec->multiout); 2862 } 2863 2864 static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 2865 struct hda_codec *codec, 2866 unsigned int stream_tag, 2867 unsigned int format, 2868 struct snd_pcm_substream *substream) 2869 { 2870 struct hdmi_spec *spec = codec->spec; 2871 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout, 2872 stream_tag, format, substream); 2873 } 2874 2875 static const struct hda_pcm_stream simple_pcm_playback = { 2876 .substreams = 1, 2877 .channels_min = 2, 2878 .channels_max = 2, 2879 .ops = { 2880 .open = simple_playback_pcm_open, 2881 .close = simple_playback_pcm_close, 2882 .prepare = simple_playback_pcm_prepare 2883 }, 2884 }; 2885 2886 static const struct hda_codec_ops simple_hdmi_patch_ops = { 2887 .build_controls = simple_playback_build_controls, 2888 .build_pcms = simple_playback_build_pcms, 2889 .init = simple_playback_init, 2890 .free = simple_playback_free, 2891 .unsol_event = simple_hdmi_unsol_event, 2892 }; 2893 2894 static int patch_simple_hdmi(struct hda_codec *codec, 2895 hda_nid_t cvt_nid, hda_nid_t pin_nid) 2896 { 2897 struct hdmi_spec *spec; 2898 struct hdmi_spec_per_cvt *per_cvt; 2899 struct hdmi_spec_per_pin *per_pin; 2900 2901 spec = kzalloc(sizeof(*spec), GFP_KERNEL); 2902 if (!spec) 2903 return -ENOMEM; 2904 2905 codec->spec = spec; 2906 hdmi_array_init(spec, 1); 2907 2908 spec->multiout.num_dacs = 0; /* no analog */ 2909 spec->multiout.max_channels = 2; 2910 spec->multiout.dig_out_nid = cvt_nid; 2911 spec->num_cvts = 1; 2912 spec->num_pins = 1; 2913 per_pin = snd_array_new(&spec->pins); 2914 per_cvt = snd_array_new(&spec->cvts); 2915 if (!per_pin || !per_cvt) { 2916 simple_playback_free(codec); 2917 return -ENOMEM; 2918 } 2919 per_cvt->cvt_nid = cvt_nid; 2920 per_pin->pin_nid = pin_nid; 2921 spec->pcm_playback = simple_pcm_playback; 2922 2923 codec->patch_ops = simple_hdmi_patch_ops; 2924 2925 return 0; 2926 } 2927 2928 static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec, 2929 int channels) 2930 { 2931 unsigned int chanmask; 2932 int chan = channels ? (channels - 1) : 1; 2933 2934 switch (channels) { 2935 default: 2936 case 0: 2937 case 2: 2938 chanmask = 0x00; 2939 break; 2940 case 4: 2941 chanmask = 0x08; 2942 break; 2943 case 6: 2944 chanmask = 0x0b; 2945 break; 2946 case 8: 2947 chanmask = 0x13; 2948 break; 2949 } 2950 2951 /* Set the audio infoframe channel allocation and checksum fields. The 2952 * channel count is computed implicitly by the hardware. */ 2953 snd_hda_codec_write(codec, 0x1, 0, 2954 Nv_VERB_SET_Channel_Allocation, chanmask); 2955 2956 snd_hda_codec_write(codec, 0x1, 0, 2957 Nv_VERB_SET_Info_Frame_Checksum, 2958 (0x71 - chan - chanmask)); 2959 } 2960 2961 static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo, 2962 struct hda_codec *codec, 2963 struct snd_pcm_substream *substream) 2964 { 2965 struct hdmi_spec *spec = codec->spec; 2966 int i; 2967 2968 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 2969 0, AC_VERB_SET_CHANNEL_STREAMID, 0); 2970 for (i = 0; i < 4; i++) { 2971 /* set the stream id */ 2972 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0, 2973 AC_VERB_SET_CHANNEL_STREAMID, 0); 2974 /* set the stream format */ 2975 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0, 2976 AC_VERB_SET_STREAM_FORMAT, 0); 2977 } 2978 2979 /* The audio hardware sends a channel count of 0x7 (8ch) when all the 2980 * streams are disabled. */ 2981 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8); 2982 2983 return snd_hda_multi_out_dig_close(codec, &spec->multiout); 2984 } 2985 2986 static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo, 2987 struct hda_codec *codec, 2988 unsigned int stream_tag, 2989 unsigned int format, 2990 struct snd_pcm_substream *substream) 2991 { 2992 int chs; 2993 unsigned int dataDCC2, channel_id; 2994 int i; 2995 struct hdmi_spec *spec = codec->spec; 2996 struct hda_spdif_out *spdif; 2997 struct hdmi_spec_per_cvt *per_cvt; 2998 2999 mutex_lock(&codec->spdif_mutex); 3000 per_cvt = get_cvt(spec, 0); 3001 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid); 3002 3003 chs = substream->runtime->channels; 3004 3005 dataDCC2 = 0x2; 3006 3007 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */ 3008 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) 3009 snd_hda_codec_write(codec, 3010 nvhdmi_master_con_nid_7x, 3011 0, 3012 AC_VERB_SET_DIGI_CONVERT_1, 3013 spdif->ctls & ~AC_DIG1_ENABLE & 0xff); 3014 3015 /* set the stream id */ 3016 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0, 3017 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0); 3018 3019 /* set the stream format */ 3020 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0, 3021 AC_VERB_SET_STREAM_FORMAT, format); 3022 3023 /* turn on again (if needed) */ 3024 /* enable and set the channel status audio/data flag */ 3025 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) { 3026 snd_hda_codec_write(codec, 3027 nvhdmi_master_con_nid_7x, 3028 0, 3029 AC_VERB_SET_DIGI_CONVERT_1, 3030 spdif->ctls & 0xff); 3031 snd_hda_codec_write(codec, 3032 nvhdmi_master_con_nid_7x, 3033 0, 3034 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2); 3035 } 3036 3037 for (i = 0; i < 4; i++) { 3038 if (chs == 2) 3039 channel_id = 0; 3040 else 3041 channel_id = i * 2; 3042 3043 /* turn off SPDIF once; 3044 *otherwise the IEC958 bits won't be updated 3045 */ 3046 if (codec->spdif_status_reset && 3047 (spdif->ctls & AC_DIG1_ENABLE)) 3048 snd_hda_codec_write(codec, 3049 nvhdmi_con_nids_7x[i], 3050 0, 3051 AC_VERB_SET_DIGI_CONVERT_1, 3052 spdif->ctls & ~AC_DIG1_ENABLE & 0xff); 3053 /* set the stream id */ 3054 snd_hda_codec_write(codec, 3055 nvhdmi_con_nids_7x[i], 3056 0, 3057 AC_VERB_SET_CHANNEL_STREAMID, 3058 (stream_tag << 4) | channel_id); 3059 /* set the stream format */ 3060 snd_hda_codec_write(codec, 3061 nvhdmi_con_nids_7x[i], 3062 0, 3063 AC_VERB_SET_STREAM_FORMAT, 3064 format); 3065 /* turn on again (if needed) */ 3066 /* enable and set the channel status audio/data flag */ 3067 if (codec->spdif_status_reset && 3068 (spdif->ctls & AC_DIG1_ENABLE)) { 3069 snd_hda_codec_write(codec, 3070 nvhdmi_con_nids_7x[i], 3071 0, 3072 AC_VERB_SET_DIGI_CONVERT_1, 3073 spdif->ctls & 0xff); 3074 snd_hda_codec_write(codec, 3075 nvhdmi_con_nids_7x[i], 3076 0, 3077 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2); 3078 } 3079 } 3080 3081 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs); 3082 3083 mutex_unlock(&codec->spdif_mutex); 3084 return 0; 3085 } 3086 3087 static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = { 3088 .substreams = 1, 3089 .channels_min = 2, 3090 .channels_max = 8, 3091 .nid = nvhdmi_master_con_nid_7x, 3092 .rates = SUPPORTED_RATES, 3093 .maxbps = SUPPORTED_MAXBPS, 3094 .formats = SUPPORTED_FORMATS, 3095 .ops = { 3096 .open = simple_playback_pcm_open, 3097 .close = nvhdmi_8ch_7x_pcm_close, 3098 .prepare = nvhdmi_8ch_7x_pcm_prepare 3099 }, 3100 }; 3101 3102 static int patch_nvhdmi_2ch(struct hda_codec *codec) 3103 { 3104 struct hdmi_spec *spec; 3105 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x, 3106 nvhdmi_master_pin_nid_7x); 3107 if (err < 0) 3108 return err; 3109 3110 codec->patch_ops.init = nvhdmi_7x_init_2ch; 3111 /* override the PCM rates, etc, as the codec doesn't give full list */ 3112 spec = codec->spec; 3113 spec->pcm_playback.rates = SUPPORTED_RATES; 3114 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS; 3115 spec->pcm_playback.formats = SUPPORTED_FORMATS; 3116 return 0; 3117 } 3118 3119 static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec) 3120 { 3121 struct hdmi_spec *spec = codec->spec; 3122 int err = simple_playback_build_pcms(codec); 3123 if (!err) { 3124 struct hda_pcm *info = get_pcm_rec(spec, 0); 3125 info->own_chmap = true; 3126 } 3127 return err; 3128 } 3129 3130 static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec) 3131 { 3132 struct hdmi_spec *spec = codec->spec; 3133 struct hda_pcm *info; 3134 struct snd_pcm_chmap *chmap; 3135 int err; 3136 3137 err = simple_playback_build_controls(codec); 3138 if (err < 0) 3139 return err; 3140 3141 /* add channel maps */ 3142 info = get_pcm_rec(spec, 0); 3143 err = snd_pcm_add_chmap_ctls(info->pcm, 3144 SNDRV_PCM_STREAM_PLAYBACK, 3145 snd_pcm_alt_chmaps, 8, 0, &chmap); 3146 if (err < 0) 3147 return err; 3148 switch (codec->preset->vendor_id) { 3149 case 0x10de0002: 3150 case 0x10de0003: 3151 case 0x10de0005: 3152 case 0x10de0006: 3153 chmap->channel_mask = (1U << 2) | (1U << 8); 3154 break; 3155 case 0x10de0007: 3156 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8); 3157 } 3158 return 0; 3159 } 3160 3161 static int patch_nvhdmi_8ch_7x(struct hda_codec *codec) 3162 { 3163 struct hdmi_spec *spec; 3164 int err = patch_nvhdmi_2ch(codec); 3165 if (err < 0) 3166 return err; 3167 spec = codec->spec; 3168 spec->multiout.max_channels = 8; 3169 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x; 3170 codec->patch_ops.init = nvhdmi_7x_init_8ch; 3171 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms; 3172 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls; 3173 3174 /* Initialize the audio infoframe channel mask and checksum to something 3175 * valid */ 3176 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8); 3177 3178 return 0; 3179 } 3180 3181 /* 3182 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on: 3183 * - 0x10de0015 3184 * - 0x10de0040 3185 */ 3186 static int nvhdmi_chmap_cea_alloc_validate_get_type(struct hdac_chmap *chmap, 3187 struct hdac_cea_channel_speaker_allocation *cap, int channels) 3188 { 3189 if (cap->ca_index == 0x00 && channels == 2) 3190 return SNDRV_CTL_TLVT_CHMAP_FIXED; 3191 3192 /* If the speaker allocation matches the channel count, it is OK. */ 3193 if (cap->channels != channels) 3194 return -1; 3195 3196 /* all channels are remappable freely */ 3197 return SNDRV_CTL_TLVT_CHMAP_VAR; 3198 } 3199 3200 static int nvhdmi_chmap_validate(struct hdac_chmap *chmap, 3201 int ca, int chs, unsigned char *map) 3202 { 3203 if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR)) 3204 return -EINVAL; 3205 3206 return 0; 3207 } 3208 3209 static int patch_nvhdmi(struct hda_codec *codec) 3210 { 3211 struct hdmi_spec *spec; 3212 int err; 3213 3214 err = patch_generic_hdmi(codec); 3215 if (err) 3216 return err; 3217 3218 spec = codec->spec; 3219 spec->dyn_pin_out = true; 3220 3221 spec->chmap.ops.chmap_cea_alloc_validate_get_type = 3222 nvhdmi_chmap_cea_alloc_validate_get_type; 3223 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate; 3224 3225 return 0; 3226 } 3227 3228 /* 3229 * The HDA codec on NVIDIA Tegra contains two scratch registers that are 3230 * accessed using vendor-defined verbs. These registers can be used for 3231 * interoperability between the HDA and HDMI drivers. 3232 */ 3233 3234 /* Audio Function Group node */ 3235 #define NVIDIA_AFG_NID 0x01 3236 3237 /* 3238 * The SCRATCH0 register is used to notify the HDMI codec of changes in audio 3239 * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to 3240 * be raised in the HDMI codec. The remainder of the bits is arbitrary. This 3241 * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an 3242 * additional bit (at position 30) to signal the validity of the format. 3243 * 3244 * | 31 | 30 | 29 16 | 15 0 | 3245 * +---------+-------+--------+--------+ 3246 * | TRIGGER | VALID | UNUSED | FORMAT | 3247 * +-----------------------------------| 3248 * 3249 * Note that for the trigger bit to take effect it needs to change value 3250 * (i.e. it needs to be toggled). 3251 */ 3252 #define NVIDIA_GET_SCRATCH0 0xfa6 3253 #define NVIDIA_SET_SCRATCH0_BYTE0 0xfa7 3254 #define NVIDIA_SET_SCRATCH0_BYTE1 0xfa8 3255 #define NVIDIA_SET_SCRATCH0_BYTE2 0xfa9 3256 #define NVIDIA_SET_SCRATCH0_BYTE3 0xfaa 3257 #define NVIDIA_SCRATCH_TRIGGER (1 << 7) 3258 #define NVIDIA_SCRATCH_VALID (1 << 6) 3259 3260 #define NVIDIA_GET_SCRATCH1 0xfab 3261 #define NVIDIA_SET_SCRATCH1_BYTE0 0xfac 3262 #define NVIDIA_SET_SCRATCH1_BYTE1 0xfad 3263 #define NVIDIA_SET_SCRATCH1_BYTE2 0xfae 3264 #define NVIDIA_SET_SCRATCH1_BYTE3 0xfaf 3265 3266 /* 3267 * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0, 3268 * the format is invalidated so that the HDMI codec can be disabled. 3269 */ 3270 static void tegra_hdmi_set_format(struct hda_codec *codec, unsigned int format) 3271 { 3272 unsigned int value; 3273 3274 /* bits [31:30] contain the trigger and valid bits */ 3275 value = snd_hda_codec_read(codec, NVIDIA_AFG_NID, 0, 3276 NVIDIA_GET_SCRATCH0, 0); 3277 value = (value >> 24) & 0xff; 3278 3279 /* bits [15:0] are used to store the HDA format */ 3280 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, 3281 NVIDIA_SET_SCRATCH0_BYTE0, 3282 (format >> 0) & 0xff); 3283 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, 3284 NVIDIA_SET_SCRATCH0_BYTE1, 3285 (format >> 8) & 0xff); 3286 3287 /* bits [16:24] are unused */ 3288 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, 3289 NVIDIA_SET_SCRATCH0_BYTE2, 0); 3290 3291 /* 3292 * Bit 30 signals that the data is valid and hence that HDMI audio can 3293 * be enabled. 3294 */ 3295 if (format == 0) 3296 value &= ~NVIDIA_SCRATCH_VALID; 3297 else 3298 value |= NVIDIA_SCRATCH_VALID; 3299 3300 /* 3301 * Whenever the trigger bit is toggled, an interrupt is raised in the 3302 * HDMI codec. The HDMI driver will use that as trigger to update its 3303 * configuration. 3304 */ 3305 value ^= NVIDIA_SCRATCH_TRIGGER; 3306 3307 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, 3308 NVIDIA_SET_SCRATCH0_BYTE3, value); 3309 } 3310 3311 static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo, 3312 struct hda_codec *codec, 3313 unsigned int stream_tag, 3314 unsigned int format, 3315 struct snd_pcm_substream *substream) 3316 { 3317 int err; 3318 3319 err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag, 3320 format, substream); 3321 if (err < 0) 3322 return err; 3323 3324 /* notify the HDMI codec of the format change */ 3325 tegra_hdmi_set_format(codec, format); 3326 3327 return 0; 3328 } 3329 3330 static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo, 3331 struct hda_codec *codec, 3332 struct snd_pcm_substream *substream) 3333 { 3334 /* invalidate the format in the HDMI codec */ 3335 tegra_hdmi_set_format(codec, 0); 3336 3337 return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream); 3338 } 3339 3340 static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type) 3341 { 3342 struct hdmi_spec *spec = codec->spec; 3343 unsigned int i; 3344 3345 for (i = 0; i < spec->num_pins; i++) { 3346 struct hda_pcm *pcm = get_pcm_rec(spec, i); 3347 3348 if (pcm->pcm_type == type) 3349 return pcm; 3350 } 3351 3352 return NULL; 3353 } 3354 3355 static int tegra_hdmi_build_pcms(struct hda_codec *codec) 3356 { 3357 struct hda_pcm_stream *stream; 3358 struct hda_pcm *pcm; 3359 int err; 3360 3361 err = generic_hdmi_build_pcms(codec); 3362 if (err < 0) 3363 return err; 3364 3365 pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI); 3366 if (!pcm) 3367 return -ENODEV; 3368 3369 /* 3370 * Override ->prepare() and ->cleanup() operations to notify the HDMI 3371 * codec about format changes. 3372 */ 3373 stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK]; 3374 stream->ops.prepare = tegra_hdmi_pcm_prepare; 3375 stream->ops.cleanup = tegra_hdmi_pcm_cleanup; 3376 3377 return 0; 3378 } 3379 3380 static int patch_tegra_hdmi(struct hda_codec *codec) 3381 { 3382 int err; 3383 3384 err = patch_generic_hdmi(codec); 3385 if (err) 3386 return err; 3387 3388 codec->patch_ops.build_pcms = tegra_hdmi_build_pcms; 3389 3390 return 0; 3391 } 3392 3393 /* 3394 * ATI/AMD-specific implementations 3395 */ 3396 3397 #define is_amdhdmi_rev3_or_later(codec) \ 3398 ((codec)->core.vendor_id == 0x1002aa01 && \ 3399 ((codec)->core.revision_id & 0xff00) >= 0x0300) 3400 #define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec) 3401 3402 /* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */ 3403 #define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771 3404 #define ATI_VERB_SET_DOWNMIX_INFO 0x772 3405 #define ATI_VERB_SET_MULTICHANNEL_01 0x777 3406 #define ATI_VERB_SET_MULTICHANNEL_23 0x778 3407 #define ATI_VERB_SET_MULTICHANNEL_45 0x779 3408 #define ATI_VERB_SET_MULTICHANNEL_67 0x77a 3409 #define ATI_VERB_SET_HBR_CONTROL 0x77c 3410 #define ATI_VERB_SET_MULTICHANNEL_1 0x785 3411 #define ATI_VERB_SET_MULTICHANNEL_3 0x786 3412 #define ATI_VERB_SET_MULTICHANNEL_5 0x787 3413 #define ATI_VERB_SET_MULTICHANNEL_7 0x788 3414 #define ATI_VERB_SET_MULTICHANNEL_MODE 0x789 3415 #define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71 3416 #define ATI_VERB_GET_DOWNMIX_INFO 0xf72 3417 #define ATI_VERB_GET_MULTICHANNEL_01 0xf77 3418 #define ATI_VERB_GET_MULTICHANNEL_23 0xf78 3419 #define ATI_VERB_GET_MULTICHANNEL_45 0xf79 3420 #define ATI_VERB_GET_MULTICHANNEL_67 0xf7a 3421 #define ATI_VERB_GET_HBR_CONTROL 0xf7c 3422 #define ATI_VERB_GET_MULTICHANNEL_1 0xf85 3423 #define ATI_VERB_GET_MULTICHANNEL_3 0xf86 3424 #define ATI_VERB_GET_MULTICHANNEL_5 0xf87 3425 #define ATI_VERB_GET_MULTICHANNEL_7 0xf88 3426 #define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89 3427 3428 /* AMD specific HDA cvt verbs */ 3429 #define ATI_VERB_SET_RAMP_RATE 0x770 3430 #define ATI_VERB_GET_RAMP_RATE 0xf70 3431 3432 #define ATI_OUT_ENABLE 0x1 3433 3434 #define ATI_MULTICHANNEL_MODE_PAIRED 0 3435 #define ATI_MULTICHANNEL_MODE_SINGLE 1 3436 3437 #define ATI_HBR_CAPABLE 0x01 3438 #define ATI_HBR_ENABLE 0x10 3439 3440 static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid, 3441 unsigned char *buf, int *eld_size) 3442 { 3443 /* call hda_eld.c ATI/AMD-specific function */ 3444 return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size, 3445 is_amdhdmi_rev3_or_later(codec)); 3446 } 3447 3448 static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, hda_nid_t pin_nid, int ca, 3449 int active_channels, int conn_type) 3450 { 3451 snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca); 3452 } 3453 3454 static int atihdmi_paired_swap_fc_lfe(int pos) 3455 { 3456 /* 3457 * ATI/AMD have automatic FC/LFE swap built-in 3458 * when in pairwise mapping mode. 3459 */ 3460 3461 switch (pos) { 3462 /* see channel_allocations[].speakers[] */ 3463 case 2: return 3; 3464 case 3: return 2; 3465 default: break; 3466 } 3467 3468 return pos; 3469 } 3470 3471 static int atihdmi_paired_chmap_validate(struct hdac_chmap *chmap, 3472 int ca, int chs, unsigned char *map) 3473 { 3474 struct hdac_cea_channel_speaker_allocation *cap; 3475 int i, j; 3476 3477 /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */ 3478 3479 cap = snd_hdac_get_ch_alloc_from_ca(ca); 3480 for (i = 0; i < chs; ++i) { 3481 int mask = snd_hdac_chmap_to_spk_mask(map[i]); 3482 bool ok = false; 3483 bool companion_ok = false; 3484 3485 if (!mask) 3486 continue; 3487 3488 for (j = 0 + i % 2; j < 8; j += 2) { 3489 int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j); 3490 if (cap->speakers[chan_idx] == mask) { 3491 /* channel is in a supported position */ 3492 ok = true; 3493 3494 if (i % 2 == 0 && i + 1 < chs) { 3495 /* even channel, check the odd companion */ 3496 int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1); 3497 int comp_mask_req = snd_hdac_chmap_to_spk_mask(map[i+1]); 3498 int comp_mask_act = cap->speakers[comp_chan_idx]; 3499 3500 if (comp_mask_req == comp_mask_act) 3501 companion_ok = true; 3502 else 3503 return -EINVAL; 3504 } 3505 break; 3506 } 3507 } 3508 3509 if (!ok) 3510 return -EINVAL; 3511 3512 if (companion_ok) 3513 i++; /* companion channel already checked */ 3514 } 3515 3516 return 0; 3517 } 3518 3519 static int atihdmi_pin_set_slot_channel(struct hdac_device *hdac, 3520 hda_nid_t pin_nid, int hdmi_slot, int stream_channel) 3521 { 3522 struct hda_codec *codec = container_of(hdac, struct hda_codec, core); 3523 int verb; 3524 int ati_channel_setup = 0; 3525 3526 if (hdmi_slot > 7) 3527 return -EINVAL; 3528 3529 if (!has_amd_full_remap_support(codec)) { 3530 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot); 3531 3532 /* In case this is an odd slot but without stream channel, do not 3533 * disable the slot since the corresponding even slot could have a 3534 * channel. In case neither have a channel, the slot pair will be 3535 * disabled when this function is called for the even slot. */ 3536 if (hdmi_slot % 2 != 0 && stream_channel == 0xf) 3537 return 0; 3538 3539 hdmi_slot -= hdmi_slot % 2; 3540 3541 if (stream_channel != 0xf) 3542 stream_channel -= stream_channel % 2; 3543 } 3544 3545 verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e; 3546 3547 /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */ 3548 3549 if (stream_channel != 0xf) 3550 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE; 3551 3552 return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup); 3553 } 3554 3555 static int atihdmi_pin_get_slot_channel(struct hdac_device *hdac, 3556 hda_nid_t pin_nid, int asp_slot) 3557 { 3558 struct hda_codec *codec = container_of(hdac, struct hda_codec, core); 3559 bool was_odd = false; 3560 int ati_asp_slot = asp_slot; 3561 int verb; 3562 int ati_channel_setup; 3563 3564 if (asp_slot > 7) 3565 return -EINVAL; 3566 3567 if (!has_amd_full_remap_support(codec)) { 3568 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot); 3569 if (ati_asp_slot % 2 != 0) { 3570 ati_asp_slot -= 1; 3571 was_odd = true; 3572 } 3573 } 3574 3575 verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e; 3576 3577 ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0); 3578 3579 if (!(ati_channel_setup & ATI_OUT_ENABLE)) 3580 return 0xf; 3581 3582 return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd; 3583 } 3584 3585 static int atihdmi_paired_chmap_cea_alloc_validate_get_type( 3586 struct hdac_chmap *chmap, 3587 struct hdac_cea_channel_speaker_allocation *cap, 3588 int channels) 3589 { 3590 int c; 3591 3592 /* 3593 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so 3594 * we need to take that into account (a single channel may take 2 3595 * channel slots if we need to carry a silent channel next to it). 3596 * On Rev3+ AMD codecs this function is not used. 3597 */ 3598 int chanpairs = 0; 3599 3600 /* We only produce even-numbered channel count TLVs */ 3601 if ((channels % 2) != 0) 3602 return -1; 3603 3604 for (c = 0; c < 7; c += 2) { 3605 if (cap->speakers[c] || cap->speakers[c+1]) 3606 chanpairs++; 3607 } 3608 3609 if (chanpairs * 2 != channels) 3610 return -1; 3611 3612 return SNDRV_CTL_TLVT_CHMAP_PAIRED; 3613 } 3614 3615 static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct hdac_chmap *hchmap, 3616 struct hdac_cea_channel_speaker_allocation *cap, 3617 unsigned int *chmap, int channels) 3618 { 3619 /* produce paired maps for pre-rev3 ATI/AMD codecs */ 3620 int count = 0; 3621 int c; 3622 3623 for (c = 7; c >= 0; c--) { 3624 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c); 3625 int spk = cap->speakers[chan]; 3626 if (!spk) { 3627 /* add N/A channel if the companion channel is occupied */ 3628 if (cap->speakers[chan + (chan % 2 ? -1 : 1)]) 3629 chmap[count++] = SNDRV_CHMAP_NA; 3630 3631 continue; 3632 } 3633 3634 chmap[count++] = snd_hdac_spk_to_chmap(spk); 3635 } 3636 3637 WARN_ON(count != channels); 3638 } 3639 3640 static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid, 3641 bool hbr) 3642 { 3643 int hbr_ctl, hbr_ctl_new; 3644 3645 hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0); 3646 if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) { 3647 if (hbr) 3648 hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE; 3649 else 3650 hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE; 3651 3652 codec_dbg(codec, 3653 "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n", 3654 pin_nid, 3655 hbr_ctl == hbr_ctl_new ? "" : "new-", 3656 hbr_ctl_new); 3657 3658 if (hbr_ctl != hbr_ctl_new) 3659 snd_hda_codec_write(codec, pin_nid, 0, 3660 ATI_VERB_SET_HBR_CONTROL, 3661 hbr_ctl_new); 3662 3663 } else if (hbr) 3664 return -EINVAL; 3665 3666 return 0; 3667 } 3668 3669 static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, 3670 hda_nid_t pin_nid, u32 stream_tag, int format) 3671 { 3672 3673 if (is_amdhdmi_rev3_or_later(codec)) { 3674 int ramp_rate = 180; /* default as per AMD spec */ 3675 /* disable ramp-up/down for non-pcm as per AMD spec */ 3676 if (format & AC_FMT_TYPE_NON_PCM) 3677 ramp_rate = 0; 3678 3679 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate); 3680 } 3681 3682 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format); 3683 } 3684 3685 3686 static int atihdmi_init(struct hda_codec *codec) 3687 { 3688 struct hdmi_spec *spec = codec->spec; 3689 int pin_idx, err; 3690 3691 err = generic_hdmi_init(codec); 3692 3693 if (err) 3694 return err; 3695 3696 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 3697 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 3698 3699 /* make sure downmix information in infoframe is zero */ 3700 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0); 3701 3702 /* enable channel-wise remap mode if supported */ 3703 if (has_amd_full_remap_support(codec)) 3704 snd_hda_codec_write(codec, per_pin->pin_nid, 0, 3705 ATI_VERB_SET_MULTICHANNEL_MODE, 3706 ATI_MULTICHANNEL_MODE_SINGLE); 3707 } 3708 3709 return 0; 3710 } 3711 3712 static int patch_atihdmi(struct hda_codec *codec) 3713 { 3714 struct hdmi_spec *spec; 3715 struct hdmi_spec_per_cvt *per_cvt; 3716 int err, cvt_idx; 3717 3718 err = patch_generic_hdmi(codec); 3719 3720 if (err) 3721 return err; 3722 3723 codec->patch_ops.init = atihdmi_init; 3724 3725 spec = codec->spec; 3726 3727 spec->ops.pin_get_eld = atihdmi_pin_get_eld; 3728 spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe; 3729 spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup; 3730 spec->ops.setup_stream = atihdmi_setup_stream; 3731 3732 spec->chmap.ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel; 3733 spec->chmap.ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel; 3734 3735 if (!has_amd_full_remap_support(codec)) { 3736 /* override to ATI/AMD-specific versions with pairwise mapping */ 3737 spec->chmap.ops.chmap_cea_alloc_validate_get_type = 3738 atihdmi_paired_chmap_cea_alloc_validate_get_type; 3739 spec->chmap.ops.cea_alloc_to_tlv_chmap = 3740 atihdmi_paired_cea_alloc_to_tlv_chmap; 3741 spec->chmap.ops.chmap_validate = atihdmi_paired_chmap_validate; 3742 } 3743 3744 /* ATI/AMD converters do not advertise all of their capabilities */ 3745 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { 3746 per_cvt = get_cvt(spec, cvt_idx); 3747 per_cvt->channels_max = max(per_cvt->channels_max, 8u); 3748 per_cvt->rates |= SUPPORTED_RATES; 3749 per_cvt->formats |= SUPPORTED_FORMATS; 3750 per_cvt->maxbps = max(per_cvt->maxbps, 24u); 3751 } 3752 3753 spec->chmap.channels_max = max(spec->chmap.channels_max, 8u); 3754 3755 /* AMD GPUs have neither EPSS nor CLKSTOP bits, hence preventing 3756 * the link-down as is. Tell the core to allow it. 3757 */ 3758 codec->link_down_at_suspend = 1; 3759 3760 return 0; 3761 } 3762 3763 /* VIA HDMI Implementation */ 3764 #define VIAHDMI_CVT_NID 0x02 /* audio converter1 */ 3765 #define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */ 3766 3767 static int patch_via_hdmi(struct hda_codec *codec) 3768 { 3769 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID); 3770 } 3771 3772 /* 3773 * patch entries 3774 */ 3775 static const struct hda_device_id snd_hda_id_hdmi[] = { 3776 HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI", patch_atihdmi), 3777 HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI", patch_atihdmi), 3778 HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI", patch_atihdmi), 3779 HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI", patch_atihdmi), 3780 HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI", patch_generic_hdmi), 3781 HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI", patch_generic_hdmi), 3782 HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI", patch_generic_hdmi), 3783 HDA_CODEC_ENTRY(0x10de0001, "MCP73 HDMI", patch_nvhdmi_2ch), 3784 HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 3785 HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 3786 HDA_CODEC_ENTRY(0x10de0004, "GPU 04 HDMI", patch_nvhdmi_8ch_7x), 3787 HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 3788 HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 3789 HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI", patch_nvhdmi_8ch_7x), 3790 HDA_CODEC_ENTRY(0x10de0008, "GPU 08 HDMI/DP", patch_nvhdmi), 3791 HDA_CODEC_ENTRY(0x10de0009, "GPU 09 HDMI/DP", patch_nvhdmi), 3792 HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP", patch_nvhdmi), 3793 HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP", patch_nvhdmi), 3794 HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI", patch_nvhdmi), 3795 HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP", patch_nvhdmi), 3796 HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP", patch_nvhdmi), 3797 HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP", patch_nvhdmi), 3798 HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP", patch_nvhdmi), 3799 HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP", patch_nvhdmi), 3800 HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP", patch_nvhdmi), 3801 HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP", patch_nvhdmi), 3802 HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP", patch_nvhdmi), 3803 /* 17 is known to be absent */ 3804 HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP", patch_nvhdmi), 3805 HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP", patch_nvhdmi), 3806 HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP", patch_nvhdmi), 3807 HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP", patch_nvhdmi), 3808 HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP", patch_nvhdmi), 3809 HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI", patch_tegra_hdmi), 3810 HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI", patch_tegra_hdmi), 3811 HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI", patch_tegra_hdmi), 3812 HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi), 3813 HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP", patch_nvhdmi), 3814 HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP", patch_nvhdmi), 3815 HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi), 3816 HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP", patch_nvhdmi), 3817 HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP", patch_nvhdmi), 3818 HDA_CODEC_ENTRY(0x10de0045, "GPU 45 HDMI/DP", patch_nvhdmi), 3819 HDA_CODEC_ENTRY(0x10de0050, "GPU 50 HDMI/DP", patch_nvhdmi), 3820 HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP", patch_nvhdmi), 3821 HDA_CODEC_ENTRY(0x10de0052, "GPU 52 HDMI/DP", patch_nvhdmi), 3822 HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP", patch_nvhdmi), 3823 HDA_CODEC_ENTRY(0x10de0061, "GPU 61 HDMI/DP", patch_nvhdmi), 3824 HDA_CODEC_ENTRY(0x10de0062, "GPU 62 HDMI/DP", patch_nvhdmi), 3825 HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI", patch_nvhdmi_2ch), 3826 HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP", patch_nvhdmi), 3827 HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP", patch_nvhdmi), 3828 HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP", patch_nvhdmi), 3829 HDA_CODEC_ENTRY(0x10de0073, "GPU 73 HDMI/DP", patch_nvhdmi), 3830 HDA_CODEC_ENTRY(0x10de0074, "GPU 74 HDMI/DP", patch_nvhdmi), 3831 HDA_CODEC_ENTRY(0x10de0076, "GPU 76 HDMI/DP", patch_nvhdmi), 3832 HDA_CODEC_ENTRY(0x10de007b, "GPU 7b HDMI/DP", patch_nvhdmi), 3833 HDA_CODEC_ENTRY(0x10de007c, "GPU 7c HDMI/DP", patch_nvhdmi), 3834 HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP", patch_nvhdmi), 3835 HDA_CODEC_ENTRY(0x10de007e, "GPU 7e HDMI/DP", patch_nvhdmi), 3836 HDA_CODEC_ENTRY(0x10de0080, "GPU 80 HDMI/DP", patch_nvhdmi), 3837 HDA_CODEC_ENTRY(0x10de0081, "GPU 81 HDMI/DP", patch_nvhdmi), 3838 HDA_CODEC_ENTRY(0x10de0082, "GPU 82 HDMI/DP", patch_nvhdmi), 3839 HDA_CODEC_ENTRY(0x10de0083, "GPU 83 HDMI/DP", patch_nvhdmi), 3840 HDA_CODEC_ENTRY(0x10de0084, "GPU 84 HDMI/DP", patch_nvhdmi), 3841 HDA_CODEC_ENTRY(0x10de0090, "GPU 90 HDMI/DP", patch_nvhdmi), 3842 HDA_CODEC_ENTRY(0x10de0091, "GPU 91 HDMI/DP", patch_nvhdmi), 3843 HDA_CODEC_ENTRY(0x10de0092, "GPU 92 HDMI/DP", patch_nvhdmi), 3844 HDA_CODEC_ENTRY(0x10de0093, "GPU 93 HDMI/DP", patch_nvhdmi), 3845 HDA_CODEC_ENTRY(0x10de0094, "GPU 94 HDMI/DP", patch_nvhdmi), 3846 HDA_CODEC_ENTRY(0x10de0095, "GPU 95 HDMI/DP", patch_nvhdmi), 3847 HDA_CODEC_ENTRY(0x10de0097, "GPU 97 HDMI/DP", patch_nvhdmi), 3848 HDA_CODEC_ENTRY(0x10de0098, "GPU 98 HDMI/DP", patch_nvhdmi), 3849 HDA_CODEC_ENTRY(0x10de0099, "GPU 99 HDMI/DP", patch_nvhdmi), 3850 HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI", patch_nvhdmi_2ch), 3851 HDA_CODEC_ENTRY(0x10de8067, "MCP67/68 HDMI", patch_nvhdmi_2ch), 3852 HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP", patch_via_hdmi), 3853 HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP", patch_via_hdmi), 3854 HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP", patch_generic_hdmi), 3855 HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP", patch_generic_hdmi), 3856 HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI", patch_i915_cpt_hdmi), 3857 HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI", patch_generic_hdmi), 3858 HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI", patch_generic_hdmi), 3859 HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI", patch_generic_hdmi), 3860 HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI", patch_i915_cpt_hdmi), 3861 HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_i915_cpt_hdmi), 3862 HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_i915_cpt_hdmi), 3863 HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI", patch_i915_hsw_hdmi), 3864 HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI", patch_i915_hsw_hdmi), 3865 HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI", patch_i915_hsw_hdmi), 3866 HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI", patch_i915_hsw_hdmi), 3867 HDA_CODEC_ENTRY(0x8086280b, "Kabylake HDMI", patch_i915_hsw_hdmi), 3868 HDA_CODEC_ENTRY(0x8086280c, "Cannonlake HDMI", patch_i915_glk_hdmi), 3869 HDA_CODEC_ENTRY(0x8086280d, "Geminilake HDMI", patch_i915_glk_hdmi), 3870 HDA_CODEC_ENTRY(0x80862800, "Geminilake HDMI", patch_i915_glk_hdmi), 3871 HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI", patch_generic_hdmi), 3872 HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_i915_byt_hdmi), 3873 HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI", patch_i915_byt_hdmi), 3874 HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI", patch_generic_hdmi), 3875 /* special ID for generic HDMI */ 3876 HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi), 3877 {} /* terminator */ 3878 }; 3879 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi); 3880 3881 MODULE_LICENSE("GPL"); 3882 MODULE_DESCRIPTION("HDMI HD-audio codec"); 3883 MODULE_ALIAS("snd-hda-codec-intelhdmi"); 3884 MODULE_ALIAS("snd-hda-codec-nvhdmi"); 3885 MODULE_ALIAS("snd-hda-codec-atihdmi"); 3886 3887 static struct hda_codec_driver hdmi_driver = { 3888 .id = snd_hda_id_hdmi, 3889 }; 3890 3891 module_hda_codec_driver(hdmi_driver); 3892