1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * 4 * patch_hdmi.c - routines for HDMI/DisplayPort codecs 5 * 6 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved. 7 * Copyright (c) 2006 ATI Technologies Inc. 8 * Copyright (c) 2008 NVIDIA Corp. All rights reserved. 9 * Copyright (c) 2008 Wei Ni <wni@nvidia.com> 10 * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi> 11 * 12 * Authors: 13 * Wu Fengguang <wfg@linux.intel.com> 14 * 15 * Maintained by: 16 * Wu Fengguang <wfg@linux.intel.com> 17 */ 18 19 #include <linux/init.h> 20 #include <linux/delay.h> 21 #include <linux/pci.h> 22 #include <linux/slab.h> 23 #include <linux/module.h> 24 #include <linux/pm_runtime.h> 25 #include <sound/core.h> 26 #include <sound/jack.h> 27 #include <sound/asoundef.h> 28 #include <sound/tlv.h> 29 #include <sound/hdaudio.h> 30 #include <sound/hda_i915.h> 31 #include <sound/hda_chmap.h> 32 #include <sound/hda_codec.h> 33 #include "hda_local.h" 34 #include "hda_jack.h" 35 #include "hda_controller.h" 36 37 static bool static_hdmi_pcm; 38 module_param(static_hdmi_pcm, bool, 0644); 39 MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info"); 40 41 struct hdmi_spec_per_cvt { 42 hda_nid_t cvt_nid; 43 int assigned; 44 unsigned int channels_min; 45 unsigned int channels_max; 46 u32 rates; 47 u64 formats; 48 unsigned int maxbps; 49 }; 50 51 /* max. connections to a widget */ 52 #define HDA_MAX_CONNECTIONS 32 53 54 struct hdmi_spec_per_pin { 55 hda_nid_t pin_nid; 56 int dev_id; 57 /* pin idx, different device entries on the same pin use the same idx */ 58 int pin_nid_idx; 59 int num_mux_nids; 60 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS]; 61 int mux_idx; 62 hda_nid_t cvt_nid; 63 64 struct hda_codec *codec; 65 struct hdmi_eld sink_eld; 66 struct mutex lock; 67 struct delayed_work work; 68 struct hdmi_pcm *pcm; /* pointer to spec->pcm_rec[n] dynamically*/ 69 int pcm_idx; /* which pcm is attached. -1 means no pcm is attached */ 70 int repoll_count; 71 bool setup; /* the stream has been set up by prepare callback */ 72 int channels; /* current number of channels */ 73 bool non_pcm; 74 bool chmap_set; /* channel-map override by ALSA API? */ 75 unsigned char chmap[8]; /* ALSA API channel-map */ 76 #ifdef CONFIG_SND_PROC_FS 77 struct snd_info_entry *proc_entry; 78 #endif 79 }; 80 81 /* operations used by generic code that can be overridden by patches */ 82 struct hdmi_ops { 83 int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid, 84 int dev_id, unsigned char *buf, int *eld_size); 85 86 void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid, 87 int dev_id, 88 int ca, int active_channels, int conn_type); 89 90 /* enable/disable HBR (HD passthrough) */ 91 int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, 92 int dev_id, bool hbr); 93 94 int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid, 95 hda_nid_t pin_nid, int dev_id, u32 stream_tag, 96 int format); 97 98 void (*pin_cvt_fixup)(struct hda_codec *codec, 99 struct hdmi_spec_per_pin *per_pin, 100 hda_nid_t cvt_nid); 101 }; 102 103 struct hdmi_pcm { 104 struct hda_pcm *pcm; 105 struct snd_jack *jack; 106 struct snd_kcontrol *eld_ctl; 107 }; 108 109 struct hdmi_spec { 110 struct hda_codec *codec; 111 int num_cvts; 112 struct snd_array cvts; /* struct hdmi_spec_per_cvt */ 113 hda_nid_t cvt_nids[4]; /* only for haswell fix */ 114 115 /* 116 * num_pins is the number of virtual pins 117 * for example, there are 3 pins, and each pin 118 * has 4 device entries, then the num_pins is 12 119 */ 120 int num_pins; 121 /* 122 * num_nids is the number of real pins 123 * In the above example, num_nids is 3 124 */ 125 int num_nids; 126 /* 127 * dev_num is the number of device entries 128 * on each pin. 129 * In the above example, dev_num is 4 130 */ 131 int dev_num; 132 struct snd_array pins; /* struct hdmi_spec_per_pin */ 133 struct hdmi_pcm pcm_rec[16]; 134 struct mutex pcm_lock; 135 struct mutex bind_lock; /* for audio component binding */ 136 /* pcm_bitmap means which pcms have been assigned to pins*/ 137 unsigned long pcm_bitmap; 138 int pcm_used; /* counter of pcm_rec[] */ 139 /* bitmap shows whether the pcm is opened in user space 140 * bit 0 means the first playback PCM (PCM3); 141 * bit 1 means the second playback PCM, and so on. 142 */ 143 unsigned long pcm_in_use; 144 145 struct hdmi_eld temp_eld; 146 struct hdmi_ops ops; 147 148 bool dyn_pin_out; 149 bool dyn_pcm_assign; 150 bool intel_hsw_fixup; /* apply Intel platform-specific fixups */ 151 /* 152 * Non-generic VIA/NVIDIA specific 153 */ 154 struct hda_multi_out multiout; 155 struct hda_pcm_stream pcm_playback; 156 157 bool use_jack_detect; /* jack detection enabled */ 158 bool use_acomp_notifier; /* use eld_notify callback for hotplug */ 159 bool acomp_registered; /* audio component registered in this driver */ 160 struct drm_audio_component_audio_ops drm_audio_ops; 161 int (*port2pin)(struct hda_codec *, int); /* reverse port/pin mapping */ 162 163 struct hdac_chmap chmap; 164 hda_nid_t vendor_nid; 165 const int *port_map; 166 int port_num; 167 }; 168 169 #ifdef CONFIG_SND_HDA_COMPONENT 170 static inline bool codec_has_acomp(struct hda_codec *codec) 171 { 172 struct hdmi_spec *spec = codec->spec; 173 return spec->use_acomp_notifier; 174 } 175 #else 176 #define codec_has_acomp(codec) false 177 #endif 178 179 struct hdmi_audio_infoframe { 180 u8 type; /* 0x84 */ 181 u8 ver; /* 0x01 */ 182 u8 len; /* 0x0a */ 183 184 u8 checksum; 185 186 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */ 187 u8 SS01_SF24; 188 u8 CXT04; 189 u8 CA; 190 u8 LFEPBL01_LSV36_DM_INH7; 191 }; 192 193 struct dp_audio_infoframe { 194 u8 type; /* 0x84 */ 195 u8 len; /* 0x1b */ 196 u8 ver; /* 0x11 << 2 */ 197 198 u8 CC02_CT47; /* match with HDMI infoframe from this on */ 199 u8 SS01_SF24; 200 u8 CXT04; 201 u8 CA; 202 u8 LFEPBL01_LSV36_DM_INH7; 203 }; 204 205 union audio_infoframe { 206 struct hdmi_audio_infoframe hdmi; 207 struct dp_audio_infoframe dp; 208 u8 bytes[0]; 209 }; 210 211 /* 212 * HDMI routines 213 */ 214 215 #define get_pin(spec, idx) \ 216 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx)) 217 #define get_cvt(spec, idx) \ 218 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx)) 219 /* obtain hdmi_pcm object assigned to idx */ 220 #define get_hdmi_pcm(spec, idx) (&(spec)->pcm_rec[idx]) 221 /* obtain hda_pcm object assigned to idx */ 222 #define get_pcm_rec(spec, idx) (get_hdmi_pcm(spec, idx)->pcm) 223 224 static int pin_id_to_pin_index(struct hda_codec *codec, 225 hda_nid_t pin_nid, int dev_id) 226 { 227 struct hdmi_spec *spec = codec->spec; 228 int pin_idx; 229 struct hdmi_spec_per_pin *per_pin; 230 231 /* 232 * (dev_id == -1) means it is NON-MST pin 233 * return the first virtual pin on this port 234 */ 235 if (dev_id == -1) 236 dev_id = 0; 237 238 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 239 per_pin = get_pin(spec, pin_idx); 240 if ((per_pin->pin_nid == pin_nid) && 241 (per_pin->dev_id == dev_id)) 242 return pin_idx; 243 } 244 245 codec_warn(codec, "HDMI: pin nid %d not registered\n", pin_nid); 246 return -EINVAL; 247 } 248 249 static int hinfo_to_pcm_index(struct hda_codec *codec, 250 struct hda_pcm_stream *hinfo) 251 { 252 struct hdmi_spec *spec = codec->spec; 253 int pcm_idx; 254 255 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) 256 if (get_pcm_rec(spec, pcm_idx)->stream == hinfo) 257 return pcm_idx; 258 259 codec_warn(codec, "HDMI: hinfo %p not registered\n", hinfo); 260 return -EINVAL; 261 } 262 263 static int hinfo_to_pin_index(struct hda_codec *codec, 264 struct hda_pcm_stream *hinfo) 265 { 266 struct hdmi_spec *spec = codec->spec; 267 struct hdmi_spec_per_pin *per_pin; 268 int pin_idx; 269 270 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 271 per_pin = get_pin(spec, pin_idx); 272 if (per_pin->pcm && 273 per_pin->pcm->pcm->stream == hinfo) 274 return pin_idx; 275 } 276 277 codec_dbg(codec, "HDMI: hinfo %p not registered\n", hinfo); 278 return -EINVAL; 279 } 280 281 static struct hdmi_spec_per_pin *pcm_idx_to_pin(struct hdmi_spec *spec, 282 int pcm_idx) 283 { 284 int i; 285 struct hdmi_spec_per_pin *per_pin; 286 287 for (i = 0; i < spec->num_pins; i++) { 288 per_pin = get_pin(spec, i); 289 if (per_pin->pcm_idx == pcm_idx) 290 return per_pin; 291 } 292 return NULL; 293 } 294 295 static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid) 296 { 297 struct hdmi_spec *spec = codec->spec; 298 int cvt_idx; 299 300 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) 301 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid) 302 return cvt_idx; 303 304 codec_warn(codec, "HDMI: cvt nid %d not registered\n", cvt_nid); 305 return -EINVAL; 306 } 307 308 static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol, 309 struct snd_ctl_elem_info *uinfo) 310 { 311 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 312 struct hdmi_spec *spec = codec->spec; 313 struct hdmi_spec_per_pin *per_pin; 314 struct hdmi_eld *eld; 315 int pcm_idx; 316 317 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; 318 319 pcm_idx = kcontrol->private_value; 320 mutex_lock(&spec->pcm_lock); 321 per_pin = pcm_idx_to_pin(spec, pcm_idx); 322 if (!per_pin) { 323 /* no pin is bound to the pcm */ 324 uinfo->count = 0; 325 goto unlock; 326 } 327 eld = &per_pin->sink_eld; 328 uinfo->count = eld->eld_valid ? eld->eld_size : 0; 329 330 unlock: 331 mutex_unlock(&spec->pcm_lock); 332 return 0; 333 } 334 335 static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol, 336 struct snd_ctl_elem_value *ucontrol) 337 { 338 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 339 struct hdmi_spec *spec = codec->spec; 340 struct hdmi_spec_per_pin *per_pin; 341 struct hdmi_eld *eld; 342 int pcm_idx; 343 int err = 0; 344 345 pcm_idx = kcontrol->private_value; 346 mutex_lock(&spec->pcm_lock); 347 per_pin = pcm_idx_to_pin(spec, pcm_idx); 348 if (!per_pin) { 349 /* no pin is bound to the pcm */ 350 memset(ucontrol->value.bytes.data, 0, 351 ARRAY_SIZE(ucontrol->value.bytes.data)); 352 goto unlock; 353 } 354 355 eld = &per_pin->sink_eld; 356 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data) || 357 eld->eld_size > ELD_MAX_SIZE) { 358 snd_BUG(); 359 err = -EINVAL; 360 goto unlock; 361 } 362 363 memset(ucontrol->value.bytes.data, 0, 364 ARRAY_SIZE(ucontrol->value.bytes.data)); 365 if (eld->eld_valid) 366 memcpy(ucontrol->value.bytes.data, eld->eld_buffer, 367 eld->eld_size); 368 369 unlock: 370 mutex_unlock(&spec->pcm_lock); 371 return err; 372 } 373 374 static const struct snd_kcontrol_new eld_bytes_ctl = { 375 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, 376 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 377 .name = "ELD", 378 .info = hdmi_eld_ctl_info, 379 .get = hdmi_eld_ctl_get, 380 }; 381 382 static int hdmi_create_eld_ctl(struct hda_codec *codec, int pcm_idx, 383 int device) 384 { 385 struct snd_kcontrol *kctl; 386 struct hdmi_spec *spec = codec->spec; 387 int err; 388 389 kctl = snd_ctl_new1(&eld_bytes_ctl, codec); 390 if (!kctl) 391 return -ENOMEM; 392 kctl->private_value = pcm_idx; 393 kctl->id.device = device; 394 395 /* no pin nid is associated with the kctl now 396 * tbd: associate pin nid to eld ctl later 397 */ 398 err = snd_hda_ctl_add(codec, 0, kctl); 399 if (err < 0) 400 return err; 401 402 get_hdmi_pcm(spec, pcm_idx)->eld_ctl = kctl; 403 return 0; 404 } 405 406 #ifdef BE_PARANOID 407 static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid, 408 int *packet_index, int *byte_index) 409 { 410 int val; 411 412 val = snd_hda_codec_read(codec, pin_nid, 0, 413 AC_VERB_GET_HDMI_DIP_INDEX, 0); 414 415 *packet_index = val >> 5; 416 *byte_index = val & 0x1f; 417 } 418 #endif 419 420 static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid, 421 int packet_index, int byte_index) 422 { 423 int val; 424 425 val = (packet_index << 5) | (byte_index & 0x1f); 426 427 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val); 428 } 429 430 static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid, 431 unsigned char val) 432 { 433 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val); 434 } 435 436 static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid) 437 { 438 struct hdmi_spec *spec = codec->spec; 439 int pin_out; 440 441 /* Unmute */ 442 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP) 443 snd_hda_codec_write(codec, pin_nid, 0, 444 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE); 445 446 if (spec->dyn_pin_out) 447 /* Disable pin out until stream is active */ 448 pin_out = 0; 449 else 450 /* Enable pin out: some machines with GM965 gets broken output 451 * when the pin is disabled or changed while using with HDMI 452 */ 453 pin_out = PIN_OUT; 454 455 snd_hda_codec_write(codec, pin_nid, 0, 456 AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out); 457 } 458 459 /* 460 * ELD proc files 461 */ 462 463 #ifdef CONFIG_SND_PROC_FS 464 static void print_eld_info(struct snd_info_entry *entry, 465 struct snd_info_buffer *buffer) 466 { 467 struct hdmi_spec_per_pin *per_pin = entry->private_data; 468 469 mutex_lock(&per_pin->lock); 470 snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer); 471 mutex_unlock(&per_pin->lock); 472 } 473 474 static void write_eld_info(struct snd_info_entry *entry, 475 struct snd_info_buffer *buffer) 476 { 477 struct hdmi_spec_per_pin *per_pin = entry->private_data; 478 479 mutex_lock(&per_pin->lock); 480 snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer); 481 mutex_unlock(&per_pin->lock); 482 } 483 484 static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index) 485 { 486 char name[32]; 487 struct hda_codec *codec = per_pin->codec; 488 struct snd_info_entry *entry; 489 int err; 490 491 snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index); 492 err = snd_card_proc_new(codec->card, name, &entry); 493 if (err < 0) 494 return err; 495 496 snd_info_set_text_ops(entry, per_pin, print_eld_info); 497 entry->c.text.write = write_eld_info; 498 entry->mode |= 0200; 499 per_pin->proc_entry = entry; 500 501 return 0; 502 } 503 504 static void eld_proc_free(struct hdmi_spec_per_pin *per_pin) 505 { 506 if (!per_pin->codec->bus->shutdown) { 507 snd_info_free_entry(per_pin->proc_entry); 508 per_pin->proc_entry = NULL; 509 } 510 } 511 #else 512 static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin, 513 int index) 514 { 515 return 0; 516 } 517 static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin) 518 { 519 } 520 #endif 521 522 /* 523 * Audio InfoFrame routines 524 */ 525 526 /* 527 * Enable Audio InfoFrame Transmission 528 */ 529 static void hdmi_start_infoframe_trans(struct hda_codec *codec, 530 hda_nid_t pin_nid) 531 { 532 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 533 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT, 534 AC_DIPXMIT_BEST); 535 } 536 537 /* 538 * Disable Audio InfoFrame Transmission 539 */ 540 static void hdmi_stop_infoframe_trans(struct hda_codec *codec, 541 hda_nid_t pin_nid) 542 { 543 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 544 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT, 545 AC_DIPXMIT_DISABLE); 546 } 547 548 static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid) 549 { 550 #ifdef CONFIG_SND_DEBUG_VERBOSE 551 int i; 552 int size; 553 554 size = snd_hdmi_get_eld_size(codec, pin_nid); 555 codec_dbg(codec, "HDMI: ELD buf size is %d\n", size); 556 557 for (i = 0; i < 8; i++) { 558 size = snd_hda_codec_read(codec, pin_nid, 0, 559 AC_VERB_GET_HDMI_DIP_SIZE, i); 560 codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size); 561 } 562 #endif 563 } 564 565 static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid) 566 { 567 #ifdef BE_PARANOID 568 int i, j; 569 int size; 570 int pi, bi; 571 for (i = 0; i < 8; i++) { 572 size = snd_hda_codec_read(codec, pin_nid, 0, 573 AC_VERB_GET_HDMI_DIP_SIZE, i); 574 if (size == 0) 575 continue; 576 577 hdmi_set_dip_index(codec, pin_nid, i, 0x0); 578 for (j = 1; j < 1000; j++) { 579 hdmi_write_dip_byte(codec, pin_nid, 0x0); 580 hdmi_get_dip_index(codec, pin_nid, &pi, &bi); 581 if (pi != i) 582 codec_dbg(codec, "dip index %d: %d != %d\n", 583 bi, pi, i); 584 if (bi == 0) /* byte index wrapped around */ 585 break; 586 } 587 codec_dbg(codec, 588 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n", 589 i, size, j); 590 } 591 #endif 592 } 593 594 static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai) 595 { 596 u8 *bytes = (u8 *)hdmi_ai; 597 u8 sum = 0; 598 int i; 599 600 hdmi_ai->checksum = 0; 601 602 for (i = 0; i < sizeof(*hdmi_ai); i++) 603 sum += bytes[i]; 604 605 hdmi_ai->checksum = -sum; 606 } 607 608 static void hdmi_fill_audio_infoframe(struct hda_codec *codec, 609 hda_nid_t pin_nid, 610 u8 *dip, int size) 611 { 612 int i; 613 614 hdmi_debug_dip_size(codec, pin_nid); 615 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */ 616 617 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 618 for (i = 0; i < size; i++) 619 hdmi_write_dip_byte(codec, pin_nid, dip[i]); 620 } 621 622 static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid, 623 u8 *dip, int size) 624 { 625 u8 val; 626 int i; 627 628 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0) 629 != AC_DIPXMIT_BEST) 630 return false; 631 632 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 633 for (i = 0; i < size; i++) { 634 val = snd_hda_codec_read(codec, pin_nid, 0, 635 AC_VERB_GET_HDMI_DIP_DATA, 0); 636 if (val != dip[i]) 637 return false; 638 } 639 640 return true; 641 } 642 643 static int hdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid, 644 int dev_id, unsigned char *buf, int *eld_size) 645 { 646 snd_hda_set_dev_select(codec, nid, dev_id); 647 648 return snd_hdmi_get_eld(codec, nid, buf, eld_size); 649 } 650 651 static void hdmi_pin_setup_infoframe(struct hda_codec *codec, 652 hda_nid_t pin_nid, int dev_id, 653 int ca, int active_channels, 654 int conn_type) 655 { 656 union audio_infoframe ai; 657 658 memset(&ai, 0, sizeof(ai)); 659 if (conn_type == 0) { /* HDMI */ 660 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi; 661 662 hdmi_ai->type = 0x84; 663 hdmi_ai->ver = 0x01; 664 hdmi_ai->len = 0x0a; 665 hdmi_ai->CC02_CT47 = active_channels - 1; 666 hdmi_ai->CA = ca; 667 hdmi_checksum_audio_infoframe(hdmi_ai); 668 } else if (conn_type == 1) { /* DisplayPort */ 669 struct dp_audio_infoframe *dp_ai = &ai.dp; 670 671 dp_ai->type = 0x84; 672 dp_ai->len = 0x1b; 673 dp_ai->ver = 0x11 << 2; 674 dp_ai->CC02_CT47 = active_channels - 1; 675 dp_ai->CA = ca; 676 } else { 677 codec_dbg(codec, "HDMI: unknown connection type at pin %d\n", 678 pin_nid); 679 return; 680 } 681 682 snd_hda_set_dev_select(codec, pin_nid, dev_id); 683 684 /* 685 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or 686 * sizeof(*dp_ai) to avoid partial match/update problems when 687 * the user switches between HDMI/DP monitors. 688 */ 689 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes, 690 sizeof(ai))) { 691 codec_dbg(codec, 692 "hdmi_pin_setup_infoframe: pin=%d channels=%d ca=0x%02x\n", 693 pin_nid, 694 active_channels, ca); 695 hdmi_stop_infoframe_trans(codec, pin_nid); 696 hdmi_fill_audio_infoframe(codec, pin_nid, 697 ai.bytes, sizeof(ai)); 698 hdmi_start_infoframe_trans(codec, pin_nid); 699 } 700 } 701 702 static void hdmi_setup_audio_infoframe(struct hda_codec *codec, 703 struct hdmi_spec_per_pin *per_pin, 704 bool non_pcm) 705 { 706 struct hdmi_spec *spec = codec->spec; 707 struct hdac_chmap *chmap = &spec->chmap; 708 hda_nid_t pin_nid = per_pin->pin_nid; 709 int dev_id = per_pin->dev_id; 710 int channels = per_pin->channels; 711 int active_channels; 712 struct hdmi_eld *eld; 713 int ca; 714 715 if (!channels) 716 return; 717 718 snd_hda_set_dev_select(codec, pin_nid, dev_id); 719 720 /* some HW (e.g. HSW+) needs reprogramming the amp at each time */ 721 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP) 722 snd_hda_codec_write(codec, pin_nid, 0, 723 AC_VERB_SET_AMP_GAIN_MUTE, 724 AMP_OUT_UNMUTE); 725 726 eld = &per_pin->sink_eld; 727 728 ca = snd_hdac_channel_allocation(&codec->core, 729 eld->info.spk_alloc, channels, 730 per_pin->chmap_set, non_pcm, per_pin->chmap); 731 732 active_channels = snd_hdac_get_active_channels(ca); 733 734 chmap->ops.set_channel_count(&codec->core, per_pin->cvt_nid, 735 active_channels); 736 737 /* 738 * always configure channel mapping, it may have been changed by the 739 * user in the meantime 740 */ 741 snd_hdac_setup_channel_mapping(&spec->chmap, 742 pin_nid, non_pcm, ca, channels, 743 per_pin->chmap, per_pin->chmap_set); 744 745 spec->ops.pin_setup_infoframe(codec, pin_nid, dev_id, 746 ca, active_channels, eld->info.conn_type); 747 748 per_pin->non_pcm = non_pcm; 749 } 750 751 /* 752 * Unsolicited events 753 */ 754 755 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll); 756 757 static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid, 758 int dev_id) 759 { 760 struct hdmi_spec *spec = codec->spec; 761 int pin_idx = pin_id_to_pin_index(codec, nid, dev_id); 762 763 if (pin_idx < 0) 764 return; 765 mutex_lock(&spec->pcm_lock); 766 if (hdmi_present_sense(get_pin(spec, pin_idx), 1)) 767 snd_hda_jack_report_sync(codec); 768 mutex_unlock(&spec->pcm_lock); 769 } 770 771 static void jack_callback(struct hda_codec *codec, 772 struct hda_jack_callback *jack) 773 { 774 /* stop polling when notification is enabled */ 775 if (codec_has_acomp(codec)) 776 return; 777 778 check_presence_and_report(codec, jack->nid, jack->dev_id); 779 } 780 781 static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res) 782 { 783 int tag = res >> AC_UNSOL_RES_TAG_SHIFT; 784 struct hda_jack_tbl *jack; 785 786 if (codec->dp_mst) { 787 int dev_entry = 788 (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT; 789 790 jack = snd_hda_jack_tbl_get_from_tag(codec, tag, dev_entry); 791 } else { 792 jack = snd_hda_jack_tbl_get_from_tag(codec, tag, 0); 793 } 794 if (!jack) 795 return; 796 jack->jack_dirty = 1; 797 798 codec_dbg(codec, 799 "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n", 800 codec->addr, jack->nid, jack->dev_id, !!(res & AC_UNSOL_RES_IA), 801 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV)); 802 803 check_presence_and_report(codec, jack->nid, jack->dev_id); 804 } 805 806 static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res) 807 { 808 int tag = res >> AC_UNSOL_RES_TAG_SHIFT; 809 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT; 810 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE); 811 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY); 812 813 codec_info(codec, 814 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n", 815 codec->addr, 816 tag, 817 subtag, 818 cp_state, 819 cp_ready); 820 821 /* TODO */ 822 if (cp_state) 823 ; 824 if (cp_ready) 825 ; 826 } 827 828 829 static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res) 830 { 831 int tag = res >> AC_UNSOL_RES_TAG_SHIFT; 832 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT; 833 struct hda_jack_tbl *jack; 834 835 if (codec_has_acomp(codec)) 836 return; 837 838 if (codec->dp_mst) { 839 int dev_entry = 840 (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT; 841 842 jack = snd_hda_jack_tbl_get_from_tag(codec, tag, dev_entry); 843 } else { 844 jack = snd_hda_jack_tbl_get_from_tag(codec, tag, 0); 845 } 846 847 if (!jack) { 848 codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag); 849 return; 850 } 851 852 if (subtag == 0) 853 hdmi_intrinsic_event(codec, res); 854 else 855 hdmi_non_intrinsic_event(codec, res); 856 } 857 858 static void haswell_verify_D0(struct hda_codec *codec, 859 hda_nid_t cvt_nid, hda_nid_t nid) 860 { 861 int pwr; 862 863 /* For Haswell, the converter 1/2 may keep in D3 state after bootup, 864 * thus pins could only choose converter 0 for use. Make sure the 865 * converters are in correct power state */ 866 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0)) 867 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0); 868 869 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) { 870 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE, 871 AC_PWRST_D0); 872 msleep(40); 873 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0); 874 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT; 875 codec_dbg(codec, "Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr); 876 } 877 } 878 879 /* 880 * Callbacks 881 */ 882 883 /* HBR should be Non-PCM, 8 channels */ 884 #define is_hbr_format(format) \ 885 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7) 886 887 static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid, 888 int dev_id, bool hbr) 889 { 890 int pinctl, new_pinctl; 891 892 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) { 893 snd_hda_set_dev_select(codec, pin_nid, dev_id); 894 pinctl = snd_hda_codec_read(codec, pin_nid, 0, 895 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 896 897 if (pinctl < 0) 898 return hbr ? -EINVAL : 0; 899 900 new_pinctl = pinctl & ~AC_PINCTL_EPT; 901 if (hbr) 902 new_pinctl |= AC_PINCTL_EPT_HBR; 903 else 904 new_pinctl |= AC_PINCTL_EPT_NATIVE; 905 906 codec_dbg(codec, 907 "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n", 908 pin_nid, 909 pinctl == new_pinctl ? "" : "new-", 910 new_pinctl); 911 912 if (pinctl != new_pinctl) 913 snd_hda_codec_write(codec, pin_nid, 0, 914 AC_VERB_SET_PIN_WIDGET_CONTROL, 915 new_pinctl); 916 } else if (hbr) 917 return -EINVAL; 918 919 return 0; 920 } 921 922 static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, 923 hda_nid_t pin_nid, int dev_id, 924 u32 stream_tag, int format) 925 { 926 struct hdmi_spec *spec = codec->spec; 927 unsigned int param; 928 int err; 929 930 err = spec->ops.pin_hbr_setup(codec, pin_nid, dev_id, 931 is_hbr_format(format)); 932 933 if (err) { 934 codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n"); 935 return err; 936 } 937 938 if (spec->intel_hsw_fixup) { 939 940 /* 941 * on recent platforms IEC Coding Type is required for HBR 942 * support, read current Digital Converter settings and set 943 * ICT bitfield if needed. 944 */ 945 param = snd_hda_codec_read(codec, cvt_nid, 0, 946 AC_VERB_GET_DIGI_CONVERT_1, 0); 947 948 param = (param >> 16) & ~(AC_DIG3_ICT); 949 950 /* on recent platforms ICT mode is required for HBR support */ 951 if (is_hbr_format(format)) 952 param |= 0x1; 953 954 snd_hda_codec_write(codec, cvt_nid, 0, 955 AC_VERB_SET_DIGI_CONVERT_3, param); 956 } 957 958 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format); 959 return 0; 960 } 961 962 /* Try to find an available converter 963 * If pin_idx is less then zero, just try to find an available converter. 964 * Otherwise, try to find an available converter and get the cvt mux index 965 * of the pin. 966 */ 967 static int hdmi_choose_cvt(struct hda_codec *codec, 968 int pin_idx, int *cvt_id) 969 { 970 struct hdmi_spec *spec = codec->spec; 971 struct hdmi_spec_per_pin *per_pin; 972 struct hdmi_spec_per_cvt *per_cvt = NULL; 973 int cvt_idx, mux_idx = 0; 974 975 /* pin_idx < 0 means no pin will be bound to the converter */ 976 if (pin_idx < 0) 977 per_pin = NULL; 978 else 979 per_pin = get_pin(spec, pin_idx); 980 981 /* Dynamically assign converter to stream */ 982 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { 983 per_cvt = get_cvt(spec, cvt_idx); 984 985 /* Must not already be assigned */ 986 if (per_cvt->assigned) 987 continue; 988 if (per_pin == NULL) 989 break; 990 /* Must be in pin's mux's list of converters */ 991 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++) 992 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid) 993 break; 994 /* Not in mux list */ 995 if (mux_idx == per_pin->num_mux_nids) 996 continue; 997 break; 998 } 999 1000 /* No free converters */ 1001 if (cvt_idx == spec->num_cvts) 1002 return -EBUSY; 1003 1004 if (per_pin != NULL) 1005 per_pin->mux_idx = mux_idx; 1006 1007 if (cvt_id) 1008 *cvt_id = cvt_idx; 1009 1010 return 0; 1011 } 1012 1013 /* Assure the pin select the right convetor */ 1014 static void intel_verify_pin_cvt_connect(struct hda_codec *codec, 1015 struct hdmi_spec_per_pin *per_pin) 1016 { 1017 hda_nid_t pin_nid = per_pin->pin_nid; 1018 int mux_idx, curr; 1019 1020 mux_idx = per_pin->mux_idx; 1021 curr = snd_hda_codec_read(codec, pin_nid, 0, 1022 AC_VERB_GET_CONNECT_SEL, 0); 1023 if (curr != mux_idx) 1024 snd_hda_codec_write_cache(codec, pin_nid, 0, 1025 AC_VERB_SET_CONNECT_SEL, 1026 mux_idx); 1027 } 1028 1029 /* get the mux index for the converter of the pins 1030 * converter's mux index is the same for all pins on Intel platform 1031 */ 1032 static int intel_cvt_id_to_mux_idx(struct hdmi_spec *spec, 1033 hda_nid_t cvt_nid) 1034 { 1035 int i; 1036 1037 for (i = 0; i < spec->num_cvts; i++) 1038 if (spec->cvt_nids[i] == cvt_nid) 1039 return i; 1040 return -EINVAL; 1041 } 1042 1043 /* Intel HDMI workaround to fix audio routing issue: 1044 * For some Intel display codecs, pins share the same connection list. 1045 * So a conveter can be selected by multiple pins and playback on any of these 1046 * pins will generate sound on the external display, because audio flows from 1047 * the same converter to the display pipeline. Also muting one pin may make 1048 * other pins have no sound output. 1049 * So this function assures that an assigned converter for a pin is not selected 1050 * by any other pins. 1051 */ 1052 static void intel_not_share_assigned_cvt(struct hda_codec *codec, 1053 hda_nid_t pin_nid, 1054 int dev_id, int mux_idx) 1055 { 1056 struct hdmi_spec *spec = codec->spec; 1057 hda_nid_t nid; 1058 int cvt_idx, curr; 1059 struct hdmi_spec_per_cvt *per_cvt; 1060 struct hdmi_spec_per_pin *per_pin; 1061 int pin_idx; 1062 1063 /* configure the pins connections */ 1064 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 1065 int dev_id_saved; 1066 int dev_num; 1067 1068 per_pin = get_pin(spec, pin_idx); 1069 /* 1070 * pin not connected to monitor 1071 * no need to operate on it 1072 */ 1073 if (!per_pin->pcm) 1074 continue; 1075 1076 if ((per_pin->pin_nid == pin_nid) && 1077 (per_pin->dev_id == dev_id)) 1078 continue; 1079 1080 /* 1081 * if per_pin->dev_id >= dev_num, 1082 * snd_hda_get_dev_select() will fail, 1083 * and the following operation is unpredictable. 1084 * So skip this situation. 1085 */ 1086 dev_num = snd_hda_get_num_devices(codec, per_pin->pin_nid) + 1; 1087 if (per_pin->dev_id >= dev_num) 1088 continue; 1089 1090 nid = per_pin->pin_nid; 1091 1092 /* 1093 * Calling this function should not impact 1094 * on the device entry selection 1095 * So let's save the dev id for each pin, 1096 * and restore it when return 1097 */ 1098 dev_id_saved = snd_hda_get_dev_select(codec, nid); 1099 snd_hda_set_dev_select(codec, nid, per_pin->dev_id); 1100 curr = snd_hda_codec_read(codec, nid, 0, 1101 AC_VERB_GET_CONNECT_SEL, 0); 1102 if (curr != mux_idx) { 1103 snd_hda_set_dev_select(codec, nid, dev_id_saved); 1104 continue; 1105 } 1106 1107 1108 /* choose an unassigned converter. The conveters in the 1109 * connection list are in the same order as in the codec. 1110 */ 1111 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { 1112 per_cvt = get_cvt(spec, cvt_idx); 1113 if (!per_cvt->assigned) { 1114 codec_dbg(codec, 1115 "choose cvt %d for pin nid %d\n", 1116 cvt_idx, nid); 1117 snd_hda_codec_write_cache(codec, nid, 0, 1118 AC_VERB_SET_CONNECT_SEL, 1119 cvt_idx); 1120 break; 1121 } 1122 } 1123 snd_hda_set_dev_select(codec, nid, dev_id_saved); 1124 } 1125 } 1126 1127 /* A wrapper of intel_not_share_asigned_cvt() */ 1128 static void intel_not_share_assigned_cvt_nid(struct hda_codec *codec, 1129 hda_nid_t pin_nid, int dev_id, hda_nid_t cvt_nid) 1130 { 1131 int mux_idx; 1132 struct hdmi_spec *spec = codec->spec; 1133 1134 /* On Intel platform, the mapping of converter nid to 1135 * mux index of the pins are always the same. 1136 * The pin nid may be 0, this means all pins will not 1137 * share the converter. 1138 */ 1139 mux_idx = intel_cvt_id_to_mux_idx(spec, cvt_nid); 1140 if (mux_idx >= 0) 1141 intel_not_share_assigned_cvt(codec, pin_nid, dev_id, mux_idx); 1142 } 1143 1144 /* skeleton caller of pin_cvt_fixup ops */ 1145 static void pin_cvt_fixup(struct hda_codec *codec, 1146 struct hdmi_spec_per_pin *per_pin, 1147 hda_nid_t cvt_nid) 1148 { 1149 struct hdmi_spec *spec = codec->spec; 1150 1151 if (spec->ops.pin_cvt_fixup) 1152 spec->ops.pin_cvt_fixup(codec, per_pin, cvt_nid); 1153 } 1154 1155 /* called in hdmi_pcm_open when no pin is assigned to the PCM 1156 * in dyn_pcm_assign mode. 1157 */ 1158 static int hdmi_pcm_open_no_pin(struct hda_pcm_stream *hinfo, 1159 struct hda_codec *codec, 1160 struct snd_pcm_substream *substream) 1161 { 1162 struct hdmi_spec *spec = codec->spec; 1163 struct snd_pcm_runtime *runtime = substream->runtime; 1164 int cvt_idx, pcm_idx; 1165 struct hdmi_spec_per_cvt *per_cvt = NULL; 1166 int err; 1167 1168 pcm_idx = hinfo_to_pcm_index(codec, hinfo); 1169 if (pcm_idx < 0) 1170 return -EINVAL; 1171 1172 err = hdmi_choose_cvt(codec, -1, &cvt_idx); 1173 if (err) 1174 return err; 1175 1176 per_cvt = get_cvt(spec, cvt_idx); 1177 per_cvt->assigned = 1; 1178 hinfo->nid = per_cvt->cvt_nid; 1179 1180 pin_cvt_fixup(codec, NULL, per_cvt->cvt_nid); 1181 1182 set_bit(pcm_idx, &spec->pcm_in_use); 1183 /* todo: setup spdif ctls assign */ 1184 1185 /* Initially set the converter's capabilities */ 1186 hinfo->channels_min = per_cvt->channels_min; 1187 hinfo->channels_max = per_cvt->channels_max; 1188 hinfo->rates = per_cvt->rates; 1189 hinfo->formats = per_cvt->formats; 1190 hinfo->maxbps = per_cvt->maxbps; 1191 1192 /* Store the updated parameters */ 1193 runtime->hw.channels_min = hinfo->channels_min; 1194 runtime->hw.channels_max = hinfo->channels_max; 1195 runtime->hw.formats = hinfo->formats; 1196 runtime->hw.rates = hinfo->rates; 1197 1198 snd_pcm_hw_constraint_step(substream->runtime, 0, 1199 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 1200 return 0; 1201 } 1202 1203 /* 1204 * HDA PCM callbacks 1205 */ 1206 static int hdmi_pcm_open(struct hda_pcm_stream *hinfo, 1207 struct hda_codec *codec, 1208 struct snd_pcm_substream *substream) 1209 { 1210 struct hdmi_spec *spec = codec->spec; 1211 struct snd_pcm_runtime *runtime = substream->runtime; 1212 int pin_idx, cvt_idx, pcm_idx; 1213 struct hdmi_spec_per_pin *per_pin; 1214 struct hdmi_eld *eld; 1215 struct hdmi_spec_per_cvt *per_cvt = NULL; 1216 int err; 1217 1218 /* Validate hinfo */ 1219 pcm_idx = hinfo_to_pcm_index(codec, hinfo); 1220 if (pcm_idx < 0) 1221 return -EINVAL; 1222 1223 mutex_lock(&spec->pcm_lock); 1224 pin_idx = hinfo_to_pin_index(codec, hinfo); 1225 if (!spec->dyn_pcm_assign) { 1226 if (snd_BUG_ON(pin_idx < 0)) { 1227 err = -EINVAL; 1228 goto unlock; 1229 } 1230 } else { 1231 /* no pin is assigned to the PCM 1232 * PA need pcm open successfully when probe 1233 */ 1234 if (pin_idx < 0) { 1235 err = hdmi_pcm_open_no_pin(hinfo, codec, substream); 1236 goto unlock; 1237 } 1238 } 1239 1240 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx); 1241 if (err < 0) 1242 goto unlock; 1243 1244 per_cvt = get_cvt(spec, cvt_idx); 1245 /* Claim converter */ 1246 per_cvt->assigned = 1; 1247 1248 set_bit(pcm_idx, &spec->pcm_in_use); 1249 per_pin = get_pin(spec, pin_idx); 1250 per_pin->cvt_nid = per_cvt->cvt_nid; 1251 hinfo->nid = per_cvt->cvt_nid; 1252 1253 /* flip stripe flag for the assigned stream if supported */ 1254 if (get_wcaps(codec, per_cvt->cvt_nid) & AC_WCAP_STRIPE) 1255 azx_stream(get_azx_dev(substream))->stripe = 1; 1256 1257 snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id); 1258 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0, 1259 AC_VERB_SET_CONNECT_SEL, 1260 per_pin->mux_idx); 1261 1262 /* configure unused pins to choose other converters */ 1263 pin_cvt_fixup(codec, per_pin, 0); 1264 1265 snd_hda_spdif_ctls_assign(codec, pcm_idx, per_cvt->cvt_nid); 1266 1267 /* Initially set the converter's capabilities */ 1268 hinfo->channels_min = per_cvt->channels_min; 1269 hinfo->channels_max = per_cvt->channels_max; 1270 hinfo->rates = per_cvt->rates; 1271 hinfo->formats = per_cvt->formats; 1272 hinfo->maxbps = per_cvt->maxbps; 1273 1274 eld = &per_pin->sink_eld; 1275 /* Restrict capabilities by ELD if this isn't disabled */ 1276 if (!static_hdmi_pcm && eld->eld_valid) { 1277 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo); 1278 if (hinfo->channels_min > hinfo->channels_max || 1279 !hinfo->rates || !hinfo->formats) { 1280 per_cvt->assigned = 0; 1281 hinfo->nid = 0; 1282 snd_hda_spdif_ctls_unassign(codec, pcm_idx); 1283 err = -ENODEV; 1284 goto unlock; 1285 } 1286 } 1287 1288 /* Store the updated parameters */ 1289 runtime->hw.channels_min = hinfo->channels_min; 1290 runtime->hw.channels_max = hinfo->channels_max; 1291 runtime->hw.formats = hinfo->formats; 1292 runtime->hw.rates = hinfo->rates; 1293 1294 snd_pcm_hw_constraint_step(substream->runtime, 0, 1295 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 1296 unlock: 1297 mutex_unlock(&spec->pcm_lock); 1298 return err; 1299 } 1300 1301 /* 1302 * HDA/HDMI auto parsing 1303 */ 1304 static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx) 1305 { 1306 struct hdmi_spec *spec = codec->spec; 1307 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 1308 hda_nid_t pin_nid = per_pin->pin_nid; 1309 int dev_id = per_pin->dev_id; 1310 int conns; 1311 1312 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) { 1313 codec_warn(codec, 1314 "HDMI: pin %d wcaps %#x does not support connection list\n", 1315 pin_nid, get_wcaps(codec, pin_nid)); 1316 return -EINVAL; 1317 } 1318 1319 snd_hda_set_dev_select(codec, pin_nid, dev_id); 1320 1321 if (spec->intel_hsw_fixup) { 1322 conns = spec->num_cvts; 1323 memcpy(per_pin->mux_nids, spec->cvt_nids, 1324 sizeof(hda_nid_t) * conns); 1325 } else { 1326 conns = snd_hda_get_raw_connections(codec, pin_nid, 1327 per_pin->mux_nids, 1328 HDA_MAX_CONNECTIONS); 1329 } 1330 1331 /* all the device entries on the same pin have the same conn list */ 1332 per_pin->num_mux_nids = conns; 1333 1334 return 0; 1335 } 1336 1337 static int hdmi_find_pcm_slot(struct hdmi_spec *spec, 1338 struct hdmi_spec_per_pin *per_pin) 1339 { 1340 int i; 1341 1342 /* 1343 * generic_hdmi_build_pcms() may allocate extra PCMs on some 1344 * platforms (with maximum of 'num_nids + dev_num - 1') 1345 * 1346 * The per_pin of pin_nid_idx=n and dev_id=m prefers to get pcm-n 1347 * if m==0. This guarantees that dynamic pcm assignments are compatible 1348 * with the legacy static per_pin-pcm assignment that existed in the 1349 * days before DP-MST. 1350 * 1351 * Intel DP-MST prefers this legacy behavior for compatibility, too. 1352 * 1353 * per_pin of m!=0 prefers to get pcm=(num_nids + (m - 1)). 1354 */ 1355 1356 if (per_pin->dev_id == 0 || spec->intel_hsw_fixup) { 1357 if (!test_bit(per_pin->pin_nid_idx, &spec->pcm_bitmap)) 1358 return per_pin->pin_nid_idx; 1359 } else { 1360 i = spec->num_nids + (per_pin->dev_id - 1); 1361 if (i < spec->pcm_used && !(test_bit(i, &spec->pcm_bitmap))) 1362 return i; 1363 } 1364 1365 /* have a second try; check the area over num_nids */ 1366 for (i = spec->num_nids; i < spec->pcm_used; i++) { 1367 if (!test_bit(i, &spec->pcm_bitmap)) 1368 return i; 1369 } 1370 1371 /* the last try; check the empty slots in pins */ 1372 for (i = 0; i < spec->num_nids; i++) { 1373 if (!test_bit(i, &spec->pcm_bitmap)) 1374 return i; 1375 } 1376 return -EBUSY; 1377 } 1378 1379 static void hdmi_attach_hda_pcm(struct hdmi_spec *spec, 1380 struct hdmi_spec_per_pin *per_pin) 1381 { 1382 int idx; 1383 1384 /* pcm already be attached to the pin */ 1385 if (per_pin->pcm) 1386 return; 1387 idx = hdmi_find_pcm_slot(spec, per_pin); 1388 if (idx == -EBUSY) 1389 return; 1390 per_pin->pcm_idx = idx; 1391 per_pin->pcm = get_hdmi_pcm(spec, idx); 1392 set_bit(idx, &spec->pcm_bitmap); 1393 } 1394 1395 static void hdmi_detach_hda_pcm(struct hdmi_spec *spec, 1396 struct hdmi_spec_per_pin *per_pin) 1397 { 1398 int idx; 1399 1400 /* pcm already be detached from the pin */ 1401 if (!per_pin->pcm) 1402 return; 1403 idx = per_pin->pcm_idx; 1404 per_pin->pcm_idx = -1; 1405 per_pin->pcm = NULL; 1406 if (idx >= 0 && idx < spec->pcm_used) 1407 clear_bit(idx, &spec->pcm_bitmap); 1408 } 1409 1410 static int hdmi_get_pin_cvt_mux(struct hdmi_spec *spec, 1411 struct hdmi_spec_per_pin *per_pin, hda_nid_t cvt_nid) 1412 { 1413 int mux_idx; 1414 1415 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++) 1416 if (per_pin->mux_nids[mux_idx] == cvt_nid) 1417 break; 1418 return mux_idx; 1419 } 1420 1421 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid); 1422 1423 static void hdmi_pcm_setup_pin(struct hdmi_spec *spec, 1424 struct hdmi_spec_per_pin *per_pin) 1425 { 1426 struct hda_codec *codec = per_pin->codec; 1427 struct hda_pcm *pcm; 1428 struct hda_pcm_stream *hinfo; 1429 struct snd_pcm_substream *substream; 1430 int mux_idx; 1431 bool non_pcm; 1432 1433 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used) 1434 pcm = get_pcm_rec(spec, per_pin->pcm_idx); 1435 else 1436 return; 1437 if (!pcm->pcm) 1438 return; 1439 if (!test_bit(per_pin->pcm_idx, &spec->pcm_in_use)) 1440 return; 1441 1442 /* hdmi audio only uses playback and one substream */ 1443 hinfo = pcm->stream; 1444 substream = pcm->pcm->streams[0].substream; 1445 1446 per_pin->cvt_nid = hinfo->nid; 1447 1448 mux_idx = hdmi_get_pin_cvt_mux(spec, per_pin, hinfo->nid); 1449 if (mux_idx < per_pin->num_mux_nids) { 1450 snd_hda_set_dev_select(codec, per_pin->pin_nid, 1451 per_pin->dev_id); 1452 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0, 1453 AC_VERB_SET_CONNECT_SEL, 1454 mux_idx); 1455 } 1456 snd_hda_spdif_ctls_assign(codec, per_pin->pcm_idx, hinfo->nid); 1457 1458 non_pcm = check_non_pcm_per_cvt(codec, hinfo->nid); 1459 if (substream->runtime) 1460 per_pin->channels = substream->runtime->channels; 1461 per_pin->setup = true; 1462 per_pin->mux_idx = mux_idx; 1463 1464 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm); 1465 } 1466 1467 static void hdmi_pcm_reset_pin(struct hdmi_spec *spec, 1468 struct hdmi_spec_per_pin *per_pin) 1469 { 1470 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used) 1471 snd_hda_spdif_ctls_unassign(per_pin->codec, per_pin->pcm_idx); 1472 1473 per_pin->chmap_set = false; 1474 memset(per_pin->chmap, 0, sizeof(per_pin->chmap)); 1475 1476 per_pin->setup = false; 1477 per_pin->channels = 0; 1478 } 1479 1480 /* update per_pin ELD from the given new ELD; 1481 * setup info frame and notification accordingly 1482 */ 1483 static bool update_eld(struct hda_codec *codec, 1484 struct hdmi_spec_per_pin *per_pin, 1485 struct hdmi_eld *eld) 1486 { 1487 struct hdmi_eld *pin_eld = &per_pin->sink_eld; 1488 struct hdmi_spec *spec = codec->spec; 1489 bool old_eld_valid = pin_eld->eld_valid; 1490 bool eld_changed; 1491 int pcm_idx; 1492 1493 /* for monitor disconnection, save pcm_idx firstly */ 1494 pcm_idx = per_pin->pcm_idx; 1495 if (spec->dyn_pcm_assign) { 1496 if (eld->eld_valid) { 1497 hdmi_attach_hda_pcm(spec, per_pin); 1498 hdmi_pcm_setup_pin(spec, per_pin); 1499 } else { 1500 hdmi_pcm_reset_pin(spec, per_pin); 1501 hdmi_detach_hda_pcm(spec, per_pin); 1502 } 1503 } 1504 /* if pcm_idx == -1, it means this is in monitor connection event 1505 * we can get the correct pcm_idx now. 1506 */ 1507 if (pcm_idx == -1) 1508 pcm_idx = per_pin->pcm_idx; 1509 1510 if (eld->eld_valid) 1511 snd_hdmi_show_eld(codec, &eld->info); 1512 1513 eld_changed = (pin_eld->eld_valid != eld->eld_valid); 1514 eld_changed |= (pin_eld->monitor_present != eld->monitor_present); 1515 if (!eld_changed && eld->eld_valid && pin_eld->eld_valid) 1516 if (pin_eld->eld_size != eld->eld_size || 1517 memcmp(pin_eld->eld_buffer, eld->eld_buffer, 1518 eld->eld_size) != 0) 1519 eld_changed = true; 1520 1521 if (eld_changed) { 1522 pin_eld->monitor_present = eld->monitor_present; 1523 pin_eld->eld_valid = eld->eld_valid; 1524 pin_eld->eld_size = eld->eld_size; 1525 if (eld->eld_valid) 1526 memcpy(pin_eld->eld_buffer, eld->eld_buffer, 1527 eld->eld_size); 1528 pin_eld->info = eld->info; 1529 } 1530 1531 /* 1532 * Re-setup pin and infoframe. This is needed e.g. when 1533 * - sink is first plugged-in 1534 * - transcoder can change during stream playback on Haswell 1535 * and this can make HW reset converter selection on a pin. 1536 */ 1537 if (eld->eld_valid && !old_eld_valid && per_pin->setup) { 1538 pin_cvt_fixup(codec, per_pin, 0); 1539 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm); 1540 } 1541 1542 if (eld_changed && pcm_idx >= 0) 1543 snd_ctl_notify(codec->card, 1544 SNDRV_CTL_EVENT_MASK_VALUE | 1545 SNDRV_CTL_EVENT_MASK_INFO, 1546 &get_hdmi_pcm(spec, pcm_idx)->eld_ctl->id); 1547 return eld_changed; 1548 } 1549 1550 /* update ELD and jack state via HD-audio verbs */ 1551 static bool hdmi_present_sense_via_verbs(struct hdmi_spec_per_pin *per_pin, 1552 int repoll) 1553 { 1554 struct hda_jack_tbl *jack; 1555 struct hda_codec *codec = per_pin->codec; 1556 struct hdmi_spec *spec = codec->spec; 1557 struct hdmi_eld *eld = &spec->temp_eld; 1558 hda_nid_t pin_nid = per_pin->pin_nid; 1559 int dev_id = per_pin->dev_id; 1560 /* 1561 * Always execute a GetPinSense verb here, even when called from 1562 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited 1563 * response's PD bit is not the real PD value, but indicates that 1564 * the real PD value changed. An older version of the HD-audio 1565 * specification worked this way. Hence, we just ignore the data in 1566 * the unsolicited response to avoid custom WARs. 1567 */ 1568 int present; 1569 bool ret; 1570 bool do_repoll = false; 1571 1572 present = snd_hda_jack_pin_sense(codec, pin_nid, dev_id); 1573 1574 mutex_lock(&per_pin->lock); 1575 eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE); 1576 if (eld->monitor_present) 1577 eld->eld_valid = !!(present & AC_PINSENSE_ELDV); 1578 else 1579 eld->eld_valid = false; 1580 1581 codec_dbg(codec, 1582 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n", 1583 codec->addr, pin_nid, eld->monitor_present, eld->eld_valid); 1584 1585 if (eld->eld_valid) { 1586 if (spec->ops.pin_get_eld(codec, pin_nid, dev_id, 1587 eld->eld_buffer, &eld->eld_size) < 0) 1588 eld->eld_valid = false; 1589 else { 1590 if (snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer, 1591 eld->eld_size) < 0) 1592 eld->eld_valid = false; 1593 } 1594 if (!eld->eld_valid && repoll) 1595 do_repoll = true; 1596 } 1597 1598 if (do_repoll) 1599 schedule_delayed_work(&per_pin->work, msecs_to_jiffies(300)); 1600 else 1601 update_eld(codec, per_pin, eld); 1602 1603 ret = !repoll || !eld->monitor_present || eld->eld_valid; 1604 1605 jack = snd_hda_jack_tbl_get_mst(codec, pin_nid, per_pin->dev_id); 1606 if (jack) { 1607 jack->block_report = !ret; 1608 jack->pin_sense = (eld->monitor_present && eld->eld_valid) ? 1609 AC_PINSENSE_PRESENCE : 0; 1610 } 1611 mutex_unlock(&per_pin->lock); 1612 return ret; 1613 } 1614 1615 static struct snd_jack *pin_idx_to_jack(struct hda_codec *codec, 1616 struct hdmi_spec_per_pin *per_pin) 1617 { 1618 struct hdmi_spec *spec = codec->spec; 1619 struct snd_jack *jack = NULL; 1620 struct hda_jack_tbl *jack_tbl; 1621 1622 /* if !dyn_pcm_assign, get jack from hda_jack_tbl 1623 * in !dyn_pcm_assign case, spec->pcm_rec[].jack is not 1624 * NULL even after snd_hda_jack_tbl_clear() is called to 1625 * free snd_jack. This may cause access invalid memory 1626 * when calling snd_jack_report 1627 */ 1628 if (per_pin->pcm_idx >= 0 && spec->dyn_pcm_assign) 1629 jack = spec->pcm_rec[per_pin->pcm_idx].jack; 1630 else if (!spec->dyn_pcm_assign) { 1631 /* 1632 * jack tbl doesn't support DP MST 1633 * DP MST will use dyn_pcm_assign, 1634 * so DP MST will never come here 1635 */ 1636 jack_tbl = snd_hda_jack_tbl_get_mst(codec, per_pin->pin_nid, 1637 per_pin->dev_id); 1638 if (jack_tbl) 1639 jack = jack_tbl->jack; 1640 } 1641 return jack; 1642 } 1643 1644 /* update ELD and jack state via audio component */ 1645 static void sync_eld_via_acomp(struct hda_codec *codec, 1646 struct hdmi_spec_per_pin *per_pin) 1647 { 1648 struct hdmi_spec *spec = codec->spec; 1649 struct hdmi_eld *eld = &spec->temp_eld; 1650 struct snd_jack *jack = NULL; 1651 bool changed; 1652 int size; 1653 1654 mutex_lock(&per_pin->lock); 1655 eld->monitor_present = false; 1656 size = snd_hdac_acomp_get_eld(&codec->core, per_pin->pin_nid, 1657 per_pin->dev_id, &eld->monitor_present, 1658 eld->eld_buffer, ELD_MAX_SIZE); 1659 if (size > 0) { 1660 size = min(size, ELD_MAX_SIZE); 1661 if (snd_hdmi_parse_eld(codec, &eld->info, 1662 eld->eld_buffer, size) < 0) 1663 size = -EINVAL; 1664 } 1665 1666 if (size > 0) { 1667 eld->eld_valid = true; 1668 eld->eld_size = size; 1669 } else { 1670 eld->eld_valid = false; 1671 eld->eld_size = 0; 1672 } 1673 1674 /* pcm_idx >=0 before update_eld() means it is in monitor 1675 * disconnected event. Jack must be fetched before update_eld() 1676 */ 1677 jack = pin_idx_to_jack(codec, per_pin); 1678 changed = update_eld(codec, per_pin, eld); 1679 if (jack == NULL) 1680 jack = pin_idx_to_jack(codec, per_pin); 1681 if (changed && jack) 1682 snd_jack_report(jack, 1683 (eld->monitor_present && eld->eld_valid) ? 1684 SND_JACK_AVOUT : 0); 1685 mutex_unlock(&per_pin->lock); 1686 } 1687 1688 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll) 1689 { 1690 struct hda_codec *codec = per_pin->codec; 1691 int ret; 1692 1693 /* no temporary power up/down needed for component notifier */ 1694 if (!codec_has_acomp(codec)) { 1695 ret = snd_hda_power_up_pm(codec); 1696 if (ret < 0 && pm_runtime_suspended(hda_codec_dev(codec))) { 1697 snd_hda_power_down_pm(codec); 1698 return false; 1699 } 1700 ret = hdmi_present_sense_via_verbs(per_pin, repoll); 1701 snd_hda_power_down_pm(codec); 1702 } else { 1703 sync_eld_via_acomp(codec, per_pin); 1704 ret = false; /* don't call snd_hda_jack_report_sync() */ 1705 } 1706 1707 return ret; 1708 } 1709 1710 static void hdmi_repoll_eld(struct work_struct *work) 1711 { 1712 struct hdmi_spec_per_pin *per_pin = 1713 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work); 1714 struct hda_codec *codec = per_pin->codec; 1715 struct hdmi_spec *spec = codec->spec; 1716 struct hda_jack_tbl *jack; 1717 1718 jack = snd_hda_jack_tbl_get_mst(codec, per_pin->pin_nid, 1719 per_pin->dev_id); 1720 if (jack) 1721 jack->jack_dirty = 1; 1722 1723 if (per_pin->repoll_count++ > 6) 1724 per_pin->repoll_count = 0; 1725 1726 mutex_lock(&spec->pcm_lock); 1727 if (hdmi_present_sense(per_pin, per_pin->repoll_count)) 1728 snd_hda_jack_report_sync(per_pin->codec); 1729 mutex_unlock(&spec->pcm_lock); 1730 } 1731 1732 static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid) 1733 { 1734 struct hdmi_spec *spec = codec->spec; 1735 unsigned int caps, config; 1736 int pin_idx; 1737 struct hdmi_spec_per_pin *per_pin; 1738 int err; 1739 int dev_num, i; 1740 1741 caps = snd_hda_query_pin_caps(codec, pin_nid); 1742 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP))) 1743 return 0; 1744 1745 /* 1746 * For DP MST audio, Configuration Default is the same for 1747 * all device entries on the same pin 1748 */ 1749 config = snd_hda_codec_get_pincfg(codec, pin_nid); 1750 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE) 1751 return 0; 1752 1753 /* 1754 * To simplify the implementation, malloc all 1755 * the virtual pins in the initialization statically 1756 */ 1757 if (spec->intel_hsw_fixup) { 1758 /* 1759 * On Intel platforms, device entries number is 1760 * changed dynamically. If there is a DP MST 1761 * hub connected, the device entries number is 3. 1762 * Otherwise, it is 1. 1763 * Here we manually set dev_num to 3, so that 1764 * we can initialize all the device entries when 1765 * bootup statically. 1766 */ 1767 dev_num = 3; 1768 spec->dev_num = 3; 1769 } else if (spec->dyn_pcm_assign && codec->dp_mst) { 1770 dev_num = snd_hda_get_num_devices(codec, pin_nid) + 1; 1771 /* 1772 * spec->dev_num is the maxinum number of device entries 1773 * among all the pins 1774 */ 1775 spec->dev_num = (spec->dev_num > dev_num) ? 1776 spec->dev_num : dev_num; 1777 } else { 1778 /* 1779 * If the platform doesn't support DP MST, 1780 * manually set dev_num to 1. This means 1781 * the pin has only one device entry. 1782 */ 1783 dev_num = 1; 1784 spec->dev_num = 1; 1785 } 1786 1787 for (i = 0; i < dev_num; i++) { 1788 pin_idx = spec->num_pins; 1789 per_pin = snd_array_new(&spec->pins); 1790 1791 if (!per_pin) 1792 return -ENOMEM; 1793 1794 if (spec->dyn_pcm_assign) { 1795 per_pin->pcm = NULL; 1796 per_pin->pcm_idx = -1; 1797 } else { 1798 per_pin->pcm = get_hdmi_pcm(spec, pin_idx); 1799 per_pin->pcm_idx = pin_idx; 1800 } 1801 per_pin->pin_nid = pin_nid; 1802 per_pin->pin_nid_idx = spec->num_nids; 1803 per_pin->dev_id = i; 1804 per_pin->non_pcm = false; 1805 snd_hda_set_dev_select(codec, pin_nid, i); 1806 err = hdmi_read_pin_conn(codec, pin_idx); 1807 if (err < 0) 1808 return err; 1809 spec->num_pins++; 1810 } 1811 spec->num_nids++; 1812 1813 return 0; 1814 } 1815 1816 static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid) 1817 { 1818 struct hdmi_spec *spec = codec->spec; 1819 struct hdmi_spec_per_cvt *per_cvt; 1820 unsigned int chans; 1821 int err; 1822 1823 chans = get_wcaps(codec, cvt_nid); 1824 chans = get_wcaps_channels(chans); 1825 1826 per_cvt = snd_array_new(&spec->cvts); 1827 if (!per_cvt) 1828 return -ENOMEM; 1829 1830 per_cvt->cvt_nid = cvt_nid; 1831 per_cvt->channels_min = 2; 1832 if (chans <= 16) { 1833 per_cvt->channels_max = chans; 1834 if (chans > spec->chmap.channels_max) 1835 spec->chmap.channels_max = chans; 1836 } 1837 1838 err = snd_hda_query_supported_pcm(codec, cvt_nid, 1839 &per_cvt->rates, 1840 &per_cvt->formats, 1841 &per_cvt->maxbps); 1842 if (err < 0) 1843 return err; 1844 1845 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids)) 1846 spec->cvt_nids[spec->num_cvts] = cvt_nid; 1847 spec->num_cvts++; 1848 1849 return 0; 1850 } 1851 1852 static int hdmi_parse_codec(struct hda_codec *codec) 1853 { 1854 hda_nid_t nid; 1855 int i, nodes; 1856 1857 nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &nid); 1858 if (!nid || nodes < 0) { 1859 codec_warn(codec, "HDMI: failed to get afg sub nodes\n"); 1860 return -EINVAL; 1861 } 1862 1863 for (i = 0; i < nodes; i++, nid++) { 1864 unsigned int caps; 1865 unsigned int type; 1866 1867 caps = get_wcaps(codec, nid); 1868 type = get_wcaps_type(caps); 1869 1870 if (!(caps & AC_WCAP_DIGITAL)) 1871 continue; 1872 1873 switch (type) { 1874 case AC_WID_AUD_OUT: 1875 hdmi_add_cvt(codec, nid); 1876 break; 1877 case AC_WID_PIN: 1878 hdmi_add_pin(codec, nid); 1879 break; 1880 } 1881 } 1882 1883 return 0; 1884 } 1885 1886 /* 1887 */ 1888 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid) 1889 { 1890 struct hda_spdif_out *spdif; 1891 bool non_pcm; 1892 1893 mutex_lock(&codec->spdif_mutex); 1894 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid); 1895 /* Add sanity check to pass klockwork check. 1896 * This should never happen. 1897 */ 1898 if (WARN_ON(spdif == NULL)) 1899 return true; 1900 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO); 1901 mutex_unlock(&codec->spdif_mutex); 1902 return non_pcm; 1903 } 1904 1905 /* 1906 * HDMI callbacks 1907 */ 1908 1909 static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 1910 struct hda_codec *codec, 1911 unsigned int stream_tag, 1912 unsigned int format, 1913 struct snd_pcm_substream *substream) 1914 { 1915 hda_nid_t cvt_nid = hinfo->nid; 1916 struct hdmi_spec *spec = codec->spec; 1917 int pin_idx; 1918 struct hdmi_spec_per_pin *per_pin; 1919 struct snd_pcm_runtime *runtime = substream->runtime; 1920 bool non_pcm; 1921 int pinctl, stripe; 1922 int err = 0; 1923 1924 mutex_lock(&spec->pcm_lock); 1925 pin_idx = hinfo_to_pin_index(codec, hinfo); 1926 if (spec->dyn_pcm_assign && pin_idx < 0) { 1927 /* when dyn_pcm_assign and pcm is not bound to a pin 1928 * skip pin setup and return 0 to make audio playback 1929 * be ongoing 1930 */ 1931 pin_cvt_fixup(codec, NULL, cvt_nid); 1932 snd_hda_codec_setup_stream(codec, cvt_nid, 1933 stream_tag, 0, format); 1934 goto unlock; 1935 } 1936 1937 if (snd_BUG_ON(pin_idx < 0)) { 1938 err = -EINVAL; 1939 goto unlock; 1940 } 1941 per_pin = get_pin(spec, pin_idx); 1942 1943 /* Verify pin:cvt selections to avoid silent audio after S3. 1944 * After S3, the audio driver restores pin:cvt selections 1945 * but this can happen before gfx is ready and such selection 1946 * is overlooked by HW. Thus multiple pins can share a same 1947 * default convertor and mute control will affect each other, 1948 * which can cause a resumed audio playback become silent 1949 * after S3. 1950 */ 1951 pin_cvt_fixup(codec, per_pin, 0); 1952 1953 /* Call sync_audio_rate to set the N/CTS/M manually if necessary */ 1954 /* Todo: add DP1.2 MST audio support later */ 1955 if (codec_has_acomp(codec)) 1956 snd_hdac_sync_audio_rate(&codec->core, per_pin->pin_nid, 1957 per_pin->dev_id, runtime->rate); 1958 1959 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid); 1960 mutex_lock(&per_pin->lock); 1961 per_pin->channels = substream->runtime->channels; 1962 per_pin->setup = true; 1963 1964 if (get_wcaps(codec, cvt_nid) & AC_WCAP_STRIPE) { 1965 stripe = snd_hdac_get_stream_stripe_ctl(&codec->bus->core, 1966 substream); 1967 snd_hda_codec_write(codec, cvt_nid, 0, 1968 AC_VERB_SET_STRIPE_CONTROL, 1969 stripe); 1970 } 1971 1972 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm); 1973 mutex_unlock(&per_pin->lock); 1974 if (spec->dyn_pin_out) { 1975 snd_hda_set_dev_select(codec, per_pin->pin_nid, 1976 per_pin->dev_id); 1977 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0, 1978 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 1979 snd_hda_codec_write(codec, per_pin->pin_nid, 0, 1980 AC_VERB_SET_PIN_WIDGET_CONTROL, 1981 pinctl | PIN_OUT); 1982 } 1983 1984 /* snd_hda_set_dev_select() has been called before */ 1985 err = spec->ops.setup_stream(codec, cvt_nid, per_pin->pin_nid, 1986 per_pin->dev_id, stream_tag, format); 1987 unlock: 1988 mutex_unlock(&spec->pcm_lock); 1989 return err; 1990 } 1991 1992 static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo, 1993 struct hda_codec *codec, 1994 struct snd_pcm_substream *substream) 1995 { 1996 snd_hda_codec_cleanup_stream(codec, hinfo->nid); 1997 return 0; 1998 } 1999 2000 static int hdmi_pcm_close(struct hda_pcm_stream *hinfo, 2001 struct hda_codec *codec, 2002 struct snd_pcm_substream *substream) 2003 { 2004 struct hdmi_spec *spec = codec->spec; 2005 int cvt_idx, pin_idx, pcm_idx; 2006 struct hdmi_spec_per_cvt *per_cvt; 2007 struct hdmi_spec_per_pin *per_pin; 2008 int pinctl; 2009 int err = 0; 2010 2011 if (hinfo->nid) { 2012 pcm_idx = hinfo_to_pcm_index(codec, hinfo); 2013 if (snd_BUG_ON(pcm_idx < 0)) 2014 return -EINVAL; 2015 cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid); 2016 if (snd_BUG_ON(cvt_idx < 0)) 2017 return -EINVAL; 2018 per_cvt = get_cvt(spec, cvt_idx); 2019 2020 snd_BUG_ON(!per_cvt->assigned); 2021 per_cvt->assigned = 0; 2022 hinfo->nid = 0; 2023 2024 mutex_lock(&spec->pcm_lock); 2025 snd_hda_spdif_ctls_unassign(codec, pcm_idx); 2026 clear_bit(pcm_idx, &spec->pcm_in_use); 2027 pin_idx = hinfo_to_pin_index(codec, hinfo); 2028 if (spec->dyn_pcm_assign && pin_idx < 0) 2029 goto unlock; 2030 2031 if (snd_BUG_ON(pin_idx < 0)) { 2032 err = -EINVAL; 2033 goto unlock; 2034 } 2035 per_pin = get_pin(spec, pin_idx); 2036 2037 if (spec->dyn_pin_out) { 2038 snd_hda_set_dev_select(codec, per_pin->pin_nid, 2039 per_pin->dev_id); 2040 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0, 2041 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 2042 snd_hda_codec_write(codec, per_pin->pin_nid, 0, 2043 AC_VERB_SET_PIN_WIDGET_CONTROL, 2044 pinctl & ~PIN_OUT); 2045 } 2046 2047 mutex_lock(&per_pin->lock); 2048 per_pin->chmap_set = false; 2049 memset(per_pin->chmap, 0, sizeof(per_pin->chmap)); 2050 2051 per_pin->setup = false; 2052 per_pin->channels = 0; 2053 mutex_unlock(&per_pin->lock); 2054 unlock: 2055 mutex_unlock(&spec->pcm_lock); 2056 } 2057 2058 return err; 2059 } 2060 2061 static const struct hda_pcm_ops generic_ops = { 2062 .open = hdmi_pcm_open, 2063 .close = hdmi_pcm_close, 2064 .prepare = generic_hdmi_playback_pcm_prepare, 2065 .cleanup = generic_hdmi_playback_pcm_cleanup, 2066 }; 2067 2068 static int hdmi_get_spk_alloc(struct hdac_device *hdac, int pcm_idx) 2069 { 2070 struct hda_codec *codec = container_of(hdac, struct hda_codec, core); 2071 struct hdmi_spec *spec = codec->spec; 2072 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2073 2074 if (!per_pin) 2075 return 0; 2076 2077 return per_pin->sink_eld.info.spk_alloc; 2078 } 2079 2080 static void hdmi_get_chmap(struct hdac_device *hdac, int pcm_idx, 2081 unsigned char *chmap) 2082 { 2083 struct hda_codec *codec = container_of(hdac, struct hda_codec, core); 2084 struct hdmi_spec *spec = codec->spec; 2085 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2086 2087 /* chmap is already set to 0 in caller */ 2088 if (!per_pin) 2089 return; 2090 2091 memcpy(chmap, per_pin->chmap, ARRAY_SIZE(per_pin->chmap)); 2092 } 2093 2094 static void hdmi_set_chmap(struct hdac_device *hdac, int pcm_idx, 2095 unsigned char *chmap, int prepared) 2096 { 2097 struct hda_codec *codec = container_of(hdac, struct hda_codec, core); 2098 struct hdmi_spec *spec = codec->spec; 2099 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2100 2101 if (!per_pin) 2102 return; 2103 mutex_lock(&per_pin->lock); 2104 per_pin->chmap_set = true; 2105 memcpy(per_pin->chmap, chmap, ARRAY_SIZE(per_pin->chmap)); 2106 if (prepared) 2107 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm); 2108 mutex_unlock(&per_pin->lock); 2109 } 2110 2111 static bool is_hdmi_pcm_attached(struct hdac_device *hdac, int pcm_idx) 2112 { 2113 struct hda_codec *codec = container_of(hdac, struct hda_codec, core); 2114 struct hdmi_spec *spec = codec->spec; 2115 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2116 2117 return per_pin ? true:false; 2118 } 2119 2120 static int generic_hdmi_build_pcms(struct hda_codec *codec) 2121 { 2122 struct hdmi_spec *spec = codec->spec; 2123 int idx, pcm_num; 2124 2125 /* 2126 * for non-mst mode, pcm number is the same as before 2127 * for DP MST mode without extra PCM, pcm number is same 2128 * for DP MST mode with extra PCMs, pcm number is 2129 * (nid number + dev_num - 1) 2130 * dev_num is the device entry number in a pin 2131 */ 2132 2133 if (codec->mst_no_extra_pcms) 2134 pcm_num = spec->num_nids; 2135 else 2136 pcm_num = spec->num_nids + spec->dev_num - 1; 2137 2138 codec_dbg(codec, "hdmi: pcm_num set to %d\n", pcm_num); 2139 2140 for (idx = 0; idx < pcm_num; idx++) { 2141 struct hda_pcm *info; 2142 struct hda_pcm_stream *pstr; 2143 2144 info = snd_hda_codec_pcm_new(codec, "HDMI %d", idx); 2145 if (!info) 2146 return -ENOMEM; 2147 2148 spec->pcm_rec[idx].pcm = info; 2149 spec->pcm_used++; 2150 info->pcm_type = HDA_PCM_TYPE_HDMI; 2151 info->own_chmap = true; 2152 2153 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK]; 2154 pstr->substreams = 1; 2155 pstr->ops = generic_ops; 2156 /* pcm number is less than 16 */ 2157 if (spec->pcm_used >= 16) 2158 break; 2159 /* other pstr fields are set in open */ 2160 } 2161 2162 return 0; 2163 } 2164 2165 static void free_hdmi_jack_priv(struct snd_jack *jack) 2166 { 2167 struct hdmi_pcm *pcm = jack->private_data; 2168 2169 pcm->jack = NULL; 2170 } 2171 2172 static int add_hdmi_jack_kctl(struct hda_codec *codec, 2173 struct hdmi_spec *spec, 2174 int pcm_idx, 2175 const char *name) 2176 { 2177 struct snd_jack *jack; 2178 int err; 2179 2180 err = snd_jack_new(codec->card, name, SND_JACK_AVOUT, &jack, 2181 true, false); 2182 if (err < 0) 2183 return err; 2184 2185 spec->pcm_rec[pcm_idx].jack = jack; 2186 jack->private_data = &spec->pcm_rec[pcm_idx]; 2187 jack->private_free = free_hdmi_jack_priv; 2188 return 0; 2189 } 2190 2191 static int generic_hdmi_build_jack(struct hda_codec *codec, int pcm_idx) 2192 { 2193 char hdmi_str[32] = "HDMI/DP"; 2194 struct hdmi_spec *spec = codec->spec; 2195 struct hdmi_spec_per_pin *per_pin; 2196 struct hda_jack_tbl *jack; 2197 int pcmdev = get_pcm_rec(spec, pcm_idx)->device; 2198 bool phantom_jack; 2199 int ret; 2200 2201 if (pcmdev > 0) 2202 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev); 2203 2204 if (spec->dyn_pcm_assign) 2205 return add_hdmi_jack_kctl(codec, spec, pcm_idx, hdmi_str); 2206 2207 /* for !dyn_pcm_assign, we still use hda_jack for compatibility */ 2208 /* if !dyn_pcm_assign, it must be non-MST mode. 2209 * This means pcms and pins are statically mapped. 2210 * And pcm_idx is pin_idx. 2211 */ 2212 per_pin = get_pin(spec, pcm_idx); 2213 phantom_jack = !is_jack_detectable(codec, per_pin->pin_nid); 2214 if (phantom_jack) 2215 strncat(hdmi_str, " Phantom", 2216 sizeof(hdmi_str) - strlen(hdmi_str) - 1); 2217 ret = snd_hda_jack_add_kctl_mst(codec, per_pin->pin_nid, 2218 per_pin->dev_id, hdmi_str, phantom_jack, 2219 0, NULL); 2220 if (ret < 0) 2221 return ret; 2222 jack = snd_hda_jack_tbl_get_mst(codec, per_pin->pin_nid, 2223 per_pin->dev_id); 2224 if (jack == NULL) 2225 return 0; 2226 /* assign jack->jack to pcm_rec[].jack to 2227 * align with dyn_pcm_assign mode 2228 */ 2229 spec->pcm_rec[pcm_idx].jack = jack->jack; 2230 return 0; 2231 } 2232 2233 static int generic_hdmi_build_controls(struct hda_codec *codec) 2234 { 2235 struct hdmi_spec *spec = codec->spec; 2236 int dev, err; 2237 int pin_idx, pcm_idx; 2238 2239 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { 2240 if (!get_pcm_rec(spec, pcm_idx)->pcm) { 2241 /* no PCM: mark this for skipping permanently */ 2242 set_bit(pcm_idx, &spec->pcm_bitmap); 2243 continue; 2244 } 2245 2246 err = generic_hdmi_build_jack(codec, pcm_idx); 2247 if (err < 0) 2248 return err; 2249 2250 /* create the spdif for each pcm 2251 * pin will be bound when monitor is connected 2252 */ 2253 if (spec->dyn_pcm_assign) 2254 err = snd_hda_create_dig_out_ctls(codec, 2255 0, spec->cvt_nids[0], 2256 HDA_PCM_TYPE_HDMI); 2257 else { 2258 struct hdmi_spec_per_pin *per_pin = 2259 get_pin(spec, pcm_idx); 2260 err = snd_hda_create_dig_out_ctls(codec, 2261 per_pin->pin_nid, 2262 per_pin->mux_nids[0], 2263 HDA_PCM_TYPE_HDMI); 2264 } 2265 if (err < 0) 2266 return err; 2267 snd_hda_spdif_ctls_unassign(codec, pcm_idx); 2268 2269 dev = get_pcm_rec(spec, pcm_idx)->device; 2270 if (dev != SNDRV_PCM_INVALID_DEVICE) { 2271 /* add control for ELD Bytes */ 2272 err = hdmi_create_eld_ctl(codec, pcm_idx, dev); 2273 if (err < 0) 2274 return err; 2275 } 2276 } 2277 2278 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2279 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2280 2281 hdmi_present_sense(per_pin, 0); 2282 } 2283 2284 /* add channel maps */ 2285 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { 2286 struct hda_pcm *pcm; 2287 2288 pcm = get_pcm_rec(spec, pcm_idx); 2289 if (!pcm || !pcm->pcm) 2290 break; 2291 err = snd_hdac_add_chmap_ctls(pcm->pcm, pcm_idx, &spec->chmap); 2292 if (err < 0) 2293 return err; 2294 } 2295 2296 return 0; 2297 } 2298 2299 static int generic_hdmi_init_per_pins(struct hda_codec *codec) 2300 { 2301 struct hdmi_spec *spec = codec->spec; 2302 int pin_idx; 2303 2304 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2305 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2306 2307 per_pin->codec = codec; 2308 mutex_init(&per_pin->lock); 2309 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld); 2310 eld_proc_new(per_pin, pin_idx); 2311 } 2312 return 0; 2313 } 2314 2315 static int generic_hdmi_init(struct hda_codec *codec) 2316 { 2317 struct hdmi_spec *spec = codec->spec; 2318 int pin_idx; 2319 2320 mutex_lock(&spec->bind_lock); 2321 spec->use_jack_detect = !codec->jackpoll_interval; 2322 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2323 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2324 hda_nid_t pin_nid = per_pin->pin_nid; 2325 int dev_id = per_pin->dev_id; 2326 2327 snd_hda_set_dev_select(codec, pin_nid, dev_id); 2328 hdmi_init_pin(codec, pin_nid); 2329 if (codec_has_acomp(codec)) 2330 continue; 2331 if (spec->use_jack_detect) 2332 snd_hda_jack_detect_enable(codec, pin_nid, dev_id); 2333 else 2334 snd_hda_jack_detect_enable_callback_mst(codec, pin_nid, 2335 dev_id, 2336 jack_callback); 2337 } 2338 mutex_unlock(&spec->bind_lock); 2339 return 0; 2340 } 2341 2342 static void hdmi_array_init(struct hdmi_spec *spec, int nums) 2343 { 2344 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums); 2345 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums); 2346 } 2347 2348 static void hdmi_array_free(struct hdmi_spec *spec) 2349 { 2350 snd_array_free(&spec->pins); 2351 snd_array_free(&spec->cvts); 2352 } 2353 2354 static void generic_spec_free(struct hda_codec *codec) 2355 { 2356 struct hdmi_spec *spec = codec->spec; 2357 2358 if (spec) { 2359 hdmi_array_free(spec); 2360 kfree(spec); 2361 codec->spec = NULL; 2362 } 2363 codec->dp_mst = false; 2364 } 2365 2366 static void generic_hdmi_free(struct hda_codec *codec) 2367 { 2368 struct hdmi_spec *spec = codec->spec; 2369 int pin_idx, pcm_idx; 2370 2371 if (spec->acomp_registered) { 2372 snd_hdac_acomp_exit(&codec->bus->core); 2373 } else if (codec_has_acomp(codec)) { 2374 snd_hdac_acomp_register_notifier(&codec->bus->core, NULL); 2375 } 2376 codec->relaxed_resume = 0; 2377 2378 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2379 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2380 cancel_delayed_work_sync(&per_pin->work); 2381 eld_proc_free(per_pin); 2382 } 2383 2384 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { 2385 if (spec->pcm_rec[pcm_idx].jack == NULL) 2386 continue; 2387 if (spec->dyn_pcm_assign) 2388 snd_device_free(codec->card, 2389 spec->pcm_rec[pcm_idx].jack); 2390 else 2391 spec->pcm_rec[pcm_idx].jack = NULL; 2392 } 2393 2394 generic_spec_free(codec); 2395 } 2396 2397 #ifdef CONFIG_PM 2398 static int generic_hdmi_resume(struct hda_codec *codec) 2399 { 2400 struct hdmi_spec *spec = codec->spec; 2401 int pin_idx; 2402 2403 codec->patch_ops.init(codec); 2404 regcache_sync(codec->core.regmap); 2405 2406 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2407 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2408 hdmi_present_sense(per_pin, 1); 2409 } 2410 return 0; 2411 } 2412 #endif 2413 2414 static const struct hda_codec_ops generic_hdmi_patch_ops = { 2415 .init = generic_hdmi_init, 2416 .free = generic_hdmi_free, 2417 .build_pcms = generic_hdmi_build_pcms, 2418 .build_controls = generic_hdmi_build_controls, 2419 .unsol_event = hdmi_unsol_event, 2420 #ifdef CONFIG_PM 2421 .resume = generic_hdmi_resume, 2422 #endif 2423 }; 2424 2425 static const struct hdmi_ops generic_standard_hdmi_ops = { 2426 .pin_get_eld = hdmi_pin_get_eld, 2427 .pin_setup_infoframe = hdmi_pin_setup_infoframe, 2428 .pin_hbr_setup = hdmi_pin_hbr_setup, 2429 .setup_stream = hdmi_setup_stream, 2430 }; 2431 2432 /* allocate codec->spec and assign/initialize generic parser ops */ 2433 static int alloc_generic_hdmi(struct hda_codec *codec) 2434 { 2435 struct hdmi_spec *spec; 2436 2437 spec = kzalloc(sizeof(*spec), GFP_KERNEL); 2438 if (!spec) 2439 return -ENOMEM; 2440 2441 spec->codec = codec; 2442 spec->ops = generic_standard_hdmi_ops; 2443 spec->dev_num = 1; /* initialize to 1 */ 2444 mutex_init(&spec->pcm_lock); 2445 mutex_init(&spec->bind_lock); 2446 snd_hdac_register_chmap_ops(&codec->core, &spec->chmap); 2447 2448 spec->chmap.ops.get_chmap = hdmi_get_chmap; 2449 spec->chmap.ops.set_chmap = hdmi_set_chmap; 2450 spec->chmap.ops.is_pcm_attached = is_hdmi_pcm_attached; 2451 spec->chmap.ops.get_spk_alloc = hdmi_get_spk_alloc, 2452 2453 codec->spec = spec; 2454 hdmi_array_init(spec, 4); 2455 2456 codec->patch_ops = generic_hdmi_patch_ops; 2457 2458 return 0; 2459 } 2460 2461 /* generic HDMI parser */ 2462 static int patch_generic_hdmi(struct hda_codec *codec) 2463 { 2464 int err; 2465 2466 err = alloc_generic_hdmi(codec); 2467 if (err < 0) 2468 return err; 2469 2470 err = hdmi_parse_codec(codec); 2471 if (err < 0) { 2472 generic_spec_free(codec); 2473 return err; 2474 } 2475 2476 generic_hdmi_init_per_pins(codec); 2477 return 0; 2478 } 2479 2480 /* 2481 * generic audio component binding 2482 */ 2483 2484 /* turn on / off the unsol event jack detection dynamically */ 2485 static void reprogram_jack_detect(struct hda_codec *codec, hda_nid_t nid, 2486 int dev_id, bool use_acomp) 2487 { 2488 struct hda_jack_tbl *tbl; 2489 2490 tbl = snd_hda_jack_tbl_get_mst(codec, nid, dev_id); 2491 if (tbl) { 2492 /* clear unsol even if component notifier is used, or re-enable 2493 * if notifier is cleared 2494 */ 2495 unsigned int val = use_acomp ? 0 : (AC_USRSP_EN | tbl->tag); 2496 snd_hda_codec_write_cache(codec, nid, 0, 2497 AC_VERB_SET_UNSOLICITED_ENABLE, val); 2498 } else { 2499 /* if no jack entry was defined beforehand, create a new one 2500 * at need (i.e. only when notifier is cleared) 2501 */ 2502 if (!use_acomp) 2503 snd_hda_jack_detect_enable(codec, nid, dev_id); 2504 } 2505 } 2506 2507 /* set up / clear component notifier dynamically */ 2508 static void generic_acomp_notifier_set(struct drm_audio_component *acomp, 2509 bool use_acomp) 2510 { 2511 struct hdmi_spec *spec; 2512 int i; 2513 2514 spec = container_of(acomp->audio_ops, struct hdmi_spec, drm_audio_ops); 2515 mutex_lock(&spec->bind_lock); 2516 spec->use_acomp_notifier = use_acomp; 2517 spec->codec->relaxed_resume = use_acomp; 2518 /* reprogram each jack detection logic depending on the notifier */ 2519 if (spec->use_jack_detect) { 2520 for (i = 0; i < spec->num_pins; i++) 2521 reprogram_jack_detect(spec->codec, 2522 get_pin(spec, i)->pin_nid, 2523 get_pin(spec, i)->dev_id, 2524 use_acomp); 2525 } 2526 mutex_unlock(&spec->bind_lock); 2527 } 2528 2529 /* enable / disable the notifier via master bind / unbind */ 2530 static int generic_acomp_master_bind(struct device *dev, 2531 struct drm_audio_component *acomp) 2532 { 2533 generic_acomp_notifier_set(acomp, true); 2534 return 0; 2535 } 2536 2537 static void generic_acomp_master_unbind(struct device *dev, 2538 struct drm_audio_component *acomp) 2539 { 2540 generic_acomp_notifier_set(acomp, false); 2541 } 2542 2543 /* check whether both HD-audio and DRM PCI devices belong to the same bus */ 2544 static int match_bound_vga(struct device *dev, int subtype, void *data) 2545 { 2546 struct hdac_bus *bus = data; 2547 struct pci_dev *pci, *master; 2548 2549 if (!dev_is_pci(dev) || !dev_is_pci(bus->dev)) 2550 return 0; 2551 master = to_pci_dev(bus->dev); 2552 pci = to_pci_dev(dev); 2553 return master->bus == pci->bus; 2554 } 2555 2556 /* audio component notifier for AMD/Nvidia HDMI codecs */ 2557 static void generic_acomp_pin_eld_notify(void *audio_ptr, int port, int dev_id) 2558 { 2559 struct hda_codec *codec = audio_ptr; 2560 struct hdmi_spec *spec = codec->spec; 2561 hda_nid_t pin_nid = spec->port2pin(codec, port); 2562 2563 if (!pin_nid) 2564 return; 2565 if (get_wcaps_type(get_wcaps(codec, pin_nid)) != AC_WID_PIN) 2566 return; 2567 /* skip notification during system suspend (but not in runtime PM); 2568 * the state will be updated at resume 2569 */ 2570 if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0) 2571 return; 2572 /* ditto during suspend/resume process itself */ 2573 if (snd_hdac_is_in_pm(&codec->core)) 2574 return; 2575 2576 check_presence_and_report(codec, pin_nid, dev_id); 2577 } 2578 2579 /* set up the private drm_audio_ops from the template */ 2580 static void setup_drm_audio_ops(struct hda_codec *codec, 2581 const struct drm_audio_component_audio_ops *ops) 2582 { 2583 struct hdmi_spec *spec = codec->spec; 2584 2585 spec->drm_audio_ops.audio_ptr = codec; 2586 /* intel_audio_codec_enable() or intel_audio_codec_disable() 2587 * will call pin_eld_notify with using audio_ptr pointer 2588 * We need make sure audio_ptr is really setup 2589 */ 2590 wmb(); 2591 spec->drm_audio_ops.pin2port = ops->pin2port; 2592 spec->drm_audio_ops.pin_eld_notify = ops->pin_eld_notify; 2593 spec->drm_audio_ops.master_bind = ops->master_bind; 2594 spec->drm_audio_ops.master_unbind = ops->master_unbind; 2595 } 2596 2597 /* initialize the generic HDMI audio component */ 2598 static void generic_acomp_init(struct hda_codec *codec, 2599 const struct drm_audio_component_audio_ops *ops, 2600 int (*port2pin)(struct hda_codec *, int)) 2601 { 2602 struct hdmi_spec *spec = codec->spec; 2603 2604 spec->port2pin = port2pin; 2605 setup_drm_audio_ops(codec, ops); 2606 if (!snd_hdac_acomp_init(&codec->bus->core, &spec->drm_audio_ops, 2607 match_bound_vga, 0)) { 2608 spec->acomp_registered = true; 2609 codec->bus->keep_power = 0; 2610 } 2611 } 2612 2613 /* 2614 * Intel codec parsers and helpers 2615 */ 2616 2617 #define INTEL_GET_VENDOR_VERB 0xf81 2618 #define INTEL_SET_VENDOR_VERB 0x781 2619 #define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */ 2620 #define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */ 2621 2622 static void intel_haswell_enable_all_pins(struct hda_codec *codec, 2623 bool update_tree) 2624 { 2625 unsigned int vendor_param; 2626 struct hdmi_spec *spec = codec->spec; 2627 2628 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0, 2629 INTEL_GET_VENDOR_VERB, 0); 2630 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS) 2631 return; 2632 2633 vendor_param |= INTEL_EN_ALL_PIN_CVTS; 2634 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0, 2635 INTEL_SET_VENDOR_VERB, vendor_param); 2636 if (vendor_param == -1) 2637 return; 2638 2639 if (update_tree) 2640 snd_hda_codec_update_widgets(codec); 2641 } 2642 2643 static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec) 2644 { 2645 unsigned int vendor_param; 2646 struct hdmi_spec *spec = codec->spec; 2647 2648 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0, 2649 INTEL_GET_VENDOR_VERB, 0); 2650 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12) 2651 return; 2652 2653 /* enable DP1.2 mode */ 2654 vendor_param |= INTEL_EN_DP12; 2655 snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB); 2656 snd_hda_codec_write_cache(codec, spec->vendor_nid, 0, 2657 INTEL_SET_VENDOR_VERB, vendor_param); 2658 } 2659 2660 /* Haswell needs to re-issue the vendor-specific verbs before turning to D0. 2661 * Otherwise you may get severe h/w communication errors. 2662 */ 2663 static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg, 2664 unsigned int power_state) 2665 { 2666 if (power_state == AC_PWRST_D0) { 2667 intel_haswell_enable_all_pins(codec, false); 2668 intel_haswell_fixup_enable_dp12(codec); 2669 } 2670 2671 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state); 2672 snd_hda_codec_set_power_to_all(codec, fg, power_state); 2673 } 2674 2675 /* There is a fixed mapping between audio pin node and display port. 2676 * on SNB, IVY, HSW, BSW, SKL, BXT, KBL: 2677 * Pin Widget 5 - PORT B (port = 1 in i915 driver) 2678 * Pin Widget 6 - PORT C (port = 2 in i915 driver) 2679 * Pin Widget 7 - PORT D (port = 3 in i915 driver) 2680 * 2681 * on VLV, ILK: 2682 * Pin Widget 4 - PORT B (port = 1 in i915 driver) 2683 * Pin Widget 5 - PORT C (port = 2 in i915 driver) 2684 * Pin Widget 6 - PORT D (port = 3 in i915 driver) 2685 */ 2686 static int intel_base_nid(struct hda_codec *codec) 2687 { 2688 switch (codec->core.vendor_id) { 2689 case 0x80860054: /* ILK */ 2690 case 0x80862804: /* ILK */ 2691 case 0x80862882: /* VLV */ 2692 return 4; 2693 default: 2694 return 5; 2695 } 2696 } 2697 2698 static int intel_pin2port(void *audio_ptr, int pin_nid) 2699 { 2700 struct hda_codec *codec = audio_ptr; 2701 struct hdmi_spec *spec = codec->spec; 2702 int base_nid, i; 2703 2704 if (!spec->port_num) { 2705 base_nid = intel_base_nid(codec); 2706 if (WARN_ON(pin_nid < base_nid || pin_nid >= base_nid + 3)) 2707 return -1; 2708 return pin_nid - base_nid + 1; 2709 } 2710 2711 /* 2712 * looking for the pin number in the mapping table and return 2713 * the index which indicate the port number 2714 */ 2715 for (i = 0; i < spec->port_num; i++) { 2716 if (pin_nid == spec->port_map[i]) 2717 return i; 2718 } 2719 2720 codec_info(codec, "Can't find the HDMI/DP port for pin %d\n", pin_nid); 2721 return -1; 2722 } 2723 2724 static int intel_port2pin(struct hda_codec *codec, int port) 2725 { 2726 struct hdmi_spec *spec = codec->spec; 2727 2728 if (!spec->port_num) { 2729 /* we assume only from port-B to port-D */ 2730 if (port < 1 || port > 3) 2731 return 0; 2732 return port + intel_base_nid(codec) - 1; 2733 } 2734 2735 if (port < 0 || port >= spec->port_num) 2736 return 0; 2737 return spec->port_map[port]; 2738 } 2739 2740 static void intel_pin_eld_notify(void *audio_ptr, int port, int pipe) 2741 { 2742 struct hda_codec *codec = audio_ptr; 2743 int pin_nid; 2744 int dev_id = pipe; 2745 2746 pin_nid = intel_port2pin(codec, port); 2747 if (!pin_nid) 2748 return; 2749 /* skip notification during system suspend (but not in runtime PM); 2750 * the state will be updated at resume 2751 */ 2752 if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0) 2753 return; 2754 /* ditto during suspend/resume process itself */ 2755 if (snd_hdac_is_in_pm(&codec->core)) 2756 return; 2757 2758 snd_hdac_i915_set_bclk(&codec->bus->core); 2759 check_presence_and_report(codec, pin_nid, dev_id); 2760 } 2761 2762 static const struct drm_audio_component_audio_ops intel_audio_ops = { 2763 .pin2port = intel_pin2port, 2764 .pin_eld_notify = intel_pin_eld_notify, 2765 }; 2766 2767 /* register i915 component pin_eld_notify callback */ 2768 static void register_i915_notifier(struct hda_codec *codec) 2769 { 2770 struct hdmi_spec *spec = codec->spec; 2771 2772 spec->use_acomp_notifier = true; 2773 spec->port2pin = intel_port2pin; 2774 setup_drm_audio_ops(codec, &intel_audio_ops); 2775 snd_hdac_acomp_register_notifier(&codec->bus->core, 2776 &spec->drm_audio_ops); 2777 /* no need for forcible resume for jack check thanks to notifier */ 2778 codec->relaxed_resume = 1; 2779 } 2780 2781 /* setup_stream ops override for HSW+ */ 2782 static int i915_hsw_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, 2783 hda_nid_t pin_nid, int dev_id, u32 stream_tag, 2784 int format) 2785 { 2786 haswell_verify_D0(codec, cvt_nid, pin_nid); 2787 return hdmi_setup_stream(codec, cvt_nid, pin_nid, dev_id, 2788 stream_tag, format); 2789 } 2790 2791 /* pin_cvt_fixup ops override for HSW+ and VLV+ */ 2792 static void i915_pin_cvt_fixup(struct hda_codec *codec, 2793 struct hdmi_spec_per_pin *per_pin, 2794 hda_nid_t cvt_nid) 2795 { 2796 if (per_pin) { 2797 snd_hda_set_dev_select(codec, per_pin->pin_nid, 2798 per_pin->dev_id); 2799 intel_verify_pin_cvt_connect(codec, per_pin); 2800 intel_not_share_assigned_cvt(codec, per_pin->pin_nid, 2801 per_pin->dev_id, per_pin->mux_idx); 2802 } else { 2803 intel_not_share_assigned_cvt_nid(codec, 0, 0, cvt_nid); 2804 } 2805 } 2806 2807 /* precondition and allocation for Intel codecs */ 2808 static int alloc_intel_hdmi(struct hda_codec *codec) 2809 { 2810 int err; 2811 2812 /* requires i915 binding */ 2813 if (!codec->bus->core.audio_component) { 2814 codec_info(codec, "No i915 binding for Intel HDMI/DP codec\n"); 2815 /* set probe_id here to prevent generic fallback binding */ 2816 codec->probe_id = HDA_CODEC_ID_SKIP_PROBE; 2817 return -ENODEV; 2818 } 2819 2820 err = alloc_generic_hdmi(codec); 2821 if (err < 0) 2822 return err; 2823 /* no need to handle unsol events */ 2824 codec->patch_ops.unsol_event = NULL; 2825 return 0; 2826 } 2827 2828 /* parse and post-process for Intel codecs */ 2829 static int parse_intel_hdmi(struct hda_codec *codec) 2830 { 2831 int err; 2832 2833 err = hdmi_parse_codec(codec); 2834 if (err < 0) { 2835 generic_spec_free(codec); 2836 return err; 2837 } 2838 2839 generic_hdmi_init_per_pins(codec); 2840 register_i915_notifier(codec); 2841 return 0; 2842 } 2843 2844 /* Intel Haswell and onwards; audio component with eld notifier */ 2845 static int intel_hsw_common_init(struct hda_codec *codec, hda_nid_t vendor_nid, 2846 const int *port_map, int port_num) 2847 { 2848 struct hdmi_spec *spec; 2849 int err; 2850 2851 err = alloc_intel_hdmi(codec); 2852 if (err < 0) 2853 return err; 2854 spec = codec->spec; 2855 codec->dp_mst = true; 2856 spec->dyn_pcm_assign = true; 2857 spec->vendor_nid = vendor_nid; 2858 spec->port_map = port_map; 2859 spec->port_num = port_num; 2860 spec->intel_hsw_fixup = true; 2861 2862 intel_haswell_enable_all_pins(codec, true); 2863 intel_haswell_fixup_enable_dp12(codec); 2864 2865 codec->display_power_control = 1; 2866 2867 codec->patch_ops.set_power_state = haswell_set_power_state; 2868 codec->depop_delay = 0; 2869 codec->auto_runtime_pm = 1; 2870 2871 spec->ops.setup_stream = i915_hsw_setup_stream; 2872 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup; 2873 2874 return parse_intel_hdmi(codec); 2875 } 2876 2877 static int patch_i915_hsw_hdmi(struct hda_codec *codec) 2878 { 2879 return intel_hsw_common_init(codec, 0x08, NULL, 0); 2880 } 2881 2882 static int patch_i915_glk_hdmi(struct hda_codec *codec) 2883 { 2884 return intel_hsw_common_init(codec, 0x0b, NULL, 0); 2885 } 2886 2887 static int patch_i915_icl_hdmi(struct hda_codec *codec) 2888 { 2889 /* 2890 * pin to port mapping table where the value indicate the pin number and 2891 * the index indicate the port number. 2892 */ 2893 static const int map[] = {0x0, 0x4, 0x6, 0x8, 0xa, 0xb}; 2894 2895 return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map)); 2896 } 2897 2898 static int patch_i915_tgl_hdmi(struct hda_codec *codec) 2899 { 2900 /* 2901 * pin to port mapping table where the value indicate the pin number and 2902 * the index indicate the port number. 2903 */ 2904 static const int map[] = {0x4, 0x6, 0x8, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf}; 2905 2906 return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map)); 2907 } 2908 2909 /* Intel Baytrail and Braswell; with eld notifier */ 2910 static int patch_i915_byt_hdmi(struct hda_codec *codec) 2911 { 2912 struct hdmi_spec *spec; 2913 int err; 2914 2915 err = alloc_intel_hdmi(codec); 2916 if (err < 0) 2917 return err; 2918 spec = codec->spec; 2919 2920 /* For Valleyview/Cherryview, only the display codec is in the display 2921 * power well and can use link_power ops to request/release the power. 2922 */ 2923 codec->display_power_control = 1; 2924 2925 codec->depop_delay = 0; 2926 codec->auto_runtime_pm = 1; 2927 2928 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup; 2929 2930 return parse_intel_hdmi(codec); 2931 } 2932 2933 /* Intel IronLake, SandyBridge and IvyBridge; with eld notifier */ 2934 static int patch_i915_cpt_hdmi(struct hda_codec *codec) 2935 { 2936 int err; 2937 2938 err = alloc_intel_hdmi(codec); 2939 if (err < 0) 2940 return err; 2941 return parse_intel_hdmi(codec); 2942 } 2943 2944 /* 2945 * Shared non-generic implementations 2946 */ 2947 2948 static int simple_playback_build_pcms(struct hda_codec *codec) 2949 { 2950 struct hdmi_spec *spec = codec->spec; 2951 struct hda_pcm *info; 2952 unsigned int chans; 2953 struct hda_pcm_stream *pstr; 2954 struct hdmi_spec_per_cvt *per_cvt; 2955 2956 per_cvt = get_cvt(spec, 0); 2957 chans = get_wcaps(codec, per_cvt->cvt_nid); 2958 chans = get_wcaps_channels(chans); 2959 2960 info = snd_hda_codec_pcm_new(codec, "HDMI 0"); 2961 if (!info) 2962 return -ENOMEM; 2963 spec->pcm_rec[0].pcm = info; 2964 info->pcm_type = HDA_PCM_TYPE_HDMI; 2965 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK]; 2966 *pstr = spec->pcm_playback; 2967 pstr->nid = per_cvt->cvt_nid; 2968 if (pstr->channels_max <= 2 && chans && chans <= 16) 2969 pstr->channels_max = chans; 2970 2971 return 0; 2972 } 2973 2974 /* unsolicited event for jack sensing */ 2975 static void simple_hdmi_unsol_event(struct hda_codec *codec, 2976 unsigned int res) 2977 { 2978 snd_hda_jack_set_dirty_all(codec); 2979 snd_hda_jack_report_sync(codec); 2980 } 2981 2982 /* generic_hdmi_build_jack can be used for simple_hdmi, too, 2983 * as long as spec->pins[] is set correctly 2984 */ 2985 #define simple_hdmi_build_jack generic_hdmi_build_jack 2986 2987 static int simple_playback_build_controls(struct hda_codec *codec) 2988 { 2989 struct hdmi_spec *spec = codec->spec; 2990 struct hdmi_spec_per_cvt *per_cvt; 2991 int err; 2992 2993 per_cvt = get_cvt(spec, 0); 2994 err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid, 2995 per_cvt->cvt_nid, 2996 HDA_PCM_TYPE_HDMI); 2997 if (err < 0) 2998 return err; 2999 return simple_hdmi_build_jack(codec, 0); 3000 } 3001 3002 static int simple_playback_init(struct hda_codec *codec) 3003 { 3004 struct hdmi_spec *spec = codec->spec; 3005 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0); 3006 hda_nid_t pin = per_pin->pin_nid; 3007 3008 snd_hda_codec_write(codec, pin, 0, 3009 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT); 3010 /* some codecs require to unmute the pin */ 3011 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP) 3012 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE, 3013 AMP_OUT_UNMUTE); 3014 snd_hda_jack_detect_enable(codec, pin, per_pin->dev_id); 3015 return 0; 3016 } 3017 3018 static void simple_playback_free(struct hda_codec *codec) 3019 { 3020 struct hdmi_spec *spec = codec->spec; 3021 3022 hdmi_array_free(spec); 3023 kfree(spec); 3024 } 3025 3026 /* 3027 * Nvidia specific implementations 3028 */ 3029 3030 #define Nv_VERB_SET_Channel_Allocation 0xF79 3031 #define Nv_VERB_SET_Info_Frame_Checksum 0xF7A 3032 #define Nv_VERB_SET_Audio_Protection_On 0xF98 3033 #define Nv_VERB_SET_Audio_Protection_Off 0xF99 3034 3035 #define nvhdmi_master_con_nid_7x 0x04 3036 #define nvhdmi_master_pin_nid_7x 0x05 3037 3038 static const hda_nid_t nvhdmi_con_nids_7x[4] = { 3039 /*front, rear, clfe, rear_surr */ 3040 0x6, 0x8, 0xa, 0xc, 3041 }; 3042 3043 static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = { 3044 /* set audio protect on */ 3045 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1}, 3046 /* enable digital output on pin widget */ 3047 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3048 {} /* terminator */ 3049 }; 3050 3051 static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = { 3052 /* set audio protect on */ 3053 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1}, 3054 /* enable digital output on pin widget */ 3055 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3056 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3057 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3058 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3059 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3060 {} /* terminator */ 3061 }; 3062 3063 #ifdef LIMITED_RATE_FMT_SUPPORT 3064 /* support only the safe format and rate */ 3065 #define SUPPORTED_RATES SNDRV_PCM_RATE_48000 3066 #define SUPPORTED_MAXBPS 16 3067 #define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE 3068 #else 3069 /* support all rates and formats */ 3070 #define SUPPORTED_RATES \ 3071 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\ 3072 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\ 3073 SNDRV_PCM_RATE_192000) 3074 #define SUPPORTED_MAXBPS 24 3075 #define SUPPORTED_FORMATS \ 3076 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE) 3077 #endif 3078 3079 static int nvhdmi_7x_init_2ch(struct hda_codec *codec) 3080 { 3081 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch); 3082 return 0; 3083 } 3084 3085 static int nvhdmi_7x_init_8ch(struct hda_codec *codec) 3086 { 3087 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch); 3088 return 0; 3089 } 3090 3091 static const unsigned int channels_2_6_8[] = { 3092 2, 6, 8 3093 }; 3094 3095 static const unsigned int channels_2_8[] = { 3096 2, 8 3097 }; 3098 3099 static const struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = { 3100 .count = ARRAY_SIZE(channels_2_6_8), 3101 .list = channels_2_6_8, 3102 .mask = 0, 3103 }; 3104 3105 static const struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = { 3106 .count = ARRAY_SIZE(channels_2_8), 3107 .list = channels_2_8, 3108 .mask = 0, 3109 }; 3110 3111 static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo, 3112 struct hda_codec *codec, 3113 struct snd_pcm_substream *substream) 3114 { 3115 struct hdmi_spec *spec = codec->spec; 3116 const struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL; 3117 3118 switch (codec->preset->vendor_id) { 3119 case 0x10de0002: 3120 case 0x10de0003: 3121 case 0x10de0005: 3122 case 0x10de0006: 3123 hw_constraints_channels = &hw_constraints_2_8_channels; 3124 break; 3125 case 0x10de0007: 3126 hw_constraints_channels = &hw_constraints_2_6_8_channels; 3127 break; 3128 default: 3129 break; 3130 } 3131 3132 if (hw_constraints_channels != NULL) { 3133 snd_pcm_hw_constraint_list(substream->runtime, 0, 3134 SNDRV_PCM_HW_PARAM_CHANNELS, 3135 hw_constraints_channels); 3136 } else { 3137 snd_pcm_hw_constraint_step(substream->runtime, 0, 3138 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 3139 } 3140 3141 return snd_hda_multi_out_dig_open(codec, &spec->multiout); 3142 } 3143 3144 static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo, 3145 struct hda_codec *codec, 3146 struct snd_pcm_substream *substream) 3147 { 3148 struct hdmi_spec *spec = codec->spec; 3149 return snd_hda_multi_out_dig_close(codec, &spec->multiout); 3150 } 3151 3152 static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 3153 struct hda_codec *codec, 3154 unsigned int stream_tag, 3155 unsigned int format, 3156 struct snd_pcm_substream *substream) 3157 { 3158 struct hdmi_spec *spec = codec->spec; 3159 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout, 3160 stream_tag, format, substream); 3161 } 3162 3163 static const struct hda_pcm_stream simple_pcm_playback = { 3164 .substreams = 1, 3165 .channels_min = 2, 3166 .channels_max = 2, 3167 .ops = { 3168 .open = simple_playback_pcm_open, 3169 .close = simple_playback_pcm_close, 3170 .prepare = simple_playback_pcm_prepare 3171 }, 3172 }; 3173 3174 static const struct hda_codec_ops simple_hdmi_patch_ops = { 3175 .build_controls = simple_playback_build_controls, 3176 .build_pcms = simple_playback_build_pcms, 3177 .init = simple_playback_init, 3178 .free = simple_playback_free, 3179 .unsol_event = simple_hdmi_unsol_event, 3180 }; 3181 3182 static int patch_simple_hdmi(struct hda_codec *codec, 3183 hda_nid_t cvt_nid, hda_nid_t pin_nid) 3184 { 3185 struct hdmi_spec *spec; 3186 struct hdmi_spec_per_cvt *per_cvt; 3187 struct hdmi_spec_per_pin *per_pin; 3188 3189 spec = kzalloc(sizeof(*spec), GFP_KERNEL); 3190 if (!spec) 3191 return -ENOMEM; 3192 3193 spec->codec = codec; 3194 codec->spec = spec; 3195 hdmi_array_init(spec, 1); 3196 3197 spec->multiout.num_dacs = 0; /* no analog */ 3198 spec->multiout.max_channels = 2; 3199 spec->multiout.dig_out_nid = cvt_nid; 3200 spec->num_cvts = 1; 3201 spec->num_pins = 1; 3202 per_pin = snd_array_new(&spec->pins); 3203 per_cvt = snd_array_new(&spec->cvts); 3204 if (!per_pin || !per_cvt) { 3205 simple_playback_free(codec); 3206 return -ENOMEM; 3207 } 3208 per_cvt->cvt_nid = cvt_nid; 3209 per_pin->pin_nid = pin_nid; 3210 spec->pcm_playback = simple_pcm_playback; 3211 3212 codec->patch_ops = simple_hdmi_patch_ops; 3213 3214 return 0; 3215 } 3216 3217 static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec, 3218 int channels) 3219 { 3220 unsigned int chanmask; 3221 int chan = channels ? (channels - 1) : 1; 3222 3223 switch (channels) { 3224 default: 3225 case 0: 3226 case 2: 3227 chanmask = 0x00; 3228 break; 3229 case 4: 3230 chanmask = 0x08; 3231 break; 3232 case 6: 3233 chanmask = 0x0b; 3234 break; 3235 case 8: 3236 chanmask = 0x13; 3237 break; 3238 } 3239 3240 /* Set the audio infoframe channel allocation and checksum fields. The 3241 * channel count is computed implicitly by the hardware. */ 3242 snd_hda_codec_write(codec, 0x1, 0, 3243 Nv_VERB_SET_Channel_Allocation, chanmask); 3244 3245 snd_hda_codec_write(codec, 0x1, 0, 3246 Nv_VERB_SET_Info_Frame_Checksum, 3247 (0x71 - chan - chanmask)); 3248 } 3249 3250 static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo, 3251 struct hda_codec *codec, 3252 struct snd_pcm_substream *substream) 3253 { 3254 struct hdmi_spec *spec = codec->spec; 3255 int i; 3256 3257 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 3258 0, AC_VERB_SET_CHANNEL_STREAMID, 0); 3259 for (i = 0; i < 4; i++) { 3260 /* set the stream id */ 3261 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0, 3262 AC_VERB_SET_CHANNEL_STREAMID, 0); 3263 /* set the stream format */ 3264 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0, 3265 AC_VERB_SET_STREAM_FORMAT, 0); 3266 } 3267 3268 /* The audio hardware sends a channel count of 0x7 (8ch) when all the 3269 * streams are disabled. */ 3270 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8); 3271 3272 return snd_hda_multi_out_dig_close(codec, &spec->multiout); 3273 } 3274 3275 static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo, 3276 struct hda_codec *codec, 3277 unsigned int stream_tag, 3278 unsigned int format, 3279 struct snd_pcm_substream *substream) 3280 { 3281 int chs; 3282 unsigned int dataDCC2, channel_id; 3283 int i; 3284 struct hdmi_spec *spec = codec->spec; 3285 struct hda_spdif_out *spdif; 3286 struct hdmi_spec_per_cvt *per_cvt; 3287 3288 mutex_lock(&codec->spdif_mutex); 3289 per_cvt = get_cvt(spec, 0); 3290 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid); 3291 3292 chs = substream->runtime->channels; 3293 3294 dataDCC2 = 0x2; 3295 3296 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */ 3297 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) 3298 snd_hda_codec_write(codec, 3299 nvhdmi_master_con_nid_7x, 3300 0, 3301 AC_VERB_SET_DIGI_CONVERT_1, 3302 spdif->ctls & ~AC_DIG1_ENABLE & 0xff); 3303 3304 /* set the stream id */ 3305 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0, 3306 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0); 3307 3308 /* set the stream format */ 3309 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0, 3310 AC_VERB_SET_STREAM_FORMAT, format); 3311 3312 /* turn on again (if needed) */ 3313 /* enable and set the channel status audio/data flag */ 3314 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) { 3315 snd_hda_codec_write(codec, 3316 nvhdmi_master_con_nid_7x, 3317 0, 3318 AC_VERB_SET_DIGI_CONVERT_1, 3319 spdif->ctls & 0xff); 3320 snd_hda_codec_write(codec, 3321 nvhdmi_master_con_nid_7x, 3322 0, 3323 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2); 3324 } 3325 3326 for (i = 0; i < 4; i++) { 3327 if (chs == 2) 3328 channel_id = 0; 3329 else 3330 channel_id = i * 2; 3331 3332 /* turn off SPDIF once; 3333 *otherwise the IEC958 bits won't be updated 3334 */ 3335 if (codec->spdif_status_reset && 3336 (spdif->ctls & AC_DIG1_ENABLE)) 3337 snd_hda_codec_write(codec, 3338 nvhdmi_con_nids_7x[i], 3339 0, 3340 AC_VERB_SET_DIGI_CONVERT_1, 3341 spdif->ctls & ~AC_DIG1_ENABLE & 0xff); 3342 /* set the stream id */ 3343 snd_hda_codec_write(codec, 3344 nvhdmi_con_nids_7x[i], 3345 0, 3346 AC_VERB_SET_CHANNEL_STREAMID, 3347 (stream_tag << 4) | channel_id); 3348 /* set the stream format */ 3349 snd_hda_codec_write(codec, 3350 nvhdmi_con_nids_7x[i], 3351 0, 3352 AC_VERB_SET_STREAM_FORMAT, 3353 format); 3354 /* turn on again (if needed) */ 3355 /* enable and set the channel status audio/data flag */ 3356 if (codec->spdif_status_reset && 3357 (spdif->ctls & AC_DIG1_ENABLE)) { 3358 snd_hda_codec_write(codec, 3359 nvhdmi_con_nids_7x[i], 3360 0, 3361 AC_VERB_SET_DIGI_CONVERT_1, 3362 spdif->ctls & 0xff); 3363 snd_hda_codec_write(codec, 3364 nvhdmi_con_nids_7x[i], 3365 0, 3366 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2); 3367 } 3368 } 3369 3370 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs); 3371 3372 mutex_unlock(&codec->spdif_mutex); 3373 return 0; 3374 } 3375 3376 static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = { 3377 .substreams = 1, 3378 .channels_min = 2, 3379 .channels_max = 8, 3380 .nid = nvhdmi_master_con_nid_7x, 3381 .rates = SUPPORTED_RATES, 3382 .maxbps = SUPPORTED_MAXBPS, 3383 .formats = SUPPORTED_FORMATS, 3384 .ops = { 3385 .open = simple_playback_pcm_open, 3386 .close = nvhdmi_8ch_7x_pcm_close, 3387 .prepare = nvhdmi_8ch_7x_pcm_prepare 3388 }, 3389 }; 3390 3391 static int patch_nvhdmi_2ch(struct hda_codec *codec) 3392 { 3393 struct hdmi_spec *spec; 3394 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x, 3395 nvhdmi_master_pin_nid_7x); 3396 if (err < 0) 3397 return err; 3398 3399 codec->patch_ops.init = nvhdmi_7x_init_2ch; 3400 /* override the PCM rates, etc, as the codec doesn't give full list */ 3401 spec = codec->spec; 3402 spec->pcm_playback.rates = SUPPORTED_RATES; 3403 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS; 3404 spec->pcm_playback.formats = SUPPORTED_FORMATS; 3405 return 0; 3406 } 3407 3408 static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec) 3409 { 3410 struct hdmi_spec *spec = codec->spec; 3411 int err = simple_playback_build_pcms(codec); 3412 if (!err) { 3413 struct hda_pcm *info = get_pcm_rec(spec, 0); 3414 info->own_chmap = true; 3415 } 3416 return err; 3417 } 3418 3419 static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec) 3420 { 3421 struct hdmi_spec *spec = codec->spec; 3422 struct hda_pcm *info; 3423 struct snd_pcm_chmap *chmap; 3424 int err; 3425 3426 err = simple_playback_build_controls(codec); 3427 if (err < 0) 3428 return err; 3429 3430 /* add channel maps */ 3431 info = get_pcm_rec(spec, 0); 3432 err = snd_pcm_add_chmap_ctls(info->pcm, 3433 SNDRV_PCM_STREAM_PLAYBACK, 3434 snd_pcm_alt_chmaps, 8, 0, &chmap); 3435 if (err < 0) 3436 return err; 3437 switch (codec->preset->vendor_id) { 3438 case 0x10de0002: 3439 case 0x10de0003: 3440 case 0x10de0005: 3441 case 0x10de0006: 3442 chmap->channel_mask = (1U << 2) | (1U << 8); 3443 break; 3444 case 0x10de0007: 3445 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8); 3446 } 3447 return 0; 3448 } 3449 3450 static int patch_nvhdmi_8ch_7x(struct hda_codec *codec) 3451 { 3452 struct hdmi_spec *spec; 3453 int err = patch_nvhdmi_2ch(codec); 3454 if (err < 0) 3455 return err; 3456 spec = codec->spec; 3457 spec->multiout.max_channels = 8; 3458 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x; 3459 codec->patch_ops.init = nvhdmi_7x_init_8ch; 3460 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms; 3461 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls; 3462 3463 /* Initialize the audio infoframe channel mask and checksum to something 3464 * valid */ 3465 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8); 3466 3467 return 0; 3468 } 3469 3470 /* 3471 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on: 3472 * - 0x10de0015 3473 * - 0x10de0040 3474 */ 3475 static int nvhdmi_chmap_cea_alloc_validate_get_type(struct hdac_chmap *chmap, 3476 struct hdac_cea_channel_speaker_allocation *cap, int channels) 3477 { 3478 if (cap->ca_index == 0x00 && channels == 2) 3479 return SNDRV_CTL_TLVT_CHMAP_FIXED; 3480 3481 /* If the speaker allocation matches the channel count, it is OK. */ 3482 if (cap->channels != channels) 3483 return -1; 3484 3485 /* all channels are remappable freely */ 3486 return SNDRV_CTL_TLVT_CHMAP_VAR; 3487 } 3488 3489 static int nvhdmi_chmap_validate(struct hdac_chmap *chmap, 3490 int ca, int chs, unsigned char *map) 3491 { 3492 if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR)) 3493 return -EINVAL; 3494 3495 return 0; 3496 } 3497 3498 /* map from pin NID to port; port is 0-based */ 3499 /* for Nvidia: assume widget NID starting from 4, with step 1 (4, 5, 6, ...) */ 3500 static int nvhdmi_pin2port(void *audio_ptr, int pin_nid) 3501 { 3502 return pin_nid - 4; 3503 } 3504 3505 /* reverse-map from port to pin NID: see above */ 3506 static int nvhdmi_port2pin(struct hda_codec *codec, int port) 3507 { 3508 return port + 4; 3509 } 3510 3511 static const struct drm_audio_component_audio_ops nvhdmi_audio_ops = { 3512 .pin2port = nvhdmi_pin2port, 3513 .pin_eld_notify = generic_acomp_pin_eld_notify, 3514 .master_bind = generic_acomp_master_bind, 3515 .master_unbind = generic_acomp_master_unbind, 3516 }; 3517 3518 static int patch_nvhdmi(struct hda_codec *codec) 3519 { 3520 struct hdmi_spec *spec; 3521 int err; 3522 3523 err = alloc_generic_hdmi(codec); 3524 if (err < 0) 3525 return err; 3526 codec->dp_mst = true; 3527 3528 spec = codec->spec; 3529 spec->dyn_pcm_assign = true; 3530 3531 err = hdmi_parse_codec(codec); 3532 if (err < 0) { 3533 generic_spec_free(codec); 3534 return err; 3535 } 3536 3537 generic_hdmi_init_per_pins(codec); 3538 3539 spec->dyn_pin_out = true; 3540 3541 spec->chmap.ops.chmap_cea_alloc_validate_get_type = 3542 nvhdmi_chmap_cea_alloc_validate_get_type; 3543 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate; 3544 3545 codec->link_down_at_suspend = 1; 3546 3547 generic_acomp_init(codec, &nvhdmi_audio_ops, nvhdmi_port2pin); 3548 3549 return 0; 3550 } 3551 3552 static int patch_nvhdmi_legacy(struct hda_codec *codec) 3553 { 3554 struct hdmi_spec *spec; 3555 int err; 3556 3557 err = patch_generic_hdmi(codec); 3558 if (err) 3559 return err; 3560 3561 spec = codec->spec; 3562 spec->dyn_pin_out = true; 3563 3564 spec->chmap.ops.chmap_cea_alloc_validate_get_type = 3565 nvhdmi_chmap_cea_alloc_validate_get_type; 3566 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate; 3567 3568 codec->link_down_at_suspend = 1; 3569 3570 return 0; 3571 } 3572 3573 /* 3574 * The HDA codec on NVIDIA Tegra contains two scratch registers that are 3575 * accessed using vendor-defined verbs. These registers can be used for 3576 * interoperability between the HDA and HDMI drivers. 3577 */ 3578 3579 /* Audio Function Group node */ 3580 #define NVIDIA_AFG_NID 0x01 3581 3582 /* 3583 * The SCRATCH0 register is used to notify the HDMI codec of changes in audio 3584 * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to 3585 * be raised in the HDMI codec. The remainder of the bits is arbitrary. This 3586 * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an 3587 * additional bit (at position 30) to signal the validity of the format. 3588 * 3589 * | 31 | 30 | 29 16 | 15 0 | 3590 * +---------+-------+--------+--------+ 3591 * | TRIGGER | VALID | UNUSED | FORMAT | 3592 * +-----------------------------------| 3593 * 3594 * Note that for the trigger bit to take effect it needs to change value 3595 * (i.e. it needs to be toggled). 3596 */ 3597 #define NVIDIA_GET_SCRATCH0 0xfa6 3598 #define NVIDIA_SET_SCRATCH0_BYTE0 0xfa7 3599 #define NVIDIA_SET_SCRATCH0_BYTE1 0xfa8 3600 #define NVIDIA_SET_SCRATCH0_BYTE2 0xfa9 3601 #define NVIDIA_SET_SCRATCH0_BYTE3 0xfaa 3602 #define NVIDIA_SCRATCH_TRIGGER (1 << 7) 3603 #define NVIDIA_SCRATCH_VALID (1 << 6) 3604 3605 #define NVIDIA_GET_SCRATCH1 0xfab 3606 #define NVIDIA_SET_SCRATCH1_BYTE0 0xfac 3607 #define NVIDIA_SET_SCRATCH1_BYTE1 0xfad 3608 #define NVIDIA_SET_SCRATCH1_BYTE2 0xfae 3609 #define NVIDIA_SET_SCRATCH1_BYTE3 0xfaf 3610 3611 /* 3612 * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0, 3613 * the format is invalidated so that the HDMI codec can be disabled. 3614 */ 3615 static void tegra_hdmi_set_format(struct hda_codec *codec, unsigned int format) 3616 { 3617 unsigned int value; 3618 3619 /* bits [31:30] contain the trigger and valid bits */ 3620 value = snd_hda_codec_read(codec, NVIDIA_AFG_NID, 0, 3621 NVIDIA_GET_SCRATCH0, 0); 3622 value = (value >> 24) & 0xff; 3623 3624 /* bits [15:0] are used to store the HDA format */ 3625 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, 3626 NVIDIA_SET_SCRATCH0_BYTE0, 3627 (format >> 0) & 0xff); 3628 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, 3629 NVIDIA_SET_SCRATCH0_BYTE1, 3630 (format >> 8) & 0xff); 3631 3632 /* bits [16:24] are unused */ 3633 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, 3634 NVIDIA_SET_SCRATCH0_BYTE2, 0); 3635 3636 /* 3637 * Bit 30 signals that the data is valid and hence that HDMI audio can 3638 * be enabled. 3639 */ 3640 if (format == 0) 3641 value &= ~NVIDIA_SCRATCH_VALID; 3642 else 3643 value |= NVIDIA_SCRATCH_VALID; 3644 3645 /* 3646 * Whenever the trigger bit is toggled, an interrupt is raised in the 3647 * HDMI codec. The HDMI driver will use that as trigger to update its 3648 * configuration. 3649 */ 3650 value ^= NVIDIA_SCRATCH_TRIGGER; 3651 3652 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, 3653 NVIDIA_SET_SCRATCH0_BYTE3, value); 3654 } 3655 3656 static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo, 3657 struct hda_codec *codec, 3658 unsigned int stream_tag, 3659 unsigned int format, 3660 struct snd_pcm_substream *substream) 3661 { 3662 int err; 3663 3664 err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag, 3665 format, substream); 3666 if (err < 0) 3667 return err; 3668 3669 /* notify the HDMI codec of the format change */ 3670 tegra_hdmi_set_format(codec, format); 3671 3672 return 0; 3673 } 3674 3675 static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo, 3676 struct hda_codec *codec, 3677 struct snd_pcm_substream *substream) 3678 { 3679 /* invalidate the format in the HDMI codec */ 3680 tegra_hdmi_set_format(codec, 0); 3681 3682 return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream); 3683 } 3684 3685 static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type) 3686 { 3687 struct hdmi_spec *spec = codec->spec; 3688 unsigned int i; 3689 3690 for (i = 0; i < spec->num_pins; i++) { 3691 struct hda_pcm *pcm = get_pcm_rec(spec, i); 3692 3693 if (pcm->pcm_type == type) 3694 return pcm; 3695 } 3696 3697 return NULL; 3698 } 3699 3700 static int tegra_hdmi_build_pcms(struct hda_codec *codec) 3701 { 3702 struct hda_pcm_stream *stream; 3703 struct hda_pcm *pcm; 3704 int err; 3705 3706 err = generic_hdmi_build_pcms(codec); 3707 if (err < 0) 3708 return err; 3709 3710 pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI); 3711 if (!pcm) 3712 return -ENODEV; 3713 3714 /* 3715 * Override ->prepare() and ->cleanup() operations to notify the HDMI 3716 * codec about format changes. 3717 */ 3718 stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK]; 3719 stream->ops.prepare = tegra_hdmi_pcm_prepare; 3720 stream->ops.cleanup = tegra_hdmi_pcm_cleanup; 3721 3722 return 0; 3723 } 3724 3725 static int patch_tegra_hdmi(struct hda_codec *codec) 3726 { 3727 int err; 3728 3729 err = patch_generic_hdmi(codec); 3730 if (err) 3731 return err; 3732 3733 codec->patch_ops.build_pcms = tegra_hdmi_build_pcms; 3734 3735 return 0; 3736 } 3737 3738 /* 3739 * ATI/AMD-specific implementations 3740 */ 3741 3742 #define is_amdhdmi_rev3_or_later(codec) \ 3743 ((codec)->core.vendor_id == 0x1002aa01 && \ 3744 ((codec)->core.revision_id & 0xff00) >= 0x0300) 3745 #define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec) 3746 3747 /* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */ 3748 #define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771 3749 #define ATI_VERB_SET_DOWNMIX_INFO 0x772 3750 #define ATI_VERB_SET_MULTICHANNEL_01 0x777 3751 #define ATI_VERB_SET_MULTICHANNEL_23 0x778 3752 #define ATI_VERB_SET_MULTICHANNEL_45 0x779 3753 #define ATI_VERB_SET_MULTICHANNEL_67 0x77a 3754 #define ATI_VERB_SET_HBR_CONTROL 0x77c 3755 #define ATI_VERB_SET_MULTICHANNEL_1 0x785 3756 #define ATI_VERB_SET_MULTICHANNEL_3 0x786 3757 #define ATI_VERB_SET_MULTICHANNEL_5 0x787 3758 #define ATI_VERB_SET_MULTICHANNEL_7 0x788 3759 #define ATI_VERB_SET_MULTICHANNEL_MODE 0x789 3760 #define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71 3761 #define ATI_VERB_GET_DOWNMIX_INFO 0xf72 3762 #define ATI_VERB_GET_MULTICHANNEL_01 0xf77 3763 #define ATI_VERB_GET_MULTICHANNEL_23 0xf78 3764 #define ATI_VERB_GET_MULTICHANNEL_45 0xf79 3765 #define ATI_VERB_GET_MULTICHANNEL_67 0xf7a 3766 #define ATI_VERB_GET_HBR_CONTROL 0xf7c 3767 #define ATI_VERB_GET_MULTICHANNEL_1 0xf85 3768 #define ATI_VERB_GET_MULTICHANNEL_3 0xf86 3769 #define ATI_VERB_GET_MULTICHANNEL_5 0xf87 3770 #define ATI_VERB_GET_MULTICHANNEL_7 0xf88 3771 #define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89 3772 3773 /* AMD specific HDA cvt verbs */ 3774 #define ATI_VERB_SET_RAMP_RATE 0x770 3775 #define ATI_VERB_GET_RAMP_RATE 0xf70 3776 3777 #define ATI_OUT_ENABLE 0x1 3778 3779 #define ATI_MULTICHANNEL_MODE_PAIRED 0 3780 #define ATI_MULTICHANNEL_MODE_SINGLE 1 3781 3782 #define ATI_HBR_CAPABLE 0x01 3783 #define ATI_HBR_ENABLE 0x10 3784 3785 static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid, 3786 int dev_id, unsigned char *buf, int *eld_size) 3787 { 3788 WARN_ON(dev_id != 0); 3789 /* call hda_eld.c ATI/AMD-specific function */ 3790 return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size, 3791 is_amdhdmi_rev3_or_later(codec)); 3792 } 3793 3794 static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, 3795 hda_nid_t pin_nid, int dev_id, int ca, 3796 int active_channels, int conn_type) 3797 { 3798 WARN_ON(dev_id != 0); 3799 snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca); 3800 } 3801 3802 static int atihdmi_paired_swap_fc_lfe(int pos) 3803 { 3804 /* 3805 * ATI/AMD have automatic FC/LFE swap built-in 3806 * when in pairwise mapping mode. 3807 */ 3808 3809 switch (pos) { 3810 /* see channel_allocations[].speakers[] */ 3811 case 2: return 3; 3812 case 3: return 2; 3813 default: break; 3814 } 3815 3816 return pos; 3817 } 3818 3819 static int atihdmi_paired_chmap_validate(struct hdac_chmap *chmap, 3820 int ca, int chs, unsigned char *map) 3821 { 3822 struct hdac_cea_channel_speaker_allocation *cap; 3823 int i, j; 3824 3825 /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */ 3826 3827 cap = snd_hdac_get_ch_alloc_from_ca(ca); 3828 for (i = 0; i < chs; ++i) { 3829 int mask = snd_hdac_chmap_to_spk_mask(map[i]); 3830 bool ok = false; 3831 bool companion_ok = false; 3832 3833 if (!mask) 3834 continue; 3835 3836 for (j = 0 + i % 2; j < 8; j += 2) { 3837 int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j); 3838 if (cap->speakers[chan_idx] == mask) { 3839 /* channel is in a supported position */ 3840 ok = true; 3841 3842 if (i % 2 == 0 && i + 1 < chs) { 3843 /* even channel, check the odd companion */ 3844 int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1); 3845 int comp_mask_req = snd_hdac_chmap_to_spk_mask(map[i+1]); 3846 int comp_mask_act = cap->speakers[comp_chan_idx]; 3847 3848 if (comp_mask_req == comp_mask_act) 3849 companion_ok = true; 3850 else 3851 return -EINVAL; 3852 } 3853 break; 3854 } 3855 } 3856 3857 if (!ok) 3858 return -EINVAL; 3859 3860 if (companion_ok) 3861 i++; /* companion channel already checked */ 3862 } 3863 3864 return 0; 3865 } 3866 3867 static int atihdmi_pin_set_slot_channel(struct hdac_device *hdac, 3868 hda_nid_t pin_nid, int hdmi_slot, int stream_channel) 3869 { 3870 struct hda_codec *codec = container_of(hdac, struct hda_codec, core); 3871 int verb; 3872 int ati_channel_setup = 0; 3873 3874 if (hdmi_slot > 7) 3875 return -EINVAL; 3876 3877 if (!has_amd_full_remap_support(codec)) { 3878 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot); 3879 3880 /* In case this is an odd slot but without stream channel, do not 3881 * disable the slot since the corresponding even slot could have a 3882 * channel. In case neither have a channel, the slot pair will be 3883 * disabled when this function is called for the even slot. */ 3884 if (hdmi_slot % 2 != 0 && stream_channel == 0xf) 3885 return 0; 3886 3887 hdmi_slot -= hdmi_slot % 2; 3888 3889 if (stream_channel != 0xf) 3890 stream_channel -= stream_channel % 2; 3891 } 3892 3893 verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e; 3894 3895 /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */ 3896 3897 if (stream_channel != 0xf) 3898 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE; 3899 3900 return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup); 3901 } 3902 3903 static int atihdmi_pin_get_slot_channel(struct hdac_device *hdac, 3904 hda_nid_t pin_nid, int asp_slot) 3905 { 3906 struct hda_codec *codec = container_of(hdac, struct hda_codec, core); 3907 bool was_odd = false; 3908 int ati_asp_slot = asp_slot; 3909 int verb; 3910 int ati_channel_setup; 3911 3912 if (asp_slot > 7) 3913 return -EINVAL; 3914 3915 if (!has_amd_full_remap_support(codec)) { 3916 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot); 3917 if (ati_asp_slot % 2 != 0) { 3918 ati_asp_slot -= 1; 3919 was_odd = true; 3920 } 3921 } 3922 3923 verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e; 3924 3925 ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0); 3926 3927 if (!(ati_channel_setup & ATI_OUT_ENABLE)) 3928 return 0xf; 3929 3930 return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd; 3931 } 3932 3933 static int atihdmi_paired_chmap_cea_alloc_validate_get_type( 3934 struct hdac_chmap *chmap, 3935 struct hdac_cea_channel_speaker_allocation *cap, 3936 int channels) 3937 { 3938 int c; 3939 3940 /* 3941 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so 3942 * we need to take that into account (a single channel may take 2 3943 * channel slots if we need to carry a silent channel next to it). 3944 * On Rev3+ AMD codecs this function is not used. 3945 */ 3946 int chanpairs = 0; 3947 3948 /* We only produce even-numbered channel count TLVs */ 3949 if ((channels % 2) != 0) 3950 return -1; 3951 3952 for (c = 0; c < 7; c += 2) { 3953 if (cap->speakers[c] || cap->speakers[c+1]) 3954 chanpairs++; 3955 } 3956 3957 if (chanpairs * 2 != channels) 3958 return -1; 3959 3960 return SNDRV_CTL_TLVT_CHMAP_PAIRED; 3961 } 3962 3963 static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct hdac_chmap *hchmap, 3964 struct hdac_cea_channel_speaker_allocation *cap, 3965 unsigned int *chmap, int channels) 3966 { 3967 /* produce paired maps for pre-rev3 ATI/AMD codecs */ 3968 int count = 0; 3969 int c; 3970 3971 for (c = 7; c >= 0; c--) { 3972 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c); 3973 int spk = cap->speakers[chan]; 3974 if (!spk) { 3975 /* add N/A channel if the companion channel is occupied */ 3976 if (cap->speakers[chan + (chan % 2 ? -1 : 1)]) 3977 chmap[count++] = SNDRV_CHMAP_NA; 3978 3979 continue; 3980 } 3981 3982 chmap[count++] = snd_hdac_spk_to_chmap(spk); 3983 } 3984 3985 WARN_ON(count != channels); 3986 } 3987 3988 static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid, 3989 int dev_id, bool hbr) 3990 { 3991 int hbr_ctl, hbr_ctl_new; 3992 3993 WARN_ON(dev_id != 0); 3994 3995 hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0); 3996 if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) { 3997 if (hbr) 3998 hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE; 3999 else 4000 hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE; 4001 4002 codec_dbg(codec, 4003 "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n", 4004 pin_nid, 4005 hbr_ctl == hbr_ctl_new ? "" : "new-", 4006 hbr_ctl_new); 4007 4008 if (hbr_ctl != hbr_ctl_new) 4009 snd_hda_codec_write(codec, pin_nid, 0, 4010 ATI_VERB_SET_HBR_CONTROL, 4011 hbr_ctl_new); 4012 4013 } else if (hbr) 4014 return -EINVAL; 4015 4016 return 0; 4017 } 4018 4019 static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, 4020 hda_nid_t pin_nid, int dev_id, 4021 u32 stream_tag, int format) 4022 { 4023 if (is_amdhdmi_rev3_or_later(codec)) { 4024 int ramp_rate = 180; /* default as per AMD spec */ 4025 /* disable ramp-up/down for non-pcm as per AMD spec */ 4026 if (format & AC_FMT_TYPE_NON_PCM) 4027 ramp_rate = 0; 4028 4029 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate); 4030 } 4031 4032 return hdmi_setup_stream(codec, cvt_nid, pin_nid, dev_id, 4033 stream_tag, format); 4034 } 4035 4036 4037 static int atihdmi_init(struct hda_codec *codec) 4038 { 4039 struct hdmi_spec *spec = codec->spec; 4040 int pin_idx, err; 4041 4042 err = generic_hdmi_init(codec); 4043 4044 if (err) 4045 return err; 4046 4047 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 4048 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 4049 4050 /* make sure downmix information in infoframe is zero */ 4051 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0); 4052 4053 /* enable channel-wise remap mode if supported */ 4054 if (has_amd_full_remap_support(codec)) 4055 snd_hda_codec_write(codec, per_pin->pin_nid, 0, 4056 ATI_VERB_SET_MULTICHANNEL_MODE, 4057 ATI_MULTICHANNEL_MODE_SINGLE); 4058 } 4059 codec->auto_runtime_pm = 1; 4060 4061 return 0; 4062 } 4063 4064 /* map from pin NID to port; port is 0-based */ 4065 /* for AMD: assume widget NID starting from 3, with step 2 (3, 5, 7, ...) */ 4066 static int atihdmi_pin2port(void *audio_ptr, int pin_nid) 4067 { 4068 return pin_nid / 2 - 1; 4069 } 4070 4071 /* reverse-map from port to pin NID: see above */ 4072 static int atihdmi_port2pin(struct hda_codec *codec, int port) 4073 { 4074 return port * 2 + 3; 4075 } 4076 4077 static const struct drm_audio_component_audio_ops atihdmi_audio_ops = { 4078 .pin2port = atihdmi_pin2port, 4079 .pin_eld_notify = generic_acomp_pin_eld_notify, 4080 .master_bind = generic_acomp_master_bind, 4081 .master_unbind = generic_acomp_master_unbind, 4082 }; 4083 4084 static int patch_atihdmi(struct hda_codec *codec) 4085 { 4086 struct hdmi_spec *spec; 4087 struct hdmi_spec_per_cvt *per_cvt; 4088 int err, cvt_idx; 4089 4090 err = patch_generic_hdmi(codec); 4091 4092 if (err) 4093 return err; 4094 4095 codec->patch_ops.init = atihdmi_init; 4096 4097 spec = codec->spec; 4098 4099 spec->ops.pin_get_eld = atihdmi_pin_get_eld; 4100 spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe; 4101 spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup; 4102 spec->ops.setup_stream = atihdmi_setup_stream; 4103 4104 spec->chmap.ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel; 4105 spec->chmap.ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel; 4106 4107 if (!has_amd_full_remap_support(codec)) { 4108 /* override to ATI/AMD-specific versions with pairwise mapping */ 4109 spec->chmap.ops.chmap_cea_alloc_validate_get_type = 4110 atihdmi_paired_chmap_cea_alloc_validate_get_type; 4111 spec->chmap.ops.cea_alloc_to_tlv_chmap = 4112 atihdmi_paired_cea_alloc_to_tlv_chmap; 4113 spec->chmap.ops.chmap_validate = atihdmi_paired_chmap_validate; 4114 } 4115 4116 /* ATI/AMD converters do not advertise all of their capabilities */ 4117 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { 4118 per_cvt = get_cvt(spec, cvt_idx); 4119 per_cvt->channels_max = max(per_cvt->channels_max, 8u); 4120 per_cvt->rates |= SUPPORTED_RATES; 4121 per_cvt->formats |= SUPPORTED_FORMATS; 4122 per_cvt->maxbps = max(per_cvt->maxbps, 24u); 4123 } 4124 4125 spec->chmap.channels_max = max(spec->chmap.channels_max, 8u); 4126 4127 /* AMD GPUs have neither EPSS nor CLKSTOP bits, hence preventing 4128 * the link-down as is. Tell the core to allow it. 4129 */ 4130 codec->link_down_at_suspend = 1; 4131 4132 generic_acomp_init(codec, &atihdmi_audio_ops, atihdmi_port2pin); 4133 4134 return 0; 4135 } 4136 4137 /* VIA HDMI Implementation */ 4138 #define VIAHDMI_CVT_NID 0x02 /* audio converter1 */ 4139 #define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */ 4140 4141 static int patch_via_hdmi(struct hda_codec *codec) 4142 { 4143 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID); 4144 } 4145 4146 /* 4147 * patch entries 4148 */ 4149 static const struct hda_device_id snd_hda_id_hdmi[] = { 4150 HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI", patch_atihdmi), 4151 HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI", patch_atihdmi), 4152 HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI", patch_atihdmi), 4153 HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI", patch_atihdmi), 4154 HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI", patch_generic_hdmi), 4155 HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI", patch_generic_hdmi), 4156 HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI", patch_generic_hdmi), 4157 HDA_CODEC_ENTRY(0x10de0001, "MCP73 HDMI", patch_nvhdmi_2ch), 4158 HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 4159 HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 4160 HDA_CODEC_ENTRY(0x10de0004, "GPU 04 HDMI", patch_nvhdmi_8ch_7x), 4161 HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 4162 HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 4163 HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI", patch_nvhdmi_8ch_7x), 4164 HDA_CODEC_ENTRY(0x10de0008, "GPU 08 HDMI/DP", patch_nvhdmi_legacy), 4165 HDA_CODEC_ENTRY(0x10de0009, "GPU 09 HDMI/DP", patch_nvhdmi_legacy), 4166 HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP", patch_nvhdmi_legacy), 4167 HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP", patch_nvhdmi_legacy), 4168 HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI", patch_nvhdmi_legacy), 4169 HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP", patch_nvhdmi_legacy), 4170 HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP", patch_nvhdmi_legacy), 4171 HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP", patch_nvhdmi_legacy), 4172 HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP", patch_nvhdmi_legacy), 4173 HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP", patch_nvhdmi_legacy), 4174 HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP", patch_nvhdmi_legacy), 4175 HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP", patch_nvhdmi_legacy), 4176 HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP", patch_nvhdmi_legacy), 4177 /* 17 is known to be absent */ 4178 HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP", patch_nvhdmi_legacy), 4179 HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP", patch_nvhdmi_legacy), 4180 HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP", patch_nvhdmi_legacy), 4181 HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP", patch_nvhdmi_legacy), 4182 HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP", patch_nvhdmi_legacy), 4183 HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI", patch_tegra_hdmi), 4184 HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI", patch_tegra_hdmi), 4185 HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI", patch_tegra_hdmi), 4186 HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi), 4187 HDA_CODEC_ENTRY(0x10de002d, "Tegra186 HDMI/DP0", patch_tegra_hdmi), 4188 HDA_CODEC_ENTRY(0x10de002e, "Tegra186 HDMI/DP1", patch_tegra_hdmi), 4189 HDA_CODEC_ENTRY(0x10de002f, "Tegra194 HDMI/DP2", patch_tegra_hdmi), 4190 HDA_CODEC_ENTRY(0x10de0030, "Tegra194 HDMI/DP3", patch_tegra_hdmi), 4191 HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP", patch_nvhdmi), 4192 HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP", patch_nvhdmi), 4193 HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi), 4194 HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP", patch_nvhdmi), 4195 HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP", patch_nvhdmi), 4196 HDA_CODEC_ENTRY(0x10de0045, "GPU 45 HDMI/DP", patch_nvhdmi), 4197 HDA_CODEC_ENTRY(0x10de0050, "GPU 50 HDMI/DP", patch_nvhdmi), 4198 HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP", patch_nvhdmi), 4199 HDA_CODEC_ENTRY(0x10de0052, "GPU 52 HDMI/DP", patch_nvhdmi), 4200 HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP", patch_nvhdmi), 4201 HDA_CODEC_ENTRY(0x10de0061, "GPU 61 HDMI/DP", patch_nvhdmi), 4202 HDA_CODEC_ENTRY(0x10de0062, "GPU 62 HDMI/DP", patch_nvhdmi), 4203 HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI", patch_nvhdmi_2ch), 4204 HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP", patch_nvhdmi), 4205 HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP", patch_nvhdmi), 4206 HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP", patch_nvhdmi), 4207 HDA_CODEC_ENTRY(0x10de0073, "GPU 73 HDMI/DP", patch_nvhdmi), 4208 HDA_CODEC_ENTRY(0x10de0074, "GPU 74 HDMI/DP", patch_nvhdmi), 4209 HDA_CODEC_ENTRY(0x10de0076, "GPU 76 HDMI/DP", patch_nvhdmi), 4210 HDA_CODEC_ENTRY(0x10de007b, "GPU 7b HDMI/DP", patch_nvhdmi), 4211 HDA_CODEC_ENTRY(0x10de007c, "GPU 7c HDMI/DP", patch_nvhdmi), 4212 HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP", patch_nvhdmi), 4213 HDA_CODEC_ENTRY(0x10de007e, "GPU 7e HDMI/DP", patch_nvhdmi), 4214 HDA_CODEC_ENTRY(0x10de0080, "GPU 80 HDMI/DP", patch_nvhdmi), 4215 HDA_CODEC_ENTRY(0x10de0081, "GPU 81 HDMI/DP", patch_nvhdmi), 4216 HDA_CODEC_ENTRY(0x10de0082, "GPU 82 HDMI/DP", patch_nvhdmi), 4217 HDA_CODEC_ENTRY(0x10de0083, "GPU 83 HDMI/DP", patch_nvhdmi), 4218 HDA_CODEC_ENTRY(0x10de0084, "GPU 84 HDMI/DP", patch_nvhdmi), 4219 HDA_CODEC_ENTRY(0x10de0090, "GPU 90 HDMI/DP", patch_nvhdmi), 4220 HDA_CODEC_ENTRY(0x10de0091, "GPU 91 HDMI/DP", patch_nvhdmi), 4221 HDA_CODEC_ENTRY(0x10de0092, "GPU 92 HDMI/DP", patch_nvhdmi), 4222 HDA_CODEC_ENTRY(0x10de0093, "GPU 93 HDMI/DP", patch_nvhdmi), 4223 HDA_CODEC_ENTRY(0x10de0094, "GPU 94 HDMI/DP", patch_nvhdmi), 4224 HDA_CODEC_ENTRY(0x10de0095, "GPU 95 HDMI/DP", patch_nvhdmi), 4225 HDA_CODEC_ENTRY(0x10de0097, "GPU 97 HDMI/DP", patch_nvhdmi), 4226 HDA_CODEC_ENTRY(0x10de0098, "GPU 98 HDMI/DP", patch_nvhdmi), 4227 HDA_CODEC_ENTRY(0x10de0099, "GPU 99 HDMI/DP", patch_nvhdmi), 4228 HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI", patch_nvhdmi_2ch), 4229 HDA_CODEC_ENTRY(0x10de8067, "MCP67/68 HDMI", patch_nvhdmi_2ch), 4230 HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP", patch_via_hdmi), 4231 HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP", patch_via_hdmi), 4232 HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP", patch_generic_hdmi), 4233 HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP", patch_generic_hdmi), 4234 HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI", patch_i915_cpt_hdmi), 4235 HDA_CODEC_ENTRY(0x80862800, "Geminilake HDMI", patch_i915_glk_hdmi), 4236 HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI", patch_generic_hdmi), 4237 HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI", patch_generic_hdmi), 4238 HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI", patch_generic_hdmi), 4239 HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI", patch_i915_cpt_hdmi), 4240 HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_i915_cpt_hdmi), 4241 HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_i915_cpt_hdmi), 4242 HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI", patch_i915_hsw_hdmi), 4243 HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI", patch_i915_hsw_hdmi), 4244 HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI", patch_i915_hsw_hdmi), 4245 HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI", patch_i915_hsw_hdmi), 4246 HDA_CODEC_ENTRY(0x8086280b, "Kabylake HDMI", patch_i915_hsw_hdmi), 4247 HDA_CODEC_ENTRY(0x8086280c, "Cannonlake HDMI", patch_i915_glk_hdmi), 4248 HDA_CODEC_ENTRY(0x8086280d, "Geminilake HDMI", patch_i915_glk_hdmi), 4249 HDA_CODEC_ENTRY(0x8086280f, "Icelake HDMI", patch_i915_icl_hdmi), 4250 HDA_CODEC_ENTRY(0x80862812, "Tigerlake HDMI", patch_i915_tgl_hdmi), 4251 HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI", patch_generic_hdmi), 4252 HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_i915_byt_hdmi), 4253 HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI", patch_i915_byt_hdmi), 4254 HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI", patch_generic_hdmi), 4255 /* special ID for generic HDMI */ 4256 HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi), 4257 {} /* terminator */ 4258 }; 4259 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi); 4260 4261 MODULE_LICENSE("GPL"); 4262 MODULE_DESCRIPTION("HDMI HD-audio codec"); 4263 MODULE_ALIAS("snd-hda-codec-intelhdmi"); 4264 MODULE_ALIAS("snd-hda-codec-nvhdmi"); 4265 MODULE_ALIAS("snd-hda-codec-atihdmi"); 4266 4267 static struct hda_codec_driver hdmi_driver = { 4268 .id = snd_hda_id_hdmi, 4269 }; 4270 4271 module_hda_codec_driver(hdmi_driver); 4272