1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * 4 * patch_hdmi.c - routines for HDMI/DisplayPort codecs 5 * 6 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved. 7 * Copyright (c) 2006 ATI Technologies Inc. 8 * Copyright (c) 2008 NVIDIA Corp. All rights reserved. 9 * Copyright (c) 2008 Wei Ni <wni@nvidia.com> 10 * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi> 11 * 12 * Authors: 13 * Wu Fengguang <wfg@linux.intel.com> 14 * 15 * Maintained by: 16 * Wu Fengguang <wfg@linux.intel.com> 17 */ 18 19 #include <linux/init.h> 20 #include <linux/delay.h> 21 #include <linux/pci.h> 22 #include <linux/slab.h> 23 #include <linux/module.h> 24 #include <linux/pm_runtime.h> 25 #include <sound/core.h> 26 #include <sound/jack.h> 27 #include <sound/asoundef.h> 28 #include <sound/tlv.h> 29 #include <sound/hdaudio.h> 30 #include <sound/hda_i915.h> 31 #include <sound/hda_chmap.h> 32 #include <sound/hda_codec.h> 33 #include "hda_local.h" 34 #include "hda_jack.h" 35 #include "hda_controller.h" 36 37 static bool static_hdmi_pcm; 38 module_param(static_hdmi_pcm, bool, 0644); 39 MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info"); 40 41 static bool enable_acomp = true; 42 module_param(enable_acomp, bool, 0444); 43 MODULE_PARM_DESC(enable_acomp, "Enable audio component binding (default=yes)"); 44 45 static bool enable_silent_stream = 46 IS_ENABLED(CONFIG_SND_HDA_INTEL_HDMI_SILENT_STREAM); 47 module_param(enable_silent_stream, bool, 0644); 48 MODULE_PARM_DESC(enable_silent_stream, "Enable Silent Stream for HDMI devices"); 49 50 static bool enable_all_pins; 51 module_param(enable_all_pins, bool, 0444); 52 MODULE_PARM_DESC(enable_all_pins, "Forcibly enable all pins"); 53 54 struct hdmi_spec_per_cvt { 55 hda_nid_t cvt_nid; 56 int assigned; 57 unsigned int channels_min; 58 unsigned int channels_max; 59 u32 rates; 60 u64 formats; 61 unsigned int maxbps; 62 }; 63 64 /* max. connections to a widget */ 65 #define HDA_MAX_CONNECTIONS 32 66 67 struct hdmi_spec_per_pin { 68 hda_nid_t pin_nid; 69 int dev_id; 70 /* pin idx, different device entries on the same pin use the same idx */ 71 int pin_nid_idx; 72 int num_mux_nids; 73 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS]; 74 int mux_idx; 75 hda_nid_t cvt_nid; 76 77 struct hda_codec *codec; 78 struct hdmi_eld sink_eld; 79 struct mutex lock; 80 struct delayed_work work; 81 struct hdmi_pcm *pcm; /* pointer to spec->pcm_rec[n] dynamically*/ 82 int pcm_idx; /* which pcm is attached. -1 means no pcm is attached */ 83 int repoll_count; 84 bool setup; /* the stream has been set up by prepare callback */ 85 bool silent_stream; 86 int channels; /* current number of channels */ 87 bool non_pcm; 88 bool chmap_set; /* channel-map override by ALSA API? */ 89 unsigned char chmap[8]; /* ALSA API channel-map */ 90 #ifdef CONFIG_SND_PROC_FS 91 struct snd_info_entry *proc_entry; 92 #endif 93 }; 94 95 /* operations used by generic code that can be overridden by patches */ 96 struct hdmi_ops { 97 int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid, 98 int dev_id, unsigned char *buf, int *eld_size); 99 100 void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid, 101 int dev_id, 102 int ca, int active_channels, int conn_type); 103 104 /* enable/disable HBR (HD passthrough) */ 105 int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, 106 int dev_id, bool hbr); 107 108 int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid, 109 hda_nid_t pin_nid, int dev_id, u32 stream_tag, 110 int format); 111 112 void (*pin_cvt_fixup)(struct hda_codec *codec, 113 struct hdmi_spec_per_pin *per_pin, 114 hda_nid_t cvt_nid); 115 }; 116 117 struct hdmi_pcm { 118 struct hda_pcm *pcm; 119 struct snd_jack *jack; 120 struct snd_kcontrol *eld_ctl; 121 }; 122 123 enum { 124 SILENT_STREAM_OFF = 0, 125 SILENT_STREAM_KAE, /* use standard HDA Keep-Alive */ 126 SILENT_STREAM_I915, /* Intel i915 extension */ 127 }; 128 129 struct hdmi_spec { 130 struct hda_codec *codec; 131 int num_cvts; 132 struct snd_array cvts; /* struct hdmi_spec_per_cvt */ 133 hda_nid_t cvt_nids[4]; /* only for haswell fix */ 134 135 /* 136 * num_pins is the number of virtual pins 137 * for example, there are 3 pins, and each pin 138 * has 4 device entries, then the num_pins is 12 139 */ 140 int num_pins; 141 /* 142 * num_nids is the number of real pins 143 * In the above example, num_nids is 3 144 */ 145 int num_nids; 146 /* 147 * dev_num is the number of device entries 148 * on each pin. 149 * In the above example, dev_num is 4 150 */ 151 int dev_num; 152 struct snd_array pins; /* struct hdmi_spec_per_pin */ 153 struct hdmi_pcm pcm_rec[16]; 154 struct mutex pcm_lock; 155 struct mutex bind_lock; /* for audio component binding */ 156 /* pcm_bitmap means which pcms have been assigned to pins*/ 157 unsigned long pcm_bitmap; 158 int pcm_used; /* counter of pcm_rec[] */ 159 /* bitmap shows whether the pcm is opened in user space 160 * bit 0 means the first playback PCM (PCM3); 161 * bit 1 means the second playback PCM, and so on. 162 */ 163 unsigned long pcm_in_use; 164 165 struct hdmi_eld temp_eld; 166 struct hdmi_ops ops; 167 168 bool dyn_pin_out; 169 bool dyn_pcm_assign; 170 bool dyn_pcm_no_legacy; 171 /* hdmi interrupt trigger control flag for Nvidia codec */ 172 bool hdmi_intr_trig_ctrl; 173 bool nv_dp_workaround; /* workaround DP audio infoframe for Nvidia */ 174 175 bool intel_hsw_fixup; /* apply Intel platform-specific fixups */ 176 /* 177 * Non-generic VIA/NVIDIA specific 178 */ 179 struct hda_multi_out multiout; 180 struct hda_pcm_stream pcm_playback; 181 182 bool use_acomp_notifier; /* use eld_notify callback for hotplug */ 183 bool acomp_registered; /* audio component registered in this driver */ 184 bool force_connect; /* force connectivity */ 185 struct drm_audio_component_audio_ops drm_audio_ops; 186 int (*port2pin)(struct hda_codec *, int); /* reverse port/pin mapping */ 187 188 struct hdac_chmap chmap; 189 hda_nid_t vendor_nid; 190 const int *port_map; 191 int port_num; 192 int silent_stream_type; 193 }; 194 195 #ifdef CONFIG_SND_HDA_COMPONENT 196 static inline bool codec_has_acomp(struct hda_codec *codec) 197 { 198 struct hdmi_spec *spec = codec->spec; 199 return spec->use_acomp_notifier; 200 } 201 #else 202 #define codec_has_acomp(codec) false 203 #endif 204 205 struct hdmi_audio_infoframe { 206 u8 type; /* 0x84 */ 207 u8 ver; /* 0x01 */ 208 u8 len; /* 0x0a */ 209 210 u8 checksum; 211 212 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */ 213 u8 SS01_SF24; 214 u8 CXT04; 215 u8 CA; 216 u8 LFEPBL01_LSV36_DM_INH7; 217 }; 218 219 struct dp_audio_infoframe { 220 u8 type; /* 0x84 */ 221 u8 len; /* 0x1b */ 222 u8 ver; /* 0x11 << 2 */ 223 224 u8 CC02_CT47; /* match with HDMI infoframe from this on */ 225 u8 SS01_SF24; 226 u8 CXT04; 227 u8 CA; 228 u8 LFEPBL01_LSV36_DM_INH7; 229 }; 230 231 union audio_infoframe { 232 struct hdmi_audio_infoframe hdmi; 233 struct dp_audio_infoframe dp; 234 u8 bytes[0]; 235 }; 236 237 /* 238 * HDMI routines 239 */ 240 241 #define get_pin(spec, idx) \ 242 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx)) 243 #define get_cvt(spec, idx) \ 244 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx)) 245 /* obtain hdmi_pcm object assigned to idx */ 246 #define get_hdmi_pcm(spec, idx) (&(spec)->pcm_rec[idx]) 247 /* obtain hda_pcm object assigned to idx */ 248 #define get_pcm_rec(spec, idx) (get_hdmi_pcm(spec, idx)->pcm) 249 250 static int pin_id_to_pin_index(struct hda_codec *codec, 251 hda_nid_t pin_nid, int dev_id) 252 { 253 struct hdmi_spec *spec = codec->spec; 254 int pin_idx; 255 struct hdmi_spec_per_pin *per_pin; 256 257 /* 258 * (dev_id == -1) means it is NON-MST pin 259 * return the first virtual pin on this port 260 */ 261 if (dev_id == -1) 262 dev_id = 0; 263 264 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 265 per_pin = get_pin(spec, pin_idx); 266 if ((per_pin->pin_nid == pin_nid) && 267 (per_pin->dev_id == dev_id)) 268 return pin_idx; 269 } 270 271 codec_warn(codec, "HDMI: pin NID 0x%x not registered\n", pin_nid); 272 return -EINVAL; 273 } 274 275 static int hinfo_to_pcm_index(struct hda_codec *codec, 276 struct hda_pcm_stream *hinfo) 277 { 278 struct hdmi_spec *spec = codec->spec; 279 int pcm_idx; 280 281 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) 282 if (get_pcm_rec(spec, pcm_idx)->stream == hinfo) 283 return pcm_idx; 284 285 codec_warn(codec, "HDMI: hinfo %p not tied to a PCM\n", hinfo); 286 return -EINVAL; 287 } 288 289 static int hinfo_to_pin_index(struct hda_codec *codec, 290 struct hda_pcm_stream *hinfo) 291 { 292 struct hdmi_spec *spec = codec->spec; 293 struct hdmi_spec_per_pin *per_pin; 294 int pin_idx; 295 296 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 297 per_pin = get_pin(spec, pin_idx); 298 if (per_pin->pcm && 299 per_pin->pcm->pcm->stream == hinfo) 300 return pin_idx; 301 } 302 303 codec_dbg(codec, "HDMI: hinfo %p (pcm %d) not registered\n", hinfo, 304 hinfo_to_pcm_index(codec, hinfo)); 305 return -EINVAL; 306 } 307 308 static struct hdmi_spec_per_pin *pcm_idx_to_pin(struct hdmi_spec *spec, 309 int pcm_idx) 310 { 311 int i; 312 struct hdmi_spec_per_pin *per_pin; 313 314 for (i = 0; i < spec->num_pins; i++) { 315 per_pin = get_pin(spec, i); 316 if (per_pin->pcm_idx == pcm_idx) 317 return per_pin; 318 } 319 return NULL; 320 } 321 322 static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid) 323 { 324 struct hdmi_spec *spec = codec->spec; 325 int cvt_idx; 326 327 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) 328 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid) 329 return cvt_idx; 330 331 codec_warn(codec, "HDMI: cvt NID 0x%x not registered\n", cvt_nid); 332 return -EINVAL; 333 } 334 335 static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol, 336 struct snd_ctl_elem_info *uinfo) 337 { 338 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 339 struct hdmi_spec *spec = codec->spec; 340 struct hdmi_spec_per_pin *per_pin; 341 struct hdmi_eld *eld; 342 int pcm_idx; 343 344 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; 345 346 pcm_idx = kcontrol->private_value; 347 mutex_lock(&spec->pcm_lock); 348 per_pin = pcm_idx_to_pin(spec, pcm_idx); 349 if (!per_pin) { 350 /* no pin is bound to the pcm */ 351 uinfo->count = 0; 352 goto unlock; 353 } 354 eld = &per_pin->sink_eld; 355 uinfo->count = eld->eld_valid ? eld->eld_size : 0; 356 357 unlock: 358 mutex_unlock(&spec->pcm_lock); 359 return 0; 360 } 361 362 static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol, 363 struct snd_ctl_elem_value *ucontrol) 364 { 365 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 366 struct hdmi_spec *spec = codec->spec; 367 struct hdmi_spec_per_pin *per_pin; 368 struct hdmi_eld *eld; 369 int pcm_idx; 370 int err = 0; 371 372 pcm_idx = kcontrol->private_value; 373 mutex_lock(&spec->pcm_lock); 374 per_pin = pcm_idx_to_pin(spec, pcm_idx); 375 if (!per_pin) { 376 /* no pin is bound to the pcm */ 377 memset(ucontrol->value.bytes.data, 0, 378 ARRAY_SIZE(ucontrol->value.bytes.data)); 379 goto unlock; 380 } 381 382 eld = &per_pin->sink_eld; 383 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data) || 384 eld->eld_size > ELD_MAX_SIZE) { 385 snd_BUG(); 386 err = -EINVAL; 387 goto unlock; 388 } 389 390 memset(ucontrol->value.bytes.data, 0, 391 ARRAY_SIZE(ucontrol->value.bytes.data)); 392 if (eld->eld_valid) 393 memcpy(ucontrol->value.bytes.data, eld->eld_buffer, 394 eld->eld_size); 395 396 unlock: 397 mutex_unlock(&spec->pcm_lock); 398 return err; 399 } 400 401 static const struct snd_kcontrol_new eld_bytes_ctl = { 402 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE | 403 SNDRV_CTL_ELEM_ACCESS_SKIP_CHECK, 404 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 405 .name = "ELD", 406 .info = hdmi_eld_ctl_info, 407 .get = hdmi_eld_ctl_get, 408 }; 409 410 static int hdmi_create_eld_ctl(struct hda_codec *codec, int pcm_idx, 411 int device) 412 { 413 struct snd_kcontrol *kctl; 414 struct hdmi_spec *spec = codec->spec; 415 int err; 416 417 kctl = snd_ctl_new1(&eld_bytes_ctl, codec); 418 if (!kctl) 419 return -ENOMEM; 420 kctl->private_value = pcm_idx; 421 kctl->id.device = device; 422 423 /* no pin nid is associated with the kctl now 424 * tbd: associate pin nid to eld ctl later 425 */ 426 err = snd_hda_ctl_add(codec, 0, kctl); 427 if (err < 0) 428 return err; 429 430 get_hdmi_pcm(spec, pcm_idx)->eld_ctl = kctl; 431 return 0; 432 } 433 434 #ifdef BE_PARANOID 435 static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid, 436 int *packet_index, int *byte_index) 437 { 438 int val; 439 440 val = snd_hda_codec_read(codec, pin_nid, 0, 441 AC_VERB_GET_HDMI_DIP_INDEX, 0); 442 443 *packet_index = val >> 5; 444 *byte_index = val & 0x1f; 445 } 446 #endif 447 448 static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid, 449 int packet_index, int byte_index) 450 { 451 int val; 452 453 val = (packet_index << 5) | (byte_index & 0x1f); 454 455 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val); 456 } 457 458 static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid, 459 unsigned char val) 460 { 461 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val); 462 } 463 464 static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid) 465 { 466 struct hdmi_spec *spec = codec->spec; 467 int pin_out; 468 469 /* Unmute */ 470 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP) 471 snd_hda_codec_write(codec, pin_nid, 0, 472 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE); 473 474 if (spec->dyn_pin_out) 475 /* Disable pin out until stream is active */ 476 pin_out = 0; 477 else 478 /* Enable pin out: some machines with GM965 gets broken output 479 * when the pin is disabled or changed while using with HDMI 480 */ 481 pin_out = PIN_OUT; 482 483 snd_hda_codec_write(codec, pin_nid, 0, 484 AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out); 485 } 486 487 /* 488 * ELD proc files 489 */ 490 491 #ifdef CONFIG_SND_PROC_FS 492 static void print_eld_info(struct snd_info_entry *entry, 493 struct snd_info_buffer *buffer) 494 { 495 struct hdmi_spec_per_pin *per_pin = entry->private_data; 496 497 mutex_lock(&per_pin->lock); 498 snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer); 499 mutex_unlock(&per_pin->lock); 500 } 501 502 static void write_eld_info(struct snd_info_entry *entry, 503 struct snd_info_buffer *buffer) 504 { 505 struct hdmi_spec_per_pin *per_pin = entry->private_data; 506 507 mutex_lock(&per_pin->lock); 508 snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer); 509 mutex_unlock(&per_pin->lock); 510 } 511 512 static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index) 513 { 514 char name[32]; 515 struct hda_codec *codec = per_pin->codec; 516 struct snd_info_entry *entry; 517 int err; 518 519 snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index); 520 err = snd_card_proc_new(codec->card, name, &entry); 521 if (err < 0) 522 return err; 523 524 snd_info_set_text_ops(entry, per_pin, print_eld_info); 525 entry->c.text.write = write_eld_info; 526 entry->mode |= 0200; 527 per_pin->proc_entry = entry; 528 529 return 0; 530 } 531 532 static void eld_proc_free(struct hdmi_spec_per_pin *per_pin) 533 { 534 if (!per_pin->codec->bus->shutdown) { 535 snd_info_free_entry(per_pin->proc_entry); 536 per_pin->proc_entry = NULL; 537 } 538 } 539 #else 540 static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin, 541 int index) 542 { 543 return 0; 544 } 545 static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin) 546 { 547 } 548 #endif 549 550 /* 551 * Audio InfoFrame routines 552 */ 553 554 /* 555 * Enable Audio InfoFrame Transmission 556 */ 557 static void hdmi_start_infoframe_trans(struct hda_codec *codec, 558 hda_nid_t pin_nid) 559 { 560 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 561 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT, 562 AC_DIPXMIT_BEST); 563 } 564 565 /* 566 * Disable Audio InfoFrame Transmission 567 */ 568 static void hdmi_stop_infoframe_trans(struct hda_codec *codec, 569 hda_nid_t pin_nid) 570 { 571 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 572 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT, 573 AC_DIPXMIT_DISABLE); 574 } 575 576 static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid) 577 { 578 #ifdef CONFIG_SND_DEBUG_VERBOSE 579 int i; 580 int size; 581 582 size = snd_hdmi_get_eld_size(codec, pin_nid); 583 codec_dbg(codec, "HDMI: ELD buf size is %d\n", size); 584 585 for (i = 0; i < 8; i++) { 586 size = snd_hda_codec_read(codec, pin_nid, 0, 587 AC_VERB_GET_HDMI_DIP_SIZE, i); 588 codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size); 589 } 590 #endif 591 } 592 593 static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid) 594 { 595 #ifdef BE_PARANOID 596 int i, j; 597 int size; 598 int pi, bi; 599 for (i = 0; i < 8; i++) { 600 size = snd_hda_codec_read(codec, pin_nid, 0, 601 AC_VERB_GET_HDMI_DIP_SIZE, i); 602 if (size == 0) 603 continue; 604 605 hdmi_set_dip_index(codec, pin_nid, i, 0x0); 606 for (j = 1; j < 1000; j++) { 607 hdmi_write_dip_byte(codec, pin_nid, 0x0); 608 hdmi_get_dip_index(codec, pin_nid, &pi, &bi); 609 if (pi != i) 610 codec_dbg(codec, "dip index %d: %d != %d\n", 611 bi, pi, i); 612 if (bi == 0) /* byte index wrapped around */ 613 break; 614 } 615 codec_dbg(codec, 616 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n", 617 i, size, j); 618 } 619 #endif 620 } 621 622 static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai) 623 { 624 u8 *bytes = (u8 *)hdmi_ai; 625 u8 sum = 0; 626 int i; 627 628 hdmi_ai->checksum = 0; 629 630 for (i = 0; i < sizeof(*hdmi_ai); i++) 631 sum += bytes[i]; 632 633 hdmi_ai->checksum = -sum; 634 } 635 636 static void hdmi_fill_audio_infoframe(struct hda_codec *codec, 637 hda_nid_t pin_nid, 638 u8 *dip, int size) 639 { 640 int i; 641 642 hdmi_debug_dip_size(codec, pin_nid); 643 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */ 644 645 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 646 for (i = 0; i < size; i++) 647 hdmi_write_dip_byte(codec, pin_nid, dip[i]); 648 } 649 650 static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid, 651 u8 *dip, int size) 652 { 653 u8 val; 654 int i; 655 656 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 657 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0) 658 != AC_DIPXMIT_BEST) 659 return false; 660 661 for (i = 0; i < size; i++) { 662 val = snd_hda_codec_read(codec, pin_nid, 0, 663 AC_VERB_GET_HDMI_DIP_DATA, 0); 664 if (val != dip[i]) 665 return false; 666 } 667 668 return true; 669 } 670 671 static int hdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid, 672 int dev_id, unsigned char *buf, int *eld_size) 673 { 674 snd_hda_set_dev_select(codec, nid, dev_id); 675 676 return snd_hdmi_get_eld(codec, nid, buf, eld_size); 677 } 678 679 static void hdmi_pin_setup_infoframe(struct hda_codec *codec, 680 hda_nid_t pin_nid, int dev_id, 681 int ca, int active_channels, 682 int conn_type) 683 { 684 struct hdmi_spec *spec = codec->spec; 685 union audio_infoframe ai; 686 687 memset(&ai, 0, sizeof(ai)); 688 if ((conn_type == 0) || /* HDMI */ 689 /* Nvidia DisplayPort: Nvidia HW expects same layout as HDMI */ 690 (conn_type == 1 && spec->nv_dp_workaround)) { 691 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi; 692 693 if (conn_type == 0) { /* HDMI */ 694 hdmi_ai->type = 0x84; 695 hdmi_ai->ver = 0x01; 696 hdmi_ai->len = 0x0a; 697 } else {/* Nvidia DP */ 698 hdmi_ai->type = 0x84; 699 hdmi_ai->ver = 0x1b; 700 hdmi_ai->len = 0x11 << 2; 701 } 702 hdmi_ai->CC02_CT47 = active_channels - 1; 703 hdmi_ai->CA = ca; 704 hdmi_checksum_audio_infoframe(hdmi_ai); 705 } else if (conn_type == 1) { /* DisplayPort */ 706 struct dp_audio_infoframe *dp_ai = &ai.dp; 707 708 dp_ai->type = 0x84; 709 dp_ai->len = 0x1b; 710 dp_ai->ver = 0x11 << 2; 711 dp_ai->CC02_CT47 = active_channels - 1; 712 dp_ai->CA = ca; 713 } else { 714 codec_dbg(codec, "HDMI: unknown connection type at pin NID 0x%x\n", pin_nid); 715 return; 716 } 717 718 snd_hda_set_dev_select(codec, pin_nid, dev_id); 719 720 /* 721 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or 722 * sizeof(*dp_ai) to avoid partial match/update problems when 723 * the user switches between HDMI/DP monitors. 724 */ 725 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes, 726 sizeof(ai))) { 727 codec_dbg(codec, "%s: pin NID=0x%x channels=%d ca=0x%02x\n", 728 __func__, pin_nid, active_channels, ca); 729 hdmi_stop_infoframe_trans(codec, pin_nid); 730 hdmi_fill_audio_infoframe(codec, pin_nid, 731 ai.bytes, sizeof(ai)); 732 hdmi_start_infoframe_trans(codec, pin_nid); 733 } 734 } 735 736 static void hdmi_setup_audio_infoframe(struct hda_codec *codec, 737 struct hdmi_spec_per_pin *per_pin, 738 bool non_pcm) 739 { 740 struct hdmi_spec *spec = codec->spec; 741 struct hdac_chmap *chmap = &spec->chmap; 742 hda_nid_t pin_nid = per_pin->pin_nid; 743 int dev_id = per_pin->dev_id; 744 int channels = per_pin->channels; 745 int active_channels; 746 struct hdmi_eld *eld; 747 int ca; 748 749 if (!channels) 750 return; 751 752 snd_hda_set_dev_select(codec, pin_nid, dev_id); 753 754 /* some HW (e.g. HSW+) needs reprogramming the amp at each time */ 755 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP) 756 snd_hda_codec_write(codec, pin_nid, 0, 757 AC_VERB_SET_AMP_GAIN_MUTE, 758 AMP_OUT_UNMUTE); 759 760 eld = &per_pin->sink_eld; 761 762 ca = snd_hdac_channel_allocation(&codec->core, 763 eld->info.spk_alloc, channels, 764 per_pin->chmap_set, non_pcm, per_pin->chmap); 765 766 active_channels = snd_hdac_get_active_channels(ca); 767 768 chmap->ops.set_channel_count(&codec->core, per_pin->cvt_nid, 769 active_channels); 770 771 /* 772 * always configure channel mapping, it may have been changed by the 773 * user in the meantime 774 */ 775 snd_hdac_setup_channel_mapping(&spec->chmap, 776 pin_nid, non_pcm, ca, channels, 777 per_pin->chmap, per_pin->chmap_set); 778 779 spec->ops.pin_setup_infoframe(codec, pin_nid, dev_id, 780 ca, active_channels, eld->info.conn_type); 781 782 per_pin->non_pcm = non_pcm; 783 } 784 785 /* 786 * Unsolicited events 787 */ 788 789 static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll); 790 791 static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid, 792 int dev_id) 793 { 794 struct hdmi_spec *spec = codec->spec; 795 int pin_idx = pin_id_to_pin_index(codec, nid, dev_id); 796 797 if (pin_idx < 0) 798 return; 799 mutex_lock(&spec->pcm_lock); 800 hdmi_present_sense(get_pin(spec, pin_idx), 1); 801 mutex_unlock(&spec->pcm_lock); 802 } 803 804 static void jack_callback(struct hda_codec *codec, 805 struct hda_jack_callback *jack) 806 { 807 /* stop polling when notification is enabled */ 808 if (codec_has_acomp(codec)) 809 return; 810 811 check_presence_and_report(codec, jack->nid, jack->dev_id); 812 } 813 814 static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res, 815 struct hda_jack_tbl *jack) 816 { 817 jack->jack_dirty = 1; 818 819 codec_dbg(codec, 820 "HDMI hot plug event: Codec=%d NID=0x%x Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n", 821 codec->addr, jack->nid, jack->dev_id, !!(res & AC_UNSOL_RES_IA), 822 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV)); 823 824 check_presence_and_report(codec, jack->nid, jack->dev_id); 825 } 826 827 static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res) 828 { 829 int tag = res >> AC_UNSOL_RES_TAG_SHIFT; 830 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT; 831 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE); 832 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY); 833 834 codec_info(codec, 835 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n", 836 codec->addr, 837 tag, 838 subtag, 839 cp_state, 840 cp_ready); 841 842 /* TODO */ 843 if (cp_state) { 844 ; 845 } 846 if (cp_ready) { 847 ; 848 } 849 } 850 851 852 static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res) 853 { 854 int tag = res >> AC_UNSOL_RES_TAG_SHIFT; 855 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT; 856 struct hda_jack_tbl *jack; 857 858 if (codec_has_acomp(codec)) 859 return; 860 861 if (codec->dp_mst) { 862 int dev_entry = 863 (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT; 864 865 jack = snd_hda_jack_tbl_get_from_tag(codec, tag, dev_entry); 866 } else { 867 jack = snd_hda_jack_tbl_get_from_tag(codec, tag, 0); 868 } 869 870 if (!jack) { 871 codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag); 872 return; 873 } 874 875 if (subtag == 0) 876 hdmi_intrinsic_event(codec, res, jack); 877 else 878 hdmi_non_intrinsic_event(codec, res); 879 } 880 881 static void haswell_verify_D0(struct hda_codec *codec, 882 hda_nid_t cvt_nid, hda_nid_t nid) 883 { 884 int pwr; 885 886 /* For Haswell, the converter 1/2 may keep in D3 state after bootup, 887 * thus pins could only choose converter 0 for use. Make sure the 888 * converters are in correct power state */ 889 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0)) 890 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0); 891 892 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) { 893 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE, 894 AC_PWRST_D0); 895 msleep(40); 896 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0); 897 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT; 898 codec_dbg(codec, "Haswell HDMI audio: Power for NID 0x%x is now D%d\n", nid, pwr); 899 } 900 } 901 902 /* 903 * Callbacks 904 */ 905 906 /* HBR should be Non-PCM, 8 channels */ 907 #define is_hbr_format(format) \ 908 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7) 909 910 static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid, 911 int dev_id, bool hbr) 912 { 913 int pinctl, new_pinctl; 914 915 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) { 916 snd_hda_set_dev_select(codec, pin_nid, dev_id); 917 pinctl = snd_hda_codec_read(codec, pin_nid, 0, 918 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 919 920 if (pinctl < 0) 921 return hbr ? -EINVAL : 0; 922 923 new_pinctl = pinctl & ~AC_PINCTL_EPT; 924 if (hbr) 925 new_pinctl |= AC_PINCTL_EPT_HBR; 926 else 927 new_pinctl |= AC_PINCTL_EPT_NATIVE; 928 929 codec_dbg(codec, 930 "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n", 931 pin_nid, 932 pinctl == new_pinctl ? "" : "new-", 933 new_pinctl); 934 935 if (pinctl != new_pinctl) 936 snd_hda_codec_write(codec, pin_nid, 0, 937 AC_VERB_SET_PIN_WIDGET_CONTROL, 938 new_pinctl); 939 } else if (hbr) 940 return -EINVAL; 941 942 return 0; 943 } 944 945 static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, 946 hda_nid_t pin_nid, int dev_id, 947 u32 stream_tag, int format) 948 { 949 struct hdmi_spec *spec = codec->spec; 950 unsigned int param; 951 int err; 952 953 err = spec->ops.pin_hbr_setup(codec, pin_nid, dev_id, 954 is_hbr_format(format)); 955 956 if (err) { 957 codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n"); 958 return err; 959 } 960 961 if (spec->intel_hsw_fixup) { 962 963 /* 964 * on recent platforms IEC Coding Type is required for HBR 965 * support, read current Digital Converter settings and set 966 * ICT bitfield if needed. 967 */ 968 param = snd_hda_codec_read(codec, cvt_nid, 0, 969 AC_VERB_GET_DIGI_CONVERT_1, 0); 970 971 param = (param >> 16) & ~(AC_DIG3_ICT); 972 973 /* on recent platforms ICT mode is required for HBR support */ 974 if (is_hbr_format(format)) 975 param |= 0x1; 976 977 snd_hda_codec_write(codec, cvt_nid, 0, 978 AC_VERB_SET_DIGI_CONVERT_3, param); 979 } 980 981 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format); 982 return 0; 983 } 984 985 /* Try to find an available converter 986 * If pin_idx is less then zero, just try to find an available converter. 987 * Otherwise, try to find an available converter and get the cvt mux index 988 * of the pin. 989 */ 990 static int hdmi_choose_cvt(struct hda_codec *codec, 991 int pin_idx, int *cvt_id) 992 { 993 struct hdmi_spec *spec = codec->spec; 994 struct hdmi_spec_per_pin *per_pin; 995 struct hdmi_spec_per_cvt *per_cvt = NULL; 996 int cvt_idx, mux_idx = 0; 997 998 /* pin_idx < 0 means no pin will be bound to the converter */ 999 if (pin_idx < 0) 1000 per_pin = NULL; 1001 else 1002 per_pin = get_pin(spec, pin_idx); 1003 1004 if (per_pin && per_pin->silent_stream) { 1005 cvt_idx = cvt_nid_to_cvt_index(codec, per_pin->cvt_nid); 1006 if (cvt_id) 1007 *cvt_id = cvt_idx; 1008 return 0; 1009 } 1010 1011 /* Dynamically assign converter to stream */ 1012 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { 1013 per_cvt = get_cvt(spec, cvt_idx); 1014 1015 /* Must not already be assigned */ 1016 if (per_cvt->assigned) 1017 continue; 1018 if (per_pin == NULL) 1019 break; 1020 /* Must be in pin's mux's list of converters */ 1021 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++) 1022 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid) 1023 break; 1024 /* Not in mux list */ 1025 if (mux_idx == per_pin->num_mux_nids) 1026 continue; 1027 break; 1028 } 1029 1030 /* No free converters */ 1031 if (cvt_idx == spec->num_cvts) 1032 return -EBUSY; 1033 1034 if (per_pin != NULL) 1035 per_pin->mux_idx = mux_idx; 1036 1037 if (cvt_id) 1038 *cvt_id = cvt_idx; 1039 1040 return 0; 1041 } 1042 1043 /* Assure the pin select the right convetor */ 1044 static void intel_verify_pin_cvt_connect(struct hda_codec *codec, 1045 struct hdmi_spec_per_pin *per_pin) 1046 { 1047 hda_nid_t pin_nid = per_pin->pin_nid; 1048 int mux_idx, curr; 1049 1050 mux_idx = per_pin->mux_idx; 1051 curr = snd_hda_codec_read(codec, pin_nid, 0, 1052 AC_VERB_GET_CONNECT_SEL, 0); 1053 if (curr != mux_idx) 1054 snd_hda_codec_write_cache(codec, pin_nid, 0, 1055 AC_VERB_SET_CONNECT_SEL, 1056 mux_idx); 1057 } 1058 1059 /* get the mux index for the converter of the pins 1060 * converter's mux index is the same for all pins on Intel platform 1061 */ 1062 static int intel_cvt_id_to_mux_idx(struct hdmi_spec *spec, 1063 hda_nid_t cvt_nid) 1064 { 1065 int i; 1066 1067 for (i = 0; i < spec->num_cvts; i++) 1068 if (spec->cvt_nids[i] == cvt_nid) 1069 return i; 1070 return -EINVAL; 1071 } 1072 1073 /* Intel HDMI workaround to fix audio routing issue: 1074 * For some Intel display codecs, pins share the same connection list. 1075 * So a conveter can be selected by multiple pins and playback on any of these 1076 * pins will generate sound on the external display, because audio flows from 1077 * the same converter to the display pipeline. Also muting one pin may make 1078 * other pins have no sound output. 1079 * So this function assures that an assigned converter for a pin is not selected 1080 * by any other pins. 1081 */ 1082 static void intel_not_share_assigned_cvt(struct hda_codec *codec, 1083 hda_nid_t pin_nid, 1084 int dev_id, int mux_idx) 1085 { 1086 struct hdmi_spec *spec = codec->spec; 1087 hda_nid_t nid; 1088 int cvt_idx, curr; 1089 struct hdmi_spec_per_cvt *per_cvt; 1090 struct hdmi_spec_per_pin *per_pin; 1091 int pin_idx; 1092 1093 /* configure the pins connections */ 1094 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 1095 int dev_id_saved; 1096 int dev_num; 1097 1098 per_pin = get_pin(spec, pin_idx); 1099 /* 1100 * pin not connected to monitor 1101 * no need to operate on it 1102 */ 1103 if (!per_pin->pcm) 1104 continue; 1105 1106 if ((per_pin->pin_nid == pin_nid) && 1107 (per_pin->dev_id == dev_id)) 1108 continue; 1109 1110 /* 1111 * if per_pin->dev_id >= dev_num, 1112 * snd_hda_get_dev_select() will fail, 1113 * and the following operation is unpredictable. 1114 * So skip this situation. 1115 */ 1116 dev_num = snd_hda_get_num_devices(codec, per_pin->pin_nid) + 1; 1117 if (per_pin->dev_id >= dev_num) 1118 continue; 1119 1120 nid = per_pin->pin_nid; 1121 1122 /* 1123 * Calling this function should not impact 1124 * on the device entry selection 1125 * So let's save the dev id for each pin, 1126 * and restore it when return 1127 */ 1128 dev_id_saved = snd_hda_get_dev_select(codec, nid); 1129 snd_hda_set_dev_select(codec, nid, per_pin->dev_id); 1130 curr = snd_hda_codec_read(codec, nid, 0, 1131 AC_VERB_GET_CONNECT_SEL, 0); 1132 if (curr != mux_idx) { 1133 snd_hda_set_dev_select(codec, nid, dev_id_saved); 1134 continue; 1135 } 1136 1137 1138 /* choose an unassigned converter. The conveters in the 1139 * connection list are in the same order as in the codec. 1140 */ 1141 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { 1142 per_cvt = get_cvt(spec, cvt_idx); 1143 if (!per_cvt->assigned) { 1144 codec_dbg(codec, 1145 "choose cvt %d for pin NID 0x%x\n", 1146 cvt_idx, nid); 1147 snd_hda_codec_write_cache(codec, nid, 0, 1148 AC_VERB_SET_CONNECT_SEL, 1149 cvt_idx); 1150 break; 1151 } 1152 } 1153 snd_hda_set_dev_select(codec, nid, dev_id_saved); 1154 } 1155 } 1156 1157 /* A wrapper of intel_not_share_asigned_cvt() */ 1158 static void intel_not_share_assigned_cvt_nid(struct hda_codec *codec, 1159 hda_nid_t pin_nid, int dev_id, hda_nid_t cvt_nid) 1160 { 1161 int mux_idx; 1162 struct hdmi_spec *spec = codec->spec; 1163 1164 /* On Intel platform, the mapping of converter nid to 1165 * mux index of the pins are always the same. 1166 * The pin nid may be 0, this means all pins will not 1167 * share the converter. 1168 */ 1169 mux_idx = intel_cvt_id_to_mux_idx(spec, cvt_nid); 1170 if (mux_idx >= 0) 1171 intel_not_share_assigned_cvt(codec, pin_nid, dev_id, mux_idx); 1172 } 1173 1174 /* skeleton caller of pin_cvt_fixup ops */ 1175 static void pin_cvt_fixup(struct hda_codec *codec, 1176 struct hdmi_spec_per_pin *per_pin, 1177 hda_nid_t cvt_nid) 1178 { 1179 struct hdmi_spec *spec = codec->spec; 1180 1181 if (spec->ops.pin_cvt_fixup) 1182 spec->ops.pin_cvt_fixup(codec, per_pin, cvt_nid); 1183 } 1184 1185 /* called in hdmi_pcm_open when no pin is assigned to the PCM 1186 * in dyn_pcm_assign mode. 1187 */ 1188 static int hdmi_pcm_open_no_pin(struct hda_pcm_stream *hinfo, 1189 struct hda_codec *codec, 1190 struct snd_pcm_substream *substream) 1191 { 1192 struct hdmi_spec *spec = codec->spec; 1193 struct snd_pcm_runtime *runtime = substream->runtime; 1194 int cvt_idx, pcm_idx; 1195 struct hdmi_spec_per_cvt *per_cvt = NULL; 1196 int err; 1197 1198 pcm_idx = hinfo_to_pcm_index(codec, hinfo); 1199 if (pcm_idx < 0) 1200 return -EINVAL; 1201 1202 err = hdmi_choose_cvt(codec, -1, &cvt_idx); 1203 if (err) 1204 return err; 1205 1206 per_cvt = get_cvt(spec, cvt_idx); 1207 per_cvt->assigned = 1; 1208 hinfo->nid = per_cvt->cvt_nid; 1209 1210 pin_cvt_fixup(codec, NULL, per_cvt->cvt_nid); 1211 1212 set_bit(pcm_idx, &spec->pcm_in_use); 1213 /* todo: setup spdif ctls assign */ 1214 1215 /* Initially set the converter's capabilities */ 1216 hinfo->channels_min = per_cvt->channels_min; 1217 hinfo->channels_max = per_cvt->channels_max; 1218 hinfo->rates = per_cvt->rates; 1219 hinfo->formats = per_cvt->formats; 1220 hinfo->maxbps = per_cvt->maxbps; 1221 1222 /* Store the updated parameters */ 1223 runtime->hw.channels_min = hinfo->channels_min; 1224 runtime->hw.channels_max = hinfo->channels_max; 1225 runtime->hw.formats = hinfo->formats; 1226 runtime->hw.rates = hinfo->rates; 1227 1228 snd_pcm_hw_constraint_step(substream->runtime, 0, 1229 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 1230 return 0; 1231 } 1232 1233 /* 1234 * HDA PCM callbacks 1235 */ 1236 static int hdmi_pcm_open(struct hda_pcm_stream *hinfo, 1237 struct hda_codec *codec, 1238 struct snd_pcm_substream *substream) 1239 { 1240 struct hdmi_spec *spec = codec->spec; 1241 struct snd_pcm_runtime *runtime = substream->runtime; 1242 int pin_idx, cvt_idx, pcm_idx; 1243 struct hdmi_spec_per_pin *per_pin; 1244 struct hdmi_eld *eld; 1245 struct hdmi_spec_per_cvt *per_cvt = NULL; 1246 int err; 1247 1248 /* Validate hinfo */ 1249 pcm_idx = hinfo_to_pcm_index(codec, hinfo); 1250 if (pcm_idx < 0) 1251 return -EINVAL; 1252 1253 mutex_lock(&spec->pcm_lock); 1254 pin_idx = hinfo_to_pin_index(codec, hinfo); 1255 if (!spec->dyn_pcm_assign) { 1256 if (snd_BUG_ON(pin_idx < 0)) { 1257 err = -EINVAL; 1258 goto unlock; 1259 } 1260 } else { 1261 /* no pin is assigned to the PCM 1262 * PA need pcm open successfully when probe 1263 */ 1264 if (pin_idx < 0) { 1265 err = hdmi_pcm_open_no_pin(hinfo, codec, substream); 1266 goto unlock; 1267 } 1268 } 1269 1270 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx); 1271 if (err < 0) 1272 goto unlock; 1273 1274 per_cvt = get_cvt(spec, cvt_idx); 1275 /* Claim converter */ 1276 per_cvt->assigned = 1; 1277 1278 set_bit(pcm_idx, &spec->pcm_in_use); 1279 per_pin = get_pin(spec, pin_idx); 1280 per_pin->cvt_nid = per_cvt->cvt_nid; 1281 per_pin->silent_stream = false; 1282 hinfo->nid = per_cvt->cvt_nid; 1283 1284 /* flip stripe flag for the assigned stream if supported */ 1285 if (get_wcaps(codec, per_cvt->cvt_nid) & AC_WCAP_STRIPE) 1286 azx_stream(get_azx_dev(substream))->stripe = 1; 1287 1288 snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id); 1289 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0, 1290 AC_VERB_SET_CONNECT_SEL, 1291 per_pin->mux_idx); 1292 1293 /* configure unused pins to choose other converters */ 1294 pin_cvt_fixup(codec, per_pin, 0); 1295 1296 snd_hda_spdif_ctls_assign(codec, pcm_idx, per_cvt->cvt_nid); 1297 1298 /* Initially set the converter's capabilities */ 1299 hinfo->channels_min = per_cvt->channels_min; 1300 hinfo->channels_max = per_cvt->channels_max; 1301 hinfo->rates = per_cvt->rates; 1302 hinfo->formats = per_cvt->formats; 1303 hinfo->maxbps = per_cvt->maxbps; 1304 1305 eld = &per_pin->sink_eld; 1306 /* Restrict capabilities by ELD if this isn't disabled */ 1307 if (!static_hdmi_pcm && eld->eld_valid) { 1308 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo); 1309 if (hinfo->channels_min > hinfo->channels_max || 1310 !hinfo->rates || !hinfo->formats) { 1311 per_cvt->assigned = 0; 1312 hinfo->nid = 0; 1313 snd_hda_spdif_ctls_unassign(codec, pcm_idx); 1314 err = -ENODEV; 1315 goto unlock; 1316 } 1317 } 1318 1319 /* Store the updated parameters */ 1320 runtime->hw.channels_min = hinfo->channels_min; 1321 runtime->hw.channels_max = hinfo->channels_max; 1322 runtime->hw.formats = hinfo->formats; 1323 runtime->hw.rates = hinfo->rates; 1324 1325 snd_pcm_hw_constraint_step(substream->runtime, 0, 1326 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 1327 unlock: 1328 mutex_unlock(&spec->pcm_lock); 1329 return err; 1330 } 1331 1332 /* 1333 * HDA/HDMI auto parsing 1334 */ 1335 static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx) 1336 { 1337 struct hdmi_spec *spec = codec->spec; 1338 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 1339 hda_nid_t pin_nid = per_pin->pin_nid; 1340 int dev_id = per_pin->dev_id; 1341 int conns; 1342 1343 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) { 1344 codec_warn(codec, 1345 "HDMI: pin NID 0x%x wcaps %#x does not support connection list\n", 1346 pin_nid, get_wcaps(codec, pin_nid)); 1347 return -EINVAL; 1348 } 1349 1350 snd_hda_set_dev_select(codec, pin_nid, dev_id); 1351 1352 if (spec->intel_hsw_fixup) { 1353 conns = spec->num_cvts; 1354 memcpy(per_pin->mux_nids, spec->cvt_nids, 1355 sizeof(hda_nid_t) * conns); 1356 } else { 1357 conns = snd_hda_get_raw_connections(codec, pin_nid, 1358 per_pin->mux_nids, 1359 HDA_MAX_CONNECTIONS); 1360 } 1361 1362 /* all the device entries on the same pin have the same conn list */ 1363 per_pin->num_mux_nids = conns; 1364 1365 return 0; 1366 } 1367 1368 static int hdmi_find_pcm_slot(struct hdmi_spec *spec, 1369 struct hdmi_spec_per_pin *per_pin) 1370 { 1371 int i; 1372 1373 /* on the new machines, try to assign the pcm slot dynamically, 1374 * not use the preferred fixed map (legacy way) anymore. 1375 */ 1376 if (spec->dyn_pcm_no_legacy) 1377 goto last_try; 1378 1379 /* 1380 * generic_hdmi_build_pcms() may allocate extra PCMs on some 1381 * platforms (with maximum of 'num_nids + dev_num - 1') 1382 * 1383 * The per_pin of pin_nid_idx=n and dev_id=m prefers to get pcm-n 1384 * if m==0. This guarantees that dynamic pcm assignments are compatible 1385 * with the legacy static per_pin-pcm assignment that existed in the 1386 * days before DP-MST. 1387 * 1388 * Intel DP-MST prefers this legacy behavior for compatibility, too. 1389 * 1390 * per_pin of m!=0 prefers to get pcm=(num_nids + (m - 1)). 1391 */ 1392 1393 if (per_pin->dev_id == 0 || spec->intel_hsw_fixup) { 1394 if (!test_bit(per_pin->pin_nid_idx, &spec->pcm_bitmap)) 1395 return per_pin->pin_nid_idx; 1396 } else { 1397 i = spec->num_nids + (per_pin->dev_id - 1); 1398 if (i < spec->pcm_used && !(test_bit(i, &spec->pcm_bitmap))) 1399 return i; 1400 } 1401 1402 /* have a second try; check the area over num_nids */ 1403 for (i = spec->num_nids; i < spec->pcm_used; i++) { 1404 if (!test_bit(i, &spec->pcm_bitmap)) 1405 return i; 1406 } 1407 1408 last_try: 1409 /* the last try; check the empty slots in pins */ 1410 for (i = 0; i < spec->pcm_used; i++) { 1411 if (!test_bit(i, &spec->pcm_bitmap)) 1412 return i; 1413 } 1414 return -EBUSY; 1415 } 1416 1417 static void hdmi_attach_hda_pcm(struct hdmi_spec *spec, 1418 struct hdmi_spec_per_pin *per_pin) 1419 { 1420 int idx; 1421 1422 /* pcm already be attached to the pin */ 1423 if (per_pin->pcm) 1424 return; 1425 idx = hdmi_find_pcm_slot(spec, per_pin); 1426 if (idx == -EBUSY) 1427 return; 1428 per_pin->pcm_idx = idx; 1429 per_pin->pcm = get_hdmi_pcm(spec, idx); 1430 set_bit(idx, &spec->pcm_bitmap); 1431 } 1432 1433 static void hdmi_detach_hda_pcm(struct hdmi_spec *spec, 1434 struct hdmi_spec_per_pin *per_pin) 1435 { 1436 int idx; 1437 1438 /* pcm already be detached from the pin */ 1439 if (!per_pin->pcm) 1440 return; 1441 idx = per_pin->pcm_idx; 1442 per_pin->pcm_idx = -1; 1443 per_pin->pcm = NULL; 1444 if (idx >= 0 && idx < spec->pcm_used) 1445 clear_bit(idx, &spec->pcm_bitmap); 1446 } 1447 1448 static int hdmi_get_pin_cvt_mux(struct hdmi_spec *spec, 1449 struct hdmi_spec_per_pin *per_pin, hda_nid_t cvt_nid) 1450 { 1451 int mux_idx; 1452 1453 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++) 1454 if (per_pin->mux_nids[mux_idx] == cvt_nid) 1455 break; 1456 return mux_idx; 1457 } 1458 1459 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid); 1460 1461 static void hdmi_pcm_setup_pin(struct hdmi_spec *spec, 1462 struct hdmi_spec_per_pin *per_pin) 1463 { 1464 struct hda_codec *codec = per_pin->codec; 1465 struct hda_pcm *pcm; 1466 struct hda_pcm_stream *hinfo; 1467 struct snd_pcm_substream *substream; 1468 int mux_idx; 1469 bool non_pcm; 1470 1471 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used) 1472 pcm = get_pcm_rec(spec, per_pin->pcm_idx); 1473 else 1474 return; 1475 if (!pcm->pcm) 1476 return; 1477 if (!test_bit(per_pin->pcm_idx, &spec->pcm_in_use)) 1478 return; 1479 1480 /* hdmi audio only uses playback and one substream */ 1481 hinfo = pcm->stream; 1482 substream = pcm->pcm->streams[0].substream; 1483 1484 per_pin->cvt_nid = hinfo->nid; 1485 1486 mux_idx = hdmi_get_pin_cvt_mux(spec, per_pin, hinfo->nid); 1487 if (mux_idx < per_pin->num_mux_nids) { 1488 snd_hda_set_dev_select(codec, per_pin->pin_nid, 1489 per_pin->dev_id); 1490 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0, 1491 AC_VERB_SET_CONNECT_SEL, 1492 mux_idx); 1493 } 1494 snd_hda_spdif_ctls_assign(codec, per_pin->pcm_idx, hinfo->nid); 1495 1496 non_pcm = check_non_pcm_per_cvt(codec, hinfo->nid); 1497 if (substream->runtime) 1498 per_pin->channels = substream->runtime->channels; 1499 per_pin->setup = true; 1500 per_pin->mux_idx = mux_idx; 1501 1502 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm); 1503 } 1504 1505 static void hdmi_pcm_reset_pin(struct hdmi_spec *spec, 1506 struct hdmi_spec_per_pin *per_pin) 1507 { 1508 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used) 1509 snd_hda_spdif_ctls_unassign(per_pin->codec, per_pin->pcm_idx); 1510 1511 per_pin->chmap_set = false; 1512 memset(per_pin->chmap, 0, sizeof(per_pin->chmap)); 1513 1514 per_pin->setup = false; 1515 per_pin->channels = 0; 1516 } 1517 1518 static struct snd_jack *pin_idx_to_pcm_jack(struct hda_codec *codec, 1519 struct hdmi_spec_per_pin *per_pin) 1520 { 1521 struct hdmi_spec *spec = codec->spec; 1522 1523 if (per_pin->pcm_idx >= 0) 1524 return spec->pcm_rec[per_pin->pcm_idx].jack; 1525 else 1526 return NULL; 1527 } 1528 1529 /* update per_pin ELD from the given new ELD; 1530 * setup info frame and notification accordingly 1531 * also notify ELD kctl and report jack status changes 1532 */ 1533 static void update_eld(struct hda_codec *codec, 1534 struct hdmi_spec_per_pin *per_pin, 1535 struct hdmi_eld *eld, 1536 int repoll) 1537 { 1538 struct hdmi_eld *pin_eld = &per_pin->sink_eld; 1539 struct hdmi_spec *spec = codec->spec; 1540 struct snd_jack *pcm_jack; 1541 bool old_eld_valid = pin_eld->eld_valid; 1542 bool eld_changed; 1543 int pcm_idx; 1544 1545 if (eld->eld_valid) { 1546 if (eld->eld_size <= 0 || 1547 snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer, 1548 eld->eld_size) < 0) { 1549 eld->eld_valid = false; 1550 if (repoll) { 1551 schedule_delayed_work(&per_pin->work, 1552 msecs_to_jiffies(300)); 1553 return; 1554 } 1555 } 1556 } 1557 1558 if (!eld->eld_valid || eld->eld_size <= 0 || eld->info.sad_count <= 0) { 1559 eld->eld_valid = false; 1560 eld->eld_size = 0; 1561 } 1562 1563 /* for monitor disconnection, save pcm_idx firstly */ 1564 pcm_idx = per_pin->pcm_idx; 1565 1566 /* 1567 * pcm_idx >=0 before update_eld() means it is in monitor 1568 * disconnected event. Jack must be fetched before update_eld(). 1569 */ 1570 pcm_jack = pin_idx_to_pcm_jack(codec, per_pin); 1571 1572 if (spec->dyn_pcm_assign) { 1573 if (eld->eld_valid) { 1574 hdmi_attach_hda_pcm(spec, per_pin); 1575 hdmi_pcm_setup_pin(spec, per_pin); 1576 } else { 1577 hdmi_pcm_reset_pin(spec, per_pin); 1578 hdmi_detach_hda_pcm(spec, per_pin); 1579 } 1580 } 1581 /* if pcm_idx == -1, it means this is in monitor connection event 1582 * we can get the correct pcm_idx now. 1583 */ 1584 if (pcm_idx == -1) 1585 pcm_idx = per_pin->pcm_idx; 1586 if (!pcm_jack) 1587 pcm_jack = pin_idx_to_pcm_jack(codec, per_pin); 1588 1589 if (eld->eld_valid) 1590 snd_hdmi_show_eld(codec, &eld->info); 1591 1592 eld_changed = (pin_eld->eld_valid != eld->eld_valid); 1593 eld_changed |= (pin_eld->monitor_present != eld->monitor_present); 1594 if (!eld_changed && eld->eld_valid && pin_eld->eld_valid) 1595 if (pin_eld->eld_size != eld->eld_size || 1596 memcmp(pin_eld->eld_buffer, eld->eld_buffer, 1597 eld->eld_size) != 0) 1598 eld_changed = true; 1599 1600 if (eld_changed) { 1601 pin_eld->monitor_present = eld->monitor_present; 1602 pin_eld->eld_valid = eld->eld_valid; 1603 pin_eld->eld_size = eld->eld_size; 1604 if (eld->eld_valid) 1605 memcpy(pin_eld->eld_buffer, eld->eld_buffer, 1606 eld->eld_size); 1607 pin_eld->info = eld->info; 1608 } 1609 1610 /* 1611 * Re-setup pin and infoframe. This is needed e.g. when 1612 * - sink is first plugged-in 1613 * - transcoder can change during stream playback on Haswell 1614 * and this can make HW reset converter selection on a pin. 1615 */ 1616 if (eld->eld_valid && !old_eld_valid && per_pin->setup) { 1617 pin_cvt_fixup(codec, per_pin, 0); 1618 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm); 1619 } 1620 1621 if (eld_changed && pcm_idx >= 0) 1622 snd_ctl_notify(codec->card, 1623 SNDRV_CTL_EVENT_MASK_VALUE | 1624 SNDRV_CTL_EVENT_MASK_INFO, 1625 &get_hdmi_pcm(spec, pcm_idx)->eld_ctl->id); 1626 1627 if (eld_changed && pcm_jack) 1628 snd_jack_report(pcm_jack, 1629 (eld->monitor_present && eld->eld_valid) ? 1630 SND_JACK_AVOUT : 0); 1631 } 1632 1633 /* update ELD and jack state via HD-audio verbs */ 1634 static void hdmi_present_sense_via_verbs(struct hdmi_spec_per_pin *per_pin, 1635 int repoll) 1636 { 1637 struct hda_codec *codec = per_pin->codec; 1638 struct hdmi_spec *spec = codec->spec; 1639 struct hdmi_eld *eld = &spec->temp_eld; 1640 struct device *dev = hda_codec_dev(codec); 1641 hda_nid_t pin_nid = per_pin->pin_nid; 1642 int dev_id = per_pin->dev_id; 1643 /* 1644 * Always execute a GetPinSense verb here, even when called from 1645 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited 1646 * response's PD bit is not the real PD value, but indicates that 1647 * the real PD value changed. An older version of the HD-audio 1648 * specification worked this way. Hence, we just ignore the data in 1649 * the unsolicited response to avoid custom WARs. 1650 */ 1651 int present; 1652 int ret; 1653 1654 #ifdef CONFIG_PM 1655 if (dev->power.runtime_status == RPM_SUSPENDING) 1656 return; 1657 #endif 1658 1659 ret = snd_hda_power_up_pm(codec); 1660 if (ret < 0 && pm_runtime_suspended(dev)) 1661 goto out; 1662 1663 present = snd_hda_jack_pin_sense(codec, pin_nid, dev_id); 1664 1665 mutex_lock(&per_pin->lock); 1666 eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE); 1667 if (eld->monitor_present) 1668 eld->eld_valid = !!(present & AC_PINSENSE_ELDV); 1669 else 1670 eld->eld_valid = false; 1671 1672 codec_dbg(codec, 1673 "HDMI status: Codec=%d NID=0x%x Presence_Detect=%d ELD_Valid=%d\n", 1674 codec->addr, pin_nid, eld->monitor_present, eld->eld_valid); 1675 1676 if (eld->eld_valid) { 1677 if (spec->ops.pin_get_eld(codec, pin_nid, dev_id, 1678 eld->eld_buffer, &eld->eld_size) < 0) 1679 eld->eld_valid = false; 1680 } 1681 1682 update_eld(codec, per_pin, eld, repoll); 1683 mutex_unlock(&per_pin->lock); 1684 out: 1685 snd_hda_power_down_pm(codec); 1686 } 1687 1688 #define I915_SILENT_RATE 48000 1689 #define I915_SILENT_CHANNELS 2 1690 #define I915_SILENT_FORMAT SNDRV_PCM_FORMAT_S16_LE 1691 #define I915_SILENT_FORMAT_BITS 16 1692 #define I915_SILENT_FMT_MASK 0xf 1693 1694 static void silent_stream_enable_i915(struct hda_codec *codec, 1695 struct hdmi_spec_per_pin *per_pin) 1696 { 1697 unsigned int format; 1698 1699 snd_hdac_sync_audio_rate(&codec->core, per_pin->pin_nid, 1700 per_pin->dev_id, I915_SILENT_RATE); 1701 1702 /* trigger silent stream generation in hw */ 1703 format = snd_hdac_calc_stream_format(I915_SILENT_RATE, I915_SILENT_CHANNELS, 1704 I915_SILENT_FORMAT, I915_SILENT_FORMAT_BITS, 0); 1705 snd_hda_codec_setup_stream(codec, per_pin->cvt_nid, 1706 I915_SILENT_FMT_MASK, I915_SILENT_FMT_MASK, format); 1707 usleep_range(100, 200); 1708 snd_hda_codec_setup_stream(codec, per_pin->cvt_nid, I915_SILENT_FMT_MASK, 0, format); 1709 1710 per_pin->channels = I915_SILENT_CHANNELS; 1711 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm); 1712 } 1713 1714 static void silent_stream_set_kae(struct hda_codec *codec, 1715 struct hdmi_spec_per_pin *per_pin, 1716 bool enable) 1717 { 1718 unsigned int param; 1719 1720 codec_dbg(codec, "HDMI: KAE %d cvt-NID=0x%x\n", enable, per_pin->cvt_nid); 1721 1722 param = snd_hda_codec_read(codec, per_pin->cvt_nid, 0, AC_VERB_GET_DIGI_CONVERT_1, 0); 1723 param = (param >> 16) & 0xff; 1724 1725 if (enable) 1726 param |= AC_DIG3_KAE; 1727 else 1728 param &= ~AC_DIG3_KAE; 1729 1730 snd_hda_codec_write(codec, per_pin->cvt_nid, 0, AC_VERB_SET_DIGI_CONVERT_3, param); 1731 } 1732 1733 static void silent_stream_enable(struct hda_codec *codec, 1734 struct hdmi_spec_per_pin *per_pin) 1735 { 1736 struct hdmi_spec *spec = codec->spec; 1737 struct hdmi_spec_per_cvt *per_cvt; 1738 int cvt_idx, pin_idx, err; 1739 int keep_power = 0; 1740 1741 /* 1742 * Power-up will call hdmi_present_sense, so the PM calls 1743 * have to be done without mutex held. 1744 */ 1745 1746 err = snd_hda_power_up_pm(codec); 1747 if (err < 0 && err != -EACCES) { 1748 codec_err(codec, 1749 "Failed to power up codec for silent stream enable ret=[%d]\n", err); 1750 snd_hda_power_down_pm(codec); 1751 return; 1752 } 1753 1754 mutex_lock(&per_pin->lock); 1755 1756 if (per_pin->setup) { 1757 codec_dbg(codec, "hdmi: PCM already open, no silent stream\n"); 1758 err = -EBUSY; 1759 goto unlock_out; 1760 } 1761 1762 pin_idx = pin_id_to_pin_index(codec, per_pin->pin_nid, per_pin->dev_id); 1763 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx); 1764 if (err) { 1765 codec_err(codec, "hdmi: no free converter to enable silent mode\n"); 1766 goto unlock_out; 1767 } 1768 1769 per_cvt = get_cvt(spec, cvt_idx); 1770 per_cvt->assigned = 1; 1771 per_pin->cvt_nid = per_cvt->cvt_nid; 1772 per_pin->silent_stream = true; 1773 1774 codec_dbg(codec, "hdmi: enabling silent stream pin-NID=0x%x cvt-NID=0x%x\n", 1775 per_pin->pin_nid, per_cvt->cvt_nid); 1776 1777 snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id); 1778 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0, 1779 AC_VERB_SET_CONNECT_SEL, 1780 per_pin->mux_idx); 1781 1782 /* configure unused pins to choose other converters */ 1783 pin_cvt_fixup(codec, per_pin, 0); 1784 1785 switch (spec->silent_stream_type) { 1786 case SILENT_STREAM_KAE: 1787 silent_stream_set_kae(codec, per_pin, true); 1788 break; 1789 case SILENT_STREAM_I915: 1790 silent_stream_enable_i915(codec, per_pin); 1791 keep_power = 1; 1792 break; 1793 default: 1794 break; 1795 } 1796 1797 unlock_out: 1798 mutex_unlock(&per_pin->lock); 1799 1800 if (err || !keep_power) 1801 snd_hda_power_down_pm(codec); 1802 } 1803 1804 static void silent_stream_disable(struct hda_codec *codec, 1805 struct hdmi_spec_per_pin *per_pin) 1806 { 1807 struct hdmi_spec *spec = codec->spec; 1808 struct hdmi_spec_per_cvt *per_cvt; 1809 int cvt_idx, err; 1810 1811 err = snd_hda_power_up_pm(codec); 1812 if (err < 0 && err != -EACCES) { 1813 codec_err(codec, 1814 "Failed to power up codec for silent stream disable ret=[%d]\n", 1815 err); 1816 snd_hda_power_down_pm(codec); 1817 return; 1818 } 1819 1820 mutex_lock(&per_pin->lock); 1821 if (!per_pin->silent_stream) 1822 goto unlock_out; 1823 1824 codec_dbg(codec, "HDMI: disable silent stream on pin-NID=0x%x cvt-NID=0x%x\n", 1825 per_pin->pin_nid, per_pin->cvt_nid); 1826 1827 cvt_idx = cvt_nid_to_cvt_index(codec, per_pin->cvt_nid); 1828 if (cvt_idx >= 0 && cvt_idx < spec->num_cvts) { 1829 per_cvt = get_cvt(spec, cvt_idx); 1830 per_cvt->assigned = 0; 1831 } 1832 1833 if (spec->silent_stream_type == SILENT_STREAM_I915) { 1834 /* release ref taken in silent_stream_enable() */ 1835 snd_hda_power_down_pm(codec); 1836 } else if (spec->silent_stream_type == SILENT_STREAM_KAE) { 1837 silent_stream_set_kae(codec, per_pin, false); 1838 } 1839 1840 per_pin->cvt_nid = 0; 1841 per_pin->silent_stream = false; 1842 1843 unlock_out: 1844 mutex_unlock(&per_pin->lock); 1845 1846 snd_hda_power_down_pm(codec); 1847 } 1848 1849 /* update ELD and jack state via audio component */ 1850 static void sync_eld_via_acomp(struct hda_codec *codec, 1851 struct hdmi_spec_per_pin *per_pin) 1852 { 1853 struct hdmi_spec *spec = codec->spec; 1854 struct hdmi_eld *eld = &spec->temp_eld; 1855 bool monitor_prev, monitor_next; 1856 1857 mutex_lock(&per_pin->lock); 1858 eld->monitor_present = false; 1859 monitor_prev = per_pin->sink_eld.monitor_present; 1860 eld->eld_size = snd_hdac_acomp_get_eld(&codec->core, per_pin->pin_nid, 1861 per_pin->dev_id, &eld->monitor_present, 1862 eld->eld_buffer, ELD_MAX_SIZE); 1863 eld->eld_valid = (eld->eld_size > 0); 1864 update_eld(codec, per_pin, eld, 0); 1865 monitor_next = per_pin->sink_eld.monitor_present; 1866 mutex_unlock(&per_pin->lock); 1867 1868 if (spec->silent_stream_type) { 1869 if (!monitor_prev && monitor_next) 1870 silent_stream_enable(codec, per_pin); 1871 else if (monitor_prev && !monitor_next) 1872 silent_stream_disable(codec, per_pin); 1873 } 1874 } 1875 1876 static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll) 1877 { 1878 struct hda_codec *codec = per_pin->codec; 1879 1880 if (!codec_has_acomp(codec)) 1881 hdmi_present_sense_via_verbs(per_pin, repoll); 1882 else 1883 sync_eld_via_acomp(codec, per_pin); 1884 } 1885 1886 static void hdmi_repoll_eld(struct work_struct *work) 1887 { 1888 struct hdmi_spec_per_pin *per_pin = 1889 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work); 1890 struct hda_codec *codec = per_pin->codec; 1891 struct hdmi_spec *spec = codec->spec; 1892 struct hda_jack_tbl *jack; 1893 1894 jack = snd_hda_jack_tbl_get_mst(codec, per_pin->pin_nid, 1895 per_pin->dev_id); 1896 if (jack) 1897 jack->jack_dirty = 1; 1898 1899 if (per_pin->repoll_count++ > 6) 1900 per_pin->repoll_count = 0; 1901 1902 mutex_lock(&spec->pcm_lock); 1903 hdmi_present_sense(per_pin, per_pin->repoll_count); 1904 mutex_unlock(&spec->pcm_lock); 1905 } 1906 1907 static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid) 1908 { 1909 struct hdmi_spec *spec = codec->spec; 1910 unsigned int caps, config; 1911 int pin_idx; 1912 struct hdmi_spec_per_pin *per_pin; 1913 int err; 1914 int dev_num, i; 1915 1916 caps = snd_hda_query_pin_caps(codec, pin_nid); 1917 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP))) 1918 return 0; 1919 1920 /* 1921 * For DP MST audio, Configuration Default is the same for 1922 * all device entries on the same pin 1923 */ 1924 config = snd_hda_codec_get_pincfg(codec, pin_nid); 1925 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE && 1926 !spec->force_connect) 1927 return 0; 1928 1929 /* 1930 * To simplify the implementation, malloc all 1931 * the virtual pins in the initialization statically 1932 */ 1933 if (spec->intel_hsw_fixup) { 1934 /* 1935 * On Intel platforms, device entries count returned 1936 * by AC_PAR_DEVLIST_LEN is dynamic, and depends on 1937 * the type of receiver that is connected. Allocate pin 1938 * structures based on worst case. 1939 */ 1940 dev_num = spec->dev_num; 1941 } else if (spec->dyn_pcm_assign && codec->dp_mst) { 1942 dev_num = snd_hda_get_num_devices(codec, pin_nid) + 1; 1943 /* 1944 * spec->dev_num is the maxinum number of device entries 1945 * among all the pins 1946 */ 1947 spec->dev_num = (spec->dev_num > dev_num) ? 1948 spec->dev_num : dev_num; 1949 } else { 1950 /* 1951 * If the platform doesn't support DP MST, 1952 * manually set dev_num to 1. This means 1953 * the pin has only one device entry. 1954 */ 1955 dev_num = 1; 1956 spec->dev_num = 1; 1957 } 1958 1959 for (i = 0; i < dev_num; i++) { 1960 pin_idx = spec->num_pins; 1961 per_pin = snd_array_new(&spec->pins); 1962 1963 if (!per_pin) 1964 return -ENOMEM; 1965 1966 if (spec->dyn_pcm_assign) { 1967 per_pin->pcm = NULL; 1968 per_pin->pcm_idx = -1; 1969 } else { 1970 per_pin->pcm = get_hdmi_pcm(spec, pin_idx); 1971 per_pin->pcm_idx = pin_idx; 1972 } 1973 per_pin->pin_nid = pin_nid; 1974 per_pin->pin_nid_idx = spec->num_nids; 1975 per_pin->dev_id = i; 1976 per_pin->non_pcm = false; 1977 snd_hda_set_dev_select(codec, pin_nid, i); 1978 err = hdmi_read_pin_conn(codec, pin_idx); 1979 if (err < 0) 1980 return err; 1981 spec->num_pins++; 1982 } 1983 spec->num_nids++; 1984 1985 return 0; 1986 } 1987 1988 static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid) 1989 { 1990 struct hdmi_spec *spec = codec->spec; 1991 struct hdmi_spec_per_cvt *per_cvt; 1992 unsigned int chans; 1993 int err; 1994 1995 chans = get_wcaps(codec, cvt_nid); 1996 chans = get_wcaps_channels(chans); 1997 1998 per_cvt = snd_array_new(&spec->cvts); 1999 if (!per_cvt) 2000 return -ENOMEM; 2001 2002 per_cvt->cvt_nid = cvt_nid; 2003 per_cvt->channels_min = 2; 2004 if (chans <= 16) { 2005 per_cvt->channels_max = chans; 2006 if (chans > spec->chmap.channels_max) 2007 spec->chmap.channels_max = chans; 2008 } 2009 2010 err = snd_hda_query_supported_pcm(codec, cvt_nid, 2011 &per_cvt->rates, 2012 &per_cvt->formats, 2013 &per_cvt->maxbps); 2014 if (err < 0) 2015 return err; 2016 2017 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids)) 2018 spec->cvt_nids[spec->num_cvts] = cvt_nid; 2019 spec->num_cvts++; 2020 2021 return 0; 2022 } 2023 2024 static const struct snd_pci_quirk force_connect_list[] = { 2025 SND_PCI_QUIRK(0x103c, 0x870f, "HP", 1), 2026 SND_PCI_QUIRK(0x103c, 0x871a, "HP", 1), 2027 SND_PCI_QUIRK(0x1462, 0xec94, "MS-7C94", 1), 2028 SND_PCI_QUIRK(0x8086, 0x2081, "Intel NUC 10", 1), 2029 {} 2030 }; 2031 2032 static int hdmi_parse_codec(struct hda_codec *codec) 2033 { 2034 struct hdmi_spec *spec = codec->spec; 2035 hda_nid_t start_nid; 2036 unsigned int caps; 2037 int i, nodes; 2038 const struct snd_pci_quirk *q; 2039 2040 nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &start_nid); 2041 if (!start_nid || nodes < 0) { 2042 codec_warn(codec, "HDMI: failed to get afg sub nodes\n"); 2043 return -EINVAL; 2044 } 2045 2046 if (enable_all_pins) 2047 spec->force_connect = true; 2048 2049 q = snd_pci_quirk_lookup(codec->bus->pci, force_connect_list); 2050 2051 if (q && q->value) 2052 spec->force_connect = true; 2053 2054 /* 2055 * hdmi_add_pin() assumes total amount of converters to 2056 * be known, so first discover all converters 2057 */ 2058 for (i = 0; i < nodes; i++) { 2059 hda_nid_t nid = start_nid + i; 2060 2061 caps = get_wcaps(codec, nid); 2062 2063 if (!(caps & AC_WCAP_DIGITAL)) 2064 continue; 2065 2066 if (get_wcaps_type(caps) == AC_WID_AUD_OUT) 2067 hdmi_add_cvt(codec, nid); 2068 } 2069 2070 /* discover audio pins */ 2071 for (i = 0; i < nodes; i++) { 2072 hda_nid_t nid = start_nid + i; 2073 2074 caps = get_wcaps(codec, nid); 2075 2076 if (!(caps & AC_WCAP_DIGITAL)) 2077 continue; 2078 2079 if (get_wcaps_type(caps) == AC_WID_PIN) 2080 hdmi_add_pin(codec, nid); 2081 } 2082 2083 return 0; 2084 } 2085 2086 /* 2087 */ 2088 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid) 2089 { 2090 struct hda_spdif_out *spdif; 2091 bool non_pcm; 2092 2093 mutex_lock(&codec->spdif_mutex); 2094 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid); 2095 /* Add sanity check to pass klockwork check. 2096 * This should never happen. 2097 */ 2098 if (WARN_ON(spdif == NULL)) { 2099 mutex_unlock(&codec->spdif_mutex); 2100 return true; 2101 } 2102 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO); 2103 mutex_unlock(&codec->spdif_mutex); 2104 return non_pcm; 2105 } 2106 2107 /* 2108 * HDMI callbacks 2109 */ 2110 2111 static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 2112 struct hda_codec *codec, 2113 unsigned int stream_tag, 2114 unsigned int format, 2115 struct snd_pcm_substream *substream) 2116 { 2117 hda_nid_t cvt_nid = hinfo->nid; 2118 struct hdmi_spec *spec = codec->spec; 2119 int pin_idx; 2120 struct hdmi_spec_per_pin *per_pin; 2121 struct snd_pcm_runtime *runtime = substream->runtime; 2122 bool non_pcm; 2123 int pinctl, stripe; 2124 int err = 0; 2125 2126 mutex_lock(&spec->pcm_lock); 2127 pin_idx = hinfo_to_pin_index(codec, hinfo); 2128 if (spec->dyn_pcm_assign && pin_idx < 0) { 2129 /* when dyn_pcm_assign and pcm is not bound to a pin 2130 * skip pin setup and return 0 to make audio playback 2131 * be ongoing 2132 */ 2133 pin_cvt_fixup(codec, NULL, cvt_nid); 2134 snd_hda_codec_setup_stream(codec, cvt_nid, 2135 stream_tag, 0, format); 2136 goto unlock; 2137 } 2138 2139 if (snd_BUG_ON(pin_idx < 0)) { 2140 err = -EINVAL; 2141 goto unlock; 2142 } 2143 per_pin = get_pin(spec, pin_idx); 2144 2145 /* Verify pin:cvt selections to avoid silent audio after S3. 2146 * After S3, the audio driver restores pin:cvt selections 2147 * but this can happen before gfx is ready and such selection 2148 * is overlooked by HW. Thus multiple pins can share a same 2149 * default convertor and mute control will affect each other, 2150 * which can cause a resumed audio playback become silent 2151 * after S3. 2152 */ 2153 pin_cvt_fixup(codec, per_pin, 0); 2154 2155 /* Call sync_audio_rate to set the N/CTS/M manually if necessary */ 2156 /* Todo: add DP1.2 MST audio support later */ 2157 if (codec_has_acomp(codec)) 2158 snd_hdac_sync_audio_rate(&codec->core, per_pin->pin_nid, 2159 per_pin->dev_id, runtime->rate); 2160 2161 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid); 2162 mutex_lock(&per_pin->lock); 2163 per_pin->channels = substream->runtime->channels; 2164 per_pin->setup = true; 2165 2166 if (get_wcaps(codec, cvt_nid) & AC_WCAP_STRIPE) { 2167 stripe = snd_hdac_get_stream_stripe_ctl(&codec->bus->core, 2168 substream); 2169 snd_hda_codec_write(codec, cvt_nid, 0, 2170 AC_VERB_SET_STRIPE_CONTROL, 2171 stripe); 2172 } 2173 2174 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm); 2175 mutex_unlock(&per_pin->lock); 2176 if (spec->dyn_pin_out) { 2177 snd_hda_set_dev_select(codec, per_pin->pin_nid, 2178 per_pin->dev_id); 2179 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0, 2180 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 2181 snd_hda_codec_write(codec, per_pin->pin_nid, 0, 2182 AC_VERB_SET_PIN_WIDGET_CONTROL, 2183 pinctl | PIN_OUT); 2184 } 2185 2186 /* snd_hda_set_dev_select() has been called before */ 2187 err = spec->ops.setup_stream(codec, cvt_nid, per_pin->pin_nid, 2188 per_pin->dev_id, stream_tag, format); 2189 unlock: 2190 mutex_unlock(&spec->pcm_lock); 2191 return err; 2192 } 2193 2194 static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo, 2195 struct hda_codec *codec, 2196 struct snd_pcm_substream *substream) 2197 { 2198 snd_hda_codec_cleanup_stream(codec, hinfo->nid); 2199 return 0; 2200 } 2201 2202 static int hdmi_pcm_close(struct hda_pcm_stream *hinfo, 2203 struct hda_codec *codec, 2204 struct snd_pcm_substream *substream) 2205 { 2206 struct hdmi_spec *spec = codec->spec; 2207 int cvt_idx, pin_idx, pcm_idx; 2208 struct hdmi_spec_per_cvt *per_cvt; 2209 struct hdmi_spec_per_pin *per_pin; 2210 int pinctl; 2211 int err = 0; 2212 2213 mutex_lock(&spec->pcm_lock); 2214 if (hinfo->nid) { 2215 pcm_idx = hinfo_to_pcm_index(codec, hinfo); 2216 if (snd_BUG_ON(pcm_idx < 0)) { 2217 err = -EINVAL; 2218 goto unlock; 2219 } 2220 cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid); 2221 if (snd_BUG_ON(cvt_idx < 0)) { 2222 err = -EINVAL; 2223 goto unlock; 2224 } 2225 per_cvt = get_cvt(spec, cvt_idx); 2226 per_cvt->assigned = 0; 2227 hinfo->nid = 0; 2228 2229 azx_stream(get_azx_dev(substream))->stripe = 0; 2230 2231 snd_hda_spdif_ctls_unassign(codec, pcm_idx); 2232 clear_bit(pcm_idx, &spec->pcm_in_use); 2233 pin_idx = hinfo_to_pin_index(codec, hinfo); 2234 if (spec->dyn_pcm_assign && pin_idx < 0) 2235 goto unlock; 2236 2237 if (snd_BUG_ON(pin_idx < 0)) { 2238 err = -EINVAL; 2239 goto unlock; 2240 } 2241 per_pin = get_pin(spec, pin_idx); 2242 2243 if (spec->dyn_pin_out) { 2244 snd_hda_set_dev_select(codec, per_pin->pin_nid, 2245 per_pin->dev_id); 2246 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0, 2247 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 2248 snd_hda_codec_write(codec, per_pin->pin_nid, 0, 2249 AC_VERB_SET_PIN_WIDGET_CONTROL, 2250 pinctl & ~PIN_OUT); 2251 } 2252 2253 mutex_lock(&per_pin->lock); 2254 per_pin->chmap_set = false; 2255 memset(per_pin->chmap, 0, sizeof(per_pin->chmap)); 2256 2257 per_pin->setup = false; 2258 per_pin->channels = 0; 2259 mutex_unlock(&per_pin->lock); 2260 } 2261 2262 unlock: 2263 mutex_unlock(&spec->pcm_lock); 2264 2265 return err; 2266 } 2267 2268 static const struct hda_pcm_ops generic_ops = { 2269 .open = hdmi_pcm_open, 2270 .close = hdmi_pcm_close, 2271 .prepare = generic_hdmi_playback_pcm_prepare, 2272 .cleanup = generic_hdmi_playback_pcm_cleanup, 2273 }; 2274 2275 static int hdmi_get_spk_alloc(struct hdac_device *hdac, int pcm_idx) 2276 { 2277 struct hda_codec *codec = hdac_to_hda_codec(hdac); 2278 struct hdmi_spec *spec = codec->spec; 2279 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2280 2281 if (!per_pin) 2282 return 0; 2283 2284 return per_pin->sink_eld.info.spk_alloc; 2285 } 2286 2287 static void hdmi_get_chmap(struct hdac_device *hdac, int pcm_idx, 2288 unsigned char *chmap) 2289 { 2290 struct hda_codec *codec = hdac_to_hda_codec(hdac); 2291 struct hdmi_spec *spec = codec->spec; 2292 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2293 2294 /* chmap is already set to 0 in caller */ 2295 if (!per_pin) 2296 return; 2297 2298 memcpy(chmap, per_pin->chmap, ARRAY_SIZE(per_pin->chmap)); 2299 } 2300 2301 static void hdmi_set_chmap(struct hdac_device *hdac, int pcm_idx, 2302 unsigned char *chmap, int prepared) 2303 { 2304 struct hda_codec *codec = hdac_to_hda_codec(hdac); 2305 struct hdmi_spec *spec = codec->spec; 2306 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2307 2308 if (!per_pin) 2309 return; 2310 mutex_lock(&per_pin->lock); 2311 per_pin->chmap_set = true; 2312 memcpy(per_pin->chmap, chmap, ARRAY_SIZE(per_pin->chmap)); 2313 if (prepared) 2314 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm); 2315 mutex_unlock(&per_pin->lock); 2316 } 2317 2318 static bool is_hdmi_pcm_attached(struct hdac_device *hdac, int pcm_idx) 2319 { 2320 struct hda_codec *codec = hdac_to_hda_codec(hdac); 2321 struct hdmi_spec *spec = codec->spec; 2322 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2323 2324 return per_pin ? true:false; 2325 } 2326 2327 static int generic_hdmi_build_pcms(struct hda_codec *codec) 2328 { 2329 struct hdmi_spec *spec = codec->spec; 2330 int idx, pcm_num; 2331 2332 /* 2333 * for non-mst mode, pcm number is the same as before 2334 * for DP MST mode without extra PCM, pcm number is same 2335 * for DP MST mode with extra PCMs, pcm number is 2336 * (nid number + dev_num - 1) 2337 * dev_num is the device entry number in a pin 2338 */ 2339 2340 if (spec->dyn_pcm_no_legacy && codec->mst_no_extra_pcms) 2341 pcm_num = spec->num_cvts; 2342 else if (codec->mst_no_extra_pcms) 2343 pcm_num = spec->num_nids; 2344 else 2345 pcm_num = spec->num_nids + spec->dev_num - 1; 2346 2347 codec_dbg(codec, "hdmi: pcm_num set to %d\n", pcm_num); 2348 2349 for (idx = 0; idx < pcm_num; idx++) { 2350 struct hda_pcm *info; 2351 struct hda_pcm_stream *pstr; 2352 2353 info = snd_hda_codec_pcm_new(codec, "HDMI %d", idx); 2354 if (!info) 2355 return -ENOMEM; 2356 2357 spec->pcm_rec[idx].pcm = info; 2358 spec->pcm_used++; 2359 info->pcm_type = HDA_PCM_TYPE_HDMI; 2360 info->own_chmap = true; 2361 2362 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK]; 2363 pstr->substreams = 1; 2364 pstr->ops = generic_ops; 2365 /* pcm number is less than 16 */ 2366 if (spec->pcm_used >= 16) 2367 break; 2368 /* other pstr fields are set in open */ 2369 } 2370 2371 return 0; 2372 } 2373 2374 static void free_hdmi_jack_priv(struct snd_jack *jack) 2375 { 2376 struct hdmi_pcm *pcm = jack->private_data; 2377 2378 pcm->jack = NULL; 2379 } 2380 2381 static int generic_hdmi_build_jack(struct hda_codec *codec, int pcm_idx) 2382 { 2383 char hdmi_str[32] = "HDMI/DP"; 2384 struct hdmi_spec *spec = codec->spec; 2385 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pcm_idx); 2386 struct snd_jack *jack; 2387 int pcmdev = get_pcm_rec(spec, pcm_idx)->device; 2388 int err; 2389 2390 if (pcmdev > 0) 2391 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev); 2392 if (!spec->dyn_pcm_assign && 2393 !is_jack_detectable(codec, per_pin->pin_nid)) 2394 strncat(hdmi_str, " Phantom", 2395 sizeof(hdmi_str) - strlen(hdmi_str) - 1); 2396 2397 err = snd_jack_new(codec->card, hdmi_str, SND_JACK_AVOUT, &jack, 2398 true, false); 2399 if (err < 0) 2400 return err; 2401 2402 spec->pcm_rec[pcm_idx].jack = jack; 2403 jack->private_data = &spec->pcm_rec[pcm_idx]; 2404 jack->private_free = free_hdmi_jack_priv; 2405 return 0; 2406 } 2407 2408 static int generic_hdmi_build_controls(struct hda_codec *codec) 2409 { 2410 struct hdmi_spec *spec = codec->spec; 2411 int dev, err; 2412 int pin_idx, pcm_idx; 2413 2414 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { 2415 if (!get_pcm_rec(spec, pcm_idx)->pcm) { 2416 /* no PCM: mark this for skipping permanently */ 2417 set_bit(pcm_idx, &spec->pcm_bitmap); 2418 continue; 2419 } 2420 2421 err = generic_hdmi_build_jack(codec, pcm_idx); 2422 if (err < 0) 2423 return err; 2424 2425 /* create the spdif for each pcm 2426 * pin will be bound when monitor is connected 2427 */ 2428 if (spec->dyn_pcm_assign) 2429 err = snd_hda_create_dig_out_ctls(codec, 2430 0, spec->cvt_nids[0], 2431 HDA_PCM_TYPE_HDMI); 2432 else { 2433 struct hdmi_spec_per_pin *per_pin = 2434 get_pin(spec, pcm_idx); 2435 err = snd_hda_create_dig_out_ctls(codec, 2436 per_pin->pin_nid, 2437 per_pin->mux_nids[0], 2438 HDA_PCM_TYPE_HDMI); 2439 } 2440 if (err < 0) 2441 return err; 2442 snd_hda_spdif_ctls_unassign(codec, pcm_idx); 2443 2444 dev = get_pcm_rec(spec, pcm_idx)->device; 2445 if (dev != SNDRV_PCM_INVALID_DEVICE) { 2446 /* add control for ELD Bytes */ 2447 err = hdmi_create_eld_ctl(codec, pcm_idx, dev); 2448 if (err < 0) 2449 return err; 2450 } 2451 } 2452 2453 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2454 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2455 struct hdmi_eld *pin_eld = &per_pin->sink_eld; 2456 2457 pin_eld->eld_valid = false; 2458 hdmi_present_sense(per_pin, 0); 2459 } 2460 2461 /* add channel maps */ 2462 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { 2463 struct hda_pcm *pcm; 2464 2465 pcm = get_pcm_rec(spec, pcm_idx); 2466 if (!pcm || !pcm->pcm) 2467 break; 2468 err = snd_hdac_add_chmap_ctls(pcm->pcm, pcm_idx, &spec->chmap); 2469 if (err < 0) 2470 return err; 2471 } 2472 2473 return 0; 2474 } 2475 2476 static int generic_hdmi_init_per_pins(struct hda_codec *codec) 2477 { 2478 struct hdmi_spec *spec = codec->spec; 2479 int pin_idx; 2480 2481 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2482 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2483 2484 per_pin->codec = codec; 2485 mutex_init(&per_pin->lock); 2486 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld); 2487 eld_proc_new(per_pin, pin_idx); 2488 } 2489 return 0; 2490 } 2491 2492 static int generic_hdmi_init(struct hda_codec *codec) 2493 { 2494 struct hdmi_spec *spec = codec->spec; 2495 int pin_idx; 2496 2497 mutex_lock(&spec->bind_lock); 2498 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2499 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2500 hda_nid_t pin_nid = per_pin->pin_nid; 2501 int dev_id = per_pin->dev_id; 2502 2503 snd_hda_set_dev_select(codec, pin_nid, dev_id); 2504 hdmi_init_pin(codec, pin_nid); 2505 if (codec_has_acomp(codec)) 2506 continue; 2507 snd_hda_jack_detect_enable_callback_mst(codec, pin_nid, dev_id, 2508 jack_callback); 2509 } 2510 mutex_unlock(&spec->bind_lock); 2511 return 0; 2512 } 2513 2514 static void hdmi_array_init(struct hdmi_spec *spec, int nums) 2515 { 2516 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums); 2517 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums); 2518 } 2519 2520 static void hdmi_array_free(struct hdmi_spec *spec) 2521 { 2522 snd_array_free(&spec->pins); 2523 snd_array_free(&spec->cvts); 2524 } 2525 2526 static void generic_spec_free(struct hda_codec *codec) 2527 { 2528 struct hdmi_spec *spec = codec->spec; 2529 2530 if (spec) { 2531 hdmi_array_free(spec); 2532 kfree(spec); 2533 codec->spec = NULL; 2534 } 2535 codec->dp_mst = false; 2536 } 2537 2538 static void generic_hdmi_free(struct hda_codec *codec) 2539 { 2540 struct hdmi_spec *spec = codec->spec; 2541 int pin_idx, pcm_idx; 2542 2543 if (spec->acomp_registered) { 2544 snd_hdac_acomp_exit(&codec->bus->core); 2545 } else if (codec_has_acomp(codec)) { 2546 snd_hdac_acomp_register_notifier(&codec->bus->core, NULL); 2547 } 2548 codec->relaxed_resume = 0; 2549 2550 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2551 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2552 cancel_delayed_work_sync(&per_pin->work); 2553 eld_proc_free(per_pin); 2554 } 2555 2556 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { 2557 if (spec->pcm_rec[pcm_idx].jack == NULL) 2558 continue; 2559 if (spec->dyn_pcm_assign) 2560 snd_device_free(codec->card, 2561 spec->pcm_rec[pcm_idx].jack); 2562 else 2563 spec->pcm_rec[pcm_idx].jack = NULL; 2564 } 2565 2566 generic_spec_free(codec); 2567 } 2568 2569 #ifdef CONFIG_PM 2570 static int generic_hdmi_suspend(struct hda_codec *codec) 2571 { 2572 struct hdmi_spec *spec = codec->spec; 2573 int pin_idx; 2574 2575 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2576 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2577 cancel_delayed_work_sync(&per_pin->work); 2578 } 2579 return 0; 2580 } 2581 2582 static int generic_hdmi_resume(struct hda_codec *codec) 2583 { 2584 struct hdmi_spec *spec = codec->spec; 2585 int pin_idx; 2586 2587 codec->patch_ops.init(codec); 2588 snd_hda_regmap_sync(codec); 2589 2590 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2591 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2592 hdmi_present_sense(per_pin, 1); 2593 } 2594 return 0; 2595 } 2596 #endif 2597 2598 static const struct hda_codec_ops generic_hdmi_patch_ops = { 2599 .init = generic_hdmi_init, 2600 .free = generic_hdmi_free, 2601 .build_pcms = generic_hdmi_build_pcms, 2602 .build_controls = generic_hdmi_build_controls, 2603 .unsol_event = hdmi_unsol_event, 2604 #ifdef CONFIG_PM 2605 .suspend = generic_hdmi_suspend, 2606 .resume = generic_hdmi_resume, 2607 #endif 2608 }; 2609 2610 static const struct hdmi_ops generic_standard_hdmi_ops = { 2611 .pin_get_eld = hdmi_pin_get_eld, 2612 .pin_setup_infoframe = hdmi_pin_setup_infoframe, 2613 .pin_hbr_setup = hdmi_pin_hbr_setup, 2614 .setup_stream = hdmi_setup_stream, 2615 }; 2616 2617 /* allocate codec->spec and assign/initialize generic parser ops */ 2618 static int alloc_generic_hdmi(struct hda_codec *codec) 2619 { 2620 struct hdmi_spec *spec; 2621 2622 spec = kzalloc(sizeof(*spec), GFP_KERNEL); 2623 if (!spec) 2624 return -ENOMEM; 2625 2626 spec->codec = codec; 2627 spec->ops = generic_standard_hdmi_ops; 2628 spec->dev_num = 1; /* initialize to 1 */ 2629 mutex_init(&spec->pcm_lock); 2630 mutex_init(&spec->bind_lock); 2631 snd_hdac_register_chmap_ops(&codec->core, &spec->chmap); 2632 2633 spec->chmap.ops.get_chmap = hdmi_get_chmap; 2634 spec->chmap.ops.set_chmap = hdmi_set_chmap; 2635 spec->chmap.ops.is_pcm_attached = is_hdmi_pcm_attached; 2636 spec->chmap.ops.get_spk_alloc = hdmi_get_spk_alloc; 2637 2638 codec->spec = spec; 2639 hdmi_array_init(spec, 4); 2640 2641 codec->patch_ops = generic_hdmi_patch_ops; 2642 2643 return 0; 2644 } 2645 2646 /* generic HDMI parser */ 2647 static int patch_generic_hdmi(struct hda_codec *codec) 2648 { 2649 int err; 2650 2651 err = alloc_generic_hdmi(codec); 2652 if (err < 0) 2653 return err; 2654 2655 err = hdmi_parse_codec(codec); 2656 if (err < 0) { 2657 generic_spec_free(codec); 2658 return err; 2659 } 2660 2661 generic_hdmi_init_per_pins(codec); 2662 return 0; 2663 } 2664 2665 /* 2666 * generic audio component binding 2667 */ 2668 2669 /* turn on / off the unsol event jack detection dynamically */ 2670 static void reprogram_jack_detect(struct hda_codec *codec, hda_nid_t nid, 2671 int dev_id, bool use_acomp) 2672 { 2673 struct hda_jack_tbl *tbl; 2674 2675 tbl = snd_hda_jack_tbl_get_mst(codec, nid, dev_id); 2676 if (tbl) { 2677 /* clear unsol even if component notifier is used, or re-enable 2678 * if notifier is cleared 2679 */ 2680 unsigned int val = use_acomp ? 0 : (AC_USRSP_EN | tbl->tag); 2681 snd_hda_codec_write_cache(codec, nid, 0, 2682 AC_VERB_SET_UNSOLICITED_ENABLE, val); 2683 } 2684 } 2685 2686 /* set up / clear component notifier dynamically */ 2687 static void generic_acomp_notifier_set(struct drm_audio_component *acomp, 2688 bool use_acomp) 2689 { 2690 struct hdmi_spec *spec; 2691 int i; 2692 2693 spec = container_of(acomp->audio_ops, struct hdmi_spec, drm_audio_ops); 2694 mutex_lock(&spec->bind_lock); 2695 spec->use_acomp_notifier = use_acomp; 2696 spec->codec->relaxed_resume = use_acomp; 2697 spec->codec->bus->keep_power = 0; 2698 /* reprogram each jack detection logic depending on the notifier */ 2699 for (i = 0; i < spec->num_pins; i++) 2700 reprogram_jack_detect(spec->codec, 2701 get_pin(spec, i)->pin_nid, 2702 get_pin(spec, i)->dev_id, 2703 use_acomp); 2704 mutex_unlock(&spec->bind_lock); 2705 } 2706 2707 /* enable / disable the notifier via master bind / unbind */ 2708 static int generic_acomp_master_bind(struct device *dev, 2709 struct drm_audio_component *acomp) 2710 { 2711 generic_acomp_notifier_set(acomp, true); 2712 return 0; 2713 } 2714 2715 static void generic_acomp_master_unbind(struct device *dev, 2716 struct drm_audio_component *acomp) 2717 { 2718 generic_acomp_notifier_set(acomp, false); 2719 } 2720 2721 /* check whether both HD-audio and DRM PCI devices belong to the same bus */ 2722 static int match_bound_vga(struct device *dev, int subtype, void *data) 2723 { 2724 struct hdac_bus *bus = data; 2725 struct pci_dev *pci, *master; 2726 2727 if (!dev_is_pci(dev) || !dev_is_pci(bus->dev)) 2728 return 0; 2729 master = to_pci_dev(bus->dev); 2730 pci = to_pci_dev(dev); 2731 return master->bus == pci->bus; 2732 } 2733 2734 /* audio component notifier for AMD/Nvidia HDMI codecs */ 2735 static void generic_acomp_pin_eld_notify(void *audio_ptr, int port, int dev_id) 2736 { 2737 struct hda_codec *codec = audio_ptr; 2738 struct hdmi_spec *spec = codec->spec; 2739 hda_nid_t pin_nid = spec->port2pin(codec, port); 2740 2741 if (!pin_nid) 2742 return; 2743 if (get_wcaps_type(get_wcaps(codec, pin_nid)) != AC_WID_PIN) 2744 return; 2745 /* skip notification during system suspend (but not in runtime PM); 2746 * the state will be updated at resume 2747 */ 2748 if (codec->core.dev.power.power_state.event == PM_EVENT_SUSPEND) 2749 return; 2750 /* ditto during suspend/resume process itself */ 2751 if (snd_hdac_is_in_pm(&codec->core)) 2752 return; 2753 2754 check_presence_and_report(codec, pin_nid, dev_id); 2755 } 2756 2757 /* set up the private drm_audio_ops from the template */ 2758 static void setup_drm_audio_ops(struct hda_codec *codec, 2759 const struct drm_audio_component_audio_ops *ops) 2760 { 2761 struct hdmi_spec *spec = codec->spec; 2762 2763 spec->drm_audio_ops.audio_ptr = codec; 2764 /* intel_audio_codec_enable() or intel_audio_codec_disable() 2765 * will call pin_eld_notify with using audio_ptr pointer 2766 * We need make sure audio_ptr is really setup 2767 */ 2768 wmb(); 2769 spec->drm_audio_ops.pin2port = ops->pin2port; 2770 spec->drm_audio_ops.pin_eld_notify = ops->pin_eld_notify; 2771 spec->drm_audio_ops.master_bind = ops->master_bind; 2772 spec->drm_audio_ops.master_unbind = ops->master_unbind; 2773 } 2774 2775 /* initialize the generic HDMI audio component */ 2776 static void generic_acomp_init(struct hda_codec *codec, 2777 const struct drm_audio_component_audio_ops *ops, 2778 int (*port2pin)(struct hda_codec *, int)) 2779 { 2780 struct hdmi_spec *spec = codec->spec; 2781 2782 if (!enable_acomp) { 2783 codec_info(codec, "audio component disabled by module option\n"); 2784 return; 2785 } 2786 2787 spec->port2pin = port2pin; 2788 setup_drm_audio_ops(codec, ops); 2789 if (!snd_hdac_acomp_init(&codec->bus->core, &spec->drm_audio_ops, 2790 match_bound_vga, 0)) { 2791 spec->acomp_registered = true; 2792 } 2793 } 2794 2795 /* 2796 * Intel codec parsers and helpers 2797 */ 2798 2799 #define INTEL_GET_VENDOR_VERB 0xf81 2800 #define INTEL_SET_VENDOR_VERB 0x781 2801 #define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */ 2802 #define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */ 2803 2804 static void intel_haswell_enable_all_pins(struct hda_codec *codec, 2805 bool update_tree) 2806 { 2807 unsigned int vendor_param; 2808 struct hdmi_spec *spec = codec->spec; 2809 2810 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0, 2811 INTEL_GET_VENDOR_VERB, 0); 2812 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS) 2813 return; 2814 2815 vendor_param |= INTEL_EN_ALL_PIN_CVTS; 2816 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0, 2817 INTEL_SET_VENDOR_VERB, vendor_param); 2818 if (vendor_param == -1) 2819 return; 2820 2821 if (update_tree) 2822 snd_hda_codec_update_widgets(codec); 2823 } 2824 2825 static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec) 2826 { 2827 unsigned int vendor_param; 2828 struct hdmi_spec *spec = codec->spec; 2829 2830 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0, 2831 INTEL_GET_VENDOR_VERB, 0); 2832 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12) 2833 return; 2834 2835 /* enable DP1.2 mode */ 2836 vendor_param |= INTEL_EN_DP12; 2837 snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB); 2838 snd_hda_codec_write_cache(codec, spec->vendor_nid, 0, 2839 INTEL_SET_VENDOR_VERB, vendor_param); 2840 } 2841 2842 /* Haswell needs to re-issue the vendor-specific verbs before turning to D0. 2843 * Otherwise you may get severe h/w communication errors. 2844 */ 2845 static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg, 2846 unsigned int power_state) 2847 { 2848 if (power_state == AC_PWRST_D0) { 2849 intel_haswell_enable_all_pins(codec, false); 2850 intel_haswell_fixup_enable_dp12(codec); 2851 } 2852 2853 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state); 2854 snd_hda_codec_set_power_to_all(codec, fg, power_state); 2855 } 2856 2857 /* There is a fixed mapping between audio pin node and display port. 2858 * on SNB, IVY, HSW, BSW, SKL, BXT, KBL: 2859 * Pin Widget 5 - PORT B (port = 1 in i915 driver) 2860 * Pin Widget 6 - PORT C (port = 2 in i915 driver) 2861 * Pin Widget 7 - PORT D (port = 3 in i915 driver) 2862 * 2863 * on VLV, ILK: 2864 * Pin Widget 4 - PORT B (port = 1 in i915 driver) 2865 * Pin Widget 5 - PORT C (port = 2 in i915 driver) 2866 * Pin Widget 6 - PORT D (port = 3 in i915 driver) 2867 */ 2868 static int intel_base_nid(struct hda_codec *codec) 2869 { 2870 switch (codec->core.vendor_id) { 2871 case 0x80860054: /* ILK */ 2872 case 0x80862804: /* ILK */ 2873 case 0x80862882: /* VLV */ 2874 return 4; 2875 default: 2876 return 5; 2877 } 2878 } 2879 2880 static int intel_pin2port(void *audio_ptr, int pin_nid) 2881 { 2882 struct hda_codec *codec = audio_ptr; 2883 struct hdmi_spec *spec = codec->spec; 2884 int base_nid, i; 2885 2886 if (!spec->port_num) { 2887 base_nid = intel_base_nid(codec); 2888 if (WARN_ON(pin_nid < base_nid || pin_nid >= base_nid + 3)) 2889 return -1; 2890 return pin_nid - base_nid + 1; 2891 } 2892 2893 /* 2894 * looking for the pin number in the mapping table and return 2895 * the index which indicate the port number 2896 */ 2897 for (i = 0; i < spec->port_num; i++) { 2898 if (pin_nid == spec->port_map[i]) 2899 return i; 2900 } 2901 2902 codec_info(codec, "Can't find the HDMI/DP port for pin NID 0x%x\n", pin_nid); 2903 return -1; 2904 } 2905 2906 static int intel_port2pin(struct hda_codec *codec, int port) 2907 { 2908 struct hdmi_spec *spec = codec->spec; 2909 2910 if (!spec->port_num) { 2911 /* we assume only from port-B to port-D */ 2912 if (port < 1 || port > 3) 2913 return 0; 2914 return port + intel_base_nid(codec) - 1; 2915 } 2916 2917 if (port < 0 || port >= spec->port_num) 2918 return 0; 2919 return spec->port_map[port]; 2920 } 2921 2922 static void intel_pin_eld_notify(void *audio_ptr, int port, int pipe) 2923 { 2924 struct hda_codec *codec = audio_ptr; 2925 int pin_nid; 2926 int dev_id = pipe; 2927 2928 pin_nid = intel_port2pin(codec, port); 2929 if (!pin_nid) 2930 return; 2931 /* skip notification during system suspend (but not in runtime PM); 2932 * the state will be updated at resume 2933 */ 2934 if (codec->core.dev.power.power_state.event == PM_EVENT_SUSPEND) 2935 return; 2936 /* ditto during suspend/resume process itself */ 2937 if (snd_hdac_is_in_pm(&codec->core)) 2938 return; 2939 2940 snd_hdac_i915_set_bclk(&codec->bus->core); 2941 check_presence_and_report(codec, pin_nid, dev_id); 2942 } 2943 2944 static const struct drm_audio_component_audio_ops intel_audio_ops = { 2945 .pin2port = intel_pin2port, 2946 .pin_eld_notify = intel_pin_eld_notify, 2947 }; 2948 2949 /* register i915 component pin_eld_notify callback */ 2950 static void register_i915_notifier(struct hda_codec *codec) 2951 { 2952 struct hdmi_spec *spec = codec->spec; 2953 2954 spec->use_acomp_notifier = true; 2955 spec->port2pin = intel_port2pin; 2956 setup_drm_audio_ops(codec, &intel_audio_ops); 2957 snd_hdac_acomp_register_notifier(&codec->bus->core, 2958 &spec->drm_audio_ops); 2959 /* no need for forcible resume for jack check thanks to notifier */ 2960 codec->relaxed_resume = 1; 2961 } 2962 2963 /* setup_stream ops override for HSW+ */ 2964 static int i915_hsw_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, 2965 hda_nid_t pin_nid, int dev_id, u32 stream_tag, 2966 int format) 2967 { 2968 haswell_verify_D0(codec, cvt_nid, pin_nid); 2969 return hdmi_setup_stream(codec, cvt_nid, pin_nid, dev_id, 2970 stream_tag, format); 2971 } 2972 2973 /* pin_cvt_fixup ops override for HSW+ and VLV+ */ 2974 static void i915_pin_cvt_fixup(struct hda_codec *codec, 2975 struct hdmi_spec_per_pin *per_pin, 2976 hda_nid_t cvt_nid) 2977 { 2978 if (per_pin) { 2979 haswell_verify_D0(codec, per_pin->cvt_nid, per_pin->pin_nid); 2980 snd_hda_set_dev_select(codec, per_pin->pin_nid, 2981 per_pin->dev_id); 2982 intel_verify_pin_cvt_connect(codec, per_pin); 2983 intel_not_share_assigned_cvt(codec, per_pin->pin_nid, 2984 per_pin->dev_id, per_pin->mux_idx); 2985 } else { 2986 intel_not_share_assigned_cvt_nid(codec, 0, 0, cvt_nid); 2987 } 2988 } 2989 2990 /* precondition and allocation for Intel codecs */ 2991 static int alloc_intel_hdmi(struct hda_codec *codec) 2992 { 2993 int err; 2994 2995 /* requires i915 binding */ 2996 if (!codec->bus->core.audio_component) { 2997 codec_info(codec, "No i915 binding for Intel HDMI/DP codec\n"); 2998 /* set probe_id here to prevent generic fallback binding */ 2999 codec->probe_id = HDA_CODEC_ID_SKIP_PROBE; 3000 return -ENODEV; 3001 } 3002 3003 err = alloc_generic_hdmi(codec); 3004 if (err < 0) 3005 return err; 3006 /* no need to handle unsol events */ 3007 codec->patch_ops.unsol_event = NULL; 3008 return 0; 3009 } 3010 3011 /* parse and post-process for Intel codecs */ 3012 static int parse_intel_hdmi(struct hda_codec *codec) 3013 { 3014 int err, retries = 3; 3015 3016 do { 3017 err = hdmi_parse_codec(codec); 3018 } while (err < 0 && retries--); 3019 3020 if (err < 0) { 3021 generic_spec_free(codec); 3022 return err; 3023 } 3024 3025 generic_hdmi_init_per_pins(codec); 3026 register_i915_notifier(codec); 3027 return 0; 3028 } 3029 3030 /* Intel Haswell and onwards; audio component with eld notifier */ 3031 static int intel_hsw_common_init(struct hda_codec *codec, hda_nid_t vendor_nid, 3032 const int *port_map, int port_num, int dev_num, 3033 bool send_silent_stream) 3034 { 3035 struct hdmi_spec *spec; 3036 int err; 3037 3038 err = alloc_intel_hdmi(codec); 3039 if (err < 0) 3040 return err; 3041 spec = codec->spec; 3042 codec->dp_mst = true; 3043 spec->dyn_pcm_assign = true; 3044 spec->vendor_nid = vendor_nid; 3045 spec->port_map = port_map; 3046 spec->port_num = port_num; 3047 spec->intel_hsw_fixup = true; 3048 spec->dev_num = dev_num; 3049 3050 intel_haswell_enable_all_pins(codec, true); 3051 intel_haswell_fixup_enable_dp12(codec); 3052 3053 codec->display_power_control = 1; 3054 3055 codec->patch_ops.set_power_state = haswell_set_power_state; 3056 codec->depop_delay = 0; 3057 codec->auto_runtime_pm = 1; 3058 3059 spec->ops.setup_stream = i915_hsw_setup_stream; 3060 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup; 3061 3062 /* 3063 * Enable silent stream feature, if it is enabled via 3064 * module param or Kconfig option 3065 */ 3066 if (send_silent_stream) 3067 spec->silent_stream_type = SILENT_STREAM_I915; 3068 3069 return parse_intel_hdmi(codec); 3070 } 3071 3072 static int patch_i915_hsw_hdmi(struct hda_codec *codec) 3073 { 3074 return intel_hsw_common_init(codec, 0x08, NULL, 0, 3, 3075 enable_silent_stream); 3076 } 3077 3078 static int patch_i915_glk_hdmi(struct hda_codec *codec) 3079 { 3080 /* 3081 * Silent stream calls audio component .get_power() from 3082 * .pin_eld_notify(). On GLK this will deadlock in i915 due 3083 * to the audio vs. CDCLK workaround. 3084 */ 3085 return intel_hsw_common_init(codec, 0x0b, NULL, 0, 3, false); 3086 } 3087 3088 static int patch_i915_icl_hdmi(struct hda_codec *codec) 3089 { 3090 /* 3091 * pin to port mapping table where the value indicate the pin number and 3092 * the index indicate the port number. 3093 */ 3094 static const int map[] = {0x0, 0x4, 0x6, 0x8, 0xa, 0xb}; 3095 3096 return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map), 3, 3097 enable_silent_stream); 3098 } 3099 3100 static int patch_i915_tgl_hdmi(struct hda_codec *codec) 3101 { 3102 /* 3103 * pin to port mapping table where the value indicate the pin number and 3104 * the index indicate the port number. 3105 */ 3106 static const int map[] = {0x4, 0x6, 0x8, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf}; 3107 int ret; 3108 3109 ret = intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map), 4, 3110 enable_silent_stream); 3111 if (!ret) { 3112 struct hdmi_spec *spec = codec->spec; 3113 3114 spec->dyn_pcm_no_legacy = true; 3115 } 3116 3117 return ret; 3118 } 3119 3120 static int patch_i915_adlp_hdmi(struct hda_codec *codec) 3121 { 3122 struct hdmi_spec *spec; 3123 int res; 3124 3125 res = patch_i915_tgl_hdmi(codec); 3126 if (!res) { 3127 spec = codec->spec; 3128 3129 if (spec->silent_stream_type) 3130 spec->silent_stream_type = SILENT_STREAM_KAE; 3131 } 3132 3133 return res; 3134 } 3135 3136 /* Intel Baytrail and Braswell; with eld notifier */ 3137 static int patch_i915_byt_hdmi(struct hda_codec *codec) 3138 { 3139 struct hdmi_spec *spec; 3140 int err; 3141 3142 err = alloc_intel_hdmi(codec); 3143 if (err < 0) 3144 return err; 3145 spec = codec->spec; 3146 3147 /* For Valleyview/Cherryview, only the display codec is in the display 3148 * power well and can use link_power ops to request/release the power. 3149 */ 3150 codec->display_power_control = 1; 3151 3152 codec->depop_delay = 0; 3153 codec->auto_runtime_pm = 1; 3154 3155 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup; 3156 3157 return parse_intel_hdmi(codec); 3158 } 3159 3160 /* Intel IronLake, SandyBridge and IvyBridge; with eld notifier */ 3161 static int patch_i915_cpt_hdmi(struct hda_codec *codec) 3162 { 3163 int err; 3164 3165 err = alloc_intel_hdmi(codec); 3166 if (err < 0) 3167 return err; 3168 return parse_intel_hdmi(codec); 3169 } 3170 3171 /* 3172 * Shared non-generic implementations 3173 */ 3174 3175 static int simple_playback_build_pcms(struct hda_codec *codec) 3176 { 3177 struct hdmi_spec *spec = codec->spec; 3178 struct hda_pcm *info; 3179 unsigned int chans; 3180 struct hda_pcm_stream *pstr; 3181 struct hdmi_spec_per_cvt *per_cvt; 3182 3183 per_cvt = get_cvt(spec, 0); 3184 chans = get_wcaps(codec, per_cvt->cvt_nid); 3185 chans = get_wcaps_channels(chans); 3186 3187 info = snd_hda_codec_pcm_new(codec, "HDMI 0"); 3188 if (!info) 3189 return -ENOMEM; 3190 spec->pcm_rec[0].pcm = info; 3191 info->pcm_type = HDA_PCM_TYPE_HDMI; 3192 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK]; 3193 *pstr = spec->pcm_playback; 3194 pstr->nid = per_cvt->cvt_nid; 3195 if (pstr->channels_max <= 2 && chans && chans <= 16) 3196 pstr->channels_max = chans; 3197 3198 return 0; 3199 } 3200 3201 /* unsolicited event for jack sensing */ 3202 static void simple_hdmi_unsol_event(struct hda_codec *codec, 3203 unsigned int res) 3204 { 3205 snd_hda_jack_set_dirty_all(codec); 3206 snd_hda_jack_report_sync(codec); 3207 } 3208 3209 /* generic_hdmi_build_jack can be used for simple_hdmi, too, 3210 * as long as spec->pins[] is set correctly 3211 */ 3212 #define simple_hdmi_build_jack generic_hdmi_build_jack 3213 3214 static int simple_playback_build_controls(struct hda_codec *codec) 3215 { 3216 struct hdmi_spec *spec = codec->spec; 3217 struct hdmi_spec_per_cvt *per_cvt; 3218 int err; 3219 3220 per_cvt = get_cvt(spec, 0); 3221 err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid, 3222 per_cvt->cvt_nid, 3223 HDA_PCM_TYPE_HDMI); 3224 if (err < 0) 3225 return err; 3226 return simple_hdmi_build_jack(codec, 0); 3227 } 3228 3229 static int simple_playback_init(struct hda_codec *codec) 3230 { 3231 struct hdmi_spec *spec = codec->spec; 3232 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0); 3233 hda_nid_t pin = per_pin->pin_nid; 3234 3235 snd_hda_codec_write(codec, pin, 0, 3236 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT); 3237 /* some codecs require to unmute the pin */ 3238 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP) 3239 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE, 3240 AMP_OUT_UNMUTE); 3241 snd_hda_jack_detect_enable(codec, pin, per_pin->dev_id); 3242 return 0; 3243 } 3244 3245 static void simple_playback_free(struct hda_codec *codec) 3246 { 3247 struct hdmi_spec *spec = codec->spec; 3248 3249 hdmi_array_free(spec); 3250 kfree(spec); 3251 } 3252 3253 /* 3254 * Nvidia specific implementations 3255 */ 3256 3257 #define Nv_VERB_SET_Channel_Allocation 0xF79 3258 #define Nv_VERB_SET_Info_Frame_Checksum 0xF7A 3259 #define Nv_VERB_SET_Audio_Protection_On 0xF98 3260 #define Nv_VERB_SET_Audio_Protection_Off 0xF99 3261 3262 #define nvhdmi_master_con_nid_7x 0x04 3263 #define nvhdmi_master_pin_nid_7x 0x05 3264 3265 static const hda_nid_t nvhdmi_con_nids_7x[4] = { 3266 /*front, rear, clfe, rear_surr */ 3267 0x6, 0x8, 0xa, 0xc, 3268 }; 3269 3270 static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = { 3271 /* set audio protect on */ 3272 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1}, 3273 /* enable digital output on pin widget */ 3274 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3275 {} /* terminator */ 3276 }; 3277 3278 static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = { 3279 /* set audio protect on */ 3280 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1}, 3281 /* enable digital output on pin widget */ 3282 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3283 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3284 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3285 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3286 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3287 {} /* terminator */ 3288 }; 3289 3290 #ifdef LIMITED_RATE_FMT_SUPPORT 3291 /* support only the safe format and rate */ 3292 #define SUPPORTED_RATES SNDRV_PCM_RATE_48000 3293 #define SUPPORTED_MAXBPS 16 3294 #define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE 3295 #else 3296 /* support all rates and formats */ 3297 #define SUPPORTED_RATES \ 3298 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\ 3299 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\ 3300 SNDRV_PCM_RATE_192000) 3301 #define SUPPORTED_MAXBPS 24 3302 #define SUPPORTED_FORMATS \ 3303 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE) 3304 #endif 3305 3306 static int nvhdmi_7x_init_2ch(struct hda_codec *codec) 3307 { 3308 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch); 3309 return 0; 3310 } 3311 3312 static int nvhdmi_7x_init_8ch(struct hda_codec *codec) 3313 { 3314 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch); 3315 return 0; 3316 } 3317 3318 static const unsigned int channels_2_6_8[] = { 3319 2, 6, 8 3320 }; 3321 3322 static const unsigned int channels_2_8[] = { 3323 2, 8 3324 }; 3325 3326 static const struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = { 3327 .count = ARRAY_SIZE(channels_2_6_8), 3328 .list = channels_2_6_8, 3329 .mask = 0, 3330 }; 3331 3332 static const struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = { 3333 .count = ARRAY_SIZE(channels_2_8), 3334 .list = channels_2_8, 3335 .mask = 0, 3336 }; 3337 3338 static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo, 3339 struct hda_codec *codec, 3340 struct snd_pcm_substream *substream) 3341 { 3342 struct hdmi_spec *spec = codec->spec; 3343 const struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL; 3344 3345 switch (codec->preset->vendor_id) { 3346 case 0x10de0002: 3347 case 0x10de0003: 3348 case 0x10de0005: 3349 case 0x10de0006: 3350 hw_constraints_channels = &hw_constraints_2_8_channels; 3351 break; 3352 case 0x10de0007: 3353 hw_constraints_channels = &hw_constraints_2_6_8_channels; 3354 break; 3355 default: 3356 break; 3357 } 3358 3359 if (hw_constraints_channels != NULL) { 3360 snd_pcm_hw_constraint_list(substream->runtime, 0, 3361 SNDRV_PCM_HW_PARAM_CHANNELS, 3362 hw_constraints_channels); 3363 } else { 3364 snd_pcm_hw_constraint_step(substream->runtime, 0, 3365 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 3366 } 3367 3368 return snd_hda_multi_out_dig_open(codec, &spec->multiout); 3369 } 3370 3371 static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo, 3372 struct hda_codec *codec, 3373 struct snd_pcm_substream *substream) 3374 { 3375 struct hdmi_spec *spec = codec->spec; 3376 return snd_hda_multi_out_dig_close(codec, &spec->multiout); 3377 } 3378 3379 static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 3380 struct hda_codec *codec, 3381 unsigned int stream_tag, 3382 unsigned int format, 3383 struct snd_pcm_substream *substream) 3384 { 3385 struct hdmi_spec *spec = codec->spec; 3386 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout, 3387 stream_tag, format, substream); 3388 } 3389 3390 static const struct hda_pcm_stream simple_pcm_playback = { 3391 .substreams = 1, 3392 .channels_min = 2, 3393 .channels_max = 2, 3394 .ops = { 3395 .open = simple_playback_pcm_open, 3396 .close = simple_playback_pcm_close, 3397 .prepare = simple_playback_pcm_prepare 3398 }, 3399 }; 3400 3401 static const struct hda_codec_ops simple_hdmi_patch_ops = { 3402 .build_controls = simple_playback_build_controls, 3403 .build_pcms = simple_playback_build_pcms, 3404 .init = simple_playback_init, 3405 .free = simple_playback_free, 3406 .unsol_event = simple_hdmi_unsol_event, 3407 }; 3408 3409 static int patch_simple_hdmi(struct hda_codec *codec, 3410 hda_nid_t cvt_nid, hda_nid_t pin_nid) 3411 { 3412 struct hdmi_spec *spec; 3413 struct hdmi_spec_per_cvt *per_cvt; 3414 struct hdmi_spec_per_pin *per_pin; 3415 3416 spec = kzalloc(sizeof(*spec), GFP_KERNEL); 3417 if (!spec) 3418 return -ENOMEM; 3419 3420 spec->codec = codec; 3421 codec->spec = spec; 3422 hdmi_array_init(spec, 1); 3423 3424 spec->multiout.num_dacs = 0; /* no analog */ 3425 spec->multiout.max_channels = 2; 3426 spec->multiout.dig_out_nid = cvt_nid; 3427 spec->num_cvts = 1; 3428 spec->num_pins = 1; 3429 per_pin = snd_array_new(&spec->pins); 3430 per_cvt = snd_array_new(&spec->cvts); 3431 if (!per_pin || !per_cvt) { 3432 simple_playback_free(codec); 3433 return -ENOMEM; 3434 } 3435 per_cvt->cvt_nid = cvt_nid; 3436 per_pin->pin_nid = pin_nid; 3437 spec->pcm_playback = simple_pcm_playback; 3438 3439 codec->patch_ops = simple_hdmi_patch_ops; 3440 3441 return 0; 3442 } 3443 3444 static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec, 3445 int channels) 3446 { 3447 unsigned int chanmask; 3448 int chan = channels ? (channels - 1) : 1; 3449 3450 switch (channels) { 3451 default: 3452 case 0: 3453 case 2: 3454 chanmask = 0x00; 3455 break; 3456 case 4: 3457 chanmask = 0x08; 3458 break; 3459 case 6: 3460 chanmask = 0x0b; 3461 break; 3462 case 8: 3463 chanmask = 0x13; 3464 break; 3465 } 3466 3467 /* Set the audio infoframe channel allocation and checksum fields. The 3468 * channel count is computed implicitly by the hardware. */ 3469 snd_hda_codec_write(codec, 0x1, 0, 3470 Nv_VERB_SET_Channel_Allocation, chanmask); 3471 3472 snd_hda_codec_write(codec, 0x1, 0, 3473 Nv_VERB_SET_Info_Frame_Checksum, 3474 (0x71 - chan - chanmask)); 3475 } 3476 3477 static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo, 3478 struct hda_codec *codec, 3479 struct snd_pcm_substream *substream) 3480 { 3481 struct hdmi_spec *spec = codec->spec; 3482 int i; 3483 3484 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 3485 0, AC_VERB_SET_CHANNEL_STREAMID, 0); 3486 for (i = 0; i < 4; i++) { 3487 /* set the stream id */ 3488 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0, 3489 AC_VERB_SET_CHANNEL_STREAMID, 0); 3490 /* set the stream format */ 3491 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0, 3492 AC_VERB_SET_STREAM_FORMAT, 0); 3493 } 3494 3495 /* The audio hardware sends a channel count of 0x7 (8ch) when all the 3496 * streams are disabled. */ 3497 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8); 3498 3499 return snd_hda_multi_out_dig_close(codec, &spec->multiout); 3500 } 3501 3502 static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo, 3503 struct hda_codec *codec, 3504 unsigned int stream_tag, 3505 unsigned int format, 3506 struct snd_pcm_substream *substream) 3507 { 3508 int chs; 3509 unsigned int dataDCC2, channel_id; 3510 int i; 3511 struct hdmi_spec *spec = codec->spec; 3512 struct hda_spdif_out *spdif; 3513 struct hdmi_spec_per_cvt *per_cvt; 3514 3515 mutex_lock(&codec->spdif_mutex); 3516 per_cvt = get_cvt(spec, 0); 3517 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid); 3518 3519 chs = substream->runtime->channels; 3520 3521 dataDCC2 = 0x2; 3522 3523 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */ 3524 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) 3525 snd_hda_codec_write(codec, 3526 nvhdmi_master_con_nid_7x, 3527 0, 3528 AC_VERB_SET_DIGI_CONVERT_1, 3529 spdif->ctls & ~AC_DIG1_ENABLE & 0xff); 3530 3531 /* set the stream id */ 3532 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0, 3533 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0); 3534 3535 /* set the stream format */ 3536 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0, 3537 AC_VERB_SET_STREAM_FORMAT, format); 3538 3539 /* turn on again (if needed) */ 3540 /* enable and set the channel status audio/data flag */ 3541 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) { 3542 snd_hda_codec_write(codec, 3543 nvhdmi_master_con_nid_7x, 3544 0, 3545 AC_VERB_SET_DIGI_CONVERT_1, 3546 spdif->ctls & 0xff); 3547 snd_hda_codec_write(codec, 3548 nvhdmi_master_con_nid_7x, 3549 0, 3550 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2); 3551 } 3552 3553 for (i = 0; i < 4; i++) { 3554 if (chs == 2) 3555 channel_id = 0; 3556 else 3557 channel_id = i * 2; 3558 3559 /* turn off SPDIF once; 3560 *otherwise the IEC958 bits won't be updated 3561 */ 3562 if (codec->spdif_status_reset && 3563 (spdif->ctls & AC_DIG1_ENABLE)) 3564 snd_hda_codec_write(codec, 3565 nvhdmi_con_nids_7x[i], 3566 0, 3567 AC_VERB_SET_DIGI_CONVERT_1, 3568 spdif->ctls & ~AC_DIG1_ENABLE & 0xff); 3569 /* set the stream id */ 3570 snd_hda_codec_write(codec, 3571 nvhdmi_con_nids_7x[i], 3572 0, 3573 AC_VERB_SET_CHANNEL_STREAMID, 3574 (stream_tag << 4) | channel_id); 3575 /* set the stream format */ 3576 snd_hda_codec_write(codec, 3577 nvhdmi_con_nids_7x[i], 3578 0, 3579 AC_VERB_SET_STREAM_FORMAT, 3580 format); 3581 /* turn on again (if needed) */ 3582 /* enable and set the channel status audio/data flag */ 3583 if (codec->spdif_status_reset && 3584 (spdif->ctls & AC_DIG1_ENABLE)) { 3585 snd_hda_codec_write(codec, 3586 nvhdmi_con_nids_7x[i], 3587 0, 3588 AC_VERB_SET_DIGI_CONVERT_1, 3589 spdif->ctls & 0xff); 3590 snd_hda_codec_write(codec, 3591 nvhdmi_con_nids_7x[i], 3592 0, 3593 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2); 3594 } 3595 } 3596 3597 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs); 3598 3599 mutex_unlock(&codec->spdif_mutex); 3600 return 0; 3601 } 3602 3603 static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = { 3604 .substreams = 1, 3605 .channels_min = 2, 3606 .channels_max = 8, 3607 .nid = nvhdmi_master_con_nid_7x, 3608 .rates = SUPPORTED_RATES, 3609 .maxbps = SUPPORTED_MAXBPS, 3610 .formats = SUPPORTED_FORMATS, 3611 .ops = { 3612 .open = simple_playback_pcm_open, 3613 .close = nvhdmi_8ch_7x_pcm_close, 3614 .prepare = nvhdmi_8ch_7x_pcm_prepare 3615 }, 3616 }; 3617 3618 static int patch_nvhdmi_2ch(struct hda_codec *codec) 3619 { 3620 struct hdmi_spec *spec; 3621 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x, 3622 nvhdmi_master_pin_nid_7x); 3623 if (err < 0) 3624 return err; 3625 3626 codec->patch_ops.init = nvhdmi_7x_init_2ch; 3627 /* override the PCM rates, etc, as the codec doesn't give full list */ 3628 spec = codec->spec; 3629 spec->pcm_playback.rates = SUPPORTED_RATES; 3630 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS; 3631 spec->pcm_playback.formats = SUPPORTED_FORMATS; 3632 spec->nv_dp_workaround = true; 3633 return 0; 3634 } 3635 3636 static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec) 3637 { 3638 struct hdmi_spec *spec = codec->spec; 3639 int err = simple_playback_build_pcms(codec); 3640 if (!err) { 3641 struct hda_pcm *info = get_pcm_rec(spec, 0); 3642 info->own_chmap = true; 3643 } 3644 return err; 3645 } 3646 3647 static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec) 3648 { 3649 struct hdmi_spec *spec = codec->spec; 3650 struct hda_pcm *info; 3651 struct snd_pcm_chmap *chmap; 3652 int err; 3653 3654 err = simple_playback_build_controls(codec); 3655 if (err < 0) 3656 return err; 3657 3658 /* add channel maps */ 3659 info = get_pcm_rec(spec, 0); 3660 err = snd_pcm_add_chmap_ctls(info->pcm, 3661 SNDRV_PCM_STREAM_PLAYBACK, 3662 snd_pcm_alt_chmaps, 8, 0, &chmap); 3663 if (err < 0) 3664 return err; 3665 switch (codec->preset->vendor_id) { 3666 case 0x10de0002: 3667 case 0x10de0003: 3668 case 0x10de0005: 3669 case 0x10de0006: 3670 chmap->channel_mask = (1U << 2) | (1U << 8); 3671 break; 3672 case 0x10de0007: 3673 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8); 3674 } 3675 return 0; 3676 } 3677 3678 static int patch_nvhdmi_8ch_7x(struct hda_codec *codec) 3679 { 3680 struct hdmi_spec *spec; 3681 int err = patch_nvhdmi_2ch(codec); 3682 if (err < 0) 3683 return err; 3684 spec = codec->spec; 3685 spec->multiout.max_channels = 8; 3686 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x; 3687 codec->patch_ops.init = nvhdmi_7x_init_8ch; 3688 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms; 3689 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls; 3690 3691 /* Initialize the audio infoframe channel mask and checksum to something 3692 * valid */ 3693 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8); 3694 3695 return 0; 3696 } 3697 3698 /* 3699 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on: 3700 * - 0x10de0015 3701 * - 0x10de0040 3702 */ 3703 static int nvhdmi_chmap_cea_alloc_validate_get_type(struct hdac_chmap *chmap, 3704 struct hdac_cea_channel_speaker_allocation *cap, int channels) 3705 { 3706 if (cap->ca_index == 0x00 && channels == 2) 3707 return SNDRV_CTL_TLVT_CHMAP_FIXED; 3708 3709 /* If the speaker allocation matches the channel count, it is OK. */ 3710 if (cap->channels != channels) 3711 return -1; 3712 3713 /* all channels are remappable freely */ 3714 return SNDRV_CTL_TLVT_CHMAP_VAR; 3715 } 3716 3717 static int nvhdmi_chmap_validate(struct hdac_chmap *chmap, 3718 int ca, int chs, unsigned char *map) 3719 { 3720 if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR)) 3721 return -EINVAL; 3722 3723 return 0; 3724 } 3725 3726 /* map from pin NID to port; port is 0-based */ 3727 /* for Nvidia: assume widget NID starting from 4, with step 1 (4, 5, 6, ...) */ 3728 static int nvhdmi_pin2port(void *audio_ptr, int pin_nid) 3729 { 3730 return pin_nid - 4; 3731 } 3732 3733 /* reverse-map from port to pin NID: see above */ 3734 static int nvhdmi_port2pin(struct hda_codec *codec, int port) 3735 { 3736 return port + 4; 3737 } 3738 3739 static const struct drm_audio_component_audio_ops nvhdmi_audio_ops = { 3740 .pin2port = nvhdmi_pin2port, 3741 .pin_eld_notify = generic_acomp_pin_eld_notify, 3742 .master_bind = generic_acomp_master_bind, 3743 .master_unbind = generic_acomp_master_unbind, 3744 }; 3745 3746 static int patch_nvhdmi(struct hda_codec *codec) 3747 { 3748 struct hdmi_spec *spec; 3749 int err; 3750 3751 err = alloc_generic_hdmi(codec); 3752 if (err < 0) 3753 return err; 3754 codec->dp_mst = true; 3755 3756 spec = codec->spec; 3757 spec->dyn_pcm_assign = true; 3758 3759 err = hdmi_parse_codec(codec); 3760 if (err < 0) { 3761 generic_spec_free(codec); 3762 return err; 3763 } 3764 3765 generic_hdmi_init_per_pins(codec); 3766 3767 spec->dyn_pin_out = true; 3768 3769 spec->chmap.ops.chmap_cea_alloc_validate_get_type = 3770 nvhdmi_chmap_cea_alloc_validate_get_type; 3771 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate; 3772 spec->nv_dp_workaround = true; 3773 3774 codec->link_down_at_suspend = 1; 3775 3776 generic_acomp_init(codec, &nvhdmi_audio_ops, nvhdmi_port2pin); 3777 3778 return 0; 3779 } 3780 3781 static int patch_nvhdmi_legacy(struct hda_codec *codec) 3782 { 3783 struct hdmi_spec *spec; 3784 int err; 3785 3786 err = patch_generic_hdmi(codec); 3787 if (err) 3788 return err; 3789 3790 spec = codec->spec; 3791 spec->dyn_pin_out = true; 3792 3793 spec->chmap.ops.chmap_cea_alloc_validate_get_type = 3794 nvhdmi_chmap_cea_alloc_validate_get_type; 3795 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate; 3796 spec->nv_dp_workaround = true; 3797 3798 codec->link_down_at_suspend = 1; 3799 3800 return 0; 3801 } 3802 3803 /* 3804 * The HDA codec on NVIDIA Tegra contains two scratch registers that are 3805 * accessed using vendor-defined verbs. These registers can be used for 3806 * interoperability between the HDA and HDMI drivers. 3807 */ 3808 3809 /* Audio Function Group node */ 3810 #define NVIDIA_AFG_NID 0x01 3811 3812 /* 3813 * The SCRATCH0 register is used to notify the HDMI codec of changes in audio 3814 * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to 3815 * be raised in the HDMI codec. The remainder of the bits is arbitrary. This 3816 * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an 3817 * additional bit (at position 30) to signal the validity of the format. 3818 * 3819 * | 31 | 30 | 29 16 | 15 0 | 3820 * +---------+-------+--------+--------+ 3821 * | TRIGGER | VALID | UNUSED | FORMAT | 3822 * +-----------------------------------| 3823 * 3824 * Note that for the trigger bit to take effect it needs to change value 3825 * (i.e. it needs to be toggled). The trigger bit is not applicable from 3826 * TEGRA234 chip onwards, as new verb id 0xf80 will be used for interrupt 3827 * trigger to hdmi. 3828 */ 3829 #define NVIDIA_SET_HOST_INTR 0xf80 3830 #define NVIDIA_GET_SCRATCH0 0xfa6 3831 #define NVIDIA_SET_SCRATCH0_BYTE0 0xfa7 3832 #define NVIDIA_SET_SCRATCH0_BYTE1 0xfa8 3833 #define NVIDIA_SET_SCRATCH0_BYTE2 0xfa9 3834 #define NVIDIA_SET_SCRATCH0_BYTE3 0xfaa 3835 #define NVIDIA_SCRATCH_TRIGGER (1 << 7) 3836 #define NVIDIA_SCRATCH_VALID (1 << 6) 3837 3838 #define NVIDIA_GET_SCRATCH1 0xfab 3839 #define NVIDIA_SET_SCRATCH1_BYTE0 0xfac 3840 #define NVIDIA_SET_SCRATCH1_BYTE1 0xfad 3841 #define NVIDIA_SET_SCRATCH1_BYTE2 0xfae 3842 #define NVIDIA_SET_SCRATCH1_BYTE3 0xfaf 3843 3844 /* 3845 * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0, 3846 * the format is invalidated so that the HDMI codec can be disabled. 3847 */ 3848 static void tegra_hdmi_set_format(struct hda_codec *codec, 3849 hda_nid_t cvt_nid, 3850 unsigned int format) 3851 { 3852 unsigned int value; 3853 unsigned int nid = NVIDIA_AFG_NID; 3854 struct hdmi_spec *spec = codec->spec; 3855 3856 /* 3857 * Tegra HDA codec design from TEGRA234 chip onwards support DP MST. 3858 * This resulted in moving scratch registers from audio function 3859 * group to converter widget context. So CVT NID should be used for 3860 * scratch register read/write for DP MST supported Tegra HDA codec. 3861 */ 3862 if (codec->dp_mst) 3863 nid = cvt_nid; 3864 3865 /* bits [31:30] contain the trigger and valid bits */ 3866 value = snd_hda_codec_read(codec, nid, 0, 3867 NVIDIA_GET_SCRATCH0, 0); 3868 value = (value >> 24) & 0xff; 3869 3870 /* bits [15:0] are used to store the HDA format */ 3871 snd_hda_codec_write(codec, nid, 0, 3872 NVIDIA_SET_SCRATCH0_BYTE0, 3873 (format >> 0) & 0xff); 3874 snd_hda_codec_write(codec, nid, 0, 3875 NVIDIA_SET_SCRATCH0_BYTE1, 3876 (format >> 8) & 0xff); 3877 3878 /* bits [16:24] are unused */ 3879 snd_hda_codec_write(codec, nid, 0, 3880 NVIDIA_SET_SCRATCH0_BYTE2, 0); 3881 3882 /* 3883 * Bit 30 signals that the data is valid and hence that HDMI audio can 3884 * be enabled. 3885 */ 3886 if (format == 0) 3887 value &= ~NVIDIA_SCRATCH_VALID; 3888 else 3889 value |= NVIDIA_SCRATCH_VALID; 3890 3891 if (spec->hdmi_intr_trig_ctrl) { 3892 /* 3893 * For Tegra HDA Codec design from TEGRA234 onwards, the 3894 * Interrupt to hdmi driver is triggered by writing 3895 * non-zero values to verb 0xF80 instead of 31st bit of 3896 * scratch register. 3897 */ 3898 snd_hda_codec_write(codec, nid, 0, 3899 NVIDIA_SET_SCRATCH0_BYTE3, value); 3900 snd_hda_codec_write(codec, nid, 0, 3901 NVIDIA_SET_HOST_INTR, 0x1); 3902 } else { 3903 /* 3904 * Whenever the 31st trigger bit is toggled, an interrupt is raised 3905 * in the HDMI codec. The HDMI driver will use that as trigger 3906 * to update its configuration. 3907 */ 3908 value ^= NVIDIA_SCRATCH_TRIGGER; 3909 3910 snd_hda_codec_write(codec, nid, 0, 3911 NVIDIA_SET_SCRATCH0_BYTE3, value); 3912 } 3913 } 3914 3915 static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo, 3916 struct hda_codec *codec, 3917 unsigned int stream_tag, 3918 unsigned int format, 3919 struct snd_pcm_substream *substream) 3920 { 3921 int err; 3922 3923 err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag, 3924 format, substream); 3925 if (err < 0) 3926 return err; 3927 3928 /* notify the HDMI codec of the format change */ 3929 tegra_hdmi_set_format(codec, hinfo->nid, format); 3930 3931 return 0; 3932 } 3933 3934 static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo, 3935 struct hda_codec *codec, 3936 struct snd_pcm_substream *substream) 3937 { 3938 /* invalidate the format in the HDMI codec */ 3939 tegra_hdmi_set_format(codec, hinfo->nid, 0); 3940 3941 return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream); 3942 } 3943 3944 static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type) 3945 { 3946 struct hdmi_spec *spec = codec->spec; 3947 unsigned int i; 3948 3949 for (i = 0; i < spec->num_pins; i++) { 3950 struct hda_pcm *pcm = get_pcm_rec(spec, i); 3951 3952 if (pcm->pcm_type == type) 3953 return pcm; 3954 } 3955 3956 return NULL; 3957 } 3958 3959 static int tegra_hdmi_build_pcms(struct hda_codec *codec) 3960 { 3961 struct hda_pcm_stream *stream; 3962 struct hda_pcm *pcm; 3963 int err; 3964 3965 err = generic_hdmi_build_pcms(codec); 3966 if (err < 0) 3967 return err; 3968 3969 pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI); 3970 if (!pcm) 3971 return -ENODEV; 3972 3973 /* 3974 * Override ->prepare() and ->cleanup() operations to notify the HDMI 3975 * codec about format changes. 3976 */ 3977 stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK]; 3978 stream->ops.prepare = tegra_hdmi_pcm_prepare; 3979 stream->ops.cleanup = tegra_hdmi_pcm_cleanup; 3980 3981 return 0; 3982 } 3983 3984 static int tegra_hdmi_init(struct hda_codec *codec) 3985 { 3986 struct hdmi_spec *spec = codec->spec; 3987 int i, err; 3988 3989 err = hdmi_parse_codec(codec); 3990 if (err < 0) { 3991 generic_spec_free(codec); 3992 return err; 3993 } 3994 3995 for (i = 0; i < spec->num_cvts; i++) 3996 snd_hda_codec_write(codec, spec->cvt_nids[i], 0, 3997 AC_VERB_SET_DIGI_CONVERT_1, 3998 AC_DIG1_ENABLE); 3999 4000 generic_hdmi_init_per_pins(codec); 4001 4002 codec->depop_delay = 10; 4003 codec->patch_ops.build_pcms = tegra_hdmi_build_pcms; 4004 spec->chmap.ops.chmap_cea_alloc_validate_get_type = 4005 nvhdmi_chmap_cea_alloc_validate_get_type; 4006 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate; 4007 4008 spec->chmap.ops.chmap_cea_alloc_validate_get_type = 4009 nvhdmi_chmap_cea_alloc_validate_get_type; 4010 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate; 4011 spec->nv_dp_workaround = true; 4012 4013 return 0; 4014 } 4015 4016 static int patch_tegra_hdmi(struct hda_codec *codec) 4017 { 4018 int err; 4019 4020 err = alloc_generic_hdmi(codec); 4021 if (err < 0) 4022 return err; 4023 4024 return tegra_hdmi_init(codec); 4025 } 4026 4027 static int patch_tegra234_hdmi(struct hda_codec *codec) 4028 { 4029 struct hdmi_spec *spec; 4030 int err; 4031 4032 err = alloc_generic_hdmi(codec); 4033 if (err < 0) 4034 return err; 4035 4036 codec->dp_mst = true; 4037 codec->mst_no_extra_pcms = true; 4038 spec = codec->spec; 4039 spec->dyn_pin_out = true; 4040 spec->dyn_pcm_assign = true; 4041 spec->hdmi_intr_trig_ctrl = true; 4042 4043 return tegra_hdmi_init(codec); 4044 } 4045 4046 /* 4047 * ATI/AMD-specific implementations 4048 */ 4049 4050 #define is_amdhdmi_rev3_or_later(codec) \ 4051 ((codec)->core.vendor_id == 0x1002aa01 && \ 4052 ((codec)->core.revision_id & 0xff00) >= 0x0300) 4053 #define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec) 4054 4055 /* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */ 4056 #define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771 4057 #define ATI_VERB_SET_DOWNMIX_INFO 0x772 4058 #define ATI_VERB_SET_MULTICHANNEL_01 0x777 4059 #define ATI_VERB_SET_MULTICHANNEL_23 0x778 4060 #define ATI_VERB_SET_MULTICHANNEL_45 0x779 4061 #define ATI_VERB_SET_MULTICHANNEL_67 0x77a 4062 #define ATI_VERB_SET_HBR_CONTROL 0x77c 4063 #define ATI_VERB_SET_MULTICHANNEL_1 0x785 4064 #define ATI_VERB_SET_MULTICHANNEL_3 0x786 4065 #define ATI_VERB_SET_MULTICHANNEL_5 0x787 4066 #define ATI_VERB_SET_MULTICHANNEL_7 0x788 4067 #define ATI_VERB_SET_MULTICHANNEL_MODE 0x789 4068 #define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71 4069 #define ATI_VERB_GET_DOWNMIX_INFO 0xf72 4070 #define ATI_VERB_GET_MULTICHANNEL_01 0xf77 4071 #define ATI_VERB_GET_MULTICHANNEL_23 0xf78 4072 #define ATI_VERB_GET_MULTICHANNEL_45 0xf79 4073 #define ATI_VERB_GET_MULTICHANNEL_67 0xf7a 4074 #define ATI_VERB_GET_HBR_CONTROL 0xf7c 4075 #define ATI_VERB_GET_MULTICHANNEL_1 0xf85 4076 #define ATI_VERB_GET_MULTICHANNEL_3 0xf86 4077 #define ATI_VERB_GET_MULTICHANNEL_5 0xf87 4078 #define ATI_VERB_GET_MULTICHANNEL_7 0xf88 4079 #define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89 4080 4081 /* AMD specific HDA cvt verbs */ 4082 #define ATI_VERB_SET_RAMP_RATE 0x770 4083 #define ATI_VERB_GET_RAMP_RATE 0xf70 4084 4085 #define ATI_OUT_ENABLE 0x1 4086 4087 #define ATI_MULTICHANNEL_MODE_PAIRED 0 4088 #define ATI_MULTICHANNEL_MODE_SINGLE 1 4089 4090 #define ATI_HBR_CAPABLE 0x01 4091 #define ATI_HBR_ENABLE 0x10 4092 4093 static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid, 4094 int dev_id, unsigned char *buf, int *eld_size) 4095 { 4096 WARN_ON(dev_id != 0); 4097 /* call hda_eld.c ATI/AMD-specific function */ 4098 return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size, 4099 is_amdhdmi_rev3_or_later(codec)); 4100 } 4101 4102 static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, 4103 hda_nid_t pin_nid, int dev_id, int ca, 4104 int active_channels, int conn_type) 4105 { 4106 WARN_ON(dev_id != 0); 4107 snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca); 4108 } 4109 4110 static int atihdmi_paired_swap_fc_lfe(int pos) 4111 { 4112 /* 4113 * ATI/AMD have automatic FC/LFE swap built-in 4114 * when in pairwise mapping mode. 4115 */ 4116 4117 switch (pos) { 4118 /* see channel_allocations[].speakers[] */ 4119 case 2: return 3; 4120 case 3: return 2; 4121 default: break; 4122 } 4123 4124 return pos; 4125 } 4126 4127 static int atihdmi_paired_chmap_validate(struct hdac_chmap *chmap, 4128 int ca, int chs, unsigned char *map) 4129 { 4130 struct hdac_cea_channel_speaker_allocation *cap; 4131 int i, j; 4132 4133 /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */ 4134 4135 cap = snd_hdac_get_ch_alloc_from_ca(ca); 4136 for (i = 0; i < chs; ++i) { 4137 int mask = snd_hdac_chmap_to_spk_mask(map[i]); 4138 bool ok = false; 4139 bool companion_ok = false; 4140 4141 if (!mask) 4142 continue; 4143 4144 for (j = 0 + i % 2; j < 8; j += 2) { 4145 int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j); 4146 if (cap->speakers[chan_idx] == mask) { 4147 /* channel is in a supported position */ 4148 ok = true; 4149 4150 if (i % 2 == 0 && i + 1 < chs) { 4151 /* even channel, check the odd companion */ 4152 int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1); 4153 int comp_mask_req = snd_hdac_chmap_to_spk_mask(map[i+1]); 4154 int comp_mask_act = cap->speakers[comp_chan_idx]; 4155 4156 if (comp_mask_req == comp_mask_act) 4157 companion_ok = true; 4158 else 4159 return -EINVAL; 4160 } 4161 break; 4162 } 4163 } 4164 4165 if (!ok) 4166 return -EINVAL; 4167 4168 if (companion_ok) 4169 i++; /* companion channel already checked */ 4170 } 4171 4172 return 0; 4173 } 4174 4175 static int atihdmi_pin_set_slot_channel(struct hdac_device *hdac, 4176 hda_nid_t pin_nid, int hdmi_slot, int stream_channel) 4177 { 4178 struct hda_codec *codec = hdac_to_hda_codec(hdac); 4179 int verb; 4180 int ati_channel_setup = 0; 4181 4182 if (hdmi_slot > 7) 4183 return -EINVAL; 4184 4185 if (!has_amd_full_remap_support(codec)) { 4186 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot); 4187 4188 /* In case this is an odd slot but without stream channel, do not 4189 * disable the slot since the corresponding even slot could have a 4190 * channel. In case neither have a channel, the slot pair will be 4191 * disabled when this function is called for the even slot. */ 4192 if (hdmi_slot % 2 != 0 && stream_channel == 0xf) 4193 return 0; 4194 4195 hdmi_slot -= hdmi_slot % 2; 4196 4197 if (stream_channel != 0xf) 4198 stream_channel -= stream_channel % 2; 4199 } 4200 4201 verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e; 4202 4203 /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */ 4204 4205 if (stream_channel != 0xf) 4206 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE; 4207 4208 return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup); 4209 } 4210 4211 static int atihdmi_pin_get_slot_channel(struct hdac_device *hdac, 4212 hda_nid_t pin_nid, int asp_slot) 4213 { 4214 struct hda_codec *codec = hdac_to_hda_codec(hdac); 4215 bool was_odd = false; 4216 int ati_asp_slot = asp_slot; 4217 int verb; 4218 int ati_channel_setup; 4219 4220 if (asp_slot > 7) 4221 return -EINVAL; 4222 4223 if (!has_amd_full_remap_support(codec)) { 4224 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot); 4225 if (ati_asp_slot % 2 != 0) { 4226 ati_asp_slot -= 1; 4227 was_odd = true; 4228 } 4229 } 4230 4231 verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e; 4232 4233 ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0); 4234 4235 if (!(ati_channel_setup & ATI_OUT_ENABLE)) 4236 return 0xf; 4237 4238 return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd; 4239 } 4240 4241 static int atihdmi_paired_chmap_cea_alloc_validate_get_type( 4242 struct hdac_chmap *chmap, 4243 struct hdac_cea_channel_speaker_allocation *cap, 4244 int channels) 4245 { 4246 int c; 4247 4248 /* 4249 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so 4250 * we need to take that into account (a single channel may take 2 4251 * channel slots if we need to carry a silent channel next to it). 4252 * On Rev3+ AMD codecs this function is not used. 4253 */ 4254 int chanpairs = 0; 4255 4256 /* We only produce even-numbered channel count TLVs */ 4257 if ((channels % 2) != 0) 4258 return -1; 4259 4260 for (c = 0; c < 7; c += 2) { 4261 if (cap->speakers[c] || cap->speakers[c+1]) 4262 chanpairs++; 4263 } 4264 4265 if (chanpairs * 2 != channels) 4266 return -1; 4267 4268 return SNDRV_CTL_TLVT_CHMAP_PAIRED; 4269 } 4270 4271 static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct hdac_chmap *hchmap, 4272 struct hdac_cea_channel_speaker_allocation *cap, 4273 unsigned int *chmap, int channels) 4274 { 4275 /* produce paired maps for pre-rev3 ATI/AMD codecs */ 4276 int count = 0; 4277 int c; 4278 4279 for (c = 7; c >= 0; c--) { 4280 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c); 4281 int spk = cap->speakers[chan]; 4282 if (!spk) { 4283 /* add N/A channel if the companion channel is occupied */ 4284 if (cap->speakers[chan + (chan % 2 ? -1 : 1)]) 4285 chmap[count++] = SNDRV_CHMAP_NA; 4286 4287 continue; 4288 } 4289 4290 chmap[count++] = snd_hdac_spk_to_chmap(spk); 4291 } 4292 4293 WARN_ON(count != channels); 4294 } 4295 4296 static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid, 4297 int dev_id, bool hbr) 4298 { 4299 int hbr_ctl, hbr_ctl_new; 4300 4301 WARN_ON(dev_id != 0); 4302 4303 hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0); 4304 if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) { 4305 if (hbr) 4306 hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE; 4307 else 4308 hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE; 4309 4310 codec_dbg(codec, 4311 "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n", 4312 pin_nid, 4313 hbr_ctl == hbr_ctl_new ? "" : "new-", 4314 hbr_ctl_new); 4315 4316 if (hbr_ctl != hbr_ctl_new) 4317 snd_hda_codec_write(codec, pin_nid, 0, 4318 ATI_VERB_SET_HBR_CONTROL, 4319 hbr_ctl_new); 4320 4321 } else if (hbr) 4322 return -EINVAL; 4323 4324 return 0; 4325 } 4326 4327 static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, 4328 hda_nid_t pin_nid, int dev_id, 4329 u32 stream_tag, int format) 4330 { 4331 if (is_amdhdmi_rev3_or_later(codec)) { 4332 int ramp_rate = 180; /* default as per AMD spec */ 4333 /* disable ramp-up/down for non-pcm as per AMD spec */ 4334 if (format & AC_FMT_TYPE_NON_PCM) 4335 ramp_rate = 0; 4336 4337 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate); 4338 } 4339 4340 return hdmi_setup_stream(codec, cvt_nid, pin_nid, dev_id, 4341 stream_tag, format); 4342 } 4343 4344 4345 static int atihdmi_init(struct hda_codec *codec) 4346 { 4347 struct hdmi_spec *spec = codec->spec; 4348 int pin_idx, err; 4349 4350 err = generic_hdmi_init(codec); 4351 4352 if (err) 4353 return err; 4354 4355 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 4356 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 4357 4358 /* make sure downmix information in infoframe is zero */ 4359 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0); 4360 4361 /* enable channel-wise remap mode if supported */ 4362 if (has_amd_full_remap_support(codec)) 4363 snd_hda_codec_write(codec, per_pin->pin_nid, 0, 4364 ATI_VERB_SET_MULTICHANNEL_MODE, 4365 ATI_MULTICHANNEL_MODE_SINGLE); 4366 } 4367 codec->auto_runtime_pm = 1; 4368 4369 return 0; 4370 } 4371 4372 /* map from pin NID to port; port is 0-based */ 4373 /* for AMD: assume widget NID starting from 3, with step 2 (3, 5, 7, ...) */ 4374 static int atihdmi_pin2port(void *audio_ptr, int pin_nid) 4375 { 4376 return pin_nid / 2 - 1; 4377 } 4378 4379 /* reverse-map from port to pin NID: see above */ 4380 static int atihdmi_port2pin(struct hda_codec *codec, int port) 4381 { 4382 return port * 2 + 3; 4383 } 4384 4385 static const struct drm_audio_component_audio_ops atihdmi_audio_ops = { 4386 .pin2port = atihdmi_pin2port, 4387 .pin_eld_notify = generic_acomp_pin_eld_notify, 4388 .master_bind = generic_acomp_master_bind, 4389 .master_unbind = generic_acomp_master_unbind, 4390 }; 4391 4392 static int patch_atihdmi(struct hda_codec *codec) 4393 { 4394 struct hdmi_spec *spec; 4395 struct hdmi_spec_per_cvt *per_cvt; 4396 int err, cvt_idx; 4397 4398 err = patch_generic_hdmi(codec); 4399 4400 if (err) 4401 return err; 4402 4403 codec->patch_ops.init = atihdmi_init; 4404 4405 spec = codec->spec; 4406 4407 spec->ops.pin_get_eld = atihdmi_pin_get_eld; 4408 spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe; 4409 spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup; 4410 spec->ops.setup_stream = atihdmi_setup_stream; 4411 4412 spec->chmap.ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel; 4413 spec->chmap.ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel; 4414 4415 if (!has_amd_full_remap_support(codec)) { 4416 /* override to ATI/AMD-specific versions with pairwise mapping */ 4417 spec->chmap.ops.chmap_cea_alloc_validate_get_type = 4418 atihdmi_paired_chmap_cea_alloc_validate_get_type; 4419 spec->chmap.ops.cea_alloc_to_tlv_chmap = 4420 atihdmi_paired_cea_alloc_to_tlv_chmap; 4421 spec->chmap.ops.chmap_validate = atihdmi_paired_chmap_validate; 4422 } 4423 4424 /* ATI/AMD converters do not advertise all of their capabilities */ 4425 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { 4426 per_cvt = get_cvt(spec, cvt_idx); 4427 per_cvt->channels_max = max(per_cvt->channels_max, 8u); 4428 per_cvt->rates |= SUPPORTED_RATES; 4429 per_cvt->formats |= SUPPORTED_FORMATS; 4430 per_cvt->maxbps = max(per_cvt->maxbps, 24u); 4431 } 4432 4433 spec->chmap.channels_max = max(spec->chmap.channels_max, 8u); 4434 4435 /* AMD GPUs have neither EPSS nor CLKSTOP bits, hence preventing 4436 * the link-down as is. Tell the core to allow it. 4437 */ 4438 codec->link_down_at_suspend = 1; 4439 4440 generic_acomp_init(codec, &atihdmi_audio_ops, atihdmi_port2pin); 4441 4442 return 0; 4443 } 4444 4445 /* VIA HDMI Implementation */ 4446 #define VIAHDMI_CVT_NID 0x02 /* audio converter1 */ 4447 #define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */ 4448 4449 static int patch_via_hdmi(struct hda_codec *codec) 4450 { 4451 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID); 4452 } 4453 4454 /* 4455 * patch entries 4456 */ 4457 static const struct hda_device_id snd_hda_id_hdmi[] = { 4458 HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI", patch_atihdmi), 4459 HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI", patch_atihdmi), 4460 HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI", patch_atihdmi), 4461 HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI", patch_atihdmi), 4462 HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI", patch_generic_hdmi), 4463 HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI", patch_generic_hdmi), 4464 HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI", patch_generic_hdmi), 4465 HDA_CODEC_ENTRY(0x10de0001, "MCP73 HDMI", patch_nvhdmi_2ch), 4466 HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 4467 HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 4468 HDA_CODEC_ENTRY(0x10de0004, "GPU 04 HDMI", patch_nvhdmi_8ch_7x), 4469 HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 4470 HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 4471 HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI", patch_nvhdmi_8ch_7x), 4472 HDA_CODEC_ENTRY(0x10de0008, "GPU 08 HDMI/DP", patch_nvhdmi_legacy), 4473 HDA_CODEC_ENTRY(0x10de0009, "GPU 09 HDMI/DP", patch_nvhdmi_legacy), 4474 HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP", patch_nvhdmi_legacy), 4475 HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP", patch_nvhdmi_legacy), 4476 HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI", patch_nvhdmi_legacy), 4477 HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP", patch_nvhdmi_legacy), 4478 HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP", patch_nvhdmi_legacy), 4479 HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP", patch_nvhdmi_legacy), 4480 HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP", patch_nvhdmi_legacy), 4481 HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP", patch_nvhdmi_legacy), 4482 HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP", patch_nvhdmi_legacy), 4483 HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP", patch_nvhdmi_legacy), 4484 HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP", patch_nvhdmi_legacy), 4485 /* 17 is known to be absent */ 4486 HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP", patch_nvhdmi_legacy), 4487 HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP", patch_nvhdmi_legacy), 4488 HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP", patch_nvhdmi_legacy), 4489 HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP", patch_nvhdmi_legacy), 4490 HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP", patch_nvhdmi_legacy), 4491 HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI", patch_tegra_hdmi), 4492 HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI", patch_tegra_hdmi), 4493 HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI", patch_tegra_hdmi), 4494 HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi), 4495 HDA_CODEC_ENTRY(0x10de002d, "Tegra186 HDMI/DP0", patch_tegra_hdmi), 4496 HDA_CODEC_ENTRY(0x10de002e, "Tegra186 HDMI/DP1", patch_tegra_hdmi), 4497 HDA_CODEC_ENTRY(0x10de002f, "Tegra194 HDMI/DP2", patch_tegra_hdmi), 4498 HDA_CODEC_ENTRY(0x10de0030, "Tegra194 HDMI/DP3", patch_tegra_hdmi), 4499 HDA_CODEC_ENTRY(0x10de0031, "Tegra234 HDMI/DP", patch_tegra234_hdmi), 4500 HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP", patch_nvhdmi), 4501 HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP", patch_nvhdmi), 4502 HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi), 4503 HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP", patch_nvhdmi), 4504 HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP", patch_nvhdmi), 4505 HDA_CODEC_ENTRY(0x10de0045, "GPU 45 HDMI/DP", patch_nvhdmi), 4506 HDA_CODEC_ENTRY(0x10de0050, "GPU 50 HDMI/DP", patch_nvhdmi), 4507 HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP", patch_nvhdmi), 4508 HDA_CODEC_ENTRY(0x10de0052, "GPU 52 HDMI/DP", patch_nvhdmi), 4509 HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP", patch_nvhdmi), 4510 HDA_CODEC_ENTRY(0x10de0061, "GPU 61 HDMI/DP", patch_nvhdmi), 4511 HDA_CODEC_ENTRY(0x10de0062, "GPU 62 HDMI/DP", patch_nvhdmi), 4512 HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI", patch_nvhdmi_2ch), 4513 HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP", patch_nvhdmi), 4514 HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP", patch_nvhdmi), 4515 HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP", patch_nvhdmi), 4516 HDA_CODEC_ENTRY(0x10de0073, "GPU 73 HDMI/DP", patch_nvhdmi), 4517 HDA_CODEC_ENTRY(0x10de0074, "GPU 74 HDMI/DP", patch_nvhdmi), 4518 HDA_CODEC_ENTRY(0x10de0076, "GPU 76 HDMI/DP", patch_nvhdmi), 4519 HDA_CODEC_ENTRY(0x10de007b, "GPU 7b HDMI/DP", patch_nvhdmi), 4520 HDA_CODEC_ENTRY(0x10de007c, "GPU 7c HDMI/DP", patch_nvhdmi), 4521 HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP", patch_nvhdmi), 4522 HDA_CODEC_ENTRY(0x10de007e, "GPU 7e HDMI/DP", patch_nvhdmi), 4523 HDA_CODEC_ENTRY(0x10de0080, "GPU 80 HDMI/DP", patch_nvhdmi), 4524 HDA_CODEC_ENTRY(0x10de0081, "GPU 81 HDMI/DP", patch_nvhdmi), 4525 HDA_CODEC_ENTRY(0x10de0082, "GPU 82 HDMI/DP", patch_nvhdmi), 4526 HDA_CODEC_ENTRY(0x10de0083, "GPU 83 HDMI/DP", patch_nvhdmi), 4527 HDA_CODEC_ENTRY(0x10de0084, "GPU 84 HDMI/DP", patch_nvhdmi), 4528 HDA_CODEC_ENTRY(0x10de0090, "GPU 90 HDMI/DP", patch_nvhdmi), 4529 HDA_CODEC_ENTRY(0x10de0091, "GPU 91 HDMI/DP", patch_nvhdmi), 4530 HDA_CODEC_ENTRY(0x10de0092, "GPU 92 HDMI/DP", patch_nvhdmi), 4531 HDA_CODEC_ENTRY(0x10de0093, "GPU 93 HDMI/DP", patch_nvhdmi), 4532 HDA_CODEC_ENTRY(0x10de0094, "GPU 94 HDMI/DP", patch_nvhdmi), 4533 HDA_CODEC_ENTRY(0x10de0095, "GPU 95 HDMI/DP", patch_nvhdmi), 4534 HDA_CODEC_ENTRY(0x10de0097, "GPU 97 HDMI/DP", patch_nvhdmi), 4535 HDA_CODEC_ENTRY(0x10de0098, "GPU 98 HDMI/DP", patch_nvhdmi), 4536 HDA_CODEC_ENTRY(0x10de0099, "GPU 99 HDMI/DP", patch_nvhdmi), 4537 HDA_CODEC_ENTRY(0x10de009a, "GPU 9a HDMI/DP", patch_nvhdmi), 4538 HDA_CODEC_ENTRY(0x10de009d, "GPU 9d HDMI/DP", patch_nvhdmi), 4539 HDA_CODEC_ENTRY(0x10de009e, "GPU 9e HDMI/DP", patch_nvhdmi), 4540 HDA_CODEC_ENTRY(0x10de009f, "GPU 9f HDMI/DP", patch_nvhdmi), 4541 HDA_CODEC_ENTRY(0x10de00a0, "GPU a0 HDMI/DP", patch_nvhdmi), 4542 HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI", patch_nvhdmi_2ch), 4543 HDA_CODEC_ENTRY(0x10de8067, "MCP67/68 HDMI", patch_nvhdmi_2ch), 4544 HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP", patch_via_hdmi), 4545 HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP", patch_via_hdmi), 4546 HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP", patch_generic_hdmi), 4547 HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP", patch_generic_hdmi), 4548 HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI", patch_i915_cpt_hdmi), 4549 HDA_CODEC_ENTRY(0x80862800, "Geminilake HDMI", patch_i915_glk_hdmi), 4550 HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI", patch_generic_hdmi), 4551 HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI", patch_generic_hdmi), 4552 HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI", patch_generic_hdmi), 4553 HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI", patch_i915_cpt_hdmi), 4554 HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_i915_cpt_hdmi), 4555 HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_i915_cpt_hdmi), 4556 HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI", patch_i915_hsw_hdmi), 4557 HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI", patch_i915_hsw_hdmi), 4558 HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI", patch_i915_hsw_hdmi), 4559 HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI", patch_i915_hsw_hdmi), 4560 HDA_CODEC_ENTRY(0x8086280b, "Kabylake HDMI", patch_i915_hsw_hdmi), 4561 HDA_CODEC_ENTRY(0x8086280c, "Cannonlake HDMI", patch_i915_glk_hdmi), 4562 HDA_CODEC_ENTRY(0x8086280d, "Geminilake HDMI", patch_i915_glk_hdmi), 4563 HDA_CODEC_ENTRY(0x8086280f, "Icelake HDMI", patch_i915_icl_hdmi), 4564 HDA_CODEC_ENTRY(0x80862812, "Tigerlake HDMI", patch_i915_tgl_hdmi), 4565 HDA_CODEC_ENTRY(0x80862814, "DG1 HDMI", patch_i915_tgl_hdmi), 4566 HDA_CODEC_ENTRY(0x80862815, "Alderlake HDMI", patch_i915_tgl_hdmi), 4567 HDA_CODEC_ENTRY(0x80862816, "Rocketlake HDMI", patch_i915_tgl_hdmi), 4568 HDA_CODEC_ENTRY(0x80862818, "Raptorlake HDMI", patch_i915_tgl_hdmi), 4569 HDA_CODEC_ENTRY(0x80862819, "DG2 HDMI", patch_i915_adlp_hdmi), 4570 HDA_CODEC_ENTRY(0x8086281a, "Jasperlake HDMI", patch_i915_icl_hdmi), 4571 HDA_CODEC_ENTRY(0x8086281b, "Elkhartlake HDMI", patch_i915_icl_hdmi), 4572 HDA_CODEC_ENTRY(0x8086281c, "Alderlake-P HDMI", patch_i915_adlp_hdmi), 4573 HDA_CODEC_ENTRY(0x8086281f, "Raptorlake-P HDMI", patch_i915_adlp_hdmi), 4574 HDA_CODEC_ENTRY(0x8086281d, "Meteorlake HDMI", patch_i915_adlp_hdmi), 4575 HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI", patch_generic_hdmi), 4576 HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_i915_byt_hdmi), 4577 HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI", patch_i915_byt_hdmi), 4578 HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI", patch_generic_hdmi), 4579 /* special ID for generic HDMI */ 4580 HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi), 4581 {} /* terminator */ 4582 }; 4583 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi); 4584 4585 MODULE_LICENSE("GPL"); 4586 MODULE_DESCRIPTION("HDMI HD-audio codec"); 4587 MODULE_ALIAS("snd-hda-codec-intelhdmi"); 4588 MODULE_ALIAS("snd-hda-codec-nvhdmi"); 4589 MODULE_ALIAS("snd-hda-codec-atihdmi"); 4590 4591 static struct hda_codec_driver hdmi_driver = { 4592 .id = snd_hda_id_hdmi, 4593 }; 4594 4595 module_hda_codec_driver(hdmi_driver); 4596