1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * 4 * patch_hdmi.c - routines for HDMI/DisplayPort codecs 5 * 6 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved. 7 * Copyright (c) 2006 ATI Technologies Inc. 8 * Copyright (c) 2008 NVIDIA Corp. All rights reserved. 9 * Copyright (c) 2008 Wei Ni <wni@nvidia.com> 10 * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi> 11 * 12 * Authors: 13 * Wu Fengguang <wfg@linux.intel.com> 14 * 15 * Maintained by: 16 * Wu Fengguang <wfg@linux.intel.com> 17 */ 18 19 #include <linux/init.h> 20 #include <linux/delay.h> 21 #include <linux/pci.h> 22 #include <linux/slab.h> 23 #include <linux/module.h> 24 #include <linux/pm_runtime.h> 25 #include <sound/core.h> 26 #include <sound/jack.h> 27 #include <sound/asoundef.h> 28 #include <sound/tlv.h> 29 #include <sound/hdaudio.h> 30 #include <sound/hda_i915.h> 31 #include <sound/hda_chmap.h> 32 #include <sound/hda_codec.h> 33 #include "hda_local.h" 34 #include "hda_jack.h" 35 36 static bool static_hdmi_pcm; 37 module_param(static_hdmi_pcm, bool, 0644); 38 MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info"); 39 40 #define is_haswell(codec) ((codec)->core.vendor_id == 0x80862807) 41 #define is_broadwell(codec) ((codec)->core.vendor_id == 0x80862808) 42 #define is_skylake(codec) ((codec)->core.vendor_id == 0x80862809) 43 #define is_broxton(codec) ((codec)->core.vendor_id == 0x8086280a) 44 #define is_kabylake(codec) ((codec)->core.vendor_id == 0x8086280b) 45 #define is_geminilake(codec) (((codec)->core.vendor_id == 0x8086280d) || \ 46 ((codec)->core.vendor_id == 0x80862800)) 47 #define is_cannonlake(codec) ((codec)->core.vendor_id == 0x8086280c) 48 #define is_icelake(codec) ((codec)->core.vendor_id == 0x8086280f) 49 #define is_haswell_plus(codec) (is_haswell(codec) || is_broadwell(codec) \ 50 || is_skylake(codec) || is_broxton(codec) \ 51 || is_kabylake(codec) || is_geminilake(codec) \ 52 || is_cannonlake(codec) || is_icelake(codec)) 53 #define is_valleyview(codec) ((codec)->core.vendor_id == 0x80862882) 54 #define is_cherryview(codec) ((codec)->core.vendor_id == 0x80862883) 55 #define is_valleyview_plus(codec) (is_valleyview(codec) || is_cherryview(codec)) 56 57 struct hdmi_spec_per_cvt { 58 hda_nid_t cvt_nid; 59 int assigned; 60 unsigned int channels_min; 61 unsigned int channels_max; 62 u32 rates; 63 u64 formats; 64 unsigned int maxbps; 65 }; 66 67 /* max. connections to a widget */ 68 #define HDA_MAX_CONNECTIONS 32 69 70 struct hdmi_spec_per_pin { 71 hda_nid_t pin_nid; 72 int dev_id; 73 /* pin idx, different device entries on the same pin use the same idx */ 74 int pin_nid_idx; 75 int num_mux_nids; 76 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS]; 77 int mux_idx; 78 hda_nid_t cvt_nid; 79 80 struct hda_codec *codec; 81 struct hdmi_eld sink_eld; 82 struct mutex lock; 83 struct delayed_work work; 84 struct hdmi_pcm *pcm; /* pointer to spec->pcm_rec[n] dynamically*/ 85 int pcm_idx; /* which pcm is attached. -1 means no pcm is attached */ 86 int repoll_count; 87 bool setup; /* the stream has been set up by prepare callback */ 88 int channels; /* current number of channels */ 89 bool non_pcm; 90 bool chmap_set; /* channel-map override by ALSA API? */ 91 unsigned char chmap[8]; /* ALSA API channel-map */ 92 #ifdef CONFIG_SND_PROC_FS 93 struct snd_info_entry *proc_entry; 94 #endif 95 }; 96 97 /* operations used by generic code that can be overridden by patches */ 98 struct hdmi_ops { 99 int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid, 100 unsigned char *buf, int *eld_size); 101 102 void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid, 103 int ca, int active_channels, int conn_type); 104 105 /* enable/disable HBR (HD passthrough) */ 106 int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, bool hbr); 107 108 int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid, 109 hda_nid_t pin_nid, u32 stream_tag, int format); 110 111 void (*pin_cvt_fixup)(struct hda_codec *codec, 112 struct hdmi_spec_per_pin *per_pin, 113 hda_nid_t cvt_nid); 114 }; 115 116 struct hdmi_pcm { 117 struct hda_pcm *pcm; 118 struct snd_jack *jack; 119 struct snd_kcontrol *eld_ctl; 120 }; 121 122 struct hdmi_spec { 123 struct hda_codec *codec; 124 int num_cvts; 125 struct snd_array cvts; /* struct hdmi_spec_per_cvt */ 126 hda_nid_t cvt_nids[4]; /* only for haswell fix */ 127 128 /* 129 * num_pins is the number of virtual pins 130 * for example, there are 3 pins, and each pin 131 * has 4 device entries, then the num_pins is 12 132 */ 133 int num_pins; 134 /* 135 * num_nids is the number of real pins 136 * In the above example, num_nids is 3 137 */ 138 int num_nids; 139 /* 140 * dev_num is the number of device entries 141 * on each pin. 142 * In the above example, dev_num is 4 143 */ 144 int dev_num; 145 struct snd_array pins; /* struct hdmi_spec_per_pin */ 146 struct hdmi_pcm pcm_rec[16]; 147 struct mutex pcm_lock; 148 struct mutex bind_lock; /* for audio component binding */ 149 /* pcm_bitmap means which pcms have been assigned to pins*/ 150 unsigned long pcm_bitmap; 151 int pcm_used; /* counter of pcm_rec[] */ 152 /* bitmap shows whether the pcm is opened in user space 153 * bit 0 means the first playback PCM (PCM3); 154 * bit 1 means the second playback PCM, and so on. 155 */ 156 unsigned long pcm_in_use; 157 158 struct hdmi_eld temp_eld; 159 struct hdmi_ops ops; 160 161 bool dyn_pin_out; 162 bool dyn_pcm_assign; 163 /* 164 * Non-generic VIA/NVIDIA specific 165 */ 166 struct hda_multi_out multiout; 167 struct hda_pcm_stream pcm_playback; 168 169 bool use_jack_detect; /* jack detection enabled */ 170 bool use_acomp_notifier; /* use eld_notify callback for hotplug */ 171 bool acomp_registered; /* audio component registered in this driver */ 172 struct drm_audio_component_audio_ops drm_audio_ops; 173 int (*port2pin)(struct hda_codec *, int); /* reverse port/pin mapping */ 174 175 struct hdac_chmap chmap; 176 hda_nid_t vendor_nid; 177 const int *port_map; 178 int port_num; 179 }; 180 181 #ifdef CONFIG_SND_HDA_COMPONENT 182 static inline bool codec_has_acomp(struct hda_codec *codec) 183 { 184 struct hdmi_spec *spec = codec->spec; 185 return spec->use_acomp_notifier; 186 } 187 #else 188 #define codec_has_acomp(codec) false 189 #endif 190 191 struct hdmi_audio_infoframe { 192 u8 type; /* 0x84 */ 193 u8 ver; /* 0x01 */ 194 u8 len; /* 0x0a */ 195 196 u8 checksum; 197 198 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */ 199 u8 SS01_SF24; 200 u8 CXT04; 201 u8 CA; 202 u8 LFEPBL01_LSV36_DM_INH7; 203 }; 204 205 struct dp_audio_infoframe { 206 u8 type; /* 0x84 */ 207 u8 len; /* 0x1b */ 208 u8 ver; /* 0x11 << 2 */ 209 210 u8 CC02_CT47; /* match with HDMI infoframe from this on */ 211 u8 SS01_SF24; 212 u8 CXT04; 213 u8 CA; 214 u8 LFEPBL01_LSV36_DM_INH7; 215 }; 216 217 union audio_infoframe { 218 struct hdmi_audio_infoframe hdmi; 219 struct dp_audio_infoframe dp; 220 u8 bytes[0]; 221 }; 222 223 /* 224 * HDMI routines 225 */ 226 227 #define get_pin(spec, idx) \ 228 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx)) 229 #define get_cvt(spec, idx) \ 230 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx)) 231 /* obtain hdmi_pcm object assigned to idx */ 232 #define get_hdmi_pcm(spec, idx) (&(spec)->pcm_rec[idx]) 233 /* obtain hda_pcm object assigned to idx */ 234 #define get_pcm_rec(spec, idx) (get_hdmi_pcm(spec, idx)->pcm) 235 236 static int pin_id_to_pin_index(struct hda_codec *codec, 237 hda_nid_t pin_nid, int dev_id) 238 { 239 struct hdmi_spec *spec = codec->spec; 240 int pin_idx; 241 struct hdmi_spec_per_pin *per_pin; 242 243 /* 244 * (dev_id == -1) means it is NON-MST pin 245 * return the first virtual pin on this port 246 */ 247 if (dev_id == -1) 248 dev_id = 0; 249 250 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 251 per_pin = get_pin(spec, pin_idx); 252 if ((per_pin->pin_nid == pin_nid) && 253 (per_pin->dev_id == dev_id)) 254 return pin_idx; 255 } 256 257 codec_warn(codec, "HDMI: pin nid %d not registered\n", pin_nid); 258 return -EINVAL; 259 } 260 261 static int hinfo_to_pcm_index(struct hda_codec *codec, 262 struct hda_pcm_stream *hinfo) 263 { 264 struct hdmi_spec *spec = codec->spec; 265 int pcm_idx; 266 267 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) 268 if (get_pcm_rec(spec, pcm_idx)->stream == hinfo) 269 return pcm_idx; 270 271 codec_warn(codec, "HDMI: hinfo %p not registered\n", hinfo); 272 return -EINVAL; 273 } 274 275 static int hinfo_to_pin_index(struct hda_codec *codec, 276 struct hda_pcm_stream *hinfo) 277 { 278 struct hdmi_spec *spec = codec->spec; 279 struct hdmi_spec_per_pin *per_pin; 280 int pin_idx; 281 282 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 283 per_pin = get_pin(spec, pin_idx); 284 if (per_pin->pcm && 285 per_pin->pcm->pcm->stream == hinfo) 286 return pin_idx; 287 } 288 289 codec_dbg(codec, "HDMI: hinfo %p not registered\n", hinfo); 290 return -EINVAL; 291 } 292 293 static struct hdmi_spec_per_pin *pcm_idx_to_pin(struct hdmi_spec *spec, 294 int pcm_idx) 295 { 296 int i; 297 struct hdmi_spec_per_pin *per_pin; 298 299 for (i = 0; i < spec->num_pins; i++) { 300 per_pin = get_pin(spec, i); 301 if (per_pin->pcm_idx == pcm_idx) 302 return per_pin; 303 } 304 return NULL; 305 } 306 307 static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid) 308 { 309 struct hdmi_spec *spec = codec->spec; 310 int cvt_idx; 311 312 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) 313 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid) 314 return cvt_idx; 315 316 codec_warn(codec, "HDMI: cvt nid %d not registered\n", cvt_nid); 317 return -EINVAL; 318 } 319 320 static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol, 321 struct snd_ctl_elem_info *uinfo) 322 { 323 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 324 struct hdmi_spec *spec = codec->spec; 325 struct hdmi_spec_per_pin *per_pin; 326 struct hdmi_eld *eld; 327 int pcm_idx; 328 329 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; 330 331 pcm_idx = kcontrol->private_value; 332 mutex_lock(&spec->pcm_lock); 333 per_pin = pcm_idx_to_pin(spec, pcm_idx); 334 if (!per_pin) { 335 /* no pin is bound to the pcm */ 336 uinfo->count = 0; 337 goto unlock; 338 } 339 eld = &per_pin->sink_eld; 340 uinfo->count = eld->eld_valid ? eld->eld_size : 0; 341 342 unlock: 343 mutex_unlock(&spec->pcm_lock); 344 return 0; 345 } 346 347 static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol, 348 struct snd_ctl_elem_value *ucontrol) 349 { 350 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 351 struct hdmi_spec *spec = codec->spec; 352 struct hdmi_spec_per_pin *per_pin; 353 struct hdmi_eld *eld; 354 int pcm_idx; 355 int err = 0; 356 357 pcm_idx = kcontrol->private_value; 358 mutex_lock(&spec->pcm_lock); 359 per_pin = pcm_idx_to_pin(spec, pcm_idx); 360 if (!per_pin) { 361 /* no pin is bound to the pcm */ 362 memset(ucontrol->value.bytes.data, 0, 363 ARRAY_SIZE(ucontrol->value.bytes.data)); 364 goto unlock; 365 } 366 367 eld = &per_pin->sink_eld; 368 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data) || 369 eld->eld_size > ELD_MAX_SIZE) { 370 snd_BUG(); 371 err = -EINVAL; 372 goto unlock; 373 } 374 375 memset(ucontrol->value.bytes.data, 0, 376 ARRAY_SIZE(ucontrol->value.bytes.data)); 377 if (eld->eld_valid) 378 memcpy(ucontrol->value.bytes.data, eld->eld_buffer, 379 eld->eld_size); 380 381 unlock: 382 mutex_unlock(&spec->pcm_lock); 383 return err; 384 } 385 386 static const struct snd_kcontrol_new eld_bytes_ctl = { 387 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, 388 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 389 .name = "ELD", 390 .info = hdmi_eld_ctl_info, 391 .get = hdmi_eld_ctl_get, 392 }; 393 394 static int hdmi_create_eld_ctl(struct hda_codec *codec, int pcm_idx, 395 int device) 396 { 397 struct snd_kcontrol *kctl; 398 struct hdmi_spec *spec = codec->spec; 399 int err; 400 401 kctl = snd_ctl_new1(&eld_bytes_ctl, codec); 402 if (!kctl) 403 return -ENOMEM; 404 kctl->private_value = pcm_idx; 405 kctl->id.device = device; 406 407 /* no pin nid is associated with the kctl now 408 * tbd: associate pin nid to eld ctl later 409 */ 410 err = snd_hda_ctl_add(codec, 0, kctl); 411 if (err < 0) 412 return err; 413 414 get_hdmi_pcm(spec, pcm_idx)->eld_ctl = kctl; 415 return 0; 416 } 417 418 #ifdef BE_PARANOID 419 static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid, 420 int *packet_index, int *byte_index) 421 { 422 int val; 423 424 val = snd_hda_codec_read(codec, pin_nid, 0, 425 AC_VERB_GET_HDMI_DIP_INDEX, 0); 426 427 *packet_index = val >> 5; 428 *byte_index = val & 0x1f; 429 } 430 #endif 431 432 static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid, 433 int packet_index, int byte_index) 434 { 435 int val; 436 437 val = (packet_index << 5) | (byte_index & 0x1f); 438 439 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val); 440 } 441 442 static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid, 443 unsigned char val) 444 { 445 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val); 446 } 447 448 static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid) 449 { 450 struct hdmi_spec *spec = codec->spec; 451 int pin_out; 452 453 /* Unmute */ 454 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP) 455 snd_hda_codec_write(codec, pin_nid, 0, 456 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE); 457 458 if (spec->dyn_pin_out) 459 /* Disable pin out until stream is active */ 460 pin_out = 0; 461 else 462 /* Enable pin out: some machines with GM965 gets broken output 463 * when the pin is disabled or changed while using with HDMI 464 */ 465 pin_out = PIN_OUT; 466 467 snd_hda_codec_write(codec, pin_nid, 0, 468 AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out); 469 } 470 471 /* 472 * ELD proc files 473 */ 474 475 #ifdef CONFIG_SND_PROC_FS 476 static void print_eld_info(struct snd_info_entry *entry, 477 struct snd_info_buffer *buffer) 478 { 479 struct hdmi_spec_per_pin *per_pin = entry->private_data; 480 481 mutex_lock(&per_pin->lock); 482 snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer); 483 mutex_unlock(&per_pin->lock); 484 } 485 486 static void write_eld_info(struct snd_info_entry *entry, 487 struct snd_info_buffer *buffer) 488 { 489 struct hdmi_spec_per_pin *per_pin = entry->private_data; 490 491 mutex_lock(&per_pin->lock); 492 snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer); 493 mutex_unlock(&per_pin->lock); 494 } 495 496 static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index) 497 { 498 char name[32]; 499 struct hda_codec *codec = per_pin->codec; 500 struct snd_info_entry *entry; 501 int err; 502 503 snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index); 504 err = snd_card_proc_new(codec->card, name, &entry); 505 if (err < 0) 506 return err; 507 508 snd_info_set_text_ops(entry, per_pin, print_eld_info); 509 entry->c.text.write = write_eld_info; 510 entry->mode |= 0200; 511 per_pin->proc_entry = entry; 512 513 return 0; 514 } 515 516 static void eld_proc_free(struct hdmi_spec_per_pin *per_pin) 517 { 518 if (!per_pin->codec->bus->shutdown) { 519 snd_info_free_entry(per_pin->proc_entry); 520 per_pin->proc_entry = NULL; 521 } 522 } 523 #else 524 static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin, 525 int index) 526 { 527 return 0; 528 } 529 static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin) 530 { 531 } 532 #endif 533 534 /* 535 * Audio InfoFrame routines 536 */ 537 538 /* 539 * Enable Audio InfoFrame Transmission 540 */ 541 static void hdmi_start_infoframe_trans(struct hda_codec *codec, 542 hda_nid_t pin_nid) 543 { 544 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 545 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT, 546 AC_DIPXMIT_BEST); 547 } 548 549 /* 550 * Disable Audio InfoFrame Transmission 551 */ 552 static void hdmi_stop_infoframe_trans(struct hda_codec *codec, 553 hda_nid_t pin_nid) 554 { 555 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 556 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT, 557 AC_DIPXMIT_DISABLE); 558 } 559 560 static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid) 561 { 562 #ifdef CONFIG_SND_DEBUG_VERBOSE 563 int i; 564 int size; 565 566 size = snd_hdmi_get_eld_size(codec, pin_nid); 567 codec_dbg(codec, "HDMI: ELD buf size is %d\n", size); 568 569 for (i = 0; i < 8; i++) { 570 size = snd_hda_codec_read(codec, pin_nid, 0, 571 AC_VERB_GET_HDMI_DIP_SIZE, i); 572 codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size); 573 } 574 #endif 575 } 576 577 static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid) 578 { 579 #ifdef BE_PARANOID 580 int i, j; 581 int size; 582 int pi, bi; 583 for (i = 0; i < 8; i++) { 584 size = snd_hda_codec_read(codec, pin_nid, 0, 585 AC_VERB_GET_HDMI_DIP_SIZE, i); 586 if (size == 0) 587 continue; 588 589 hdmi_set_dip_index(codec, pin_nid, i, 0x0); 590 for (j = 1; j < 1000; j++) { 591 hdmi_write_dip_byte(codec, pin_nid, 0x0); 592 hdmi_get_dip_index(codec, pin_nid, &pi, &bi); 593 if (pi != i) 594 codec_dbg(codec, "dip index %d: %d != %d\n", 595 bi, pi, i); 596 if (bi == 0) /* byte index wrapped around */ 597 break; 598 } 599 codec_dbg(codec, 600 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n", 601 i, size, j); 602 } 603 #endif 604 } 605 606 static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai) 607 { 608 u8 *bytes = (u8 *)hdmi_ai; 609 u8 sum = 0; 610 int i; 611 612 hdmi_ai->checksum = 0; 613 614 for (i = 0; i < sizeof(*hdmi_ai); i++) 615 sum += bytes[i]; 616 617 hdmi_ai->checksum = -sum; 618 } 619 620 static void hdmi_fill_audio_infoframe(struct hda_codec *codec, 621 hda_nid_t pin_nid, 622 u8 *dip, int size) 623 { 624 int i; 625 626 hdmi_debug_dip_size(codec, pin_nid); 627 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */ 628 629 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 630 for (i = 0; i < size; i++) 631 hdmi_write_dip_byte(codec, pin_nid, dip[i]); 632 } 633 634 static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid, 635 u8 *dip, int size) 636 { 637 u8 val; 638 int i; 639 640 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0) 641 != AC_DIPXMIT_BEST) 642 return false; 643 644 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 645 for (i = 0; i < size; i++) { 646 val = snd_hda_codec_read(codec, pin_nid, 0, 647 AC_VERB_GET_HDMI_DIP_DATA, 0); 648 if (val != dip[i]) 649 return false; 650 } 651 652 return true; 653 } 654 655 static void hdmi_pin_setup_infoframe(struct hda_codec *codec, 656 hda_nid_t pin_nid, 657 int ca, int active_channels, 658 int conn_type) 659 { 660 union audio_infoframe ai; 661 662 memset(&ai, 0, sizeof(ai)); 663 if (conn_type == 0) { /* HDMI */ 664 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi; 665 666 hdmi_ai->type = 0x84; 667 hdmi_ai->ver = 0x01; 668 hdmi_ai->len = 0x0a; 669 hdmi_ai->CC02_CT47 = active_channels - 1; 670 hdmi_ai->CA = ca; 671 hdmi_checksum_audio_infoframe(hdmi_ai); 672 } else if (conn_type == 1) { /* DisplayPort */ 673 struct dp_audio_infoframe *dp_ai = &ai.dp; 674 675 dp_ai->type = 0x84; 676 dp_ai->len = 0x1b; 677 dp_ai->ver = 0x11 << 2; 678 dp_ai->CC02_CT47 = active_channels - 1; 679 dp_ai->CA = ca; 680 } else { 681 codec_dbg(codec, "HDMI: unknown connection type at pin %d\n", 682 pin_nid); 683 return; 684 } 685 686 /* 687 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or 688 * sizeof(*dp_ai) to avoid partial match/update problems when 689 * the user switches between HDMI/DP monitors. 690 */ 691 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes, 692 sizeof(ai))) { 693 codec_dbg(codec, 694 "hdmi_pin_setup_infoframe: pin=%d channels=%d ca=0x%02x\n", 695 pin_nid, 696 active_channels, ca); 697 hdmi_stop_infoframe_trans(codec, pin_nid); 698 hdmi_fill_audio_infoframe(codec, pin_nid, 699 ai.bytes, sizeof(ai)); 700 hdmi_start_infoframe_trans(codec, pin_nid); 701 } 702 } 703 704 static void hdmi_setup_audio_infoframe(struct hda_codec *codec, 705 struct hdmi_spec_per_pin *per_pin, 706 bool non_pcm) 707 { 708 struct hdmi_spec *spec = codec->spec; 709 struct hdac_chmap *chmap = &spec->chmap; 710 hda_nid_t pin_nid = per_pin->pin_nid; 711 int channels = per_pin->channels; 712 int active_channels; 713 struct hdmi_eld *eld; 714 int ca; 715 716 if (!channels) 717 return; 718 719 /* some HW (e.g. HSW+) needs reprogramming the amp at each time */ 720 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP) 721 snd_hda_codec_write(codec, pin_nid, 0, 722 AC_VERB_SET_AMP_GAIN_MUTE, 723 AMP_OUT_UNMUTE); 724 725 eld = &per_pin->sink_eld; 726 727 ca = snd_hdac_channel_allocation(&codec->core, 728 eld->info.spk_alloc, channels, 729 per_pin->chmap_set, non_pcm, per_pin->chmap); 730 731 active_channels = snd_hdac_get_active_channels(ca); 732 733 chmap->ops.set_channel_count(&codec->core, per_pin->cvt_nid, 734 active_channels); 735 736 /* 737 * always configure channel mapping, it may have been changed by the 738 * user in the meantime 739 */ 740 snd_hdac_setup_channel_mapping(&spec->chmap, 741 pin_nid, non_pcm, ca, channels, 742 per_pin->chmap, per_pin->chmap_set); 743 744 spec->ops.pin_setup_infoframe(codec, pin_nid, ca, active_channels, 745 eld->info.conn_type); 746 747 per_pin->non_pcm = non_pcm; 748 } 749 750 /* 751 * Unsolicited events 752 */ 753 754 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll); 755 756 static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid, 757 int dev_id) 758 { 759 struct hdmi_spec *spec = codec->spec; 760 int pin_idx = pin_id_to_pin_index(codec, nid, dev_id); 761 762 if (pin_idx < 0) 763 return; 764 mutex_lock(&spec->pcm_lock); 765 if (hdmi_present_sense(get_pin(spec, pin_idx), 1)) 766 snd_hda_jack_report_sync(codec); 767 mutex_unlock(&spec->pcm_lock); 768 } 769 770 static void jack_callback(struct hda_codec *codec, 771 struct hda_jack_callback *jack) 772 { 773 /* stop polling when notification is enabled */ 774 if (codec_has_acomp(codec)) 775 return; 776 777 /* hda_jack don't support DP MST */ 778 check_presence_and_report(codec, jack->nid, 0); 779 } 780 781 static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res) 782 { 783 int tag = res >> AC_UNSOL_RES_TAG_SHIFT; 784 struct hda_jack_tbl *jack; 785 int dev_entry = (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT; 786 787 /* 788 * assume DP MST uses dyn_pcm_assign and acomp and 789 * never comes here 790 * if DP MST supports unsol event, below code need 791 * consider dev_entry 792 */ 793 jack = snd_hda_jack_tbl_get_from_tag(codec, tag); 794 if (!jack) 795 return; 796 jack->jack_dirty = 1; 797 798 codec_dbg(codec, 799 "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n", 800 codec->addr, jack->nid, dev_entry, !!(res & AC_UNSOL_RES_IA), 801 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV)); 802 803 /* hda_jack don't support DP MST */ 804 check_presence_and_report(codec, jack->nid, 0); 805 } 806 807 static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res) 808 { 809 int tag = res >> AC_UNSOL_RES_TAG_SHIFT; 810 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT; 811 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE); 812 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY); 813 814 codec_info(codec, 815 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n", 816 codec->addr, 817 tag, 818 subtag, 819 cp_state, 820 cp_ready); 821 822 /* TODO */ 823 if (cp_state) 824 ; 825 if (cp_ready) 826 ; 827 } 828 829 830 static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res) 831 { 832 int tag = res >> AC_UNSOL_RES_TAG_SHIFT; 833 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT; 834 835 if (codec_has_acomp(codec)) 836 return; 837 838 if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) { 839 codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag); 840 return; 841 } 842 843 if (subtag == 0) 844 hdmi_intrinsic_event(codec, res); 845 else 846 hdmi_non_intrinsic_event(codec, res); 847 } 848 849 static void haswell_verify_D0(struct hda_codec *codec, 850 hda_nid_t cvt_nid, hda_nid_t nid) 851 { 852 int pwr; 853 854 /* For Haswell, the converter 1/2 may keep in D3 state after bootup, 855 * thus pins could only choose converter 0 for use. Make sure the 856 * converters are in correct power state */ 857 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0)) 858 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0); 859 860 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) { 861 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE, 862 AC_PWRST_D0); 863 msleep(40); 864 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0); 865 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT; 866 codec_dbg(codec, "Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr); 867 } 868 } 869 870 /* 871 * Callbacks 872 */ 873 874 /* HBR should be Non-PCM, 8 channels */ 875 #define is_hbr_format(format) \ 876 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7) 877 878 static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid, 879 bool hbr) 880 { 881 int pinctl, new_pinctl; 882 883 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) { 884 pinctl = snd_hda_codec_read(codec, pin_nid, 0, 885 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 886 887 if (pinctl < 0) 888 return hbr ? -EINVAL : 0; 889 890 new_pinctl = pinctl & ~AC_PINCTL_EPT; 891 if (hbr) 892 new_pinctl |= AC_PINCTL_EPT_HBR; 893 else 894 new_pinctl |= AC_PINCTL_EPT_NATIVE; 895 896 codec_dbg(codec, 897 "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n", 898 pin_nid, 899 pinctl == new_pinctl ? "" : "new-", 900 new_pinctl); 901 902 if (pinctl != new_pinctl) 903 snd_hda_codec_write(codec, pin_nid, 0, 904 AC_VERB_SET_PIN_WIDGET_CONTROL, 905 new_pinctl); 906 } else if (hbr) 907 return -EINVAL; 908 909 return 0; 910 } 911 912 static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, 913 hda_nid_t pin_nid, u32 stream_tag, int format) 914 { 915 struct hdmi_spec *spec = codec->spec; 916 unsigned int param; 917 int err; 918 919 err = spec->ops.pin_hbr_setup(codec, pin_nid, is_hbr_format(format)); 920 921 if (err) { 922 codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n"); 923 return err; 924 } 925 926 if (is_haswell_plus(codec)) { 927 928 /* 929 * on recent platforms IEC Coding Type is required for HBR 930 * support, read current Digital Converter settings and set 931 * ICT bitfield if needed. 932 */ 933 param = snd_hda_codec_read(codec, cvt_nid, 0, 934 AC_VERB_GET_DIGI_CONVERT_1, 0); 935 936 param = (param >> 16) & ~(AC_DIG3_ICT); 937 938 /* on recent platforms ICT mode is required for HBR support */ 939 if (is_hbr_format(format)) 940 param |= 0x1; 941 942 snd_hda_codec_write(codec, cvt_nid, 0, 943 AC_VERB_SET_DIGI_CONVERT_3, param); 944 } 945 946 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format); 947 return 0; 948 } 949 950 /* Try to find an available converter 951 * If pin_idx is less then zero, just try to find an available converter. 952 * Otherwise, try to find an available converter and get the cvt mux index 953 * of the pin. 954 */ 955 static int hdmi_choose_cvt(struct hda_codec *codec, 956 int pin_idx, int *cvt_id) 957 { 958 struct hdmi_spec *spec = codec->spec; 959 struct hdmi_spec_per_pin *per_pin; 960 struct hdmi_spec_per_cvt *per_cvt = NULL; 961 int cvt_idx, mux_idx = 0; 962 963 /* pin_idx < 0 means no pin will be bound to the converter */ 964 if (pin_idx < 0) 965 per_pin = NULL; 966 else 967 per_pin = get_pin(spec, pin_idx); 968 969 /* Dynamically assign converter to stream */ 970 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { 971 per_cvt = get_cvt(spec, cvt_idx); 972 973 /* Must not already be assigned */ 974 if (per_cvt->assigned) 975 continue; 976 if (per_pin == NULL) 977 break; 978 /* Must be in pin's mux's list of converters */ 979 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++) 980 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid) 981 break; 982 /* Not in mux list */ 983 if (mux_idx == per_pin->num_mux_nids) 984 continue; 985 break; 986 } 987 988 /* No free converters */ 989 if (cvt_idx == spec->num_cvts) 990 return -EBUSY; 991 992 if (per_pin != NULL) 993 per_pin->mux_idx = mux_idx; 994 995 if (cvt_id) 996 *cvt_id = cvt_idx; 997 998 return 0; 999 } 1000 1001 /* Assure the pin select the right convetor */ 1002 static void intel_verify_pin_cvt_connect(struct hda_codec *codec, 1003 struct hdmi_spec_per_pin *per_pin) 1004 { 1005 hda_nid_t pin_nid = per_pin->pin_nid; 1006 int mux_idx, curr; 1007 1008 mux_idx = per_pin->mux_idx; 1009 curr = snd_hda_codec_read(codec, pin_nid, 0, 1010 AC_VERB_GET_CONNECT_SEL, 0); 1011 if (curr != mux_idx) 1012 snd_hda_codec_write_cache(codec, pin_nid, 0, 1013 AC_VERB_SET_CONNECT_SEL, 1014 mux_idx); 1015 } 1016 1017 /* get the mux index for the converter of the pins 1018 * converter's mux index is the same for all pins on Intel platform 1019 */ 1020 static int intel_cvt_id_to_mux_idx(struct hdmi_spec *spec, 1021 hda_nid_t cvt_nid) 1022 { 1023 int i; 1024 1025 for (i = 0; i < spec->num_cvts; i++) 1026 if (spec->cvt_nids[i] == cvt_nid) 1027 return i; 1028 return -EINVAL; 1029 } 1030 1031 /* Intel HDMI workaround to fix audio routing issue: 1032 * For some Intel display codecs, pins share the same connection list. 1033 * So a conveter can be selected by multiple pins and playback on any of these 1034 * pins will generate sound on the external display, because audio flows from 1035 * the same converter to the display pipeline. Also muting one pin may make 1036 * other pins have no sound output. 1037 * So this function assures that an assigned converter for a pin is not selected 1038 * by any other pins. 1039 */ 1040 static void intel_not_share_assigned_cvt(struct hda_codec *codec, 1041 hda_nid_t pin_nid, 1042 int dev_id, int mux_idx) 1043 { 1044 struct hdmi_spec *spec = codec->spec; 1045 hda_nid_t nid; 1046 int cvt_idx, curr; 1047 struct hdmi_spec_per_cvt *per_cvt; 1048 struct hdmi_spec_per_pin *per_pin; 1049 int pin_idx; 1050 1051 /* configure the pins connections */ 1052 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 1053 int dev_id_saved; 1054 int dev_num; 1055 1056 per_pin = get_pin(spec, pin_idx); 1057 /* 1058 * pin not connected to monitor 1059 * no need to operate on it 1060 */ 1061 if (!per_pin->pcm) 1062 continue; 1063 1064 if ((per_pin->pin_nid == pin_nid) && 1065 (per_pin->dev_id == dev_id)) 1066 continue; 1067 1068 /* 1069 * if per_pin->dev_id >= dev_num, 1070 * snd_hda_get_dev_select() will fail, 1071 * and the following operation is unpredictable. 1072 * So skip this situation. 1073 */ 1074 dev_num = snd_hda_get_num_devices(codec, per_pin->pin_nid) + 1; 1075 if (per_pin->dev_id >= dev_num) 1076 continue; 1077 1078 nid = per_pin->pin_nid; 1079 1080 /* 1081 * Calling this function should not impact 1082 * on the device entry selection 1083 * So let's save the dev id for each pin, 1084 * and restore it when return 1085 */ 1086 dev_id_saved = snd_hda_get_dev_select(codec, nid); 1087 snd_hda_set_dev_select(codec, nid, per_pin->dev_id); 1088 curr = snd_hda_codec_read(codec, nid, 0, 1089 AC_VERB_GET_CONNECT_SEL, 0); 1090 if (curr != mux_idx) { 1091 snd_hda_set_dev_select(codec, nid, dev_id_saved); 1092 continue; 1093 } 1094 1095 1096 /* choose an unassigned converter. The conveters in the 1097 * connection list are in the same order as in the codec. 1098 */ 1099 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { 1100 per_cvt = get_cvt(spec, cvt_idx); 1101 if (!per_cvt->assigned) { 1102 codec_dbg(codec, 1103 "choose cvt %d for pin nid %d\n", 1104 cvt_idx, nid); 1105 snd_hda_codec_write_cache(codec, nid, 0, 1106 AC_VERB_SET_CONNECT_SEL, 1107 cvt_idx); 1108 break; 1109 } 1110 } 1111 snd_hda_set_dev_select(codec, nid, dev_id_saved); 1112 } 1113 } 1114 1115 /* A wrapper of intel_not_share_asigned_cvt() */ 1116 static void intel_not_share_assigned_cvt_nid(struct hda_codec *codec, 1117 hda_nid_t pin_nid, int dev_id, hda_nid_t cvt_nid) 1118 { 1119 int mux_idx; 1120 struct hdmi_spec *spec = codec->spec; 1121 1122 /* On Intel platform, the mapping of converter nid to 1123 * mux index of the pins are always the same. 1124 * The pin nid may be 0, this means all pins will not 1125 * share the converter. 1126 */ 1127 mux_idx = intel_cvt_id_to_mux_idx(spec, cvt_nid); 1128 if (mux_idx >= 0) 1129 intel_not_share_assigned_cvt(codec, pin_nid, dev_id, mux_idx); 1130 } 1131 1132 /* skeleton caller of pin_cvt_fixup ops */ 1133 static void pin_cvt_fixup(struct hda_codec *codec, 1134 struct hdmi_spec_per_pin *per_pin, 1135 hda_nid_t cvt_nid) 1136 { 1137 struct hdmi_spec *spec = codec->spec; 1138 1139 if (spec->ops.pin_cvt_fixup) 1140 spec->ops.pin_cvt_fixup(codec, per_pin, cvt_nid); 1141 } 1142 1143 /* called in hdmi_pcm_open when no pin is assigned to the PCM 1144 * in dyn_pcm_assign mode. 1145 */ 1146 static int hdmi_pcm_open_no_pin(struct hda_pcm_stream *hinfo, 1147 struct hda_codec *codec, 1148 struct snd_pcm_substream *substream) 1149 { 1150 struct hdmi_spec *spec = codec->spec; 1151 struct snd_pcm_runtime *runtime = substream->runtime; 1152 int cvt_idx, pcm_idx; 1153 struct hdmi_spec_per_cvt *per_cvt = NULL; 1154 int err; 1155 1156 pcm_idx = hinfo_to_pcm_index(codec, hinfo); 1157 if (pcm_idx < 0) 1158 return -EINVAL; 1159 1160 err = hdmi_choose_cvt(codec, -1, &cvt_idx); 1161 if (err) 1162 return err; 1163 1164 per_cvt = get_cvt(spec, cvt_idx); 1165 per_cvt->assigned = 1; 1166 hinfo->nid = per_cvt->cvt_nid; 1167 1168 pin_cvt_fixup(codec, NULL, per_cvt->cvt_nid); 1169 1170 set_bit(pcm_idx, &spec->pcm_in_use); 1171 /* todo: setup spdif ctls assign */ 1172 1173 /* Initially set the converter's capabilities */ 1174 hinfo->channels_min = per_cvt->channels_min; 1175 hinfo->channels_max = per_cvt->channels_max; 1176 hinfo->rates = per_cvt->rates; 1177 hinfo->formats = per_cvt->formats; 1178 hinfo->maxbps = per_cvt->maxbps; 1179 1180 /* Store the updated parameters */ 1181 runtime->hw.channels_min = hinfo->channels_min; 1182 runtime->hw.channels_max = hinfo->channels_max; 1183 runtime->hw.formats = hinfo->formats; 1184 runtime->hw.rates = hinfo->rates; 1185 1186 snd_pcm_hw_constraint_step(substream->runtime, 0, 1187 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 1188 return 0; 1189 } 1190 1191 /* 1192 * HDA PCM callbacks 1193 */ 1194 static int hdmi_pcm_open(struct hda_pcm_stream *hinfo, 1195 struct hda_codec *codec, 1196 struct snd_pcm_substream *substream) 1197 { 1198 struct hdmi_spec *spec = codec->spec; 1199 struct snd_pcm_runtime *runtime = substream->runtime; 1200 int pin_idx, cvt_idx, pcm_idx; 1201 struct hdmi_spec_per_pin *per_pin; 1202 struct hdmi_eld *eld; 1203 struct hdmi_spec_per_cvt *per_cvt = NULL; 1204 int err; 1205 1206 /* Validate hinfo */ 1207 pcm_idx = hinfo_to_pcm_index(codec, hinfo); 1208 if (pcm_idx < 0) 1209 return -EINVAL; 1210 1211 mutex_lock(&spec->pcm_lock); 1212 pin_idx = hinfo_to_pin_index(codec, hinfo); 1213 if (!spec->dyn_pcm_assign) { 1214 if (snd_BUG_ON(pin_idx < 0)) { 1215 err = -EINVAL; 1216 goto unlock; 1217 } 1218 } else { 1219 /* no pin is assigned to the PCM 1220 * PA need pcm open successfully when probe 1221 */ 1222 if (pin_idx < 0) { 1223 err = hdmi_pcm_open_no_pin(hinfo, codec, substream); 1224 goto unlock; 1225 } 1226 } 1227 1228 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx); 1229 if (err < 0) 1230 goto unlock; 1231 1232 per_cvt = get_cvt(spec, cvt_idx); 1233 /* Claim converter */ 1234 per_cvt->assigned = 1; 1235 1236 set_bit(pcm_idx, &spec->pcm_in_use); 1237 per_pin = get_pin(spec, pin_idx); 1238 per_pin->cvt_nid = per_cvt->cvt_nid; 1239 hinfo->nid = per_cvt->cvt_nid; 1240 1241 snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id); 1242 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0, 1243 AC_VERB_SET_CONNECT_SEL, 1244 per_pin->mux_idx); 1245 1246 /* configure unused pins to choose other converters */ 1247 pin_cvt_fixup(codec, per_pin, 0); 1248 1249 snd_hda_spdif_ctls_assign(codec, pcm_idx, per_cvt->cvt_nid); 1250 1251 /* Initially set the converter's capabilities */ 1252 hinfo->channels_min = per_cvt->channels_min; 1253 hinfo->channels_max = per_cvt->channels_max; 1254 hinfo->rates = per_cvt->rates; 1255 hinfo->formats = per_cvt->formats; 1256 hinfo->maxbps = per_cvt->maxbps; 1257 1258 eld = &per_pin->sink_eld; 1259 /* Restrict capabilities by ELD if this isn't disabled */ 1260 if (!static_hdmi_pcm && eld->eld_valid) { 1261 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo); 1262 if (hinfo->channels_min > hinfo->channels_max || 1263 !hinfo->rates || !hinfo->formats) { 1264 per_cvt->assigned = 0; 1265 hinfo->nid = 0; 1266 snd_hda_spdif_ctls_unassign(codec, pcm_idx); 1267 err = -ENODEV; 1268 goto unlock; 1269 } 1270 } 1271 1272 /* Store the updated parameters */ 1273 runtime->hw.channels_min = hinfo->channels_min; 1274 runtime->hw.channels_max = hinfo->channels_max; 1275 runtime->hw.formats = hinfo->formats; 1276 runtime->hw.rates = hinfo->rates; 1277 1278 snd_pcm_hw_constraint_step(substream->runtime, 0, 1279 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 1280 unlock: 1281 mutex_unlock(&spec->pcm_lock); 1282 return err; 1283 } 1284 1285 /* 1286 * HDA/HDMI auto parsing 1287 */ 1288 static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx) 1289 { 1290 struct hdmi_spec *spec = codec->spec; 1291 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 1292 hda_nid_t pin_nid = per_pin->pin_nid; 1293 1294 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) { 1295 codec_warn(codec, 1296 "HDMI: pin %d wcaps %#x does not support connection list\n", 1297 pin_nid, get_wcaps(codec, pin_nid)); 1298 return -EINVAL; 1299 } 1300 1301 /* all the device entries on the same pin have the same conn list */ 1302 per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid, 1303 per_pin->mux_nids, 1304 HDA_MAX_CONNECTIONS); 1305 1306 return 0; 1307 } 1308 1309 static int hdmi_find_pcm_slot(struct hdmi_spec *spec, 1310 struct hdmi_spec_per_pin *per_pin) 1311 { 1312 int i; 1313 1314 /* try the prefer PCM */ 1315 if (!test_bit(per_pin->pin_nid_idx, &spec->pcm_bitmap)) 1316 return per_pin->pin_nid_idx; 1317 1318 /* have a second try; check the "reserved area" over num_pins */ 1319 for (i = spec->num_nids; i < spec->pcm_used; i++) { 1320 if (!test_bit(i, &spec->pcm_bitmap)) 1321 return i; 1322 } 1323 1324 /* the last try; check the empty slots in pins */ 1325 for (i = 0; i < spec->num_nids; i++) { 1326 if (!test_bit(i, &spec->pcm_bitmap)) 1327 return i; 1328 } 1329 return -EBUSY; 1330 } 1331 1332 static void hdmi_attach_hda_pcm(struct hdmi_spec *spec, 1333 struct hdmi_spec_per_pin *per_pin) 1334 { 1335 int idx; 1336 1337 /* pcm already be attached to the pin */ 1338 if (per_pin->pcm) 1339 return; 1340 idx = hdmi_find_pcm_slot(spec, per_pin); 1341 if (idx == -EBUSY) 1342 return; 1343 per_pin->pcm_idx = idx; 1344 per_pin->pcm = get_hdmi_pcm(spec, idx); 1345 set_bit(idx, &spec->pcm_bitmap); 1346 } 1347 1348 static void hdmi_detach_hda_pcm(struct hdmi_spec *spec, 1349 struct hdmi_spec_per_pin *per_pin) 1350 { 1351 int idx; 1352 1353 /* pcm already be detached from the pin */ 1354 if (!per_pin->pcm) 1355 return; 1356 idx = per_pin->pcm_idx; 1357 per_pin->pcm_idx = -1; 1358 per_pin->pcm = NULL; 1359 if (idx >= 0 && idx < spec->pcm_used) 1360 clear_bit(idx, &spec->pcm_bitmap); 1361 } 1362 1363 static int hdmi_get_pin_cvt_mux(struct hdmi_spec *spec, 1364 struct hdmi_spec_per_pin *per_pin, hda_nid_t cvt_nid) 1365 { 1366 int mux_idx; 1367 1368 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++) 1369 if (per_pin->mux_nids[mux_idx] == cvt_nid) 1370 break; 1371 return mux_idx; 1372 } 1373 1374 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid); 1375 1376 static void hdmi_pcm_setup_pin(struct hdmi_spec *spec, 1377 struct hdmi_spec_per_pin *per_pin) 1378 { 1379 struct hda_codec *codec = per_pin->codec; 1380 struct hda_pcm *pcm; 1381 struct hda_pcm_stream *hinfo; 1382 struct snd_pcm_substream *substream; 1383 int mux_idx; 1384 bool non_pcm; 1385 1386 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used) 1387 pcm = get_pcm_rec(spec, per_pin->pcm_idx); 1388 else 1389 return; 1390 if (!pcm->pcm) 1391 return; 1392 if (!test_bit(per_pin->pcm_idx, &spec->pcm_in_use)) 1393 return; 1394 1395 /* hdmi audio only uses playback and one substream */ 1396 hinfo = pcm->stream; 1397 substream = pcm->pcm->streams[0].substream; 1398 1399 per_pin->cvt_nid = hinfo->nid; 1400 1401 mux_idx = hdmi_get_pin_cvt_mux(spec, per_pin, hinfo->nid); 1402 if (mux_idx < per_pin->num_mux_nids) { 1403 snd_hda_set_dev_select(codec, per_pin->pin_nid, 1404 per_pin->dev_id); 1405 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0, 1406 AC_VERB_SET_CONNECT_SEL, 1407 mux_idx); 1408 } 1409 snd_hda_spdif_ctls_assign(codec, per_pin->pcm_idx, hinfo->nid); 1410 1411 non_pcm = check_non_pcm_per_cvt(codec, hinfo->nid); 1412 if (substream->runtime) 1413 per_pin->channels = substream->runtime->channels; 1414 per_pin->setup = true; 1415 per_pin->mux_idx = mux_idx; 1416 1417 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm); 1418 } 1419 1420 static void hdmi_pcm_reset_pin(struct hdmi_spec *spec, 1421 struct hdmi_spec_per_pin *per_pin) 1422 { 1423 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used) 1424 snd_hda_spdif_ctls_unassign(per_pin->codec, per_pin->pcm_idx); 1425 1426 per_pin->chmap_set = false; 1427 memset(per_pin->chmap, 0, sizeof(per_pin->chmap)); 1428 1429 per_pin->setup = false; 1430 per_pin->channels = 0; 1431 } 1432 1433 /* update per_pin ELD from the given new ELD; 1434 * setup info frame and notification accordingly 1435 */ 1436 static bool update_eld(struct hda_codec *codec, 1437 struct hdmi_spec_per_pin *per_pin, 1438 struct hdmi_eld *eld) 1439 { 1440 struct hdmi_eld *pin_eld = &per_pin->sink_eld; 1441 struct hdmi_spec *spec = codec->spec; 1442 bool old_eld_valid = pin_eld->eld_valid; 1443 bool eld_changed; 1444 int pcm_idx; 1445 1446 /* for monitor disconnection, save pcm_idx firstly */ 1447 pcm_idx = per_pin->pcm_idx; 1448 if (spec->dyn_pcm_assign) { 1449 if (eld->eld_valid) { 1450 hdmi_attach_hda_pcm(spec, per_pin); 1451 hdmi_pcm_setup_pin(spec, per_pin); 1452 } else { 1453 hdmi_pcm_reset_pin(spec, per_pin); 1454 hdmi_detach_hda_pcm(spec, per_pin); 1455 } 1456 } 1457 /* if pcm_idx == -1, it means this is in monitor connection event 1458 * we can get the correct pcm_idx now. 1459 */ 1460 if (pcm_idx == -1) 1461 pcm_idx = per_pin->pcm_idx; 1462 1463 if (eld->eld_valid) 1464 snd_hdmi_show_eld(codec, &eld->info); 1465 1466 eld_changed = (pin_eld->eld_valid != eld->eld_valid); 1467 eld_changed |= (pin_eld->monitor_present != eld->monitor_present); 1468 if (!eld_changed && eld->eld_valid && pin_eld->eld_valid) 1469 if (pin_eld->eld_size != eld->eld_size || 1470 memcmp(pin_eld->eld_buffer, eld->eld_buffer, 1471 eld->eld_size) != 0) 1472 eld_changed = true; 1473 1474 if (eld_changed) { 1475 pin_eld->monitor_present = eld->monitor_present; 1476 pin_eld->eld_valid = eld->eld_valid; 1477 pin_eld->eld_size = eld->eld_size; 1478 if (eld->eld_valid) 1479 memcpy(pin_eld->eld_buffer, eld->eld_buffer, 1480 eld->eld_size); 1481 pin_eld->info = eld->info; 1482 } 1483 1484 /* 1485 * Re-setup pin and infoframe. This is needed e.g. when 1486 * - sink is first plugged-in 1487 * - transcoder can change during stream playback on Haswell 1488 * and this can make HW reset converter selection on a pin. 1489 */ 1490 if (eld->eld_valid && !old_eld_valid && per_pin->setup) { 1491 pin_cvt_fixup(codec, per_pin, 0); 1492 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm); 1493 } 1494 1495 if (eld_changed && pcm_idx >= 0) 1496 snd_ctl_notify(codec->card, 1497 SNDRV_CTL_EVENT_MASK_VALUE | 1498 SNDRV_CTL_EVENT_MASK_INFO, 1499 &get_hdmi_pcm(spec, pcm_idx)->eld_ctl->id); 1500 return eld_changed; 1501 } 1502 1503 /* update ELD and jack state via HD-audio verbs */ 1504 static bool hdmi_present_sense_via_verbs(struct hdmi_spec_per_pin *per_pin, 1505 int repoll) 1506 { 1507 struct hda_jack_tbl *jack; 1508 struct hda_codec *codec = per_pin->codec; 1509 struct hdmi_spec *spec = codec->spec; 1510 struct hdmi_eld *eld = &spec->temp_eld; 1511 hda_nid_t pin_nid = per_pin->pin_nid; 1512 /* 1513 * Always execute a GetPinSense verb here, even when called from 1514 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited 1515 * response's PD bit is not the real PD value, but indicates that 1516 * the real PD value changed. An older version of the HD-audio 1517 * specification worked this way. Hence, we just ignore the data in 1518 * the unsolicited response to avoid custom WARs. 1519 */ 1520 int present; 1521 bool ret; 1522 bool do_repoll = false; 1523 1524 present = snd_hda_pin_sense(codec, pin_nid); 1525 1526 mutex_lock(&per_pin->lock); 1527 eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE); 1528 if (eld->monitor_present) 1529 eld->eld_valid = !!(present & AC_PINSENSE_ELDV); 1530 else 1531 eld->eld_valid = false; 1532 1533 codec_dbg(codec, 1534 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n", 1535 codec->addr, pin_nid, eld->monitor_present, eld->eld_valid); 1536 1537 if (eld->eld_valid) { 1538 if (spec->ops.pin_get_eld(codec, pin_nid, eld->eld_buffer, 1539 &eld->eld_size) < 0) 1540 eld->eld_valid = false; 1541 else { 1542 if (snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer, 1543 eld->eld_size) < 0) 1544 eld->eld_valid = false; 1545 } 1546 if (!eld->eld_valid && repoll) 1547 do_repoll = true; 1548 } 1549 1550 if (do_repoll) 1551 schedule_delayed_work(&per_pin->work, msecs_to_jiffies(300)); 1552 else 1553 update_eld(codec, per_pin, eld); 1554 1555 ret = !repoll || !eld->monitor_present || eld->eld_valid; 1556 1557 jack = snd_hda_jack_tbl_get(codec, pin_nid); 1558 if (jack) { 1559 jack->block_report = !ret; 1560 jack->pin_sense = (eld->monitor_present && eld->eld_valid) ? 1561 AC_PINSENSE_PRESENCE : 0; 1562 } 1563 mutex_unlock(&per_pin->lock); 1564 return ret; 1565 } 1566 1567 static struct snd_jack *pin_idx_to_jack(struct hda_codec *codec, 1568 struct hdmi_spec_per_pin *per_pin) 1569 { 1570 struct hdmi_spec *spec = codec->spec; 1571 struct snd_jack *jack = NULL; 1572 struct hda_jack_tbl *jack_tbl; 1573 1574 /* if !dyn_pcm_assign, get jack from hda_jack_tbl 1575 * in !dyn_pcm_assign case, spec->pcm_rec[].jack is not 1576 * NULL even after snd_hda_jack_tbl_clear() is called to 1577 * free snd_jack. This may cause access invalid memory 1578 * when calling snd_jack_report 1579 */ 1580 if (per_pin->pcm_idx >= 0 && spec->dyn_pcm_assign) 1581 jack = spec->pcm_rec[per_pin->pcm_idx].jack; 1582 else if (!spec->dyn_pcm_assign) { 1583 /* 1584 * jack tbl doesn't support DP MST 1585 * DP MST will use dyn_pcm_assign, 1586 * so DP MST will never come here 1587 */ 1588 jack_tbl = snd_hda_jack_tbl_get(codec, per_pin->pin_nid); 1589 if (jack_tbl) 1590 jack = jack_tbl->jack; 1591 } 1592 return jack; 1593 } 1594 1595 /* update ELD and jack state via audio component */ 1596 static void sync_eld_via_acomp(struct hda_codec *codec, 1597 struct hdmi_spec_per_pin *per_pin) 1598 { 1599 struct hdmi_spec *spec = codec->spec; 1600 struct hdmi_eld *eld = &spec->temp_eld; 1601 struct snd_jack *jack = NULL; 1602 bool changed; 1603 int size; 1604 1605 mutex_lock(&per_pin->lock); 1606 eld->monitor_present = false; 1607 size = snd_hdac_acomp_get_eld(&codec->core, per_pin->pin_nid, 1608 per_pin->dev_id, &eld->monitor_present, 1609 eld->eld_buffer, ELD_MAX_SIZE); 1610 if (size > 0) { 1611 size = min(size, ELD_MAX_SIZE); 1612 if (snd_hdmi_parse_eld(codec, &eld->info, 1613 eld->eld_buffer, size) < 0) 1614 size = -EINVAL; 1615 } 1616 1617 if (size > 0) { 1618 eld->eld_valid = true; 1619 eld->eld_size = size; 1620 } else { 1621 eld->eld_valid = false; 1622 eld->eld_size = 0; 1623 } 1624 1625 /* pcm_idx >=0 before update_eld() means it is in monitor 1626 * disconnected event. Jack must be fetched before update_eld() 1627 */ 1628 jack = pin_idx_to_jack(codec, per_pin); 1629 changed = update_eld(codec, per_pin, eld); 1630 if (jack == NULL) 1631 jack = pin_idx_to_jack(codec, per_pin); 1632 if (changed && jack) 1633 snd_jack_report(jack, 1634 (eld->monitor_present && eld->eld_valid) ? 1635 SND_JACK_AVOUT : 0); 1636 mutex_unlock(&per_pin->lock); 1637 } 1638 1639 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll) 1640 { 1641 struct hda_codec *codec = per_pin->codec; 1642 int ret; 1643 1644 /* no temporary power up/down needed for component notifier */ 1645 if (!codec_has_acomp(codec)) { 1646 ret = snd_hda_power_up_pm(codec); 1647 if (ret < 0 && pm_runtime_suspended(hda_codec_dev(codec))) { 1648 snd_hda_power_down_pm(codec); 1649 return false; 1650 } 1651 ret = hdmi_present_sense_via_verbs(per_pin, repoll); 1652 snd_hda_power_down_pm(codec); 1653 } else { 1654 sync_eld_via_acomp(codec, per_pin); 1655 ret = false; /* don't call snd_hda_jack_report_sync() */ 1656 } 1657 1658 return ret; 1659 } 1660 1661 static void hdmi_repoll_eld(struct work_struct *work) 1662 { 1663 struct hdmi_spec_per_pin *per_pin = 1664 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work); 1665 struct hda_codec *codec = per_pin->codec; 1666 struct hdmi_spec *spec = codec->spec; 1667 struct hda_jack_tbl *jack; 1668 1669 jack = snd_hda_jack_tbl_get(codec, per_pin->pin_nid); 1670 if (jack) 1671 jack->jack_dirty = 1; 1672 1673 if (per_pin->repoll_count++ > 6) 1674 per_pin->repoll_count = 0; 1675 1676 mutex_lock(&spec->pcm_lock); 1677 if (hdmi_present_sense(per_pin, per_pin->repoll_count)) 1678 snd_hda_jack_report_sync(per_pin->codec); 1679 mutex_unlock(&spec->pcm_lock); 1680 } 1681 1682 static void intel_haswell_fixup_connect_list(struct hda_codec *codec, 1683 hda_nid_t nid); 1684 1685 static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid) 1686 { 1687 struct hdmi_spec *spec = codec->spec; 1688 unsigned int caps, config; 1689 int pin_idx; 1690 struct hdmi_spec_per_pin *per_pin; 1691 int err; 1692 int dev_num, i; 1693 1694 caps = snd_hda_query_pin_caps(codec, pin_nid); 1695 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP))) 1696 return 0; 1697 1698 /* 1699 * For DP MST audio, Configuration Default is the same for 1700 * all device entries on the same pin 1701 */ 1702 config = snd_hda_codec_get_pincfg(codec, pin_nid); 1703 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE) 1704 return 0; 1705 1706 /* 1707 * To simplify the implementation, malloc all 1708 * the virtual pins in the initialization statically 1709 */ 1710 if (is_haswell_plus(codec)) { 1711 /* 1712 * On Intel platforms, device entries number is 1713 * changed dynamically. If there is a DP MST 1714 * hub connected, the device entries number is 3. 1715 * Otherwise, it is 1. 1716 * Here we manually set dev_num to 3, so that 1717 * we can initialize all the device entries when 1718 * bootup statically. 1719 */ 1720 dev_num = 3; 1721 spec->dev_num = 3; 1722 } else if (spec->dyn_pcm_assign && codec->dp_mst) { 1723 dev_num = snd_hda_get_num_devices(codec, pin_nid) + 1; 1724 /* 1725 * spec->dev_num is the maxinum number of device entries 1726 * among all the pins 1727 */ 1728 spec->dev_num = (spec->dev_num > dev_num) ? 1729 spec->dev_num : dev_num; 1730 } else { 1731 /* 1732 * If the platform doesn't support DP MST, 1733 * manually set dev_num to 1. This means 1734 * the pin has only one device entry. 1735 */ 1736 dev_num = 1; 1737 spec->dev_num = 1; 1738 } 1739 1740 for (i = 0; i < dev_num; i++) { 1741 pin_idx = spec->num_pins; 1742 per_pin = snd_array_new(&spec->pins); 1743 1744 if (!per_pin) 1745 return -ENOMEM; 1746 1747 if (spec->dyn_pcm_assign) { 1748 per_pin->pcm = NULL; 1749 per_pin->pcm_idx = -1; 1750 } else { 1751 per_pin->pcm = get_hdmi_pcm(spec, pin_idx); 1752 per_pin->pcm_idx = pin_idx; 1753 } 1754 per_pin->pin_nid = pin_nid; 1755 per_pin->pin_nid_idx = spec->num_nids; 1756 per_pin->dev_id = i; 1757 per_pin->non_pcm = false; 1758 snd_hda_set_dev_select(codec, pin_nid, i); 1759 if (is_haswell_plus(codec)) 1760 intel_haswell_fixup_connect_list(codec, pin_nid); 1761 err = hdmi_read_pin_conn(codec, pin_idx); 1762 if (err < 0) 1763 return err; 1764 spec->num_pins++; 1765 } 1766 spec->num_nids++; 1767 1768 return 0; 1769 } 1770 1771 static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid) 1772 { 1773 struct hdmi_spec *spec = codec->spec; 1774 struct hdmi_spec_per_cvt *per_cvt; 1775 unsigned int chans; 1776 int err; 1777 1778 chans = get_wcaps(codec, cvt_nid); 1779 chans = get_wcaps_channels(chans); 1780 1781 per_cvt = snd_array_new(&spec->cvts); 1782 if (!per_cvt) 1783 return -ENOMEM; 1784 1785 per_cvt->cvt_nid = cvt_nid; 1786 per_cvt->channels_min = 2; 1787 if (chans <= 16) { 1788 per_cvt->channels_max = chans; 1789 if (chans > spec->chmap.channels_max) 1790 spec->chmap.channels_max = chans; 1791 } 1792 1793 err = snd_hda_query_supported_pcm(codec, cvt_nid, 1794 &per_cvt->rates, 1795 &per_cvt->formats, 1796 &per_cvt->maxbps); 1797 if (err < 0) 1798 return err; 1799 1800 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids)) 1801 spec->cvt_nids[spec->num_cvts] = cvt_nid; 1802 spec->num_cvts++; 1803 1804 return 0; 1805 } 1806 1807 static int hdmi_parse_codec(struct hda_codec *codec) 1808 { 1809 hda_nid_t nid; 1810 int i, nodes; 1811 1812 nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &nid); 1813 if (!nid || nodes < 0) { 1814 codec_warn(codec, "HDMI: failed to get afg sub nodes\n"); 1815 return -EINVAL; 1816 } 1817 1818 for (i = 0; i < nodes; i++, nid++) { 1819 unsigned int caps; 1820 unsigned int type; 1821 1822 caps = get_wcaps(codec, nid); 1823 type = get_wcaps_type(caps); 1824 1825 if (!(caps & AC_WCAP_DIGITAL)) 1826 continue; 1827 1828 switch (type) { 1829 case AC_WID_AUD_OUT: 1830 hdmi_add_cvt(codec, nid); 1831 break; 1832 case AC_WID_PIN: 1833 hdmi_add_pin(codec, nid); 1834 break; 1835 } 1836 } 1837 1838 return 0; 1839 } 1840 1841 /* 1842 */ 1843 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid) 1844 { 1845 struct hda_spdif_out *spdif; 1846 bool non_pcm; 1847 1848 mutex_lock(&codec->spdif_mutex); 1849 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid); 1850 /* Add sanity check to pass klockwork check. 1851 * This should never happen. 1852 */ 1853 if (WARN_ON(spdif == NULL)) 1854 return true; 1855 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO); 1856 mutex_unlock(&codec->spdif_mutex); 1857 return non_pcm; 1858 } 1859 1860 /* 1861 * HDMI callbacks 1862 */ 1863 1864 static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 1865 struct hda_codec *codec, 1866 unsigned int stream_tag, 1867 unsigned int format, 1868 struct snd_pcm_substream *substream) 1869 { 1870 hda_nid_t cvt_nid = hinfo->nid; 1871 struct hdmi_spec *spec = codec->spec; 1872 int pin_idx; 1873 struct hdmi_spec_per_pin *per_pin; 1874 hda_nid_t pin_nid; 1875 struct snd_pcm_runtime *runtime = substream->runtime; 1876 bool non_pcm; 1877 int pinctl, stripe; 1878 int err = 0; 1879 1880 mutex_lock(&spec->pcm_lock); 1881 pin_idx = hinfo_to_pin_index(codec, hinfo); 1882 if (spec->dyn_pcm_assign && pin_idx < 0) { 1883 /* when dyn_pcm_assign and pcm is not bound to a pin 1884 * skip pin setup and return 0 to make audio playback 1885 * be ongoing 1886 */ 1887 pin_cvt_fixup(codec, NULL, cvt_nid); 1888 snd_hda_codec_setup_stream(codec, cvt_nid, 1889 stream_tag, 0, format); 1890 goto unlock; 1891 } 1892 1893 if (snd_BUG_ON(pin_idx < 0)) { 1894 err = -EINVAL; 1895 goto unlock; 1896 } 1897 per_pin = get_pin(spec, pin_idx); 1898 pin_nid = per_pin->pin_nid; 1899 1900 /* Verify pin:cvt selections to avoid silent audio after S3. 1901 * After S3, the audio driver restores pin:cvt selections 1902 * but this can happen before gfx is ready and such selection 1903 * is overlooked by HW. Thus multiple pins can share a same 1904 * default convertor and mute control will affect each other, 1905 * which can cause a resumed audio playback become silent 1906 * after S3. 1907 */ 1908 pin_cvt_fixup(codec, per_pin, 0); 1909 1910 /* Call sync_audio_rate to set the N/CTS/M manually if necessary */ 1911 /* Todo: add DP1.2 MST audio support later */ 1912 if (codec_has_acomp(codec)) 1913 snd_hdac_sync_audio_rate(&codec->core, pin_nid, per_pin->dev_id, 1914 runtime->rate); 1915 1916 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid); 1917 mutex_lock(&per_pin->lock); 1918 per_pin->channels = substream->runtime->channels; 1919 per_pin->setup = true; 1920 1921 if (get_wcaps(codec, cvt_nid) & AC_WCAP_STRIPE) { 1922 stripe = snd_hdac_get_stream_stripe_ctl(&codec->bus->core, 1923 substream); 1924 snd_hda_codec_write(codec, cvt_nid, 0, 1925 AC_VERB_SET_STRIPE_CONTROL, 1926 stripe); 1927 } 1928 1929 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm); 1930 mutex_unlock(&per_pin->lock); 1931 if (spec->dyn_pin_out) { 1932 pinctl = snd_hda_codec_read(codec, pin_nid, 0, 1933 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 1934 snd_hda_codec_write(codec, pin_nid, 0, 1935 AC_VERB_SET_PIN_WIDGET_CONTROL, 1936 pinctl | PIN_OUT); 1937 } 1938 1939 /* snd_hda_set_dev_select() has been called before */ 1940 err = spec->ops.setup_stream(codec, cvt_nid, pin_nid, 1941 stream_tag, format); 1942 unlock: 1943 mutex_unlock(&spec->pcm_lock); 1944 return err; 1945 } 1946 1947 static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo, 1948 struct hda_codec *codec, 1949 struct snd_pcm_substream *substream) 1950 { 1951 snd_hda_codec_cleanup_stream(codec, hinfo->nid); 1952 return 0; 1953 } 1954 1955 static int hdmi_pcm_close(struct hda_pcm_stream *hinfo, 1956 struct hda_codec *codec, 1957 struct snd_pcm_substream *substream) 1958 { 1959 struct hdmi_spec *spec = codec->spec; 1960 int cvt_idx, pin_idx, pcm_idx; 1961 struct hdmi_spec_per_cvt *per_cvt; 1962 struct hdmi_spec_per_pin *per_pin; 1963 int pinctl; 1964 int err = 0; 1965 1966 if (hinfo->nid) { 1967 pcm_idx = hinfo_to_pcm_index(codec, hinfo); 1968 if (snd_BUG_ON(pcm_idx < 0)) 1969 return -EINVAL; 1970 cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid); 1971 if (snd_BUG_ON(cvt_idx < 0)) 1972 return -EINVAL; 1973 per_cvt = get_cvt(spec, cvt_idx); 1974 1975 snd_BUG_ON(!per_cvt->assigned); 1976 per_cvt->assigned = 0; 1977 hinfo->nid = 0; 1978 1979 mutex_lock(&spec->pcm_lock); 1980 snd_hda_spdif_ctls_unassign(codec, pcm_idx); 1981 clear_bit(pcm_idx, &spec->pcm_in_use); 1982 pin_idx = hinfo_to_pin_index(codec, hinfo); 1983 if (spec->dyn_pcm_assign && pin_idx < 0) 1984 goto unlock; 1985 1986 if (snd_BUG_ON(pin_idx < 0)) { 1987 err = -EINVAL; 1988 goto unlock; 1989 } 1990 per_pin = get_pin(spec, pin_idx); 1991 1992 if (spec->dyn_pin_out) { 1993 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0, 1994 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 1995 snd_hda_codec_write(codec, per_pin->pin_nid, 0, 1996 AC_VERB_SET_PIN_WIDGET_CONTROL, 1997 pinctl & ~PIN_OUT); 1998 } 1999 2000 mutex_lock(&per_pin->lock); 2001 per_pin->chmap_set = false; 2002 memset(per_pin->chmap, 0, sizeof(per_pin->chmap)); 2003 2004 per_pin->setup = false; 2005 per_pin->channels = 0; 2006 mutex_unlock(&per_pin->lock); 2007 unlock: 2008 mutex_unlock(&spec->pcm_lock); 2009 } 2010 2011 return err; 2012 } 2013 2014 static const struct hda_pcm_ops generic_ops = { 2015 .open = hdmi_pcm_open, 2016 .close = hdmi_pcm_close, 2017 .prepare = generic_hdmi_playback_pcm_prepare, 2018 .cleanup = generic_hdmi_playback_pcm_cleanup, 2019 }; 2020 2021 static int hdmi_get_spk_alloc(struct hdac_device *hdac, int pcm_idx) 2022 { 2023 struct hda_codec *codec = container_of(hdac, struct hda_codec, core); 2024 struct hdmi_spec *spec = codec->spec; 2025 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2026 2027 if (!per_pin) 2028 return 0; 2029 2030 return per_pin->sink_eld.info.spk_alloc; 2031 } 2032 2033 static void hdmi_get_chmap(struct hdac_device *hdac, int pcm_idx, 2034 unsigned char *chmap) 2035 { 2036 struct hda_codec *codec = container_of(hdac, struct hda_codec, core); 2037 struct hdmi_spec *spec = codec->spec; 2038 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2039 2040 /* chmap is already set to 0 in caller */ 2041 if (!per_pin) 2042 return; 2043 2044 memcpy(chmap, per_pin->chmap, ARRAY_SIZE(per_pin->chmap)); 2045 } 2046 2047 static void hdmi_set_chmap(struct hdac_device *hdac, int pcm_idx, 2048 unsigned char *chmap, int prepared) 2049 { 2050 struct hda_codec *codec = container_of(hdac, struct hda_codec, core); 2051 struct hdmi_spec *spec = codec->spec; 2052 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2053 2054 if (!per_pin) 2055 return; 2056 mutex_lock(&per_pin->lock); 2057 per_pin->chmap_set = true; 2058 memcpy(per_pin->chmap, chmap, ARRAY_SIZE(per_pin->chmap)); 2059 if (prepared) 2060 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm); 2061 mutex_unlock(&per_pin->lock); 2062 } 2063 2064 static bool is_hdmi_pcm_attached(struct hdac_device *hdac, int pcm_idx) 2065 { 2066 struct hda_codec *codec = container_of(hdac, struct hda_codec, core); 2067 struct hdmi_spec *spec = codec->spec; 2068 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2069 2070 return per_pin ? true:false; 2071 } 2072 2073 static int generic_hdmi_build_pcms(struct hda_codec *codec) 2074 { 2075 struct hdmi_spec *spec = codec->spec; 2076 int idx; 2077 2078 /* 2079 * for non-mst mode, pcm number is the same as before 2080 * for DP MST mode, pcm number is (nid number + dev_num - 1) 2081 * dev_num is the device entry number in a pin 2082 * 2083 */ 2084 for (idx = 0; idx < spec->num_nids + spec->dev_num - 1; idx++) { 2085 struct hda_pcm *info; 2086 struct hda_pcm_stream *pstr; 2087 2088 info = snd_hda_codec_pcm_new(codec, "HDMI %d", idx); 2089 if (!info) 2090 return -ENOMEM; 2091 2092 spec->pcm_rec[idx].pcm = info; 2093 spec->pcm_used++; 2094 info->pcm_type = HDA_PCM_TYPE_HDMI; 2095 info->own_chmap = true; 2096 2097 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK]; 2098 pstr->substreams = 1; 2099 pstr->ops = generic_ops; 2100 /* pcm number is less than 16 */ 2101 if (spec->pcm_used >= 16) 2102 break; 2103 /* other pstr fields are set in open */ 2104 } 2105 2106 return 0; 2107 } 2108 2109 static void free_hdmi_jack_priv(struct snd_jack *jack) 2110 { 2111 struct hdmi_pcm *pcm = jack->private_data; 2112 2113 pcm->jack = NULL; 2114 } 2115 2116 static int add_hdmi_jack_kctl(struct hda_codec *codec, 2117 struct hdmi_spec *spec, 2118 int pcm_idx, 2119 const char *name) 2120 { 2121 struct snd_jack *jack; 2122 int err; 2123 2124 err = snd_jack_new(codec->card, name, SND_JACK_AVOUT, &jack, 2125 true, false); 2126 if (err < 0) 2127 return err; 2128 2129 spec->pcm_rec[pcm_idx].jack = jack; 2130 jack->private_data = &spec->pcm_rec[pcm_idx]; 2131 jack->private_free = free_hdmi_jack_priv; 2132 return 0; 2133 } 2134 2135 static int generic_hdmi_build_jack(struct hda_codec *codec, int pcm_idx) 2136 { 2137 char hdmi_str[32] = "HDMI/DP"; 2138 struct hdmi_spec *spec = codec->spec; 2139 struct hdmi_spec_per_pin *per_pin; 2140 struct hda_jack_tbl *jack; 2141 int pcmdev = get_pcm_rec(spec, pcm_idx)->device; 2142 bool phantom_jack; 2143 int ret; 2144 2145 if (pcmdev > 0) 2146 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev); 2147 2148 if (spec->dyn_pcm_assign) 2149 return add_hdmi_jack_kctl(codec, spec, pcm_idx, hdmi_str); 2150 2151 /* for !dyn_pcm_assign, we still use hda_jack for compatibility */ 2152 /* if !dyn_pcm_assign, it must be non-MST mode. 2153 * This means pcms and pins are statically mapped. 2154 * And pcm_idx is pin_idx. 2155 */ 2156 per_pin = get_pin(spec, pcm_idx); 2157 phantom_jack = !is_jack_detectable(codec, per_pin->pin_nid); 2158 if (phantom_jack) 2159 strncat(hdmi_str, " Phantom", 2160 sizeof(hdmi_str) - strlen(hdmi_str) - 1); 2161 ret = snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str, 2162 phantom_jack, 0, NULL); 2163 if (ret < 0) 2164 return ret; 2165 jack = snd_hda_jack_tbl_get(codec, per_pin->pin_nid); 2166 if (jack == NULL) 2167 return 0; 2168 /* assign jack->jack to pcm_rec[].jack to 2169 * align with dyn_pcm_assign mode 2170 */ 2171 spec->pcm_rec[pcm_idx].jack = jack->jack; 2172 return 0; 2173 } 2174 2175 static int generic_hdmi_build_controls(struct hda_codec *codec) 2176 { 2177 struct hdmi_spec *spec = codec->spec; 2178 int dev, err; 2179 int pin_idx, pcm_idx; 2180 2181 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { 2182 if (!get_pcm_rec(spec, pcm_idx)->pcm) { 2183 /* no PCM: mark this for skipping permanently */ 2184 set_bit(pcm_idx, &spec->pcm_bitmap); 2185 continue; 2186 } 2187 2188 err = generic_hdmi_build_jack(codec, pcm_idx); 2189 if (err < 0) 2190 return err; 2191 2192 /* create the spdif for each pcm 2193 * pin will be bound when monitor is connected 2194 */ 2195 if (spec->dyn_pcm_assign) 2196 err = snd_hda_create_dig_out_ctls(codec, 2197 0, spec->cvt_nids[0], 2198 HDA_PCM_TYPE_HDMI); 2199 else { 2200 struct hdmi_spec_per_pin *per_pin = 2201 get_pin(spec, pcm_idx); 2202 err = snd_hda_create_dig_out_ctls(codec, 2203 per_pin->pin_nid, 2204 per_pin->mux_nids[0], 2205 HDA_PCM_TYPE_HDMI); 2206 } 2207 if (err < 0) 2208 return err; 2209 snd_hda_spdif_ctls_unassign(codec, pcm_idx); 2210 2211 dev = get_pcm_rec(spec, pcm_idx)->device; 2212 if (dev != SNDRV_PCM_INVALID_DEVICE) { 2213 /* add control for ELD Bytes */ 2214 err = hdmi_create_eld_ctl(codec, pcm_idx, dev); 2215 if (err < 0) 2216 return err; 2217 } 2218 } 2219 2220 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2221 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2222 2223 hdmi_present_sense(per_pin, 0); 2224 } 2225 2226 /* add channel maps */ 2227 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { 2228 struct hda_pcm *pcm; 2229 2230 pcm = get_pcm_rec(spec, pcm_idx); 2231 if (!pcm || !pcm->pcm) 2232 break; 2233 err = snd_hdac_add_chmap_ctls(pcm->pcm, pcm_idx, &spec->chmap); 2234 if (err < 0) 2235 return err; 2236 } 2237 2238 return 0; 2239 } 2240 2241 static int generic_hdmi_init_per_pins(struct hda_codec *codec) 2242 { 2243 struct hdmi_spec *spec = codec->spec; 2244 int pin_idx; 2245 2246 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2247 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2248 2249 per_pin->codec = codec; 2250 mutex_init(&per_pin->lock); 2251 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld); 2252 eld_proc_new(per_pin, pin_idx); 2253 } 2254 return 0; 2255 } 2256 2257 static int generic_hdmi_init(struct hda_codec *codec) 2258 { 2259 struct hdmi_spec *spec = codec->spec; 2260 int pin_idx; 2261 2262 mutex_lock(&spec->bind_lock); 2263 spec->use_jack_detect = !codec->jackpoll_interval; 2264 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2265 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2266 hda_nid_t pin_nid = per_pin->pin_nid; 2267 int dev_id = per_pin->dev_id; 2268 2269 snd_hda_set_dev_select(codec, pin_nid, dev_id); 2270 hdmi_init_pin(codec, pin_nid); 2271 if (codec_has_acomp(codec)) 2272 continue; 2273 if (spec->use_jack_detect) 2274 snd_hda_jack_detect_enable(codec, pin_nid); 2275 else 2276 snd_hda_jack_detect_enable_callback(codec, pin_nid, 2277 jack_callback); 2278 } 2279 mutex_unlock(&spec->bind_lock); 2280 return 0; 2281 } 2282 2283 static void hdmi_array_init(struct hdmi_spec *spec, int nums) 2284 { 2285 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums); 2286 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums); 2287 } 2288 2289 static void hdmi_array_free(struct hdmi_spec *spec) 2290 { 2291 snd_array_free(&spec->pins); 2292 snd_array_free(&spec->cvts); 2293 } 2294 2295 static void generic_spec_free(struct hda_codec *codec) 2296 { 2297 struct hdmi_spec *spec = codec->spec; 2298 2299 if (spec) { 2300 hdmi_array_free(spec); 2301 kfree(spec); 2302 codec->spec = NULL; 2303 } 2304 codec->dp_mst = false; 2305 } 2306 2307 static void generic_hdmi_free(struct hda_codec *codec) 2308 { 2309 struct hdmi_spec *spec = codec->spec; 2310 int pin_idx, pcm_idx; 2311 2312 if (spec->acomp_registered) { 2313 snd_hdac_acomp_exit(&codec->bus->core); 2314 } else if (codec_has_acomp(codec)) { 2315 snd_hdac_acomp_register_notifier(&codec->bus->core, NULL); 2316 codec->relaxed_resume = 0; 2317 } 2318 2319 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2320 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2321 cancel_delayed_work_sync(&per_pin->work); 2322 eld_proc_free(per_pin); 2323 } 2324 2325 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { 2326 if (spec->pcm_rec[pcm_idx].jack == NULL) 2327 continue; 2328 if (spec->dyn_pcm_assign) 2329 snd_device_free(codec->card, 2330 spec->pcm_rec[pcm_idx].jack); 2331 else 2332 spec->pcm_rec[pcm_idx].jack = NULL; 2333 } 2334 2335 generic_spec_free(codec); 2336 } 2337 2338 #ifdef CONFIG_PM 2339 static int generic_hdmi_resume(struct hda_codec *codec) 2340 { 2341 struct hdmi_spec *spec = codec->spec; 2342 int pin_idx; 2343 2344 codec->patch_ops.init(codec); 2345 regcache_sync(codec->core.regmap); 2346 2347 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2348 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2349 hdmi_present_sense(per_pin, 1); 2350 } 2351 return 0; 2352 } 2353 #endif 2354 2355 static const struct hda_codec_ops generic_hdmi_patch_ops = { 2356 .init = generic_hdmi_init, 2357 .free = generic_hdmi_free, 2358 .build_pcms = generic_hdmi_build_pcms, 2359 .build_controls = generic_hdmi_build_controls, 2360 .unsol_event = hdmi_unsol_event, 2361 #ifdef CONFIG_PM 2362 .resume = generic_hdmi_resume, 2363 #endif 2364 }; 2365 2366 static const struct hdmi_ops generic_standard_hdmi_ops = { 2367 .pin_get_eld = snd_hdmi_get_eld, 2368 .pin_setup_infoframe = hdmi_pin_setup_infoframe, 2369 .pin_hbr_setup = hdmi_pin_hbr_setup, 2370 .setup_stream = hdmi_setup_stream, 2371 }; 2372 2373 /* allocate codec->spec and assign/initialize generic parser ops */ 2374 static int alloc_generic_hdmi(struct hda_codec *codec) 2375 { 2376 struct hdmi_spec *spec; 2377 2378 spec = kzalloc(sizeof(*spec), GFP_KERNEL); 2379 if (!spec) 2380 return -ENOMEM; 2381 2382 spec->codec = codec; 2383 spec->ops = generic_standard_hdmi_ops; 2384 spec->dev_num = 1; /* initialize to 1 */ 2385 mutex_init(&spec->pcm_lock); 2386 mutex_init(&spec->bind_lock); 2387 snd_hdac_register_chmap_ops(&codec->core, &spec->chmap); 2388 2389 spec->chmap.ops.get_chmap = hdmi_get_chmap; 2390 spec->chmap.ops.set_chmap = hdmi_set_chmap; 2391 spec->chmap.ops.is_pcm_attached = is_hdmi_pcm_attached; 2392 spec->chmap.ops.get_spk_alloc = hdmi_get_spk_alloc, 2393 2394 codec->spec = spec; 2395 hdmi_array_init(spec, 4); 2396 2397 codec->patch_ops = generic_hdmi_patch_ops; 2398 2399 return 0; 2400 } 2401 2402 /* generic HDMI parser */ 2403 static int patch_generic_hdmi(struct hda_codec *codec) 2404 { 2405 int err; 2406 2407 err = alloc_generic_hdmi(codec); 2408 if (err < 0) 2409 return err; 2410 2411 err = hdmi_parse_codec(codec); 2412 if (err < 0) { 2413 generic_spec_free(codec); 2414 return err; 2415 } 2416 2417 generic_hdmi_init_per_pins(codec); 2418 return 0; 2419 } 2420 2421 /* 2422 * generic audio component binding 2423 */ 2424 2425 /* turn on / off the unsol event jack detection dynamically */ 2426 static void reprogram_jack_detect(struct hda_codec *codec, hda_nid_t nid, 2427 bool use_acomp) 2428 { 2429 struct hda_jack_tbl *tbl; 2430 2431 tbl = snd_hda_jack_tbl_get(codec, nid); 2432 if (tbl) { 2433 /* clear unsol even if component notifier is used, or re-enable 2434 * if notifier is cleared 2435 */ 2436 unsigned int val = use_acomp ? 0 : (AC_USRSP_EN | tbl->tag); 2437 snd_hda_codec_write_cache(codec, nid, 0, 2438 AC_VERB_SET_UNSOLICITED_ENABLE, val); 2439 } else { 2440 /* if no jack entry was defined beforehand, create a new one 2441 * at need (i.e. only when notifier is cleared) 2442 */ 2443 if (!use_acomp) 2444 snd_hda_jack_detect_enable(codec, nid); 2445 } 2446 } 2447 2448 /* set up / clear component notifier dynamically */ 2449 static void generic_acomp_notifier_set(struct drm_audio_component *acomp, 2450 bool use_acomp) 2451 { 2452 struct hdmi_spec *spec; 2453 int i; 2454 2455 spec = container_of(acomp->audio_ops, struct hdmi_spec, drm_audio_ops); 2456 mutex_lock(&spec->bind_lock); 2457 spec->use_acomp_notifier = use_acomp; 2458 spec->codec->relaxed_resume = use_acomp; 2459 /* reprogram each jack detection logic depending on the notifier */ 2460 if (spec->use_jack_detect) { 2461 for (i = 0; i < spec->num_pins; i++) 2462 reprogram_jack_detect(spec->codec, 2463 get_pin(spec, i)->pin_nid, 2464 use_acomp); 2465 } 2466 mutex_unlock(&spec->bind_lock); 2467 } 2468 2469 /* enable / disable the notifier via master bind / unbind */ 2470 static int generic_acomp_master_bind(struct device *dev, 2471 struct drm_audio_component *acomp) 2472 { 2473 generic_acomp_notifier_set(acomp, true); 2474 return 0; 2475 } 2476 2477 static void generic_acomp_master_unbind(struct device *dev, 2478 struct drm_audio_component *acomp) 2479 { 2480 generic_acomp_notifier_set(acomp, false); 2481 } 2482 2483 /* check whether both HD-audio and DRM PCI devices belong to the same bus */ 2484 static int match_bound_vga(struct device *dev, int subtype, void *data) 2485 { 2486 struct hdac_bus *bus = data; 2487 struct pci_dev *pci, *master; 2488 2489 if (!dev_is_pci(dev) || !dev_is_pci(bus->dev)) 2490 return 0; 2491 master = to_pci_dev(bus->dev); 2492 pci = to_pci_dev(dev); 2493 return master->bus == pci->bus; 2494 } 2495 2496 /* audio component notifier for AMD/Nvidia HDMI codecs */ 2497 static void generic_acomp_pin_eld_notify(void *audio_ptr, int port, int dev_id) 2498 { 2499 struct hda_codec *codec = audio_ptr; 2500 struct hdmi_spec *spec = codec->spec; 2501 hda_nid_t pin_nid = spec->port2pin(codec, port); 2502 2503 if (!pin_nid) 2504 return; 2505 if (get_wcaps_type(get_wcaps(codec, pin_nid)) != AC_WID_PIN) 2506 return; 2507 /* skip notification during system suspend (but not in runtime PM); 2508 * the state will be updated at resume 2509 */ 2510 if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0) 2511 return; 2512 /* ditto during suspend/resume process itself */ 2513 if (snd_hdac_is_in_pm(&codec->core)) 2514 return; 2515 2516 check_presence_and_report(codec, pin_nid, dev_id); 2517 } 2518 2519 /* set up the private drm_audio_ops from the template */ 2520 static void setup_drm_audio_ops(struct hda_codec *codec, 2521 const struct drm_audio_component_audio_ops *ops) 2522 { 2523 struct hdmi_spec *spec = codec->spec; 2524 2525 spec->drm_audio_ops.audio_ptr = codec; 2526 /* intel_audio_codec_enable() or intel_audio_codec_disable() 2527 * will call pin_eld_notify with using audio_ptr pointer 2528 * We need make sure audio_ptr is really setup 2529 */ 2530 wmb(); 2531 spec->drm_audio_ops.pin2port = ops->pin2port; 2532 spec->drm_audio_ops.pin_eld_notify = ops->pin_eld_notify; 2533 spec->drm_audio_ops.master_bind = ops->master_bind; 2534 spec->drm_audio_ops.master_unbind = ops->master_unbind; 2535 } 2536 2537 /* initialize the generic HDMI audio component */ 2538 static void generic_acomp_init(struct hda_codec *codec, 2539 const struct drm_audio_component_audio_ops *ops, 2540 int (*port2pin)(struct hda_codec *, int)) 2541 { 2542 struct hdmi_spec *spec = codec->spec; 2543 2544 spec->port2pin = port2pin; 2545 setup_drm_audio_ops(codec, ops); 2546 if (!snd_hdac_acomp_init(&codec->bus->core, &spec->drm_audio_ops, 2547 match_bound_vga, 0)) { 2548 spec->acomp_registered = true; 2549 codec->bus->keep_power = 0; 2550 } 2551 } 2552 2553 /* 2554 * Intel codec parsers and helpers 2555 */ 2556 2557 static void intel_haswell_fixup_connect_list(struct hda_codec *codec, 2558 hda_nid_t nid) 2559 { 2560 struct hdmi_spec *spec = codec->spec; 2561 hda_nid_t conns[4]; 2562 int nconns; 2563 2564 nconns = snd_hda_get_connections(codec, nid, conns, ARRAY_SIZE(conns)); 2565 if (nconns == spec->num_cvts && 2566 !memcmp(conns, spec->cvt_nids, spec->num_cvts * sizeof(hda_nid_t))) 2567 return; 2568 2569 /* override pins connection list */ 2570 codec_dbg(codec, "hdmi: haswell: override pin connection 0x%x\n", nid); 2571 snd_hda_override_conn_list(codec, nid, spec->num_cvts, spec->cvt_nids); 2572 } 2573 2574 #define INTEL_GET_VENDOR_VERB 0xf81 2575 #define INTEL_SET_VENDOR_VERB 0x781 2576 #define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */ 2577 #define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */ 2578 2579 static void intel_haswell_enable_all_pins(struct hda_codec *codec, 2580 bool update_tree) 2581 { 2582 unsigned int vendor_param; 2583 struct hdmi_spec *spec = codec->spec; 2584 2585 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0, 2586 INTEL_GET_VENDOR_VERB, 0); 2587 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS) 2588 return; 2589 2590 vendor_param |= INTEL_EN_ALL_PIN_CVTS; 2591 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0, 2592 INTEL_SET_VENDOR_VERB, vendor_param); 2593 if (vendor_param == -1) 2594 return; 2595 2596 if (update_tree) 2597 snd_hda_codec_update_widgets(codec); 2598 } 2599 2600 static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec) 2601 { 2602 unsigned int vendor_param; 2603 struct hdmi_spec *spec = codec->spec; 2604 2605 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0, 2606 INTEL_GET_VENDOR_VERB, 0); 2607 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12) 2608 return; 2609 2610 /* enable DP1.2 mode */ 2611 vendor_param |= INTEL_EN_DP12; 2612 snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB); 2613 snd_hda_codec_write_cache(codec, spec->vendor_nid, 0, 2614 INTEL_SET_VENDOR_VERB, vendor_param); 2615 } 2616 2617 /* Haswell needs to re-issue the vendor-specific verbs before turning to D0. 2618 * Otherwise you may get severe h/w communication errors. 2619 */ 2620 static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg, 2621 unsigned int power_state) 2622 { 2623 if (power_state == AC_PWRST_D0) { 2624 intel_haswell_enable_all_pins(codec, false); 2625 intel_haswell_fixup_enable_dp12(codec); 2626 } 2627 2628 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state); 2629 snd_hda_codec_set_power_to_all(codec, fg, power_state); 2630 } 2631 2632 /* There is a fixed mapping between audio pin node and display port. 2633 * on SNB, IVY, HSW, BSW, SKL, BXT, KBL: 2634 * Pin Widget 5 - PORT B (port = 1 in i915 driver) 2635 * Pin Widget 6 - PORT C (port = 2 in i915 driver) 2636 * Pin Widget 7 - PORT D (port = 3 in i915 driver) 2637 * 2638 * on VLV, ILK: 2639 * Pin Widget 4 - PORT B (port = 1 in i915 driver) 2640 * Pin Widget 5 - PORT C (port = 2 in i915 driver) 2641 * Pin Widget 6 - PORT D (port = 3 in i915 driver) 2642 */ 2643 static int intel_base_nid(struct hda_codec *codec) 2644 { 2645 switch (codec->core.vendor_id) { 2646 case 0x80860054: /* ILK */ 2647 case 0x80862804: /* ILK */ 2648 case 0x80862882: /* VLV */ 2649 return 4; 2650 default: 2651 return 5; 2652 } 2653 } 2654 2655 static int intel_pin2port(void *audio_ptr, int pin_nid) 2656 { 2657 struct hda_codec *codec = audio_ptr; 2658 struct hdmi_spec *spec = codec->spec; 2659 int base_nid, i; 2660 2661 if (!spec->port_num) { 2662 base_nid = intel_base_nid(codec); 2663 if (WARN_ON(pin_nid < base_nid || pin_nid >= base_nid + 3)) 2664 return -1; 2665 return pin_nid - base_nid + 1; /* intel port is 1-based */ 2666 } 2667 2668 /* 2669 * looking for the pin number in the mapping table and return 2670 * the index which indicate the port number 2671 */ 2672 for (i = 0; i < spec->port_num; i++) { 2673 if (pin_nid == spec->port_map[i]) 2674 return i + 1; 2675 } 2676 2677 /* return -1 if pin number exceeds our expectation */ 2678 codec_info(codec, "Can't find the HDMI/DP port for pin %d\n", pin_nid); 2679 return -1; 2680 } 2681 2682 static int intel_port2pin(struct hda_codec *codec, int port) 2683 { 2684 struct hdmi_spec *spec = codec->spec; 2685 2686 if (!spec->port_num) { 2687 /* we assume only from port-B to port-D */ 2688 if (port < 1 || port > 3) 2689 return 0; 2690 /* intel port is 1-based */ 2691 return port + intel_base_nid(codec) - 1; 2692 } 2693 2694 if (port < 1 || port > spec->port_num) 2695 return 0; 2696 return spec->port_map[port - 1]; 2697 } 2698 2699 static void intel_pin_eld_notify(void *audio_ptr, int port, int pipe) 2700 { 2701 struct hda_codec *codec = audio_ptr; 2702 int pin_nid; 2703 int dev_id = pipe; 2704 2705 pin_nid = intel_port2pin(codec, port); 2706 if (!pin_nid) 2707 return; 2708 /* skip notification during system suspend (but not in runtime PM); 2709 * the state will be updated at resume 2710 */ 2711 if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0) 2712 return; 2713 /* ditto during suspend/resume process itself */ 2714 if (snd_hdac_is_in_pm(&codec->core)) 2715 return; 2716 2717 snd_hdac_i915_set_bclk(&codec->bus->core); 2718 check_presence_and_report(codec, pin_nid, dev_id); 2719 } 2720 2721 static const struct drm_audio_component_audio_ops intel_audio_ops = { 2722 .pin2port = intel_pin2port, 2723 .pin_eld_notify = intel_pin_eld_notify, 2724 }; 2725 2726 /* register i915 component pin_eld_notify callback */ 2727 static void register_i915_notifier(struct hda_codec *codec) 2728 { 2729 struct hdmi_spec *spec = codec->spec; 2730 2731 spec->use_acomp_notifier = true; 2732 spec->port2pin = intel_port2pin; 2733 setup_drm_audio_ops(codec, &intel_audio_ops); 2734 snd_hdac_acomp_register_notifier(&codec->bus->core, 2735 &spec->drm_audio_ops); 2736 /* no need for forcible resume for jack check thanks to notifier */ 2737 codec->relaxed_resume = 1; 2738 } 2739 2740 /* setup_stream ops override for HSW+ */ 2741 static int i915_hsw_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, 2742 hda_nid_t pin_nid, u32 stream_tag, int format) 2743 { 2744 haswell_verify_D0(codec, cvt_nid, pin_nid); 2745 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format); 2746 } 2747 2748 /* pin_cvt_fixup ops override for HSW+ and VLV+ */ 2749 static void i915_pin_cvt_fixup(struct hda_codec *codec, 2750 struct hdmi_spec_per_pin *per_pin, 2751 hda_nid_t cvt_nid) 2752 { 2753 if (per_pin) { 2754 snd_hda_set_dev_select(codec, per_pin->pin_nid, 2755 per_pin->dev_id); 2756 intel_verify_pin_cvt_connect(codec, per_pin); 2757 intel_not_share_assigned_cvt(codec, per_pin->pin_nid, 2758 per_pin->dev_id, per_pin->mux_idx); 2759 } else { 2760 intel_not_share_assigned_cvt_nid(codec, 0, 0, cvt_nid); 2761 } 2762 } 2763 2764 /* precondition and allocation for Intel codecs */ 2765 static int alloc_intel_hdmi(struct hda_codec *codec) 2766 { 2767 int err; 2768 2769 /* requires i915 binding */ 2770 if (!codec->bus->core.audio_component) { 2771 codec_info(codec, "No i915 binding for Intel HDMI/DP codec\n"); 2772 /* set probe_id here to prevent generic fallback binding */ 2773 codec->probe_id = HDA_CODEC_ID_SKIP_PROBE; 2774 return -ENODEV; 2775 } 2776 2777 err = alloc_generic_hdmi(codec); 2778 if (err < 0) 2779 return err; 2780 /* no need to handle unsol events */ 2781 codec->patch_ops.unsol_event = NULL; 2782 return 0; 2783 } 2784 2785 /* parse and post-process for Intel codecs */ 2786 static int parse_intel_hdmi(struct hda_codec *codec) 2787 { 2788 int err; 2789 2790 err = hdmi_parse_codec(codec); 2791 if (err < 0) { 2792 generic_spec_free(codec); 2793 return err; 2794 } 2795 2796 generic_hdmi_init_per_pins(codec); 2797 register_i915_notifier(codec); 2798 return 0; 2799 } 2800 2801 /* Intel Haswell and onwards; audio component with eld notifier */ 2802 static int intel_hsw_common_init(struct hda_codec *codec, hda_nid_t vendor_nid, 2803 const int *port_map, int port_num) 2804 { 2805 struct hdmi_spec *spec; 2806 int err; 2807 2808 err = alloc_intel_hdmi(codec); 2809 if (err < 0) 2810 return err; 2811 spec = codec->spec; 2812 codec->dp_mst = true; 2813 spec->dyn_pcm_assign = true; 2814 spec->vendor_nid = vendor_nid; 2815 spec->port_map = port_map; 2816 spec->port_num = port_num; 2817 2818 intel_haswell_enable_all_pins(codec, true); 2819 intel_haswell_fixup_enable_dp12(codec); 2820 2821 codec->display_power_control = 1; 2822 2823 codec->patch_ops.set_power_state = haswell_set_power_state; 2824 codec->depop_delay = 0; 2825 codec->auto_runtime_pm = 1; 2826 2827 spec->ops.setup_stream = i915_hsw_setup_stream; 2828 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup; 2829 2830 return parse_intel_hdmi(codec); 2831 } 2832 2833 static int patch_i915_hsw_hdmi(struct hda_codec *codec) 2834 { 2835 return intel_hsw_common_init(codec, 0x08, NULL, 0); 2836 } 2837 2838 static int patch_i915_glk_hdmi(struct hda_codec *codec) 2839 { 2840 return intel_hsw_common_init(codec, 0x0b, NULL, 0); 2841 } 2842 2843 static int patch_i915_icl_hdmi(struct hda_codec *codec) 2844 { 2845 /* 2846 * pin to port mapping table where the value indicate the pin number and 2847 * the index indicate the port number with 1 base. 2848 */ 2849 static const int map[] = {0x4, 0x6, 0x8, 0xa, 0xb}; 2850 2851 return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map)); 2852 } 2853 2854 static int patch_i915_tgl_hdmi(struct hda_codec *codec) 2855 { 2856 /* 2857 * pin to port mapping table where the value indicate the pin number and 2858 * the index indicate the port number with 1 base. 2859 */ 2860 static const int map[] = {0x4, 0x6, 0x8, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf}; 2861 2862 return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map)); 2863 } 2864 2865 2866 /* Intel Baytrail and Braswell; with eld notifier */ 2867 static int patch_i915_byt_hdmi(struct hda_codec *codec) 2868 { 2869 struct hdmi_spec *spec; 2870 int err; 2871 2872 err = alloc_intel_hdmi(codec); 2873 if (err < 0) 2874 return err; 2875 spec = codec->spec; 2876 2877 /* For Valleyview/Cherryview, only the display codec is in the display 2878 * power well and can use link_power ops to request/release the power. 2879 */ 2880 codec->display_power_control = 1; 2881 2882 codec->depop_delay = 0; 2883 codec->auto_runtime_pm = 1; 2884 2885 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup; 2886 2887 return parse_intel_hdmi(codec); 2888 } 2889 2890 /* Intel IronLake, SandyBridge and IvyBridge; with eld notifier */ 2891 static int patch_i915_cpt_hdmi(struct hda_codec *codec) 2892 { 2893 int err; 2894 2895 err = alloc_intel_hdmi(codec); 2896 if (err < 0) 2897 return err; 2898 return parse_intel_hdmi(codec); 2899 } 2900 2901 /* 2902 * Shared non-generic implementations 2903 */ 2904 2905 static int simple_playback_build_pcms(struct hda_codec *codec) 2906 { 2907 struct hdmi_spec *spec = codec->spec; 2908 struct hda_pcm *info; 2909 unsigned int chans; 2910 struct hda_pcm_stream *pstr; 2911 struct hdmi_spec_per_cvt *per_cvt; 2912 2913 per_cvt = get_cvt(spec, 0); 2914 chans = get_wcaps(codec, per_cvt->cvt_nid); 2915 chans = get_wcaps_channels(chans); 2916 2917 info = snd_hda_codec_pcm_new(codec, "HDMI 0"); 2918 if (!info) 2919 return -ENOMEM; 2920 spec->pcm_rec[0].pcm = info; 2921 info->pcm_type = HDA_PCM_TYPE_HDMI; 2922 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK]; 2923 *pstr = spec->pcm_playback; 2924 pstr->nid = per_cvt->cvt_nid; 2925 if (pstr->channels_max <= 2 && chans && chans <= 16) 2926 pstr->channels_max = chans; 2927 2928 return 0; 2929 } 2930 2931 /* unsolicited event for jack sensing */ 2932 static void simple_hdmi_unsol_event(struct hda_codec *codec, 2933 unsigned int res) 2934 { 2935 snd_hda_jack_set_dirty_all(codec); 2936 snd_hda_jack_report_sync(codec); 2937 } 2938 2939 /* generic_hdmi_build_jack can be used for simple_hdmi, too, 2940 * as long as spec->pins[] is set correctly 2941 */ 2942 #define simple_hdmi_build_jack generic_hdmi_build_jack 2943 2944 static int simple_playback_build_controls(struct hda_codec *codec) 2945 { 2946 struct hdmi_spec *spec = codec->spec; 2947 struct hdmi_spec_per_cvt *per_cvt; 2948 int err; 2949 2950 per_cvt = get_cvt(spec, 0); 2951 err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid, 2952 per_cvt->cvt_nid, 2953 HDA_PCM_TYPE_HDMI); 2954 if (err < 0) 2955 return err; 2956 return simple_hdmi_build_jack(codec, 0); 2957 } 2958 2959 static int simple_playback_init(struct hda_codec *codec) 2960 { 2961 struct hdmi_spec *spec = codec->spec; 2962 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0); 2963 hda_nid_t pin = per_pin->pin_nid; 2964 2965 snd_hda_codec_write(codec, pin, 0, 2966 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT); 2967 /* some codecs require to unmute the pin */ 2968 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP) 2969 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE, 2970 AMP_OUT_UNMUTE); 2971 snd_hda_jack_detect_enable(codec, pin); 2972 return 0; 2973 } 2974 2975 static void simple_playback_free(struct hda_codec *codec) 2976 { 2977 struct hdmi_spec *spec = codec->spec; 2978 2979 hdmi_array_free(spec); 2980 kfree(spec); 2981 } 2982 2983 /* 2984 * Nvidia specific implementations 2985 */ 2986 2987 #define Nv_VERB_SET_Channel_Allocation 0xF79 2988 #define Nv_VERB_SET_Info_Frame_Checksum 0xF7A 2989 #define Nv_VERB_SET_Audio_Protection_On 0xF98 2990 #define Nv_VERB_SET_Audio_Protection_Off 0xF99 2991 2992 #define nvhdmi_master_con_nid_7x 0x04 2993 #define nvhdmi_master_pin_nid_7x 0x05 2994 2995 static const hda_nid_t nvhdmi_con_nids_7x[4] = { 2996 /*front, rear, clfe, rear_surr */ 2997 0x6, 0x8, 0xa, 0xc, 2998 }; 2999 3000 static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = { 3001 /* set audio protect on */ 3002 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1}, 3003 /* enable digital output on pin widget */ 3004 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3005 {} /* terminator */ 3006 }; 3007 3008 static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = { 3009 /* set audio protect on */ 3010 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1}, 3011 /* enable digital output on pin widget */ 3012 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3013 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3014 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3015 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3016 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3017 {} /* terminator */ 3018 }; 3019 3020 #ifdef LIMITED_RATE_FMT_SUPPORT 3021 /* support only the safe format and rate */ 3022 #define SUPPORTED_RATES SNDRV_PCM_RATE_48000 3023 #define SUPPORTED_MAXBPS 16 3024 #define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE 3025 #else 3026 /* support all rates and formats */ 3027 #define SUPPORTED_RATES \ 3028 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\ 3029 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\ 3030 SNDRV_PCM_RATE_192000) 3031 #define SUPPORTED_MAXBPS 24 3032 #define SUPPORTED_FORMATS \ 3033 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE) 3034 #endif 3035 3036 static int nvhdmi_7x_init_2ch(struct hda_codec *codec) 3037 { 3038 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch); 3039 return 0; 3040 } 3041 3042 static int nvhdmi_7x_init_8ch(struct hda_codec *codec) 3043 { 3044 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch); 3045 return 0; 3046 } 3047 3048 static const unsigned int channels_2_6_8[] = { 3049 2, 6, 8 3050 }; 3051 3052 static const unsigned int channels_2_8[] = { 3053 2, 8 3054 }; 3055 3056 static const struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = { 3057 .count = ARRAY_SIZE(channels_2_6_8), 3058 .list = channels_2_6_8, 3059 .mask = 0, 3060 }; 3061 3062 static const struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = { 3063 .count = ARRAY_SIZE(channels_2_8), 3064 .list = channels_2_8, 3065 .mask = 0, 3066 }; 3067 3068 static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo, 3069 struct hda_codec *codec, 3070 struct snd_pcm_substream *substream) 3071 { 3072 struct hdmi_spec *spec = codec->spec; 3073 const struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL; 3074 3075 switch (codec->preset->vendor_id) { 3076 case 0x10de0002: 3077 case 0x10de0003: 3078 case 0x10de0005: 3079 case 0x10de0006: 3080 hw_constraints_channels = &hw_constraints_2_8_channels; 3081 break; 3082 case 0x10de0007: 3083 hw_constraints_channels = &hw_constraints_2_6_8_channels; 3084 break; 3085 default: 3086 break; 3087 } 3088 3089 if (hw_constraints_channels != NULL) { 3090 snd_pcm_hw_constraint_list(substream->runtime, 0, 3091 SNDRV_PCM_HW_PARAM_CHANNELS, 3092 hw_constraints_channels); 3093 } else { 3094 snd_pcm_hw_constraint_step(substream->runtime, 0, 3095 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 3096 } 3097 3098 return snd_hda_multi_out_dig_open(codec, &spec->multiout); 3099 } 3100 3101 static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo, 3102 struct hda_codec *codec, 3103 struct snd_pcm_substream *substream) 3104 { 3105 struct hdmi_spec *spec = codec->spec; 3106 return snd_hda_multi_out_dig_close(codec, &spec->multiout); 3107 } 3108 3109 static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 3110 struct hda_codec *codec, 3111 unsigned int stream_tag, 3112 unsigned int format, 3113 struct snd_pcm_substream *substream) 3114 { 3115 struct hdmi_spec *spec = codec->spec; 3116 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout, 3117 stream_tag, format, substream); 3118 } 3119 3120 static const struct hda_pcm_stream simple_pcm_playback = { 3121 .substreams = 1, 3122 .channels_min = 2, 3123 .channels_max = 2, 3124 .ops = { 3125 .open = simple_playback_pcm_open, 3126 .close = simple_playback_pcm_close, 3127 .prepare = simple_playback_pcm_prepare 3128 }, 3129 }; 3130 3131 static const struct hda_codec_ops simple_hdmi_patch_ops = { 3132 .build_controls = simple_playback_build_controls, 3133 .build_pcms = simple_playback_build_pcms, 3134 .init = simple_playback_init, 3135 .free = simple_playback_free, 3136 .unsol_event = simple_hdmi_unsol_event, 3137 }; 3138 3139 static int patch_simple_hdmi(struct hda_codec *codec, 3140 hda_nid_t cvt_nid, hda_nid_t pin_nid) 3141 { 3142 struct hdmi_spec *spec; 3143 struct hdmi_spec_per_cvt *per_cvt; 3144 struct hdmi_spec_per_pin *per_pin; 3145 3146 spec = kzalloc(sizeof(*spec), GFP_KERNEL); 3147 if (!spec) 3148 return -ENOMEM; 3149 3150 spec->codec = codec; 3151 codec->spec = spec; 3152 hdmi_array_init(spec, 1); 3153 3154 spec->multiout.num_dacs = 0; /* no analog */ 3155 spec->multiout.max_channels = 2; 3156 spec->multiout.dig_out_nid = cvt_nid; 3157 spec->num_cvts = 1; 3158 spec->num_pins = 1; 3159 per_pin = snd_array_new(&spec->pins); 3160 per_cvt = snd_array_new(&spec->cvts); 3161 if (!per_pin || !per_cvt) { 3162 simple_playback_free(codec); 3163 return -ENOMEM; 3164 } 3165 per_cvt->cvt_nid = cvt_nid; 3166 per_pin->pin_nid = pin_nid; 3167 spec->pcm_playback = simple_pcm_playback; 3168 3169 codec->patch_ops = simple_hdmi_patch_ops; 3170 3171 return 0; 3172 } 3173 3174 static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec, 3175 int channels) 3176 { 3177 unsigned int chanmask; 3178 int chan = channels ? (channels - 1) : 1; 3179 3180 switch (channels) { 3181 default: 3182 case 0: 3183 case 2: 3184 chanmask = 0x00; 3185 break; 3186 case 4: 3187 chanmask = 0x08; 3188 break; 3189 case 6: 3190 chanmask = 0x0b; 3191 break; 3192 case 8: 3193 chanmask = 0x13; 3194 break; 3195 } 3196 3197 /* Set the audio infoframe channel allocation and checksum fields. The 3198 * channel count is computed implicitly by the hardware. */ 3199 snd_hda_codec_write(codec, 0x1, 0, 3200 Nv_VERB_SET_Channel_Allocation, chanmask); 3201 3202 snd_hda_codec_write(codec, 0x1, 0, 3203 Nv_VERB_SET_Info_Frame_Checksum, 3204 (0x71 - chan - chanmask)); 3205 } 3206 3207 static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo, 3208 struct hda_codec *codec, 3209 struct snd_pcm_substream *substream) 3210 { 3211 struct hdmi_spec *spec = codec->spec; 3212 int i; 3213 3214 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 3215 0, AC_VERB_SET_CHANNEL_STREAMID, 0); 3216 for (i = 0; i < 4; i++) { 3217 /* set the stream id */ 3218 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0, 3219 AC_VERB_SET_CHANNEL_STREAMID, 0); 3220 /* set the stream format */ 3221 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0, 3222 AC_VERB_SET_STREAM_FORMAT, 0); 3223 } 3224 3225 /* The audio hardware sends a channel count of 0x7 (8ch) when all the 3226 * streams are disabled. */ 3227 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8); 3228 3229 return snd_hda_multi_out_dig_close(codec, &spec->multiout); 3230 } 3231 3232 static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo, 3233 struct hda_codec *codec, 3234 unsigned int stream_tag, 3235 unsigned int format, 3236 struct snd_pcm_substream *substream) 3237 { 3238 int chs; 3239 unsigned int dataDCC2, channel_id; 3240 int i; 3241 struct hdmi_spec *spec = codec->spec; 3242 struct hda_spdif_out *spdif; 3243 struct hdmi_spec_per_cvt *per_cvt; 3244 3245 mutex_lock(&codec->spdif_mutex); 3246 per_cvt = get_cvt(spec, 0); 3247 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid); 3248 3249 chs = substream->runtime->channels; 3250 3251 dataDCC2 = 0x2; 3252 3253 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */ 3254 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) 3255 snd_hda_codec_write(codec, 3256 nvhdmi_master_con_nid_7x, 3257 0, 3258 AC_VERB_SET_DIGI_CONVERT_1, 3259 spdif->ctls & ~AC_DIG1_ENABLE & 0xff); 3260 3261 /* set the stream id */ 3262 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0, 3263 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0); 3264 3265 /* set the stream format */ 3266 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0, 3267 AC_VERB_SET_STREAM_FORMAT, format); 3268 3269 /* turn on again (if needed) */ 3270 /* enable and set the channel status audio/data flag */ 3271 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) { 3272 snd_hda_codec_write(codec, 3273 nvhdmi_master_con_nid_7x, 3274 0, 3275 AC_VERB_SET_DIGI_CONVERT_1, 3276 spdif->ctls & 0xff); 3277 snd_hda_codec_write(codec, 3278 nvhdmi_master_con_nid_7x, 3279 0, 3280 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2); 3281 } 3282 3283 for (i = 0; i < 4; i++) { 3284 if (chs == 2) 3285 channel_id = 0; 3286 else 3287 channel_id = i * 2; 3288 3289 /* turn off SPDIF once; 3290 *otherwise the IEC958 bits won't be updated 3291 */ 3292 if (codec->spdif_status_reset && 3293 (spdif->ctls & AC_DIG1_ENABLE)) 3294 snd_hda_codec_write(codec, 3295 nvhdmi_con_nids_7x[i], 3296 0, 3297 AC_VERB_SET_DIGI_CONVERT_1, 3298 spdif->ctls & ~AC_DIG1_ENABLE & 0xff); 3299 /* set the stream id */ 3300 snd_hda_codec_write(codec, 3301 nvhdmi_con_nids_7x[i], 3302 0, 3303 AC_VERB_SET_CHANNEL_STREAMID, 3304 (stream_tag << 4) | channel_id); 3305 /* set the stream format */ 3306 snd_hda_codec_write(codec, 3307 nvhdmi_con_nids_7x[i], 3308 0, 3309 AC_VERB_SET_STREAM_FORMAT, 3310 format); 3311 /* turn on again (if needed) */ 3312 /* enable and set the channel status audio/data flag */ 3313 if (codec->spdif_status_reset && 3314 (spdif->ctls & AC_DIG1_ENABLE)) { 3315 snd_hda_codec_write(codec, 3316 nvhdmi_con_nids_7x[i], 3317 0, 3318 AC_VERB_SET_DIGI_CONVERT_1, 3319 spdif->ctls & 0xff); 3320 snd_hda_codec_write(codec, 3321 nvhdmi_con_nids_7x[i], 3322 0, 3323 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2); 3324 } 3325 } 3326 3327 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs); 3328 3329 mutex_unlock(&codec->spdif_mutex); 3330 return 0; 3331 } 3332 3333 static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = { 3334 .substreams = 1, 3335 .channels_min = 2, 3336 .channels_max = 8, 3337 .nid = nvhdmi_master_con_nid_7x, 3338 .rates = SUPPORTED_RATES, 3339 .maxbps = SUPPORTED_MAXBPS, 3340 .formats = SUPPORTED_FORMATS, 3341 .ops = { 3342 .open = simple_playback_pcm_open, 3343 .close = nvhdmi_8ch_7x_pcm_close, 3344 .prepare = nvhdmi_8ch_7x_pcm_prepare 3345 }, 3346 }; 3347 3348 static int patch_nvhdmi_2ch(struct hda_codec *codec) 3349 { 3350 struct hdmi_spec *spec; 3351 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x, 3352 nvhdmi_master_pin_nid_7x); 3353 if (err < 0) 3354 return err; 3355 3356 codec->patch_ops.init = nvhdmi_7x_init_2ch; 3357 /* override the PCM rates, etc, as the codec doesn't give full list */ 3358 spec = codec->spec; 3359 spec->pcm_playback.rates = SUPPORTED_RATES; 3360 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS; 3361 spec->pcm_playback.formats = SUPPORTED_FORMATS; 3362 return 0; 3363 } 3364 3365 static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec) 3366 { 3367 struct hdmi_spec *spec = codec->spec; 3368 int err = simple_playback_build_pcms(codec); 3369 if (!err) { 3370 struct hda_pcm *info = get_pcm_rec(spec, 0); 3371 info->own_chmap = true; 3372 } 3373 return err; 3374 } 3375 3376 static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec) 3377 { 3378 struct hdmi_spec *spec = codec->spec; 3379 struct hda_pcm *info; 3380 struct snd_pcm_chmap *chmap; 3381 int err; 3382 3383 err = simple_playback_build_controls(codec); 3384 if (err < 0) 3385 return err; 3386 3387 /* add channel maps */ 3388 info = get_pcm_rec(spec, 0); 3389 err = snd_pcm_add_chmap_ctls(info->pcm, 3390 SNDRV_PCM_STREAM_PLAYBACK, 3391 snd_pcm_alt_chmaps, 8, 0, &chmap); 3392 if (err < 0) 3393 return err; 3394 switch (codec->preset->vendor_id) { 3395 case 0x10de0002: 3396 case 0x10de0003: 3397 case 0x10de0005: 3398 case 0x10de0006: 3399 chmap->channel_mask = (1U << 2) | (1U << 8); 3400 break; 3401 case 0x10de0007: 3402 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8); 3403 } 3404 return 0; 3405 } 3406 3407 static int patch_nvhdmi_8ch_7x(struct hda_codec *codec) 3408 { 3409 struct hdmi_spec *spec; 3410 int err = patch_nvhdmi_2ch(codec); 3411 if (err < 0) 3412 return err; 3413 spec = codec->spec; 3414 spec->multiout.max_channels = 8; 3415 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x; 3416 codec->patch_ops.init = nvhdmi_7x_init_8ch; 3417 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms; 3418 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls; 3419 3420 /* Initialize the audio infoframe channel mask and checksum to something 3421 * valid */ 3422 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8); 3423 3424 return 0; 3425 } 3426 3427 /* 3428 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on: 3429 * - 0x10de0015 3430 * - 0x10de0040 3431 */ 3432 static int nvhdmi_chmap_cea_alloc_validate_get_type(struct hdac_chmap *chmap, 3433 struct hdac_cea_channel_speaker_allocation *cap, int channels) 3434 { 3435 if (cap->ca_index == 0x00 && channels == 2) 3436 return SNDRV_CTL_TLVT_CHMAP_FIXED; 3437 3438 /* If the speaker allocation matches the channel count, it is OK. */ 3439 if (cap->channels != channels) 3440 return -1; 3441 3442 /* all channels are remappable freely */ 3443 return SNDRV_CTL_TLVT_CHMAP_VAR; 3444 } 3445 3446 static int nvhdmi_chmap_validate(struct hdac_chmap *chmap, 3447 int ca, int chs, unsigned char *map) 3448 { 3449 if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR)) 3450 return -EINVAL; 3451 3452 return 0; 3453 } 3454 3455 /* map from pin NID to port; port is 0-based */ 3456 /* for Nvidia: assume widget NID starting from 4, with step 1 (4, 5, 6, ...) */ 3457 static int nvhdmi_pin2port(void *audio_ptr, int pin_nid) 3458 { 3459 return pin_nid - 4; 3460 } 3461 3462 /* reverse-map from port to pin NID: see above */ 3463 static int nvhdmi_port2pin(struct hda_codec *codec, int port) 3464 { 3465 return port + 4; 3466 } 3467 3468 static const struct drm_audio_component_audio_ops nvhdmi_audio_ops = { 3469 .pin2port = nvhdmi_pin2port, 3470 .pin_eld_notify = generic_acomp_pin_eld_notify, 3471 .master_bind = generic_acomp_master_bind, 3472 .master_unbind = generic_acomp_master_unbind, 3473 }; 3474 3475 static int patch_nvhdmi(struct hda_codec *codec) 3476 { 3477 struct hdmi_spec *spec; 3478 int err; 3479 3480 err = patch_generic_hdmi(codec); 3481 if (err) 3482 return err; 3483 3484 spec = codec->spec; 3485 spec->dyn_pin_out = true; 3486 3487 spec->chmap.ops.chmap_cea_alloc_validate_get_type = 3488 nvhdmi_chmap_cea_alloc_validate_get_type; 3489 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate; 3490 3491 codec->link_down_at_suspend = 1; 3492 3493 generic_acomp_init(codec, &nvhdmi_audio_ops, nvhdmi_port2pin); 3494 3495 return 0; 3496 } 3497 3498 /* 3499 * The HDA codec on NVIDIA Tegra contains two scratch registers that are 3500 * accessed using vendor-defined verbs. These registers can be used for 3501 * interoperability between the HDA and HDMI drivers. 3502 */ 3503 3504 /* Audio Function Group node */ 3505 #define NVIDIA_AFG_NID 0x01 3506 3507 /* 3508 * The SCRATCH0 register is used to notify the HDMI codec of changes in audio 3509 * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to 3510 * be raised in the HDMI codec. The remainder of the bits is arbitrary. This 3511 * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an 3512 * additional bit (at position 30) to signal the validity of the format. 3513 * 3514 * | 31 | 30 | 29 16 | 15 0 | 3515 * +---------+-------+--------+--------+ 3516 * | TRIGGER | VALID | UNUSED | FORMAT | 3517 * +-----------------------------------| 3518 * 3519 * Note that for the trigger bit to take effect it needs to change value 3520 * (i.e. it needs to be toggled). 3521 */ 3522 #define NVIDIA_GET_SCRATCH0 0xfa6 3523 #define NVIDIA_SET_SCRATCH0_BYTE0 0xfa7 3524 #define NVIDIA_SET_SCRATCH0_BYTE1 0xfa8 3525 #define NVIDIA_SET_SCRATCH0_BYTE2 0xfa9 3526 #define NVIDIA_SET_SCRATCH0_BYTE3 0xfaa 3527 #define NVIDIA_SCRATCH_TRIGGER (1 << 7) 3528 #define NVIDIA_SCRATCH_VALID (1 << 6) 3529 3530 #define NVIDIA_GET_SCRATCH1 0xfab 3531 #define NVIDIA_SET_SCRATCH1_BYTE0 0xfac 3532 #define NVIDIA_SET_SCRATCH1_BYTE1 0xfad 3533 #define NVIDIA_SET_SCRATCH1_BYTE2 0xfae 3534 #define NVIDIA_SET_SCRATCH1_BYTE3 0xfaf 3535 3536 /* 3537 * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0, 3538 * the format is invalidated so that the HDMI codec can be disabled. 3539 */ 3540 static void tegra_hdmi_set_format(struct hda_codec *codec, unsigned int format) 3541 { 3542 unsigned int value; 3543 3544 /* bits [31:30] contain the trigger and valid bits */ 3545 value = snd_hda_codec_read(codec, NVIDIA_AFG_NID, 0, 3546 NVIDIA_GET_SCRATCH0, 0); 3547 value = (value >> 24) & 0xff; 3548 3549 /* bits [15:0] are used to store the HDA format */ 3550 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, 3551 NVIDIA_SET_SCRATCH0_BYTE0, 3552 (format >> 0) & 0xff); 3553 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, 3554 NVIDIA_SET_SCRATCH0_BYTE1, 3555 (format >> 8) & 0xff); 3556 3557 /* bits [16:24] are unused */ 3558 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, 3559 NVIDIA_SET_SCRATCH0_BYTE2, 0); 3560 3561 /* 3562 * Bit 30 signals that the data is valid and hence that HDMI audio can 3563 * be enabled. 3564 */ 3565 if (format == 0) 3566 value &= ~NVIDIA_SCRATCH_VALID; 3567 else 3568 value |= NVIDIA_SCRATCH_VALID; 3569 3570 /* 3571 * Whenever the trigger bit is toggled, an interrupt is raised in the 3572 * HDMI codec. The HDMI driver will use that as trigger to update its 3573 * configuration. 3574 */ 3575 value ^= NVIDIA_SCRATCH_TRIGGER; 3576 3577 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0, 3578 NVIDIA_SET_SCRATCH0_BYTE3, value); 3579 } 3580 3581 static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo, 3582 struct hda_codec *codec, 3583 unsigned int stream_tag, 3584 unsigned int format, 3585 struct snd_pcm_substream *substream) 3586 { 3587 int err; 3588 3589 err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag, 3590 format, substream); 3591 if (err < 0) 3592 return err; 3593 3594 /* notify the HDMI codec of the format change */ 3595 tegra_hdmi_set_format(codec, format); 3596 3597 return 0; 3598 } 3599 3600 static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo, 3601 struct hda_codec *codec, 3602 struct snd_pcm_substream *substream) 3603 { 3604 /* invalidate the format in the HDMI codec */ 3605 tegra_hdmi_set_format(codec, 0); 3606 3607 return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream); 3608 } 3609 3610 static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type) 3611 { 3612 struct hdmi_spec *spec = codec->spec; 3613 unsigned int i; 3614 3615 for (i = 0; i < spec->num_pins; i++) { 3616 struct hda_pcm *pcm = get_pcm_rec(spec, i); 3617 3618 if (pcm->pcm_type == type) 3619 return pcm; 3620 } 3621 3622 return NULL; 3623 } 3624 3625 static int tegra_hdmi_build_pcms(struct hda_codec *codec) 3626 { 3627 struct hda_pcm_stream *stream; 3628 struct hda_pcm *pcm; 3629 int err; 3630 3631 err = generic_hdmi_build_pcms(codec); 3632 if (err < 0) 3633 return err; 3634 3635 pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI); 3636 if (!pcm) 3637 return -ENODEV; 3638 3639 /* 3640 * Override ->prepare() and ->cleanup() operations to notify the HDMI 3641 * codec about format changes. 3642 */ 3643 stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK]; 3644 stream->ops.prepare = tegra_hdmi_pcm_prepare; 3645 stream->ops.cleanup = tegra_hdmi_pcm_cleanup; 3646 3647 return 0; 3648 } 3649 3650 static int patch_tegra_hdmi(struct hda_codec *codec) 3651 { 3652 int err; 3653 3654 err = patch_generic_hdmi(codec); 3655 if (err) 3656 return err; 3657 3658 codec->patch_ops.build_pcms = tegra_hdmi_build_pcms; 3659 3660 return 0; 3661 } 3662 3663 /* 3664 * ATI/AMD-specific implementations 3665 */ 3666 3667 #define is_amdhdmi_rev3_or_later(codec) \ 3668 ((codec)->core.vendor_id == 0x1002aa01 && \ 3669 ((codec)->core.revision_id & 0xff00) >= 0x0300) 3670 #define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec) 3671 3672 /* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */ 3673 #define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771 3674 #define ATI_VERB_SET_DOWNMIX_INFO 0x772 3675 #define ATI_VERB_SET_MULTICHANNEL_01 0x777 3676 #define ATI_VERB_SET_MULTICHANNEL_23 0x778 3677 #define ATI_VERB_SET_MULTICHANNEL_45 0x779 3678 #define ATI_VERB_SET_MULTICHANNEL_67 0x77a 3679 #define ATI_VERB_SET_HBR_CONTROL 0x77c 3680 #define ATI_VERB_SET_MULTICHANNEL_1 0x785 3681 #define ATI_VERB_SET_MULTICHANNEL_3 0x786 3682 #define ATI_VERB_SET_MULTICHANNEL_5 0x787 3683 #define ATI_VERB_SET_MULTICHANNEL_7 0x788 3684 #define ATI_VERB_SET_MULTICHANNEL_MODE 0x789 3685 #define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71 3686 #define ATI_VERB_GET_DOWNMIX_INFO 0xf72 3687 #define ATI_VERB_GET_MULTICHANNEL_01 0xf77 3688 #define ATI_VERB_GET_MULTICHANNEL_23 0xf78 3689 #define ATI_VERB_GET_MULTICHANNEL_45 0xf79 3690 #define ATI_VERB_GET_MULTICHANNEL_67 0xf7a 3691 #define ATI_VERB_GET_HBR_CONTROL 0xf7c 3692 #define ATI_VERB_GET_MULTICHANNEL_1 0xf85 3693 #define ATI_VERB_GET_MULTICHANNEL_3 0xf86 3694 #define ATI_VERB_GET_MULTICHANNEL_5 0xf87 3695 #define ATI_VERB_GET_MULTICHANNEL_7 0xf88 3696 #define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89 3697 3698 /* AMD specific HDA cvt verbs */ 3699 #define ATI_VERB_SET_RAMP_RATE 0x770 3700 #define ATI_VERB_GET_RAMP_RATE 0xf70 3701 3702 #define ATI_OUT_ENABLE 0x1 3703 3704 #define ATI_MULTICHANNEL_MODE_PAIRED 0 3705 #define ATI_MULTICHANNEL_MODE_SINGLE 1 3706 3707 #define ATI_HBR_CAPABLE 0x01 3708 #define ATI_HBR_ENABLE 0x10 3709 3710 static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid, 3711 unsigned char *buf, int *eld_size) 3712 { 3713 /* call hda_eld.c ATI/AMD-specific function */ 3714 return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size, 3715 is_amdhdmi_rev3_or_later(codec)); 3716 } 3717 3718 static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, hda_nid_t pin_nid, int ca, 3719 int active_channels, int conn_type) 3720 { 3721 snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca); 3722 } 3723 3724 static int atihdmi_paired_swap_fc_lfe(int pos) 3725 { 3726 /* 3727 * ATI/AMD have automatic FC/LFE swap built-in 3728 * when in pairwise mapping mode. 3729 */ 3730 3731 switch (pos) { 3732 /* see channel_allocations[].speakers[] */ 3733 case 2: return 3; 3734 case 3: return 2; 3735 default: break; 3736 } 3737 3738 return pos; 3739 } 3740 3741 static int atihdmi_paired_chmap_validate(struct hdac_chmap *chmap, 3742 int ca, int chs, unsigned char *map) 3743 { 3744 struct hdac_cea_channel_speaker_allocation *cap; 3745 int i, j; 3746 3747 /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */ 3748 3749 cap = snd_hdac_get_ch_alloc_from_ca(ca); 3750 for (i = 0; i < chs; ++i) { 3751 int mask = snd_hdac_chmap_to_spk_mask(map[i]); 3752 bool ok = false; 3753 bool companion_ok = false; 3754 3755 if (!mask) 3756 continue; 3757 3758 for (j = 0 + i % 2; j < 8; j += 2) { 3759 int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j); 3760 if (cap->speakers[chan_idx] == mask) { 3761 /* channel is in a supported position */ 3762 ok = true; 3763 3764 if (i % 2 == 0 && i + 1 < chs) { 3765 /* even channel, check the odd companion */ 3766 int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1); 3767 int comp_mask_req = snd_hdac_chmap_to_spk_mask(map[i+1]); 3768 int comp_mask_act = cap->speakers[comp_chan_idx]; 3769 3770 if (comp_mask_req == comp_mask_act) 3771 companion_ok = true; 3772 else 3773 return -EINVAL; 3774 } 3775 break; 3776 } 3777 } 3778 3779 if (!ok) 3780 return -EINVAL; 3781 3782 if (companion_ok) 3783 i++; /* companion channel already checked */ 3784 } 3785 3786 return 0; 3787 } 3788 3789 static int atihdmi_pin_set_slot_channel(struct hdac_device *hdac, 3790 hda_nid_t pin_nid, int hdmi_slot, int stream_channel) 3791 { 3792 struct hda_codec *codec = container_of(hdac, struct hda_codec, core); 3793 int verb; 3794 int ati_channel_setup = 0; 3795 3796 if (hdmi_slot > 7) 3797 return -EINVAL; 3798 3799 if (!has_amd_full_remap_support(codec)) { 3800 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot); 3801 3802 /* In case this is an odd slot but without stream channel, do not 3803 * disable the slot since the corresponding even slot could have a 3804 * channel. In case neither have a channel, the slot pair will be 3805 * disabled when this function is called for the even slot. */ 3806 if (hdmi_slot % 2 != 0 && stream_channel == 0xf) 3807 return 0; 3808 3809 hdmi_slot -= hdmi_slot % 2; 3810 3811 if (stream_channel != 0xf) 3812 stream_channel -= stream_channel % 2; 3813 } 3814 3815 verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e; 3816 3817 /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */ 3818 3819 if (stream_channel != 0xf) 3820 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE; 3821 3822 return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup); 3823 } 3824 3825 static int atihdmi_pin_get_slot_channel(struct hdac_device *hdac, 3826 hda_nid_t pin_nid, int asp_slot) 3827 { 3828 struct hda_codec *codec = container_of(hdac, struct hda_codec, core); 3829 bool was_odd = false; 3830 int ati_asp_slot = asp_slot; 3831 int verb; 3832 int ati_channel_setup; 3833 3834 if (asp_slot > 7) 3835 return -EINVAL; 3836 3837 if (!has_amd_full_remap_support(codec)) { 3838 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot); 3839 if (ati_asp_slot % 2 != 0) { 3840 ati_asp_slot -= 1; 3841 was_odd = true; 3842 } 3843 } 3844 3845 verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e; 3846 3847 ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0); 3848 3849 if (!(ati_channel_setup & ATI_OUT_ENABLE)) 3850 return 0xf; 3851 3852 return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd; 3853 } 3854 3855 static int atihdmi_paired_chmap_cea_alloc_validate_get_type( 3856 struct hdac_chmap *chmap, 3857 struct hdac_cea_channel_speaker_allocation *cap, 3858 int channels) 3859 { 3860 int c; 3861 3862 /* 3863 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so 3864 * we need to take that into account (a single channel may take 2 3865 * channel slots if we need to carry a silent channel next to it). 3866 * On Rev3+ AMD codecs this function is not used. 3867 */ 3868 int chanpairs = 0; 3869 3870 /* We only produce even-numbered channel count TLVs */ 3871 if ((channels % 2) != 0) 3872 return -1; 3873 3874 for (c = 0; c < 7; c += 2) { 3875 if (cap->speakers[c] || cap->speakers[c+1]) 3876 chanpairs++; 3877 } 3878 3879 if (chanpairs * 2 != channels) 3880 return -1; 3881 3882 return SNDRV_CTL_TLVT_CHMAP_PAIRED; 3883 } 3884 3885 static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct hdac_chmap *hchmap, 3886 struct hdac_cea_channel_speaker_allocation *cap, 3887 unsigned int *chmap, int channels) 3888 { 3889 /* produce paired maps for pre-rev3 ATI/AMD codecs */ 3890 int count = 0; 3891 int c; 3892 3893 for (c = 7; c >= 0; c--) { 3894 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c); 3895 int spk = cap->speakers[chan]; 3896 if (!spk) { 3897 /* add N/A channel if the companion channel is occupied */ 3898 if (cap->speakers[chan + (chan % 2 ? -1 : 1)]) 3899 chmap[count++] = SNDRV_CHMAP_NA; 3900 3901 continue; 3902 } 3903 3904 chmap[count++] = snd_hdac_spk_to_chmap(spk); 3905 } 3906 3907 WARN_ON(count != channels); 3908 } 3909 3910 static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid, 3911 bool hbr) 3912 { 3913 int hbr_ctl, hbr_ctl_new; 3914 3915 hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0); 3916 if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) { 3917 if (hbr) 3918 hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE; 3919 else 3920 hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE; 3921 3922 codec_dbg(codec, 3923 "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n", 3924 pin_nid, 3925 hbr_ctl == hbr_ctl_new ? "" : "new-", 3926 hbr_ctl_new); 3927 3928 if (hbr_ctl != hbr_ctl_new) 3929 snd_hda_codec_write(codec, pin_nid, 0, 3930 ATI_VERB_SET_HBR_CONTROL, 3931 hbr_ctl_new); 3932 3933 } else if (hbr) 3934 return -EINVAL; 3935 3936 return 0; 3937 } 3938 3939 static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, 3940 hda_nid_t pin_nid, u32 stream_tag, int format) 3941 { 3942 3943 if (is_amdhdmi_rev3_or_later(codec)) { 3944 int ramp_rate = 180; /* default as per AMD spec */ 3945 /* disable ramp-up/down for non-pcm as per AMD spec */ 3946 if (format & AC_FMT_TYPE_NON_PCM) 3947 ramp_rate = 0; 3948 3949 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate); 3950 } 3951 3952 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format); 3953 } 3954 3955 3956 static int atihdmi_init(struct hda_codec *codec) 3957 { 3958 struct hdmi_spec *spec = codec->spec; 3959 int pin_idx, err; 3960 3961 err = generic_hdmi_init(codec); 3962 3963 if (err) 3964 return err; 3965 3966 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 3967 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 3968 3969 /* make sure downmix information in infoframe is zero */ 3970 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0); 3971 3972 /* enable channel-wise remap mode if supported */ 3973 if (has_amd_full_remap_support(codec)) 3974 snd_hda_codec_write(codec, per_pin->pin_nid, 0, 3975 ATI_VERB_SET_MULTICHANNEL_MODE, 3976 ATI_MULTICHANNEL_MODE_SINGLE); 3977 } 3978 3979 return 0; 3980 } 3981 3982 /* map from pin NID to port; port is 0-based */ 3983 /* for AMD: assume widget NID starting from 3, with step 2 (3, 5, 7, ...) */ 3984 static int atihdmi_pin2port(void *audio_ptr, int pin_nid) 3985 { 3986 return pin_nid / 2 - 1; 3987 } 3988 3989 /* reverse-map from port to pin NID: see above */ 3990 static int atihdmi_port2pin(struct hda_codec *codec, int port) 3991 { 3992 return port * 2 + 3; 3993 } 3994 3995 static const struct drm_audio_component_audio_ops atihdmi_audio_ops = { 3996 .pin2port = atihdmi_pin2port, 3997 .pin_eld_notify = generic_acomp_pin_eld_notify, 3998 .master_bind = generic_acomp_master_bind, 3999 .master_unbind = generic_acomp_master_unbind, 4000 }; 4001 4002 static int patch_atihdmi(struct hda_codec *codec) 4003 { 4004 struct hdmi_spec *spec; 4005 struct hdmi_spec_per_cvt *per_cvt; 4006 int err, cvt_idx; 4007 4008 err = patch_generic_hdmi(codec); 4009 4010 if (err) 4011 return err; 4012 4013 codec->patch_ops.init = atihdmi_init; 4014 4015 spec = codec->spec; 4016 4017 spec->ops.pin_get_eld = atihdmi_pin_get_eld; 4018 spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe; 4019 spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup; 4020 spec->ops.setup_stream = atihdmi_setup_stream; 4021 4022 spec->chmap.ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel; 4023 spec->chmap.ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel; 4024 4025 if (!has_amd_full_remap_support(codec)) { 4026 /* override to ATI/AMD-specific versions with pairwise mapping */ 4027 spec->chmap.ops.chmap_cea_alloc_validate_get_type = 4028 atihdmi_paired_chmap_cea_alloc_validate_get_type; 4029 spec->chmap.ops.cea_alloc_to_tlv_chmap = 4030 atihdmi_paired_cea_alloc_to_tlv_chmap; 4031 spec->chmap.ops.chmap_validate = atihdmi_paired_chmap_validate; 4032 } 4033 4034 /* ATI/AMD converters do not advertise all of their capabilities */ 4035 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { 4036 per_cvt = get_cvt(spec, cvt_idx); 4037 per_cvt->channels_max = max(per_cvt->channels_max, 8u); 4038 per_cvt->rates |= SUPPORTED_RATES; 4039 per_cvt->formats |= SUPPORTED_FORMATS; 4040 per_cvt->maxbps = max(per_cvt->maxbps, 24u); 4041 } 4042 4043 spec->chmap.channels_max = max(spec->chmap.channels_max, 8u); 4044 4045 /* AMD GPUs have neither EPSS nor CLKSTOP bits, hence preventing 4046 * the link-down as is. Tell the core to allow it. 4047 */ 4048 codec->link_down_at_suspend = 1; 4049 4050 generic_acomp_init(codec, &atihdmi_audio_ops, atihdmi_port2pin); 4051 4052 return 0; 4053 } 4054 4055 /* VIA HDMI Implementation */ 4056 #define VIAHDMI_CVT_NID 0x02 /* audio converter1 */ 4057 #define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */ 4058 4059 static int patch_via_hdmi(struct hda_codec *codec) 4060 { 4061 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID); 4062 } 4063 4064 /* 4065 * patch entries 4066 */ 4067 static const struct hda_device_id snd_hda_id_hdmi[] = { 4068 HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI", patch_atihdmi), 4069 HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI", patch_atihdmi), 4070 HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI", patch_atihdmi), 4071 HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI", patch_atihdmi), 4072 HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI", patch_generic_hdmi), 4073 HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI", patch_generic_hdmi), 4074 HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI", patch_generic_hdmi), 4075 HDA_CODEC_ENTRY(0x10de0001, "MCP73 HDMI", patch_nvhdmi_2ch), 4076 HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 4077 HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 4078 HDA_CODEC_ENTRY(0x10de0004, "GPU 04 HDMI", patch_nvhdmi_8ch_7x), 4079 HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 4080 HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 4081 HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI", patch_nvhdmi_8ch_7x), 4082 HDA_CODEC_ENTRY(0x10de0008, "GPU 08 HDMI/DP", patch_nvhdmi), 4083 HDA_CODEC_ENTRY(0x10de0009, "GPU 09 HDMI/DP", patch_nvhdmi), 4084 HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP", patch_nvhdmi), 4085 HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP", patch_nvhdmi), 4086 HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI", patch_nvhdmi), 4087 HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP", patch_nvhdmi), 4088 HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP", patch_nvhdmi), 4089 HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP", patch_nvhdmi), 4090 HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP", patch_nvhdmi), 4091 HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP", patch_nvhdmi), 4092 HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP", patch_nvhdmi), 4093 HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP", patch_nvhdmi), 4094 HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP", patch_nvhdmi), 4095 /* 17 is known to be absent */ 4096 HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP", patch_nvhdmi), 4097 HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP", patch_nvhdmi), 4098 HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP", patch_nvhdmi), 4099 HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP", patch_nvhdmi), 4100 HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP", patch_nvhdmi), 4101 HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI", patch_tegra_hdmi), 4102 HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI", patch_tegra_hdmi), 4103 HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI", patch_tegra_hdmi), 4104 HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi), 4105 HDA_CODEC_ENTRY(0x10de002d, "Tegra186 HDMI/DP0", patch_tegra_hdmi), 4106 HDA_CODEC_ENTRY(0x10de002e, "Tegra186 HDMI/DP1", patch_tegra_hdmi), 4107 HDA_CODEC_ENTRY(0x10de002f, "Tegra194 HDMI/DP2", patch_tegra_hdmi), 4108 HDA_CODEC_ENTRY(0x10de0030, "Tegra194 HDMI/DP3", patch_tegra_hdmi), 4109 HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP", patch_nvhdmi), 4110 HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP", patch_nvhdmi), 4111 HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi), 4112 HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP", patch_nvhdmi), 4113 HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP", patch_nvhdmi), 4114 HDA_CODEC_ENTRY(0x10de0045, "GPU 45 HDMI/DP", patch_nvhdmi), 4115 HDA_CODEC_ENTRY(0x10de0050, "GPU 50 HDMI/DP", patch_nvhdmi), 4116 HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP", patch_nvhdmi), 4117 HDA_CODEC_ENTRY(0x10de0052, "GPU 52 HDMI/DP", patch_nvhdmi), 4118 HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP", patch_nvhdmi), 4119 HDA_CODEC_ENTRY(0x10de0061, "GPU 61 HDMI/DP", patch_nvhdmi), 4120 HDA_CODEC_ENTRY(0x10de0062, "GPU 62 HDMI/DP", patch_nvhdmi), 4121 HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI", patch_nvhdmi_2ch), 4122 HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP", patch_nvhdmi), 4123 HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP", patch_nvhdmi), 4124 HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP", patch_nvhdmi), 4125 HDA_CODEC_ENTRY(0x10de0073, "GPU 73 HDMI/DP", patch_nvhdmi), 4126 HDA_CODEC_ENTRY(0x10de0074, "GPU 74 HDMI/DP", patch_nvhdmi), 4127 HDA_CODEC_ENTRY(0x10de0076, "GPU 76 HDMI/DP", patch_nvhdmi), 4128 HDA_CODEC_ENTRY(0x10de007b, "GPU 7b HDMI/DP", patch_nvhdmi), 4129 HDA_CODEC_ENTRY(0x10de007c, "GPU 7c HDMI/DP", patch_nvhdmi), 4130 HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP", patch_nvhdmi), 4131 HDA_CODEC_ENTRY(0x10de007e, "GPU 7e HDMI/DP", patch_nvhdmi), 4132 HDA_CODEC_ENTRY(0x10de0080, "GPU 80 HDMI/DP", patch_nvhdmi), 4133 HDA_CODEC_ENTRY(0x10de0081, "GPU 81 HDMI/DP", patch_nvhdmi), 4134 HDA_CODEC_ENTRY(0x10de0082, "GPU 82 HDMI/DP", patch_nvhdmi), 4135 HDA_CODEC_ENTRY(0x10de0083, "GPU 83 HDMI/DP", patch_nvhdmi), 4136 HDA_CODEC_ENTRY(0x10de0084, "GPU 84 HDMI/DP", patch_nvhdmi), 4137 HDA_CODEC_ENTRY(0x10de0090, "GPU 90 HDMI/DP", patch_nvhdmi), 4138 HDA_CODEC_ENTRY(0x10de0091, "GPU 91 HDMI/DP", patch_nvhdmi), 4139 HDA_CODEC_ENTRY(0x10de0092, "GPU 92 HDMI/DP", patch_nvhdmi), 4140 HDA_CODEC_ENTRY(0x10de0093, "GPU 93 HDMI/DP", patch_nvhdmi), 4141 HDA_CODEC_ENTRY(0x10de0094, "GPU 94 HDMI/DP", patch_nvhdmi), 4142 HDA_CODEC_ENTRY(0x10de0095, "GPU 95 HDMI/DP", patch_nvhdmi), 4143 HDA_CODEC_ENTRY(0x10de0097, "GPU 97 HDMI/DP", patch_nvhdmi), 4144 HDA_CODEC_ENTRY(0x10de0098, "GPU 98 HDMI/DP", patch_nvhdmi), 4145 HDA_CODEC_ENTRY(0x10de0099, "GPU 99 HDMI/DP", patch_nvhdmi), 4146 HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI", patch_nvhdmi_2ch), 4147 HDA_CODEC_ENTRY(0x10de8067, "MCP67/68 HDMI", patch_nvhdmi_2ch), 4148 HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP", patch_via_hdmi), 4149 HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP", patch_via_hdmi), 4150 HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP", patch_generic_hdmi), 4151 HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP", patch_generic_hdmi), 4152 HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI", patch_i915_cpt_hdmi), 4153 HDA_CODEC_ENTRY(0x80862800, "Geminilake HDMI", patch_i915_glk_hdmi), 4154 HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI", patch_generic_hdmi), 4155 HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI", patch_generic_hdmi), 4156 HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI", patch_generic_hdmi), 4157 HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI", patch_i915_cpt_hdmi), 4158 HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_i915_cpt_hdmi), 4159 HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_i915_cpt_hdmi), 4160 HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI", patch_i915_hsw_hdmi), 4161 HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI", patch_i915_hsw_hdmi), 4162 HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI", patch_i915_hsw_hdmi), 4163 HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI", patch_i915_hsw_hdmi), 4164 HDA_CODEC_ENTRY(0x8086280b, "Kabylake HDMI", patch_i915_hsw_hdmi), 4165 HDA_CODEC_ENTRY(0x8086280c, "Cannonlake HDMI", patch_i915_glk_hdmi), 4166 HDA_CODEC_ENTRY(0x8086280d, "Geminilake HDMI", patch_i915_glk_hdmi), 4167 HDA_CODEC_ENTRY(0x8086280f, "Icelake HDMI", patch_i915_icl_hdmi), 4168 HDA_CODEC_ENTRY(0x80862812, "Tigerlake HDMI", patch_i915_tgl_hdmi), 4169 HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI", patch_generic_hdmi), 4170 HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_i915_byt_hdmi), 4171 HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI", patch_i915_byt_hdmi), 4172 HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI", patch_generic_hdmi), 4173 /* special ID for generic HDMI */ 4174 HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi), 4175 {} /* terminator */ 4176 }; 4177 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi); 4178 4179 MODULE_LICENSE("GPL"); 4180 MODULE_DESCRIPTION("HDMI HD-audio codec"); 4181 MODULE_ALIAS("snd-hda-codec-intelhdmi"); 4182 MODULE_ALIAS("snd-hda-codec-nvhdmi"); 4183 MODULE_ALIAS("snd-hda-codec-atihdmi"); 4184 4185 static struct hda_codec_driver hdmi_driver = { 4186 .id = snd_hda_id_hdmi, 4187 }; 4188 4189 module_hda_codec_driver(hdmi_driver); 4190