1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * patch_cs8409-tables.c -- HD audio interface patch for Cirrus Logic CS8409 HDA bridge chip 4 * 5 * Copyright (C) 2021 Cirrus Logic, Inc. and 6 * Cirrus Logic International Semiconductor Ltd. 7 * 8 * Author: Lucas Tanure <tanureal@opensource.cirrus.com> 9 */ 10 11 #include "patch_cs8409.h" 12 13 /****************************************************************************** 14 * CS42L42 Specific Data 15 * 16 ******************************************************************************/ 17 18 static const DECLARE_TLV_DB_SCALE(cs42l42_dac_db_scale, CS42L42_HP_VOL_REAL_MIN * 100, 100, 1); 19 20 static const DECLARE_TLV_DB_SCALE(cs42l42_adc_db_scale, CS42L42_AMIC_VOL_REAL_MIN * 100, 100, 1); 21 22 const struct snd_kcontrol_new cs42l42_dac_volume_mixer = { 23 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 24 .index = 0, 25 .subdevice = (HDA_SUBDEV_AMP_FLAG | HDA_SUBDEV_NID_FLAG), 26 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ), 27 .info = cs42l42_volume_info, 28 .get = cs42l42_volume_get, 29 .put = cs42l42_volume_put, 30 .tlv = { .p = cs42l42_dac_db_scale }, 31 .private_value = HDA_COMPOSE_AMP_VAL_OFS(CS8409_PIN_ASP1_TRANSMITTER_A, 3, CS8409_CODEC0, 32 HDA_OUTPUT, CS42L42_VOL_DAC) | HDA_AMP_VAL_MIN_MUTE 33 }; 34 35 const struct snd_kcontrol_new cs42l42_adc_volume_mixer = { 36 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 37 .index = 0, 38 .subdevice = (HDA_SUBDEV_AMP_FLAG | HDA_SUBDEV_NID_FLAG), 39 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ), 40 .info = cs42l42_volume_info, 41 .get = cs42l42_volume_get, 42 .put = cs42l42_volume_put, 43 .tlv = { .p = cs42l42_adc_db_scale }, 44 .private_value = HDA_COMPOSE_AMP_VAL_OFS(CS8409_PIN_ASP1_RECEIVER_A, 1, CS8409_CODEC0, 45 HDA_INPUT, CS42L42_VOL_ADC) | HDA_AMP_VAL_MIN_MUTE 46 }; 47 48 const struct hda_pcm_stream cs42l42_48k_pcm_analog_playback = { 49 .rates = SNDRV_PCM_RATE_48000, /* fixed rate */ 50 }; 51 52 const struct hda_pcm_stream cs42l42_48k_pcm_analog_capture = { 53 .rates = SNDRV_PCM_RATE_48000, /* fixed rate */ 54 }; 55 56 /****************************************************************************** 57 * BULLSEYE / WARLOCK / CYBORG Specific Arrays 58 * CS8409/CS42L42 59 ******************************************************************************/ 60 61 const struct hda_verb cs8409_cs42l42_init_verbs[] = { 62 { CS8409_PIN_AFG, AC_VERB_SET_GPIO_WAKE_MASK, 0x0018 }, /* WAKE from GPIO 3,4 */ 63 { CS8409_PIN_VENDOR_WIDGET, AC_VERB_SET_PROC_STATE, 0x0001 }, /* Enable VPW processing */ 64 { CS8409_PIN_VENDOR_WIDGET, AC_VERB_SET_COEF_INDEX, 0x0002 }, /* Configure GPIO 6,7 */ 65 { CS8409_PIN_VENDOR_WIDGET, AC_VERB_SET_PROC_COEF, 0x0080 }, /* I2C mode */ 66 { CS8409_PIN_VENDOR_WIDGET, AC_VERB_SET_COEF_INDEX, 0x005b }, /* Set I2C bus speed */ 67 { CS8409_PIN_VENDOR_WIDGET, AC_VERB_SET_PROC_COEF, 0x0200 }, /* 100kHz I2C_STO = 2 */ 68 {} /* terminator */ 69 }; 70 71 const struct hda_pintbl cs8409_cs42l42_pincfgs[] = { 72 { CS8409_PIN_ASP1_TRANSMITTER_A, 0x042120f0 }, /* ASP-1-TX */ 73 { CS8409_PIN_ASP1_RECEIVER_A, 0x04a12050 }, /* ASP-1-RX */ 74 { CS8409_PIN_ASP2_TRANSMITTER_A, 0x901000f0 }, /* ASP-2-TX */ 75 { CS8409_PIN_DMIC1_IN, 0x90a00090 }, /* DMIC-1 */ 76 {} /* terminator */ 77 }; 78 79 /* Vendor specific HW configuration for CS42L42 */ 80 static const struct cs8409_i2c_param cs42l42_init_reg_seq[] = { 81 { 0x1010, 0xB0 }, 82 { 0x1D01, 0x00 }, 83 { 0x1D02, 0x06 }, 84 { 0x1D03, 0x9F }, 85 { 0x1107, 0x01 }, 86 { 0x1009, 0x02 }, 87 { 0x1007, 0x03 }, 88 { 0x1201, 0x00 }, 89 { 0x1208, 0x13 }, 90 { 0x1205, 0xFF }, 91 { 0x1206, 0x00 }, 92 { 0x1207, 0x20 }, 93 { 0x1202, 0x0D }, 94 { 0x2A02, 0x02 }, 95 { 0x2A03, 0x00 }, 96 { 0x2A04, 0x00 }, 97 { 0x2A05, 0x02 }, 98 { 0x2A06, 0x00 }, 99 { 0x2A07, 0x20 }, 100 { 0x2A08, 0x02 }, 101 { 0x2A09, 0x00 }, 102 { 0x2A0A, 0x80 }, 103 { 0x2A0B, 0x02 }, 104 { 0x2A0C, 0x00 }, 105 { 0x2A0D, 0xA0 }, 106 { 0x2A01, 0x0C }, 107 { 0x2902, 0x01 }, 108 { 0x2903, 0x02 }, 109 { 0x2904, 0x00 }, 110 { 0x2905, 0x00 }, 111 { 0x2901, 0x01 }, 112 { 0x1101, 0x0A }, 113 { 0x1102, 0x84 }, 114 { 0x2301, 0x3F }, 115 { 0x2303, 0x3F }, 116 { 0x2302, 0x3f }, 117 { 0x2001, 0x03 }, 118 { 0x1B75, 0xB6 }, 119 { 0x1B73, 0xC2 }, 120 { 0x1129, 0x01 }, 121 { 0x1121, 0xF3 }, 122 { 0x1103, 0x20 }, 123 { 0x1105, 0x00 }, 124 { 0x1112, 0x00 }, 125 { 0x1113, 0x80 }, 126 { 0x1C03, 0xC0 }, 127 { 0x1101, 0x02 }, 128 { 0x1316, 0xff }, 129 { 0x1317, 0xff }, 130 { 0x1318, 0xff }, 131 { 0x1319, 0xff }, 132 { 0x131a, 0xff }, 133 { 0x131b, 0xff }, 134 { 0x131c, 0xff }, 135 { 0x131e, 0xff }, 136 { 0x131f, 0xff }, 137 { 0x1320, 0xff }, 138 { 0x1b79, 0xff }, 139 { 0x1b7a, 0xff }, 140 }; 141 142 /* Vendor specific hw configuration for CS8409 */ 143 const struct cs8409_cir_param cs8409_cs42l42_hw_cfg[] = { 144 /* +PLL1/2_EN, +I2C_EN */ 145 { CS8409_PIN_VENDOR_WIDGET, CS8409_DEV_CFG1, 0xb008 }, 146 /* ASP1/2_EN=0, ASP1_STP=1 */ 147 { CS8409_PIN_VENDOR_WIDGET, CS8409_DEV_CFG2, 0x0002 }, 148 /* ASP1/2_BUS_IDLE=10, +GPIO_I2C */ 149 { CS8409_PIN_VENDOR_WIDGET, CS8409_DEV_CFG3, 0x0a80 }, 150 /* ASP1.A: TX.LAP=0, TX.LSZ=24 bits, TX.LCS=0 */ 151 { CS8409_PIN_VENDOR_WIDGET, ASP1_A_TX_CTRL1, 0x0800 }, 152 /* ASP1.A: TX.RAP=0, TX.RSZ=24 bits, TX.RCS=32 */ 153 { CS8409_PIN_VENDOR_WIDGET, ASP1_A_TX_CTRL2, 0x0820 }, 154 /* ASP2.A: TX.LAP=0, TX.LSZ=24 bits, TX.LCS=0 */ 155 { CS8409_PIN_VENDOR_WIDGET, ASP2_A_TX_CTRL1, 0x0800 }, 156 /* ASP2.A: TX.RAP=1, TX.RSZ=24 bits, TX.RCS=0 */ 157 { CS8409_PIN_VENDOR_WIDGET, ASP2_A_TX_CTRL2, 0x2800 }, 158 /* ASP1.A: RX.LAP=0, RX.LSZ=24 bits, RX.LCS=0 */ 159 { CS8409_PIN_VENDOR_WIDGET, ASP1_A_RX_CTRL1, 0x0800 }, 160 /* ASP1.A: RX.RAP=0, RX.RSZ=24 bits, RX.RCS=0 */ 161 { CS8409_PIN_VENDOR_WIDGET, ASP1_A_RX_CTRL2, 0x0800 }, 162 /* ASP1: LCHI = 00h */ 163 { CS8409_PIN_VENDOR_WIDGET, CS8409_ASP1_CLK_CTRL1, 0x8000 }, 164 /* ASP1: MC/SC_SRCSEL=PLL1, LCPR=FFh */ 165 { CS8409_PIN_VENDOR_WIDGET, CS8409_ASP1_CLK_CTRL2, 0x28ff }, 166 /* ASP1: MCEN=0, FSD=011, SCPOL_IN/OUT=0, SCDIV=1:4 */ 167 { CS8409_PIN_VENDOR_WIDGET, CS8409_ASP1_CLK_CTRL3, 0x0062 }, 168 /* ASP2: LCHI=1Fh */ 169 { CS8409_PIN_VENDOR_WIDGET, CS8409_ASP2_CLK_CTRL1, 0x801f }, 170 /* ASP2: MC/SC_SRCSEL=PLL1, LCPR=3Fh */ 171 { CS8409_PIN_VENDOR_WIDGET, CS8409_ASP2_CLK_CTRL2, 0x283f }, 172 /* ASP2: 5050=1, MCEN=0, FSD=010, SCPOL_IN/OUT=1, SCDIV=1:16 */ 173 { CS8409_PIN_VENDOR_WIDGET, CS8409_ASP2_CLK_CTRL3, 0x805c }, 174 /* DMIC1_MO=10b, DMIC1/2_SR=1 */ 175 { CS8409_PIN_VENDOR_WIDGET, CS8409_DMIC_CFG, 0x0023 }, 176 /* ASP1/2_BEEP=0 */ 177 { CS8409_PIN_VENDOR_WIDGET, CS8409_BEEP_CFG, 0x0000 }, 178 /* ASP1/2_EN=1, ASP1_STP=1 */ 179 { CS8409_PIN_VENDOR_WIDGET, CS8409_DEV_CFG2, 0x0062 }, 180 /* -PLL2_EN */ 181 { CS8409_PIN_VENDOR_WIDGET, CS8409_DEV_CFG1, 0x9008 }, 182 /* TX2.A: pre-scale att.=0 dB */ 183 { CS8409_PIN_VENDOR_WIDGET, CS8409_PRE_SCALE_ATTN2, 0x0000 }, 184 /* ASP1/2_xxx_EN=1, ASP1/2_MCLK_EN=0, DMIC1_SCL_EN=1 */ 185 { CS8409_PIN_VENDOR_WIDGET, CS8409_PAD_CFG_SLW_RATE_CTRL, 0xfc03 }, 186 /* test mode on */ 187 { CS8409_PIN_VENDOR_WIDGET, 0xc0, 0x9999 }, 188 /* GPIO hysteresis = 30 us */ 189 { CS8409_PIN_VENDOR_WIDGET, 0xc5, 0x0000 }, 190 /* test mode off */ 191 { CS8409_PIN_VENDOR_WIDGET, 0xc0, 0x0000 }, 192 {} /* Terminator */ 193 }; 194 195 const struct cs8409_cir_param cs8409_cs42l42_bullseye_atn[] = { 196 /* EQ_SEL=1, EQ1/2_EN=0 */ 197 { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_CTRL1, 0x4000 }, 198 /* +EQ_ACC */ 199 { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W2, 0x4000 }, 200 /* +EQ2_EN */ 201 { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_CTRL1, 0x4010 }, 202 /* EQ_DATA_HI=0x0647 */ 203 { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W1, 0x0647 }, 204 /* +EQ_WRT, +EQ_ACC, EQ_ADR=0, EQ_DATA_LO=0x67 */ 205 { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W2, 0xc0c7 }, 206 /* EQ_DATA_HI=0x0647 */ 207 { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W1, 0x0647 }, 208 /* +EQ_WRT, +EQ_ACC, EQ_ADR=1, EQ_DATA_LO=0x67 */ 209 { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W2, 0xc1c7 }, 210 /* EQ_DATA_HI=0xf370 */ 211 { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W1, 0xf370 }, 212 /* +EQ_WRT, +EQ_ACC, EQ_ADR=2, EQ_DATA_LO=0x71 */ 213 { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W2, 0xc271 }, 214 /* EQ_DATA_HI=0x1ef8 */ 215 { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W1, 0x1ef8 }, 216 /* +EQ_WRT, +EQ_ACC, EQ_ADR=3, EQ_DATA_LO=0x48 */ 217 { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W2, 0xc348 }, 218 /* EQ_DATA_HI=0xc110 */ 219 { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W1, 0xc110 }, 220 /* +EQ_WRT, +EQ_ACC, EQ_ADR=4, EQ_DATA_LO=0x5a */ 221 { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W2, 0xc45a }, 222 /* EQ_DATA_HI=0x1f29 */ 223 { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W1, 0x1f29 }, 224 /* +EQ_WRT, +EQ_ACC, EQ_ADR=5, EQ_DATA_LO=0x74 */ 225 { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W2, 0xc574 }, 226 /* EQ_DATA_HI=0x1d7a */ 227 { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W1, 0x1d7a }, 228 /* +EQ_WRT, +EQ_ACC, EQ_ADR=6, EQ_DATA_LO=0x53 */ 229 { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W2, 0xc653 }, 230 /* EQ_DATA_HI=0xc38c */ 231 { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W1, 0xc38c }, 232 /* +EQ_WRT, +EQ_ACC, EQ_ADR=7, EQ_DATA_LO=0x14 */ 233 { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W2, 0xc714 }, 234 /* EQ_DATA_HI=0x1ca3 */ 235 { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W1, 0x1ca3 }, 236 /* +EQ_WRT, +EQ_ACC, EQ_ADR=8, EQ_DATA_LO=0xc7 */ 237 { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W2, 0xc8c7 }, 238 /* EQ_DATA_HI=0xc38c */ 239 { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W1, 0xc38c }, 240 /* +EQ_WRT, +EQ_ACC, EQ_ADR=9, EQ_DATA_LO=0x14 */ 241 { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W2, 0xc914 }, 242 /* -EQ_ACC, -EQ_WRT */ 243 { CS8409_PIN_VENDOR_WIDGET, CS8409_PFE_COEF_W2, 0x0000 }, 244 {} /* Terminator */ 245 }; 246 247 struct sub_codec cs8409_cs42l42_codec = { 248 .addr = CS42L42_I2C_ADDR, 249 .reset_gpio = CS8409_CS42L42_RESET, 250 .irq_mask = CS8409_CS42L42_INT, 251 .init_seq = cs42l42_init_reg_seq, 252 .init_seq_num = ARRAY_SIZE(cs42l42_init_reg_seq), 253 .hp_jack_in = 0, 254 .mic_jack_in = 0, 255 .paged = 1, 256 .suspended = 1, 257 .no_type_dect = 0, 258 }; 259 260 /****************************************************************************** 261 * Dolphin Specific Arrays 262 * CS8409/ 2 X CS42L42 263 ******************************************************************************/ 264 265 const struct hda_verb dolphin_init_verbs[] = { 266 { 0x01, AC_VERB_SET_GPIO_WAKE_MASK, DOLPHIN_WAKE }, /* WAKE from GPIO 0,4 */ 267 { CS8409_PIN_VENDOR_WIDGET, AC_VERB_SET_PROC_STATE, 0x0001 }, /* Enable VPW processing */ 268 { CS8409_PIN_VENDOR_WIDGET, AC_VERB_SET_COEF_INDEX, 0x0002 }, /* Configure GPIO 6,7 */ 269 { CS8409_PIN_VENDOR_WIDGET, AC_VERB_SET_PROC_COEF, 0x0080 }, /* I2C mode */ 270 { CS8409_PIN_VENDOR_WIDGET, AC_VERB_SET_COEF_INDEX, 0x005b }, /* Set I2C bus speed */ 271 { CS8409_PIN_VENDOR_WIDGET, AC_VERB_SET_PROC_COEF, 0x0200 }, /* 100kHz I2C_STO = 2 */ 272 {} /* terminator */ 273 }; 274 275 const struct hda_pintbl dolphin_pincfgs[] = { 276 { 0x24, 0x022210f0 }, /* ASP-1-TX-A */ 277 { 0x25, 0x010240f0 }, /* ASP-1-TX-B */ 278 { 0x34, 0x02a21050 }, /* ASP-1-RX */ 279 {} /* terminator */ 280 }; 281 282 /* Vendor specific HW configuration for CS42L42 */ 283 static const struct cs8409_i2c_param dolphin_c0_init_reg_seq[] = { 284 { 0x1010, 0xB0 }, 285 { 0x1D01, 0x00 }, 286 { 0x1D02, 0x06 }, 287 { 0x1D03, 0x9F }, 288 { 0x1107, 0x01 }, 289 { 0x1009, 0x02 }, 290 { 0x1007, 0x03 }, 291 { 0x1201, 0x00 }, 292 { 0x1208, 0x13 }, 293 { 0x1205, 0xFF }, 294 { 0x1206, 0x00 }, 295 { 0x1207, 0x20 }, 296 { 0x1202, 0x0D }, 297 { 0x2A02, 0x02 }, 298 { 0x2A03, 0x00 }, 299 { 0x2A04, 0x00 }, 300 { 0x2A05, 0x02 }, 301 { 0x2A06, 0x00 }, 302 { 0x2A07, 0x20 }, 303 { 0x2A01, 0x0C }, 304 { 0x2902, 0x01 }, 305 { 0x2903, 0x02 }, 306 { 0x2904, 0x00 }, 307 { 0x2905, 0x00 }, 308 { 0x2901, 0x01 }, 309 { 0x1101, 0x0A }, 310 { 0x1102, 0x84 }, 311 { 0x2001, 0x03 }, 312 { 0x2301, 0x3F }, 313 { 0x2303, 0x3F }, 314 { 0x2302, 0x3f }, 315 { 0x1B75, 0xB6 }, 316 { 0x1B73, 0xC2 }, 317 { 0x1129, 0x01 }, 318 { 0x1121, 0xF3 }, 319 { 0x1103, 0x20 }, 320 { 0x1105, 0x00 }, 321 { 0x1112, 0x00 }, 322 { 0x1113, 0x80 }, 323 { 0x1C03, 0xC0 }, 324 { 0x1101, 0x02 }, 325 { 0x1316, 0xff }, 326 { 0x1317, 0xff }, 327 { 0x1318, 0xff }, 328 { 0x1319, 0xff }, 329 { 0x131a, 0xff }, 330 { 0x131b, 0xff }, 331 { 0x131c, 0xff }, 332 { 0x131e, 0xff }, 333 { 0x131f, 0xff }, 334 { 0x1320, 0xff }, 335 { 0x1b79, 0xff }, 336 { 0x1b7a, 0xff } 337 }; 338 339 static const struct cs8409_i2c_param dolphin_c1_init_reg_seq[] = { 340 { 0x1010, 0xB0 }, 341 { 0x1D01, 0x00 }, 342 { 0x1D02, 0x06 }, 343 { 0x1D03, 0x9F }, 344 { 0x1107, 0x01 }, 345 { 0x1009, 0x02 }, 346 { 0x1007, 0x03 }, 347 { 0x1201, 0x00 }, 348 { 0x1208, 0x13 }, 349 { 0x1205, 0xFF }, 350 { 0x1206, 0x00 }, 351 { 0x1207, 0x20 }, 352 { 0x1202, 0x0D }, 353 { 0x2A02, 0x02 }, 354 { 0x2A03, 0x00 }, 355 { 0x2A04, 0x80 }, 356 { 0x2A05, 0x02 }, 357 { 0x2A06, 0x00 }, 358 { 0x2A07, 0xA0 }, 359 { 0x2A01, 0x0C }, 360 { 0x2902, 0x00 }, 361 { 0x2903, 0x02 }, 362 { 0x2904, 0x00 }, 363 { 0x2905, 0x00 }, 364 { 0x2901, 0x00 }, 365 { 0x1101, 0x0E }, 366 { 0x1102, 0x84 }, 367 { 0x2001, 0x01 }, 368 { 0x2301, 0x3F }, 369 { 0x2303, 0x3F }, 370 { 0x2302, 0x3f }, 371 { 0x1B75, 0xB6 }, 372 { 0x1B73, 0xC2 }, 373 { 0x1129, 0x01 }, 374 { 0x1121, 0xF3 }, 375 { 0x1103, 0x20 }, 376 { 0x1105, 0x00 }, 377 { 0x1112, 0x00 }, 378 { 0x1113, 0x80 }, 379 { 0x1C03, 0xC0 }, 380 { 0x1101, 0x06 }, 381 { 0x1316, 0xff }, 382 { 0x1317, 0xff }, 383 { 0x1318, 0xff }, 384 { 0x1319, 0xff }, 385 { 0x131a, 0xff }, 386 { 0x131b, 0xff }, 387 { 0x131c, 0xff }, 388 { 0x131e, 0xff }, 389 { 0x131f, 0xff }, 390 { 0x1320, 0xff }, 391 { 0x1b79, 0xff }, 392 { 0x1b7a, 0xff } 393 }; 394 395 /* Vendor specific hw configuration for CS8409 */ 396 const struct cs8409_cir_param dolphin_hw_cfg[] = { 397 /* +PLL1/2_EN, +I2C_EN */ 398 { CS8409_PIN_VENDOR_WIDGET, CS8409_DEV_CFG1, 0xb008 }, 399 /* ASP1_EN=0, ASP1_STP=1 */ 400 { CS8409_PIN_VENDOR_WIDGET, CS8409_DEV_CFG2, 0x0002 }, 401 /* ASP1/2_BUS_IDLE=10, +GPIO_I2C */ 402 { CS8409_PIN_VENDOR_WIDGET, CS8409_DEV_CFG3, 0x0a80 }, 403 /* ASP1.A: TX.LAP=0, TX.LSZ=24 bits, TX.LCS=0 */ 404 { CS8409_PIN_VENDOR_WIDGET, ASP1_A_TX_CTRL1, 0x0800 }, 405 /* ASP1.A: TX.RAP=0, TX.RSZ=24 bits, TX.RCS=32 */ 406 { CS8409_PIN_VENDOR_WIDGET, ASP1_A_TX_CTRL2, 0x0820 }, 407 /* ASP1.B: TX.LAP=0, TX.LSZ=24 bits, TX.LCS=128 */ 408 { CS8409_PIN_VENDOR_WIDGET, ASP1_B_TX_CTRL1, 0x0880 }, 409 /* ASP1.B: TX.RAP=0, TX.RSZ=24 bits, TX.RCS=160 */ 410 { CS8409_PIN_VENDOR_WIDGET, ASP1_B_TX_CTRL2, 0x08a0 }, 411 /* ASP1.A: RX.LAP=0, RX.LSZ=24 bits, RX.LCS=0 */ 412 { CS8409_PIN_VENDOR_WIDGET, ASP1_A_RX_CTRL1, 0x0800 }, 413 /* ASP1.A: RX.RAP=0, RX.RSZ=24 bits, RX.RCS=0 */ 414 { CS8409_PIN_VENDOR_WIDGET, ASP1_A_RX_CTRL2, 0x0800 }, 415 /* ASP1: LCHI = 00h */ 416 { CS8409_PIN_VENDOR_WIDGET, CS8409_ASP1_CLK_CTRL1, 0x8000 }, 417 /* ASP1: MC/SC_SRCSEL=PLL1, LCPR=FFh */ 418 { CS8409_PIN_VENDOR_WIDGET, CS8409_ASP1_CLK_CTRL2, 0x28ff }, 419 /* ASP1: MCEN=0, FSD=011, SCPOL_IN/OUT=0, SCDIV=1:4 */ 420 { CS8409_PIN_VENDOR_WIDGET, CS8409_ASP1_CLK_CTRL3, 0x0062 }, 421 /* ASP1/2_BEEP=0 */ 422 { CS8409_PIN_VENDOR_WIDGET, CS8409_BEEP_CFG, 0x0000 }, 423 /* ASP1_EN=1, ASP1_STP=1 */ 424 { CS8409_PIN_VENDOR_WIDGET, CS8409_DEV_CFG2, 0x0022 }, 425 /* -PLL2_EN */ 426 { CS8409_PIN_VENDOR_WIDGET, CS8409_DEV_CFG1, 0x9008 }, 427 /* ASP1_xxx_EN=1, ASP1_MCLK_EN=0 */ 428 { CS8409_PIN_VENDOR_WIDGET, CS8409_PAD_CFG_SLW_RATE_CTRL, 0x5400 }, 429 /* test mode on */ 430 { CS8409_PIN_VENDOR_WIDGET, 0xc0, 0x9999 }, 431 /* GPIO hysteresis = 30 us */ 432 { CS8409_PIN_VENDOR_WIDGET, 0xc5, 0x0000 }, 433 /* test mode off */ 434 { CS8409_PIN_VENDOR_WIDGET, 0xc0, 0x0000 }, 435 {} /* Terminator */ 436 }; 437 438 struct sub_codec dolphin_cs42l42_0 = { 439 .addr = DOLPHIN_C0_I2C_ADDR, 440 .reset_gpio = DOLPHIN_C0_RESET, 441 .irq_mask = DOLPHIN_C0_INT, 442 .init_seq = dolphin_c0_init_reg_seq, 443 .init_seq_num = ARRAY_SIZE(dolphin_c0_init_reg_seq), 444 .hp_jack_in = 0, 445 .mic_jack_in = 0, 446 .paged = 1, 447 .suspended = 1, 448 .no_type_dect = 0, 449 }; 450 451 struct sub_codec dolphin_cs42l42_1 = { 452 .addr = DOLPHIN_C1_I2C_ADDR, 453 .reset_gpio = DOLPHIN_C1_RESET, 454 .irq_mask = DOLPHIN_C1_INT, 455 .init_seq = dolphin_c1_init_reg_seq, 456 .init_seq_num = ARRAY_SIZE(dolphin_c1_init_reg_seq), 457 .hp_jack_in = 0, 458 .mic_jack_in = 0, 459 .paged = 1, 460 .suspended = 1, 461 .no_type_dect = 1, 462 }; 463 464 /****************************************************************************** 465 * CS8409 Patch Driver Structs 466 * Arrays Used for all projects using CS8409 467 ******************************************************************************/ 468 469 const struct snd_pci_quirk cs8409_fixup_tbl[] = { 470 SND_PCI_QUIRK(0x1028, 0x0A11, "Bullseye", CS8409_BULLSEYE), 471 SND_PCI_QUIRK(0x1028, 0x0A12, "Bullseye", CS8409_BULLSEYE), 472 SND_PCI_QUIRK(0x1028, 0x0A23, "Bullseye", CS8409_BULLSEYE), 473 SND_PCI_QUIRK(0x1028, 0x0A24, "Bullseye", CS8409_BULLSEYE), 474 SND_PCI_QUIRK(0x1028, 0x0A25, "Bullseye", CS8409_BULLSEYE), 475 SND_PCI_QUIRK(0x1028, 0x0A29, "Bullseye", CS8409_BULLSEYE), 476 SND_PCI_QUIRK(0x1028, 0x0A2A, "Bullseye", CS8409_BULLSEYE), 477 SND_PCI_QUIRK(0x1028, 0x0A2B, "Bullseye", CS8409_BULLSEYE), 478 SND_PCI_QUIRK(0x1028, 0x0AB0, "Warlock", CS8409_WARLOCK), 479 SND_PCI_QUIRK(0x1028, 0x0AB2, "Warlock", CS8409_WARLOCK), 480 SND_PCI_QUIRK(0x1028, 0x0AB1, "Warlock", CS8409_WARLOCK), 481 SND_PCI_QUIRK(0x1028, 0x0AB3, "Warlock", CS8409_WARLOCK), 482 SND_PCI_QUIRK(0x1028, 0x0AB4, "Warlock", CS8409_WARLOCK), 483 SND_PCI_QUIRK(0x1028, 0x0AB5, "Warlock", CS8409_WARLOCK), 484 SND_PCI_QUIRK(0x1028, 0x0AD9, "Warlock", CS8409_WARLOCK), 485 SND_PCI_QUIRK(0x1028, 0x0ADA, "Warlock", CS8409_WARLOCK), 486 SND_PCI_QUIRK(0x1028, 0x0ADB, "Warlock", CS8409_WARLOCK), 487 SND_PCI_QUIRK(0x1028, 0x0ADC, "Warlock", CS8409_WARLOCK), 488 SND_PCI_QUIRK(0x1028, 0x0AF4, "Warlock", CS8409_WARLOCK), 489 SND_PCI_QUIRK(0x1028, 0x0AF5, "Warlock", CS8409_WARLOCK), 490 SND_PCI_QUIRK(0x1028, 0x0A77, "Cyborg", CS8409_CYBORG), 491 SND_PCI_QUIRK(0x1028, 0x0A78, "Cyborg", CS8409_CYBORG), 492 SND_PCI_QUIRK(0x1028, 0x0A79, "Cyborg", CS8409_CYBORG), 493 SND_PCI_QUIRK(0x1028, 0x0A7A, "Cyborg", CS8409_CYBORG), 494 SND_PCI_QUIRK(0x1028, 0x0A7D, "Cyborg", CS8409_CYBORG), 495 SND_PCI_QUIRK(0x1028, 0x0A7E, "Cyborg", CS8409_CYBORG), 496 SND_PCI_QUIRK(0x1028, 0x0A7F, "Cyborg", CS8409_CYBORG), 497 SND_PCI_QUIRK(0x1028, 0x0A80, "Cyborg", CS8409_CYBORG), 498 SND_PCI_QUIRK(0x1028, 0x0ADF, "Cyborg", CS8409_CYBORG), 499 SND_PCI_QUIRK(0x1028, 0x0AE0, "Cyborg", CS8409_CYBORG), 500 SND_PCI_QUIRK(0x1028, 0x0AE1, "Cyborg", CS8409_CYBORG), 501 SND_PCI_QUIRK(0x1028, 0x0AE2, "Cyborg", CS8409_CYBORG), 502 SND_PCI_QUIRK(0x1028, 0x0AE9, "Cyborg", CS8409_CYBORG), 503 SND_PCI_QUIRK(0x1028, 0x0AEA, "Cyborg", CS8409_CYBORG), 504 SND_PCI_QUIRK(0x1028, 0x0AEB, "Cyborg", CS8409_CYBORG), 505 SND_PCI_QUIRK(0x1028, 0x0AEC, "Cyborg", CS8409_CYBORG), 506 SND_PCI_QUIRK(0x1028, 0x0AED, "Cyborg", CS8409_CYBORG), 507 SND_PCI_QUIRK(0x1028, 0x0AEE, "Cyborg", CS8409_CYBORG), 508 SND_PCI_QUIRK(0x1028, 0x0AEF, "Cyborg", CS8409_CYBORG), 509 SND_PCI_QUIRK(0x1028, 0x0AF0, "Cyborg", CS8409_CYBORG), 510 SND_PCI_QUIRK(0x1028, 0x0AD0, "Dolphin", CS8409_DOLPHIN), 511 SND_PCI_QUIRK(0x1028, 0x0AD1, "Dolphin", CS8409_DOLPHIN), 512 SND_PCI_QUIRK(0x1028, 0x0AD2, "Dolphin", CS8409_DOLPHIN), 513 SND_PCI_QUIRK(0x1028, 0x0AD3, "Dolphin", CS8409_DOLPHIN), 514 SND_PCI_QUIRK(0x1028, 0x0ACF, "Dolphin", CS8409_DOLPHIN), 515 {} /* terminator */ 516 }; 517 518 /* Dell Inspiron models with cs8409/cs42l42 */ 519 const struct hda_model_fixup cs8409_models[] = { 520 { .id = CS8409_BULLSEYE, .name = "bullseye" }, 521 { .id = CS8409_WARLOCK, .name = "warlock" }, 522 { .id = CS8409_CYBORG, .name = "cyborg" }, 523 { .id = CS8409_DOLPHIN, .name = "dolphin" }, 524 {} 525 }; 526 527 const struct hda_fixup cs8409_fixups[] = { 528 [CS8409_BULLSEYE] = { 529 .type = HDA_FIXUP_PINS, 530 .v.pins = cs8409_cs42l42_pincfgs, 531 .chained = true, 532 .chain_id = CS8409_FIXUPS, 533 }, 534 [CS8409_WARLOCK] = { 535 .type = HDA_FIXUP_PINS, 536 .v.pins = cs8409_cs42l42_pincfgs, 537 .chained = true, 538 .chain_id = CS8409_FIXUPS, 539 }, 540 [CS8409_CYBORG] = { 541 .type = HDA_FIXUP_PINS, 542 .v.pins = cs8409_cs42l42_pincfgs, 543 .chained = true, 544 .chain_id = CS8409_FIXUPS, 545 }, 546 [CS8409_FIXUPS] = { 547 .type = HDA_FIXUP_FUNC, 548 .v.func = cs8409_cs42l42_fixups, 549 }, 550 [CS8409_DOLPHIN] = { 551 .type = HDA_FIXUP_PINS, 552 .v.pins = dolphin_pincfgs, 553 .chained = true, 554 .chain_id = CS8409_DOLPHIN_FIXUPS, 555 }, 556 [CS8409_DOLPHIN_FIXUPS] = { 557 .type = HDA_FIXUP_FUNC, 558 .v.func = dolphin_fixups, 559 }, 560 }; 561