xref: /linux/sound/pci/hda/patch_ca0132.c (revision bfd5bb6f90af092aa345b15cd78143956a13c2a8)
1 /*
2  * HD audio interface patch for Creative CA0132 chip
3  *
4  * Copyright (c) 2011, Creative Technology Ltd.
5  *
6  * Based on patch_ca0110.c
7  * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de>
8  *
9  *  This driver is free software; you can redistribute it and/or modify
10  *  it under the terms of the GNU General Public License as published by
11  *  the Free Software Foundation; either version 2 of the License, or
12  *  (at your option) any later version.
13  *
14  *  This driver is distributed in the hope that it will be useful,
15  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
16  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  *  GNU General Public License for more details.
18  *
19  *  You should have received a copy of the GNU General Public License
20  *  along with this program; if not, write to the Free Software
21  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
22  */
23 
24 #include <linux/init.h>
25 #include <linux/delay.h>
26 #include <linux/slab.h>
27 #include <linux/mutex.h>
28 #include <linux/module.h>
29 #include <linux/firmware.h>
30 #include <linux/kernel.h>
31 #include <linux/types.h>
32 #include <linux/io.h>
33 #include <linux/pci.h>
34 #include <sound/core.h>
35 #include "hda_codec.h"
36 #include "hda_local.h"
37 #include "hda_auto_parser.h"
38 #include "hda_jack.h"
39 
40 #include "ca0132_regs.h"
41 
42 /* Enable this to see controls for tuning purpose. */
43 /*#define ENABLE_TUNING_CONTROLS*/
44 
45 #ifdef ENABLE_TUNING_CONTROLS
46 #include <sound/tlv.h>
47 #endif
48 
49 #define FLOAT_ZERO	0x00000000
50 #define FLOAT_ONE	0x3f800000
51 #define FLOAT_TWO	0x40000000
52 #define FLOAT_THREE     0x40400000
53 #define FLOAT_EIGHT     0x41000000
54 #define FLOAT_MINUS_5	0xc0a00000
55 
56 #define UNSOL_TAG_DSP	0x16
57 
58 #define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18)
59 #define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15)
60 
61 #define DMA_TRANSFER_FRAME_SIZE_NWORDS		8
62 #define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS	32
63 #define DMA_OVERLAY_FRAME_SIZE_NWORDS		2
64 
65 #define MASTERCONTROL				0x80
66 #define MASTERCONTROL_ALLOC_DMA_CHAN		10
67 #define MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS	60
68 
69 #define WIDGET_CHIP_CTRL      0x15
70 #define WIDGET_DSP_CTRL       0x16
71 
72 #define MEM_CONNID_MICIN1     3
73 #define MEM_CONNID_MICIN2     5
74 #define MEM_CONNID_MICOUT1    12
75 #define MEM_CONNID_MICOUT2    14
76 #define MEM_CONNID_WUH        10
77 #define MEM_CONNID_DSP        16
78 #define MEM_CONNID_DMIC       100
79 
80 #define SCP_SET    0
81 #define SCP_GET    1
82 
83 #define EFX_FILE   "ctefx.bin"
84 #define SBZ_EFX_FILE   "ctefx-sbz.bin"
85 #define R3DI_EFX_FILE  "ctefx-r3di.bin"
86 
87 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
88 MODULE_FIRMWARE(EFX_FILE);
89 MODULE_FIRMWARE(SBZ_EFX_FILE);
90 MODULE_FIRMWARE(R3DI_EFX_FILE);
91 #endif
92 
93 static const char *const dirstr[2] = { "Playback", "Capture" };
94 
95 #define NUM_OF_OUTPUTS 3
96 enum {
97 	SPEAKER_OUT,
98 	HEADPHONE_OUT,
99 	SURROUND_OUT
100 };
101 
102 enum {
103 	DIGITAL_MIC,
104 	LINE_MIC_IN
105 };
106 
107 /* Strings for Input Source Enum Control */
108 static const char *const in_src_str[3] = {"Rear Mic", "Line", "Front Mic" };
109 #define IN_SRC_NUM_OF_INPUTS 3
110 enum {
111 	REAR_MIC,
112 	REAR_LINE_IN,
113 	FRONT_MIC,
114 };
115 
116 enum {
117 #define VNODE_START_NID    0x80
118 	VNID_SPK = VNODE_START_NID,			/* Speaker vnid */
119 	VNID_MIC,
120 	VNID_HP_SEL,
121 	VNID_AMIC1_SEL,
122 	VNID_HP_ASEL,
123 	VNID_AMIC1_ASEL,
124 	VNODE_END_NID,
125 #define VNODES_COUNT  (VNODE_END_NID - VNODE_START_NID)
126 
127 #define EFFECT_START_NID    0x90
128 #define OUT_EFFECT_START_NID    EFFECT_START_NID
129 	SURROUND = OUT_EFFECT_START_NID,
130 	CRYSTALIZER,
131 	DIALOG_PLUS,
132 	SMART_VOLUME,
133 	X_BASS,
134 	EQUALIZER,
135 	OUT_EFFECT_END_NID,
136 #define OUT_EFFECTS_COUNT  (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID)
137 
138 #define IN_EFFECT_START_NID  OUT_EFFECT_END_NID
139 	ECHO_CANCELLATION = IN_EFFECT_START_NID,
140 	VOICE_FOCUS,
141 	MIC_SVM,
142 	NOISE_REDUCTION,
143 	IN_EFFECT_END_NID,
144 #define IN_EFFECTS_COUNT  (IN_EFFECT_END_NID - IN_EFFECT_START_NID)
145 
146 	VOICEFX = IN_EFFECT_END_NID,
147 	PLAY_ENHANCEMENT,
148 	CRYSTAL_VOICE,
149 	EFFECT_END_NID,
150 	OUTPUT_SOURCE_ENUM,
151 	INPUT_SOURCE_ENUM,
152 	XBASS_XOVER,
153 	EQ_PRESET_ENUM,
154 	SMART_VOLUME_ENUM,
155 	MIC_BOOST_ENUM
156 #define EFFECTS_COUNT  (EFFECT_END_NID - EFFECT_START_NID)
157 };
158 
159 /* Effects values size*/
160 #define EFFECT_VALS_MAX_COUNT 12
161 
162 /*
163  * Default values for the effect slider controls, they are in order of their
164  * effect NID's. Surround, Crystalizer, Dialog Plus, Smart Volume, and then
165  * X-bass.
166  */
167 static const unsigned int effect_slider_defaults[] = {67, 65, 50, 74, 50};
168 /* Amount of effect level sliders for ca0132_alt controls. */
169 #define EFFECT_LEVEL_SLIDERS 5
170 
171 /* Latency introduced by DSP blocks in milliseconds. */
172 #define DSP_CAPTURE_INIT_LATENCY        0
173 #define DSP_CRYSTAL_VOICE_LATENCY       124
174 #define DSP_PLAYBACK_INIT_LATENCY       13
175 #define DSP_PLAY_ENHANCEMENT_LATENCY    30
176 #define DSP_SPEAKER_OUT_LATENCY         7
177 
178 struct ct_effect {
179 	char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
180 	hda_nid_t nid;
181 	int mid; /*effect module ID*/
182 	int reqs[EFFECT_VALS_MAX_COUNT]; /*effect module request*/
183 	int direct; /* 0:output; 1:input*/
184 	int params; /* number of default non-on/off params */
185 	/*effect default values, 1st is on/off. */
186 	unsigned int def_vals[EFFECT_VALS_MAX_COUNT];
187 };
188 
189 #define EFX_DIR_OUT 0
190 #define EFX_DIR_IN  1
191 
192 static const struct ct_effect ca0132_effects[EFFECTS_COUNT] = {
193 	{ .name = "Surround",
194 	  .nid = SURROUND,
195 	  .mid = 0x96,
196 	  .reqs = {0, 1},
197 	  .direct = EFX_DIR_OUT,
198 	  .params = 1,
199 	  .def_vals = {0x3F800000, 0x3F2B851F}
200 	},
201 	{ .name = "Crystalizer",
202 	  .nid = CRYSTALIZER,
203 	  .mid = 0x96,
204 	  .reqs = {7, 8},
205 	  .direct = EFX_DIR_OUT,
206 	  .params = 1,
207 	  .def_vals = {0x3F800000, 0x3F266666}
208 	},
209 	{ .name = "Dialog Plus",
210 	  .nid = DIALOG_PLUS,
211 	  .mid = 0x96,
212 	  .reqs = {2, 3},
213 	  .direct = EFX_DIR_OUT,
214 	  .params = 1,
215 	  .def_vals = {0x00000000, 0x3F000000}
216 	},
217 	{ .name = "Smart Volume",
218 	  .nid = SMART_VOLUME,
219 	  .mid = 0x96,
220 	  .reqs = {4, 5, 6},
221 	  .direct = EFX_DIR_OUT,
222 	  .params = 2,
223 	  .def_vals = {0x3F800000, 0x3F3D70A4, 0x00000000}
224 	},
225 	{ .name = "X-Bass",
226 	  .nid = X_BASS,
227 	  .mid = 0x96,
228 	  .reqs = {24, 23, 25},
229 	  .direct = EFX_DIR_OUT,
230 	  .params = 2,
231 	  .def_vals = {0x3F800000, 0x42A00000, 0x3F000000}
232 	},
233 	{ .name = "Equalizer",
234 	  .nid = EQUALIZER,
235 	  .mid = 0x96,
236 	  .reqs = {9, 10, 11, 12, 13, 14,
237 			15, 16, 17, 18, 19, 20},
238 	  .direct = EFX_DIR_OUT,
239 	  .params = 11,
240 	  .def_vals = {0x00000000, 0x00000000, 0x00000000, 0x00000000,
241 		       0x00000000, 0x00000000, 0x00000000, 0x00000000,
242 		       0x00000000, 0x00000000, 0x00000000, 0x00000000}
243 	},
244 	{ .name = "Echo Cancellation",
245 	  .nid = ECHO_CANCELLATION,
246 	  .mid = 0x95,
247 	  .reqs = {0, 1, 2, 3},
248 	  .direct = EFX_DIR_IN,
249 	  .params = 3,
250 	  .def_vals = {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000}
251 	},
252 	{ .name = "Voice Focus",
253 	  .nid = VOICE_FOCUS,
254 	  .mid = 0x95,
255 	  .reqs = {6, 7, 8, 9},
256 	  .direct = EFX_DIR_IN,
257 	  .params = 3,
258 	  .def_vals = {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000}
259 	},
260 	{ .name = "Mic SVM",
261 	  .nid = MIC_SVM,
262 	  .mid = 0x95,
263 	  .reqs = {44, 45},
264 	  .direct = EFX_DIR_IN,
265 	  .params = 1,
266 	  .def_vals = {0x00000000, 0x3F3D70A4}
267 	},
268 	{ .name = "Noise Reduction",
269 	  .nid = NOISE_REDUCTION,
270 	  .mid = 0x95,
271 	  .reqs = {4, 5},
272 	  .direct = EFX_DIR_IN,
273 	  .params = 1,
274 	  .def_vals = {0x3F800000, 0x3F000000}
275 	},
276 	{ .name = "VoiceFX",
277 	  .nid = VOICEFX,
278 	  .mid = 0x95,
279 	  .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18},
280 	  .direct = EFX_DIR_IN,
281 	  .params = 8,
282 	  .def_vals = {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000,
283 		       0x3F800000, 0x3F800000, 0x3F800000, 0x00000000,
284 		       0x00000000}
285 	}
286 };
287 
288 /* Tuning controls */
289 #ifdef ENABLE_TUNING_CONTROLS
290 
291 enum {
292 #define TUNING_CTL_START_NID  0xC0
293 	WEDGE_ANGLE = TUNING_CTL_START_NID,
294 	SVM_LEVEL,
295 	EQUALIZER_BAND_0,
296 	EQUALIZER_BAND_1,
297 	EQUALIZER_BAND_2,
298 	EQUALIZER_BAND_3,
299 	EQUALIZER_BAND_4,
300 	EQUALIZER_BAND_5,
301 	EQUALIZER_BAND_6,
302 	EQUALIZER_BAND_7,
303 	EQUALIZER_BAND_8,
304 	EQUALIZER_BAND_9,
305 	TUNING_CTL_END_NID
306 #define TUNING_CTLS_COUNT  (TUNING_CTL_END_NID - TUNING_CTL_START_NID)
307 };
308 
309 struct ct_tuning_ctl {
310 	char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
311 	hda_nid_t parent_nid;
312 	hda_nid_t nid;
313 	int mid; /*effect module ID*/
314 	int req; /*effect module request*/
315 	int direct; /* 0:output; 1:input*/
316 	unsigned int def_val;/*effect default values*/
317 };
318 
319 static const struct ct_tuning_ctl ca0132_tuning_ctls[] = {
320 	{ .name = "Wedge Angle",
321 	  .parent_nid = VOICE_FOCUS,
322 	  .nid = WEDGE_ANGLE,
323 	  .mid = 0x95,
324 	  .req = 8,
325 	  .direct = EFX_DIR_IN,
326 	  .def_val = 0x41F00000
327 	},
328 	{ .name = "SVM Level",
329 	  .parent_nid = MIC_SVM,
330 	  .nid = SVM_LEVEL,
331 	  .mid = 0x95,
332 	  .req = 45,
333 	  .direct = EFX_DIR_IN,
334 	  .def_val = 0x3F3D70A4
335 	},
336 	{ .name = "EQ Band0",
337 	  .parent_nid = EQUALIZER,
338 	  .nid = EQUALIZER_BAND_0,
339 	  .mid = 0x96,
340 	  .req = 11,
341 	  .direct = EFX_DIR_OUT,
342 	  .def_val = 0x00000000
343 	},
344 	{ .name = "EQ Band1",
345 	  .parent_nid = EQUALIZER,
346 	  .nid = EQUALIZER_BAND_1,
347 	  .mid = 0x96,
348 	  .req = 12,
349 	  .direct = EFX_DIR_OUT,
350 	  .def_val = 0x00000000
351 	},
352 	{ .name = "EQ Band2",
353 	  .parent_nid = EQUALIZER,
354 	  .nid = EQUALIZER_BAND_2,
355 	  .mid = 0x96,
356 	  .req = 13,
357 	  .direct = EFX_DIR_OUT,
358 	  .def_val = 0x00000000
359 	},
360 	{ .name = "EQ Band3",
361 	  .parent_nid = EQUALIZER,
362 	  .nid = EQUALIZER_BAND_3,
363 	  .mid = 0x96,
364 	  .req = 14,
365 	  .direct = EFX_DIR_OUT,
366 	  .def_val = 0x00000000
367 	},
368 	{ .name = "EQ Band4",
369 	  .parent_nid = EQUALIZER,
370 	  .nid = EQUALIZER_BAND_4,
371 	  .mid = 0x96,
372 	  .req = 15,
373 	  .direct = EFX_DIR_OUT,
374 	  .def_val = 0x00000000
375 	},
376 	{ .name = "EQ Band5",
377 	  .parent_nid = EQUALIZER,
378 	  .nid = EQUALIZER_BAND_5,
379 	  .mid = 0x96,
380 	  .req = 16,
381 	  .direct = EFX_DIR_OUT,
382 	  .def_val = 0x00000000
383 	},
384 	{ .name = "EQ Band6",
385 	  .parent_nid = EQUALIZER,
386 	  .nid = EQUALIZER_BAND_6,
387 	  .mid = 0x96,
388 	  .req = 17,
389 	  .direct = EFX_DIR_OUT,
390 	  .def_val = 0x00000000
391 	},
392 	{ .name = "EQ Band7",
393 	  .parent_nid = EQUALIZER,
394 	  .nid = EQUALIZER_BAND_7,
395 	  .mid = 0x96,
396 	  .req = 18,
397 	  .direct = EFX_DIR_OUT,
398 	  .def_val = 0x00000000
399 	},
400 	{ .name = "EQ Band8",
401 	  .parent_nid = EQUALIZER,
402 	  .nid = EQUALIZER_BAND_8,
403 	  .mid = 0x96,
404 	  .req = 19,
405 	  .direct = EFX_DIR_OUT,
406 	  .def_val = 0x00000000
407 	},
408 	{ .name = "EQ Band9",
409 	  .parent_nid = EQUALIZER,
410 	  .nid = EQUALIZER_BAND_9,
411 	  .mid = 0x96,
412 	  .req = 20,
413 	  .direct = EFX_DIR_OUT,
414 	  .def_val = 0x00000000
415 	}
416 };
417 #endif
418 
419 /* Voice FX Presets */
420 #define VOICEFX_MAX_PARAM_COUNT 9
421 
422 struct ct_voicefx {
423 	char *name;
424 	hda_nid_t nid;
425 	int mid;
426 	int reqs[VOICEFX_MAX_PARAM_COUNT]; /*effect module request*/
427 };
428 
429 struct ct_voicefx_preset {
430 	char *name; /*preset name*/
431 	unsigned int vals[VOICEFX_MAX_PARAM_COUNT];
432 };
433 
434 static const struct ct_voicefx ca0132_voicefx = {
435 	.name = "VoiceFX Capture Switch",
436 	.nid = VOICEFX,
437 	.mid = 0x95,
438 	.reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18}
439 };
440 
441 static const struct ct_voicefx_preset ca0132_voicefx_presets[] = {
442 	{ .name = "Neutral",
443 	  .vals = { 0x00000000, 0x43C80000, 0x44AF0000,
444 		    0x44FA0000, 0x3F800000, 0x3F800000,
445 		    0x3F800000, 0x00000000, 0x00000000 }
446 	},
447 	{ .name = "Female2Male",
448 	  .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
449 		    0x44FA0000, 0x3F19999A, 0x3F866666,
450 		    0x3F800000, 0x00000000, 0x00000000 }
451 	},
452 	{ .name = "Male2Female",
453 	  .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
454 		    0x450AC000, 0x4017AE14, 0x3F6B851F,
455 		    0x3F800000, 0x00000000, 0x00000000 }
456 	},
457 	{ .name = "ScrappyKid",
458 	  .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
459 		    0x44FA0000, 0x40400000, 0x3F28F5C3,
460 		    0x3F800000, 0x00000000, 0x00000000 }
461 	},
462 	{ .name = "Elderly",
463 	  .vals = { 0x3F800000, 0x44324000, 0x44BB8000,
464 		    0x44E10000, 0x3FB33333, 0x3FB9999A,
465 		    0x3F800000, 0x3E3A2E43, 0x00000000 }
466 	},
467 	{ .name = "Orc",
468 	  .vals = { 0x3F800000, 0x43EA0000, 0x44A52000,
469 		    0x45098000, 0x3F266666, 0x3FC00000,
470 		    0x3F800000, 0x00000000, 0x00000000 }
471 	},
472 	{ .name = "Elf",
473 	  .vals = { 0x3F800000, 0x43C70000, 0x44AE6000,
474 		    0x45193000, 0x3F8E147B, 0x3F75C28F,
475 		    0x3F800000, 0x00000000, 0x00000000 }
476 	},
477 	{ .name = "Dwarf",
478 	  .vals = { 0x3F800000, 0x43930000, 0x44BEE000,
479 		    0x45007000, 0x3F451EB8, 0x3F7851EC,
480 		    0x3F800000, 0x00000000, 0x00000000 }
481 	},
482 	{ .name = "AlienBrute",
483 	  .vals = { 0x3F800000, 0x43BFC5AC, 0x44B28FDF,
484 		    0x451F6000, 0x3F266666, 0x3FA7D945,
485 		    0x3F800000, 0x3CF5C28F, 0x00000000 }
486 	},
487 	{ .name = "Robot",
488 	  .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
489 		    0x44FA0000, 0x3FB2718B, 0x3F800000,
490 		    0xBC07010E, 0x00000000, 0x00000000 }
491 	},
492 	{ .name = "Marine",
493 	  .vals = { 0x3F800000, 0x43C20000, 0x44906000,
494 		    0x44E70000, 0x3F4CCCCD, 0x3F8A3D71,
495 		    0x3F0A3D71, 0x00000000, 0x00000000 }
496 	},
497 	{ .name = "Emo",
498 	  .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
499 		    0x44FA0000, 0x3F800000, 0x3F800000,
500 		    0x3E4CCCCD, 0x00000000, 0x00000000 }
501 	},
502 	{ .name = "DeepVoice",
503 	  .vals = { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF,
504 		    0x44FFC000, 0x3EDBB56F, 0x3F99C4CA,
505 		    0x3F800000, 0x00000000, 0x00000000 }
506 	},
507 	{ .name = "Munchkin",
508 	  .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
509 		    0x44FA0000, 0x3F800000, 0x3F1A043C,
510 		    0x3F800000, 0x00000000, 0x00000000 }
511 	}
512 };
513 
514 /* ca0132 EQ presets, taken from Windows Sound Blaster Z Driver */
515 
516 #define EQ_PRESET_MAX_PARAM_COUNT 11
517 
518 struct ct_eq {
519 	char *name;
520 	hda_nid_t nid;
521 	int mid;
522 	int reqs[EQ_PRESET_MAX_PARAM_COUNT]; /*effect module request*/
523 };
524 
525 struct ct_eq_preset {
526 	char *name; /*preset name*/
527 	unsigned int vals[EQ_PRESET_MAX_PARAM_COUNT];
528 };
529 
530 static const struct ct_eq ca0132_alt_eq_enum = {
531 	.name = "FX: Equalizer Preset Switch",
532 	.nid = EQ_PRESET_ENUM,
533 	.mid = 0x96,
534 	.reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20}
535 };
536 
537 
538 static const struct ct_eq_preset ca0132_alt_eq_presets[] = {
539 	{ .name = "Flat",
540 	 .vals = { 0x00000000, 0x00000000, 0x00000000,
541 		   0x00000000, 0x00000000, 0x00000000,
542 		   0x00000000, 0x00000000, 0x00000000,
543 		   0x00000000, 0x00000000	     }
544 	},
545 	{ .name = "Acoustic",
546 	 .vals = { 0x00000000, 0x00000000, 0x3F8CCCCD,
547 		   0x40000000, 0x00000000, 0x00000000,
548 		   0x00000000, 0x00000000, 0x40000000,
549 		   0x40000000, 0x40000000	     }
550 	},
551 	{ .name = "Classical",
552 	 .vals = { 0x00000000, 0x00000000, 0x40C00000,
553 		   0x40C00000, 0x40466666, 0x00000000,
554 		   0x00000000, 0x00000000, 0x00000000,
555 		   0x40466666, 0x40466666	     }
556 	},
557 	{ .name = "Country",
558 	 .vals = { 0x00000000, 0xBF99999A, 0x00000000,
559 		   0x3FA66666, 0x3FA66666, 0x3F8CCCCD,
560 		   0x00000000, 0x00000000, 0x40000000,
561 		   0x40466666, 0x40800000	     }
562 	},
563 	{ .name = "Dance",
564 	 .vals = { 0x00000000, 0xBF99999A, 0x40000000,
565 		   0x40466666, 0x40866666, 0xBF99999A,
566 		   0xBF99999A, 0x00000000, 0x00000000,
567 		   0x40800000, 0x40800000	     }
568 	},
569 	{ .name = "Jazz",
570 	 .vals = { 0x00000000, 0x00000000, 0x00000000,
571 		   0x3F8CCCCD, 0x40800000, 0x40800000,
572 		   0x40800000, 0x00000000, 0x3F8CCCCD,
573 		   0x40466666, 0x40466666	     }
574 	},
575 	{ .name = "New Age",
576 	 .vals = { 0x00000000, 0x00000000, 0x40000000,
577 		   0x40000000, 0x00000000, 0x00000000,
578 		   0x00000000, 0x3F8CCCCD, 0x40000000,
579 		   0x40000000, 0x40000000	     }
580 	},
581 	{ .name = "Pop",
582 	 .vals = { 0x00000000, 0xBFCCCCCD, 0x00000000,
583 		   0x40000000, 0x40000000, 0x00000000,
584 		   0xBF99999A, 0xBF99999A, 0x00000000,
585 		   0x40466666, 0x40C00000	     }
586 	},
587 	{ .name = "Rock",
588 	 .vals = { 0x00000000, 0xBF99999A, 0xBF99999A,
589 		   0x3F8CCCCD, 0x40000000, 0xBF99999A,
590 		   0xBF99999A, 0x00000000, 0x00000000,
591 		   0x40800000, 0x40800000	     }
592 	},
593 	{ .name = "Vocal",
594 	 .vals = { 0x00000000, 0xC0000000, 0xBF99999A,
595 		   0xBF99999A, 0x00000000, 0x40466666,
596 		   0x40800000, 0x40466666, 0x00000000,
597 		   0x00000000, 0x3F8CCCCD	     }
598 	}
599 };
600 
601 /* DSP command sequences for ca0132_alt_select_out */
602 #define ALT_OUT_SET_MAX_COMMANDS 9 /* Max number of commands in sequence */
603 struct ca0132_alt_out_set {
604 	char *name; /*preset name*/
605 	unsigned char commands;
606 	unsigned int mids[ALT_OUT_SET_MAX_COMMANDS];
607 	unsigned int reqs[ALT_OUT_SET_MAX_COMMANDS];
608 	unsigned int vals[ALT_OUT_SET_MAX_COMMANDS];
609 };
610 
611 static const struct ca0132_alt_out_set alt_out_presets[] = {
612 	{ .name = "Line Out",
613 	  .commands = 7,
614 	  .mids = { 0x96, 0x96, 0x96, 0x8F,
615 		    0x96, 0x96, 0x96 },
616 	  .reqs = { 0x19, 0x17, 0x18, 0x01,
617 		    0x1F, 0x15, 0x3A },
618 	  .vals = { 0x3F000000, 0x42A00000, 0x00000000,
619 		    0x00000000, 0x00000000, 0x00000000,
620 		    0x00000000 }
621 	},
622 	{ .name = "Headphone",
623 	  .commands = 7,
624 	  .mids = { 0x96, 0x96, 0x96, 0x8F,
625 		    0x96, 0x96, 0x96 },
626 	  .reqs = { 0x19, 0x17, 0x18, 0x01,
627 		    0x1F, 0x15, 0x3A },
628 	  .vals = { 0x3F000000, 0x42A00000, 0x00000000,
629 		    0x00000000, 0x00000000, 0x00000000,
630 		    0x00000000 }
631 	},
632 	{ .name = "Surround",
633 	  .commands = 8,
634 	  .mids = { 0x96, 0x8F, 0x96, 0x96,
635 		    0x96, 0x96, 0x96, 0x96 },
636 	  .reqs = { 0x18, 0x01, 0x1F, 0x15,
637 		    0x3A, 0x1A, 0x1B, 0x1C },
638 	  .vals = { 0x00000000, 0x00000000, 0x00000000,
639 		    0x00000000, 0x00000000, 0x00000000,
640 		    0x00000000, 0x00000000 }
641 	}
642 };
643 
644 /*
645  * DSP volume setting structs. Req 1 is left volume, req 2 is right volume,
646  * and I don't know what the third req is, but it's always zero. I assume it's
647  * some sort of update or set command to tell the DSP there's new volume info.
648  */
649 #define DSP_VOL_OUT 0
650 #define DSP_VOL_IN  1
651 
652 struct ct_dsp_volume_ctl {
653 	hda_nid_t vnid;
654 	int mid; /* module ID*/
655 	unsigned int reqs[3]; /* scp req ID */
656 };
657 
658 static const struct ct_dsp_volume_ctl ca0132_alt_vol_ctls[] = {
659 	{ .vnid = VNID_SPK,
660 	  .mid = 0x32,
661 	  .reqs = {3, 4, 2}
662 	},
663 	{ .vnid = VNID_MIC,
664 	  .mid = 0x37,
665 	  .reqs = {2, 3, 1}
666 	}
667 };
668 
669 enum hda_cmd_vendor_io {
670 	/* for DspIO node */
671 	VENDOR_DSPIO_SCP_WRITE_DATA_LOW      = 0x000,
672 	VENDOR_DSPIO_SCP_WRITE_DATA_HIGH     = 0x100,
673 
674 	VENDOR_DSPIO_STATUS                  = 0xF01,
675 	VENDOR_DSPIO_SCP_POST_READ_DATA      = 0x702,
676 	VENDOR_DSPIO_SCP_READ_DATA           = 0xF02,
677 	VENDOR_DSPIO_DSP_INIT                = 0x703,
678 	VENDOR_DSPIO_SCP_POST_COUNT_QUERY    = 0x704,
679 	VENDOR_DSPIO_SCP_READ_COUNT          = 0xF04,
680 
681 	/* for ChipIO node */
682 	VENDOR_CHIPIO_ADDRESS_LOW            = 0x000,
683 	VENDOR_CHIPIO_ADDRESS_HIGH           = 0x100,
684 	VENDOR_CHIPIO_STREAM_FORMAT          = 0x200,
685 	VENDOR_CHIPIO_DATA_LOW               = 0x300,
686 	VENDOR_CHIPIO_DATA_HIGH              = 0x400,
687 
688 	VENDOR_CHIPIO_GET_PARAMETER          = 0xF00,
689 	VENDOR_CHIPIO_STATUS                 = 0xF01,
690 	VENDOR_CHIPIO_HIC_POST_READ          = 0x702,
691 	VENDOR_CHIPIO_HIC_READ_DATA          = 0xF03,
692 
693 	VENDOR_CHIPIO_8051_DATA_WRITE        = 0x707,
694 	VENDOR_CHIPIO_8051_DATA_READ         = 0xF07,
695 
696 	VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE   = 0x70A,
697 	VENDOR_CHIPIO_CT_EXTENSIONS_GET      = 0xF0A,
698 
699 	VENDOR_CHIPIO_PLL_PMU_WRITE          = 0x70C,
700 	VENDOR_CHIPIO_PLL_PMU_READ           = 0xF0C,
701 	VENDOR_CHIPIO_8051_ADDRESS_LOW       = 0x70D,
702 	VENDOR_CHIPIO_8051_ADDRESS_HIGH      = 0x70E,
703 	VENDOR_CHIPIO_FLAG_SET               = 0x70F,
704 	VENDOR_CHIPIO_FLAGS_GET              = 0xF0F,
705 	VENDOR_CHIPIO_PARAM_SET              = 0x710,
706 	VENDOR_CHIPIO_PARAM_GET              = 0xF10,
707 
708 	VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET  = 0x711,
709 	VENDOR_CHIPIO_PORT_ALLOC_SET         = 0x712,
710 	VENDOR_CHIPIO_PORT_ALLOC_GET         = 0xF12,
711 	VENDOR_CHIPIO_PORT_FREE_SET          = 0x713,
712 
713 	VENDOR_CHIPIO_PARAM_EX_ID_GET        = 0xF17,
714 	VENDOR_CHIPIO_PARAM_EX_ID_SET        = 0x717,
715 	VENDOR_CHIPIO_PARAM_EX_VALUE_GET     = 0xF18,
716 	VENDOR_CHIPIO_PARAM_EX_VALUE_SET     = 0x718,
717 
718 	VENDOR_CHIPIO_DMIC_CTL_SET           = 0x788,
719 	VENDOR_CHIPIO_DMIC_CTL_GET           = 0xF88,
720 	VENDOR_CHIPIO_DMIC_PIN_SET           = 0x789,
721 	VENDOR_CHIPIO_DMIC_PIN_GET           = 0xF89,
722 	VENDOR_CHIPIO_DMIC_MCLK_SET          = 0x78A,
723 	VENDOR_CHIPIO_DMIC_MCLK_GET          = 0xF8A,
724 
725 	VENDOR_CHIPIO_EAPD_SEL_SET           = 0x78D
726 };
727 
728 /*
729  *  Control flag IDs
730  */
731 enum control_flag_id {
732 	/* Connection manager stream setup is bypassed/enabled */
733 	CONTROL_FLAG_C_MGR                  = 0,
734 	/* DSP DMA is bypassed/enabled */
735 	CONTROL_FLAG_DMA                    = 1,
736 	/* 8051 'idle' mode is disabled/enabled */
737 	CONTROL_FLAG_IDLE_ENABLE            = 2,
738 	/* Tracker for the SPDIF-in path is bypassed/enabled */
739 	CONTROL_FLAG_TRACKER                = 3,
740 	/* DigitalOut to Spdif2Out connection is disabled/enabled */
741 	CONTROL_FLAG_SPDIF2OUT              = 4,
742 	/* Digital Microphone is disabled/enabled */
743 	CONTROL_FLAG_DMIC                   = 5,
744 	/* ADC_B rate is 48 kHz/96 kHz */
745 	CONTROL_FLAG_ADC_B_96KHZ            = 6,
746 	/* ADC_C rate is 48 kHz/96 kHz */
747 	CONTROL_FLAG_ADC_C_96KHZ            = 7,
748 	/* DAC rate is 48 kHz/96 kHz (affects all DACs) */
749 	CONTROL_FLAG_DAC_96KHZ              = 8,
750 	/* DSP rate is 48 kHz/96 kHz */
751 	CONTROL_FLAG_DSP_96KHZ              = 9,
752 	/* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */
753 	CONTROL_FLAG_SRC_CLOCK_196MHZ       = 10,
754 	/* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */
755 	CONTROL_FLAG_SRC_RATE_96KHZ         = 11,
756 	/* Decode Loop (DSP->SRC->DSP) is disabled/enabled */
757 	CONTROL_FLAG_DECODE_LOOP            = 12,
758 	/* De-emphasis filter on DAC-1 disabled/enabled */
759 	CONTROL_FLAG_DAC1_DEEMPHASIS        = 13,
760 	/* De-emphasis filter on DAC-2 disabled/enabled */
761 	CONTROL_FLAG_DAC2_DEEMPHASIS        = 14,
762 	/* De-emphasis filter on DAC-3 disabled/enabled */
763 	CONTROL_FLAG_DAC3_DEEMPHASIS        = 15,
764 	/* High-pass filter on ADC_B disabled/enabled */
765 	CONTROL_FLAG_ADC_B_HIGH_PASS        = 16,
766 	/* High-pass filter on ADC_C disabled/enabled */
767 	CONTROL_FLAG_ADC_C_HIGH_PASS        = 17,
768 	/* Common mode on Port_A disabled/enabled */
769 	CONTROL_FLAG_PORT_A_COMMON_MODE     = 18,
770 	/* Common mode on Port_D disabled/enabled */
771 	CONTROL_FLAG_PORT_D_COMMON_MODE     = 19,
772 	/* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */
773 	CONTROL_FLAG_PORT_A_10KOHM_LOAD     = 20,
774 	/* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */
775 	CONTROL_FLAG_PORT_D_10KOHM_LOAD     = 21,
776 	/* ASI rate is 48kHz/96kHz */
777 	CONTROL_FLAG_ASI_96KHZ              = 22,
778 	/* DAC power settings able to control attached ports no/yes */
779 	CONTROL_FLAG_DACS_CONTROL_PORTS     = 23,
780 	/* Clock Stop OK reporting is disabled/enabled */
781 	CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24,
782 	/* Number of control flags */
783 	CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1)
784 };
785 
786 /*
787  * Control parameter IDs
788  */
789 enum control_param_id {
790 	/* 0: None, 1: Mic1In*/
791 	CONTROL_PARAM_VIP_SOURCE               = 1,
792 	/* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */
793 	CONTROL_PARAM_SPDIF1_SOURCE            = 2,
794 	/* Port A output stage gain setting to use when 16 Ohm output
795 	 * impedance is selected*/
796 	CONTROL_PARAM_PORTA_160OHM_GAIN        = 8,
797 	/* Port D output stage gain setting to use when 16 Ohm output
798 	 * impedance is selected*/
799 	CONTROL_PARAM_PORTD_160OHM_GAIN        = 10,
800 
801 	/* Stream Control */
802 
803 	/* Select stream with the given ID */
804 	CONTROL_PARAM_STREAM_ID                = 24,
805 	/* Source connection point for the selected stream */
806 	CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25,
807 	/* Destination connection point for the selected stream */
808 	CONTROL_PARAM_STREAM_DEST_CONN_POINT   = 26,
809 	/* Number of audio channels in the selected stream */
810 	CONTROL_PARAM_STREAMS_CHANNELS         = 27,
811 	/*Enable control for the selected stream */
812 	CONTROL_PARAM_STREAM_CONTROL           = 28,
813 
814 	/* Connection Point Control */
815 
816 	/* Select connection point with the given ID */
817 	CONTROL_PARAM_CONN_POINT_ID            = 29,
818 	/* Connection point sample rate */
819 	CONTROL_PARAM_CONN_POINT_SAMPLE_RATE   = 30,
820 
821 	/* Node Control */
822 
823 	/* Select HDA node with the given ID */
824 	CONTROL_PARAM_NODE_ID                  = 31
825 };
826 
827 /*
828  *  Dsp Io Status codes
829  */
830 enum hda_vendor_status_dspio {
831 	/* Success */
832 	VENDOR_STATUS_DSPIO_OK                       = 0x00,
833 	/* Busy, unable to accept new command, the host must retry */
834 	VENDOR_STATUS_DSPIO_BUSY                     = 0x01,
835 	/* SCP command queue is full */
836 	VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL   = 0x02,
837 	/* SCP response queue is empty */
838 	VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03
839 };
840 
841 /*
842  *  Chip Io Status codes
843  */
844 enum hda_vendor_status_chipio {
845 	/* Success */
846 	VENDOR_STATUS_CHIPIO_OK   = 0x00,
847 	/* Busy, unable to accept new command, the host must retry */
848 	VENDOR_STATUS_CHIPIO_BUSY = 0x01
849 };
850 
851 /*
852  *  CA0132 sample rate
853  */
854 enum ca0132_sample_rate {
855 	SR_6_000        = 0x00,
856 	SR_8_000        = 0x01,
857 	SR_9_600        = 0x02,
858 	SR_11_025       = 0x03,
859 	SR_16_000       = 0x04,
860 	SR_22_050       = 0x05,
861 	SR_24_000       = 0x06,
862 	SR_32_000       = 0x07,
863 	SR_44_100       = 0x08,
864 	SR_48_000       = 0x09,
865 	SR_88_200       = 0x0A,
866 	SR_96_000       = 0x0B,
867 	SR_144_000      = 0x0C,
868 	SR_176_400      = 0x0D,
869 	SR_192_000      = 0x0E,
870 	SR_384_000      = 0x0F,
871 
872 	SR_COUNT        = 0x10,
873 
874 	SR_RATE_UNKNOWN = 0x1F
875 };
876 
877 enum dsp_download_state {
878 	DSP_DOWNLOAD_FAILED = -1,
879 	DSP_DOWNLOAD_INIT   = 0,
880 	DSP_DOWNLOADING     = 1,
881 	DSP_DOWNLOADED      = 2
882 };
883 
884 /* retrieve parameters from hda format */
885 #define get_hdafmt_chs(fmt)	(fmt & 0xf)
886 #define get_hdafmt_bits(fmt)	((fmt >> 4) & 0x7)
887 #define get_hdafmt_rate(fmt)	((fmt >> 8) & 0x7f)
888 #define get_hdafmt_type(fmt)	((fmt >> 15) & 0x1)
889 
890 /*
891  * CA0132 specific
892  */
893 
894 struct ca0132_spec {
895 	const struct snd_kcontrol_new *mixers[5];
896 	unsigned int num_mixers;
897 	const struct hda_verb *base_init_verbs;
898 	const struct hda_verb *base_exit_verbs;
899 	const struct hda_verb *chip_init_verbs;
900 	const struct hda_verb *sbz_init_verbs;
901 	struct hda_verb *spec_init_verbs;
902 	struct auto_pin_cfg autocfg;
903 
904 	/* Nodes configurations */
905 	struct hda_multi_out multiout;
906 	hda_nid_t out_pins[AUTO_CFG_MAX_OUTS];
907 	hda_nid_t dacs[AUTO_CFG_MAX_OUTS];
908 	unsigned int num_outputs;
909 	hda_nid_t input_pins[AUTO_PIN_LAST];
910 	hda_nid_t adcs[AUTO_PIN_LAST];
911 	hda_nid_t dig_out;
912 	hda_nid_t dig_in;
913 	unsigned int num_inputs;
914 	hda_nid_t shared_mic_nid;
915 	hda_nid_t shared_out_nid;
916 	hda_nid_t unsol_tag_hp;
917 	hda_nid_t unsol_tag_front_hp; /* for desktop ca0132 codecs */
918 	hda_nid_t unsol_tag_amic1;
919 
920 	/* chip access */
921 	struct mutex chipio_mutex; /* chip access mutex */
922 	u32 curr_chip_addx;
923 
924 	/* DSP download related */
925 	enum dsp_download_state dsp_state;
926 	unsigned int dsp_stream_id;
927 	unsigned int wait_scp;
928 	unsigned int wait_scp_header;
929 	unsigned int wait_num_data;
930 	unsigned int scp_resp_header;
931 	unsigned int scp_resp_data[4];
932 	unsigned int scp_resp_count;
933 	bool alt_firmware_present;
934 	bool startup_check_entered;
935 	bool dsp_reload;
936 
937 	/* mixer and effects related */
938 	unsigned char dmic_ctl;
939 	int cur_out_type;
940 	int cur_mic_type;
941 	long vnode_lvol[VNODES_COUNT];
942 	long vnode_rvol[VNODES_COUNT];
943 	long vnode_lswitch[VNODES_COUNT];
944 	long vnode_rswitch[VNODES_COUNT];
945 	long effects_switch[EFFECTS_COUNT];
946 	long voicefx_val;
947 	long cur_mic_boost;
948 	/* ca0132_alt control related values */
949 	unsigned char in_enum_val;
950 	unsigned char out_enum_val;
951 	unsigned char mic_boost_enum_val;
952 	unsigned char smart_volume_setting;
953 	long fx_ctl_val[EFFECT_LEVEL_SLIDERS];
954 	long xbass_xover_freq;
955 	long eq_preset_val;
956 	unsigned int tlv[4];
957 	struct hda_vmaster_mute_hook vmaster_mute;
958 
959 
960 	struct hda_codec *codec;
961 	struct delayed_work unsol_hp_work;
962 	int quirk;
963 
964 #ifdef ENABLE_TUNING_CONTROLS
965 	long cur_ctl_vals[TUNING_CTLS_COUNT];
966 #endif
967 	/*
968 	 * Sound Blaster Z PCI region 2 iomem, used for input and output
969 	 * switching, and other unknown commands.
970 	 */
971 	void __iomem *mem_base;
972 
973 	/*
974 	 * Whether or not to use the alt functions like alt_select_out,
975 	 * alt_select_in, etc. Only used on desktop codecs for now, because of
976 	 * surround sound support.
977 	 */
978 	bool use_alt_functions;
979 
980 	/*
981 	 * Whether or not to use alt controls:	volume effect sliders, EQ
982 	 * presets, smart volume presets, and new control names with FX prefix.
983 	 * Renames PlayEnhancement and CrystalVoice too.
984 	 */
985 	bool use_alt_controls;
986 };
987 
988 /*
989  * CA0132 quirks table
990  */
991 enum {
992 	QUIRK_NONE,
993 	QUIRK_ALIENWARE,
994 	QUIRK_ALIENWARE_M17XR4,
995 	QUIRK_SBZ,
996 	QUIRK_R3DI,
997 };
998 
999 static const struct hda_pintbl alienware_pincfgs[] = {
1000 	{ 0x0b, 0x90170110 }, /* Builtin Speaker */
1001 	{ 0x0c, 0x411111f0 }, /* N/A */
1002 	{ 0x0d, 0x411111f0 }, /* N/A */
1003 	{ 0x0e, 0x411111f0 }, /* N/A */
1004 	{ 0x0f, 0x0321101f }, /* HP */
1005 	{ 0x10, 0x411111f0 }, /* Headset?  disabled for now */
1006 	{ 0x11, 0x03a11021 }, /* Mic */
1007 	{ 0x12, 0xd5a30140 }, /* Builtin Mic */
1008 	{ 0x13, 0x411111f0 }, /* N/A */
1009 	{ 0x18, 0x411111f0 }, /* N/A */
1010 	{}
1011 };
1012 
1013 /* Sound Blaster Z pin configs taken from Windows Driver */
1014 static const struct hda_pintbl sbz_pincfgs[] = {
1015 	{ 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */
1016 	{ 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1017 	{ 0x0d, 0x014510f0 }, /* Digital Out */
1018 	{ 0x0e, 0x01c510f0 }, /* SPDIF In */
1019 	{ 0x0f, 0x0221701f }, /* Port A -- BackPanel HP */
1020 	{ 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */
1021 	{ 0x11, 0x01017014 }, /* Port B -- LineMicIn2 / Rear L/R */
1022 	{ 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */
1023 	{ 0x13, 0x908700f0 }, /* What U Hear In*/
1024 	{ 0x18, 0x50d000f0 }, /* N/A */
1025 	{}
1026 };
1027 
1028 /* Recon3D integrated pin configs taken from Windows Driver */
1029 static const struct hda_pintbl r3di_pincfgs[] = {
1030 	{ 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */
1031 	{ 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1032 	{ 0x0d, 0x014510f0 }, /* Digital Out */
1033 	{ 0x0e, 0x41c520f0 }, /* SPDIF In */
1034 	{ 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */
1035 	{ 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */
1036 	{ 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */
1037 	{ 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */
1038 	{ 0x13, 0x908700f0 }, /* What U Hear In*/
1039 	{ 0x18, 0x500000f0 }, /* N/A */
1040 	{}
1041 };
1042 
1043 static const struct snd_pci_quirk ca0132_quirks[] = {
1044 	SND_PCI_QUIRK(0x1028, 0x057b, "Alienware M17x R4", QUIRK_ALIENWARE_M17XR4),
1045 	SND_PCI_QUIRK(0x1028, 0x0685, "Alienware 15 2015", QUIRK_ALIENWARE),
1046 	SND_PCI_QUIRK(0x1028, 0x0688, "Alienware 17 2015", QUIRK_ALIENWARE),
1047 	SND_PCI_QUIRK(0x1028, 0x0708, "Alienware 15 R2 2016", QUIRK_ALIENWARE),
1048 	SND_PCI_QUIRK(0x1102, 0x0010, "Sound Blaster Z", QUIRK_SBZ),
1049 	SND_PCI_QUIRK(0x1102, 0x0023, "Sound Blaster Z", QUIRK_SBZ),
1050 	SND_PCI_QUIRK(0x1458, 0xA016, "Recon3Di", QUIRK_R3DI),
1051 	SND_PCI_QUIRK(0x1458, 0xA026, "Gigabyte G1.Sniper Z97", QUIRK_R3DI),
1052 	SND_PCI_QUIRK(0x1458, 0xA036, "Gigabyte GA-Z170X-Gaming 7", QUIRK_R3DI),
1053 	{}
1054 };
1055 
1056 /*
1057  * CA0132 codec access
1058  */
1059 static unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid,
1060 		unsigned int verb, unsigned int parm, unsigned int *res)
1061 {
1062 	unsigned int response;
1063 	response = snd_hda_codec_read(codec, nid, 0, verb, parm);
1064 	*res = response;
1065 
1066 	return ((response == -1) ? -1 : 0);
1067 }
1068 
1069 static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid,
1070 		unsigned short converter_format, unsigned int *res)
1071 {
1072 	return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT,
1073 				converter_format & 0xffff, res);
1074 }
1075 
1076 static int codec_set_converter_stream_channel(struct hda_codec *codec,
1077 				hda_nid_t nid, unsigned char stream,
1078 				unsigned char channel, unsigned int *res)
1079 {
1080 	unsigned char converter_stream_channel = 0;
1081 
1082 	converter_stream_channel = (stream << 4) | (channel & 0x0f);
1083 	return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID,
1084 				converter_stream_channel, res);
1085 }
1086 
1087 /* Chip access helper function */
1088 static int chipio_send(struct hda_codec *codec,
1089 		       unsigned int reg,
1090 		       unsigned int data)
1091 {
1092 	unsigned int res;
1093 	unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1094 
1095 	/* send bits of data specified by reg */
1096 	do {
1097 		res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1098 					 reg, data);
1099 		if (res == VENDOR_STATUS_CHIPIO_OK)
1100 			return 0;
1101 		msleep(20);
1102 	} while (time_before(jiffies, timeout));
1103 
1104 	return -EIO;
1105 }
1106 
1107 /*
1108  * Write chip address through the vendor widget -- NOT protected by the Mutex!
1109  */
1110 static int chipio_write_address(struct hda_codec *codec,
1111 				unsigned int chip_addx)
1112 {
1113 	struct ca0132_spec *spec = codec->spec;
1114 	int res;
1115 
1116 	if (spec->curr_chip_addx == chip_addx)
1117 			return 0;
1118 
1119 	/* send low 16 bits of the address */
1120 	res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW,
1121 			  chip_addx & 0xffff);
1122 
1123 	if (res != -EIO) {
1124 		/* send high 16 bits of the address */
1125 		res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH,
1126 				  chip_addx >> 16);
1127 	}
1128 
1129 	spec->curr_chip_addx = (res < 0) ? ~0U : chip_addx;
1130 
1131 	return res;
1132 }
1133 
1134 /*
1135  * Write data through the vendor widget -- NOT protected by the Mutex!
1136  */
1137 static int chipio_write_data(struct hda_codec *codec, unsigned int data)
1138 {
1139 	struct ca0132_spec *spec = codec->spec;
1140 	int res;
1141 
1142 	/* send low 16 bits of the data */
1143 	res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff);
1144 
1145 	if (res != -EIO) {
1146 		/* send high 16 bits of the data */
1147 		res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH,
1148 				  data >> 16);
1149 	}
1150 
1151 	/*If no error encountered, automatically increment the address
1152 	as per chip behaviour*/
1153 	spec->curr_chip_addx = (res != -EIO) ?
1154 					(spec->curr_chip_addx + 4) : ~0U;
1155 	return res;
1156 }
1157 
1158 /*
1159  * Write multiple data through the vendor widget -- NOT protected by the Mutex!
1160  */
1161 static int chipio_write_data_multiple(struct hda_codec *codec,
1162 				      const u32 *data,
1163 				      unsigned int count)
1164 {
1165 	int status = 0;
1166 
1167 	if (data == NULL) {
1168 		codec_dbg(codec, "chipio_write_data null ptr\n");
1169 		return -EINVAL;
1170 	}
1171 
1172 	while ((count-- != 0) && (status == 0))
1173 		status = chipio_write_data(codec, *data++);
1174 
1175 	return status;
1176 }
1177 
1178 
1179 /*
1180  * Read data through the vendor widget -- NOT protected by the Mutex!
1181  */
1182 static int chipio_read_data(struct hda_codec *codec, unsigned int *data)
1183 {
1184 	struct ca0132_spec *spec = codec->spec;
1185 	int res;
1186 
1187 	/* post read */
1188 	res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0);
1189 
1190 	if (res != -EIO) {
1191 		/* read status */
1192 		res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1193 	}
1194 
1195 	if (res != -EIO) {
1196 		/* read data */
1197 		*data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1198 					   VENDOR_CHIPIO_HIC_READ_DATA,
1199 					   0);
1200 	}
1201 
1202 	/*If no error encountered, automatically increment the address
1203 	as per chip behaviour*/
1204 	spec->curr_chip_addx = (res != -EIO) ?
1205 					(spec->curr_chip_addx + 4) : ~0U;
1206 	return res;
1207 }
1208 
1209 /*
1210  * Write given value to the given address through the chip I/O widget.
1211  * protected by the Mutex
1212  */
1213 static int chipio_write(struct hda_codec *codec,
1214 		unsigned int chip_addx, const unsigned int data)
1215 {
1216 	struct ca0132_spec *spec = codec->spec;
1217 	int err;
1218 
1219 	mutex_lock(&spec->chipio_mutex);
1220 
1221 	/* write the address, and if successful proceed to write data */
1222 	err = chipio_write_address(codec, chip_addx);
1223 	if (err < 0)
1224 		goto exit;
1225 
1226 	err = chipio_write_data(codec, data);
1227 	if (err < 0)
1228 		goto exit;
1229 
1230 exit:
1231 	mutex_unlock(&spec->chipio_mutex);
1232 	return err;
1233 }
1234 
1235 /*
1236  * Write given value to the given address through the chip I/O widget.
1237  * not protected by the Mutex
1238  */
1239 static int chipio_write_no_mutex(struct hda_codec *codec,
1240 		unsigned int chip_addx, const unsigned int data)
1241 {
1242 	int err;
1243 
1244 
1245 	/* write the address, and if successful proceed to write data */
1246 	err = chipio_write_address(codec, chip_addx);
1247 	if (err < 0)
1248 		goto exit;
1249 
1250 	err = chipio_write_data(codec, data);
1251 	if (err < 0)
1252 		goto exit;
1253 
1254 exit:
1255 	return err;
1256 }
1257 
1258 /*
1259  * Write multiple values to the given address through the chip I/O widget.
1260  * protected by the Mutex
1261  */
1262 static int chipio_write_multiple(struct hda_codec *codec,
1263 				 u32 chip_addx,
1264 				 const u32 *data,
1265 				 unsigned int count)
1266 {
1267 	struct ca0132_spec *spec = codec->spec;
1268 	int status;
1269 
1270 	mutex_lock(&spec->chipio_mutex);
1271 	status = chipio_write_address(codec, chip_addx);
1272 	if (status < 0)
1273 		goto error;
1274 
1275 	status = chipio_write_data_multiple(codec, data, count);
1276 error:
1277 	mutex_unlock(&spec->chipio_mutex);
1278 
1279 	return status;
1280 }
1281 
1282 /*
1283  * Read the given address through the chip I/O widget
1284  * protected by the Mutex
1285  */
1286 static int chipio_read(struct hda_codec *codec,
1287 		unsigned int chip_addx, unsigned int *data)
1288 {
1289 	struct ca0132_spec *spec = codec->spec;
1290 	int err;
1291 
1292 	mutex_lock(&spec->chipio_mutex);
1293 
1294 	/* write the address, and if successful proceed to write data */
1295 	err = chipio_write_address(codec, chip_addx);
1296 	if (err < 0)
1297 		goto exit;
1298 
1299 	err = chipio_read_data(codec, data);
1300 	if (err < 0)
1301 		goto exit;
1302 
1303 exit:
1304 	mutex_unlock(&spec->chipio_mutex);
1305 	return err;
1306 }
1307 
1308 /*
1309  * Set chip control flags through the chip I/O widget.
1310  */
1311 static void chipio_set_control_flag(struct hda_codec *codec,
1312 				    enum control_flag_id flag_id,
1313 				    bool flag_state)
1314 {
1315 	unsigned int val;
1316 	unsigned int flag_bit;
1317 
1318 	flag_bit = (flag_state ? 1 : 0);
1319 	val = (flag_bit << 7) | (flag_id);
1320 	snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1321 			    VENDOR_CHIPIO_FLAG_SET, val);
1322 }
1323 
1324 /*
1325  * Set chip parameters through the chip I/O widget.
1326  */
1327 static void chipio_set_control_param(struct hda_codec *codec,
1328 		enum control_param_id param_id, int param_val)
1329 {
1330 	struct ca0132_spec *spec = codec->spec;
1331 	int val;
1332 
1333 	if ((param_id < 32) && (param_val < 8)) {
1334 		val = (param_val << 5) | (param_id);
1335 		snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1336 				    VENDOR_CHIPIO_PARAM_SET, val);
1337 	} else {
1338 		mutex_lock(&spec->chipio_mutex);
1339 		if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1340 			snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1341 					    VENDOR_CHIPIO_PARAM_EX_ID_SET,
1342 					    param_id);
1343 			snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1344 					    VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1345 					    param_val);
1346 		}
1347 		mutex_unlock(&spec->chipio_mutex);
1348 	}
1349 }
1350 
1351 /*
1352  * Set chip parameters through the chip I/O widget. NO MUTEX.
1353  */
1354 static void chipio_set_control_param_no_mutex(struct hda_codec *codec,
1355 		enum control_param_id param_id, int param_val)
1356 {
1357 	int val;
1358 
1359 	if ((param_id < 32) && (param_val < 8)) {
1360 		val = (param_val << 5) | (param_id);
1361 		snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1362 				    VENDOR_CHIPIO_PARAM_SET, val);
1363 	} else {
1364 		if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1365 			snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1366 					    VENDOR_CHIPIO_PARAM_EX_ID_SET,
1367 					    param_id);
1368 			snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1369 					    VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1370 					    param_val);
1371 		}
1372 	}
1373 }
1374 /*
1375  * Connect stream to a source point, and then connect
1376  * that source point to a destination point.
1377  */
1378 static void chipio_set_stream_source_dest(struct hda_codec *codec,
1379 				int streamid, int source_point, int dest_point)
1380 {
1381 	chipio_set_control_param_no_mutex(codec,
1382 			CONTROL_PARAM_STREAM_ID, streamid);
1383 	chipio_set_control_param_no_mutex(codec,
1384 			CONTROL_PARAM_STREAM_SOURCE_CONN_POINT, source_point);
1385 	chipio_set_control_param_no_mutex(codec,
1386 			CONTROL_PARAM_STREAM_DEST_CONN_POINT, dest_point);
1387 }
1388 
1389 /*
1390  * Set number of channels in the selected stream.
1391  */
1392 static void chipio_set_stream_channels(struct hda_codec *codec,
1393 				int streamid, unsigned int channels)
1394 {
1395 	chipio_set_control_param_no_mutex(codec,
1396 			CONTROL_PARAM_STREAM_ID, streamid);
1397 	chipio_set_control_param_no_mutex(codec,
1398 			CONTROL_PARAM_STREAMS_CHANNELS, channels);
1399 }
1400 
1401 /*
1402  * Enable/Disable audio stream.
1403  */
1404 static void chipio_set_stream_control(struct hda_codec *codec,
1405 				int streamid, int enable)
1406 {
1407 	chipio_set_control_param_no_mutex(codec,
1408 			CONTROL_PARAM_STREAM_ID, streamid);
1409 	chipio_set_control_param_no_mutex(codec,
1410 			CONTROL_PARAM_STREAM_CONTROL, enable);
1411 }
1412 
1413 
1414 /*
1415  * Set sampling rate of the connection point. NO MUTEX.
1416  */
1417 static void chipio_set_conn_rate_no_mutex(struct hda_codec *codec,
1418 				int connid, enum ca0132_sample_rate rate)
1419 {
1420 	chipio_set_control_param_no_mutex(codec,
1421 			CONTROL_PARAM_CONN_POINT_ID, connid);
1422 	chipio_set_control_param_no_mutex(codec,
1423 			CONTROL_PARAM_CONN_POINT_SAMPLE_RATE, rate);
1424 }
1425 
1426 /*
1427  * Set sampling rate of the connection point.
1428  */
1429 static void chipio_set_conn_rate(struct hda_codec *codec,
1430 				int connid, enum ca0132_sample_rate rate)
1431 {
1432 	chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid);
1433 	chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE,
1434 				 rate);
1435 }
1436 
1437 /*
1438  * Enable clocks.
1439  */
1440 static void chipio_enable_clocks(struct hda_codec *codec)
1441 {
1442 	struct ca0132_spec *spec = codec->spec;
1443 
1444 	mutex_lock(&spec->chipio_mutex);
1445 	snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1446 			    VENDOR_CHIPIO_8051_ADDRESS_LOW, 0);
1447 	snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1448 			    VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1449 	snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1450 			    VENDOR_CHIPIO_8051_ADDRESS_LOW, 5);
1451 	snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1452 			    VENDOR_CHIPIO_PLL_PMU_WRITE, 0x0b);
1453 	snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1454 			    VENDOR_CHIPIO_8051_ADDRESS_LOW, 6);
1455 	snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1456 			    VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1457 	mutex_unlock(&spec->chipio_mutex);
1458 }
1459 
1460 /*
1461  * CA0132 DSP IO stuffs
1462  */
1463 static int dspio_send(struct hda_codec *codec, unsigned int reg,
1464 		      unsigned int data)
1465 {
1466 	int res;
1467 	unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1468 
1469 	/* send bits of data specified by reg to dsp */
1470 	do {
1471 		res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data);
1472 		if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY))
1473 			return res;
1474 		msleep(20);
1475 	} while (time_before(jiffies, timeout));
1476 
1477 	return -EIO;
1478 }
1479 
1480 /*
1481  * Wait for DSP to be ready for commands
1482  */
1483 static void dspio_write_wait(struct hda_codec *codec)
1484 {
1485 	int status;
1486 	unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1487 
1488 	do {
1489 		status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1490 						VENDOR_DSPIO_STATUS, 0);
1491 		if ((status == VENDOR_STATUS_DSPIO_OK) ||
1492 		    (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY))
1493 			break;
1494 		msleep(1);
1495 	} while (time_before(jiffies, timeout));
1496 }
1497 
1498 /*
1499  * Write SCP data to DSP
1500  */
1501 static int dspio_write(struct hda_codec *codec, unsigned int scp_data)
1502 {
1503 	struct ca0132_spec *spec = codec->spec;
1504 	int status;
1505 
1506 	dspio_write_wait(codec);
1507 
1508 	mutex_lock(&spec->chipio_mutex);
1509 	status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW,
1510 			    scp_data & 0xffff);
1511 	if (status < 0)
1512 		goto error;
1513 
1514 	status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH,
1515 				    scp_data >> 16);
1516 	if (status < 0)
1517 		goto error;
1518 
1519 	/* OK, now check if the write itself has executed*/
1520 	status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1521 				    VENDOR_DSPIO_STATUS, 0);
1522 error:
1523 	mutex_unlock(&spec->chipio_mutex);
1524 
1525 	return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ?
1526 			-EIO : 0;
1527 }
1528 
1529 /*
1530  * Write multiple SCP data to DSP
1531  */
1532 static int dspio_write_multiple(struct hda_codec *codec,
1533 				unsigned int *buffer, unsigned int size)
1534 {
1535 	int status = 0;
1536 	unsigned int count;
1537 
1538 	if (buffer == NULL)
1539 		return -EINVAL;
1540 
1541 	count = 0;
1542 	while (count < size) {
1543 		status = dspio_write(codec, *buffer++);
1544 		if (status != 0)
1545 			break;
1546 		count++;
1547 	}
1548 
1549 	return status;
1550 }
1551 
1552 static int dspio_read(struct hda_codec *codec, unsigned int *data)
1553 {
1554 	int status;
1555 
1556 	status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0);
1557 	if (status == -EIO)
1558 		return status;
1559 
1560 	status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0);
1561 	if (status == -EIO ||
1562 	    status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY)
1563 		return -EIO;
1564 
1565 	*data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1566 				   VENDOR_DSPIO_SCP_READ_DATA, 0);
1567 
1568 	return 0;
1569 }
1570 
1571 static int dspio_read_multiple(struct hda_codec *codec, unsigned int *buffer,
1572 			       unsigned int *buf_size, unsigned int size_count)
1573 {
1574 	int status = 0;
1575 	unsigned int size = *buf_size;
1576 	unsigned int count;
1577 	unsigned int skip_count;
1578 	unsigned int dummy;
1579 
1580 	if (buffer == NULL)
1581 		return -1;
1582 
1583 	count = 0;
1584 	while (count < size && count < size_count) {
1585 		status = dspio_read(codec, buffer++);
1586 		if (status != 0)
1587 			break;
1588 		count++;
1589 	}
1590 
1591 	skip_count = count;
1592 	if (status == 0) {
1593 		while (skip_count < size) {
1594 			status = dspio_read(codec, &dummy);
1595 			if (status != 0)
1596 				break;
1597 			skip_count++;
1598 		}
1599 	}
1600 	*buf_size = count;
1601 
1602 	return status;
1603 }
1604 
1605 /*
1606  * Construct the SCP header using corresponding fields
1607  */
1608 static inline unsigned int
1609 make_scp_header(unsigned int target_id, unsigned int source_id,
1610 		unsigned int get_flag, unsigned int req,
1611 		unsigned int device_flag, unsigned int resp_flag,
1612 		unsigned int error_flag, unsigned int data_size)
1613 {
1614 	unsigned int header = 0;
1615 
1616 	header = (data_size & 0x1f) << 27;
1617 	header |= (error_flag & 0x01) << 26;
1618 	header |= (resp_flag & 0x01) << 25;
1619 	header |= (device_flag & 0x01) << 24;
1620 	header |= (req & 0x7f) << 17;
1621 	header |= (get_flag & 0x01) << 16;
1622 	header |= (source_id & 0xff) << 8;
1623 	header |= target_id & 0xff;
1624 
1625 	return header;
1626 }
1627 
1628 /*
1629  * Extract corresponding fields from SCP header
1630  */
1631 static inline void
1632 extract_scp_header(unsigned int header,
1633 		   unsigned int *target_id, unsigned int *source_id,
1634 		   unsigned int *get_flag, unsigned int *req,
1635 		   unsigned int *device_flag, unsigned int *resp_flag,
1636 		   unsigned int *error_flag, unsigned int *data_size)
1637 {
1638 	if (data_size)
1639 		*data_size = (header >> 27) & 0x1f;
1640 	if (error_flag)
1641 		*error_flag = (header >> 26) & 0x01;
1642 	if (resp_flag)
1643 		*resp_flag = (header >> 25) & 0x01;
1644 	if (device_flag)
1645 		*device_flag = (header >> 24) & 0x01;
1646 	if (req)
1647 		*req = (header >> 17) & 0x7f;
1648 	if (get_flag)
1649 		*get_flag = (header >> 16) & 0x01;
1650 	if (source_id)
1651 		*source_id = (header >> 8) & 0xff;
1652 	if (target_id)
1653 		*target_id = header & 0xff;
1654 }
1655 
1656 #define SCP_MAX_DATA_WORDS  (16)
1657 
1658 /* Structure to contain any SCP message */
1659 struct scp_msg {
1660 	unsigned int hdr;
1661 	unsigned int data[SCP_MAX_DATA_WORDS];
1662 };
1663 
1664 static void dspio_clear_response_queue(struct hda_codec *codec)
1665 {
1666 	unsigned int dummy = 0;
1667 	int status = -1;
1668 
1669 	/* clear all from the response queue */
1670 	do {
1671 		status = dspio_read(codec, &dummy);
1672 	} while (status == 0);
1673 }
1674 
1675 static int dspio_get_response_data(struct hda_codec *codec)
1676 {
1677 	struct ca0132_spec *spec = codec->spec;
1678 	unsigned int data = 0;
1679 	unsigned int count;
1680 
1681 	if (dspio_read(codec, &data) < 0)
1682 		return -EIO;
1683 
1684 	if ((data & 0x00ffffff) == spec->wait_scp_header) {
1685 		spec->scp_resp_header = data;
1686 		spec->scp_resp_count = data >> 27;
1687 		count = spec->wait_num_data;
1688 		dspio_read_multiple(codec, spec->scp_resp_data,
1689 				    &spec->scp_resp_count, count);
1690 		return 0;
1691 	}
1692 
1693 	return -EIO;
1694 }
1695 
1696 /*
1697  * Send SCP message to DSP
1698  */
1699 static int dspio_send_scp_message(struct hda_codec *codec,
1700 				  unsigned char *send_buf,
1701 				  unsigned int send_buf_size,
1702 				  unsigned char *return_buf,
1703 				  unsigned int return_buf_size,
1704 				  unsigned int *bytes_returned)
1705 {
1706 	struct ca0132_spec *spec = codec->spec;
1707 	int status = -1;
1708 	unsigned int scp_send_size = 0;
1709 	unsigned int total_size;
1710 	bool waiting_for_resp = false;
1711 	unsigned int header;
1712 	struct scp_msg *ret_msg;
1713 	unsigned int resp_src_id, resp_target_id;
1714 	unsigned int data_size, src_id, target_id, get_flag, device_flag;
1715 
1716 	if (bytes_returned)
1717 		*bytes_returned = 0;
1718 
1719 	/* get scp header from buffer */
1720 	header = *((unsigned int *)send_buf);
1721 	extract_scp_header(header, &target_id, &src_id, &get_flag, NULL,
1722 			   &device_flag, NULL, NULL, &data_size);
1723 	scp_send_size = data_size + 1;
1724 	total_size = (scp_send_size * 4);
1725 
1726 	if (send_buf_size < total_size)
1727 		return -EINVAL;
1728 
1729 	if (get_flag || device_flag) {
1730 		if (!return_buf || return_buf_size < 4 || !bytes_returned)
1731 			return -EINVAL;
1732 
1733 		spec->wait_scp_header = *((unsigned int *)send_buf);
1734 
1735 		/* swap source id with target id */
1736 		resp_target_id = src_id;
1737 		resp_src_id = target_id;
1738 		spec->wait_scp_header &= 0xffff0000;
1739 		spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id);
1740 		spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1;
1741 		spec->wait_scp = 1;
1742 		waiting_for_resp = true;
1743 	}
1744 
1745 	status = dspio_write_multiple(codec, (unsigned int *)send_buf,
1746 				      scp_send_size);
1747 	if (status < 0) {
1748 		spec->wait_scp = 0;
1749 		return status;
1750 	}
1751 
1752 	if (waiting_for_resp) {
1753 		unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1754 		memset(return_buf, 0, return_buf_size);
1755 		do {
1756 			msleep(20);
1757 		} while (spec->wait_scp && time_before(jiffies, timeout));
1758 		waiting_for_resp = false;
1759 		if (!spec->wait_scp) {
1760 			ret_msg = (struct scp_msg *)return_buf;
1761 			memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4);
1762 			memcpy(&ret_msg->data, spec->scp_resp_data,
1763 			       spec->wait_num_data);
1764 			*bytes_returned = (spec->scp_resp_count + 1) * 4;
1765 			status = 0;
1766 		} else {
1767 			status = -EIO;
1768 		}
1769 		spec->wait_scp = 0;
1770 	}
1771 
1772 	return status;
1773 }
1774 
1775 /**
1776  * Prepare and send the SCP message to DSP
1777  * @codec: the HDA codec
1778  * @mod_id: ID of the DSP module to send the command
1779  * @req: ID of request to send to the DSP module
1780  * @dir: SET or GET
1781  * @data: pointer to the data to send with the request, request specific
1782  * @len: length of the data, in bytes
1783  * @reply: point to the buffer to hold data returned for a reply
1784  * @reply_len: length of the reply buffer returned from GET
1785  *
1786  * Returns zero or a negative error code.
1787  */
1788 static int dspio_scp(struct hda_codec *codec,
1789 		int mod_id, int src_id, int req, int dir, const void *data,
1790 		unsigned int len, void *reply, unsigned int *reply_len)
1791 {
1792 	int status = 0;
1793 	struct scp_msg scp_send, scp_reply;
1794 	unsigned int ret_bytes, send_size, ret_size;
1795 	unsigned int send_get_flag, reply_resp_flag, reply_error_flag;
1796 	unsigned int reply_data_size;
1797 
1798 	memset(&scp_send, 0, sizeof(scp_send));
1799 	memset(&scp_reply, 0, sizeof(scp_reply));
1800 
1801 	if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS))
1802 		return -EINVAL;
1803 
1804 	if (dir == SCP_GET && reply == NULL) {
1805 		codec_dbg(codec, "dspio_scp get but has no buffer\n");
1806 		return -EINVAL;
1807 	}
1808 
1809 	if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) {
1810 		codec_dbg(codec, "dspio_scp bad resp buf len parms\n");
1811 		return -EINVAL;
1812 	}
1813 
1814 	scp_send.hdr = make_scp_header(mod_id, src_id, (dir == SCP_GET), req,
1815 				       0, 0, 0, len/sizeof(unsigned int));
1816 	if (data != NULL && len > 0) {
1817 		len = min((unsigned int)(sizeof(scp_send.data)), len);
1818 		memcpy(scp_send.data, data, len);
1819 	}
1820 
1821 	ret_bytes = 0;
1822 	send_size = sizeof(unsigned int) + len;
1823 	status = dspio_send_scp_message(codec, (unsigned char *)&scp_send,
1824 					send_size, (unsigned char *)&scp_reply,
1825 					sizeof(scp_reply), &ret_bytes);
1826 
1827 	if (status < 0) {
1828 		codec_dbg(codec, "dspio_scp: send scp msg failed\n");
1829 		return status;
1830 	}
1831 
1832 	/* extract send and reply headers members */
1833 	extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag,
1834 			   NULL, NULL, NULL, NULL, NULL);
1835 	extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL,
1836 			   &reply_resp_flag, &reply_error_flag,
1837 			   &reply_data_size);
1838 
1839 	if (!send_get_flag)
1840 		return 0;
1841 
1842 	if (reply_resp_flag && !reply_error_flag) {
1843 		ret_size = (ret_bytes - sizeof(scp_reply.hdr))
1844 					/ sizeof(unsigned int);
1845 
1846 		if (*reply_len < ret_size*sizeof(unsigned int)) {
1847 			codec_dbg(codec, "reply too long for buf\n");
1848 			return -EINVAL;
1849 		} else if (ret_size != reply_data_size) {
1850 			codec_dbg(codec, "RetLen and HdrLen .NE.\n");
1851 			return -EINVAL;
1852 		} else if (!reply) {
1853 			codec_dbg(codec, "NULL reply\n");
1854 			return -EINVAL;
1855 		} else {
1856 			*reply_len = ret_size*sizeof(unsigned int);
1857 			memcpy(reply, scp_reply.data, *reply_len);
1858 		}
1859 	} else {
1860 		codec_dbg(codec, "reply ill-formed or errflag set\n");
1861 		return -EIO;
1862 	}
1863 
1864 	return status;
1865 }
1866 
1867 /*
1868  * Set DSP parameters
1869  */
1870 static int dspio_set_param(struct hda_codec *codec, int mod_id,
1871 			int src_id, int req, const void *data, unsigned int len)
1872 {
1873 	return dspio_scp(codec, mod_id, src_id, req, SCP_SET, data, len, NULL,
1874 			NULL);
1875 }
1876 
1877 static int dspio_set_uint_param(struct hda_codec *codec, int mod_id,
1878 			int req, const unsigned int data)
1879 {
1880 	return dspio_set_param(codec, mod_id, 0x20, req, &data,
1881 			sizeof(unsigned int));
1882 }
1883 
1884 static int dspio_set_uint_param_no_source(struct hda_codec *codec, int mod_id,
1885 			int req, const unsigned int data)
1886 {
1887 	return dspio_set_param(codec, mod_id, 0x00, req, &data,
1888 			sizeof(unsigned int));
1889 }
1890 
1891 /*
1892  * Allocate a DSP DMA channel via an SCP message
1893  */
1894 static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan)
1895 {
1896 	int status = 0;
1897 	unsigned int size = sizeof(dma_chan);
1898 
1899 	codec_dbg(codec, "     dspio_alloc_dma_chan() -- begin\n");
1900 	status = dspio_scp(codec, MASTERCONTROL, 0x20,
1901 			MASTERCONTROL_ALLOC_DMA_CHAN, SCP_GET, NULL, 0,
1902 			dma_chan, &size);
1903 
1904 	if (status < 0) {
1905 		codec_dbg(codec, "dspio_alloc_dma_chan: SCP Failed\n");
1906 		return status;
1907 	}
1908 
1909 	if ((*dma_chan + 1) == 0) {
1910 		codec_dbg(codec, "no free dma channels to allocate\n");
1911 		return -EBUSY;
1912 	}
1913 
1914 	codec_dbg(codec, "dspio_alloc_dma_chan: chan=%d\n", *dma_chan);
1915 	codec_dbg(codec, "     dspio_alloc_dma_chan() -- complete\n");
1916 
1917 	return status;
1918 }
1919 
1920 /*
1921  * Free a DSP DMA via an SCP message
1922  */
1923 static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan)
1924 {
1925 	int status = 0;
1926 	unsigned int dummy = 0;
1927 
1928 	codec_dbg(codec, "     dspio_free_dma_chan() -- begin\n");
1929 	codec_dbg(codec, "dspio_free_dma_chan: chan=%d\n", dma_chan);
1930 
1931 	status = dspio_scp(codec, MASTERCONTROL, 0x20,
1932 			MASTERCONTROL_ALLOC_DMA_CHAN, SCP_SET, &dma_chan,
1933 			sizeof(dma_chan), NULL, &dummy);
1934 
1935 	if (status < 0) {
1936 		codec_dbg(codec, "dspio_free_dma_chan: SCP Failed\n");
1937 		return status;
1938 	}
1939 
1940 	codec_dbg(codec, "     dspio_free_dma_chan() -- complete\n");
1941 
1942 	return status;
1943 }
1944 
1945 /*
1946  * (Re)start the DSP
1947  */
1948 static int dsp_set_run_state(struct hda_codec *codec)
1949 {
1950 	unsigned int dbg_ctrl_reg;
1951 	unsigned int halt_state;
1952 	int err;
1953 
1954 	err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg);
1955 	if (err < 0)
1956 		return err;
1957 
1958 	halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >>
1959 		      DSP_DBGCNTL_STATE_LOBIT;
1960 
1961 	if (halt_state != 0) {
1962 		dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) &
1963 				  DSP_DBGCNTL_SS_MASK);
1964 		err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
1965 				   dbg_ctrl_reg);
1966 		if (err < 0)
1967 			return err;
1968 
1969 		dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) &
1970 				DSP_DBGCNTL_EXEC_MASK;
1971 		err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
1972 				   dbg_ctrl_reg);
1973 		if (err < 0)
1974 			return err;
1975 	}
1976 
1977 	return 0;
1978 }
1979 
1980 /*
1981  * Reset the DSP
1982  */
1983 static int dsp_reset(struct hda_codec *codec)
1984 {
1985 	unsigned int res;
1986 	int retry = 20;
1987 
1988 	codec_dbg(codec, "dsp_reset\n");
1989 	do {
1990 		res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0);
1991 		retry--;
1992 	} while (res == -EIO && retry);
1993 
1994 	if (!retry) {
1995 		codec_dbg(codec, "dsp_reset timeout\n");
1996 		return -EIO;
1997 	}
1998 
1999 	return 0;
2000 }
2001 
2002 /*
2003  * Convert chip address to DSP address
2004  */
2005 static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx,
2006 					bool *code, bool *yram)
2007 {
2008 	*code = *yram = false;
2009 
2010 	if (UC_RANGE(chip_addx, 1)) {
2011 		*code = true;
2012 		return UC_OFF(chip_addx);
2013 	} else if (X_RANGE_ALL(chip_addx, 1)) {
2014 		return X_OFF(chip_addx);
2015 	} else if (Y_RANGE_ALL(chip_addx, 1)) {
2016 		*yram = true;
2017 		return Y_OFF(chip_addx);
2018 	}
2019 
2020 	return INVALID_CHIP_ADDRESS;
2021 }
2022 
2023 /*
2024  * Check if the DSP DMA is active
2025  */
2026 static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan)
2027 {
2028 	unsigned int dma_chnlstart_reg;
2029 
2030 	chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg);
2031 
2032 	return ((dma_chnlstart_reg & (1 <<
2033 			(DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0);
2034 }
2035 
2036 static int dsp_dma_setup_common(struct hda_codec *codec,
2037 				unsigned int chip_addx,
2038 				unsigned int dma_chan,
2039 				unsigned int port_map_mask,
2040 				bool ovly)
2041 {
2042 	int status = 0;
2043 	unsigned int chnl_prop;
2044 	unsigned int dsp_addx;
2045 	unsigned int active;
2046 	bool code, yram;
2047 
2048 	codec_dbg(codec, "-- dsp_dma_setup_common() -- Begin ---------\n");
2049 
2050 	if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT) {
2051 		codec_dbg(codec, "dma chan num invalid\n");
2052 		return -EINVAL;
2053 	}
2054 
2055 	if (dsp_is_dma_active(codec, dma_chan)) {
2056 		codec_dbg(codec, "dma already active\n");
2057 		return -EBUSY;
2058 	}
2059 
2060 	dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
2061 
2062 	if (dsp_addx == INVALID_CHIP_ADDRESS) {
2063 		codec_dbg(codec, "invalid chip addr\n");
2064 		return -ENXIO;
2065 	}
2066 
2067 	chnl_prop = DSPDMAC_CHNLPROP_AC_MASK;
2068 	active = 0;
2069 
2070 	codec_dbg(codec, "   dsp_dma_setup_common()    start reg pgm\n");
2071 
2072 	if (ovly) {
2073 		status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET,
2074 				     &chnl_prop);
2075 
2076 		if (status < 0) {
2077 			codec_dbg(codec, "read CHNLPROP Reg fail\n");
2078 			return status;
2079 		}
2080 		codec_dbg(codec, "dsp_dma_setup_common() Read CHNLPROP\n");
2081 	}
2082 
2083 	if (!code)
2084 		chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
2085 	else
2086 		chnl_prop |=  (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
2087 
2088 	chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan));
2089 
2090 	status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop);
2091 	if (status < 0) {
2092 		codec_dbg(codec, "write CHNLPROP Reg fail\n");
2093 		return status;
2094 	}
2095 	codec_dbg(codec, "   dsp_dma_setup_common()    Write CHNLPROP\n");
2096 
2097 	if (ovly) {
2098 		status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET,
2099 				     &active);
2100 
2101 		if (status < 0) {
2102 			codec_dbg(codec, "read ACTIVE Reg fail\n");
2103 			return status;
2104 		}
2105 		codec_dbg(codec, "dsp_dma_setup_common() Read ACTIVE\n");
2106 	}
2107 
2108 	active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) &
2109 		DSPDMAC_ACTIVE_AAR_MASK;
2110 
2111 	status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active);
2112 	if (status < 0) {
2113 		codec_dbg(codec, "write ACTIVE Reg fail\n");
2114 		return status;
2115 	}
2116 
2117 	codec_dbg(codec, "   dsp_dma_setup_common()    Write ACTIVE\n");
2118 
2119 	status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan),
2120 			      port_map_mask);
2121 	if (status < 0) {
2122 		codec_dbg(codec, "write AUDCHSEL Reg fail\n");
2123 		return status;
2124 	}
2125 	codec_dbg(codec, "   dsp_dma_setup_common()    Write AUDCHSEL\n");
2126 
2127 	status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan),
2128 			DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK);
2129 	if (status < 0) {
2130 		codec_dbg(codec, "write IRQCNT Reg fail\n");
2131 		return status;
2132 	}
2133 	codec_dbg(codec, "   dsp_dma_setup_common()    Write IRQCNT\n");
2134 
2135 	codec_dbg(codec,
2136 		   "ChipA=0x%x,DspA=0x%x,dmaCh=%u, "
2137 		   "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n",
2138 		   chip_addx, dsp_addx, dma_chan,
2139 		   port_map_mask, chnl_prop, active);
2140 
2141 	codec_dbg(codec, "-- dsp_dma_setup_common() -- Complete ------\n");
2142 
2143 	return 0;
2144 }
2145 
2146 /*
2147  * Setup the DSP DMA per-transfer-specific registers
2148  */
2149 static int dsp_dma_setup(struct hda_codec *codec,
2150 			unsigned int chip_addx,
2151 			unsigned int count,
2152 			unsigned int dma_chan)
2153 {
2154 	int status = 0;
2155 	bool code, yram;
2156 	unsigned int dsp_addx;
2157 	unsigned int addr_field;
2158 	unsigned int incr_field;
2159 	unsigned int base_cnt;
2160 	unsigned int cur_cnt;
2161 	unsigned int dma_cfg = 0;
2162 	unsigned int adr_ofs = 0;
2163 	unsigned int xfr_cnt = 0;
2164 	const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT -
2165 						DSPDMAC_XFRCNT_BCNT_LOBIT + 1);
2166 
2167 	codec_dbg(codec, "-- dsp_dma_setup() -- Begin ---------\n");
2168 
2169 	if (count > max_dma_count) {
2170 		codec_dbg(codec, "count too big\n");
2171 		return -EINVAL;
2172 	}
2173 
2174 	dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
2175 	if (dsp_addx == INVALID_CHIP_ADDRESS) {
2176 		codec_dbg(codec, "invalid chip addr\n");
2177 		return -ENXIO;
2178 	}
2179 
2180 	codec_dbg(codec, "   dsp_dma_setup()    start reg pgm\n");
2181 
2182 	addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT;
2183 	incr_field   = 0;
2184 
2185 	if (!code) {
2186 		addr_field <<= 1;
2187 		if (yram)
2188 			addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT);
2189 
2190 		incr_field  = (1 << DSPDMAC_DMACFG_AINCR_LOBIT);
2191 	}
2192 
2193 	dma_cfg = addr_field + incr_field;
2194 	status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan),
2195 				dma_cfg);
2196 	if (status < 0) {
2197 		codec_dbg(codec, "write DMACFG Reg fail\n");
2198 		return status;
2199 	}
2200 	codec_dbg(codec, "   dsp_dma_setup()    Write DMACFG\n");
2201 
2202 	adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT +
2203 							(code ? 0 : 1));
2204 
2205 	status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan),
2206 				adr_ofs);
2207 	if (status < 0) {
2208 		codec_dbg(codec, "write DSPADROFS Reg fail\n");
2209 		return status;
2210 	}
2211 	codec_dbg(codec, "   dsp_dma_setup()    Write DSPADROFS\n");
2212 
2213 	base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT;
2214 
2215 	cur_cnt  = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT;
2216 
2217 	xfr_cnt = base_cnt | cur_cnt;
2218 
2219 	status = chipio_write(codec,
2220 				DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt);
2221 	if (status < 0) {
2222 		codec_dbg(codec, "write XFRCNT Reg fail\n");
2223 		return status;
2224 	}
2225 	codec_dbg(codec, "   dsp_dma_setup()    Write XFRCNT\n");
2226 
2227 	codec_dbg(codec,
2228 		   "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, "
2229 		   "ADROFS=0x%x, XFRCNT=0x%x\n",
2230 		   chip_addx, count, dma_cfg, adr_ofs, xfr_cnt);
2231 
2232 	codec_dbg(codec, "-- dsp_dma_setup() -- Complete ---------\n");
2233 
2234 	return 0;
2235 }
2236 
2237 /*
2238  * Start the DSP DMA
2239  */
2240 static int dsp_dma_start(struct hda_codec *codec,
2241 			 unsigned int dma_chan, bool ovly)
2242 {
2243 	unsigned int reg = 0;
2244 	int status = 0;
2245 
2246 	codec_dbg(codec, "-- dsp_dma_start() -- Begin ---------\n");
2247 
2248 	if (ovly) {
2249 		status = chipio_read(codec,
2250 				     DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
2251 
2252 		if (status < 0) {
2253 			codec_dbg(codec, "read CHNLSTART reg fail\n");
2254 			return status;
2255 		}
2256 		codec_dbg(codec, "-- dsp_dma_start()    Read CHNLSTART\n");
2257 
2258 		reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
2259 				DSPDMAC_CHNLSTART_DIS_MASK);
2260 	}
2261 
2262 	status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
2263 			reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT)));
2264 	if (status < 0) {
2265 		codec_dbg(codec, "write CHNLSTART reg fail\n");
2266 		return status;
2267 	}
2268 	codec_dbg(codec, "-- dsp_dma_start() -- Complete ---------\n");
2269 
2270 	return status;
2271 }
2272 
2273 /*
2274  * Stop the DSP DMA
2275  */
2276 static int dsp_dma_stop(struct hda_codec *codec,
2277 			unsigned int dma_chan, bool ovly)
2278 {
2279 	unsigned int reg = 0;
2280 	int status = 0;
2281 
2282 	codec_dbg(codec, "-- dsp_dma_stop() -- Begin ---------\n");
2283 
2284 	if (ovly) {
2285 		status = chipio_read(codec,
2286 				     DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
2287 
2288 		if (status < 0) {
2289 			codec_dbg(codec, "read CHNLSTART reg fail\n");
2290 			return status;
2291 		}
2292 		codec_dbg(codec, "-- dsp_dma_stop()    Read CHNLSTART\n");
2293 		reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
2294 				DSPDMAC_CHNLSTART_DIS_MASK);
2295 	}
2296 
2297 	status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
2298 			reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT)));
2299 	if (status < 0) {
2300 		codec_dbg(codec, "write CHNLSTART reg fail\n");
2301 		return status;
2302 	}
2303 	codec_dbg(codec, "-- dsp_dma_stop() -- Complete ---------\n");
2304 
2305 	return status;
2306 }
2307 
2308 /**
2309  * Allocate router ports
2310  *
2311  * @codec: the HDA codec
2312  * @num_chans: number of channels in the stream
2313  * @ports_per_channel: number of ports per channel
2314  * @start_device: start device
2315  * @port_map: pointer to the port list to hold the allocated ports
2316  *
2317  * Returns zero or a negative error code.
2318  */
2319 static int dsp_allocate_router_ports(struct hda_codec *codec,
2320 				     unsigned int num_chans,
2321 				     unsigned int ports_per_channel,
2322 				     unsigned int start_device,
2323 				     unsigned int *port_map)
2324 {
2325 	int status = 0;
2326 	int res;
2327 	u8 val;
2328 
2329 	status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2330 	if (status < 0)
2331 		return status;
2332 
2333 	val = start_device << 6;
2334 	val |= (ports_per_channel - 1) << 4;
2335 	val |= num_chans - 1;
2336 
2337 	snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2338 			    VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET,
2339 			    val);
2340 
2341 	snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2342 			    VENDOR_CHIPIO_PORT_ALLOC_SET,
2343 			    MEM_CONNID_DSP);
2344 
2345 	status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2346 	if (status < 0)
2347 		return status;
2348 
2349 	res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
2350 				VENDOR_CHIPIO_PORT_ALLOC_GET, 0);
2351 
2352 	*port_map = res;
2353 
2354 	return (res < 0) ? res : 0;
2355 }
2356 
2357 /*
2358  * Free router ports
2359  */
2360 static int dsp_free_router_ports(struct hda_codec *codec)
2361 {
2362 	int status = 0;
2363 
2364 	status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2365 	if (status < 0)
2366 		return status;
2367 
2368 	snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2369 			    VENDOR_CHIPIO_PORT_FREE_SET,
2370 			    MEM_CONNID_DSP);
2371 
2372 	status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2373 
2374 	return status;
2375 }
2376 
2377 /*
2378  * Allocate DSP ports for the download stream
2379  */
2380 static int dsp_allocate_ports(struct hda_codec *codec,
2381 			unsigned int num_chans,
2382 			unsigned int rate_multi, unsigned int *port_map)
2383 {
2384 	int status;
2385 
2386 	codec_dbg(codec, "     dsp_allocate_ports() -- begin\n");
2387 
2388 	if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
2389 		codec_dbg(codec, "bad rate multiple\n");
2390 		return -EINVAL;
2391 	}
2392 
2393 	status = dsp_allocate_router_ports(codec, num_chans,
2394 					   rate_multi, 0, port_map);
2395 
2396 	codec_dbg(codec, "     dsp_allocate_ports() -- complete\n");
2397 
2398 	return status;
2399 }
2400 
2401 static int dsp_allocate_ports_format(struct hda_codec *codec,
2402 			const unsigned short fmt,
2403 			unsigned int *port_map)
2404 {
2405 	int status;
2406 	unsigned int num_chans;
2407 
2408 	unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1;
2409 	unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1;
2410 	unsigned int rate_multi = sample_rate_mul / sample_rate_div;
2411 
2412 	if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
2413 		codec_dbg(codec, "bad rate multiple\n");
2414 		return -EINVAL;
2415 	}
2416 
2417 	num_chans = get_hdafmt_chs(fmt) + 1;
2418 
2419 	status = dsp_allocate_ports(codec, num_chans, rate_multi, port_map);
2420 
2421 	return status;
2422 }
2423 
2424 /*
2425  * free DSP ports
2426  */
2427 static int dsp_free_ports(struct hda_codec *codec)
2428 {
2429 	int status;
2430 
2431 	codec_dbg(codec, "     dsp_free_ports() -- begin\n");
2432 
2433 	status = dsp_free_router_ports(codec);
2434 	if (status < 0) {
2435 		codec_dbg(codec, "free router ports fail\n");
2436 		return status;
2437 	}
2438 	codec_dbg(codec, "     dsp_free_ports() -- complete\n");
2439 
2440 	return status;
2441 }
2442 
2443 /*
2444  *  HDA DMA engine stuffs for DSP code download
2445  */
2446 struct dma_engine {
2447 	struct hda_codec *codec;
2448 	unsigned short m_converter_format;
2449 	struct snd_dma_buffer *dmab;
2450 	unsigned int buf_size;
2451 };
2452 
2453 
2454 enum dma_state {
2455 	DMA_STATE_STOP  = 0,
2456 	DMA_STATE_RUN   = 1
2457 };
2458 
2459 static int dma_convert_to_hda_format(struct hda_codec *codec,
2460 		unsigned int sample_rate,
2461 		unsigned short channels,
2462 		unsigned short *hda_format)
2463 {
2464 	unsigned int format_val;
2465 
2466 	format_val = snd_hdac_calc_stream_format(sample_rate,
2467 				channels, SNDRV_PCM_FORMAT_S32_LE, 32, 0);
2468 
2469 	if (hda_format)
2470 		*hda_format = (unsigned short)format_val;
2471 
2472 	return 0;
2473 }
2474 
2475 /*
2476  *  Reset DMA for DSP download
2477  */
2478 static int dma_reset(struct dma_engine *dma)
2479 {
2480 	struct hda_codec *codec = dma->codec;
2481 	struct ca0132_spec *spec = codec->spec;
2482 	int status;
2483 
2484 	if (dma->dmab->area)
2485 		snd_hda_codec_load_dsp_cleanup(codec, dma->dmab);
2486 
2487 	status = snd_hda_codec_load_dsp_prepare(codec,
2488 			dma->m_converter_format,
2489 			dma->buf_size,
2490 			dma->dmab);
2491 	if (status < 0)
2492 		return status;
2493 	spec->dsp_stream_id = status;
2494 	return 0;
2495 }
2496 
2497 static int dma_set_state(struct dma_engine *dma, enum dma_state state)
2498 {
2499 	bool cmd;
2500 
2501 	switch (state) {
2502 	case DMA_STATE_STOP:
2503 		cmd = false;
2504 		break;
2505 	case DMA_STATE_RUN:
2506 		cmd = true;
2507 		break;
2508 	default:
2509 		return 0;
2510 	}
2511 
2512 	snd_hda_codec_load_dsp_trigger(dma->codec, cmd);
2513 	return 0;
2514 }
2515 
2516 static unsigned int dma_get_buffer_size(struct dma_engine *dma)
2517 {
2518 	return dma->dmab->bytes;
2519 }
2520 
2521 static unsigned char *dma_get_buffer_addr(struct dma_engine *dma)
2522 {
2523 	return dma->dmab->area;
2524 }
2525 
2526 static int dma_xfer(struct dma_engine *dma,
2527 		const unsigned int *data,
2528 		unsigned int count)
2529 {
2530 	memcpy(dma->dmab->area, data, count);
2531 	return 0;
2532 }
2533 
2534 static void dma_get_converter_format(
2535 		struct dma_engine *dma,
2536 		unsigned short *format)
2537 {
2538 	if (format)
2539 		*format = dma->m_converter_format;
2540 }
2541 
2542 static unsigned int dma_get_stream_id(struct dma_engine *dma)
2543 {
2544 	struct ca0132_spec *spec = dma->codec->spec;
2545 
2546 	return spec->dsp_stream_id;
2547 }
2548 
2549 struct dsp_image_seg {
2550 	u32 magic;
2551 	u32 chip_addr;
2552 	u32 count;
2553 	u32 data[0];
2554 };
2555 
2556 static const u32 g_magic_value = 0x4c46584d;
2557 static const u32 g_chip_addr_magic_value = 0xFFFFFF01;
2558 
2559 static bool is_valid(const struct dsp_image_seg *p)
2560 {
2561 	return p->magic == g_magic_value;
2562 }
2563 
2564 static bool is_hci_prog_list_seg(const struct dsp_image_seg *p)
2565 {
2566 	return g_chip_addr_magic_value == p->chip_addr;
2567 }
2568 
2569 static bool is_last(const struct dsp_image_seg *p)
2570 {
2571 	return p->count == 0;
2572 }
2573 
2574 static size_t dsp_sizeof(const struct dsp_image_seg *p)
2575 {
2576 	return sizeof(*p) + p->count*sizeof(u32);
2577 }
2578 
2579 static const struct dsp_image_seg *get_next_seg_ptr(
2580 				const struct dsp_image_seg *p)
2581 {
2582 	return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p));
2583 }
2584 
2585 /*
2586  * CA0132 chip DSP transfer stuffs.  For DSP download.
2587  */
2588 #define INVALID_DMA_CHANNEL (~0U)
2589 
2590 /*
2591  * Program a list of address/data pairs via the ChipIO widget.
2592  * The segment data is in the format of successive pairs of words.
2593  * These are repeated as indicated by the segment's count field.
2594  */
2595 static int dspxfr_hci_write(struct hda_codec *codec,
2596 			const struct dsp_image_seg *fls)
2597 {
2598 	int status;
2599 	const u32 *data;
2600 	unsigned int count;
2601 
2602 	if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) {
2603 		codec_dbg(codec, "hci_write invalid params\n");
2604 		return -EINVAL;
2605 	}
2606 
2607 	count = fls->count;
2608 	data = (u32 *)(fls->data);
2609 	while (count >= 2) {
2610 		status = chipio_write(codec, data[0], data[1]);
2611 		if (status < 0) {
2612 			codec_dbg(codec, "hci_write chipio failed\n");
2613 			return status;
2614 		}
2615 		count -= 2;
2616 		data  += 2;
2617 	}
2618 	return 0;
2619 }
2620 
2621 /**
2622  * Write a block of data into DSP code or data RAM using pre-allocated
2623  * DMA engine.
2624  *
2625  * @codec: the HDA codec
2626  * @fls: pointer to a fast load image
2627  * @reloc: Relocation address for loading single-segment overlays, or 0 for
2628  *	   no relocation
2629  * @dma_engine: pointer to DMA engine to be used for DSP download
2630  * @dma_chan: The number of DMA channels used for DSP download
2631  * @port_map_mask: port mapping
2632  * @ovly: TRUE if overlay format is required
2633  *
2634  * Returns zero or a negative error code.
2635  */
2636 static int dspxfr_one_seg(struct hda_codec *codec,
2637 			const struct dsp_image_seg *fls,
2638 			unsigned int reloc,
2639 			struct dma_engine *dma_engine,
2640 			unsigned int dma_chan,
2641 			unsigned int port_map_mask,
2642 			bool ovly)
2643 {
2644 	int status = 0;
2645 	bool comm_dma_setup_done = false;
2646 	const unsigned int *data;
2647 	unsigned int chip_addx;
2648 	unsigned int words_to_write;
2649 	unsigned int buffer_size_words;
2650 	unsigned char *buffer_addx;
2651 	unsigned short hda_format;
2652 	unsigned int sample_rate_div;
2653 	unsigned int sample_rate_mul;
2654 	unsigned int num_chans;
2655 	unsigned int hda_frame_size_words;
2656 	unsigned int remainder_words;
2657 	const u32 *data_remainder;
2658 	u32 chip_addx_remainder;
2659 	unsigned int run_size_words;
2660 	const struct dsp_image_seg *hci_write = NULL;
2661 	unsigned long timeout;
2662 	bool dma_active;
2663 
2664 	if (fls == NULL)
2665 		return -EINVAL;
2666 	if (is_hci_prog_list_seg(fls)) {
2667 		hci_write = fls;
2668 		fls = get_next_seg_ptr(fls);
2669 	}
2670 
2671 	if (hci_write && (!fls || is_last(fls))) {
2672 		codec_dbg(codec, "hci_write\n");
2673 		return dspxfr_hci_write(codec, hci_write);
2674 	}
2675 
2676 	if (fls == NULL || dma_engine == NULL || port_map_mask == 0) {
2677 		codec_dbg(codec, "Invalid Params\n");
2678 		return -EINVAL;
2679 	}
2680 
2681 	data = fls->data;
2682 	chip_addx = fls->chip_addr,
2683 	words_to_write = fls->count;
2684 
2685 	if (!words_to_write)
2686 		return hci_write ? dspxfr_hci_write(codec, hci_write) : 0;
2687 	if (reloc)
2688 		chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2);
2689 
2690 	if (!UC_RANGE(chip_addx, words_to_write) &&
2691 	    !X_RANGE_ALL(chip_addx, words_to_write) &&
2692 	    !Y_RANGE_ALL(chip_addx, words_to_write)) {
2693 		codec_dbg(codec, "Invalid chip_addx Params\n");
2694 		return -EINVAL;
2695 	}
2696 
2697 	buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) /
2698 					sizeof(u32);
2699 
2700 	buffer_addx = dma_get_buffer_addr(dma_engine);
2701 
2702 	if (buffer_addx == NULL) {
2703 		codec_dbg(codec, "dma_engine buffer NULL\n");
2704 		return -EINVAL;
2705 	}
2706 
2707 	dma_get_converter_format(dma_engine, &hda_format);
2708 	sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1;
2709 	sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1;
2710 	num_chans = get_hdafmt_chs(hda_format) + 1;
2711 
2712 	hda_frame_size_words = ((sample_rate_div == 0) ? 0 :
2713 			(num_chans * sample_rate_mul / sample_rate_div));
2714 
2715 	if (hda_frame_size_words == 0) {
2716 		codec_dbg(codec, "frmsz zero\n");
2717 		return -EINVAL;
2718 	}
2719 
2720 	buffer_size_words = min(buffer_size_words,
2721 				(unsigned int)(UC_RANGE(chip_addx, 1) ?
2722 				65536 : 32768));
2723 	buffer_size_words -= buffer_size_words % hda_frame_size_words;
2724 	codec_dbg(codec,
2725 		   "chpadr=0x%08x frmsz=%u nchan=%u "
2726 		   "rate_mul=%u div=%u bufsz=%u\n",
2727 		   chip_addx, hda_frame_size_words, num_chans,
2728 		   sample_rate_mul, sample_rate_div, buffer_size_words);
2729 
2730 	if (buffer_size_words < hda_frame_size_words) {
2731 		codec_dbg(codec, "dspxfr_one_seg:failed\n");
2732 		return -EINVAL;
2733 	}
2734 
2735 	remainder_words = words_to_write % hda_frame_size_words;
2736 	data_remainder = data;
2737 	chip_addx_remainder = chip_addx;
2738 
2739 	data += remainder_words;
2740 	chip_addx += remainder_words*sizeof(u32);
2741 	words_to_write -= remainder_words;
2742 
2743 	while (words_to_write != 0) {
2744 		run_size_words = min(buffer_size_words, words_to_write);
2745 		codec_dbg(codec, "dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n",
2746 			    words_to_write, run_size_words, remainder_words);
2747 		dma_xfer(dma_engine, data, run_size_words*sizeof(u32));
2748 		if (!comm_dma_setup_done) {
2749 			status = dsp_dma_stop(codec, dma_chan, ovly);
2750 			if (status < 0)
2751 				return status;
2752 			status = dsp_dma_setup_common(codec, chip_addx,
2753 						dma_chan, port_map_mask, ovly);
2754 			if (status < 0)
2755 				return status;
2756 			comm_dma_setup_done = true;
2757 		}
2758 
2759 		status = dsp_dma_setup(codec, chip_addx,
2760 						run_size_words, dma_chan);
2761 		if (status < 0)
2762 			return status;
2763 		status = dsp_dma_start(codec, dma_chan, ovly);
2764 		if (status < 0)
2765 			return status;
2766 		if (!dsp_is_dma_active(codec, dma_chan)) {
2767 			codec_dbg(codec, "dspxfr:DMA did not start\n");
2768 			return -EIO;
2769 		}
2770 		status = dma_set_state(dma_engine, DMA_STATE_RUN);
2771 		if (status < 0)
2772 			return status;
2773 		if (remainder_words != 0) {
2774 			status = chipio_write_multiple(codec,
2775 						chip_addx_remainder,
2776 						data_remainder,
2777 						remainder_words);
2778 			if (status < 0)
2779 				return status;
2780 			remainder_words = 0;
2781 		}
2782 		if (hci_write) {
2783 			status = dspxfr_hci_write(codec, hci_write);
2784 			if (status < 0)
2785 				return status;
2786 			hci_write = NULL;
2787 		}
2788 
2789 		timeout = jiffies + msecs_to_jiffies(2000);
2790 		do {
2791 			dma_active = dsp_is_dma_active(codec, dma_chan);
2792 			if (!dma_active)
2793 				break;
2794 			msleep(20);
2795 		} while (time_before(jiffies, timeout));
2796 		if (dma_active)
2797 			break;
2798 
2799 		codec_dbg(codec, "+++++ DMA complete\n");
2800 		dma_set_state(dma_engine, DMA_STATE_STOP);
2801 		status = dma_reset(dma_engine);
2802 
2803 		if (status < 0)
2804 			return status;
2805 
2806 		data += run_size_words;
2807 		chip_addx += run_size_words*sizeof(u32);
2808 		words_to_write -= run_size_words;
2809 	}
2810 
2811 	if (remainder_words != 0) {
2812 		status = chipio_write_multiple(codec, chip_addx_remainder,
2813 					data_remainder, remainder_words);
2814 	}
2815 
2816 	return status;
2817 }
2818 
2819 /**
2820  * Write the entire DSP image of a DSP code/data overlay to DSP memories
2821  *
2822  * @codec: the HDA codec
2823  * @fls_data: pointer to a fast load image
2824  * @reloc: Relocation address for loading single-segment overlays, or 0 for
2825  *	   no relocation
2826  * @sample_rate: sampling rate of the stream used for DSP download
2827  * @channels: channels of the stream used for DSP download
2828  * @ovly: TRUE if overlay format is required
2829  *
2830  * Returns zero or a negative error code.
2831  */
2832 static int dspxfr_image(struct hda_codec *codec,
2833 			const struct dsp_image_seg *fls_data,
2834 			unsigned int reloc,
2835 			unsigned int sample_rate,
2836 			unsigned short channels,
2837 			bool ovly)
2838 {
2839 	struct ca0132_spec *spec = codec->spec;
2840 	int status;
2841 	unsigned short hda_format = 0;
2842 	unsigned int response;
2843 	unsigned char stream_id = 0;
2844 	struct dma_engine *dma_engine;
2845 	unsigned int dma_chan;
2846 	unsigned int port_map_mask;
2847 
2848 	if (fls_data == NULL)
2849 		return -EINVAL;
2850 
2851 	dma_engine = kzalloc(sizeof(*dma_engine), GFP_KERNEL);
2852 	if (!dma_engine)
2853 		return -ENOMEM;
2854 
2855 	dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL);
2856 	if (!dma_engine->dmab) {
2857 		kfree(dma_engine);
2858 		return -ENOMEM;
2859 	}
2860 
2861 	dma_engine->codec = codec;
2862 	dma_convert_to_hda_format(codec, sample_rate, channels, &hda_format);
2863 	dma_engine->m_converter_format = hda_format;
2864 	dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY :
2865 			DSP_DMA_WRITE_BUFLEN_INIT) * 2;
2866 
2867 	dma_chan = ovly ? INVALID_DMA_CHANNEL : 0;
2868 
2869 	status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL,
2870 					hda_format, &response);
2871 
2872 	if (status < 0) {
2873 		codec_dbg(codec, "set converter format fail\n");
2874 		goto exit;
2875 	}
2876 
2877 	status = snd_hda_codec_load_dsp_prepare(codec,
2878 				dma_engine->m_converter_format,
2879 				dma_engine->buf_size,
2880 				dma_engine->dmab);
2881 	if (status < 0)
2882 		goto exit;
2883 	spec->dsp_stream_id = status;
2884 
2885 	if (ovly) {
2886 		status = dspio_alloc_dma_chan(codec, &dma_chan);
2887 		if (status < 0) {
2888 			codec_dbg(codec, "alloc dmachan fail\n");
2889 			dma_chan = INVALID_DMA_CHANNEL;
2890 			goto exit;
2891 		}
2892 	}
2893 
2894 	port_map_mask = 0;
2895 	status = dsp_allocate_ports_format(codec, hda_format,
2896 					&port_map_mask);
2897 	if (status < 0) {
2898 		codec_dbg(codec, "alloc ports fail\n");
2899 		goto exit;
2900 	}
2901 
2902 	stream_id = dma_get_stream_id(dma_engine);
2903 	status = codec_set_converter_stream_channel(codec,
2904 			WIDGET_CHIP_CTRL, stream_id, 0, &response);
2905 	if (status < 0) {
2906 		codec_dbg(codec, "set stream chan fail\n");
2907 		goto exit;
2908 	}
2909 
2910 	while ((fls_data != NULL) && !is_last(fls_data)) {
2911 		if (!is_valid(fls_data)) {
2912 			codec_dbg(codec, "FLS check fail\n");
2913 			status = -EINVAL;
2914 			goto exit;
2915 		}
2916 		status = dspxfr_one_seg(codec, fls_data, reloc,
2917 					dma_engine, dma_chan,
2918 					port_map_mask, ovly);
2919 		if (status < 0)
2920 			break;
2921 
2922 		if (is_hci_prog_list_seg(fls_data))
2923 			fls_data = get_next_seg_ptr(fls_data);
2924 
2925 		if ((fls_data != NULL) && !is_last(fls_data))
2926 			fls_data = get_next_seg_ptr(fls_data);
2927 	}
2928 
2929 	if (port_map_mask != 0)
2930 		status = dsp_free_ports(codec);
2931 
2932 	if (status < 0)
2933 		goto exit;
2934 
2935 	status = codec_set_converter_stream_channel(codec,
2936 				WIDGET_CHIP_CTRL, 0, 0, &response);
2937 
2938 exit:
2939 	if (ovly && (dma_chan != INVALID_DMA_CHANNEL))
2940 		dspio_free_dma_chan(codec, dma_chan);
2941 
2942 	if (dma_engine->dmab->area)
2943 		snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab);
2944 	kfree(dma_engine->dmab);
2945 	kfree(dma_engine);
2946 
2947 	return status;
2948 }
2949 
2950 /*
2951  * CA0132 DSP download stuffs.
2952  */
2953 static void dspload_post_setup(struct hda_codec *codec)
2954 {
2955 	struct ca0132_spec *spec = codec->spec;
2956 	codec_dbg(codec, "---- dspload_post_setup ------\n");
2957 	if (!spec->use_alt_functions) {
2958 		/*set DSP speaker to 2.0 configuration*/
2959 		chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080);
2960 		chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000);
2961 
2962 		/*update write pointer*/
2963 		chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002);
2964 	}
2965 }
2966 
2967 /**
2968  * dspload_image - Download DSP from a DSP Image Fast Load structure.
2969  *
2970  * @codec: the HDA codec
2971  * @fls: pointer to a fast load image
2972  * @ovly: TRUE if overlay format is required
2973  * @reloc: Relocation address for loading single-segment overlays, or 0 for
2974  *	   no relocation
2975  * @autostart: TRUE if DSP starts after loading; ignored if ovly is TRUE
2976  * @router_chans: number of audio router channels to be allocated (0 means use
2977  *		  internal defaults; max is 32)
2978  *
2979  * Download DSP from a DSP Image Fast Load structure. This structure is a
2980  * linear, non-constant sized element array of structures, each of which
2981  * contain the count of the data to be loaded, the data itself, and the
2982  * corresponding starting chip address of the starting data location.
2983  * Returns zero or a negative error code.
2984  */
2985 static int dspload_image(struct hda_codec *codec,
2986 			const struct dsp_image_seg *fls,
2987 			bool ovly,
2988 			unsigned int reloc,
2989 			bool autostart,
2990 			int router_chans)
2991 {
2992 	int status = 0;
2993 	unsigned int sample_rate;
2994 	unsigned short channels;
2995 
2996 	codec_dbg(codec, "---- dspload_image begin ------\n");
2997 	if (router_chans == 0) {
2998 		if (!ovly)
2999 			router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS;
3000 		else
3001 			router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS;
3002 	}
3003 
3004 	sample_rate = 48000;
3005 	channels = (unsigned short)router_chans;
3006 
3007 	while (channels > 16) {
3008 		sample_rate *= 2;
3009 		channels /= 2;
3010 	}
3011 
3012 	do {
3013 		codec_dbg(codec, "Ready to program DMA\n");
3014 		if (!ovly)
3015 			status = dsp_reset(codec);
3016 
3017 		if (status < 0)
3018 			break;
3019 
3020 		codec_dbg(codec, "dsp_reset() complete\n");
3021 		status = dspxfr_image(codec, fls, reloc, sample_rate, channels,
3022 				      ovly);
3023 
3024 		if (status < 0)
3025 			break;
3026 
3027 		codec_dbg(codec, "dspxfr_image() complete\n");
3028 		if (autostart && !ovly) {
3029 			dspload_post_setup(codec);
3030 			status = dsp_set_run_state(codec);
3031 		}
3032 
3033 		codec_dbg(codec, "LOAD FINISHED\n");
3034 	} while (0);
3035 
3036 	return status;
3037 }
3038 
3039 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
3040 static bool dspload_is_loaded(struct hda_codec *codec)
3041 {
3042 	unsigned int data = 0;
3043 	int status = 0;
3044 
3045 	status = chipio_read(codec, 0x40004, &data);
3046 	if ((status < 0) || (data != 1))
3047 		return false;
3048 
3049 	return true;
3050 }
3051 #else
3052 #define dspload_is_loaded(codec)	false
3053 #endif
3054 
3055 static bool dspload_wait_loaded(struct hda_codec *codec)
3056 {
3057 	unsigned long timeout = jiffies + msecs_to_jiffies(2000);
3058 
3059 	do {
3060 		if (dspload_is_loaded(codec)) {
3061 			codec_info(codec, "ca0132 DSP downloaded and running\n");
3062 			return true;
3063 		}
3064 		msleep(20);
3065 	} while (time_before(jiffies, timeout));
3066 
3067 	codec_err(codec, "ca0132 failed to download DSP\n");
3068 	return false;
3069 }
3070 
3071 /*
3072  * Setup GPIO for the other variants of Core3D.
3073  */
3074 
3075 /*
3076  * Sets up the GPIO pins so that they are discoverable. If this isn't done,
3077  * the card shows as having no GPIO pins.
3078  */
3079 static void ca0132_gpio_init(struct hda_codec *codec)
3080 {
3081 	struct ca0132_spec *spec = codec->spec;
3082 
3083 	switch (spec->quirk) {
3084 	case QUIRK_SBZ:
3085 		snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
3086 		snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
3087 		snd_hda_codec_write(codec, 0x01, 0, 0x790, 0x23);
3088 		break;
3089 	case QUIRK_R3DI:
3090 		snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
3091 		snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5B);
3092 		break;
3093 	}
3094 
3095 }
3096 
3097 /* Sets the GPIO for audio output. */
3098 static void ca0132_gpio_setup(struct hda_codec *codec)
3099 {
3100 	struct ca0132_spec *spec = codec->spec;
3101 
3102 	switch (spec->quirk) {
3103 	case QUIRK_SBZ:
3104 		snd_hda_codec_write(codec, 0x01, 0,
3105 				AC_VERB_SET_GPIO_DIRECTION, 0x07);
3106 		snd_hda_codec_write(codec, 0x01, 0,
3107 				AC_VERB_SET_GPIO_MASK, 0x07);
3108 		snd_hda_codec_write(codec, 0x01, 0,
3109 				AC_VERB_SET_GPIO_DATA, 0x04);
3110 		snd_hda_codec_write(codec, 0x01, 0,
3111 				AC_VERB_SET_GPIO_DATA, 0x06);
3112 		break;
3113 	case QUIRK_R3DI:
3114 		snd_hda_codec_write(codec, 0x01, 0,
3115 				AC_VERB_SET_GPIO_DIRECTION, 0x1E);
3116 		snd_hda_codec_write(codec, 0x01, 0,
3117 				AC_VERB_SET_GPIO_MASK, 0x1F);
3118 		snd_hda_codec_write(codec, 0x01, 0,
3119 				AC_VERB_SET_GPIO_DATA, 0x0C);
3120 		break;
3121 	}
3122 }
3123 
3124 /*
3125  * GPIO control functions for the Recon3D integrated.
3126  */
3127 
3128 enum r3di_gpio_bit {
3129 	/* Bit 1 - Switch between front/rear mic. 0 = rear, 1 = front */
3130 	R3DI_MIC_SELECT_BIT = 1,
3131 	/* Bit 2 - Switch between headphone/line out. 0 = Headphone, 1 = Line */
3132 	R3DI_OUT_SELECT_BIT = 2,
3133 	/*
3134 	 * I dunno what this actually does, but it stays on until the dsp
3135 	 * is downloaded.
3136 	 */
3137 	R3DI_GPIO_DSP_DOWNLOADING = 3,
3138 	/*
3139 	 * Same as above, no clue what it does, but it comes on after the dsp
3140 	 * is downloaded.
3141 	 */
3142 	R3DI_GPIO_DSP_DOWNLOADED = 4
3143 };
3144 
3145 enum r3di_mic_select {
3146 	/* Set GPIO bit 1 to 0 for rear mic */
3147 	R3DI_REAR_MIC = 0,
3148 	/* Set GPIO bit 1 to 1 for front microphone*/
3149 	R3DI_FRONT_MIC = 1
3150 };
3151 
3152 enum r3di_out_select {
3153 	/* Set GPIO bit 2 to 0 for headphone */
3154 	R3DI_HEADPHONE_OUT = 0,
3155 	/* Set GPIO bit 2 to 1 for speaker */
3156 	R3DI_LINE_OUT = 1
3157 };
3158 enum r3di_dsp_status {
3159 	/* Set GPIO bit 3 to 1 until DSP is downloaded */
3160 	R3DI_DSP_DOWNLOADING = 0,
3161 	/* Set GPIO bit 4 to 1 once DSP is downloaded */
3162 	R3DI_DSP_DOWNLOADED = 1
3163 };
3164 
3165 
3166 static void r3di_gpio_mic_set(struct hda_codec *codec,
3167 		enum r3di_mic_select cur_mic)
3168 {
3169 	unsigned int cur_gpio;
3170 
3171 	/* Get the current GPIO Data setup */
3172 	cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3173 
3174 	switch (cur_mic) {
3175 	case R3DI_REAR_MIC:
3176 		cur_gpio &= ~(1 << R3DI_MIC_SELECT_BIT);
3177 		break;
3178 	case R3DI_FRONT_MIC:
3179 		cur_gpio |= (1 << R3DI_MIC_SELECT_BIT);
3180 		break;
3181 	}
3182 	snd_hda_codec_write(codec, codec->core.afg, 0,
3183 			    AC_VERB_SET_GPIO_DATA, cur_gpio);
3184 }
3185 
3186 static void r3di_gpio_out_set(struct hda_codec *codec,
3187 		enum r3di_out_select cur_out)
3188 {
3189 	unsigned int cur_gpio;
3190 
3191 	/* Get the current GPIO Data setup */
3192 	cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3193 
3194 	switch (cur_out) {
3195 	case R3DI_HEADPHONE_OUT:
3196 		cur_gpio &= ~(1 << R3DI_OUT_SELECT_BIT);
3197 		break;
3198 	case R3DI_LINE_OUT:
3199 		cur_gpio |= (1 << R3DI_OUT_SELECT_BIT);
3200 		break;
3201 	}
3202 	snd_hda_codec_write(codec, codec->core.afg, 0,
3203 			    AC_VERB_SET_GPIO_DATA, cur_gpio);
3204 }
3205 
3206 static void r3di_gpio_dsp_status_set(struct hda_codec *codec,
3207 		enum r3di_dsp_status dsp_status)
3208 {
3209 	unsigned int cur_gpio;
3210 
3211 	/* Get the current GPIO Data setup */
3212 	cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3213 
3214 	switch (dsp_status) {
3215 	case R3DI_DSP_DOWNLOADING:
3216 		cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADING);
3217 		snd_hda_codec_write(codec, codec->core.afg, 0,
3218 				AC_VERB_SET_GPIO_DATA, cur_gpio);
3219 		break;
3220 	case R3DI_DSP_DOWNLOADED:
3221 		/* Set DOWNLOADING bit to 0. */
3222 		cur_gpio &= ~(1 << R3DI_GPIO_DSP_DOWNLOADING);
3223 
3224 		snd_hda_codec_write(codec, codec->core.afg, 0,
3225 				AC_VERB_SET_GPIO_DATA, cur_gpio);
3226 
3227 		cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADED);
3228 		break;
3229 	}
3230 
3231 	snd_hda_codec_write(codec, codec->core.afg, 0,
3232 			    AC_VERB_SET_GPIO_DATA, cur_gpio);
3233 }
3234 
3235 /*
3236  * PCM callbacks
3237  */
3238 static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
3239 			struct hda_codec *codec,
3240 			unsigned int stream_tag,
3241 			unsigned int format,
3242 			struct snd_pcm_substream *substream)
3243 {
3244 	struct ca0132_spec *spec = codec->spec;
3245 
3246 	snd_hda_codec_setup_stream(codec, spec->dacs[0], stream_tag, 0, format);
3247 
3248 	return 0;
3249 }
3250 
3251 static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
3252 			struct hda_codec *codec,
3253 			struct snd_pcm_substream *substream)
3254 {
3255 	struct ca0132_spec *spec = codec->spec;
3256 
3257 	if (spec->dsp_state == DSP_DOWNLOADING)
3258 		return 0;
3259 
3260 	/*If Playback effects are on, allow stream some time to flush
3261 	 *effects tail*/
3262 	if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
3263 		msleep(50);
3264 
3265 	snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
3266 
3267 	return 0;
3268 }
3269 
3270 static unsigned int ca0132_playback_pcm_delay(struct hda_pcm_stream *info,
3271 			struct hda_codec *codec,
3272 			struct snd_pcm_substream *substream)
3273 {
3274 	struct ca0132_spec *spec = codec->spec;
3275 	unsigned int latency = DSP_PLAYBACK_INIT_LATENCY;
3276 	struct snd_pcm_runtime *runtime = substream->runtime;
3277 
3278 	if (spec->dsp_state != DSP_DOWNLOADED)
3279 		return 0;
3280 
3281 	/* Add latency if playback enhancement and either effect is enabled. */
3282 	if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) {
3283 		if ((spec->effects_switch[SURROUND - EFFECT_START_NID]) ||
3284 		    (spec->effects_switch[DIALOG_PLUS - EFFECT_START_NID]))
3285 			latency += DSP_PLAY_ENHANCEMENT_LATENCY;
3286 	}
3287 
3288 	/* Applying Speaker EQ adds latency as well. */
3289 	if (spec->cur_out_type == SPEAKER_OUT)
3290 		latency += DSP_SPEAKER_OUT_LATENCY;
3291 
3292 	return (latency * runtime->rate) / 1000;
3293 }
3294 
3295 /*
3296  * Digital out
3297  */
3298 static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo,
3299 					struct hda_codec *codec,
3300 					struct snd_pcm_substream *substream)
3301 {
3302 	struct ca0132_spec *spec = codec->spec;
3303 	return snd_hda_multi_out_dig_open(codec, &spec->multiout);
3304 }
3305 
3306 static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
3307 			struct hda_codec *codec,
3308 			unsigned int stream_tag,
3309 			unsigned int format,
3310 			struct snd_pcm_substream *substream)
3311 {
3312 	struct ca0132_spec *spec = codec->spec;
3313 	return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
3314 					     stream_tag, format, substream);
3315 }
3316 
3317 static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
3318 			struct hda_codec *codec,
3319 			struct snd_pcm_substream *substream)
3320 {
3321 	struct ca0132_spec *spec = codec->spec;
3322 	return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout);
3323 }
3324 
3325 static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo,
3326 					 struct hda_codec *codec,
3327 					 struct snd_pcm_substream *substream)
3328 {
3329 	struct ca0132_spec *spec = codec->spec;
3330 	return snd_hda_multi_out_dig_close(codec, &spec->multiout);
3331 }
3332 
3333 /*
3334  * Analog capture
3335  */
3336 static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo,
3337 					struct hda_codec *codec,
3338 					unsigned int stream_tag,
3339 					unsigned int format,
3340 					struct snd_pcm_substream *substream)
3341 {
3342 	snd_hda_codec_setup_stream(codec, hinfo->nid,
3343 				   stream_tag, 0, format);
3344 
3345 	return 0;
3346 }
3347 
3348 static int ca0132_capture_pcm_cleanup(struct hda_pcm_stream *hinfo,
3349 			struct hda_codec *codec,
3350 			struct snd_pcm_substream *substream)
3351 {
3352 	struct ca0132_spec *spec = codec->spec;
3353 
3354 	if (spec->dsp_state == DSP_DOWNLOADING)
3355 		return 0;
3356 
3357 	snd_hda_codec_cleanup_stream(codec, hinfo->nid);
3358 	return 0;
3359 }
3360 
3361 static unsigned int ca0132_capture_pcm_delay(struct hda_pcm_stream *info,
3362 			struct hda_codec *codec,
3363 			struct snd_pcm_substream *substream)
3364 {
3365 	struct ca0132_spec *spec = codec->spec;
3366 	unsigned int latency = DSP_CAPTURE_INIT_LATENCY;
3367 	struct snd_pcm_runtime *runtime = substream->runtime;
3368 
3369 	if (spec->dsp_state != DSP_DOWNLOADED)
3370 		return 0;
3371 
3372 	if (spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
3373 		latency += DSP_CRYSTAL_VOICE_LATENCY;
3374 
3375 	return (latency * runtime->rate) / 1000;
3376 }
3377 
3378 /*
3379  * Controls stuffs.
3380  */
3381 
3382 /*
3383  * Mixer controls helpers.
3384  */
3385 #define CA0132_CODEC_VOL_MONO(xname, nid, channel, dir) \
3386 	{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3387 	  .name = xname, \
3388 	  .subdevice = HDA_SUBDEV_AMP_FLAG, \
3389 	  .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
3390 			SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
3391 			SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
3392 	  .info = ca0132_volume_info, \
3393 	  .get = ca0132_volume_get, \
3394 	  .put = ca0132_volume_put, \
3395 	  .tlv = { .c = ca0132_volume_tlv }, \
3396 	  .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
3397 
3398 /*
3399  * Creates a mixer control that uses defaults of HDA_CODEC_VOL except for the
3400  * volume put, which is used for setting the DSP volume. This was done because
3401  * the ca0132 functions were taking too much time and causing lag.
3402  */
3403 #define CA0132_ALT_CODEC_VOL_MONO(xname, nid, channel, dir) \
3404 	{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3405 	  .name = xname, \
3406 	  .subdevice = HDA_SUBDEV_AMP_FLAG, \
3407 	  .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
3408 			SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
3409 			SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
3410 	  .info = snd_hda_mixer_amp_volume_info, \
3411 	  .get = snd_hda_mixer_amp_volume_get, \
3412 	  .put = ca0132_alt_volume_put, \
3413 	  .tlv = { .c = snd_hda_mixer_amp_tlv }, \
3414 	  .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
3415 
3416 #define CA0132_CODEC_MUTE_MONO(xname, nid, channel, dir) \
3417 	{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3418 	  .name = xname, \
3419 	  .subdevice = HDA_SUBDEV_AMP_FLAG, \
3420 	  .info = snd_hda_mixer_amp_switch_info, \
3421 	  .get = ca0132_switch_get, \
3422 	  .put = ca0132_switch_put, \
3423 	  .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
3424 
3425 /* stereo */
3426 #define CA0132_CODEC_VOL(xname, nid, dir) \
3427 	CA0132_CODEC_VOL_MONO(xname, nid, 3, dir)
3428 #define CA0132_ALT_CODEC_VOL(xname, nid, dir) \
3429 	CA0132_ALT_CODEC_VOL_MONO(xname, nid, 3, dir)
3430 #define CA0132_CODEC_MUTE(xname, nid, dir) \
3431 	CA0132_CODEC_MUTE_MONO(xname, nid, 3, dir)
3432 
3433 /* lookup tables */
3434 /*
3435  * Lookup table with decibel values for the DSP. When volume is changed in
3436  * Windows, the DSP is also sent the dB value in floating point. In Windows,
3437  * these values have decimal points, probably because the Windows driver
3438  * actually uses floating point. We can't here, so I made a lookup table of
3439  * values -90 to 9. -90 is the lowest decibel value for both the ADC's and the
3440  * DAC's, and 9 is the maximum.
3441  */
3442 static const unsigned int float_vol_db_lookup[] = {
3443 0xC2B40000, 0xC2B20000, 0xC2B00000, 0xC2AE0000, 0xC2AC0000, 0xC2AA0000,
3444 0xC2A80000, 0xC2A60000, 0xC2A40000, 0xC2A20000, 0xC2A00000, 0xC29E0000,
3445 0xC29C0000, 0xC29A0000, 0xC2980000, 0xC2960000, 0xC2940000, 0xC2920000,
3446 0xC2900000, 0xC28E0000, 0xC28C0000, 0xC28A0000, 0xC2880000, 0xC2860000,
3447 0xC2840000, 0xC2820000, 0xC2800000, 0xC27C0000, 0xC2780000, 0xC2740000,
3448 0xC2700000, 0xC26C0000, 0xC2680000, 0xC2640000, 0xC2600000, 0xC25C0000,
3449 0xC2580000, 0xC2540000, 0xC2500000, 0xC24C0000, 0xC2480000, 0xC2440000,
3450 0xC2400000, 0xC23C0000, 0xC2380000, 0xC2340000, 0xC2300000, 0xC22C0000,
3451 0xC2280000, 0xC2240000, 0xC2200000, 0xC21C0000, 0xC2180000, 0xC2140000,
3452 0xC2100000, 0xC20C0000, 0xC2080000, 0xC2040000, 0xC2000000, 0xC1F80000,
3453 0xC1F00000, 0xC1E80000, 0xC1E00000, 0xC1D80000, 0xC1D00000, 0xC1C80000,
3454 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
3455 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
3456 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
3457 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
3458 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
3459 0x40C00000, 0x40E00000, 0x41000000, 0x41100000
3460 };
3461 
3462 /*
3463  * This table counts from float 0 to 1 in increments of .01, which is
3464  * useful for a few different sliders.
3465  */
3466 static const unsigned int float_zero_to_one_lookup[] = {
3467 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
3468 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
3469 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
3470 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
3471 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
3472 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
3473 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
3474 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
3475 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
3476 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
3477 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
3478 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
3479 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
3480 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
3481 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
3482 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
3483 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
3484 };
3485 
3486 /*
3487  * This table counts from float 10 to 1000, which is the range of the x-bass
3488  * crossover slider in Windows.
3489  */
3490 static const unsigned int float_xbass_xover_lookup[] = {
3491 0x41200000, 0x41A00000, 0x41F00000, 0x42200000, 0x42480000, 0x42700000,
3492 0x428C0000, 0x42A00000, 0x42B40000, 0x42C80000, 0x42DC0000, 0x42F00000,
3493 0x43020000, 0x430C0000, 0x43160000, 0x43200000, 0x432A0000, 0x43340000,
3494 0x433E0000, 0x43480000, 0x43520000, 0x435C0000, 0x43660000, 0x43700000,
3495 0x437A0000, 0x43820000, 0x43870000, 0x438C0000, 0x43910000, 0x43960000,
3496 0x439B0000, 0x43A00000, 0x43A50000, 0x43AA0000, 0x43AF0000, 0x43B40000,
3497 0x43B90000, 0x43BE0000, 0x43C30000, 0x43C80000, 0x43CD0000, 0x43D20000,
3498 0x43D70000, 0x43DC0000, 0x43E10000, 0x43E60000, 0x43EB0000, 0x43F00000,
3499 0x43F50000, 0x43FA0000, 0x43FF0000, 0x44020000, 0x44048000, 0x44070000,
3500 0x44098000, 0x440C0000, 0x440E8000, 0x44110000, 0x44138000, 0x44160000,
3501 0x44188000, 0x441B0000, 0x441D8000, 0x44200000, 0x44228000, 0x44250000,
3502 0x44278000, 0x442A0000, 0x442C8000, 0x442F0000, 0x44318000, 0x44340000,
3503 0x44368000, 0x44390000, 0x443B8000, 0x443E0000, 0x44408000, 0x44430000,
3504 0x44458000, 0x44480000, 0x444A8000, 0x444D0000, 0x444F8000, 0x44520000,
3505 0x44548000, 0x44570000, 0x44598000, 0x445C0000, 0x445E8000, 0x44610000,
3506 0x44638000, 0x44660000, 0x44688000, 0x446B0000, 0x446D8000, 0x44700000,
3507 0x44728000, 0x44750000, 0x44778000, 0x447A0000
3508 };
3509 
3510 /* The following are for tuning of products */
3511 #ifdef ENABLE_TUNING_CONTROLS
3512 
3513 static unsigned int voice_focus_vals_lookup[] = {
3514 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000, 0x41C80000,
3515 0x41D00000, 0x41D80000, 0x41E00000, 0x41E80000, 0x41F00000, 0x41F80000,
3516 0x42000000, 0x42040000, 0x42080000, 0x420C0000, 0x42100000, 0x42140000,
3517 0x42180000, 0x421C0000, 0x42200000, 0x42240000, 0x42280000, 0x422C0000,
3518 0x42300000, 0x42340000, 0x42380000, 0x423C0000, 0x42400000, 0x42440000,
3519 0x42480000, 0x424C0000, 0x42500000, 0x42540000, 0x42580000, 0x425C0000,
3520 0x42600000, 0x42640000, 0x42680000, 0x426C0000, 0x42700000, 0x42740000,
3521 0x42780000, 0x427C0000, 0x42800000, 0x42820000, 0x42840000, 0x42860000,
3522 0x42880000, 0x428A0000, 0x428C0000, 0x428E0000, 0x42900000, 0x42920000,
3523 0x42940000, 0x42960000, 0x42980000, 0x429A0000, 0x429C0000, 0x429E0000,
3524 0x42A00000, 0x42A20000, 0x42A40000, 0x42A60000, 0x42A80000, 0x42AA0000,
3525 0x42AC0000, 0x42AE0000, 0x42B00000, 0x42B20000, 0x42B40000, 0x42B60000,
3526 0x42B80000, 0x42BA0000, 0x42BC0000, 0x42BE0000, 0x42C00000, 0x42C20000,
3527 0x42C40000, 0x42C60000, 0x42C80000, 0x42CA0000, 0x42CC0000, 0x42CE0000,
3528 0x42D00000, 0x42D20000, 0x42D40000, 0x42D60000, 0x42D80000, 0x42DA0000,
3529 0x42DC0000, 0x42DE0000, 0x42E00000, 0x42E20000, 0x42E40000, 0x42E60000,
3530 0x42E80000, 0x42EA0000, 0x42EC0000, 0x42EE0000, 0x42F00000, 0x42F20000,
3531 0x42F40000, 0x42F60000, 0x42F80000, 0x42FA0000, 0x42FC0000, 0x42FE0000,
3532 0x43000000, 0x43010000, 0x43020000, 0x43030000, 0x43040000, 0x43050000,
3533 0x43060000, 0x43070000, 0x43080000, 0x43090000, 0x430A0000, 0x430B0000,
3534 0x430C0000, 0x430D0000, 0x430E0000, 0x430F0000, 0x43100000, 0x43110000,
3535 0x43120000, 0x43130000, 0x43140000, 0x43150000, 0x43160000, 0x43170000,
3536 0x43180000, 0x43190000, 0x431A0000, 0x431B0000, 0x431C0000, 0x431D0000,
3537 0x431E0000, 0x431F0000, 0x43200000, 0x43210000, 0x43220000, 0x43230000,
3538 0x43240000, 0x43250000, 0x43260000, 0x43270000, 0x43280000, 0x43290000,
3539 0x432A0000, 0x432B0000, 0x432C0000, 0x432D0000, 0x432E0000, 0x432F0000,
3540 0x43300000, 0x43310000, 0x43320000, 0x43330000, 0x43340000
3541 };
3542 
3543 static unsigned int mic_svm_vals_lookup[] = {
3544 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
3545 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
3546 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
3547 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
3548 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
3549 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
3550 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
3551 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
3552 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
3553 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
3554 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
3555 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
3556 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
3557 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
3558 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
3559 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
3560 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
3561 };
3562 
3563 static unsigned int equalizer_vals_lookup[] = {
3564 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
3565 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
3566 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
3567 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
3568 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
3569 0x40C00000, 0x40E00000, 0x41000000, 0x41100000, 0x41200000, 0x41300000,
3570 0x41400000, 0x41500000, 0x41600000, 0x41700000, 0x41800000, 0x41880000,
3571 0x41900000, 0x41980000, 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000,
3572 0x41C00000
3573 };
3574 
3575 static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid,
3576 			  unsigned int *lookup, int idx)
3577 {
3578 	int i = 0;
3579 
3580 	for (i = 0; i < TUNING_CTLS_COUNT; i++)
3581 		if (nid == ca0132_tuning_ctls[i].nid)
3582 			break;
3583 
3584 	snd_hda_power_up(codec);
3585 	dspio_set_param(codec, ca0132_tuning_ctls[i].mid, 0x20,
3586 			ca0132_tuning_ctls[i].req,
3587 			&(lookup[idx]), sizeof(unsigned int));
3588 	snd_hda_power_down(codec);
3589 
3590 	return 1;
3591 }
3592 
3593 static int tuning_ctl_get(struct snd_kcontrol *kcontrol,
3594 			  struct snd_ctl_elem_value *ucontrol)
3595 {
3596 	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3597 	struct ca0132_spec *spec = codec->spec;
3598 	hda_nid_t nid = get_amp_nid(kcontrol);
3599 	long *valp = ucontrol->value.integer.value;
3600 	int idx = nid - TUNING_CTL_START_NID;
3601 
3602 	*valp = spec->cur_ctl_vals[idx];
3603 	return 0;
3604 }
3605 
3606 static int voice_focus_ctl_info(struct snd_kcontrol *kcontrol,
3607 			      struct snd_ctl_elem_info *uinfo)
3608 {
3609 	int chs = get_amp_channels(kcontrol);
3610 	uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3611 	uinfo->count = chs == 3 ? 2 : 1;
3612 	uinfo->value.integer.min = 20;
3613 	uinfo->value.integer.max = 180;
3614 	uinfo->value.integer.step = 1;
3615 
3616 	return 0;
3617 }
3618 
3619 static int voice_focus_ctl_put(struct snd_kcontrol *kcontrol,
3620 				struct snd_ctl_elem_value *ucontrol)
3621 {
3622 	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3623 	struct ca0132_spec *spec = codec->spec;
3624 	hda_nid_t nid = get_amp_nid(kcontrol);
3625 	long *valp = ucontrol->value.integer.value;
3626 	int idx;
3627 
3628 	idx = nid - TUNING_CTL_START_NID;
3629 	/* any change? */
3630 	if (spec->cur_ctl_vals[idx] == *valp)
3631 		return 0;
3632 
3633 	spec->cur_ctl_vals[idx] = *valp;
3634 
3635 	idx = *valp - 20;
3636 	tuning_ctl_set(codec, nid, voice_focus_vals_lookup, idx);
3637 
3638 	return 1;
3639 }
3640 
3641 static int mic_svm_ctl_info(struct snd_kcontrol *kcontrol,
3642 			      struct snd_ctl_elem_info *uinfo)
3643 {
3644 	int chs = get_amp_channels(kcontrol);
3645 	uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3646 	uinfo->count = chs == 3 ? 2 : 1;
3647 	uinfo->value.integer.min = 0;
3648 	uinfo->value.integer.max = 100;
3649 	uinfo->value.integer.step = 1;
3650 
3651 	return 0;
3652 }
3653 
3654 static int mic_svm_ctl_put(struct snd_kcontrol *kcontrol,
3655 				struct snd_ctl_elem_value *ucontrol)
3656 {
3657 	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3658 	struct ca0132_spec *spec = codec->spec;
3659 	hda_nid_t nid = get_amp_nid(kcontrol);
3660 	long *valp = ucontrol->value.integer.value;
3661 	int idx;
3662 
3663 	idx = nid - TUNING_CTL_START_NID;
3664 	/* any change? */
3665 	if (spec->cur_ctl_vals[idx] == *valp)
3666 		return 0;
3667 
3668 	spec->cur_ctl_vals[idx] = *valp;
3669 
3670 	idx = *valp;
3671 	tuning_ctl_set(codec, nid, mic_svm_vals_lookup, idx);
3672 
3673 	return 0;
3674 }
3675 
3676 static int equalizer_ctl_info(struct snd_kcontrol *kcontrol,
3677 			      struct snd_ctl_elem_info *uinfo)
3678 {
3679 	int chs = get_amp_channels(kcontrol);
3680 	uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3681 	uinfo->count = chs == 3 ? 2 : 1;
3682 	uinfo->value.integer.min = 0;
3683 	uinfo->value.integer.max = 48;
3684 	uinfo->value.integer.step = 1;
3685 
3686 	return 0;
3687 }
3688 
3689 static int equalizer_ctl_put(struct snd_kcontrol *kcontrol,
3690 				struct snd_ctl_elem_value *ucontrol)
3691 {
3692 	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3693 	struct ca0132_spec *spec = codec->spec;
3694 	hda_nid_t nid = get_amp_nid(kcontrol);
3695 	long *valp = ucontrol->value.integer.value;
3696 	int idx;
3697 
3698 	idx = nid - TUNING_CTL_START_NID;
3699 	/* any change? */
3700 	if (spec->cur_ctl_vals[idx] == *valp)
3701 		return 0;
3702 
3703 	spec->cur_ctl_vals[idx] = *valp;
3704 
3705 	idx = *valp;
3706 	tuning_ctl_set(codec, nid, equalizer_vals_lookup, idx);
3707 
3708 	return 1;
3709 }
3710 
3711 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(voice_focus_db_scale, 2000, 100, 0);
3712 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(eq_db_scale, -2400, 100, 0);
3713 
3714 static int add_tuning_control(struct hda_codec *codec,
3715 				hda_nid_t pnid, hda_nid_t nid,
3716 				const char *name, int dir)
3717 {
3718 	char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
3719 	int type = dir ? HDA_INPUT : HDA_OUTPUT;
3720 	struct snd_kcontrol_new knew =
3721 		HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
3722 
3723 	knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
3724 			SNDRV_CTL_ELEM_ACCESS_TLV_READ;
3725 	knew.tlv.c = 0;
3726 	knew.tlv.p = 0;
3727 	switch (pnid) {
3728 	case VOICE_FOCUS:
3729 		knew.info = voice_focus_ctl_info;
3730 		knew.get = tuning_ctl_get;
3731 		knew.put = voice_focus_ctl_put;
3732 		knew.tlv.p = voice_focus_db_scale;
3733 		break;
3734 	case MIC_SVM:
3735 		knew.info = mic_svm_ctl_info;
3736 		knew.get = tuning_ctl_get;
3737 		knew.put = mic_svm_ctl_put;
3738 		break;
3739 	case EQUALIZER:
3740 		knew.info = equalizer_ctl_info;
3741 		knew.get = tuning_ctl_get;
3742 		knew.put = equalizer_ctl_put;
3743 		knew.tlv.p = eq_db_scale;
3744 		break;
3745 	default:
3746 		return 0;
3747 	}
3748 	knew.private_value =
3749 		HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
3750 	sprintf(namestr, "%s %s Volume", name, dirstr[dir]);
3751 	return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
3752 }
3753 
3754 static int add_tuning_ctls(struct hda_codec *codec)
3755 {
3756 	int i;
3757 	int err;
3758 
3759 	for (i = 0; i < TUNING_CTLS_COUNT; i++) {
3760 		err = add_tuning_control(codec,
3761 					ca0132_tuning_ctls[i].parent_nid,
3762 					ca0132_tuning_ctls[i].nid,
3763 					ca0132_tuning_ctls[i].name,
3764 					ca0132_tuning_ctls[i].direct);
3765 		if (err < 0)
3766 			return err;
3767 	}
3768 
3769 	return 0;
3770 }
3771 
3772 static void ca0132_init_tuning_defaults(struct hda_codec *codec)
3773 {
3774 	struct ca0132_spec *spec = codec->spec;
3775 	int i;
3776 
3777 	/* Wedge Angle defaults to 30.  10 below is 30 - 20.  20 is min. */
3778 	spec->cur_ctl_vals[WEDGE_ANGLE - TUNING_CTL_START_NID] = 10;
3779 	/* SVM level defaults to 0.74. */
3780 	spec->cur_ctl_vals[SVM_LEVEL - TUNING_CTL_START_NID] = 74;
3781 
3782 	/* EQ defaults to 0dB. */
3783 	for (i = 2; i < TUNING_CTLS_COUNT; i++)
3784 		spec->cur_ctl_vals[i] = 24;
3785 }
3786 #endif /*ENABLE_TUNING_CONTROLS*/
3787 
3788 /*
3789  * Select the active output.
3790  * If autodetect is enabled, output will be selected based on jack detection.
3791  * If jack inserted, headphone will be selected, else built-in speakers
3792  * If autodetect is disabled, output will be selected based on selection.
3793  */
3794 static int ca0132_select_out(struct hda_codec *codec)
3795 {
3796 	struct ca0132_spec *spec = codec->spec;
3797 	unsigned int pin_ctl;
3798 	int jack_present;
3799 	int auto_jack;
3800 	unsigned int tmp;
3801 	int err;
3802 
3803 	codec_dbg(codec, "ca0132_select_out\n");
3804 
3805 	snd_hda_power_up_pm(codec);
3806 
3807 	auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
3808 
3809 	if (auto_jack)
3810 		jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp);
3811 	else
3812 		jack_present =
3813 			spec->vnode_lswitch[VNID_HP_SEL - VNODE_START_NID];
3814 
3815 	if (jack_present)
3816 		spec->cur_out_type = HEADPHONE_OUT;
3817 	else
3818 		spec->cur_out_type = SPEAKER_OUT;
3819 
3820 	if (spec->cur_out_type == SPEAKER_OUT) {
3821 		codec_dbg(codec, "ca0132_select_out speaker\n");
3822 		/*speaker out config*/
3823 		tmp = FLOAT_ONE;
3824 		err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
3825 		if (err < 0)
3826 			goto exit;
3827 		/*enable speaker EQ*/
3828 		tmp = FLOAT_ONE;
3829 		err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
3830 		if (err < 0)
3831 			goto exit;
3832 
3833 		/* Setup EAPD */
3834 		snd_hda_codec_write(codec, spec->out_pins[1], 0,
3835 				    VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
3836 		snd_hda_codec_write(codec, spec->out_pins[0], 0,
3837 				    AC_VERB_SET_EAPD_BTLENABLE, 0x00);
3838 		snd_hda_codec_write(codec, spec->out_pins[0], 0,
3839 				    VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
3840 		snd_hda_codec_write(codec, spec->out_pins[0], 0,
3841 				    AC_VERB_SET_EAPD_BTLENABLE, 0x02);
3842 
3843 		/* disable headphone node */
3844 		pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
3845 					AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3846 		snd_hda_set_pin_ctl(codec, spec->out_pins[1],
3847 				    pin_ctl & ~PIN_HP);
3848 		/* enable speaker node */
3849 		pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
3850 				AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3851 		snd_hda_set_pin_ctl(codec, spec->out_pins[0],
3852 				    pin_ctl | PIN_OUT);
3853 	} else {
3854 		codec_dbg(codec, "ca0132_select_out hp\n");
3855 		/*headphone out config*/
3856 		tmp = FLOAT_ZERO;
3857 		err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
3858 		if (err < 0)
3859 			goto exit;
3860 		/*disable speaker EQ*/
3861 		tmp = FLOAT_ZERO;
3862 		err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
3863 		if (err < 0)
3864 			goto exit;
3865 
3866 		/* Setup EAPD */
3867 		snd_hda_codec_write(codec, spec->out_pins[0], 0,
3868 				    VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
3869 		snd_hda_codec_write(codec, spec->out_pins[0], 0,
3870 				    AC_VERB_SET_EAPD_BTLENABLE, 0x00);
3871 		snd_hda_codec_write(codec, spec->out_pins[1], 0,
3872 				    VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
3873 		snd_hda_codec_write(codec, spec->out_pins[0], 0,
3874 				    AC_VERB_SET_EAPD_BTLENABLE, 0x02);
3875 
3876 		/* disable speaker*/
3877 		pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
3878 					AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3879 		snd_hda_set_pin_ctl(codec, spec->out_pins[0],
3880 				    pin_ctl & ~PIN_HP);
3881 		/* enable headphone*/
3882 		pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
3883 					AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3884 		snd_hda_set_pin_ctl(codec, spec->out_pins[1],
3885 				    pin_ctl | PIN_HP);
3886 	}
3887 
3888 exit:
3889 	snd_hda_power_down_pm(codec);
3890 
3891 	return err < 0 ? err : 0;
3892 }
3893 
3894 /*
3895  * This function behaves similarly to the ca0132_select_out funciton above,
3896  * except with a few differences. It adds the ability to select the current
3897  * output with an enumerated control "output source" if the auto detect
3898  * mute switch is set to off. If the auto detect mute switch is enabled, it
3899  * will detect either headphone or lineout(SPEAKER_OUT) from jack detection.
3900  * It also adds the ability to auto-detect the front headphone port. The only
3901  * way to select surround is to disable auto detect, and set Surround with the
3902  * enumerated control.
3903  */
3904 static int ca0132_alt_select_out(struct hda_codec *codec)
3905 {
3906 	struct ca0132_spec *spec = codec->spec;
3907 	unsigned int pin_ctl;
3908 	int jack_present;
3909 	int auto_jack;
3910 	unsigned int i;
3911 	unsigned int tmp;
3912 	int err;
3913 	/* Default Headphone is rear headphone */
3914 	hda_nid_t headphone_nid = spec->out_pins[1];
3915 
3916 	codec_dbg(codec, "%s\n", __func__);
3917 
3918 	snd_hda_power_up_pm(codec);
3919 
3920 	auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
3921 
3922 	/*
3923 	 * If headphone rear or front is plugged in, set to headphone.
3924 	 * If neither is plugged in, set to rear line out. Only if
3925 	 * hp/speaker auto detect is enabled.
3926 	 */
3927 	if (auto_jack) {
3928 		jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp) ||
3929 			   snd_hda_jack_detect(codec, spec->unsol_tag_front_hp);
3930 
3931 		if (jack_present)
3932 			spec->cur_out_type = HEADPHONE_OUT;
3933 		else
3934 			spec->cur_out_type = SPEAKER_OUT;
3935 	} else
3936 		spec->cur_out_type = spec->out_enum_val;
3937 
3938 	/* Begin DSP output switch */
3939 	tmp = FLOAT_ONE;
3940 	err = dspio_set_uint_param(codec, 0x96, 0x3A, tmp);
3941 	if (err < 0)
3942 		goto exit;
3943 
3944 	switch (spec->cur_out_type) {
3945 	case SPEAKER_OUT:
3946 		codec_dbg(codec, "%s speaker\n", __func__);
3947 		/*speaker out config*/
3948 		switch (spec->quirk) {
3949 		case QUIRK_SBZ:
3950 			writew(0x0007, spec->mem_base + 0x320);
3951 			writew(0x0104, spec->mem_base + 0x320);
3952 			writew(0x0101, spec->mem_base + 0x320);
3953 			chipio_set_control_param(codec, 0x0D, 0x18);
3954 			break;
3955 		case QUIRK_R3DI:
3956 			chipio_set_control_param(codec, 0x0D, 0x24);
3957 			r3di_gpio_out_set(codec, R3DI_LINE_OUT);
3958 			break;
3959 		}
3960 
3961 		/* disable headphone node */
3962 		pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
3963 					AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3964 		snd_hda_set_pin_ctl(codec, spec->out_pins[1],
3965 				    pin_ctl & ~PIN_HP);
3966 		/* enable line-out node */
3967 		pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
3968 				AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3969 		snd_hda_set_pin_ctl(codec, spec->out_pins[0],
3970 				    pin_ctl | PIN_OUT);
3971 		/* Enable EAPD */
3972 		snd_hda_codec_write(codec, spec->out_pins[0], 0,
3973 			AC_VERB_SET_EAPD_BTLENABLE, 0x01);
3974 
3975 		/* If PlayEnhancement is enabled, set different source */
3976 		if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
3977 			dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE);
3978 		else
3979 			dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_EIGHT);
3980 		break;
3981 	case HEADPHONE_OUT:
3982 		codec_dbg(codec, "%s hp\n", __func__);
3983 		/* Headphone out config*/
3984 		switch (spec->quirk) {
3985 		case QUIRK_SBZ:
3986 			writew(0x0107, spec->mem_base + 0x320);
3987 			writew(0x0104, spec->mem_base + 0x320);
3988 			writew(0x0001, spec->mem_base + 0x320);
3989 			chipio_set_control_param(codec, 0x0D, 0x12);
3990 			break;
3991 		case QUIRK_R3DI:
3992 			chipio_set_control_param(codec, 0x0D, 0x21);
3993 			r3di_gpio_out_set(codec, R3DI_HEADPHONE_OUT);
3994 			break;
3995 		}
3996 
3997 		snd_hda_codec_write(codec, spec->out_pins[0], 0,
3998 			AC_VERB_SET_EAPD_BTLENABLE, 0x00);
3999 
4000 		/* disable speaker*/
4001 		pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4002 					AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4003 		snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4004 				pin_ctl & ~PIN_HP);
4005 
4006 		/* enable headphone, either front or rear */
4007 
4008 		if (snd_hda_jack_detect(codec, spec->unsol_tag_front_hp))
4009 			headphone_nid = spec->out_pins[2];
4010 		else if (snd_hda_jack_detect(codec, spec->unsol_tag_hp))
4011 			headphone_nid = spec->out_pins[1];
4012 
4013 		pin_ctl = snd_hda_codec_read(codec, headphone_nid, 0,
4014 					AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4015 		snd_hda_set_pin_ctl(codec, headphone_nid,
4016 				    pin_ctl | PIN_HP);
4017 
4018 		if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
4019 			dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE);
4020 		else
4021 			dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ZERO);
4022 		break;
4023 	case SURROUND_OUT:
4024 		codec_dbg(codec, "%s surround\n", __func__);
4025 		/* Surround out config*/
4026 		switch (spec->quirk) {
4027 		case QUIRK_SBZ:
4028 			writew(0x0007, spec->mem_base + 0x320);
4029 			writew(0x0104, spec->mem_base + 0x320);
4030 			writew(0x0101, spec->mem_base + 0x320);
4031 			chipio_set_control_param(codec, 0x0D, 0x18);
4032 			break;
4033 		case QUIRK_R3DI:
4034 			chipio_set_control_param(codec, 0x0D, 0x24);
4035 			r3di_gpio_out_set(codec, R3DI_LINE_OUT);
4036 			break;
4037 		}
4038 		/* enable line out node */
4039 		pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4040 				AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4041 		snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4042 						pin_ctl | PIN_OUT);
4043 		/* Disable headphone out */
4044 		pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4045 					AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4046 		snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4047 				    pin_ctl & ~PIN_HP);
4048 		/* Enable EAPD on line out */
4049 		snd_hda_codec_write(codec, spec->out_pins[0], 0,
4050 			AC_VERB_SET_EAPD_BTLENABLE, 0x01);
4051 		/* enable center/lfe out node */
4052 		pin_ctl = snd_hda_codec_read(codec, spec->out_pins[2], 0,
4053 					AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4054 		snd_hda_set_pin_ctl(codec, spec->out_pins[2],
4055 				    pin_ctl | PIN_OUT);
4056 		/* Now set rear surround node as out. */
4057 		pin_ctl = snd_hda_codec_read(codec, spec->out_pins[3], 0,
4058 					AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4059 		snd_hda_set_pin_ctl(codec, spec->out_pins[3],
4060 				    pin_ctl | PIN_OUT);
4061 
4062 		if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
4063 			dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE);
4064 		else
4065 			dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_EIGHT);
4066 		break;
4067 	}
4068 
4069 	/* run through the output dsp commands for line-out */
4070 	for (i = 0; i < alt_out_presets[spec->cur_out_type].commands; i++) {
4071 		err = dspio_set_uint_param(codec,
4072 		alt_out_presets[spec->cur_out_type].mids[i],
4073 		alt_out_presets[spec->cur_out_type].reqs[i],
4074 		alt_out_presets[spec->cur_out_type].vals[i]);
4075 
4076 		if (err < 0)
4077 			goto exit;
4078 	}
4079 
4080 exit:
4081 	snd_hda_power_down_pm(codec);
4082 
4083 	return err < 0 ? err : 0;
4084 }
4085 
4086 static void ca0132_unsol_hp_delayed(struct work_struct *work)
4087 {
4088 	struct ca0132_spec *spec = container_of(
4089 		to_delayed_work(work), struct ca0132_spec, unsol_hp_work);
4090 	struct hda_jack_tbl *jack;
4091 
4092 	if (spec->use_alt_functions)
4093 		ca0132_alt_select_out(spec->codec);
4094 	else
4095 		ca0132_select_out(spec->codec);
4096 
4097 	jack = snd_hda_jack_tbl_get(spec->codec, spec->unsol_tag_hp);
4098 	if (jack) {
4099 		jack->block_report = 0;
4100 		snd_hda_jack_report_sync(spec->codec);
4101 	}
4102 }
4103 
4104 static void ca0132_set_dmic(struct hda_codec *codec, int enable);
4105 static int ca0132_mic_boost_set(struct hda_codec *codec, long val);
4106 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val);
4107 static void resume_mic1(struct hda_codec *codec, unsigned int oldval);
4108 static int stop_mic1(struct hda_codec *codec);
4109 static int ca0132_cvoice_switch_set(struct hda_codec *codec);
4110 static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val);
4111 
4112 /*
4113  * Select the active VIP source
4114  */
4115 static int ca0132_set_vipsource(struct hda_codec *codec, int val)
4116 {
4117 	struct ca0132_spec *spec = codec->spec;
4118 	unsigned int tmp;
4119 
4120 	if (spec->dsp_state != DSP_DOWNLOADED)
4121 		return 0;
4122 
4123 	/* if CrystalVoice if off, vipsource should be 0 */
4124 	if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
4125 	    (val == 0)) {
4126 		chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
4127 		chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4128 		chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4129 		if (spec->cur_mic_type == DIGITAL_MIC)
4130 			tmp = FLOAT_TWO;
4131 		else
4132 			tmp = FLOAT_ONE;
4133 		dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4134 		tmp = FLOAT_ZERO;
4135 		dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4136 	} else {
4137 		chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
4138 		chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
4139 		if (spec->cur_mic_type == DIGITAL_MIC)
4140 			tmp = FLOAT_TWO;
4141 		else
4142 			tmp = FLOAT_ONE;
4143 		dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4144 		tmp = FLOAT_ONE;
4145 		dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4146 		msleep(20);
4147 		chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
4148 	}
4149 
4150 	return 1;
4151 }
4152 
4153 static int ca0132_alt_set_vipsource(struct hda_codec *codec, int val)
4154 {
4155 	struct ca0132_spec *spec = codec->spec;
4156 	unsigned int tmp;
4157 
4158 	if (spec->dsp_state != DSP_DOWNLOADED)
4159 		return 0;
4160 
4161 	codec_dbg(codec, "%s\n", __func__);
4162 
4163 	chipio_set_stream_control(codec, 0x03, 0);
4164 	chipio_set_stream_control(codec, 0x04, 0);
4165 
4166 	/* if CrystalVoice is off, vipsource should be 0 */
4167 	if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
4168 	    (val == 0) || spec->in_enum_val == REAR_LINE_IN) {
4169 		codec_dbg(codec, "%s: off.", __func__);
4170 		chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
4171 
4172 		tmp = FLOAT_ZERO;
4173 		dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4174 
4175 		chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4176 		chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4177 		if (spec->quirk == QUIRK_R3DI)
4178 			chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4179 
4180 
4181 		if (spec->in_enum_val == REAR_LINE_IN)
4182 			tmp = FLOAT_ZERO;
4183 		else {
4184 			if (spec->quirk == QUIRK_SBZ)
4185 				tmp = FLOAT_THREE;
4186 			else
4187 				tmp = FLOAT_ONE;
4188 		}
4189 
4190 		dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4191 
4192 	} else {
4193 		codec_dbg(codec, "%s: on.", __func__);
4194 		chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
4195 		chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
4196 		if (spec->quirk == QUIRK_R3DI)
4197 			chipio_set_conn_rate(codec, 0x0F, SR_16_000);
4198 
4199 		if (spec->effects_switch[VOICE_FOCUS - EFFECT_START_NID])
4200 			tmp = FLOAT_TWO;
4201 		else
4202 			tmp = FLOAT_ONE;
4203 		dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4204 
4205 		tmp = FLOAT_ONE;
4206 		dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4207 
4208 		msleep(20);
4209 		chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
4210 	}
4211 
4212 	chipio_set_stream_control(codec, 0x03, 1);
4213 	chipio_set_stream_control(codec, 0x04, 1);
4214 
4215 	return 1;
4216 }
4217 
4218 /*
4219  * Select the active microphone.
4220  * If autodetect is enabled, mic will be selected based on jack detection.
4221  * If jack inserted, ext.mic will be selected, else built-in mic
4222  * If autodetect is disabled, mic will be selected based on selection.
4223  */
4224 static int ca0132_select_mic(struct hda_codec *codec)
4225 {
4226 	struct ca0132_spec *spec = codec->spec;
4227 	int jack_present;
4228 	int auto_jack;
4229 
4230 	codec_dbg(codec, "ca0132_select_mic\n");
4231 
4232 	snd_hda_power_up_pm(codec);
4233 
4234 	auto_jack = spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
4235 
4236 	if (auto_jack)
4237 		jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_amic1);
4238 	else
4239 		jack_present =
4240 			spec->vnode_lswitch[VNID_AMIC1_SEL - VNODE_START_NID];
4241 
4242 	if (jack_present)
4243 		spec->cur_mic_type = LINE_MIC_IN;
4244 	else
4245 		spec->cur_mic_type = DIGITAL_MIC;
4246 
4247 	if (spec->cur_mic_type == DIGITAL_MIC) {
4248 		/* enable digital Mic */
4249 		chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_32_000);
4250 		ca0132_set_dmic(codec, 1);
4251 		ca0132_mic_boost_set(codec, 0);
4252 		/* set voice focus */
4253 		ca0132_effects_set(codec, VOICE_FOCUS,
4254 				   spec->effects_switch
4255 				   [VOICE_FOCUS - EFFECT_START_NID]);
4256 	} else {
4257 		/* disable digital Mic */
4258 		chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_96_000);
4259 		ca0132_set_dmic(codec, 0);
4260 		ca0132_mic_boost_set(codec, spec->cur_mic_boost);
4261 		/* disable voice focus */
4262 		ca0132_effects_set(codec, VOICE_FOCUS, 0);
4263 	}
4264 
4265 	snd_hda_power_down_pm(codec);
4266 
4267 	return 0;
4268 }
4269 
4270 /*
4271  * Select the active input.
4272  * Mic detection isn't used, because it's kind of pointless on the SBZ.
4273  * The front mic has no jack-detection, so the only way to switch to it
4274  * is to do it manually in alsamixer.
4275  */
4276 static int ca0132_alt_select_in(struct hda_codec *codec)
4277 {
4278 	struct ca0132_spec *spec = codec->spec;
4279 	unsigned int tmp;
4280 
4281 	codec_dbg(codec, "%s\n", __func__);
4282 
4283 	snd_hda_power_up_pm(codec);
4284 
4285 	chipio_set_stream_control(codec, 0x03, 0);
4286 	chipio_set_stream_control(codec, 0x04, 0);
4287 
4288 	spec->cur_mic_type = spec->in_enum_val;
4289 
4290 	switch (spec->cur_mic_type) {
4291 	case REAR_MIC:
4292 		switch (spec->quirk) {
4293 		case QUIRK_SBZ:
4294 			writew(0x0000, spec->mem_base + 0x320);
4295 			tmp = FLOAT_THREE;
4296 			break;
4297 		case QUIRK_R3DI:
4298 			r3di_gpio_mic_set(codec, R3DI_REAR_MIC);
4299 			tmp = FLOAT_ONE;
4300 			break;
4301 		default:
4302 			tmp = FLOAT_ONE;
4303 			break;
4304 		}
4305 
4306 		chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4307 		chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4308 		if (spec->quirk == QUIRK_R3DI)
4309 			chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4310 
4311 		dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4312 
4313 		chipio_set_stream_control(codec, 0x03, 1);
4314 		chipio_set_stream_control(codec, 0x04, 1);
4315 
4316 		if (spec->quirk == QUIRK_SBZ) {
4317 			chipio_write(codec, 0x18B098, 0x0000000C);
4318 			chipio_write(codec, 0x18B09C, 0x0000000C);
4319 		}
4320 		ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
4321 		break;
4322 	case REAR_LINE_IN:
4323 		ca0132_mic_boost_set(codec, 0);
4324 		switch (spec->quirk) {
4325 		case QUIRK_SBZ:
4326 			writew(0x0000, spec->mem_base + 0x320);
4327 			break;
4328 		case QUIRK_R3DI:
4329 			r3di_gpio_mic_set(codec, R3DI_REAR_MIC);
4330 			break;
4331 		}
4332 
4333 		chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4334 		chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4335 		if (spec->quirk == QUIRK_R3DI)
4336 			chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4337 
4338 		tmp = FLOAT_ZERO;
4339 		dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4340 
4341 		if (spec->quirk == QUIRK_SBZ) {
4342 			chipio_write(codec, 0x18B098, 0x00000000);
4343 			chipio_write(codec, 0x18B09C, 0x00000000);
4344 		}
4345 
4346 		chipio_set_stream_control(codec, 0x03, 1);
4347 		chipio_set_stream_control(codec, 0x04, 1);
4348 		break;
4349 	case FRONT_MIC:
4350 		switch (spec->quirk) {
4351 		case QUIRK_SBZ:
4352 			writew(0x0100, spec->mem_base + 0x320);
4353 			writew(0x0005, spec->mem_base + 0x320);
4354 			tmp = FLOAT_THREE;
4355 			break;
4356 		case QUIRK_R3DI:
4357 			r3di_gpio_mic_set(codec, R3DI_FRONT_MIC);
4358 			tmp = FLOAT_ONE;
4359 			break;
4360 		default:
4361 			tmp = FLOAT_ONE;
4362 			break;
4363 		}
4364 
4365 		chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4366 		chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4367 		if (spec->quirk == QUIRK_R3DI)
4368 			chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4369 
4370 		dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4371 
4372 		chipio_set_stream_control(codec, 0x03, 1);
4373 		chipio_set_stream_control(codec, 0x04, 1);
4374 
4375 		if (spec->quirk == QUIRK_SBZ) {
4376 			chipio_write(codec, 0x18B098, 0x0000000C);
4377 			chipio_write(codec, 0x18B09C, 0x000000CC);
4378 		}
4379 		ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
4380 		break;
4381 	}
4382 	ca0132_cvoice_switch_set(codec);
4383 
4384 	snd_hda_power_down_pm(codec);
4385 	return 0;
4386 
4387 }
4388 
4389 /*
4390  * Check if VNODE settings take effect immediately.
4391  */
4392 static bool ca0132_is_vnode_effective(struct hda_codec *codec,
4393 				     hda_nid_t vnid,
4394 				     hda_nid_t *shared_nid)
4395 {
4396 	struct ca0132_spec *spec = codec->spec;
4397 	hda_nid_t nid;
4398 
4399 	switch (vnid) {
4400 	case VNID_SPK:
4401 		nid = spec->shared_out_nid;
4402 		break;
4403 	case VNID_MIC:
4404 		nid = spec->shared_mic_nid;
4405 		break;
4406 	default:
4407 		return false;
4408 	}
4409 
4410 	if (shared_nid)
4411 		*shared_nid = nid;
4412 
4413 	return true;
4414 }
4415 
4416 /*
4417 * The following functions are control change helpers.
4418 * They return 0 if no changed.  Return 1 if changed.
4419 */
4420 static int ca0132_voicefx_set(struct hda_codec *codec, int enable)
4421 {
4422 	struct ca0132_spec *spec = codec->spec;
4423 	unsigned int tmp;
4424 
4425 	/* based on CrystalVoice state to enable VoiceFX. */
4426 	if (enable) {
4427 		tmp = spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ?
4428 			FLOAT_ONE : FLOAT_ZERO;
4429 	} else {
4430 		tmp = FLOAT_ZERO;
4431 	}
4432 
4433 	dspio_set_uint_param(codec, ca0132_voicefx.mid,
4434 			     ca0132_voicefx.reqs[0], tmp);
4435 
4436 	return 1;
4437 }
4438 
4439 /*
4440  * Set the effects parameters
4441  */
4442 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val)
4443 {
4444 	struct ca0132_spec *spec = codec->spec;
4445 	unsigned int on, tmp;
4446 	int num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
4447 	int err = 0;
4448 	int idx = nid - EFFECT_START_NID;
4449 
4450 	if ((idx < 0) || (idx >= num_fx))
4451 		return 0; /* no changed */
4452 
4453 	/* for out effect, qualify with PE */
4454 	if ((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) {
4455 		/* if PE if off, turn off out effects. */
4456 		if (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
4457 			val = 0;
4458 	}
4459 
4460 	/* for in effect, qualify with CrystalVoice */
4461 	if ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID)) {
4462 		/* if CrystalVoice if off, turn off in effects. */
4463 		if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
4464 			val = 0;
4465 
4466 		/* Voice Focus applies to 2-ch Mic, Digital Mic */
4467 		if ((nid == VOICE_FOCUS) && (spec->cur_mic_type != DIGITAL_MIC))
4468 			val = 0;
4469 
4470 		/* If Voice Focus on SBZ, set to two channel. */
4471 		if ((nid == VOICE_FOCUS) && (spec->quirk == QUIRK_SBZ)
4472 				&& (spec->cur_mic_type != REAR_LINE_IN)) {
4473 			if (spec->effects_switch[CRYSTAL_VOICE -
4474 						 EFFECT_START_NID]) {
4475 
4476 				if (spec->effects_switch[VOICE_FOCUS -
4477 							 EFFECT_START_NID]) {
4478 					tmp = FLOAT_TWO;
4479 					val = 1;
4480 				} else
4481 					tmp = FLOAT_ONE;
4482 
4483 				dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4484 			}
4485 		}
4486 		/*
4487 		 * For SBZ noise reduction, there's an extra command
4488 		 * to module ID 0x47. No clue why.
4489 		 */
4490 		if ((nid == NOISE_REDUCTION) && (spec->quirk == QUIRK_SBZ)
4491 				&& (spec->cur_mic_type != REAR_LINE_IN)) {
4492 			if (spec->effects_switch[CRYSTAL_VOICE -
4493 						 EFFECT_START_NID]) {
4494 				if (spec->effects_switch[NOISE_REDUCTION -
4495 							 EFFECT_START_NID])
4496 					tmp = FLOAT_ONE;
4497 				else
4498 					tmp = FLOAT_ZERO;
4499 			} else
4500 				tmp = FLOAT_ZERO;
4501 
4502 			dspio_set_uint_param(codec, 0x47, 0x00, tmp);
4503 		}
4504 
4505 		/* If rear line in disable effects. */
4506 		if (spec->use_alt_functions &&
4507 				spec->in_enum_val == REAR_LINE_IN)
4508 			val = 0;
4509 	}
4510 
4511 	codec_dbg(codec, "ca0132_effect_set: nid=0x%x, val=%ld\n",
4512 		    nid, val);
4513 
4514 	on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE;
4515 	err = dspio_set_uint_param(codec, ca0132_effects[idx].mid,
4516 				   ca0132_effects[idx].reqs[0], on);
4517 
4518 	if (err < 0)
4519 		return 0; /* no changed */
4520 
4521 	return 1;
4522 }
4523 
4524 /*
4525  * Turn on/off Playback Enhancements
4526  */
4527 static int ca0132_pe_switch_set(struct hda_codec *codec)
4528 {
4529 	struct ca0132_spec *spec = codec->spec;
4530 	hda_nid_t nid;
4531 	int i, ret = 0;
4532 
4533 	codec_dbg(codec, "ca0132_pe_switch_set: val=%ld\n",
4534 		    spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]);
4535 
4536 	if (spec->use_alt_functions)
4537 		ca0132_alt_select_out(codec);
4538 
4539 	i = OUT_EFFECT_START_NID - EFFECT_START_NID;
4540 	nid = OUT_EFFECT_START_NID;
4541 	/* PE affects all out effects */
4542 	for (; nid < OUT_EFFECT_END_NID; nid++, i++)
4543 		ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
4544 
4545 	return ret;
4546 }
4547 
4548 /* Check if Mic1 is streaming, if so, stop streaming */
4549 static int stop_mic1(struct hda_codec *codec)
4550 {
4551 	struct ca0132_spec *spec = codec->spec;
4552 	unsigned int oldval = snd_hda_codec_read(codec, spec->adcs[0], 0,
4553 						 AC_VERB_GET_CONV, 0);
4554 	if (oldval != 0)
4555 		snd_hda_codec_write(codec, spec->adcs[0], 0,
4556 				    AC_VERB_SET_CHANNEL_STREAMID,
4557 				    0);
4558 	return oldval;
4559 }
4560 
4561 /* Resume Mic1 streaming if it was stopped. */
4562 static void resume_mic1(struct hda_codec *codec, unsigned int oldval)
4563 {
4564 	struct ca0132_spec *spec = codec->spec;
4565 	/* Restore the previous stream and channel */
4566 	if (oldval != 0)
4567 		snd_hda_codec_write(codec, spec->adcs[0], 0,
4568 				    AC_VERB_SET_CHANNEL_STREAMID,
4569 				    oldval);
4570 }
4571 
4572 /*
4573  * Turn on/off CrystalVoice
4574  */
4575 static int ca0132_cvoice_switch_set(struct hda_codec *codec)
4576 {
4577 	struct ca0132_spec *spec = codec->spec;
4578 	hda_nid_t nid;
4579 	int i, ret = 0;
4580 	unsigned int oldval;
4581 
4582 	codec_dbg(codec, "ca0132_cvoice_switch_set: val=%ld\n",
4583 		    spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]);
4584 
4585 	i = IN_EFFECT_START_NID - EFFECT_START_NID;
4586 	nid = IN_EFFECT_START_NID;
4587 	/* CrystalVoice affects all in effects */
4588 	for (; nid < IN_EFFECT_END_NID; nid++, i++)
4589 		ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
4590 
4591 	/* including VoiceFX */
4592 	ret |= ca0132_voicefx_set(codec, (spec->voicefx_val ? 1 : 0));
4593 
4594 	/* set correct vipsource */
4595 	oldval = stop_mic1(codec);
4596 	if (spec->use_alt_functions)
4597 		ret |= ca0132_alt_set_vipsource(codec, 1);
4598 	else
4599 		ret |= ca0132_set_vipsource(codec, 1);
4600 	resume_mic1(codec, oldval);
4601 	return ret;
4602 }
4603 
4604 static int ca0132_mic_boost_set(struct hda_codec *codec, long val)
4605 {
4606 	struct ca0132_spec *spec = codec->spec;
4607 	int ret = 0;
4608 
4609 	if (val) /* on */
4610 		ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
4611 					HDA_INPUT, 0, HDA_AMP_VOLMASK, 3);
4612 	else /* off */
4613 		ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
4614 					HDA_INPUT, 0, HDA_AMP_VOLMASK, 0);
4615 
4616 	return ret;
4617 }
4618 
4619 static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val)
4620 {
4621 	struct ca0132_spec *spec = codec->spec;
4622 	int ret = 0;
4623 
4624 	ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
4625 				HDA_INPUT, 0, HDA_AMP_VOLMASK, val);
4626 	return ret;
4627 }
4628 
4629 static int ca0132_vnode_switch_set(struct snd_kcontrol *kcontrol,
4630 				struct snd_ctl_elem_value *ucontrol)
4631 {
4632 	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4633 	hda_nid_t nid = get_amp_nid(kcontrol);
4634 	hda_nid_t shared_nid = 0;
4635 	bool effective;
4636 	int ret = 0;
4637 	struct ca0132_spec *spec = codec->spec;
4638 	int auto_jack;
4639 
4640 	if (nid == VNID_HP_SEL) {
4641 		auto_jack =
4642 			spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
4643 		if (!auto_jack) {
4644 			if (spec->use_alt_functions)
4645 				ca0132_alt_select_out(codec);
4646 			else
4647 				ca0132_select_out(codec);
4648 		}
4649 		return 1;
4650 	}
4651 
4652 	if (nid == VNID_AMIC1_SEL) {
4653 		auto_jack =
4654 			spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
4655 		if (!auto_jack)
4656 			ca0132_select_mic(codec);
4657 		return 1;
4658 	}
4659 
4660 	if (nid == VNID_HP_ASEL) {
4661 		if (spec->use_alt_functions)
4662 			ca0132_alt_select_out(codec);
4663 		else
4664 			ca0132_select_out(codec);
4665 		return 1;
4666 	}
4667 
4668 	if (nid == VNID_AMIC1_ASEL) {
4669 		ca0132_select_mic(codec);
4670 		return 1;
4671 	}
4672 
4673 	/* if effective conditions, then update hw immediately. */
4674 	effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
4675 	if (effective) {
4676 		int dir = get_amp_direction(kcontrol);
4677 		int ch = get_amp_channels(kcontrol);
4678 		unsigned long pval;
4679 
4680 		mutex_lock(&codec->control_mutex);
4681 		pval = kcontrol->private_value;
4682 		kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
4683 								0, dir);
4684 		ret = snd_hda_mixer_amp_switch_put(kcontrol, ucontrol);
4685 		kcontrol->private_value = pval;
4686 		mutex_unlock(&codec->control_mutex);
4687 	}
4688 
4689 	return ret;
4690 }
4691 /* End of control change helpers. */
4692 /*
4693  * Below I've added controls to mess with the effect levels, I've only enabled
4694  * them on the Sound Blaster Z, but they would probably also work on the
4695  * Chromebook. I figured they were probably tuned specifically for it, and left
4696  * out for a reason.
4697  */
4698 
4699 /* Sets DSP effect level from the sliders above the controls */
4700 static int ca0132_alt_slider_ctl_set(struct hda_codec *codec, hda_nid_t nid,
4701 			  const unsigned int *lookup, int idx)
4702 {
4703 	int i = 0;
4704 	unsigned int y;
4705 	/*
4706 	 * For X_BASS, req 2 is actually crossover freq instead of
4707 	 * effect level
4708 	 */
4709 	if (nid == X_BASS)
4710 		y = 2;
4711 	else
4712 		y = 1;
4713 
4714 	snd_hda_power_up(codec);
4715 	if (nid == XBASS_XOVER) {
4716 		for (i = 0; i < OUT_EFFECTS_COUNT; i++)
4717 			if (ca0132_effects[i].nid == X_BASS)
4718 				break;
4719 
4720 		dspio_set_param(codec, ca0132_effects[i].mid, 0x20,
4721 				ca0132_effects[i].reqs[1],
4722 				&(lookup[idx - 1]), sizeof(unsigned int));
4723 	} else {
4724 		/* Find the actual effect structure */
4725 		for (i = 0; i < OUT_EFFECTS_COUNT; i++)
4726 			if (nid == ca0132_effects[i].nid)
4727 				break;
4728 
4729 		dspio_set_param(codec, ca0132_effects[i].mid, 0x20,
4730 				ca0132_effects[i].reqs[y],
4731 				&(lookup[idx]), sizeof(unsigned int));
4732 	}
4733 
4734 	snd_hda_power_down(codec);
4735 
4736 	return 0;
4737 }
4738 
4739 static int ca0132_alt_xbass_xover_slider_ctl_get(struct snd_kcontrol *kcontrol,
4740 			  struct snd_ctl_elem_value *ucontrol)
4741 {
4742 	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4743 	struct ca0132_spec *spec = codec->spec;
4744 	long *valp = ucontrol->value.integer.value;
4745 
4746 	*valp = spec->xbass_xover_freq;
4747 	return 0;
4748 }
4749 
4750 static int ca0132_alt_slider_ctl_get(struct snd_kcontrol *kcontrol,
4751 			  struct snd_ctl_elem_value *ucontrol)
4752 {
4753 	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4754 	struct ca0132_spec *spec = codec->spec;
4755 	hda_nid_t nid = get_amp_nid(kcontrol);
4756 	long *valp = ucontrol->value.integer.value;
4757 	int idx = nid - OUT_EFFECT_START_NID;
4758 
4759 	*valp = spec->fx_ctl_val[idx];
4760 	return 0;
4761 }
4762 
4763 /*
4764  * The X-bass crossover starts at 10hz, so the min is 1. The
4765  * frequency is set in multiples of 10.
4766  */
4767 static int ca0132_alt_xbass_xover_slider_info(struct snd_kcontrol *kcontrol,
4768 		struct snd_ctl_elem_info *uinfo)
4769 {
4770 	uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
4771 	uinfo->count = 1;
4772 	uinfo->value.integer.min = 1;
4773 	uinfo->value.integer.max = 100;
4774 	uinfo->value.integer.step = 1;
4775 
4776 	return 0;
4777 }
4778 
4779 static int ca0132_alt_effect_slider_info(struct snd_kcontrol *kcontrol,
4780 		struct snd_ctl_elem_info *uinfo)
4781 {
4782 	int chs = get_amp_channels(kcontrol);
4783 
4784 	uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
4785 	uinfo->count = chs == 3 ? 2 : 1;
4786 	uinfo->value.integer.min = 0;
4787 	uinfo->value.integer.max = 100;
4788 	uinfo->value.integer.step = 1;
4789 
4790 	return 0;
4791 }
4792 
4793 static int ca0132_alt_xbass_xover_slider_put(struct snd_kcontrol *kcontrol,
4794 				struct snd_ctl_elem_value *ucontrol)
4795 {
4796 	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4797 	struct ca0132_spec *spec = codec->spec;
4798 	hda_nid_t nid = get_amp_nid(kcontrol);
4799 	long *valp = ucontrol->value.integer.value;
4800 	int idx;
4801 
4802 	/* any change? */
4803 	if (spec->xbass_xover_freq == *valp)
4804 		return 0;
4805 
4806 	spec->xbass_xover_freq = *valp;
4807 
4808 	idx = *valp;
4809 	ca0132_alt_slider_ctl_set(codec, nid, float_xbass_xover_lookup, idx);
4810 
4811 	return 0;
4812 }
4813 
4814 static int ca0132_alt_effect_slider_put(struct snd_kcontrol *kcontrol,
4815 				struct snd_ctl_elem_value *ucontrol)
4816 {
4817 	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4818 	struct ca0132_spec *spec = codec->spec;
4819 	hda_nid_t nid = get_amp_nid(kcontrol);
4820 	long *valp = ucontrol->value.integer.value;
4821 	int idx;
4822 
4823 	idx = nid - EFFECT_START_NID;
4824 	/* any change? */
4825 	if (spec->fx_ctl_val[idx] == *valp)
4826 		return 0;
4827 
4828 	spec->fx_ctl_val[idx] = *valp;
4829 
4830 	idx = *valp;
4831 	ca0132_alt_slider_ctl_set(codec, nid, float_zero_to_one_lookup, idx);
4832 
4833 	return 0;
4834 }
4835 
4836 
4837 /*
4838  * Mic Boost Enum for alternative ca0132 codecs. I didn't like that the original
4839  * only has off or full 30 dB, and didn't like making a volume slider that has
4840  * traditional 0-100 in alsamixer that goes in big steps. I like enum better.
4841  */
4842 #define MIC_BOOST_NUM_OF_STEPS 4
4843 #define MIC_BOOST_ENUM_MAX_STRLEN 10
4844 
4845 static int ca0132_alt_mic_boost_info(struct snd_kcontrol *kcontrol,
4846 				 struct snd_ctl_elem_info *uinfo)
4847 {
4848 	char *sfx = "dB";
4849 	char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
4850 
4851 	uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4852 	uinfo->count = 1;
4853 	uinfo->value.enumerated.items = MIC_BOOST_NUM_OF_STEPS;
4854 	if (uinfo->value.enumerated.item >= MIC_BOOST_NUM_OF_STEPS)
4855 		uinfo->value.enumerated.item = MIC_BOOST_NUM_OF_STEPS - 1;
4856 	sprintf(namestr, "%d %s", (uinfo->value.enumerated.item * 10), sfx);
4857 	strcpy(uinfo->value.enumerated.name, namestr);
4858 	return 0;
4859 }
4860 
4861 static int ca0132_alt_mic_boost_get(struct snd_kcontrol *kcontrol,
4862 				struct snd_ctl_elem_value *ucontrol)
4863 {
4864 	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4865 	struct ca0132_spec *spec = codec->spec;
4866 
4867 	ucontrol->value.enumerated.item[0] = spec->mic_boost_enum_val;
4868 	return 0;
4869 }
4870 
4871 static int ca0132_alt_mic_boost_put(struct snd_kcontrol *kcontrol,
4872 				struct snd_ctl_elem_value *ucontrol)
4873 {
4874 	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4875 	struct ca0132_spec *spec = codec->spec;
4876 	int sel = ucontrol->value.enumerated.item[0];
4877 	unsigned int items = MIC_BOOST_NUM_OF_STEPS;
4878 
4879 	if (sel >= items)
4880 		return 0;
4881 
4882 	codec_dbg(codec, "ca0132_alt_mic_boost: boost=%d\n",
4883 		    sel);
4884 
4885 	spec->mic_boost_enum_val = sel;
4886 
4887 	if (spec->in_enum_val != REAR_LINE_IN)
4888 		ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
4889 
4890 	return 1;
4891 }
4892 
4893 
4894 /*
4895  * Input Select Control for alternative ca0132 codecs. This exists because
4896  * front microphone has no auto-detect, and we need a way to set the rear
4897  * as line-in
4898  */
4899 static int ca0132_alt_input_source_info(struct snd_kcontrol *kcontrol,
4900 				 struct snd_ctl_elem_info *uinfo)
4901 {
4902 	uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4903 	uinfo->count = 1;
4904 	uinfo->value.enumerated.items = IN_SRC_NUM_OF_INPUTS;
4905 	if (uinfo->value.enumerated.item >= IN_SRC_NUM_OF_INPUTS)
4906 		uinfo->value.enumerated.item = IN_SRC_NUM_OF_INPUTS - 1;
4907 	strcpy(uinfo->value.enumerated.name,
4908 			in_src_str[uinfo->value.enumerated.item]);
4909 	return 0;
4910 }
4911 
4912 static int ca0132_alt_input_source_get(struct snd_kcontrol *kcontrol,
4913 				struct snd_ctl_elem_value *ucontrol)
4914 {
4915 	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4916 	struct ca0132_spec *spec = codec->spec;
4917 
4918 	ucontrol->value.enumerated.item[0] = spec->in_enum_val;
4919 	return 0;
4920 }
4921 
4922 static int ca0132_alt_input_source_put(struct snd_kcontrol *kcontrol,
4923 				struct snd_ctl_elem_value *ucontrol)
4924 {
4925 	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4926 	struct ca0132_spec *spec = codec->spec;
4927 	int sel = ucontrol->value.enumerated.item[0];
4928 	unsigned int items = IN_SRC_NUM_OF_INPUTS;
4929 
4930 	if (sel >= items)
4931 		return 0;
4932 
4933 	codec_dbg(codec, "ca0132_alt_input_select: sel=%d, preset=%s\n",
4934 		    sel, in_src_str[sel]);
4935 
4936 	spec->in_enum_val = sel;
4937 
4938 	ca0132_alt_select_in(codec);
4939 
4940 	return 1;
4941 }
4942 
4943 /* Sound Blaster Z Output Select Control */
4944 static int ca0132_alt_output_select_get_info(struct snd_kcontrol *kcontrol,
4945 				 struct snd_ctl_elem_info *uinfo)
4946 {
4947 	uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4948 	uinfo->count = 1;
4949 	uinfo->value.enumerated.items = NUM_OF_OUTPUTS;
4950 	if (uinfo->value.enumerated.item >= NUM_OF_OUTPUTS)
4951 		uinfo->value.enumerated.item = NUM_OF_OUTPUTS - 1;
4952 	strcpy(uinfo->value.enumerated.name,
4953 			alt_out_presets[uinfo->value.enumerated.item].name);
4954 	return 0;
4955 }
4956 
4957 static int ca0132_alt_output_select_get(struct snd_kcontrol *kcontrol,
4958 				struct snd_ctl_elem_value *ucontrol)
4959 {
4960 	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4961 	struct ca0132_spec *spec = codec->spec;
4962 
4963 	ucontrol->value.enumerated.item[0] = spec->out_enum_val;
4964 	return 0;
4965 }
4966 
4967 static int ca0132_alt_output_select_put(struct snd_kcontrol *kcontrol,
4968 				struct snd_ctl_elem_value *ucontrol)
4969 {
4970 	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4971 	struct ca0132_spec *spec = codec->spec;
4972 	int sel = ucontrol->value.enumerated.item[0];
4973 	unsigned int items = NUM_OF_OUTPUTS;
4974 	unsigned int auto_jack;
4975 
4976 	if (sel >= items)
4977 		return 0;
4978 
4979 	codec_dbg(codec, "ca0132_alt_output_select: sel=%d, preset=%s\n",
4980 		    sel, alt_out_presets[sel].name);
4981 
4982 	spec->out_enum_val = sel;
4983 
4984 	auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
4985 
4986 	if (!auto_jack)
4987 		ca0132_alt_select_out(codec);
4988 
4989 	return 1;
4990 }
4991 
4992 /*
4993  * Smart Volume output setting control. Three different settings, Normal,
4994  * which takes the value from the smart volume slider. The two others, loud
4995  * and night, disregard the slider value and have uneditable values.
4996  */
4997 #define NUM_OF_SVM_SETTINGS 3
4998 static const char *const out_svm_set_enum_str[3] = {"Normal", "Loud", "Night" };
4999 
5000 static int ca0132_alt_svm_setting_info(struct snd_kcontrol *kcontrol,
5001 				 struct snd_ctl_elem_info *uinfo)
5002 {
5003 	uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5004 	uinfo->count = 1;
5005 	uinfo->value.enumerated.items = NUM_OF_SVM_SETTINGS;
5006 	if (uinfo->value.enumerated.item >= NUM_OF_SVM_SETTINGS)
5007 		uinfo->value.enumerated.item = NUM_OF_SVM_SETTINGS - 1;
5008 	strcpy(uinfo->value.enumerated.name,
5009 			out_svm_set_enum_str[uinfo->value.enumerated.item]);
5010 	return 0;
5011 }
5012 
5013 static int ca0132_alt_svm_setting_get(struct snd_kcontrol *kcontrol,
5014 				struct snd_ctl_elem_value *ucontrol)
5015 {
5016 	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5017 	struct ca0132_spec *spec = codec->spec;
5018 
5019 	ucontrol->value.enumerated.item[0] = spec->smart_volume_setting;
5020 	return 0;
5021 }
5022 
5023 static int ca0132_alt_svm_setting_put(struct snd_kcontrol *kcontrol,
5024 				struct snd_ctl_elem_value *ucontrol)
5025 {
5026 	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5027 	struct ca0132_spec *spec = codec->spec;
5028 	int sel = ucontrol->value.enumerated.item[0];
5029 	unsigned int items = NUM_OF_SVM_SETTINGS;
5030 	unsigned int idx = SMART_VOLUME - EFFECT_START_NID;
5031 	unsigned int tmp;
5032 
5033 	if (sel >= items)
5034 		return 0;
5035 
5036 	codec_dbg(codec, "ca0132_alt_svm_setting: sel=%d, preset=%s\n",
5037 		    sel, out_svm_set_enum_str[sel]);
5038 
5039 	spec->smart_volume_setting = sel;
5040 
5041 	switch (sel) {
5042 	case 0:
5043 		tmp = FLOAT_ZERO;
5044 		break;
5045 	case 1:
5046 		tmp = FLOAT_ONE;
5047 		break;
5048 	case 2:
5049 		tmp = FLOAT_TWO;
5050 		break;
5051 	default:
5052 		tmp = FLOAT_ZERO;
5053 		break;
5054 	}
5055 	/* Req 2 is the Smart Volume Setting req. */
5056 	dspio_set_uint_param(codec, ca0132_effects[idx].mid,
5057 			ca0132_effects[idx].reqs[2], tmp);
5058 	return 1;
5059 }
5060 
5061 /* Sound Blaster Z EQ preset controls */
5062 static int ca0132_alt_eq_preset_info(struct snd_kcontrol *kcontrol,
5063 				 struct snd_ctl_elem_info *uinfo)
5064 {
5065 	unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets);
5066 
5067 	uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5068 	uinfo->count = 1;
5069 	uinfo->value.enumerated.items = items;
5070 	if (uinfo->value.enumerated.item >= items)
5071 		uinfo->value.enumerated.item = items - 1;
5072 	strcpy(uinfo->value.enumerated.name,
5073 		ca0132_alt_eq_presets[uinfo->value.enumerated.item].name);
5074 	return 0;
5075 }
5076 
5077 static int ca0132_alt_eq_preset_get(struct snd_kcontrol *kcontrol,
5078 				struct snd_ctl_elem_value *ucontrol)
5079 {
5080 	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5081 	struct ca0132_spec *spec = codec->spec;
5082 
5083 	ucontrol->value.enumerated.item[0] = spec->eq_preset_val;
5084 	return 0;
5085 }
5086 
5087 static int ca0132_alt_eq_preset_put(struct snd_kcontrol *kcontrol,
5088 				struct snd_ctl_elem_value *ucontrol)
5089 {
5090 	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5091 	struct ca0132_spec *spec = codec->spec;
5092 	int i, err = 0;
5093 	int sel = ucontrol->value.enumerated.item[0];
5094 	unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets);
5095 
5096 	if (sel >= items)
5097 		return 0;
5098 
5099 	codec_dbg(codec, "%s: sel=%d, preset=%s\n", __func__, sel,
5100 			ca0132_alt_eq_presets[sel].name);
5101 	/*
5102 	 * Idx 0 is default.
5103 	 * Default needs to qualify with CrystalVoice state.
5104 	 */
5105 	for (i = 0; i < EQ_PRESET_MAX_PARAM_COUNT; i++) {
5106 		err = dspio_set_uint_param(codec, ca0132_alt_eq_enum.mid,
5107 				ca0132_alt_eq_enum.reqs[i],
5108 				ca0132_alt_eq_presets[sel].vals[i]);
5109 		if (err < 0)
5110 			break;
5111 	}
5112 
5113 	if (err >= 0)
5114 		spec->eq_preset_val = sel;
5115 
5116 	return 1;
5117 }
5118 
5119 static int ca0132_voicefx_info(struct snd_kcontrol *kcontrol,
5120 				 struct snd_ctl_elem_info *uinfo)
5121 {
5122 	unsigned int items = ARRAY_SIZE(ca0132_voicefx_presets);
5123 
5124 	uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5125 	uinfo->count = 1;
5126 	uinfo->value.enumerated.items = items;
5127 	if (uinfo->value.enumerated.item >= items)
5128 		uinfo->value.enumerated.item = items - 1;
5129 	strcpy(uinfo->value.enumerated.name,
5130 	       ca0132_voicefx_presets[uinfo->value.enumerated.item].name);
5131 	return 0;
5132 }
5133 
5134 static int ca0132_voicefx_get(struct snd_kcontrol *kcontrol,
5135 				struct snd_ctl_elem_value *ucontrol)
5136 {
5137 	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5138 	struct ca0132_spec *spec = codec->spec;
5139 
5140 	ucontrol->value.enumerated.item[0] = spec->voicefx_val;
5141 	return 0;
5142 }
5143 
5144 static int ca0132_voicefx_put(struct snd_kcontrol *kcontrol,
5145 				struct snd_ctl_elem_value *ucontrol)
5146 {
5147 	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5148 	struct ca0132_spec *spec = codec->spec;
5149 	int i, err = 0;
5150 	int sel = ucontrol->value.enumerated.item[0];
5151 
5152 	if (sel >= ARRAY_SIZE(ca0132_voicefx_presets))
5153 		return 0;
5154 
5155 	codec_dbg(codec, "ca0132_voicefx_put: sel=%d, preset=%s\n",
5156 		    sel, ca0132_voicefx_presets[sel].name);
5157 
5158 	/*
5159 	 * Idx 0 is default.
5160 	 * Default needs to qualify with CrystalVoice state.
5161 	 */
5162 	for (i = 0; i < VOICEFX_MAX_PARAM_COUNT; i++) {
5163 		err = dspio_set_uint_param(codec, ca0132_voicefx.mid,
5164 				ca0132_voicefx.reqs[i],
5165 				ca0132_voicefx_presets[sel].vals[i]);
5166 		if (err < 0)
5167 			break;
5168 	}
5169 
5170 	if (err >= 0) {
5171 		spec->voicefx_val = sel;
5172 		/* enable voice fx */
5173 		ca0132_voicefx_set(codec, (sel ? 1 : 0));
5174 	}
5175 
5176 	return 1;
5177 }
5178 
5179 static int ca0132_switch_get(struct snd_kcontrol *kcontrol,
5180 				struct snd_ctl_elem_value *ucontrol)
5181 {
5182 	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5183 	struct ca0132_spec *spec = codec->spec;
5184 	hda_nid_t nid = get_amp_nid(kcontrol);
5185 	int ch = get_amp_channels(kcontrol);
5186 	long *valp = ucontrol->value.integer.value;
5187 
5188 	/* vnode */
5189 	if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
5190 		if (ch & 1) {
5191 			*valp = spec->vnode_lswitch[nid - VNODE_START_NID];
5192 			valp++;
5193 		}
5194 		if (ch & 2) {
5195 			*valp = spec->vnode_rswitch[nid - VNODE_START_NID];
5196 			valp++;
5197 		}
5198 		return 0;
5199 	}
5200 
5201 	/* effects, include PE and CrystalVoice */
5202 	if ((nid >= EFFECT_START_NID) && (nid < EFFECT_END_NID)) {
5203 		*valp = spec->effects_switch[nid - EFFECT_START_NID];
5204 		return 0;
5205 	}
5206 
5207 	/* mic boost */
5208 	if (nid == spec->input_pins[0]) {
5209 		*valp = spec->cur_mic_boost;
5210 		return 0;
5211 	}
5212 
5213 	return 0;
5214 }
5215 
5216 static int ca0132_switch_put(struct snd_kcontrol *kcontrol,
5217 			     struct snd_ctl_elem_value *ucontrol)
5218 {
5219 	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5220 	struct ca0132_spec *spec = codec->spec;
5221 	hda_nid_t nid = get_amp_nid(kcontrol);
5222 	int ch = get_amp_channels(kcontrol);
5223 	long *valp = ucontrol->value.integer.value;
5224 	int changed = 1;
5225 
5226 	codec_dbg(codec, "ca0132_switch_put: nid=0x%x, val=%ld\n",
5227 		    nid, *valp);
5228 
5229 	snd_hda_power_up(codec);
5230 	/* vnode */
5231 	if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
5232 		if (ch & 1) {
5233 			spec->vnode_lswitch[nid - VNODE_START_NID] = *valp;
5234 			valp++;
5235 		}
5236 		if (ch & 2) {
5237 			spec->vnode_rswitch[nid - VNODE_START_NID] = *valp;
5238 			valp++;
5239 		}
5240 		changed = ca0132_vnode_switch_set(kcontrol, ucontrol);
5241 		goto exit;
5242 	}
5243 
5244 	/* PE */
5245 	if (nid == PLAY_ENHANCEMENT) {
5246 		spec->effects_switch[nid - EFFECT_START_NID] = *valp;
5247 		changed = ca0132_pe_switch_set(codec);
5248 		goto exit;
5249 	}
5250 
5251 	/* CrystalVoice */
5252 	if (nid == CRYSTAL_VOICE) {
5253 		spec->effects_switch[nid - EFFECT_START_NID] = *valp;
5254 		changed = ca0132_cvoice_switch_set(codec);
5255 		goto exit;
5256 	}
5257 
5258 	/* out and in effects */
5259 	if (((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) ||
5260 	    ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID))) {
5261 		spec->effects_switch[nid - EFFECT_START_NID] = *valp;
5262 		changed = ca0132_effects_set(codec, nid, *valp);
5263 		goto exit;
5264 	}
5265 
5266 	/* mic boost */
5267 	if (nid == spec->input_pins[0]) {
5268 		spec->cur_mic_boost = *valp;
5269 		if (spec->use_alt_functions) {
5270 			if (spec->in_enum_val != REAR_LINE_IN)
5271 				changed = ca0132_mic_boost_set(codec, *valp);
5272 		} else {
5273 			/* Mic boost does not apply to Digital Mic */
5274 			if (spec->cur_mic_type != DIGITAL_MIC)
5275 				changed = ca0132_mic_boost_set(codec, *valp);
5276 		}
5277 
5278 		goto exit;
5279 	}
5280 
5281 exit:
5282 	snd_hda_power_down(codec);
5283 	return changed;
5284 }
5285 
5286 /*
5287  * Volume related
5288  */
5289 /*
5290  * Sets the internal DSP decibel level to match the DAC for output, and the
5291  * ADC for input. Currently only the SBZ sets dsp capture volume level, and
5292  * all alternative codecs set DSP playback volume.
5293  */
5294 static void ca0132_alt_dsp_volume_put(struct hda_codec *codec, hda_nid_t nid)
5295 {
5296 	struct ca0132_spec *spec = codec->spec;
5297 	unsigned int dsp_dir;
5298 	unsigned int lookup_val;
5299 
5300 	if (nid == VNID_SPK)
5301 		dsp_dir = DSP_VOL_OUT;
5302 	else
5303 		dsp_dir = DSP_VOL_IN;
5304 
5305 	lookup_val = spec->vnode_lvol[nid - VNODE_START_NID];
5306 
5307 	dspio_set_uint_param(codec,
5308 		ca0132_alt_vol_ctls[dsp_dir].mid,
5309 		ca0132_alt_vol_ctls[dsp_dir].reqs[0],
5310 		float_vol_db_lookup[lookup_val]);
5311 
5312 	lookup_val = spec->vnode_rvol[nid - VNODE_START_NID];
5313 
5314 	dspio_set_uint_param(codec,
5315 		ca0132_alt_vol_ctls[dsp_dir].mid,
5316 		ca0132_alt_vol_ctls[dsp_dir].reqs[1],
5317 		float_vol_db_lookup[lookup_val]);
5318 
5319 	dspio_set_uint_param(codec,
5320 		ca0132_alt_vol_ctls[dsp_dir].mid,
5321 		ca0132_alt_vol_ctls[dsp_dir].reqs[2], FLOAT_ZERO);
5322 }
5323 
5324 static int ca0132_volume_info(struct snd_kcontrol *kcontrol,
5325 			      struct snd_ctl_elem_info *uinfo)
5326 {
5327 	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5328 	struct ca0132_spec *spec = codec->spec;
5329 	hda_nid_t nid = get_amp_nid(kcontrol);
5330 	int ch = get_amp_channels(kcontrol);
5331 	int dir = get_amp_direction(kcontrol);
5332 	unsigned long pval;
5333 	int err;
5334 
5335 	switch (nid) {
5336 	case VNID_SPK:
5337 		/* follow shared_out info */
5338 		nid = spec->shared_out_nid;
5339 		mutex_lock(&codec->control_mutex);
5340 		pval = kcontrol->private_value;
5341 		kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
5342 		err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
5343 		kcontrol->private_value = pval;
5344 		mutex_unlock(&codec->control_mutex);
5345 		break;
5346 	case VNID_MIC:
5347 		/* follow shared_mic info */
5348 		nid = spec->shared_mic_nid;
5349 		mutex_lock(&codec->control_mutex);
5350 		pval = kcontrol->private_value;
5351 		kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
5352 		err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
5353 		kcontrol->private_value = pval;
5354 		mutex_unlock(&codec->control_mutex);
5355 		break;
5356 	default:
5357 		err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
5358 	}
5359 	return err;
5360 }
5361 
5362 static int ca0132_volume_get(struct snd_kcontrol *kcontrol,
5363 				struct snd_ctl_elem_value *ucontrol)
5364 {
5365 	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5366 	struct ca0132_spec *spec = codec->spec;
5367 	hda_nid_t nid = get_amp_nid(kcontrol);
5368 	int ch = get_amp_channels(kcontrol);
5369 	long *valp = ucontrol->value.integer.value;
5370 
5371 	/* store the left and right volume */
5372 	if (ch & 1) {
5373 		*valp = spec->vnode_lvol[nid - VNODE_START_NID];
5374 		valp++;
5375 	}
5376 	if (ch & 2) {
5377 		*valp = spec->vnode_rvol[nid - VNODE_START_NID];
5378 		valp++;
5379 	}
5380 	return 0;
5381 }
5382 
5383 static int ca0132_volume_put(struct snd_kcontrol *kcontrol,
5384 				struct snd_ctl_elem_value *ucontrol)
5385 {
5386 	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5387 	struct ca0132_spec *spec = codec->spec;
5388 	hda_nid_t nid = get_amp_nid(kcontrol);
5389 	int ch = get_amp_channels(kcontrol);
5390 	long *valp = ucontrol->value.integer.value;
5391 	hda_nid_t shared_nid = 0;
5392 	bool effective;
5393 	int changed = 1;
5394 
5395 	/* store the left and right volume */
5396 	if (ch & 1) {
5397 		spec->vnode_lvol[nid - VNODE_START_NID] = *valp;
5398 		valp++;
5399 	}
5400 	if (ch & 2) {
5401 		spec->vnode_rvol[nid - VNODE_START_NID] = *valp;
5402 		valp++;
5403 	}
5404 
5405 	/* if effective conditions, then update hw immediately. */
5406 	effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
5407 	if (effective) {
5408 		int dir = get_amp_direction(kcontrol);
5409 		unsigned long pval;
5410 
5411 		snd_hda_power_up(codec);
5412 		mutex_lock(&codec->control_mutex);
5413 		pval = kcontrol->private_value;
5414 		kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
5415 								0, dir);
5416 		changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
5417 		kcontrol->private_value = pval;
5418 		mutex_unlock(&codec->control_mutex);
5419 		snd_hda_power_down(codec);
5420 	}
5421 
5422 	return changed;
5423 }
5424 
5425 /*
5426  * This function is the same as the one above, because using an if statement
5427  * inside of the above volume control for the DSP volume would cause too much
5428  * lag. This is a lot more smooth.
5429  */
5430 static int ca0132_alt_volume_put(struct snd_kcontrol *kcontrol,
5431 				struct snd_ctl_elem_value *ucontrol)
5432 {
5433 	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5434 	struct ca0132_spec *spec = codec->spec;
5435 	hda_nid_t nid = get_amp_nid(kcontrol);
5436 	int ch = get_amp_channels(kcontrol);
5437 	long *valp = ucontrol->value.integer.value;
5438 	hda_nid_t vnid = 0;
5439 	int changed = 1;
5440 
5441 	switch (nid) {
5442 	case 0x02:
5443 		vnid = VNID_SPK;
5444 		break;
5445 	case 0x07:
5446 		vnid = VNID_MIC;
5447 		break;
5448 	}
5449 
5450 	/* store the left and right volume */
5451 	if (ch & 1) {
5452 		spec->vnode_lvol[vnid - VNODE_START_NID] = *valp;
5453 		valp++;
5454 	}
5455 	if (ch & 2) {
5456 		spec->vnode_rvol[vnid - VNODE_START_NID] = *valp;
5457 		valp++;
5458 	}
5459 
5460 	snd_hda_power_up(codec);
5461 	ca0132_alt_dsp_volume_put(codec, vnid);
5462 	mutex_lock(&codec->control_mutex);
5463 	changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
5464 	mutex_unlock(&codec->control_mutex);
5465 	snd_hda_power_down(codec);
5466 
5467 	return changed;
5468 }
5469 
5470 static int ca0132_volume_tlv(struct snd_kcontrol *kcontrol, int op_flag,
5471 			     unsigned int size, unsigned int __user *tlv)
5472 {
5473 	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5474 	struct ca0132_spec *spec = codec->spec;
5475 	hda_nid_t nid = get_amp_nid(kcontrol);
5476 	int ch = get_amp_channels(kcontrol);
5477 	int dir = get_amp_direction(kcontrol);
5478 	unsigned long pval;
5479 	int err;
5480 
5481 	switch (nid) {
5482 	case VNID_SPK:
5483 		/* follow shared_out tlv */
5484 		nid = spec->shared_out_nid;
5485 		mutex_lock(&codec->control_mutex);
5486 		pval = kcontrol->private_value;
5487 		kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
5488 		err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
5489 		kcontrol->private_value = pval;
5490 		mutex_unlock(&codec->control_mutex);
5491 		break;
5492 	case VNID_MIC:
5493 		/* follow shared_mic tlv */
5494 		nid = spec->shared_mic_nid;
5495 		mutex_lock(&codec->control_mutex);
5496 		pval = kcontrol->private_value;
5497 		kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
5498 		err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
5499 		kcontrol->private_value = pval;
5500 		mutex_unlock(&codec->control_mutex);
5501 		break;
5502 	default:
5503 		err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
5504 	}
5505 	return err;
5506 }
5507 
5508 /* Add volume slider control for effect level */
5509 static int ca0132_alt_add_effect_slider(struct hda_codec *codec, hda_nid_t nid,
5510 					const char *pfx, int dir)
5511 {
5512 	char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
5513 	int type = dir ? HDA_INPUT : HDA_OUTPUT;
5514 	struct snd_kcontrol_new knew =
5515 		HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
5516 
5517 	sprintf(namestr, "FX: %s %s Volume", pfx, dirstr[dir]);
5518 
5519 	knew.tlv.c = 0;
5520 	knew.tlv.p = 0;
5521 
5522 	switch (nid) {
5523 	case XBASS_XOVER:
5524 		knew.info = ca0132_alt_xbass_xover_slider_info;
5525 		knew.get = ca0132_alt_xbass_xover_slider_ctl_get;
5526 		knew.put = ca0132_alt_xbass_xover_slider_put;
5527 		break;
5528 	default:
5529 		knew.info = ca0132_alt_effect_slider_info;
5530 		knew.get = ca0132_alt_slider_ctl_get;
5531 		knew.put = ca0132_alt_effect_slider_put;
5532 		knew.private_value =
5533 			HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
5534 		break;
5535 	}
5536 
5537 	return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
5538 }
5539 
5540 /*
5541  * Added FX: prefix for the alternative codecs, because otherwise the surround
5542  * effect would conflict with the Surround sound volume control. Also seems more
5543  * clear as to what the switches do. Left alone for others.
5544  */
5545 static int add_fx_switch(struct hda_codec *codec, hda_nid_t nid,
5546 			 const char *pfx, int dir)
5547 {
5548 	struct ca0132_spec *spec = codec->spec;
5549 	char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
5550 	int type = dir ? HDA_INPUT : HDA_OUTPUT;
5551 	struct snd_kcontrol_new knew =
5552 		CA0132_CODEC_MUTE_MONO(namestr, nid, 1, type);
5553 	/* If using alt_controls, add FX: prefix. But, don't add FX:
5554 	 * prefix to OutFX or InFX enable controls.
5555 	 */
5556 	if ((spec->use_alt_controls) && (nid <= IN_EFFECT_END_NID))
5557 		sprintf(namestr, "FX: %s %s Switch", pfx, dirstr[dir]);
5558 	else
5559 		sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]);
5560 
5561 	return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
5562 }
5563 
5564 static int add_voicefx(struct hda_codec *codec)
5565 {
5566 	struct snd_kcontrol_new knew =
5567 		HDA_CODEC_MUTE_MONO(ca0132_voicefx.name,
5568 				    VOICEFX, 1, 0, HDA_INPUT);
5569 	knew.info = ca0132_voicefx_info;
5570 	knew.get = ca0132_voicefx_get;
5571 	knew.put = ca0132_voicefx_put;
5572 	return snd_hda_ctl_add(codec, VOICEFX, snd_ctl_new1(&knew, codec));
5573 }
5574 
5575 /* Create the EQ Preset control */
5576 static int add_ca0132_alt_eq_presets(struct hda_codec *codec)
5577 {
5578 	struct snd_kcontrol_new knew =
5579 		HDA_CODEC_MUTE_MONO(ca0132_alt_eq_enum.name,
5580 				    EQ_PRESET_ENUM, 1, 0, HDA_OUTPUT);
5581 	knew.info = ca0132_alt_eq_preset_info;
5582 	knew.get = ca0132_alt_eq_preset_get;
5583 	knew.put = ca0132_alt_eq_preset_put;
5584 	return snd_hda_ctl_add(codec, EQ_PRESET_ENUM,
5585 				snd_ctl_new1(&knew, codec));
5586 }
5587 
5588 /*
5589  * Add enumerated control for the three different settings of the smart volume
5590  * output effect. Normal just uses the slider value, and loud and night are
5591  * their own things that ignore that value.
5592  */
5593 static int ca0132_alt_add_svm_enum(struct hda_codec *codec)
5594 {
5595 	struct snd_kcontrol_new knew =
5596 		HDA_CODEC_MUTE_MONO("FX: Smart Volume Setting",
5597 				    SMART_VOLUME_ENUM, 1, 0, HDA_OUTPUT);
5598 	knew.info = ca0132_alt_svm_setting_info;
5599 	knew.get = ca0132_alt_svm_setting_get;
5600 	knew.put = ca0132_alt_svm_setting_put;
5601 	return snd_hda_ctl_add(codec, SMART_VOLUME_ENUM,
5602 				snd_ctl_new1(&knew, codec));
5603 
5604 }
5605 
5606 /*
5607  * Create an Output Select enumerated control for codecs with surround
5608  * out capabilities.
5609  */
5610 static int ca0132_alt_add_output_enum(struct hda_codec *codec)
5611 {
5612 	struct snd_kcontrol_new knew =
5613 		HDA_CODEC_MUTE_MONO("Output Select",
5614 				    OUTPUT_SOURCE_ENUM, 1, 0, HDA_OUTPUT);
5615 	knew.info = ca0132_alt_output_select_get_info;
5616 	knew.get = ca0132_alt_output_select_get;
5617 	knew.put = ca0132_alt_output_select_put;
5618 	return snd_hda_ctl_add(codec, OUTPUT_SOURCE_ENUM,
5619 				snd_ctl_new1(&knew, codec));
5620 }
5621 
5622 /*
5623  * Create an Input Source enumerated control for the alternate ca0132 codecs
5624  * because the front microphone has no auto-detect, and Line-in has to be set
5625  * somehow.
5626  */
5627 static int ca0132_alt_add_input_enum(struct hda_codec *codec)
5628 {
5629 	struct snd_kcontrol_new knew =
5630 		HDA_CODEC_MUTE_MONO("Input Source",
5631 				    INPUT_SOURCE_ENUM, 1, 0, HDA_INPUT);
5632 	knew.info = ca0132_alt_input_source_info;
5633 	knew.get = ca0132_alt_input_source_get;
5634 	knew.put = ca0132_alt_input_source_put;
5635 	return snd_hda_ctl_add(codec, INPUT_SOURCE_ENUM,
5636 				snd_ctl_new1(&knew, codec));
5637 }
5638 
5639 /*
5640  * Add mic boost enumerated control. Switches through 0dB to 30dB. This adds
5641  * more control than the original mic boost, which is either full 30dB or off.
5642  */
5643 static int ca0132_alt_add_mic_boost_enum(struct hda_codec *codec)
5644 {
5645 	struct snd_kcontrol_new knew =
5646 		HDA_CODEC_MUTE_MONO("Mic Boost Capture Switch",
5647 				    MIC_BOOST_ENUM, 1, 0, HDA_INPUT);
5648 	knew.info = ca0132_alt_mic_boost_info;
5649 	knew.get = ca0132_alt_mic_boost_get;
5650 	knew.put = ca0132_alt_mic_boost_put;
5651 	return snd_hda_ctl_add(codec, MIC_BOOST_ENUM,
5652 				snd_ctl_new1(&knew, codec));
5653 
5654 }
5655 
5656 /*
5657  * Need to create slave controls for the alternate codecs that have surround
5658  * capabilities.
5659  */
5660 static const char * const ca0132_alt_slave_pfxs[] = {
5661 	"Front", "Surround", "Center", "LFE", NULL,
5662 };
5663 
5664 /*
5665  * Also need special channel map, because the default one is incorrect.
5666  * I think this has to do with the pin for rear surround being 0x11,
5667  * and the center/lfe being 0x10. Usually the pin order is the opposite.
5668  */
5669 static const struct snd_pcm_chmap_elem ca0132_alt_chmaps[] = {
5670 	{ .channels = 2,
5671 	  .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR } },
5672 	{ .channels = 4,
5673 	  .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR,
5674 		   SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
5675 	{ .channels = 6,
5676 	  .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR,
5677 		   SNDRV_CHMAP_FC, SNDRV_CHMAP_LFE,
5678 		   SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
5679 	{ }
5680 };
5681 
5682 /* Add the correct chmap for streams with 6 channels. */
5683 static void ca0132_alt_add_chmap_ctls(struct hda_codec *codec)
5684 {
5685 	int err = 0;
5686 	struct hda_pcm *pcm;
5687 
5688 	list_for_each_entry(pcm, &codec->pcm_list_head, list) {
5689 		struct hda_pcm_stream *hinfo =
5690 			&pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
5691 		struct snd_pcm_chmap *chmap;
5692 		const struct snd_pcm_chmap_elem *elem;
5693 
5694 		elem = ca0132_alt_chmaps;
5695 		if (hinfo->channels_max == 6) {
5696 			err = snd_pcm_add_chmap_ctls(pcm->pcm,
5697 					SNDRV_PCM_STREAM_PLAYBACK,
5698 					elem, hinfo->channels_max, 0, &chmap);
5699 			if (err < 0)
5700 				codec_dbg(codec, "snd_pcm_add_chmap_ctls failed!");
5701 		}
5702 	}
5703 }
5704 
5705 /*
5706  * When changing Node IDs for Mixer Controls below, make sure to update
5707  * Node IDs in ca0132_config() as well.
5708  */
5709 static const struct snd_kcontrol_new ca0132_mixer[] = {
5710 	CA0132_CODEC_VOL("Master Playback Volume", VNID_SPK, HDA_OUTPUT),
5711 	CA0132_CODEC_MUTE("Master Playback Switch", VNID_SPK, HDA_OUTPUT),
5712 	CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
5713 	CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
5714 	HDA_CODEC_VOLUME("Analog-Mic2 Capture Volume", 0x08, 0, HDA_INPUT),
5715 	HDA_CODEC_MUTE("Analog-Mic2 Capture Switch", 0x08, 0, HDA_INPUT),
5716 	HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
5717 	HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
5718 	CA0132_CODEC_MUTE_MONO("Mic1-Boost (30dB) Capture Switch",
5719 			       0x12, 1, HDA_INPUT),
5720 	CA0132_CODEC_MUTE_MONO("HP/Speaker Playback Switch",
5721 			       VNID_HP_SEL, 1, HDA_OUTPUT),
5722 	CA0132_CODEC_MUTE_MONO("AMic1/DMic Capture Switch",
5723 			       VNID_AMIC1_SEL, 1, HDA_INPUT),
5724 	CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
5725 			       VNID_HP_ASEL, 1, HDA_OUTPUT),
5726 	CA0132_CODEC_MUTE_MONO("AMic1/DMic Auto Detect Capture Switch",
5727 			       VNID_AMIC1_ASEL, 1, HDA_INPUT),
5728 	{ } /* end */
5729 };
5730 
5731 /*
5732  * SBZ specific control mixer. Removes auto-detect for mic, and adds surround
5733  * controls. Also sets both the Front Playback and Capture Volume controls to
5734  * alt so they set the DSP's decibel level.
5735  */
5736 static const struct snd_kcontrol_new sbz_mixer[] = {
5737 	CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT),
5738 	CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT),
5739 	HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT),
5740 	HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT),
5741 	HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT),
5742 	HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT),
5743 	HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT),
5744 	HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT),
5745 	CA0132_ALT_CODEC_VOL("Capture Volume", 0x07, HDA_INPUT),
5746 	CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
5747 	HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
5748 	HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
5749 	CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
5750 				VNID_HP_ASEL, 1, HDA_OUTPUT),
5751 	{ } /* end */
5752 };
5753 
5754 /*
5755  * Same as the Sound Blaster Z, except doesn't use the alt volume for capture
5756  * because it doesn't set decibel levels for the DSP for capture.
5757  */
5758 static const struct snd_kcontrol_new r3di_mixer[] = {
5759 	CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT),
5760 	CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT),
5761 	HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT),
5762 	HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT),
5763 	HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT),
5764 	HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT),
5765 	HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT),
5766 	HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT),
5767 	CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
5768 	CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
5769 	HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
5770 	HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
5771 	CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
5772 				VNID_HP_ASEL, 1, HDA_OUTPUT),
5773 	{ } /* end */
5774 };
5775 
5776 static int ca0132_build_controls(struct hda_codec *codec)
5777 {
5778 	struct ca0132_spec *spec = codec->spec;
5779 	int i, num_fx, num_sliders;
5780 	int err = 0;
5781 
5782 	/* Add Mixer controls */
5783 	for (i = 0; i < spec->num_mixers; i++) {
5784 		err = snd_hda_add_new_ctls(codec, spec->mixers[i]);
5785 		if (err < 0)
5786 			return err;
5787 	}
5788 	/* Setup vmaster with surround slaves for desktop ca0132 devices */
5789 	if (spec->use_alt_functions) {
5790 		snd_hda_set_vmaster_tlv(codec, spec->dacs[0], HDA_OUTPUT,
5791 					spec->tlv);
5792 		snd_hda_add_vmaster(codec, "Master Playback Volume",
5793 					spec->tlv, ca0132_alt_slave_pfxs,
5794 					"Playback Volume");
5795 		err = __snd_hda_add_vmaster(codec, "Master Playback Switch",
5796 					    NULL, ca0132_alt_slave_pfxs,
5797 					    "Playback Switch",
5798 					    true, &spec->vmaster_mute.sw_kctl);
5799 
5800 	}
5801 
5802 	/* Add in and out effects controls.
5803 	 * VoiceFX, PE and CrystalVoice are added separately.
5804 	 */
5805 	num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
5806 	for (i = 0; i < num_fx; i++) {
5807 		/* SBZ breaks if Echo Cancellation is used */
5808 		if (spec->quirk == QUIRK_SBZ) {
5809 			if (i == (ECHO_CANCELLATION - IN_EFFECT_START_NID +
5810 						OUT_EFFECTS_COUNT))
5811 				continue;
5812 		}
5813 
5814 		err = add_fx_switch(codec, ca0132_effects[i].nid,
5815 				    ca0132_effects[i].name,
5816 				    ca0132_effects[i].direct);
5817 		if (err < 0)
5818 			return err;
5819 	}
5820 	/*
5821 	 * If codec has use_alt_controls set to true, add effect level sliders,
5822 	 * EQ presets, and Smart Volume presets. Also, change names to add FX
5823 	 * prefix, and change PlayEnhancement and CrystalVoice to match.
5824 	 */
5825 	if (spec->use_alt_controls) {
5826 		ca0132_alt_add_svm_enum(codec);
5827 		add_ca0132_alt_eq_presets(codec);
5828 		err = add_fx_switch(codec, PLAY_ENHANCEMENT,
5829 					"Enable OutFX", 0);
5830 		if (err < 0)
5831 			return err;
5832 
5833 		err = add_fx_switch(codec, CRYSTAL_VOICE,
5834 					"Enable InFX", 1);
5835 		if (err < 0)
5836 			return err;
5837 
5838 		num_sliders = OUT_EFFECTS_COUNT - 1;
5839 		for (i = 0; i < num_sliders; i++) {
5840 			err = ca0132_alt_add_effect_slider(codec,
5841 					    ca0132_effects[i].nid,
5842 					    ca0132_effects[i].name,
5843 					    ca0132_effects[i].direct);
5844 			if (err < 0)
5845 				return err;
5846 		}
5847 
5848 		err = ca0132_alt_add_effect_slider(codec, XBASS_XOVER,
5849 					"X-Bass Crossover", EFX_DIR_OUT);
5850 
5851 		if (err < 0)
5852 			return err;
5853 	} else {
5854 		err = add_fx_switch(codec, PLAY_ENHANCEMENT,
5855 					"PlayEnhancement", 0);
5856 		if (err < 0)
5857 			return err;
5858 
5859 		err = add_fx_switch(codec, CRYSTAL_VOICE,
5860 					"CrystalVoice", 1);
5861 		if (err < 0)
5862 			return err;
5863 	}
5864 	add_voicefx(codec);
5865 
5866 	/*
5867 	 * If the codec uses alt_functions, you need the enumerated controls
5868 	 * to select the new outputs and inputs, plus add the new mic boost
5869 	 * setting control.
5870 	 */
5871 	if (spec->use_alt_functions) {
5872 		ca0132_alt_add_output_enum(codec);
5873 		ca0132_alt_add_input_enum(codec);
5874 		ca0132_alt_add_mic_boost_enum(codec);
5875 	}
5876 #ifdef ENABLE_TUNING_CONTROLS
5877 	add_tuning_ctls(codec);
5878 #endif
5879 
5880 	err = snd_hda_jack_add_kctls(codec, &spec->autocfg);
5881 	if (err < 0)
5882 		return err;
5883 
5884 	if (spec->dig_out) {
5885 		err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out,
5886 						    spec->dig_out);
5887 		if (err < 0)
5888 			return err;
5889 		err = snd_hda_create_spdif_share_sw(codec, &spec->multiout);
5890 		if (err < 0)
5891 			return err;
5892 		/* spec->multiout.share_spdif = 1; */
5893 	}
5894 
5895 	if (spec->dig_in) {
5896 		err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in);
5897 		if (err < 0)
5898 			return err;
5899 	}
5900 
5901 	if (spec->use_alt_functions)
5902 		ca0132_alt_add_chmap_ctls(codec);
5903 
5904 	return 0;
5905 }
5906 
5907 /*
5908  * PCM
5909  */
5910 static const struct hda_pcm_stream ca0132_pcm_analog_playback = {
5911 	.substreams = 1,
5912 	.channels_min = 2,
5913 	.channels_max = 6,
5914 	.ops = {
5915 		.prepare = ca0132_playback_pcm_prepare,
5916 		.cleanup = ca0132_playback_pcm_cleanup,
5917 		.get_delay = ca0132_playback_pcm_delay,
5918 	},
5919 };
5920 
5921 static const struct hda_pcm_stream ca0132_pcm_analog_capture = {
5922 	.substreams = 1,
5923 	.channels_min = 2,
5924 	.channels_max = 2,
5925 	.ops = {
5926 		.prepare = ca0132_capture_pcm_prepare,
5927 		.cleanup = ca0132_capture_pcm_cleanup,
5928 		.get_delay = ca0132_capture_pcm_delay,
5929 	},
5930 };
5931 
5932 static const struct hda_pcm_stream ca0132_pcm_digital_playback = {
5933 	.substreams = 1,
5934 	.channels_min = 2,
5935 	.channels_max = 2,
5936 	.ops = {
5937 		.open = ca0132_dig_playback_pcm_open,
5938 		.close = ca0132_dig_playback_pcm_close,
5939 		.prepare = ca0132_dig_playback_pcm_prepare,
5940 		.cleanup = ca0132_dig_playback_pcm_cleanup
5941 	},
5942 };
5943 
5944 static const struct hda_pcm_stream ca0132_pcm_digital_capture = {
5945 	.substreams = 1,
5946 	.channels_min = 2,
5947 	.channels_max = 2,
5948 };
5949 
5950 static int ca0132_build_pcms(struct hda_codec *codec)
5951 {
5952 	struct ca0132_spec *spec = codec->spec;
5953 	struct hda_pcm *info;
5954 
5955 	info = snd_hda_codec_pcm_new(codec, "CA0132 Analog");
5956 	if (!info)
5957 		return -ENOMEM;
5958 	if (spec->use_alt_functions) {
5959 		info->own_chmap = true;
5960 		info->stream[SNDRV_PCM_STREAM_PLAYBACK].chmap
5961 			= ca0132_alt_chmaps;
5962 	}
5963 	info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback;
5964 	info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0];
5965 	info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max =
5966 		spec->multiout.max_channels;
5967 	info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
5968 	info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
5969 	info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
5970 
5971 	/* With the DSP enabled, desktops don't use this ADC. */
5972 	if (!spec->use_alt_functions) {
5973 		info = snd_hda_codec_pcm_new(codec, "CA0132 Analog Mic-In2");
5974 		if (!info)
5975 			return -ENOMEM;
5976 		info->stream[SNDRV_PCM_STREAM_CAPTURE] =
5977 			ca0132_pcm_analog_capture;
5978 		info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
5979 		info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[1];
5980 	}
5981 
5982 	info = snd_hda_codec_pcm_new(codec, "CA0132 What U Hear");
5983 	if (!info)
5984 		return -ENOMEM;
5985 	info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
5986 	info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
5987 	info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[2];
5988 
5989 	if (!spec->dig_out && !spec->dig_in)
5990 		return 0;
5991 
5992 	info = snd_hda_codec_pcm_new(codec, "CA0132 Digital");
5993 	if (!info)
5994 		return -ENOMEM;
5995 	info->pcm_type = HDA_PCM_TYPE_SPDIF;
5996 	if (spec->dig_out) {
5997 		info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
5998 			ca0132_pcm_digital_playback;
5999 		info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out;
6000 	}
6001 	if (spec->dig_in) {
6002 		info->stream[SNDRV_PCM_STREAM_CAPTURE] =
6003 			ca0132_pcm_digital_capture;
6004 		info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in;
6005 	}
6006 
6007 	return 0;
6008 }
6009 
6010 static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac)
6011 {
6012 	if (pin) {
6013 		snd_hda_set_pin_ctl(codec, pin, PIN_HP);
6014 		if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
6015 			snd_hda_codec_write(codec, pin, 0,
6016 					    AC_VERB_SET_AMP_GAIN_MUTE,
6017 					    AMP_OUT_UNMUTE);
6018 	}
6019 	if (dac && (get_wcaps(codec, dac) & AC_WCAP_OUT_AMP))
6020 		snd_hda_codec_write(codec, dac, 0,
6021 				    AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO);
6022 }
6023 
6024 static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc)
6025 {
6026 	if (pin) {
6027 		snd_hda_set_pin_ctl(codec, pin, PIN_VREF80);
6028 		if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP)
6029 			snd_hda_codec_write(codec, pin, 0,
6030 					    AC_VERB_SET_AMP_GAIN_MUTE,
6031 					    AMP_IN_UNMUTE(0));
6032 	}
6033 	if (adc && (get_wcaps(codec, adc) & AC_WCAP_IN_AMP)) {
6034 		snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE,
6035 				    AMP_IN_UNMUTE(0));
6036 
6037 		/* init to 0 dB and unmute. */
6038 		snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
6039 					 HDA_AMP_VOLMASK, 0x5a);
6040 		snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
6041 					 HDA_AMP_MUTE, 0);
6042 	}
6043 }
6044 
6045 static void refresh_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir)
6046 {
6047 	unsigned int caps;
6048 
6049 	caps = snd_hda_param_read(codec, nid, dir == HDA_OUTPUT ?
6050 				  AC_PAR_AMP_OUT_CAP : AC_PAR_AMP_IN_CAP);
6051 	snd_hda_override_amp_caps(codec, nid, dir, caps);
6052 }
6053 
6054 /*
6055  * Switch between Digital built-in mic and analog mic.
6056  */
6057 static void ca0132_set_dmic(struct hda_codec *codec, int enable)
6058 {
6059 	struct ca0132_spec *spec = codec->spec;
6060 	unsigned int tmp;
6061 	u8 val;
6062 	unsigned int oldval;
6063 
6064 	codec_dbg(codec, "ca0132_set_dmic: enable=%d\n", enable);
6065 
6066 	oldval = stop_mic1(codec);
6067 	ca0132_set_vipsource(codec, 0);
6068 	if (enable) {
6069 		/* set DMic input as 2-ch */
6070 		tmp = FLOAT_TWO;
6071 		dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6072 
6073 		val = spec->dmic_ctl;
6074 		val |= 0x80;
6075 		snd_hda_codec_write(codec, spec->input_pins[0], 0,
6076 				    VENDOR_CHIPIO_DMIC_CTL_SET, val);
6077 
6078 		if (!(spec->dmic_ctl & 0x20))
6079 			chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 1);
6080 	} else {
6081 		/* set AMic input as mono */
6082 		tmp = FLOAT_ONE;
6083 		dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6084 
6085 		val = spec->dmic_ctl;
6086 		/* clear bit7 and bit5 to disable dmic */
6087 		val &= 0x5f;
6088 		snd_hda_codec_write(codec, spec->input_pins[0], 0,
6089 				    VENDOR_CHIPIO_DMIC_CTL_SET, val);
6090 
6091 		if (!(spec->dmic_ctl & 0x20))
6092 			chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0);
6093 	}
6094 	ca0132_set_vipsource(codec, 1);
6095 	resume_mic1(codec, oldval);
6096 }
6097 
6098 /*
6099  * Initialization for Digital Mic.
6100  */
6101 static void ca0132_init_dmic(struct hda_codec *codec)
6102 {
6103 	struct ca0132_spec *spec = codec->spec;
6104 	u8 val;
6105 
6106 	/* Setup Digital Mic here, but don't enable.
6107 	 * Enable based on jack detect.
6108 	 */
6109 
6110 	/* MCLK uses MPIO1, set to enable.
6111 	 * Bit 2-0: MPIO select
6112 	 * Bit   3: set to disable
6113 	 * Bit 7-4: reserved
6114 	 */
6115 	val = 0x01;
6116 	snd_hda_codec_write(codec, spec->input_pins[0], 0,
6117 			    VENDOR_CHIPIO_DMIC_MCLK_SET, val);
6118 
6119 	/* Data1 uses MPIO3. Data2 not use
6120 	 * Bit 2-0: Data1 MPIO select
6121 	 * Bit   3: set disable Data1
6122 	 * Bit 6-4: Data2 MPIO select
6123 	 * Bit   7: set disable Data2
6124 	 */
6125 	val = 0x83;
6126 	snd_hda_codec_write(codec, spec->input_pins[0], 0,
6127 			    VENDOR_CHIPIO_DMIC_PIN_SET, val);
6128 
6129 	/* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first.
6130 	 * Bit 3-0: Channel mask
6131 	 * Bit   4: set for 48KHz, clear for 32KHz
6132 	 * Bit   5: mode
6133 	 * Bit   6: set to select Data2, clear for Data1
6134 	 * Bit   7: set to enable DMic, clear for AMic
6135 	 */
6136 	if (spec->quirk == QUIRK_ALIENWARE_M17XR4)
6137 		val = 0x33;
6138 	else
6139 		val = 0x23;
6140 	/* keep a copy of dmic ctl val for enable/disable dmic purpuse */
6141 	spec->dmic_ctl = val;
6142 	snd_hda_codec_write(codec, spec->input_pins[0], 0,
6143 			    VENDOR_CHIPIO_DMIC_CTL_SET, val);
6144 }
6145 
6146 /*
6147  * Initialization for Analog Mic 2
6148  */
6149 static void ca0132_init_analog_mic2(struct hda_codec *codec)
6150 {
6151 	struct ca0132_spec *spec = codec->spec;
6152 
6153 	mutex_lock(&spec->chipio_mutex);
6154 	snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6155 			    VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20);
6156 	snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6157 			    VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
6158 	snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6159 			    VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
6160 	snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6161 			    VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x2D);
6162 	snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6163 			    VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
6164 	snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6165 			    VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
6166 	mutex_unlock(&spec->chipio_mutex);
6167 }
6168 
6169 static void ca0132_refresh_widget_caps(struct hda_codec *codec)
6170 {
6171 	struct ca0132_spec *spec = codec->spec;
6172 	int i;
6173 
6174 	codec_dbg(codec, "ca0132_refresh_widget_caps.\n");
6175 	snd_hda_codec_update_widgets(codec);
6176 
6177 	for (i = 0; i < spec->multiout.num_dacs; i++)
6178 		refresh_amp_caps(codec, spec->dacs[i], HDA_OUTPUT);
6179 
6180 	for (i = 0; i < spec->num_outputs; i++)
6181 		refresh_amp_caps(codec, spec->out_pins[i], HDA_OUTPUT);
6182 
6183 	for (i = 0; i < spec->num_inputs; i++) {
6184 		refresh_amp_caps(codec, spec->adcs[i], HDA_INPUT);
6185 		refresh_amp_caps(codec, spec->input_pins[i], HDA_INPUT);
6186 	}
6187 }
6188 
6189 /*
6190  * Recon3Di r3di_setup_defaults sub functions.
6191  */
6192 
6193 static void r3di_dsp_scp_startup(struct hda_codec *codec)
6194 {
6195 	unsigned int tmp;
6196 
6197 	tmp = 0x00000000;
6198 	dspio_set_uint_param_no_source(codec, 0x80, 0x0A, tmp);
6199 
6200 	tmp = 0x00000001;
6201 	dspio_set_uint_param_no_source(codec, 0x80, 0x0B, tmp);
6202 
6203 	tmp = 0x00000004;
6204 	dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6205 
6206 	tmp = 0x00000005;
6207 	dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6208 
6209 	tmp = 0x00000000;
6210 	dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6211 
6212 }
6213 
6214 static void r3di_dsp_initial_mic_setup(struct hda_codec *codec)
6215 {
6216 	unsigned int tmp;
6217 
6218 	/* Mic 1 Setup */
6219 	chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
6220 	chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
6221 	/* This ConnPointID is unique to Recon3Di. Haven't seen it elsewhere */
6222 	chipio_set_conn_rate(codec, 0x0F, SR_96_000);
6223 	tmp = FLOAT_ONE;
6224 	dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6225 
6226 	/* Mic 2 Setup, even though it isn't connected on SBZ */
6227 	chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, SR_96_000);
6228 	chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, SR_96_000);
6229 	chipio_set_conn_rate(codec, 0x0F, SR_96_000);
6230 	tmp = FLOAT_ZERO;
6231 	dspio_set_uint_param(codec, 0x80, 0x01, tmp);
6232 }
6233 
6234 /*
6235  * Initialize Sound Blaster Z analog microphones.
6236  */
6237 static void sbz_init_analog_mics(struct hda_codec *codec)
6238 {
6239 	unsigned int tmp;
6240 
6241 	/* Mic 1 Setup */
6242 	chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
6243 	chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
6244 	tmp = FLOAT_THREE;
6245 	dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6246 
6247 	/* Mic 2 Setup, even though it isn't connected on SBZ */
6248 	chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, SR_96_000);
6249 	chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, SR_96_000);
6250 	tmp = FLOAT_ZERO;
6251 	dspio_set_uint_param(codec, 0x80, 0x01, tmp);
6252 
6253 }
6254 
6255 /*
6256  * Sets the source of stream 0x14 to connpointID 0x48, and the destination
6257  * connpointID to 0x91. If this isn't done, the destination is 0x71, and
6258  * you get no sound. I'm guessing this has to do with the Sound Blaster Z
6259  * having an updated DAC, which changes the destination to that DAC.
6260  */
6261 static void sbz_connect_streams(struct hda_codec *codec)
6262 {
6263 	struct ca0132_spec *spec = codec->spec;
6264 
6265 	mutex_lock(&spec->chipio_mutex);
6266 
6267 	codec_dbg(codec, "Connect Streams entered, mutex locked and loaded.\n");
6268 
6269 	chipio_set_stream_channels(codec, 0x0C, 6);
6270 	chipio_set_stream_control(codec, 0x0C, 1);
6271 
6272 	/* This value is 0x43 for 96khz, and 0x83 for 192khz. */
6273 	chipio_write_no_mutex(codec, 0x18a020, 0x00000043);
6274 
6275 	/* Setup stream 0x14 with it's source and destination points */
6276 	chipio_set_stream_source_dest(codec, 0x14, 0x48, 0x91);
6277 	chipio_set_conn_rate_no_mutex(codec, 0x48, SR_96_000);
6278 	chipio_set_conn_rate_no_mutex(codec, 0x91, SR_96_000);
6279 	chipio_set_stream_channels(codec, 0x14, 2);
6280 	chipio_set_stream_control(codec, 0x14, 1);
6281 
6282 	codec_dbg(codec, "Connect Streams exited, mutex released.\n");
6283 
6284 	mutex_unlock(&spec->chipio_mutex);
6285 
6286 }
6287 
6288 /*
6289  * Write data through ChipIO to setup proper stream destinations.
6290  * Not sure how it exactly works, but it seems to direct data
6291  * to different destinations. Example is f8 to c0, e0 to c0.
6292  * All I know is, if you don't set these, you get no sound.
6293  */
6294 static void sbz_chipio_startup_data(struct hda_codec *codec)
6295 {
6296 	struct ca0132_spec *spec = codec->spec;
6297 
6298 	mutex_lock(&spec->chipio_mutex);
6299 	codec_dbg(codec, "Startup Data entered, mutex locked and loaded.\n");
6300 
6301 	/* These control audio output */
6302 	chipio_write_no_mutex(codec, 0x190060, 0x0001f8c0);
6303 	chipio_write_no_mutex(codec, 0x190064, 0x0001f9c1);
6304 	chipio_write_no_mutex(codec, 0x190068, 0x0001fac6);
6305 	chipio_write_no_mutex(codec, 0x19006c, 0x0001fbc7);
6306 	/* Signal to update I think */
6307 	chipio_write_no_mutex(codec, 0x19042c, 0x00000001);
6308 
6309 	chipio_set_stream_channels(codec, 0x0C, 6);
6310 	chipio_set_stream_control(codec, 0x0C, 1);
6311 	/* No clue what these control */
6312 	chipio_write_no_mutex(codec, 0x190030, 0x0001e0c0);
6313 	chipio_write_no_mutex(codec, 0x190034, 0x0001e1c1);
6314 	chipio_write_no_mutex(codec, 0x190038, 0x0001e4c2);
6315 	chipio_write_no_mutex(codec, 0x19003c, 0x0001e5c3);
6316 	chipio_write_no_mutex(codec, 0x190040, 0x0001e2c4);
6317 	chipio_write_no_mutex(codec, 0x190044, 0x0001e3c5);
6318 	chipio_write_no_mutex(codec, 0x190048, 0x0001e8c6);
6319 	chipio_write_no_mutex(codec, 0x19004c, 0x0001e9c7);
6320 	chipio_write_no_mutex(codec, 0x190050, 0x0001ecc8);
6321 	chipio_write_no_mutex(codec, 0x190054, 0x0001edc9);
6322 	chipio_write_no_mutex(codec, 0x190058, 0x0001eaca);
6323 	chipio_write_no_mutex(codec, 0x19005c, 0x0001ebcb);
6324 
6325 	chipio_write_no_mutex(codec, 0x19042c, 0x00000001);
6326 
6327 	codec_dbg(codec, "Startup Data exited, mutex released.\n");
6328 	mutex_unlock(&spec->chipio_mutex);
6329 }
6330 
6331 /*
6332  * Sound Blaster Z uses these after DSP is loaded. Weird SCP commands
6333  * without a 0x20 source like normal.
6334  */
6335 static void sbz_dsp_scp_startup(struct hda_codec *codec)
6336 {
6337 	unsigned int tmp;
6338 
6339 	tmp = 0x00000003;
6340 	dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6341 
6342 	tmp = 0x00000000;
6343 	dspio_set_uint_param_no_source(codec, 0x80, 0x0A, tmp);
6344 
6345 	tmp = 0x00000001;
6346 	dspio_set_uint_param_no_source(codec, 0x80, 0x0B, tmp);
6347 
6348 	tmp = 0x00000004;
6349 	dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6350 
6351 	tmp = 0x00000005;
6352 	dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6353 
6354 	tmp = 0x00000000;
6355 	dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6356 
6357 }
6358 
6359 static void sbz_dsp_initial_mic_setup(struct hda_codec *codec)
6360 {
6361 	unsigned int tmp;
6362 
6363 	chipio_set_stream_control(codec, 0x03, 0);
6364 	chipio_set_stream_control(codec, 0x04, 0);
6365 
6366 	chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
6367 	chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
6368 
6369 	tmp = FLOAT_THREE;
6370 	dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6371 
6372 	chipio_set_stream_control(codec, 0x03, 1);
6373 	chipio_set_stream_control(codec, 0x04, 1);
6374 
6375 	chipio_write(codec, 0x18b098, 0x0000000c);
6376 	chipio_write(codec, 0x18b09C, 0x0000000c);
6377 }
6378 
6379 /*
6380  * Setup default parameters for DSP
6381  */
6382 static void ca0132_setup_defaults(struct hda_codec *codec)
6383 {
6384 	struct ca0132_spec *spec = codec->spec;
6385 	unsigned int tmp;
6386 	int num_fx;
6387 	int idx, i;
6388 
6389 	if (spec->dsp_state != DSP_DOWNLOADED)
6390 		return;
6391 
6392 	/* out, in effects + voicefx */
6393 	num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
6394 	for (idx = 0; idx < num_fx; idx++) {
6395 		for (i = 0; i <= ca0132_effects[idx].params; i++) {
6396 			dspio_set_uint_param(codec, ca0132_effects[idx].mid,
6397 					     ca0132_effects[idx].reqs[i],
6398 					     ca0132_effects[idx].def_vals[i]);
6399 		}
6400 	}
6401 
6402 	/*remove DSP headroom*/
6403 	tmp = FLOAT_ZERO;
6404 	dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
6405 
6406 	/*set speaker EQ bypass attenuation*/
6407 	dspio_set_uint_param(codec, 0x8f, 0x01, tmp);
6408 
6409 	/* set AMic1 and AMic2 as mono mic */
6410 	tmp = FLOAT_ONE;
6411 	dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6412 	dspio_set_uint_param(codec, 0x80, 0x01, tmp);
6413 
6414 	/* set AMic1 as CrystalVoice input */
6415 	tmp = FLOAT_ONE;
6416 	dspio_set_uint_param(codec, 0x80, 0x05, tmp);
6417 
6418 	/* set WUH source */
6419 	tmp = FLOAT_TWO;
6420 	dspio_set_uint_param(codec, 0x31, 0x00, tmp);
6421 }
6422 
6423 /*
6424  * Setup default parameters for Recon3Di DSP.
6425  */
6426 
6427 static void r3di_setup_defaults(struct hda_codec *codec)
6428 {
6429 	struct ca0132_spec *spec = codec->spec;
6430 	unsigned int tmp;
6431 	int num_fx;
6432 	int idx, i;
6433 
6434 	if (spec->dsp_state != DSP_DOWNLOADED)
6435 		return;
6436 
6437 	r3di_dsp_scp_startup(codec);
6438 
6439 	r3di_dsp_initial_mic_setup(codec);
6440 
6441 	/*remove DSP headroom*/
6442 	tmp = FLOAT_ZERO;
6443 	dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
6444 
6445 	/* set WUH source */
6446 	tmp = FLOAT_TWO;
6447 	dspio_set_uint_param(codec, 0x31, 0x00, tmp);
6448 	chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
6449 
6450 	/* Set speaker source? */
6451 	dspio_set_uint_param(codec, 0x32, 0x00, tmp);
6452 
6453 	r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADED);
6454 
6455 	/* Setup effect defaults */
6456 	num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
6457 	for (idx = 0; idx < num_fx; idx++) {
6458 		for (i = 0; i <= ca0132_effects[idx].params; i++) {
6459 			dspio_set_uint_param(codec,
6460 					ca0132_effects[idx].mid,
6461 					ca0132_effects[idx].reqs[i],
6462 					ca0132_effects[idx].def_vals[i]);
6463 		}
6464 	}
6465 
6466 }
6467 
6468 /*
6469  * Setup default parameters for the Sound Blaster Z DSP. A lot more going on
6470  * than the Chromebook setup.
6471  */
6472 static void sbz_setup_defaults(struct hda_codec *codec)
6473 {
6474 	struct ca0132_spec *spec = codec->spec;
6475 	unsigned int tmp, stream_format;
6476 	int num_fx;
6477 	int idx, i;
6478 
6479 	if (spec->dsp_state != DSP_DOWNLOADED)
6480 		return;
6481 
6482 	sbz_dsp_scp_startup(codec);
6483 
6484 	sbz_init_analog_mics(codec);
6485 
6486 	sbz_connect_streams(codec);
6487 
6488 	sbz_chipio_startup_data(codec);
6489 
6490 	chipio_set_stream_control(codec, 0x03, 1);
6491 	chipio_set_stream_control(codec, 0x04, 1);
6492 
6493 	/*
6494 	 * Sets internal input loopback to off, used to have a switch to
6495 	 * enable input loopback, but turned out to be way too buggy.
6496 	 */
6497 	tmp = FLOAT_ONE;
6498 	dspio_set_uint_param(codec, 0x37, 0x08, tmp);
6499 	dspio_set_uint_param(codec, 0x37, 0x10, tmp);
6500 
6501 	/*remove DSP headroom*/
6502 	tmp = FLOAT_ZERO;
6503 	dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
6504 
6505 	/* set WUH source */
6506 	tmp = FLOAT_TWO;
6507 	dspio_set_uint_param(codec, 0x31, 0x00, tmp);
6508 	chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
6509 
6510 	/* Set speaker source? */
6511 	dspio_set_uint_param(codec, 0x32, 0x00, tmp);
6512 
6513 	sbz_dsp_initial_mic_setup(codec);
6514 
6515 
6516 	/* out, in effects + voicefx */
6517 	num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
6518 	for (idx = 0; idx < num_fx; idx++) {
6519 		for (i = 0; i <= ca0132_effects[idx].params; i++) {
6520 			dspio_set_uint_param(codec,
6521 					ca0132_effects[idx].mid,
6522 					ca0132_effects[idx].reqs[i],
6523 					ca0132_effects[idx].def_vals[i]);
6524 		}
6525 	}
6526 
6527 	/*
6528 	 * Have to make a stream to bind the sound output to, otherwise
6529 	 * you'll get dead audio. Before I did this, it would bind to an
6530 	 * audio input, and would never work
6531 	 */
6532 	stream_format = snd_hdac_calc_stream_format(48000, 2,
6533 			SNDRV_PCM_FORMAT_S32_LE, 32, 0);
6534 
6535 	snd_hda_codec_setup_stream(codec, spec->dacs[0], spec->dsp_stream_id,
6536 					0, stream_format);
6537 
6538 	snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
6539 
6540 	snd_hda_codec_setup_stream(codec, spec->dacs[0], spec->dsp_stream_id,
6541 					0, stream_format);
6542 
6543 	snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
6544 }
6545 
6546 /*
6547  * Initialization of flags in chip
6548  */
6549 static void ca0132_init_flags(struct hda_codec *codec)
6550 {
6551 	struct ca0132_spec *spec = codec->spec;
6552 
6553 	if (spec->use_alt_functions) {
6554 		chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, 1);
6555 		chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, 1);
6556 		chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, 1);
6557 		chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, 1);
6558 		chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, 1);
6559 		chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
6560 		chipio_set_control_flag(codec, CONTROL_FLAG_SPDIF2OUT, 0);
6561 		chipio_set_control_flag(codec,
6562 				CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
6563 		chipio_set_control_flag(codec,
6564 				CONTROL_FLAG_PORT_A_10KOHM_LOAD, 1);
6565 	} else {
6566 		chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
6567 		chipio_set_control_flag(codec,
6568 				CONTROL_FLAG_PORT_A_COMMON_MODE, 0);
6569 		chipio_set_control_flag(codec,
6570 				CONTROL_FLAG_PORT_D_COMMON_MODE, 0);
6571 		chipio_set_control_flag(codec,
6572 				CONTROL_FLAG_PORT_A_10KOHM_LOAD, 0);
6573 		chipio_set_control_flag(codec,
6574 				CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
6575 		chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_HIGH_PASS, 1);
6576 	}
6577 }
6578 
6579 /*
6580  * Initialization of parameters in chip
6581  */
6582 static void ca0132_init_params(struct hda_codec *codec)
6583 {
6584 	struct ca0132_spec *spec = codec->spec;
6585 
6586 	if (spec->use_alt_functions) {
6587 		chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
6588 		chipio_set_conn_rate(codec, 0x0B, SR_48_000);
6589 		chipio_set_control_param(codec, CONTROL_PARAM_SPDIF1_SOURCE, 0);
6590 		chipio_set_control_param(codec, 0, 0);
6591 		chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
6592 	}
6593 
6594 	chipio_set_control_param(codec, CONTROL_PARAM_PORTA_160OHM_GAIN, 6);
6595 	chipio_set_control_param(codec, CONTROL_PARAM_PORTD_160OHM_GAIN, 6);
6596 }
6597 
6598 static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k)
6599 {
6600 	chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k);
6601 	chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k);
6602 	chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k);
6603 	chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k);
6604 	chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k);
6605 	chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k);
6606 
6607 	chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
6608 	chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
6609 	chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
6610 }
6611 
6612 static bool ca0132_download_dsp_images(struct hda_codec *codec)
6613 {
6614 	bool dsp_loaded = false;
6615 	struct ca0132_spec *spec = codec->spec;
6616 	const struct dsp_image_seg *dsp_os_image;
6617 	const struct firmware *fw_entry;
6618 	/*
6619 	 * Alternate firmwares for different variants. The Recon3Di apparently
6620 	 * can use the default firmware, but I'll leave the option in case
6621 	 * it needs it again.
6622 	 */
6623 	switch (spec->quirk) {
6624 	case QUIRK_SBZ:
6625 		if (request_firmware(&fw_entry, SBZ_EFX_FILE,
6626 					codec->card->dev) != 0) {
6627 			codec_dbg(codec, "SBZ alt firmware not detected. ");
6628 			spec->alt_firmware_present = false;
6629 		} else {
6630 			codec_dbg(codec, "Sound Blaster Z firmware selected.");
6631 			spec->alt_firmware_present = true;
6632 		}
6633 		break;
6634 	case QUIRK_R3DI:
6635 		if (request_firmware(&fw_entry, R3DI_EFX_FILE,
6636 					codec->card->dev) != 0) {
6637 			codec_dbg(codec, "Recon3Di alt firmware not detected.");
6638 			spec->alt_firmware_present = false;
6639 		} else {
6640 			codec_dbg(codec, "Recon3Di firmware selected.");
6641 			spec->alt_firmware_present = true;
6642 		}
6643 		break;
6644 	default:
6645 		spec->alt_firmware_present = false;
6646 		break;
6647 	}
6648 	/*
6649 	 * Use default ctefx.bin if no alt firmware is detected, or if none
6650 	 * exists for your particular codec.
6651 	 */
6652 	if (!spec->alt_firmware_present) {
6653 		codec_dbg(codec, "Default firmware selected.");
6654 		if (request_firmware(&fw_entry, EFX_FILE,
6655 					codec->card->dev) != 0)
6656 			return false;
6657 	}
6658 
6659 	dsp_os_image = (struct dsp_image_seg *)(fw_entry->data);
6660 	if (dspload_image(codec, dsp_os_image, 0, 0, true, 0)) {
6661 		codec_err(codec, "ca0132 DSP load image failed\n");
6662 		goto exit_download;
6663 	}
6664 
6665 	dsp_loaded = dspload_wait_loaded(codec);
6666 
6667 exit_download:
6668 	release_firmware(fw_entry);
6669 
6670 	return dsp_loaded;
6671 }
6672 
6673 static void ca0132_download_dsp(struct hda_codec *codec)
6674 {
6675 	struct ca0132_spec *spec = codec->spec;
6676 
6677 #ifndef CONFIG_SND_HDA_CODEC_CA0132_DSP
6678 	return; /* NOP */
6679 #endif
6680 
6681 	if (spec->dsp_state == DSP_DOWNLOAD_FAILED)
6682 		return; /* don't retry failures */
6683 
6684 	chipio_enable_clocks(codec);
6685 	if (spec->dsp_state != DSP_DOWNLOADED) {
6686 		spec->dsp_state = DSP_DOWNLOADING;
6687 
6688 		if (!ca0132_download_dsp_images(codec))
6689 			spec->dsp_state = DSP_DOWNLOAD_FAILED;
6690 		else
6691 			spec->dsp_state = DSP_DOWNLOADED;
6692 	}
6693 
6694 	/* For codecs using alt functions, this is already done earlier */
6695 	if (spec->dsp_state == DSP_DOWNLOADED && (!spec->use_alt_functions))
6696 		ca0132_set_dsp_msr(codec, true);
6697 }
6698 
6699 static void ca0132_process_dsp_response(struct hda_codec *codec,
6700 					struct hda_jack_callback *callback)
6701 {
6702 	struct ca0132_spec *spec = codec->spec;
6703 
6704 	codec_dbg(codec, "ca0132_process_dsp_response\n");
6705 	if (spec->wait_scp) {
6706 		if (dspio_get_response_data(codec) >= 0)
6707 			spec->wait_scp = 0;
6708 	}
6709 
6710 	dspio_clear_response_queue(codec);
6711 }
6712 
6713 static void hp_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
6714 {
6715 	struct ca0132_spec *spec = codec->spec;
6716 	struct hda_jack_tbl *tbl;
6717 
6718 	/* Delay enabling the HP amp, to let the mic-detection
6719 	 * state machine run.
6720 	 */
6721 	cancel_delayed_work_sync(&spec->unsol_hp_work);
6722 	schedule_delayed_work(&spec->unsol_hp_work, msecs_to_jiffies(500));
6723 	tbl = snd_hda_jack_tbl_get(codec, cb->nid);
6724 	if (tbl)
6725 		tbl->block_report = 1;
6726 }
6727 
6728 static void amic_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
6729 {
6730 	ca0132_select_mic(codec);
6731 }
6732 
6733 static void ca0132_init_unsol(struct hda_codec *codec)
6734 {
6735 	struct ca0132_spec *spec = codec->spec;
6736 	snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_hp, hp_callback);
6737 	snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_amic1,
6738 					    amic_callback);
6739 	snd_hda_jack_detect_enable_callback(codec, UNSOL_TAG_DSP,
6740 					    ca0132_process_dsp_response);
6741 	/* Front headphone jack detection */
6742 	if (spec->use_alt_functions)
6743 		snd_hda_jack_detect_enable_callback(codec,
6744 			spec->unsol_tag_front_hp, hp_callback);
6745 }
6746 
6747 /*
6748  * Verbs tables.
6749  */
6750 
6751 /* Sends before DSP download. */
6752 static struct hda_verb ca0132_base_init_verbs[] = {
6753 	/*enable ct extension*/
6754 	{0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1},
6755 	{}
6756 };
6757 
6758 /* Send at exit. */
6759 static struct hda_verb ca0132_base_exit_verbs[] = {
6760 	/*set afg to D3*/
6761 	{0x01, AC_VERB_SET_POWER_STATE, 0x03},
6762 	/*disable ct extension*/
6763 	{0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0},
6764 	{}
6765 };
6766 
6767 /* Other verbs tables. Sends after DSP download. */
6768 
6769 static struct hda_verb ca0132_init_verbs0[] = {
6770 	/* chip init verbs */
6771 	{0x15, 0x70D, 0xF0},
6772 	{0x15, 0x70E, 0xFE},
6773 	{0x15, 0x707, 0x75},
6774 	{0x15, 0x707, 0xD3},
6775 	{0x15, 0x707, 0x09},
6776 	{0x15, 0x707, 0x53},
6777 	{0x15, 0x707, 0xD4},
6778 	{0x15, 0x707, 0xEF},
6779 	{0x15, 0x707, 0x75},
6780 	{0x15, 0x707, 0xD3},
6781 	{0x15, 0x707, 0x09},
6782 	{0x15, 0x707, 0x02},
6783 	{0x15, 0x707, 0x37},
6784 	{0x15, 0x707, 0x78},
6785 	{0x15, 0x53C, 0xCE},
6786 	{0x15, 0x575, 0xC9},
6787 	{0x15, 0x53D, 0xCE},
6788 	{0x15, 0x5B7, 0xC9},
6789 	{0x15, 0x70D, 0xE8},
6790 	{0x15, 0x70E, 0xFE},
6791 	{0x15, 0x707, 0x02},
6792 	{0x15, 0x707, 0x68},
6793 	{0x15, 0x707, 0x62},
6794 	{0x15, 0x53A, 0xCE},
6795 	{0x15, 0x546, 0xC9},
6796 	{0x15, 0x53B, 0xCE},
6797 	{0x15, 0x5E8, 0xC9},
6798 	{}
6799 };
6800 
6801 /* Extra init verbs for SBZ */
6802 static struct hda_verb sbz_init_verbs[] = {
6803 	{0x15, 0x70D, 0x20},
6804 	{0x15, 0x70E, 0x19},
6805 	{0x15, 0x707, 0x00},
6806 	{0x15, 0x539, 0xCE},
6807 	{0x15, 0x546, 0xC9},
6808 	{0x15, 0x70D, 0xB7},
6809 	{0x15, 0x70E, 0x09},
6810 	{0x15, 0x707, 0x10},
6811 	{0x15, 0x70D, 0xAF},
6812 	{0x15, 0x70E, 0x09},
6813 	{0x15, 0x707, 0x01},
6814 	{0x15, 0x707, 0x05},
6815 	{0x15, 0x70D, 0x73},
6816 	{0x15, 0x70E, 0x09},
6817 	{0x15, 0x707, 0x14},
6818 	{0x15, 0x6FF, 0xC4},
6819 	{}
6820 };
6821 
6822 static void ca0132_init_chip(struct hda_codec *codec)
6823 {
6824 	struct ca0132_spec *spec = codec->spec;
6825 	int num_fx;
6826 	int i;
6827 	unsigned int on;
6828 
6829 	mutex_init(&spec->chipio_mutex);
6830 
6831 	spec->cur_out_type = SPEAKER_OUT;
6832 	if (!spec->use_alt_functions)
6833 		spec->cur_mic_type = DIGITAL_MIC;
6834 	else
6835 		spec->cur_mic_type = REAR_MIC;
6836 
6837 	spec->cur_mic_boost = 0;
6838 
6839 	for (i = 0; i < VNODES_COUNT; i++) {
6840 		spec->vnode_lvol[i] = 0x5a;
6841 		spec->vnode_rvol[i] = 0x5a;
6842 		spec->vnode_lswitch[i] = 0;
6843 		spec->vnode_rswitch[i] = 0;
6844 	}
6845 
6846 	/*
6847 	 * Default states for effects are in ca0132_effects[].
6848 	 */
6849 	num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
6850 	for (i = 0; i < num_fx; i++) {
6851 		on = (unsigned int)ca0132_effects[i].reqs[0];
6852 		spec->effects_switch[i] = on ? 1 : 0;
6853 	}
6854 	/*
6855 	 * Sets defaults for the effect slider controls, only for alternative
6856 	 * ca0132 codecs. Also sets x-bass crossover frequency to 80hz.
6857 	 */
6858 	if (spec->use_alt_controls) {
6859 		spec->xbass_xover_freq = 8;
6860 		for (i = 0; i < EFFECT_LEVEL_SLIDERS; i++)
6861 			spec->fx_ctl_val[i] = effect_slider_defaults[i];
6862 	}
6863 
6864 	spec->voicefx_val = 0;
6865 	spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID] = 1;
6866 	spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0;
6867 
6868 #ifdef ENABLE_TUNING_CONTROLS
6869 	ca0132_init_tuning_defaults(codec);
6870 #endif
6871 }
6872 
6873 /*
6874  * Recon3Di exit specific commands.
6875  */
6876 /* prevents popping noise on shutdown */
6877 static void r3di_gpio_shutdown(struct hda_codec *codec)
6878 {
6879 	snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DATA, 0x00);
6880 }
6881 
6882 /*
6883  * Sound Blaster Z exit specific commands.
6884  */
6885 static void sbz_region2_exit(struct hda_codec *codec)
6886 {
6887 	struct ca0132_spec *spec = codec->spec;
6888 	unsigned int i;
6889 
6890 	for (i = 0; i < 4; i++)
6891 		writeb(0x0, spec->mem_base + 0x100);
6892 	for (i = 0; i < 8; i++)
6893 		writeb(0xb3, spec->mem_base + 0x304);
6894 	/*
6895 	 * I believe these are GPIO, with the right most hex digit being the
6896 	 * gpio pin, and the second digit being on or off. We see this more in
6897 	 * the input/output select functions.
6898 	 */
6899 	writew(0x0000, spec->mem_base + 0x320);
6900 	writew(0x0001, spec->mem_base + 0x320);
6901 	writew(0x0104, spec->mem_base + 0x320);
6902 	writew(0x0005, spec->mem_base + 0x320);
6903 	writew(0x0007, spec->mem_base + 0x320);
6904 }
6905 
6906 static void sbz_set_pin_ctl_default(struct hda_codec *codec)
6907 {
6908 	hda_nid_t pins[5] = {0x0B, 0x0C, 0x0E, 0x12, 0x13};
6909 	unsigned int i;
6910 
6911 	snd_hda_codec_write(codec, 0x11, 0,
6912 			AC_VERB_SET_PIN_WIDGET_CONTROL, 0x40);
6913 
6914 	for (i = 0; i < 5; i++)
6915 		snd_hda_codec_write(codec, pins[i], 0,
6916 				AC_VERB_SET_PIN_WIDGET_CONTROL, 0x00);
6917 }
6918 
6919 static void sbz_clear_unsolicited(struct hda_codec *codec)
6920 {
6921 	hda_nid_t pins[7] = {0x0B, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13};
6922 	unsigned int i;
6923 
6924 	for (i = 0; i < 7; i++) {
6925 		snd_hda_codec_write(codec, pins[i], 0,
6926 				AC_VERB_SET_UNSOLICITED_ENABLE, 0x00);
6927 	}
6928 }
6929 
6930 /* On shutdown, sends commands in sets of three */
6931 static void sbz_gpio_shutdown_commands(struct hda_codec *codec, int dir,
6932 							int mask, int data)
6933 {
6934 	if (dir >= 0)
6935 		snd_hda_codec_write(codec, 0x01, 0,
6936 				AC_VERB_SET_GPIO_DIRECTION, dir);
6937 	if (mask >= 0)
6938 		snd_hda_codec_write(codec, 0x01, 0,
6939 				AC_VERB_SET_GPIO_MASK, mask);
6940 
6941 	if (data >= 0)
6942 		snd_hda_codec_write(codec, 0x01, 0,
6943 				AC_VERB_SET_GPIO_DATA, data);
6944 }
6945 
6946 static void sbz_exit_chip(struct hda_codec *codec)
6947 {
6948 	chipio_set_stream_control(codec, 0x03, 0);
6949 	chipio_set_stream_control(codec, 0x04, 0);
6950 
6951 	/* Mess with GPIO */
6952 	sbz_gpio_shutdown_commands(codec, 0x07, 0x07, -1);
6953 	sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x05);
6954 	sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x01);
6955 
6956 	chipio_set_stream_control(codec, 0x14, 0);
6957 	chipio_set_stream_control(codec, 0x0C, 0);
6958 
6959 	chipio_set_conn_rate(codec, 0x41, SR_192_000);
6960 	chipio_set_conn_rate(codec, 0x91, SR_192_000);
6961 
6962 	chipio_write(codec, 0x18a020, 0x00000083);
6963 
6964 	sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x03);
6965 	sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x07);
6966 	sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x06);
6967 
6968 	chipio_set_stream_control(codec, 0x0C, 0);
6969 
6970 	chipio_set_control_param(codec, 0x0D, 0x24);
6971 
6972 	sbz_clear_unsolicited(codec);
6973 	sbz_set_pin_ctl_default(codec);
6974 
6975 	snd_hda_codec_write(codec, 0x0B, 0,
6976 		AC_VERB_SET_EAPD_BTLENABLE, 0x00);
6977 
6978 	if (dspload_is_loaded(codec))
6979 		dsp_reset(codec);
6980 
6981 	snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6982 		VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x00);
6983 
6984 	sbz_region2_exit(codec);
6985 }
6986 
6987 static void ca0132_exit_chip(struct hda_codec *codec)
6988 {
6989 	/* put any chip cleanup stuffs here. */
6990 
6991 	if (dspload_is_loaded(codec))
6992 		dsp_reset(codec);
6993 }
6994 
6995 /*
6996  * This fixes a problem that was hard to reproduce. Very rarely, I would
6997  * boot up, and there would be no sound, but the DSP indicated it had loaded
6998  * properly. I did a few memory dumps to see if anything was different, and
6999  * there were a few areas of memory uninitialized with a1a2a3a4. This function
7000  * checks if those areas are uninitialized, and if they are, it'll attempt to
7001  * reload the card 3 times. Usually it fixes by the second.
7002  */
7003 static void sbz_dsp_startup_check(struct hda_codec *codec)
7004 {
7005 	struct ca0132_spec *spec = codec->spec;
7006 	unsigned int dsp_data_check[4];
7007 	unsigned int cur_address = 0x390;
7008 	unsigned int i;
7009 	unsigned int failure = 0;
7010 	unsigned int reload = 3;
7011 
7012 	if (spec->startup_check_entered)
7013 		return;
7014 
7015 	spec->startup_check_entered = true;
7016 
7017 	for (i = 0; i < 4; i++) {
7018 		chipio_read(codec, cur_address, &dsp_data_check[i]);
7019 		cur_address += 0x4;
7020 	}
7021 	for (i = 0; i < 4; i++) {
7022 		if (dsp_data_check[i] == 0xa1a2a3a4)
7023 			failure = 1;
7024 	}
7025 
7026 	codec_dbg(codec, "Startup Check: %d ", failure);
7027 	if (failure)
7028 		codec_info(codec, "DSP not initialized properly. Attempting to fix.");
7029 	/*
7030 	 * While the failure condition is true, and we haven't reached our
7031 	 * three reload limit, continue trying to reload the driver and
7032 	 * fix the issue.
7033 	 */
7034 	while (failure && (reload != 0)) {
7035 		codec_info(codec, "Reloading... Tries left: %d", reload);
7036 		sbz_exit_chip(codec);
7037 		spec->dsp_state = DSP_DOWNLOAD_INIT;
7038 		codec->patch_ops.init(codec);
7039 		failure = 0;
7040 		for (i = 0; i < 4; i++) {
7041 			chipio_read(codec, cur_address, &dsp_data_check[i]);
7042 			cur_address += 0x4;
7043 		}
7044 		for (i = 0; i < 4; i++) {
7045 			if (dsp_data_check[i] == 0xa1a2a3a4)
7046 				failure = 1;
7047 		}
7048 		reload--;
7049 	}
7050 
7051 	if (!failure && reload < 3)
7052 		codec_info(codec, "DSP fixed.");
7053 
7054 	if (!failure)
7055 		return;
7056 
7057 	codec_info(codec, "DSP failed to initialize properly. Either try a full shutdown or a suspend to clear the internal memory.");
7058 }
7059 
7060 /*
7061  * This is for the extra volume verbs 0x797 (left) and 0x798 (right). These add
7062  * extra precision for decibel values. If you had the dB value in floating point
7063  * you would take the value after the decimal point, multiply by 64, and divide
7064  * by 2. So for 8.59, it's (59 * 64) / 100. Useful if someone wanted to
7065  * implement fixed point or floating point dB volumes. For now, I'll set them
7066  * to 0 just incase a value has lingered from a boot into Windows.
7067  */
7068 static void ca0132_alt_vol_setup(struct hda_codec *codec)
7069 {
7070 	snd_hda_codec_write(codec, 0x02, 0, 0x797, 0x00);
7071 	snd_hda_codec_write(codec, 0x02, 0, 0x798, 0x00);
7072 	snd_hda_codec_write(codec, 0x03, 0, 0x797, 0x00);
7073 	snd_hda_codec_write(codec, 0x03, 0, 0x798, 0x00);
7074 	snd_hda_codec_write(codec, 0x04, 0, 0x797, 0x00);
7075 	snd_hda_codec_write(codec, 0x04, 0, 0x798, 0x00);
7076 	snd_hda_codec_write(codec, 0x07, 0, 0x797, 0x00);
7077 	snd_hda_codec_write(codec, 0x07, 0, 0x798, 0x00);
7078 }
7079 
7080 /*
7081  * Extra commands that don't really fit anywhere else.
7082  */
7083 static void sbz_pre_dsp_setup(struct hda_codec *codec)
7084 {
7085 	struct ca0132_spec *spec = codec->spec;
7086 
7087 	writel(0x00820680, spec->mem_base + 0x01C);
7088 	writel(0x00820680, spec->mem_base + 0x01C);
7089 
7090 	snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xfc);
7091 	snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xfd);
7092 	snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xfe);
7093 	snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xff);
7094 
7095 	chipio_write(codec, 0x18b0a4, 0x000000c2);
7096 
7097 	snd_hda_codec_write(codec, 0x11, 0,
7098 			AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44);
7099 }
7100 
7101 /*
7102  * Extra commands that don't really fit anywhere else.
7103  */
7104 static void r3di_pre_dsp_setup(struct hda_codec *codec)
7105 {
7106 	chipio_write(codec, 0x18b0a4, 0x000000c2);
7107 
7108 	snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7109 			    VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x1E);
7110 	snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7111 			    VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x1C);
7112 	snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7113 			    VENDOR_CHIPIO_8051_DATA_WRITE, 0x5B);
7114 
7115 	snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7116 			    VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20);
7117 	snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7118 			    VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
7119 	snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7120 			    VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
7121 	snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7122 			    VENDOR_CHIPIO_8051_DATA_WRITE, 0x40);
7123 
7124 	snd_hda_codec_write(codec, 0x11, 0,
7125 			AC_VERB_SET_PIN_WIDGET_CONTROL, 0x04);
7126 }
7127 
7128 
7129 /*
7130  * These are sent before the DSP is downloaded. Not sure
7131  * what they do, or if they're necessary. Could possibly
7132  * be removed. Figure they're better to leave in.
7133  */
7134 static void sbz_region2_startup(struct hda_codec *codec)
7135 {
7136 	struct ca0132_spec *spec = codec->spec;
7137 
7138 	writel(0x00000000, spec->mem_base + 0x400);
7139 	writel(0x00000000, spec->mem_base + 0x408);
7140 	writel(0x00000000, spec->mem_base + 0x40C);
7141 	writel(0x00880680, spec->mem_base + 0x01C);
7142 	writel(0x00000083, spec->mem_base + 0xC0C);
7143 	writel(0x00000030, spec->mem_base + 0xC00);
7144 	writel(0x00000000, spec->mem_base + 0xC04);
7145 	writel(0x00000003, spec->mem_base + 0xC0C);
7146 	writel(0x00000003, spec->mem_base + 0xC0C);
7147 	writel(0x00000003, spec->mem_base + 0xC0C);
7148 	writel(0x00000003, spec->mem_base + 0xC0C);
7149 	writel(0x000000C1, spec->mem_base + 0xC08);
7150 	writel(0x000000F1, spec->mem_base + 0xC08);
7151 	writel(0x00000001, spec->mem_base + 0xC08);
7152 	writel(0x000000C7, spec->mem_base + 0xC08);
7153 	writel(0x000000C1, spec->mem_base + 0xC08);
7154 	writel(0x00000080, spec->mem_base + 0xC04);
7155 }
7156 
7157 /*
7158  * Extra init functions for alternative ca0132 codecs. Done
7159  * here so they don't clutter up the main ca0132_init function
7160  * anymore than they have to.
7161  */
7162 static void ca0132_alt_init(struct hda_codec *codec)
7163 {
7164 	struct ca0132_spec *spec = codec->spec;
7165 
7166 	ca0132_alt_vol_setup(codec);
7167 
7168 	switch (spec->quirk) {
7169 	case QUIRK_SBZ:
7170 		codec_dbg(codec, "SBZ alt_init");
7171 		ca0132_gpio_init(codec);
7172 		sbz_pre_dsp_setup(codec);
7173 		snd_hda_sequence_write(codec, spec->chip_init_verbs);
7174 		snd_hda_sequence_write(codec, spec->sbz_init_verbs);
7175 		break;
7176 	case QUIRK_R3DI:
7177 		codec_dbg(codec, "R3DI alt_init");
7178 		ca0132_gpio_init(codec);
7179 		ca0132_gpio_setup(codec);
7180 		r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADING);
7181 		r3di_pre_dsp_setup(codec);
7182 		snd_hda_sequence_write(codec, spec->chip_init_verbs);
7183 		snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x6FF, 0xC4);
7184 		break;
7185 	}
7186 }
7187 
7188 static int ca0132_init(struct hda_codec *codec)
7189 {
7190 	struct ca0132_spec *spec = codec->spec;
7191 	struct auto_pin_cfg *cfg = &spec->autocfg;
7192 	int i;
7193 	bool dsp_loaded;
7194 
7195 	/*
7196 	 * If the DSP is already downloaded, and init has been entered again,
7197 	 * there's only two reasons for it. One, the codec has awaken from a
7198 	 * suspended state, and in that case dspload_is_loaded will return
7199 	 * false, and the init will be ran again. The other reason it gets
7200 	 * re entered is on startup for some reason it triggers a suspend and
7201 	 * resume state. In this case, it will check if the DSP is downloaded,
7202 	 * and not run the init function again. For codecs using alt_functions,
7203 	 * it will check if the DSP is loaded properly.
7204 	 */
7205 	if (spec->dsp_state == DSP_DOWNLOADED) {
7206 		dsp_loaded = dspload_is_loaded(codec);
7207 		if (!dsp_loaded) {
7208 			spec->dsp_reload = true;
7209 			spec->dsp_state = DSP_DOWNLOAD_INIT;
7210 		} else {
7211 			if (spec->quirk == QUIRK_SBZ)
7212 				sbz_dsp_startup_check(codec);
7213 			return 0;
7214 		}
7215 	}
7216 
7217 	if (spec->dsp_state != DSP_DOWNLOAD_FAILED)
7218 		spec->dsp_state = DSP_DOWNLOAD_INIT;
7219 	spec->curr_chip_addx = INVALID_CHIP_ADDRESS;
7220 
7221 	if (spec->quirk == QUIRK_SBZ)
7222 		sbz_region2_startup(codec);
7223 
7224 	snd_hda_power_up_pm(codec);
7225 
7226 	ca0132_init_unsol(codec);
7227 	ca0132_init_params(codec);
7228 	ca0132_init_flags(codec);
7229 
7230 	snd_hda_sequence_write(codec, spec->base_init_verbs);
7231 
7232 	if (spec->use_alt_functions)
7233 		ca0132_alt_init(codec);
7234 
7235 	ca0132_download_dsp(codec);
7236 
7237 	ca0132_refresh_widget_caps(codec);
7238 
7239 	if (spec->quirk == QUIRK_SBZ)
7240 		writew(0x0107, spec->mem_base + 0x320);
7241 
7242 	switch (spec->quirk) {
7243 	case QUIRK_R3DI:
7244 		r3di_setup_defaults(codec);
7245 		break;
7246 	case QUIRK_SBZ:
7247 		break;
7248 	default:
7249 		ca0132_setup_defaults(codec);
7250 		ca0132_init_analog_mic2(codec);
7251 		ca0132_init_dmic(codec);
7252 		break;
7253 	}
7254 
7255 	for (i = 0; i < spec->num_outputs; i++)
7256 		init_output(codec, spec->out_pins[i], spec->dacs[0]);
7257 
7258 	init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
7259 
7260 	for (i = 0; i < spec->num_inputs; i++)
7261 		init_input(codec, spec->input_pins[i], spec->adcs[i]);
7262 
7263 	init_input(codec, cfg->dig_in_pin, spec->dig_in);
7264 
7265 	if (!spec->use_alt_functions) {
7266 		snd_hda_sequence_write(codec, spec->chip_init_verbs);
7267 		snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7268 			    VENDOR_CHIPIO_PARAM_EX_ID_SET, 0x0D);
7269 		snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7270 			    VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 0x20);
7271 	}
7272 
7273 	if (spec->quirk == QUIRK_SBZ)
7274 		ca0132_gpio_setup(codec);
7275 
7276 	snd_hda_sequence_write(codec, spec->spec_init_verbs);
7277 	switch (spec->quirk) {
7278 	case QUIRK_SBZ:
7279 		sbz_setup_defaults(codec);
7280 		ca0132_alt_select_out(codec);
7281 		ca0132_alt_select_in(codec);
7282 		break;
7283 	case QUIRK_R3DI:
7284 		ca0132_alt_select_out(codec);
7285 		ca0132_alt_select_in(codec);
7286 		break;
7287 	default:
7288 		ca0132_select_out(codec);
7289 		ca0132_select_mic(codec);
7290 		break;
7291 	}
7292 
7293 	snd_hda_jack_report_sync(codec);
7294 
7295 	/*
7296 	 * Re set the PlayEnhancement switch on a resume event, because the
7297 	 * controls will not be reloaded.
7298 	 */
7299 	if (spec->dsp_reload) {
7300 		spec->dsp_reload = false;
7301 		ca0132_pe_switch_set(codec);
7302 	}
7303 
7304 	snd_hda_power_down_pm(codec);
7305 
7306 	return 0;
7307 }
7308 
7309 static void ca0132_free(struct hda_codec *codec)
7310 {
7311 	struct ca0132_spec *spec = codec->spec;
7312 
7313 	cancel_delayed_work_sync(&spec->unsol_hp_work);
7314 	snd_hda_power_up(codec);
7315 	switch (spec->quirk) {
7316 	case QUIRK_SBZ:
7317 		sbz_exit_chip(codec);
7318 		break;
7319 	case QUIRK_R3DI:
7320 		r3di_gpio_shutdown(codec);
7321 		snd_hda_sequence_write(codec, spec->base_exit_verbs);
7322 		ca0132_exit_chip(codec);
7323 		break;
7324 	default:
7325 		snd_hda_sequence_write(codec, spec->base_exit_verbs);
7326 		ca0132_exit_chip(codec);
7327 		break;
7328 	}
7329 	snd_hda_power_down(codec);
7330 	if (spec->mem_base)
7331 		iounmap(spec->mem_base);
7332 	kfree(spec->spec_init_verbs);
7333 	kfree(codec->spec);
7334 }
7335 
7336 static void ca0132_reboot_notify(struct hda_codec *codec)
7337 {
7338 	codec->patch_ops.free(codec);
7339 }
7340 
7341 static const struct hda_codec_ops ca0132_patch_ops = {
7342 	.build_controls = ca0132_build_controls,
7343 	.build_pcms = ca0132_build_pcms,
7344 	.init = ca0132_init,
7345 	.free = ca0132_free,
7346 	.unsol_event = snd_hda_jack_unsol_event,
7347 	.reboot_notify = ca0132_reboot_notify,
7348 };
7349 
7350 static void ca0132_config(struct hda_codec *codec)
7351 {
7352 	struct ca0132_spec *spec = codec->spec;
7353 
7354 	spec->dacs[0] = 0x2;
7355 	spec->dacs[1] = 0x3;
7356 	spec->dacs[2] = 0x4;
7357 
7358 	spec->multiout.dac_nids = spec->dacs;
7359 	spec->multiout.num_dacs = 3;
7360 
7361 	if (!spec->use_alt_functions)
7362 		spec->multiout.max_channels = 2;
7363 	else
7364 		spec->multiout.max_channels = 6;
7365 
7366 	switch (spec->quirk) {
7367 	case QUIRK_ALIENWARE:
7368 		codec_dbg(codec, "ca0132_config: QUIRK_ALIENWARE applied.\n");
7369 		snd_hda_apply_pincfgs(codec, alienware_pincfgs);
7370 
7371 		spec->num_outputs = 2;
7372 		spec->out_pins[0] = 0x0b; /* speaker out */
7373 		spec->out_pins[1] = 0x0f;
7374 		spec->shared_out_nid = 0x2;
7375 		spec->unsol_tag_hp = 0x0f;
7376 
7377 		spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
7378 		spec->adcs[1] = 0x8; /* analog mic2 */
7379 		spec->adcs[2] = 0xa; /* what u hear */
7380 
7381 		spec->num_inputs = 3;
7382 		spec->input_pins[0] = 0x12;
7383 		spec->input_pins[1] = 0x11;
7384 		spec->input_pins[2] = 0x13;
7385 		spec->shared_mic_nid = 0x7;
7386 		spec->unsol_tag_amic1 = 0x11;
7387 		break;
7388 	case QUIRK_SBZ:
7389 		codec_dbg(codec, "%s: QUIRK_SBZ applied.\n", __func__);
7390 		snd_hda_apply_pincfgs(codec, sbz_pincfgs);
7391 
7392 		spec->num_outputs = 2;
7393 		spec->out_pins[0] = 0x0B; /* Line out */
7394 		spec->out_pins[1] = 0x0F; /* Rear headphone out */
7395 		spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
7396 		spec->out_pins[3] = 0x11; /* Rear surround */
7397 		spec->shared_out_nid = 0x2;
7398 		spec->unsol_tag_hp = spec->out_pins[1];
7399 		spec->unsol_tag_front_hp = spec->out_pins[2];
7400 
7401 		spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
7402 		spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */
7403 		spec->adcs[2] = 0xa; /* what u hear */
7404 
7405 		spec->num_inputs = 2;
7406 		spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
7407 		spec->input_pins[1] = 0x13; /* What U Hear */
7408 		spec->shared_mic_nid = 0x7;
7409 		spec->unsol_tag_amic1 = spec->input_pins[0];
7410 
7411 		/* SPDIF I/O */
7412 		spec->dig_out = 0x05;
7413 		spec->multiout.dig_out_nid = spec->dig_out;
7414 		spec->dig_in = 0x09;
7415 		break;
7416 	case QUIRK_R3DI:
7417 		codec_dbg(codec, "%s: QUIRK_R3DI applied.\n", __func__);
7418 		snd_hda_apply_pincfgs(codec, r3di_pincfgs);
7419 
7420 		spec->num_outputs = 2;
7421 		spec->out_pins[0] = 0x0B; /* Line out */
7422 		spec->out_pins[1] = 0x0F; /* Rear headphone out */
7423 		spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
7424 		spec->out_pins[3] = 0x11; /* Rear surround */
7425 		spec->shared_out_nid = 0x2;
7426 		spec->unsol_tag_hp = spec->out_pins[1];
7427 		spec->unsol_tag_front_hp = spec->out_pins[2];
7428 
7429 		spec->adcs[0] = 0x07; /* Rear Mic / Line-in */
7430 		spec->adcs[1] = 0x08; /* Front Mic, but only if no DSP */
7431 		spec->adcs[2] = 0x0a; /* what u hear */
7432 
7433 		spec->num_inputs = 2;
7434 		spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
7435 		spec->input_pins[1] = 0x13; /* What U Hear */
7436 		spec->shared_mic_nid = 0x7;
7437 		spec->unsol_tag_amic1 = spec->input_pins[0];
7438 
7439 		/* SPDIF I/O */
7440 		spec->dig_out = 0x05;
7441 		spec->multiout.dig_out_nid = spec->dig_out;
7442 		break;
7443 	default:
7444 		spec->num_outputs = 2;
7445 		spec->out_pins[0] = 0x0b; /* speaker out */
7446 		spec->out_pins[1] = 0x10; /* headphone out */
7447 		spec->shared_out_nid = 0x2;
7448 		spec->unsol_tag_hp = spec->out_pins[1];
7449 
7450 		spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
7451 		spec->adcs[1] = 0x8; /* analog mic2 */
7452 		spec->adcs[2] = 0xa; /* what u hear */
7453 
7454 		spec->num_inputs = 3;
7455 		spec->input_pins[0] = 0x12;
7456 		spec->input_pins[1] = 0x11;
7457 		spec->input_pins[2] = 0x13;
7458 		spec->shared_mic_nid = 0x7;
7459 		spec->unsol_tag_amic1 = spec->input_pins[0];
7460 
7461 		/* SPDIF I/O */
7462 		spec->dig_out = 0x05;
7463 		spec->multiout.dig_out_nid = spec->dig_out;
7464 		spec->dig_in = 0x09;
7465 		break;
7466 	}
7467 }
7468 
7469 static int ca0132_prepare_verbs(struct hda_codec *codec)
7470 {
7471 /* Verbs + terminator (an empty element) */
7472 #define NUM_SPEC_VERBS 2
7473 	struct ca0132_spec *spec = codec->spec;
7474 
7475 	spec->chip_init_verbs = ca0132_init_verbs0;
7476 	if (spec->quirk == QUIRK_SBZ)
7477 		spec->sbz_init_verbs = sbz_init_verbs;
7478 	spec->spec_init_verbs = kcalloc(NUM_SPEC_VERBS,
7479 					sizeof(struct hda_verb),
7480 					GFP_KERNEL);
7481 	if (!spec->spec_init_verbs)
7482 		return -ENOMEM;
7483 
7484 	/* config EAPD */
7485 	spec->spec_init_verbs[0].nid = 0x0b;
7486 	spec->spec_init_verbs[0].param = 0x78D;
7487 	spec->spec_init_verbs[0].verb = 0x00;
7488 
7489 	/* Previously commented configuration */
7490 	/*
7491 	spec->spec_init_verbs[2].nid = 0x0b;
7492 	spec->spec_init_verbs[2].param = AC_VERB_SET_EAPD_BTLENABLE;
7493 	spec->spec_init_verbs[2].verb = 0x02;
7494 
7495 	spec->spec_init_verbs[3].nid = 0x10;
7496 	spec->spec_init_verbs[3].param = 0x78D;
7497 	spec->spec_init_verbs[3].verb = 0x02;
7498 
7499 	spec->spec_init_verbs[4].nid = 0x10;
7500 	spec->spec_init_verbs[4].param = AC_VERB_SET_EAPD_BTLENABLE;
7501 	spec->spec_init_verbs[4].verb = 0x02;
7502 	*/
7503 
7504 	/* Terminator: spec->spec_init_verbs[NUM_SPEC_VERBS-1] */
7505 	return 0;
7506 }
7507 
7508 static int patch_ca0132(struct hda_codec *codec)
7509 {
7510 	struct ca0132_spec *spec;
7511 	int err;
7512 	const struct snd_pci_quirk *quirk;
7513 
7514 	codec_dbg(codec, "patch_ca0132\n");
7515 
7516 	spec = kzalloc(sizeof(*spec), GFP_KERNEL);
7517 	if (!spec)
7518 		return -ENOMEM;
7519 	codec->spec = spec;
7520 	spec->codec = codec;
7521 
7522 	codec->patch_ops = ca0132_patch_ops;
7523 	codec->pcm_format_first = 1;
7524 	codec->no_sticky_stream = 1;
7525 
7526 	/* Detect codec quirk */
7527 	quirk = snd_pci_quirk_lookup(codec->bus->pci, ca0132_quirks);
7528 	if (quirk)
7529 		spec->quirk = quirk->value;
7530 	else
7531 		spec->quirk = QUIRK_NONE;
7532 
7533 	/* Setup BAR Region 2 for Sound Blaster Z */
7534 	if (spec->quirk == QUIRK_SBZ) {
7535 		spec->mem_base = pci_iomap(codec->bus->pci, 2, 0xC20);
7536 		if (spec->mem_base == NULL) {
7537 			codec_warn(codec, "pci_iomap failed!");
7538 			codec_info(codec, "perhaps this is not an SBZ?");
7539 			spec->quirk = QUIRK_NONE;
7540 		}
7541 	}
7542 
7543 	spec->dsp_state = DSP_DOWNLOAD_INIT;
7544 	spec->num_mixers = 1;
7545 
7546 	/* Set which mixers each quirk uses. */
7547 	switch (spec->quirk) {
7548 	case QUIRK_SBZ:
7549 		spec->mixers[0] = sbz_mixer;
7550 		snd_hda_codec_set_name(codec, "Sound Blaster Z");
7551 		break;
7552 	case QUIRK_R3DI:
7553 		spec->mixers[0] = r3di_mixer;
7554 		snd_hda_codec_set_name(codec, "Recon3Di");
7555 		break;
7556 	default:
7557 		spec->mixers[0] = ca0132_mixer;
7558 		break;
7559 	}
7560 
7561 	/* Setup whether or not to use alt functions/controls */
7562 	switch (spec->quirk) {
7563 	case QUIRK_SBZ:
7564 	case QUIRK_R3DI:
7565 		spec->use_alt_controls = true;
7566 		spec->use_alt_functions = true;
7567 		break;
7568 	default:
7569 		spec->use_alt_controls = false;
7570 		spec->use_alt_functions = false;
7571 		break;
7572 	}
7573 
7574 	spec->base_init_verbs = ca0132_base_init_verbs;
7575 	spec->base_exit_verbs = ca0132_base_exit_verbs;
7576 
7577 	INIT_DELAYED_WORK(&spec->unsol_hp_work, ca0132_unsol_hp_delayed);
7578 
7579 	ca0132_init_chip(codec);
7580 
7581 	ca0132_config(codec);
7582 
7583 	err = ca0132_prepare_verbs(codec);
7584 	if (err < 0)
7585 		goto error;
7586 
7587 	err = snd_hda_parse_pin_def_config(codec, &spec->autocfg, NULL);
7588 	if (err < 0)
7589 		goto error;
7590 
7591 	return 0;
7592 
7593  error:
7594 	ca0132_free(codec);
7595 	return err;
7596 }
7597 
7598 /*
7599  * patch entries
7600  */
7601 static struct hda_device_id snd_hda_id_ca0132[] = {
7602 	HDA_CODEC_ENTRY(0x11020011, "CA0132", patch_ca0132),
7603 	{} /* terminator */
7604 };
7605 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_ca0132);
7606 
7607 MODULE_LICENSE("GPL");
7608 MODULE_DESCRIPTION("Creative Sound Core3D codec");
7609 
7610 static struct hda_codec_driver ca0132_driver = {
7611 	.id = snd_hda_id_ca0132,
7612 };
7613 
7614 module_hda_codec_driver(ca0132_driver);
7615