1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * HD audio interface patch for Creative CA0132 chip 4 * 5 * Copyright (c) 2011, Creative Technology Ltd. 6 * 7 * Based on patch_ca0110.c 8 * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de> 9 */ 10 11 #include <linux/init.h> 12 #include <linux/delay.h> 13 #include <linux/slab.h> 14 #include <linux/mutex.h> 15 #include <linux/module.h> 16 #include <linux/firmware.h> 17 #include <linux/kernel.h> 18 #include <linux/types.h> 19 #include <linux/io.h> 20 #include <linux/pci.h> 21 #include <asm/io.h> 22 #include <sound/core.h> 23 #include <sound/hda_codec.h> 24 #include "hda_local.h" 25 #include "hda_auto_parser.h" 26 #include "hda_jack.h" 27 28 #include "ca0132_regs.h" 29 30 /* Enable this to see controls for tuning purpose. */ 31 /*#define ENABLE_TUNING_CONTROLS*/ 32 33 #ifdef ENABLE_TUNING_CONTROLS 34 #include <sound/tlv.h> 35 #endif 36 37 #define FLOAT_ZERO 0x00000000 38 #define FLOAT_ONE 0x3f800000 39 #define FLOAT_TWO 0x40000000 40 #define FLOAT_THREE 0x40400000 41 #define FLOAT_EIGHT 0x41000000 42 #define FLOAT_MINUS_5 0xc0a00000 43 44 #define UNSOL_TAG_DSP 0x16 45 46 #define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18) 47 #define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15) 48 49 #define DMA_TRANSFER_FRAME_SIZE_NWORDS 8 50 #define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS 32 51 #define DMA_OVERLAY_FRAME_SIZE_NWORDS 2 52 53 #define MASTERCONTROL 0x80 54 #define MASTERCONTROL_ALLOC_DMA_CHAN 10 55 #define MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS 60 56 57 #define WIDGET_CHIP_CTRL 0x15 58 #define WIDGET_DSP_CTRL 0x16 59 60 #define MEM_CONNID_MICIN1 3 61 #define MEM_CONNID_MICIN2 5 62 #define MEM_CONNID_MICOUT1 12 63 #define MEM_CONNID_MICOUT2 14 64 #define MEM_CONNID_WUH 10 65 #define MEM_CONNID_DSP 16 66 #define MEM_CONNID_DMIC 100 67 68 #define SCP_SET 0 69 #define SCP_GET 1 70 71 #define EFX_FILE "ctefx.bin" 72 #define DESKTOP_EFX_FILE "ctefx-desktop.bin" 73 #define R3DI_EFX_FILE "ctefx-r3di.bin" 74 75 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP 76 MODULE_FIRMWARE(EFX_FILE); 77 MODULE_FIRMWARE(DESKTOP_EFX_FILE); 78 MODULE_FIRMWARE(R3DI_EFX_FILE); 79 #endif 80 81 static const char *const dirstr[2] = { "Playback", "Capture" }; 82 83 #define NUM_OF_OUTPUTS 3 84 enum { 85 SPEAKER_OUT, 86 HEADPHONE_OUT, 87 SURROUND_OUT 88 }; 89 90 enum { 91 DIGITAL_MIC, 92 LINE_MIC_IN 93 }; 94 95 /* Strings for Input Source Enum Control */ 96 static const char *const in_src_str[3] = {"Rear Mic", "Line", "Front Mic" }; 97 #define IN_SRC_NUM_OF_INPUTS 3 98 enum { 99 REAR_MIC, 100 REAR_LINE_IN, 101 FRONT_MIC, 102 }; 103 104 enum { 105 #define VNODE_START_NID 0x80 106 VNID_SPK = VNODE_START_NID, /* Speaker vnid */ 107 VNID_MIC, 108 VNID_HP_SEL, 109 VNID_AMIC1_SEL, 110 VNID_HP_ASEL, 111 VNID_AMIC1_ASEL, 112 VNODE_END_NID, 113 #define VNODES_COUNT (VNODE_END_NID - VNODE_START_NID) 114 115 #define EFFECT_START_NID 0x90 116 #define OUT_EFFECT_START_NID EFFECT_START_NID 117 SURROUND = OUT_EFFECT_START_NID, 118 CRYSTALIZER, 119 DIALOG_PLUS, 120 SMART_VOLUME, 121 X_BASS, 122 EQUALIZER, 123 OUT_EFFECT_END_NID, 124 #define OUT_EFFECTS_COUNT (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID) 125 126 #define IN_EFFECT_START_NID OUT_EFFECT_END_NID 127 ECHO_CANCELLATION = IN_EFFECT_START_NID, 128 VOICE_FOCUS, 129 MIC_SVM, 130 NOISE_REDUCTION, 131 IN_EFFECT_END_NID, 132 #define IN_EFFECTS_COUNT (IN_EFFECT_END_NID - IN_EFFECT_START_NID) 133 134 VOICEFX = IN_EFFECT_END_NID, 135 PLAY_ENHANCEMENT, 136 CRYSTAL_VOICE, 137 EFFECT_END_NID, 138 OUTPUT_SOURCE_ENUM, 139 INPUT_SOURCE_ENUM, 140 XBASS_XOVER, 141 EQ_PRESET_ENUM, 142 SMART_VOLUME_ENUM, 143 MIC_BOOST_ENUM, 144 AE5_HEADPHONE_GAIN_ENUM, 145 AE5_SOUND_FILTER_ENUM, 146 ZXR_HEADPHONE_GAIN 147 #define EFFECTS_COUNT (EFFECT_END_NID - EFFECT_START_NID) 148 }; 149 150 /* Effects values size*/ 151 #define EFFECT_VALS_MAX_COUNT 12 152 153 /* 154 * Default values for the effect slider controls, they are in order of their 155 * effect NID's. Surround, Crystalizer, Dialog Plus, Smart Volume, and then 156 * X-bass. 157 */ 158 static const unsigned int effect_slider_defaults[] = {67, 65, 50, 74, 50}; 159 /* Amount of effect level sliders for ca0132_alt controls. */ 160 #define EFFECT_LEVEL_SLIDERS 5 161 162 /* Latency introduced by DSP blocks in milliseconds. */ 163 #define DSP_CAPTURE_INIT_LATENCY 0 164 #define DSP_CRYSTAL_VOICE_LATENCY 124 165 #define DSP_PLAYBACK_INIT_LATENCY 13 166 #define DSP_PLAY_ENHANCEMENT_LATENCY 30 167 #define DSP_SPEAKER_OUT_LATENCY 7 168 169 struct ct_effect { 170 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 171 hda_nid_t nid; 172 int mid; /*effect module ID*/ 173 int reqs[EFFECT_VALS_MAX_COUNT]; /*effect module request*/ 174 int direct; /* 0:output; 1:input*/ 175 int params; /* number of default non-on/off params */ 176 /*effect default values, 1st is on/off. */ 177 unsigned int def_vals[EFFECT_VALS_MAX_COUNT]; 178 }; 179 180 #define EFX_DIR_OUT 0 181 #define EFX_DIR_IN 1 182 183 static const struct ct_effect ca0132_effects[EFFECTS_COUNT] = { 184 { .name = "Surround", 185 .nid = SURROUND, 186 .mid = 0x96, 187 .reqs = {0, 1}, 188 .direct = EFX_DIR_OUT, 189 .params = 1, 190 .def_vals = {0x3F800000, 0x3F2B851F} 191 }, 192 { .name = "Crystalizer", 193 .nid = CRYSTALIZER, 194 .mid = 0x96, 195 .reqs = {7, 8}, 196 .direct = EFX_DIR_OUT, 197 .params = 1, 198 .def_vals = {0x3F800000, 0x3F266666} 199 }, 200 { .name = "Dialog Plus", 201 .nid = DIALOG_PLUS, 202 .mid = 0x96, 203 .reqs = {2, 3}, 204 .direct = EFX_DIR_OUT, 205 .params = 1, 206 .def_vals = {0x00000000, 0x3F000000} 207 }, 208 { .name = "Smart Volume", 209 .nid = SMART_VOLUME, 210 .mid = 0x96, 211 .reqs = {4, 5, 6}, 212 .direct = EFX_DIR_OUT, 213 .params = 2, 214 .def_vals = {0x3F800000, 0x3F3D70A4, 0x00000000} 215 }, 216 { .name = "X-Bass", 217 .nid = X_BASS, 218 .mid = 0x96, 219 .reqs = {24, 23, 25}, 220 .direct = EFX_DIR_OUT, 221 .params = 2, 222 .def_vals = {0x3F800000, 0x42A00000, 0x3F000000} 223 }, 224 { .name = "Equalizer", 225 .nid = EQUALIZER, 226 .mid = 0x96, 227 .reqs = {9, 10, 11, 12, 13, 14, 228 15, 16, 17, 18, 19, 20}, 229 .direct = EFX_DIR_OUT, 230 .params = 11, 231 .def_vals = {0x00000000, 0x00000000, 0x00000000, 0x00000000, 232 0x00000000, 0x00000000, 0x00000000, 0x00000000, 233 0x00000000, 0x00000000, 0x00000000, 0x00000000} 234 }, 235 { .name = "Echo Cancellation", 236 .nid = ECHO_CANCELLATION, 237 .mid = 0x95, 238 .reqs = {0, 1, 2, 3}, 239 .direct = EFX_DIR_IN, 240 .params = 3, 241 .def_vals = {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000} 242 }, 243 { .name = "Voice Focus", 244 .nid = VOICE_FOCUS, 245 .mid = 0x95, 246 .reqs = {6, 7, 8, 9}, 247 .direct = EFX_DIR_IN, 248 .params = 3, 249 .def_vals = {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000} 250 }, 251 { .name = "Mic SVM", 252 .nid = MIC_SVM, 253 .mid = 0x95, 254 .reqs = {44, 45}, 255 .direct = EFX_DIR_IN, 256 .params = 1, 257 .def_vals = {0x00000000, 0x3F3D70A4} 258 }, 259 { .name = "Noise Reduction", 260 .nid = NOISE_REDUCTION, 261 .mid = 0x95, 262 .reqs = {4, 5}, 263 .direct = EFX_DIR_IN, 264 .params = 1, 265 .def_vals = {0x3F800000, 0x3F000000} 266 }, 267 { .name = "VoiceFX", 268 .nid = VOICEFX, 269 .mid = 0x95, 270 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18}, 271 .direct = EFX_DIR_IN, 272 .params = 8, 273 .def_vals = {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000, 274 0x3F800000, 0x3F800000, 0x3F800000, 0x00000000, 275 0x00000000} 276 } 277 }; 278 279 /* Tuning controls */ 280 #ifdef ENABLE_TUNING_CONTROLS 281 282 enum { 283 #define TUNING_CTL_START_NID 0xC0 284 WEDGE_ANGLE = TUNING_CTL_START_NID, 285 SVM_LEVEL, 286 EQUALIZER_BAND_0, 287 EQUALIZER_BAND_1, 288 EQUALIZER_BAND_2, 289 EQUALIZER_BAND_3, 290 EQUALIZER_BAND_4, 291 EQUALIZER_BAND_5, 292 EQUALIZER_BAND_6, 293 EQUALIZER_BAND_7, 294 EQUALIZER_BAND_8, 295 EQUALIZER_BAND_9, 296 TUNING_CTL_END_NID 297 #define TUNING_CTLS_COUNT (TUNING_CTL_END_NID - TUNING_CTL_START_NID) 298 }; 299 300 struct ct_tuning_ctl { 301 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 302 hda_nid_t parent_nid; 303 hda_nid_t nid; 304 int mid; /*effect module ID*/ 305 int req; /*effect module request*/ 306 int direct; /* 0:output; 1:input*/ 307 unsigned int def_val;/*effect default values*/ 308 }; 309 310 static const struct ct_tuning_ctl ca0132_tuning_ctls[] = { 311 { .name = "Wedge Angle", 312 .parent_nid = VOICE_FOCUS, 313 .nid = WEDGE_ANGLE, 314 .mid = 0x95, 315 .req = 8, 316 .direct = EFX_DIR_IN, 317 .def_val = 0x41F00000 318 }, 319 { .name = "SVM Level", 320 .parent_nid = MIC_SVM, 321 .nid = SVM_LEVEL, 322 .mid = 0x95, 323 .req = 45, 324 .direct = EFX_DIR_IN, 325 .def_val = 0x3F3D70A4 326 }, 327 { .name = "EQ Band0", 328 .parent_nid = EQUALIZER, 329 .nid = EQUALIZER_BAND_0, 330 .mid = 0x96, 331 .req = 11, 332 .direct = EFX_DIR_OUT, 333 .def_val = 0x00000000 334 }, 335 { .name = "EQ Band1", 336 .parent_nid = EQUALIZER, 337 .nid = EQUALIZER_BAND_1, 338 .mid = 0x96, 339 .req = 12, 340 .direct = EFX_DIR_OUT, 341 .def_val = 0x00000000 342 }, 343 { .name = "EQ Band2", 344 .parent_nid = EQUALIZER, 345 .nid = EQUALIZER_BAND_2, 346 .mid = 0x96, 347 .req = 13, 348 .direct = EFX_DIR_OUT, 349 .def_val = 0x00000000 350 }, 351 { .name = "EQ Band3", 352 .parent_nid = EQUALIZER, 353 .nid = EQUALIZER_BAND_3, 354 .mid = 0x96, 355 .req = 14, 356 .direct = EFX_DIR_OUT, 357 .def_val = 0x00000000 358 }, 359 { .name = "EQ Band4", 360 .parent_nid = EQUALIZER, 361 .nid = EQUALIZER_BAND_4, 362 .mid = 0x96, 363 .req = 15, 364 .direct = EFX_DIR_OUT, 365 .def_val = 0x00000000 366 }, 367 { .name = "EQ Band5", 368 .parent_nid = EQUALIZER, 369 .nid = EQUALIZER_BAND_5, 370 .mid = 0x96, 371 .req = 16, 372 .direct = EFX_DIR_OUT, 373 .def_val = 0x00000000 374 }, 375 { .name = "EQ Band6", 376 .parent_nid = EQUALIZER, 377 .nid = EQUALIZER_BAND_6, 378 .mid = 0x96, 379 .req = 17, 380 .direct = EFX_DIR_OUT, 381 .def_val = 0x00000000 382 }, 383 { .name = "EQ Band7", 384 .parent_nid = EQUALIZER, 385 .nid = EQUALIZER_BAND_7, 386 .mid = 0x96, 387 .req = 18, 388 .direct = EFX_DIR_OUT, 389 .def_val = 0x00000000 390 }, 391 { .name = "EQ Band8", 392 .parent_nid = EQUALIZER, 393 .nid = EQUALIZER_BAND_8, 394 .mid = 0x96, 395 .req = 19, 396 .direct = EFX_DIR_OUT, 397 .def_val = 0x00000000 398 }, 399 { .name = "EQ Band9", 400 .parent_nid = EQUALIZER, 401 .nid = EQUALIZER_BAND_9, 402 .mid = 0x96, 403 .req = 20, 404 .direct = EFX_DIR_OUT, 405 .def_val = 0x00000000 406 } 407 }; 408 #endif 409 410 /* Voice FX Presets */ 411 #define VOICEFX_MAX_PARAM_COUNT 9 412 413 struct ct_voicefx { 414 char *name; 415 hda_nid_t nid; 416 int mid; 417 int reqs[VOICEFX_MAX_PARAM_COUNT]; /*effect module request*/ 418 }; 419 420 struct ct_voicefx_preset { 421 char *name; /*preset name*/ 422 unsigned int vals[VOICEFX_MAX_PARAM_COUNT]; 423 }; 424 425 static const struct ct_voicefx ca0132_voicefx = { 426 .name = "VoiceFX Capture Switch", 427 .nid = VOICEFX, 428 .mid = 0x95, 429 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18} 430 }; 431 432 static const struct ct_voicefx_preset ca0132_voicefx_presets[] = { 433 { .name = "Neutral", 434 .vals = { 0x00000000, 0x43C80000, 0x44AF0000, 435 0x44FA0000, 0x3F800000, 0x3F800000, 436 0x3F800000, 0x00000000, 0x00000000 } 437 }, 438 { .name = "Female2Male", 439 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 440 0x44FA0000, 0x3F19999A, 0x3F866666, 441 0x3F800000, 0x00000000, 0x00000000 } 442 }, 443 { .name = "Male2Female", 444 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 445 0x450AC000, 0x4017AE14, 0x3F6B851F, 446 0x3F800000, 0x00000000, 0x00000000 } 447 }, 448 { .name = "ScrappyKid", 449 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 450 0x44FA0000, 0x40400000, 0x3F28F5C3, 451 0x3F800000, 0x00000000, 0x00000000 } 452 }, 453 { .name = "Elderly", 454 .vals = { 0x3F800000, 0x44324000, 0x44BB8000, 455 0x44E10000, 0x3FB33333, 0x3FB9999A, 456 0x3F800000, 0x3E3A2E43, 0x00000000 } 457 }, 458 { .name = "Orc", 459 .vals = { 0x3F800000, 0x43EA0000, 0x44A52000, 460 0x45098000, 0x3F266666, 0x3FC00000, 461 0x3F800000, 0x00000000, 0x00000000 } 462 }, 463 { .name = "Elf", 464 .vals = { 0x3F800000, 0x43C70000, 0x44AE6000, 465 0x45193000, 0x3F8E147B, 0x3F75C28F, 466 0x3F800000, 0x00000000, 0x00000000 } 467 }, 468 { .name = "Dwarf", 469 .vals = { 0x3F800000, 0x43930000, 0x44BEE000, 470 0x45007000, 0x3F451EB8, 0x3F7851EC, 471 0x3F800000, 0x00000000, 0x00000000 } 472 }, 473 { .name = "AlienBrute", 474 .vals = { 0x3F800000, 0x43BFC5AC, 0x44B28FDF, 475 0x451F6000, 0x3F266666, 0x3FA7D945, 476 0x3F800000, 0x3CF5C28F, 0x00000000 } 477 }, 478 { .name = "Robot", 479 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 480 0x44FA0000, 0x3FB2718B, 0x3F800000, 481 0xBC07010E, 0x00000000, 0x00000000 } 482 }, 483 { .name = "Marine", 484 .vals = { 0x3F800000, 0x43C20000, 0x44906000, 485 0x44E70000, 0x3F4CCCCD, 0x3F8A3D71, 486 0x3F0A3D71, 0x00000000, 0x00000000 } 487 }, 488 { .name = "Emo", 489 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 490 0x44FA0000, 0x3F800000, 0x3F800000, 491 0x3E4CCCCD, 0x00000000, 0x00000000 } 492 }, 493 { .name = "DeepVoice", 494 .vals = { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF, 495 0x44FFC000, 0x3EDBB56F, 0x3F99C4CA, 496 0x3F800000, 0x00000000, 0x00000000 } 497 }, 498 { .name = "Munchkin", 499 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 500 0x44FA0000, 0x3F800000, 0x3F1A043C, 501 0x3F800000, 0x00000000, 0x00000000 } 502 } 503 }; 504 505 /* ca0132 EQ presets, taken from Windows Sound Blaster Z Driver */ 506 507 #define EQ_PRESET_MAX_PARAM_COUNT 11 508 509 struct ct_eq { 510 char *name; 511 hda_nid_t nid; 512 int mid; 513 int reqs[EQ_PRESET_MAX_PARAM_COUNT]; /*effect module request*/ 514 }; 515 516 struct ct_eq_preset { 517 char *name; /*preset name*/ 518 unsigned int vals[EQ_PRESET_MAX_PARAM_COUNT]; 519 }; 520 521 static const struct ct_eq ca0132_alt_eq_enum = { 522 .name = "FX: Equalizer Preset Switch", 523 .nid = EQ_PRESET_ENUM, 524 .mid = 0x96, 525 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20} 526 }; 527 528 529 static const struct ct_eq_preset ca0132_alt_eq_presets[] = { 530 { .name = "Flat", 531 .vals = { 0x00000000, 0x00000000, 0x00000000, 532 0x00000000, 0x00000000, 0x00000000, 533 0x00000000, 0x00000000, 0x00000000, 534 0x00000000, 0x00000000 } 535 }, 536 { .name = "Acoustic", 537 .vals = { 0x00000000, 0x00000000, 0x3F8CCCCD, 538 0x40000000, 0x00000000, 0x00000000, 539 0x00000000, 0x00000000, 0x40000000, 540 0x40000000, 0x40000000 } 541 }, 542 { .name = "Classical", 543 .vals = { 0x00000000, 0x00000000, 0x40C00000, 544 0x40C00000, 0x40466666, 0x00000000, 545 0x00000000, 0x00000000, 0x00000000, 546 0x40466666, 0x40466666 } 547 }, 548 { .name = "Country", 549 .vals = { 0x00000000, 0xBF99999A, 0x00000000, 550 0x3FA66666, 0x3FA66666, 0x3F8CCCCD, 551 0x00000000, 0x00000000, 0x40000000, 552 0x40466666, 0x40800000 } 553 }, 554 { .name = "Dance", 555 .vals = { 0x00000000, 0xBF99999A, 0x40000000, 556 0x40466666, 0x40866666, 0xBF99999A, 557 0xBF99999A, 0x00000000, 0x00000000, 558 0x40800000, 0x40800000 } 559 }, 560 { .name = "Jazz", 561 .vals = { 0x00000000, 0x00000000, 0x00000000, 562 0x3F8CCCCD, 0x40800000, 0x40800000, 563 0x40800000, 0x00000000, 0x3F8CCCCD, 564 0x40466666, 0x40466666 } 565 }, 566 { .name = "New Age", 567 .vals = { 0x00000000, 0x00000000, 0x40000000, 568 0x40000000, 0x00000000, 0x00000000, 569 0x00000000, 0x3F8CCCCD, 0x40000000, 570 0x40000000, 0x40000000 } 571 }, 572 { .name = "Pop", 573 .vals = { 0x00000000, 0xBFCCCCCD, 0x00000000, 574 0x40000000, 0x40000000, 0x00000000, 575 0xBF99999A, 0xBF99999A, 0x00000000, 576 0x40466666, 0x40C00000 } 577 }, 578 { .name = "Rock", 579 .vals = { 0x00000000, 0xBF99999A, 0xBF99999A, 580 0x3F8CCCCD, 0x40000000, 0xBF99999A, 581 0xBF99999A, 0x00000000, 0x00000000, 582 0x40800000, 0x40800000 } 583 }, 584 { .name = "Vocal", 585 .vals = { 0x00000000, 0xC0000000, 0xBF99999A, 586 0xBF99999A, 0x00000000, 0x40466666, 587 0x40800000, 0x40466666, 0x00000000, 588 0x00000000, 0x3F8CCCCD } 589 } 590 }; 591 592 /* DSP command sequences for ca0132_alt_select_out */ 593 #define ALT_OUT_SET_MAX_COMMANDS 9 /* Max number of commands in sequence */ 594 struct ca0132_alt_out_set { 595 char *name; /*preset name*/ 596 unsigned char commands; 597 unsigned int mids[ALT_OUT_SET_MAX_COMMANDS]; 598 unsigned int reqs[ALT_OUT_SET_MAX_COMMANDS]; 599 unsigned int vals[ALT_OUT_SET_MAX_COMMANDS]; 600 }; 601 602 static const struct ca0132_alt_out_set alt_out_presets[] = { 603 { .name = "Line Out", 604 .commands = 7, 605 .mids = { 0x96, 0x96, 0x96, 0x8F, 606 0x96, 0x96, 0x96 }, 607 .reqs = { 0x19, 0x17, 0x18, 0x01, 608 0x1F, 0x15, 0x3A }, 609 .vals = { 0x3F000000, 0x42A00000, 0x00000000, 610 0x00000000, 0x00000000, 0x00000000, 611 0x00000000 } 612 }, 613 { .name = "Headphone", 614 .commands = 7, 615 .mids = { 0x96, 0x96, 0x96, 0x8F, 616 0x96, 0x96, 0x96 }, 617 .reqs = { 0x19, 0x17, 0x18, 0x01, 618 0x1F, 0x15, 0x3A }, 619 .vals = { 0x3F000000, 0x42A00000, 0x00000000, 620 0x00000000, 0x00000000, 0x00000000, 621 0x00000000 } 622 }, 623 { .name = "Surround", 624 .commands = 8, 625 .mids = { 0x96, 0x8F, 0x96, 0x96, 626 0x96, 0x96, 0x96, 0x96 }, 627 .reqs = { 0x18, 0x01, 0x1F, 0x15, 628 0x3A, 0x1A, 0x1B, 0x1C }, 629 .vals = { 0x00000000, 0x00000000, 0x00000000, 630 0x00000000, 0x00000000, 0x00000000, 631 0x00000000, 0x00000000 } 632 } 633 }; 634 635 /* 636 * DSP volume setting structs. Req 1 is left volume, req 2 is right volume, 637 * and I don't know what the third req is, but it's always zero. I assume it's 638 * some sort of update or set command to tell the DSP there's new volume info. 639 */ 640 #define DSP_VOL_OUT 0 641 #define DSP_VOL_IN 1 642 643 struct ct_dsp_volume_ctl { 644 hda_nid_t vnid; 645 int mid; /* module ID*/ 646 unsigned int reqs[3]; /* scp req ID */ 647 }; 648 649 static const struct ct_dsp_volume_ctl ca0132_alt_vol_ctls[] = { 650 { .vnid = VNID_SPK, 651 .mid = 0x32, 652 .reqs = {3, 4, 2} 653 }, 654 { .vnid = VNID_MIC, 655 .mid = 0x37, 656 .reqs = {2, 3, 1} 657 } 658 }; 659 660 /* Values for ca0113_mmio_command_set for selecting output. */ 661 #define AE5_CA0113_OUT_SET_COMMANDS 6 662 struct ae5_ca0113_output_set { 663 unsigned int group[AE5_CA0113_OUT_SET_COMMANDS]; 664 unsigned int target[AE5_CA0113_OUT_SET_COMMANDS]; 665 unsigned int vals[AE5_CA0113_OUT_SET_COMMANDS]; 666 }; 667 668 static const struct ae5_ca0113_output_set ae5_ca0113_output_presets[] = { 669 { .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 }, 670 .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 }, 671 .vals = { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f } 672 }, 673 { .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 }, 674 .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 }, 675 .vals = { 0x3f, 0x3f, 0x00, 0x00, 0x00, 0x00 } 676 }, 677 { .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 }, 678 .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 }, 679 .vals = { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f } 680 } 681 }; 682 683 /* ae5 ca0113 command sequences to set headphone gain levels. */ 684 #define AE5_HEADPHONE_GAIN_PRESET_MAX_COMMANDS 4 685 struct ae5_headphone_gain_set { 686 char *name; 687 unsigned int vals[AE5_HEADPHONE_GAIN_PRESET_MAX_COMMANDS]; 688 }; 689 690 static const struct ae5_headphone_gain_set ae5_headphone_gain_presets[] = { 691 { .name = "Low (16-31", 692 .vals = { 0xff, 0x2c, 0xf5, 0x32 } 693 }, 694 { .name = "Medium (32-149", 695 .vals = { 0x38, 0xa8, 0x3e, 0x4c } 696 }, 697 { .name = "High (150-600", 698 .vals = { 0xff, 0xff, 0xff, 0x7f } 699 } 700 }; 701 702 struct ae5_filter_set { 703 char *name; 704 unsigned int val; 705 }; 706 707 static const struct ae5_filter_set ae5_filter_presets[] = { 708 { .name = "Slow Roll Off", 709 .val = 0xa0 710 }, 711 { .name = "Minimum Phase", 712 .val = 0xc0 713 }, 714 { .name = "Fast Roll Off", 715 .val = 0x80 716 } 717 }; 718 719 enum hda_cmd_vendor_io { 720 /* for DspIO node */ 721 VENDOR_DSPIO_SCP_WRITE_DATA_LOW = 0x000, 722 VENDOR_DSPIO_SCP_WRITE_DATA_HIGH = 0x100, 723 724 VENDOR_DSPIO_STATUS = 0xF01, 725 VENDOR_DSPIO_SCP_POST_READ_DATA = 0x702, 726 VENDOR_DSPIO_SCP_READ_DATA = 0xF02, 727 VENDOR_DSPIO_DSP_INIT = 0x703, 728 VENDOR_DSPIO_SCP_POST_COUNT_QUERY = 0x704, 729 VENDOR_DSPIO_SCP_READ_COUNT = 0xF04, 730 731 /* for ChipIO node */ 732 VENDOR_CHIPIO_ADDRESS_LOW = 0x000, 733 VENDOR_CHIPIO_ADDRESS_HIGH = 0x100, 734 VENDOR_CHIPIO_STREAM_FORMAT = 0x200, 735 VENDOR_CHIPIO_DATA_LOW = 0x300, 736 VENDOR_CHIPIO_DATA_HIGH = 0x400, 737 738 VENDOR_CHIPIO_8051_WRITE_DIRECT = 0x500, 739 VENDOR_CHIPIO_8051_READ_DIRECT = 0xD00, 740 741 VENDOR_CHIPIO_GET_PARAMETER = 0xF00, 742 VENDOR_CHIPIO_STATUS = 0xF01, 743 VENDOR_CHIPIO_HIC_POST_READ = 0x702, 744 VENDOR_CHIPIO_HIC_READ_DATA = 0xF03, 745 746 VENDOR_CHIPIO_8051_DATA_WRITE = 0x707, 747 VENDOR_CHIPIO_8051_DATA_READ = 0xF07, 748 VENDOR_CHIPIO_8051_PMEM_READ = 0xF08, 749 VENDOR_CHIPIO_8051_IRAM_WRITE = 0x709, 750 VENDOR_CHIPIO_8051_IRAM_READ = 0xF09, 751 752 VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE = 0x70A, 753 VENDOR_CHIPIO_CT_EXTENSIONS_GET = 0xF0A, 754 755 VENDOR_CHIPIO_PLL_PMU_WRITE = 0x70C, 756 VENDOR_CHIPIO_PLL_PMU_READ = 0xF0C, 757 VENDOR_CHIPIO_8051_ADDRESS_LOW = 0x70D, 758 VENDOR_CHIPIO_8051_ADDRESS_HIGH = 0x70E, 759 VENDOR_CHIPIO_FLAG_SET = 0x70F, 760 VENDOR_CHIPIO_FLAGS_GET = 0xF0F, 761 VENDOR_CHIPIO_PARAM_SET = 0x710, 762 VENDOR_CHIPIO_PARAM_GET = 0xF10, 763 764 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET = 0x711, 765 VENDOR_CHIPIO_PORT_ALLOC_SET = 0x712, 766 VENDOR_CHIPIO_PORT_ALLOC_GET = 0xF12, 767 VENDOR_CHIPIO_PORT_FREE_SET = 0x713, 768 769 VENDOR_CHIPIO_PARAM_EX_ID_GET = 0xF17, 770 VENDOR_CHIPIO_PARAM_EX_ID_SET = 0x717, 771 VENDOR_CHIPIO_PARAM_EX_VALUE_GET = 0xF18, 772 VENDOR_CHIPIO_PARAM_EX_VALUE_SET = 0x718, 773 774 VENDOR_CHIPIO_DMIC_CTL_SET = 0x788, 775 VENDOR_CHIPIO_DMIC_CTL_GET = 0xF88, 776 VENDOR_CHIPIO_DMIC_PIN_SET = 0x789, 777 VENDOR_CHIPIO_DMIC_PIN_GET = 0xF89, 778 VENDOR_CHIPIO_DMIC_MCLK_SET = 0x78A, 779 VENDOR_CHIPIO_DMIC_MCLK_GET = 0xF8A, 780 781 VENDOR_CHIPIO_EAPD_SEL_SET = 0x78D 782 }; 783 784 /* 785 * Control flag IDs 786 */ 787 enum control_flag_id { 788 /* Connection manager stream setup is bypassed/enabled */ 789 CONTROL_FLAG_C_MGR = 0, 790 /* DSP DMA is bypassed/enabled */ 791 CONTROL_FLAG_DMA = 1, 792 /* 8051 'idle' mode is disabled/enabled */ 793 CONTROL_FLAG_IDLE_ENABLE = 2, 794 /* Tracker for the SPDIF-in path is bypassed/enabled */ 795 CONTROL_FLAG_TRACKER = 3, 796 /* DigitalOut to Spdif2Out connection is disabled/enabled */ 797 CONTROL_FLAG_SPDIF2OUT = 4, 798 /* Digital Microphone is disabled/enabled */ 799 CONTROL_FLAG_DMIC = 5, 800 /* ADC_B rate is 48 kHz/96 kHz */ 801 CONTROL_FLAG_ADC_B_96KHZ = 6, 802 /* ADC_C rate is 48 kHz/96 kHz */ 803 CONTROL_FLAG_ADC_C_96KHZ = 7, 804 /* DAC rate is 48 kHz/96 kHz (affects all DACs) */ 805 CONTROL_FLAG_DAC_96KHZ = 8, 806 /* DSP rate is 48 kHz/96 kHz */ 807 CONTROL_FLAG_DSP_96KHZ = 9, 808 /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */ 809 CONTROL_FLAG_SRC_CLOCK_196MHZ = 10, 810 /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */ 811 CONTROL_FLAG_SRC_RATE_96KHZ = 11, 812 /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */ 813 CONTROL_FLAG_DECODE_LOOP = 12, 814 /* De-emphasis filter on DAC-1 disabled/enabled */ 815 CONTROL_FLAG_DAC1_DEEMPHASIS = 13, 816 /* De-emphasis filter on DAC-2 disabled/enabled */ 817 CONTROL_FLAG_DAC2_DEEMPHASIS = 14, 818 /* De-emphasis filter on DAC-3 disabled/enabled */ 819 CONTROL_FLAG_DAC3_DEEMPHASIS = 15, 820 /* High-pass filter on ADC_B disabled/enabled */ 821 CONTROL_FLAG_ADC_B_HIGH_PASS = 16, 822 /* High-pass filter on ADC_C disabled/enabled */ 823 CONTROL_FLAG_ADC_C_HIGH_PASS = 17, 824 /* Common mode on Port_A disabled/enabled */ 825 CONTROL_FLAG_PORT_A_COMMON_MODE = 18, 826 /* Common mode on Port_D disabled/enabled */ 827 CONTROL_FLAG_PORT_D_COMMON_MODE = 19, 828 /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */ 829 CONTROL_FLAG_PORT_A_10KOHM_LOAD = 20, 830 /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */ 831 CONTROL_FLAG_PORT_D_10KOHM_LOAD = 21, 832 /* ASI rate is 48kHz/96kHz */ 833 CONTROL_FLAG_ASI_96KHZ = 22, 834 /* DAC power settings able to control attached ports no/yes */ 835 CONTROL_FLAG_DACS_CONTROL_PORTS = 23, 836 /* Clock Stop OK reporting is disabled/enabled */ 837 CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24, 838 /* Number of control flags */ 839 CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1) 840 }; 841 842 /* 843 * Control parameter IDs 844 */ 845 enum control_param_id { 846 /* 0: None, 1: Mic1In*/ 847 CONTROL_PARAM_VIP_SOURCE = 1, 848 /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */ 849 CONTROL_PARAM_SPDIF1_SOURCE = 2, 850 /* Port A output stage gain setting to use when 16 Ohm output 851 * impedance is selected*/ 852 CONTROL_PARAM_PORTA_160OHM_GAIN = 8, 853 /* Port D output stage gain setting to use when 16 Ohm output 854 * impedance is selected*/ 855 CONTROL_PARAM_PORTD_160OHM_GAIN = 10, 856 857 /* 858 * This control param name was found in the 8051 memory, and makes 859 * sense given the fact the AE-5 uses it and has the ASI flag set. 860 */ 861 CONTROL_PARAM_ASI = 23, 862 863 /* Stream Control */ 864 865 /* Select stream with the given ID */ 866 CONTROL_PARAM_STREAM_ID = 24, 867 /* Source connection point for the selected stream */ 868 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25, 869 /* Destination connection point for the selected stream */ 870 CONTROL_PARAM_STREAM_DEST_CONN_POINT = 26, 871 /* Number of audio channels in the selected stream */ 872 CONTROL_PARAM_STREAMS_CHANNELS = 27, 873 /*Enable control for the selected stream */ 874 CONTROL_PARAM_STREAM_CONTROL = 28, 875 876 /* Connection Point Control */ 877 878 /* Select connection point with the given ID */ 879 CONTROL_PARAM_CONN_POINT_ID = 29, 880 /* Connection point sample rate */ 881 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE = 30, 882 883 /* Node Control */ 884 885 /* Select HDA node with the given ID */ 886 CONTROL_PARAM_NODE_ID = 31 887 }; 888 889 /* 890 * Dsp Io Status codes 891 */ 892 enum hda_vendor_status_dspio { 893 /* Success */ 894 VENDOR_STATUS_DSPIO_OK = 0x00, 895 /* Busy, unable to accept new command, the host must retry */ 896 VENDOR_STATUS_DSPIO_BUSY = 0x01, 897 /* SCP command queue is full */ 898 VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL = 0x02, 899 /* SCP response queue is empty */ 900 VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03 901 }; 902 903 /* 904 * Chip Io Status codes 905 */ 906 enum hda_vendor_status_chipio { 907 /* Success */ 908 VENDOR_STATUS_CHIPIO_OK = 0x00, 909 /* Busy, unable to accept new command, the host must retry */ 910 VENDOR_STATUS_CHIPIO_BUSY = 0x01 911 }; 912 913 /* 914 * CA0132 sample rate 915 */ 916 enum ca0132_sample_rate { 917 SR_6_000 = 0x00, 918 SR_8_000 = 0x01, 919 SR_9_600 = 0x02, 920 SR_11_025 = 0x03, 921 SR_16_000 = 0x04, 922 SR_22_050 = 0x05, 923 SR_24_000 = 0x06, 924 SR_32_000 = 0x07, 925 SR_44_100 = 0x08, 926 SR_48_000 = 0x09, 927 SR_88_200 = 0x0A, 928 SR_96_000 = 0x0B, 929 SR_144_000 = 0x0C, 930 SR_176_400 = 0x0D, 931 SR_192_000 = 0x0E, 932 SR_384_000 = 0x0F, 933 934 SR_COUNT = 0x10, 935 936 SR_RATE_UNKNOWN = 0x1F 937 }; 938 939 enum dsp_download_state { 940 DSP_DOWNLOAD_FAILED = -1, 941 DSP_DOWNLOAD_INIT = 0, 942 DSP_DOWNLOADING = 1, 943 DSP_DOWNLOADED = 2 944 }; 945 946 /* retrieve parameters from hda format */ 947 #define get_hdafmt_chs(fmt) (fmt & 0xf) 948 #define get_hdafmt_bits(fmt) ((fmt >> 4) & 0x7) 949 #define get_hdafmt_rate(fmt) ((fmt >> 8) & 0x7f) 950 #define get_hdafmt_type(fmt) ((fmt >> 15) & 0x1) 951 952 /* 953 * CA0132 specific 954 */ 955 956 struct ca0132_spec { 957 const struct snd_kcontrol_new *mixers[5]; 958 unsigned int num_mixers; 959 const struct hda_verb *base_init_verbs; 960 const struct hda_verb *base_exit_verbs; 961 const struct hda_verb *chip_init_verbs; 962 const struct hda_verb *desktop_init_verbs; 963 struct hda_verb *spec_init_verbs; 964 struct auto_pin_cfg autocfg; 965 966 /* Nodes configurations */ 967 struct hda_multi_out multiout; 968 hda_nid_t out_pins[AUTO_CFG_MAX_OUTS]; 969 hda_nid_t dacs[AUTO_CFG_MAX_OUTS]; 970 unsigned int num_outputs; 971 hda_nid_t input_pins[AUTO_PIN_LAST]; 972 hda_nid_t adcs[AUTO_PIN_LAST]; 973 hda_nid_t dig_out; 974 hda_nid_t dig_in; 975 unsigned int num_inputs; 976 hda_nid_t shared_mic_nid; 977 hda_nid_t shared_out_nid; 978 hda_nid_t unsol_tag_hp; 979 hda_nid_t unsol_tag_front_hp; /* for desktop ca0132 codecs */ 980 hda_nid_t unsol_tag_amic1; 981 982 /* chip access */ 983 struct mutex chipio_mutex; /* chip access mutex */ 984 u32 curr_chip_addx; 985 986 /* DSP download related */ 987 enum dsp_download_state dsp_state; 988 unsigned int dsp_stream_id; 989 unsigned int wait_scp; 990 unsigned int wait_scp_header; 991 unsigned int wait_num_data; 992 unsigned int scp_resp_header; 993 unsigned int scp_resp_data[4]; 994 unsigned int scp_resp_count; 995 bool startup_check_entered; 996 bool dsp_reload; 997 998 /* mixer and effects related */ 999 unsigned char dmic_ctl; 1000 int cur_out_type; 1001 int cur_mic_type; 1002 long vnode_lvol[VNODES_COUNT]; 1003 long vnode_rvol[VNODES_COUNT]; 1004 long vnode_lswitch[VNODES_COUNT]; 1005 long vnode_rswitch[VNODES_COUNT]; 1006 long effects_switch[EFFECTS_COUNT]; 1007 long voicefx_val; 1008 long cur_mic_boost; 1009 /* ca0132_alt control related values */ 1010 unsigned char in_enum_val; 1011 unsigned char out_enum_val; 1012 unsigned char mic_boost_enum_val; 1013 unsigned char smart_volume_setting; 1014 long fx_ctl_val[EFFECT_LEVEL_SLIDERS]; 1015 long xbass_xover_freq; 1016 long eq_preset_val; 1017 unsigned int tlv[4]; 1018 struct hda_vmaster_mute_hook vmaster_mute; 1019 /* AE-5 Control values */ 1020 unsigned char ae5_headphone_gain_val; 1021 unsigned char ae5_filter_val; 1022 /* ZxR Control Values */ 1023 unsigned char zxr_gain_set; 1024 1025 struct hda_codec *codec; 1026 struct delayed_work unsol_hp_work; 1027 int quirk; 1028 1029 #ifdef ENABLE_TUNING_CONTROLS 1030 long cur_ctl_vals[TUNING_CTLS_COUNT]; 1031 #endif 1032 /* 1033 * The Recon3D, Sound Blaster Z, Sound Blaster ZxR, and Sound Blaster 1034 * AE-5 all use PCI region 2 to toggle GPIO and other currently unknown 1035 * things. 1036 */ 1037 bool use_pci_mmio; 1038 void __iomem *mem_base; 1039 1040 /* 1041 * Whether or not to use the alt functions like alt_select_out, 1042 * alt_select_in, etc. Only used on desktop codecs for now, because of 1043 * surround sound support. 1044 */ 1045 bool use_alt_functions; 1046 1047 /* 1048 * Whether or not to use alt controls: volume effect sliders, EQ 1049 * presets, smart volume presets, and new control names with FX prefix. 1050 * Renames PlayEnhancement and CrystalVoice too. 1051 */ 1052 bool use_alt_controls; 1053 }; 1054 1055 /* 1056 * CA0132 quirks table 1057 */ 1058 enum { 1059 QUIRK_NONE, 1060 QUIRK_ALIENWARE, 1061 QUIRK_ALIENWARE_M17XR4, 1062 QUIRK_SBZ, 1063 QUIRK_ZXR, 1064 QUIRK_ZXR_DBPRO, 1065 QUIRK_R3DI, 1066 QUIRK_R3D, 1067 QUIRK_AE5, 1068 }; 1069 1070 #ifdef CONFIG_PCI 1071 #define ca0132_quirk(spec) ((spec)->quirk) 1072 #define ca0132_use_pci_mmio(spec) ((spec)->use_pci_mmio) 1073 #define ca0132_use_alt_functions(spec) ((spec)->use_alt_functions) 1074 #define ca0132_use_alt_controls(spec) ((spec)->use_alt_controls) 1075 #else 1076 #define ca0132_quirk(spec) ({ (void)(spec); QUIRK_NONE; }) 1077 #define ca0132_use_alt_functions(spec) ({ (void)(spec); false; }) 1078 #define ca0132_use_pci_mmio(spec) ({ (void)(spec); false; }) 1079 #define ca0132_use_alt_controls(spec) ({ (void)(spec); false; }) 1080 #endif 1081 1082 static const struct hda_pintbl alienware_pincfgs[] = { 1083 { 0x0b, 0x90170110 }, /* Builtin Speaker */ 1084 { 0x0c, 0x411111f0 }, /* N/A */ 1085 { 0x0d, 0x411111f0 }, /* N/A */ 1086 { 0x0e, 0x411111f0 }, /* N/A */ 1087 { 0x0f, 0x0321101f }, /* HP */ 1088 { 0x10, 0x411111f0 }, /* Headset? disabled for now */ 1089 { 0x11, 0x03a11021 }, /* Mic */ 1090 { 0x12, 0xd5a30140 }, /* Builtin Mic */ 1091 { 0x13, 0x411111f0 }, /* N/A */ 1092 { 0x18, 0x411111f0 }, /* N/A */ 1093 {} 1094 }; 1095 1096 /* Sound Blaster Z pin configs taken from Windows Driver */ 1097 static const struct hda_pintbl sbz_pincfgs[] = { 1098 { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */ 1099 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */ 1100 { 0x0d, 0x014510f0 }, /* Digital Out */ 1101 { 0x0e, 0x01c510f0 }, /* SPDIF In */ 1102 { 0x0f, 0x0221701f }, /* Port A -- BackPanel HP */ 1103 { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */ 1104 { 0x11, 0x01017014 }, /* Port B -- LineMicIn2 / Rear L/R */ 1105 { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */ 1106 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1107 { 0x18, 0x50d000f0 }, /* N/A */ 1108 {} 1109 }; 1110 1111 /* Sound Blaster ZxR pin configs taken from Windows Driver */ 1112 static const struct hda_pintbl zxr_pincfgs[] = { 1113 { 0x0b, 0x01047110 }, /* Port G -- Lineout FRONT L/R */ 1114 { 0x0c, 0x414510f0 }, /* SPDIF Out 1 - Disabled*/ 1115 { 0x0d, 0x014510f0 }, /* Digital Out */ 1116 { 0x0e, 0x41c520f0 }, /* SPDIF In - Disabled*/ 1117 { 0x0f, 0x0122711f }, /* Port A -- BackPanel HP */ 1118 { 0x10, 0x01017111 }, /* Port D -- Center/LFE */ 1119 { 0x11, 0x01017114 }, /* Port B -- LineMicIn2 / Rear L/R */ 1120 { 0x12, 0x01a271f0 }, /* Port C -- LineIn1 */ 1121 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1122 { 0x18, 0x50d000f0 }, /* N/A */ 1123 {} 1124 }; 1125 1126 /* Recon3D pin configs taken from Windows Driver */ 1127 static const struct hda_pintbl r3d_pincfgs[] = { 1128 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */ 1129 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */ 1130 { 0x0d, 0x014510f0 }, /* Digital Out */ 1131 { 0x0e, 0x01c520f0 }, /* SPDIF In */ 1132 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */ 1133 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */ 1134 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */ 1135 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */ 1136 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1137 { 0x18, 0x50d000f0 }, /* N/A */ 1138 {} 1139 }; 1140 1141 /* Sound Blaster AE-5 pin configs taken from Windows Driver */ 1142 static const struct hda_pintbl ae5_pincfgs[] = { 1143 { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */ 1144 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */ 1145 { 0x0d, 0x014510f0 }, /* Digital Out */ 1146 { 0x0e, 0x01c510f0 }, /* SPDIF In */ 1147 { 0x0f, 0x01017114 }, /* Port A -- Rear L/R. */ 1148 { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */ 1149 { 0x11, 0x01a170ff }, /* Port B -- LineMicIn2 / Rear Headphone */ 1150 { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */ 1151 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1152 { 0x18, 0x50d000f0 }, /* N/A */ 1153 {} 1154 }; 1155 1156 /* Recon3D integrated pin configs taken from Windows Driver */ 1157 static const struct hda_pintbl r3di_pincfgs[] = { 1158 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */ 1159 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */ 1160 { 0x0d, 0x014510f0 }, /* Digital Out */ 1161 { 0x0e, 0x41c520f0 }, /* SPDIF In */ 1162 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */ 1163 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */ 1164 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */ 1165 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */ 1166 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1167 { 0x18, 0x500000f0 }, /* N/A */ 1168 {} 1169 }; 1170 1171 static const struct snd_pci_quirk ca0132_quirks[] = { 1172 SND_PCI_QUIRK(0x1028, 0x057b, "Alienware M17x R4", QUIRK_ALIENWARE_M17XR4), 1173 SND_PCI_QUIRK(0x1028, 0x0685, "Alienware 15 2015", QUIRK_ALIENWARE), 1174 SND_PCI_QUIRK(0x1028, 0x0688, "Alienware 17 2015", QUIRK_ALIENWARE), 1175 SND_PCI_QUIRK(0x1028, 0x0708, "Alienware 15 R2 2016", QUIRK_ALIENWARE), 1176 SND_PCI_QUIRK(0x1102, 0x0010, "Sound Blaster Z", QUIRK_SBZ), 1177 SND_PCI_QUIRK(0x1102, 0x0023, "Sound Blaster Z", QUIRK_SBZ), 1178 SND_PCI_QUIRK(0x1102, 0x0033, "Sound Blaster ZxR", QUIRK_SBZ), 1179 SND_PCI_QUIRK(0x1458, 0xA016, "Recon3Di", QUIRK_R3DI), 1180 SND_PCI_QUIRK(0x1458, 0xA026, "Gigabyte G1.Sniper Z97", QUIRK_R3DI), 1181 SND_PCI_QUIRK(0x1458, 0xA036, "Gigabyte GA-Z170X-Gaming 7", QUIRK_R3DI), 1182 SND_PCI_QUIRK(0x1102, 0x0013, "Recon3D", QUIRK_R3D), 1183 SND_PCI_QUIRK(0x1102, 0x0051, "Sound Blaster AE-5", QUIRK_AE5), 1184 {} 1185 }; 1186 1187 /* 1188 * CA0132 codec access 1189 */ 1190 static unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid, 1191 unsigned int verb, unsigned int parm, unsigned int *res) 1192 { 1193 unsigned int response; 1194 response = snd_hda_codec_read(codec, nid, 0, verb, parm); 1195 *res = response; 1196 1197 return ((response == -1) ? -1 : 0); 1198 } 1199 1200 static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid, 1201 unsigned short converter_format, unsigned int *res) 1202 { 1203 return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT, 1204 converter_format & 0xffff, res); 1205 } 1206 1207 static int codec_set_converter_stream_channel(struct hda_codec *codec, 1208 hda_nid_t nid, unsigned char stream, 1209 unsigned char channel, unsigned int *res) 1210 { 1211 unsigned char converter_stream_channel = 0; 1212 1213 converter_stream_channel = (stream << 4) | (channel & 0x0f); 1214 return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID, 1215 converter_stream_channel, res); 1216 } 1217 1218 /* Chip access helper function */ 1219 static int chipio_send(struct hda_codec *codec, 1220 unsigned int reg, 1221 unsigned int data) 1222 { 1223 unsigned int res; 1224 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 1225 1226 /* send bits of data specified by reg */ 1227 do { 1228 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, 1229 reg, data); 1230 if (res == VENDOR_STATUS_CHIPIO_OK) 1231 return 0; 1232 msleep(20); 1233 } while (time_before(jiffies, timeout)); 1234 1235 return -EIO; 1236 } 1237 1238 /* 1239 * Write chip address through the vendor widget -- NOT protected by the Mutex! 1240 */ 1241 static int chipio_write_address(struct hda_codec *codec, 1242 unsigned int chip_addx) 1243 { 1244 struct ca0132_spec *spec = codec->spec; 1245 int res; 1246 1247 if (spec->curr_chip_addx == chip_addx) 1248 return 0; 1249 1250 /* send low 16 bits of the address */ 1251 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW, 1252 chip_addx & 0xffff); 1253 1254 if (res != -EIO) { 1255 /* send high 16 bits of the address */ 1256 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH, 1257 chip_addx >> 16); 1258 } 1259 1260 spec->curr_chip_addx = (res < 0) ? ~0U : chip_addx; 1261 1262 return res; 1263 } 1264 1265 /* 1266 * Write data through the vendor widget -- NOT protected by the Mutex! 1267 */ 1268 static int chipio_write_data(struct hda_codec *codec, unsigned int data) 1269 { 1270 struct ca0132_spec *spec = codec->spec; 1271 int res; 1272 1273 /* send low 16 bits of the data */ 1274 res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff); 1275 1276 if (res != -EIO) { 1277 /* send high 16 bits of the data */ 1278 res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH, 1279 data >> 16); 1280 } 1281 1282 /*If no error encountered, automatically increment the address 1283 as per chip behaviour*/ 1284 spec->curr_chip_addx = (res != -EIO) ? 1285 (spec->curr_chip_addx + 4) : ~0U; 1286 return res; 1287 } 1288 1289 /* 1290 * Write multiple data through the vendor widget -- NOT protected by the Mutex! 1291 */ 1292 static int chipio_write_data_multiple(struct hda_codec *codec, 1293 const u32 *data, 1294 unsigned int count) 1295 { 1296 int status = 0; 1297 1298 if (data == NULL) { 1299 codec_dbg(codec, "chipio_write_data null ptr\n"); 1300 return -EINVAL; 1301 } 1302 1303 while ((count-- != 0) && (status == 0)) 1304 status = chipio_write_data(codec, *data++); 1305 1306 return status; 1307 } 1308 1309 1310 /* 1311 * Read data through the vendor widget -- NOT protected by the Mutex! 1312 */ 1313 static int chipio_read_data(struct hda_codec *codec, unsigned int *data) 1314 { 1315 struct ca0132_spec *spec = codec->spec; 1316 int res; 1317 1318 /* post read */ 1319 res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0); 1320 1321 if (res != -EIO) { 1322 /* read status */ 1323 res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 1324 } 1325 1326 if (res != -EIO) { 1327 /* read data */ 1328 *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, 1329 VENDOR_CHIPIO_HIC_READ_DATA, 1330 0); 1331 } 1332 1333 /*If no error encountered, automatically increment the address 1334 as per chip behaviour*/ 1335 spec->curr_chip_addx = (res != -EIO) ? 1336 (spec->curr_chip_addx + 4) : ~0U; 1337 return res; 1338 } 1339 1340 /* 1341 * Write given value to the given address through the chip I/O widget. 1342 * protected by the Mutex 1343 */ 1344 static int chipio_write(struct hda_codec *codec, 1345 unsigned int chip_addx, const unsigned int data) 1346 { 1347 struct ca0132_spec *spec = codec->spec; 1348 int err; 1349 1350 mutex_lock(&spec->chipio_mutex); 1351 1352 /* write the address, and if successful proceed to write data */ 1353 err = chipio_write_address(codec, chip_addx); 1354 if (err < 0) 1355 goto exit; 1356 1357 err = chipio_write_data(codec, data); 1358 if (err < 0) 1359 goto exit; 1360 1361 exit: 1362 mutex_unlock(&spec->chipio_mutex); 1363 return err; 1364 } 1365 1366 /* 1367 * Write given value to the given address through the chip I/O widget. 1368 * not protected by the Mutex 1369 */ 1370 static int chipio_write_no_mutex(struct hda_codec *codec, 1371 unsigned int chip_addx, const unsigned int data) 1372 { 1373 int err; 1374 1375 1376 /* write the address, and if successful proceed to write data */ 1377 err = chipio_write_address(codec, chip_addx); 1378 if (err < 0) 1379 goto exit; 1380 1381 err = chipio_write_data(codec, data); 1382 if (err < 0) 1383 goto exit; 1384 1385 exit: 1386 return err; 1387 } 1388 1389 /* 1390 * Write multiple values to the given address through the chip I/O widget. 1391 * protected by the Mutex 1392 */ 1393 static int chipio_write_multiple(struct hda_codec *codec, 1394 u32 chip_addx, 1395 const u32 *data, 1396 unsigned int count) 1397 { 1398 struct ca0132_spec *spec = codec->spec; 1399 int status; 1400 1401 mutex_lock(&spec->chipio_mutex); 1402 status = chipio_write_address(codec, chip_addx); 1403 if (status < 0) 1404 goto error; 1405 1406 status = chipio_write_data_multiple(codec, data, count); 1407 error: 1408 mutex_unlock(&spec->chipio_mutex); 1409 1410 return status; 1411 } 1412 1413 /* 1414 * Read the given address through the chip I/O widget 1415 * protected by the Mutex 1416 */ 1417 static int chipio_read(struct hda_codec *codec, 1418 unsigned int chip_addx, unsigned int *data) 1419 { 1420 struct ca0132_spec *spec = codec->spec; 1421 int err; 1422 1423 mutex_lock(&spec->chipio_mutex); 1424 1425 /* write the address, and if successful proceed to write data */ 1426 err = chipio_write_address(codec, chip_addx); 1427 if (err < 0) 1428 goto exit; 1429 1430 err = chipio_read_data(codec, data); 1431 if (err < 0) 1432 goto exit; 1433 1434 exit: 1435 mutex_unlock(&spec->chipio_mutex); 1436 return err; 1437 } 1438 1439 /* 1440 * Set chip control flags through the chip I/O widget. 1441 */ 1442 static void chipio_set_control_flag(struct hda_codec *codec, 1443 enum control_flag_id flag_id, 1444 bool flag_state) 1445 { 1446 unsigned int val; 1447 unsigned int flag_bit; 1448 1449 flag_bit = (flag_state ? 1 : 0); 1450 val = (flag_bit << 7) | (flag_id); 1451 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1452 VENDOR_CHIPIO_FLAG_SET, val); 1453 } 1454 1455 /* 1456 * Set chip parameters through the chip I/O widget. 1457 */ 1458 static void chipio_set_control_param(struct hda_codec *codec, 1459 enum control_param_id param_id, int param_val) 1460 { 1461 struct ca0132_spec *spec = codec->spec; 1462 int val; 1463 1464 if ((param_id < 32) && (param_val < 8)) { 1465 val = (param_val << 5) | (param_id); 1466 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1467 VENDOR_CHIPIO_PARAM_SET, val); 1468 } else { 1469 mutex_lock(&spec->chipio_mutex); 1470 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) { 1471 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1472 VENDOR_CHIPIO_PARAM_EX_ID_SET, 1473 param_id); 1474 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1475 VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 1476 param_val); 1477 } 1478 mutex_unlock(&spec->chipio_mutex); 1479 } 1480 } 1481 1482 /* 1483 * Set chip parameters through the chip I/O widget. NO MUTEX. 1484 */ 1485 static void chipio_set_control_param_no_mutex(struct hda_codec *codec, 1486 enum control_param_id param_id, int param_val) 1487 { 1488 int val; 1489 1490 if ((param_id < 32) && (param_val < 8)) { 1491 val = (param_val << 5) | (param_id); 1492 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1493 VENDOR_CHIPIO_PARAM_SET, val); 1494 } else { 1495 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) { 1496 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1497 VENDOR_CHIPIO_PARAM_EX_ID_SET, 1498 param_id); 1499 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1500 VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 1501 param_val); 1502 } 1503 } 1504 } 1505 /* 1506 * Connect stream to a source point, and then connect 1507 * that source point to a destination point. 1508 */ 1509 static void chipio_set_stream_source_dest(struct hda_codec *codec, 1510 int streamid, int source_point, int dest_point) 1511 { 1512 chipio_set_control_param_no_mutex(codec, 1513 CONTROL_PARAM_STREAM_ID, streamid); 1514 chipio_set_control_param_no_mutex(codec, 1515 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT, source_point); 1516 chipio_set_control_param_no_mutex(codec, 1517 CONTROL_PARAM_STREAM_DEST_CONN_POINT, dest_point); 1518 } 1519 1520 /* 1521 * Set number of channels in the selected stream. 1522 */ 1523 static void chipio_set_stream_channels(struct hda_codec *codec, 1524 int streamid, unsigned int channels) 1525 { 1526 chipio_set_control_param_no_mutex(codec, 1527 CONTROL_PARAM_STREAM_ID, streamid); 1528 chipio_set_control_param_no_mutex(codec, 1529 CONTROL_PARAM_STREAMS_CHANNELS, channels); 1530 } 1531 1532 /* 1533 * Enable/Disable audio stream. 1534 */ 1535 static void chipio_set_stream_control(struct hda_codec *codec, 1536 int streamid, int enable) 1537 { 1538 chipio_set_control_param_no_mutex(codec, 1539 CONTROL_PARAM_STREAM_ID, streamid); 1540 chipio_set_control_param_no_mutex(codec, 1541 CONTROL_PARAM_STREAM_CONTROL, enable); 1542 } 1543 1544 1545 /* 1546 * Set sampling rate of the connection point. NO MUTEX. 1547 */ 1548 static void chipio_set_conn_rate_no_mutex(struct hda_codec *codec, 1549 int connid, enum ca0132_sample_rate rate) 1550 { 1551 chipio_set_control_param_no_mutex(codec, 1552 CONTROL_PARAM_CONN_POINT_ID, connid); 1553 chipio_set_control_param_no_mutex(codec, 1554 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE, rate); 1555 } 1556 1557 /* 1558 * Set sampling rate of the connection point. 1559 */ 1560 static void chipio_set_conn_rate(struct hda_codec *codec, 1561 int connid, enum ca0132_sample_rate rate) 1562 { 1563 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid); 1564 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE, 1565 rate); 1566 } 1567 1568 /* 1569 * Writes to the 8051's internal address space directly instead of indirectly, 1570 * giving access to the special function registers located at addresses 1571 * 0x80-0xFF. 1572 */ 1573 static void chipio_8051_write_direct(struct hda_codec *codec, 1574 unsigned int addr, unsigned int data) 1575 { 1576 unsigned int verb; 1577 1578 verb = VENDOR_CHIPIO_8051_WRITE_DIRECT | data; 1579 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, verb, addr); 1580 } 1581 1582 /* 1583 * Enable clocks. 1584 */ 1585 static void chipio_enable_clocks(struct hda_codec *codec) 1586 { 1587 struct ca0132_spec *spec = codec->spec; 1588 1589 mutex_lock(&spec->chipio_mutex); 1590 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1591 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0); 1592 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1593 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff); 1594 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1595 VENDOR_CHIPIO_8051_ADDRESS_LOW, 5); 1596 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1597 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x0b); 1598 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1599 VENDOR_CHIPIO_8051_ADDRESS_LOW, 6); 1600 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1601 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff); 1602 mutex_unlock(&spec->chipio_mutex); 1603 } 1604 1605 /* 1606 * CA0132 DSP IO stuffs 1607 */ 1608 static int dspio_send(struct hda_codec *codec, unsigned int reg, 1609 unsigned int data) 1610 { 1611 int res; 1612 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 1613 1614 /* send bits of data specified by reg to dsp */ 1615 do { 1616 res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data); 1617 if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY)) 1618 return res; 1619 msleep(20); 1620 } while (time_before(jiffies, timeout)); 1621 1622 return -EIO; 1623 } 1624 1625 /* 1626 * Wait for DSP to be ready for commands 1627 */ 1628 static void dspio_write_wait(struct hda_codec *codec) 1629 { 1630 int status; 1631 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 1632 1633 do { 1634 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, 1635 VENDOR_DSPIO_STATUS, 0); 1636 if ((status == VENDOR_STATUS_DSPIO_OK) || 1637 (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY)) 1638 break; 1639 msleep(1); 1640 } while (time_before(jiffies, timeout)); 1641 } 1642 1643 /* 1644 * Write SCP data to DSP 1645 */ 1646 static int dspio_write(struct hda_codec *codec, unsigned int scp_data) 1647 { 1648 struct ca0132_spec *spec = codec->spec; 1649 int status; 1650 1651 dspio_write_wait(codec); 1652 1653 mutex_lock(&spec->chipio_mutex); 1654 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW, 1655 scp_data & 0xffff); 1656 if (status < 0) 1657 goto error; 1658 1659 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH, 1660 scp_data >> 16); 1661 if (status < 0) 1662 goto error; 1663 1664 /* OK, now check if the write itself has executed*/ 1665 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, 1666 VENDOR_DSPIO_STATUS, 0); 1667 error: 1668 mutex_unlock(&spec->chipio_mutex); 1669 1670 return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ? 1671 -EIO : 0; 1672 } 1673 1674 /* 1675 * Write multiple SCP data to DSP 1676 */ 1677 static int dspio_write_multiple(struct hda_codec *codec, 1678 unsigned int *buffer, unsigned int size) 1679 { 1680 int status = 0; 1681 unsigned int count; 1682 1683 if (buffer == NULL) 1684 return -EINVAL; 1685 1686 count = 0; 1687 while (count < size) { 1688 status = dspio_write(codec, *buffer++); 1689 if (status != 0) 1690 break; 1691 count++; 1692 } 1693 1694 return status; 1695 } 1696 1697 static int dspio_read(struct hda_codec *codec, unsigned int *data) 1698 { 1699 int status; 1700 1701 status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0); 1702 if (status == -EIO) 1703 return status; 1704 1705 status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0); 1706 if (status == -EIO || 1707 status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY) 1708 return -EIO; 1709 1710 *data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, 1711 VENDOR_DSPIO_SCP_READ_DATA, 0); 1712 1713 return 0; 1714 } 1715 1716 static int dspio_read_multiple(struct hda_codec *codec, unsigned int *buffer, 1717 unsigned int *buf_size, unsigned int size_count) 1718 { 1719 int status = 0; 1720 unsigned int size = *buf_size; 1721 unsigned int count; 1722 unsigned int skip_count; 1723 unsigned int dummy; 1724 1725 if (buffer == NULL) 1726 return -1; 1727 1728 count = 0; 1729 while (count < size && count < size_count) { 1730 status = dspio_read(codec, buffer++); 1731 if (status != 0) 1732 break; 1733 count++; 1734 } 1735 1736 skip_count = count; 1737 if (status == 0) { 1738 while (skip_count < size) { 1739 status = dspio_read(codec, &dummy); 1740 if (status != 0) 1741 break; 1742 skip_count++; 1743 } 1744 } 1745 *buf_size = count; 1746 1747 return status; 1748 } 1749 1750 /* 1751 * Construct the SCP header using corresponding fields 1752 */ 1753 static inline unsigned int 1754 make_scp_header(unsigned int target_id, unsigned int source_id, 1755 unsigned int get_flag, unsigned int req, 1756 unsigned int device_flag, unsigned int resp_flag, 1757 unsigned int error_flag, unsigned int data_size) 1758 { 1759 unsigned int header = 0; 1760 1761 header = (data_size & 0x1f) << 27; 1762 header |= (error_flag & 0x01) << 26; 1763 header |= (resp_flag & 0x01) << 25; 1764 header |= (device_flag & 0x01) << 24; 1765 header |= (req & 0x7f) << 17; 1766 header |= (get_flag & 0x01) << 16; 1767 header |= (source_id & 0xff) << 8; 1768 header |= target_id & 0xff; 1769 1770 return header; 1771 } 1772 1773 /* 1774 * Extract corresponding fields from SCP header 1775 */ 1776 static inline void 1777 extract_scp_header(unsigned int header, 1778 unsigned int *target_id, unsigned int *source_id, 1779 unsigned int *get_flag, unsigned int *req, 1780 unsigned int *device_flag, unsigned int *resp_flag, 1781 unsigned int *error_flag, unsigned int *data_size) 1782 { 1783 if (data_size) 1784 *data_size = (header >> 27) & 0x1f; 1785 if (error_flag) 1786 *error_flag = (header >> 26) & 0x01; 1787 if (resp_flag) 1788 *resp_flag = (header >> 25) & 0x01; 1789 if (device_flag) 1790 *device_flag = (header >> 24) & 0x01; 1791 if (req) 1792 *req = (header >> 17) & 0x7f; 1793 if (get_flag) 1794 *get_flag = (header >> 16) & 0x01; 1795 if (source_id) 1796 *source_id = (header >> 8) & 0xff; 1797 if (target_id) 1798 *target_id = header & 0xff; 1799 } 1800 1801 #define SCP_MAX_DATA_WORDS (16) 1802 1803 /* Structure to contain any SCP message */ 1804 struct scp_msg { 1805 unsigned int hdr; 1806 unsigned int data[SCP_MAX_DATA_WORDS]; 1807 }; 1808 1809 static void dspio_clear_response_queue(struct hda_codec *codec) 1810 { 1811 unsigned int dummy = 0; 1812 int status = -1; 1813 1814 /* clear all from the response queue */ 1815 do { 1816 status = dspio_read(codec, &dummy); 1817 } while (status == 0); 1818 } 1819 1820 static int dspio_get_response_data(struct hda_codec *codec) 1821 { 1822 struct ca0132_spec *spec = codec->spec; 1823 unsigned int data = 0; 1824 unsigned int count; 1825 1826 if (dspio_read(codec, &data) < 0) 1827 return -EIO; 1828 1829 if ((data & 0x00ffffff) == spec->wait_scp_header) { 1830 spec->scp_resp_header = data; 1831 spec->scp_resp_count = data >> 27; 1832 count = spec->wait_num_data; 1833 dspio_read_multiple(codec, spec->scp_resp_data, 1834 &spec->scp_resp_count, count); 1835 return 0; 1836 } 1837 1838 return -EIO; 1839 } 1840 1841 /* 1842 * Send SCP message to DSP 1843 */ 1844 static int dspio_send_scp_message(struct hda_codec *codec, 1845 unsigned char *send_buf, 1846 unsigned int send_buf_size, 1847 unsigned char *return_buf, 1848 unsigned int return_buf_size, 1849 unsigned int *bytes_returned) 1850 { 1851 struct ca0132_spec *spec = codec->spec; 1852 int status = -1; 1853 unsigned int scp_send_size = 0; 1854 unsigned int total_size; 1855 bool waiting_for_resp = false; 1856 unsigned int header; 1857 struct scp_msg *ret_msg; 1858 unsigned int resp_src_id, resp_target_id; 1859 unsigned int data_size, src_id, target_id, get_flag, device_flag; 1860 1861 if (bytes_returned) 1862 *bytes_returned = 0; 1863 1864 /* get scp header from buffer */ 1865 header = *((unsigned int *)send_buf); 1866 extract_scp_header(header, &target_id, &src_id, &get_flag, NULL, 1867 &device_flag, NULL, NULL, &data_size); 1868 scp_send_size = data_size + 1; 1869 total_size = (scp_send_size * 4); 1870 1871 if (send_buf_size < total_size) 1872 return -EINVAL; 1873 1874 if (get_flag || device_flag) { 1875 if (!return_buf || return_buf_size < 4 || !bytes_returned) 1876 return -EINVAL; 1877 1878 spec->wait_scp_header = *((unsigned int *)send_buf); 1879 1880 /* swap source id with target id */ 1881 resp_target_id = src_id; 1882 resp_src_id = target_id; 1883 spec->wait_scp_header &= 0xffff0000; 1884 spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id); 1885 spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1; 1886 spec->wait_scp = 1; 1887 waiting_for_resp = true; 1888 } 1889 1890 status = dspio_write_multiple(codec, (unsigned int *)send_buf, 1891 scp_send_size); 1892 if (status < 0) { 1893 spec->wait_scp = 0; 1894 return status; 1895 } 1896 1897 if (waiting_for_resp) { 1898 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 1899 memset(return_buf, 0, return_buf_size); 1900 do { 1901 msleep(20); 1902 } while (spec->wait_scp && time_before(jiffies, timeout)); 1903 waiting_for_resp = false; 1904 if (!spec->wait_scp) { 1905 ret_msg = (struct scp_msg *)return_buf; 1906 memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4); 1907 memcpy(&ret_msg->data, spec->scp_resp_data, 1908 spec->wait_num_data); 1909 *bytes_returned = (spec->scp_resp_count + 1) * 4; 1910 status = 0; 1911 } else { 1912 status = -EIO; 1913 } 1914 spec->wait_scp = 0; 1915 } 1916 1917 return status; 1918 } 1919 1920 /** 1921 * Prepare and send the SCP message to DSP 1922 * @codec: the HDA codec 1923 * @mod_id: ID of the DSP module to send the command 1924 * @req: ID of request to send to the DSP module 1925 * @dir: SET or GET 1926 * @data: pointer to the data to send with the request, request specific 1927 * @len: length of the data, in bytes 1928 * @reply: point to the buffer to hold data returned for a reply 1929 * @reply_len: length of the reply buffer returned from GET 1930 * 1931 * Returns zero or a negative error code. 1932 */ 1933 static int dspio_scp(struct hda_codec *codec, 1934 int mod_id, int src_id, int req, int dir, const void *data, 1935 unsigned int len, void *reply, unsigned int *reply_len) 1936 { 1937 int status = 0; 1938 struct scp_msg scp_send, scp_reply; 1939 unsigned int ret_bytes, send_size, ret_size; 1940 unsigned int send_get_flag, reply_resp_flag, reply_error_flag; 1941 unsigned int reply_data_size; 1942 1943 memset(&scp_send, 0, sizeof(scp_send)); 1944 memset(&scp_reply, 0, sizeof(scp_reply)); 1945 1946 if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS)) 1947 return -EINVAL; 1948 1949 if (dir == SCP_GET && reply == NULL) { 1950 codec_dbg(codec, "dspio_scp get but has no buffer\n"); 1951 return -EINVAL; 1952 } 1953 1954 if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) { 1955 codec_dbg(codec, "dspio_scp bad resp buf len parms\n"); 1956 return -EINVAL; 1957 } 1958 1959 scp_send.hdr = make_scp_header(mod_id, src_id, (dir == SCP_GET), req, 1960 0, 0, 0, len/sizeof(unsigned int)); 1961 if (data != NULL && len > 0) { 1962 len = min((unsigned int)(sizeof(scp_send.data)), len); 1963 memcpy(scp_send.data, data, len); 1964 } 1965 1966 ret_bytes = 0; 1967 send_size = sizeof(unsigned int) + len; 1968 status = dspio_send_scp_message(codec, (unsigned char *)&scp_send, 1969 send_size, (unsigned char *)&scp_reply, 1970 sizeof(scp_reply), &ret_bytes); 1971 1972 if (status < 0) { 1973 codec_dbg(codec, "dspio_scp: send scp msg failed\n"); 1974 return status; 1975 } 1976 1977 /* extract send and reply headers members */ 1978 extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag, 1979 NULL, NULL, NULL, NULL, NULL); 1980 extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL, 1981 &reply_resp_flag, &reply_error_flag, 1982 &reply_data_size); 1983 1984 if (!send_get_flag) 1985 return 0; 1986 1987 if (reply_resp_flag && !reply_error_flag) { 1988 ret_size = (ret_bytes - sizeof(scp_reply.hdr)) 1989 / sizeof(unsigned int); 1990 1991 if (*reply_len < ret_size*sizeof(unsigned int)) { 1992 codec_dbg(codec, "reply too long for buf\n"); 1993 return -EINVAL; 1994 } else if (ret_size != reply_data_size) { 1995 codec_dbg(codec, "RetLen and HdrLen .NE.\n"); 1996 return -EINVAL; 1997 } else if (!reply) { 1998 codec_dbg(codec, "NULL reply\n"); 1999 return -EINVAL; 2000 } else { 2001 *reply_len = ret_size*sizeof(unsigned int); 2002 memcpy(reply, scp_reply.data, *reply_len); 2003 } 2004 } else { 2005 codec_dbg(codec, "reply ill-formed or errflag set\n"); 2006 return -EIO; 2007 } 2008 2009 return status; 2010 } 2011 2012 /* 2013 * Set DSP parameters 2014 */ 2015 static int dspio_set_param(struct hda_codec *codec, int mod_id, 2016 int src_id, int req, const void *data, unsigned int len) 2017 { 2018 return dspio_scp(codec, mod_id, src_id, req, SCP_SET, data, len, NULL, 2019 NULL); 2020 } 2021 2022 static int dspio_set_uint_param(struct hda_codec *codec, int mod_id, 2023 int req, const unsigned int data) 2024 { 2025 return dspio_set_param(codec, mod_id, 0x20, req, &data, 2026 sizeof(unsigned int)); 2027 } 2028 2029 static int dspio_set_uint_param_no_source(struct hda_codec *codec, int mod_id, 2030 int req, const unsigned int data) 2031 { 2032 return dspio_set_param(codec, mod_id, 0x00, req, &data, 2033 sizeof(unsigned int)); 2034 } 2035 2036 /* 2037 * Allocate a DSP DMA channel via an SCP message 2038 */ 2039 static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan) 2040 { 2041 int status = 0; 2042 unsigned int size = sizeof(dma_chan); 2043 2044 codec_dbg(codec, " dspio_alloc_dma_chan() -- begin\n"); 2045 status = dspio_scp(codec, MASTERCONTROL, 0x20, 2046 MASTERCONTROL_ALLOC_DMA_CHAN, SCP_GET, NULL, 0, 2047 dma_chan, &size); 2048 2049 if (status < 0) { 2050 codec_dbg(codec, "dspio_alloc_dma_chan: SCP Failed\n"); 2051 return status; 2052 } 2053 2054 if ((*dma_chan + 1) == 0) { 2055 codec_dbg(codec, "no free dma channels to allocate\n"); 2056 return -EBUSY; 2057 } 2058 2059 codec_dbg(codec, "dspio_alloc_dma_chan: chan=%d\n", *dma_chan); 2060 codec_dbg(codec, " dspio_alloc_dma_chan() -- complete\n"); 2061 2062 return status; 2063 } 2064 2065 /* 2066 * Free a DSP DMA via an SCP message 2067 */ 2068 static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan) 2069 { 2070 int status = 0; 2071 unsigned int dummy = 0; 2072 2073 codec_dbg(codec, " dspio_free_dma_chan() -- begin\n"); 2074 codec_dbg(codec, "dspio_free_dma_chan: chan=%d\n", dma_chan); 2075 2076 status = dspio_scp(codec, MASTERCONTROL, 0x20, 2077 MASTERCONTROL_ALLOC_DMA_CHAN, SCP_SET, &dma_chan, 2078 sizeof(dma_chan), NULL, &dummy); 2079 2080 if (status < 0) { 2081 codec_dbg(codec, "dspio_free_dma_chan: SCP Failed\n"); 2082 return status; 2083 } 2084 2085 codec_dbg(codec, " dspio_free_dma_chan() -- complete\n"); 2086 2087 return status; 2088 } 2089 2090 /* 2091 * (Re)start the DSP 2092 */ 2093 static int dsp_set_run_state(struct hda_codec *codec) 2094 { 2095 unsigned int dbg_ctrl_reg; 2096 unsigned int halt_state; 2097 int err; 2098 2099 err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg); 2100 if (err < 0) 2101 return err; 2102 2103 halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >> 2104 DSP_DBGCNTL_STATE_LOBIT; 2105 2106 if (halt_state != 0) { 2107 dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) & 2108 DSP_DBGCNTL_SS_MASK); 2109 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET, 2110 dbg_ctrl_reg); 2111 if (err < 0) 2112 return err; 2113 2114 dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) & 2115 DSP_DBGCNTL_EXEC_MASK; 2116 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET, 2117 dbg_ctrl_reg); 2118 if (err < 0) 2119 return err; 2120 } 2121 2122 return 0; 2123 } 2124 2125 /* 2126 * Reset the DSP 2127 */ 2128 static int dsp_reset(struct hda_codec *codec) 2129 { 2130 unsigned int res; 2131 int retry = 20; 2132 2133 codec_dbg(codec, "dsp_reset\n"); 2134 do { 2135 res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0); 2136 retry--; 2137 } while (res == -EIO && retry); 2138 2139 if (!retry) { 2140 codec_dbg(codec, "dsp_reset timeout\n"); 2141 return -EIO; 2142 } 2143 2144 return 0; 2145 } 2146 2147 /* 2148 * Convert chip address to DSP address 2149 */ 2150 static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx, 2151 bool *code, bool *yram) 2152 { 2153 *code = *yram = false; 2154 2155 if (UC_RANGE(chip_addx, 1)) { 2156 *code = true; 2157 return UC_OFF(chip_addx); 2158 } else if (X_RANGE_ALL(chip_addx, 1)) { 2159 return X_OFF(chip_addx); 2160 } else if (Y_RANGE_ALL(chip_addx, 1)) { 2161 *yram = true; 2162 return Y_OFF(chip_addx); 2163 } 2164 2165 return INVALID_CHIP_ADDRESS; 2166 } 2167 2168 /* 2169 * Check if the DSP DMA is active 2170 */ 2171 static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan) 2172 { 2173 unsigned int dma_chnlstart_reg; 2174 2175 chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg); 2176 2177 return ((dma_chnlstart_reg & (1 << 2178 (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0); 2179 } 2180 2181 static int dsp_dma_setup_common(struct hda_codec *codec, 2182 unsigned int chip_addx, 2183 unsigned int dma_chan, 2184 unsigned int port_map_mask, 2185 bool ovly) 2186 { 2187 int status = 0; 2188 unsigned int chnl_prop; 2189 unsigned int dsp_addx; 2190 unsigned int active; 2191 bool code, yram; 2192 2193 codec_dbg(codec, "-- dsp_dma_setup_common() -- Begin ---------\n"); 2194 2195 if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT) { 2196 codec_dbg(codec, "dma chan num invalid\n"); 2197 return -EINVAL; 2198 } 2199 2200 if (dsp_is_dma_active(codec, dma_chan)) { 2201 codec_dbg(codec, "dma already active\n"); 2202 return -EBUSY; 2203 } 2204 2205 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram); 2206 2207 if (dsp_addx == INVALID_CHIP_ADDRESS) { 2208 codec_dbg(codec, "invalid chip addr\n"); 2209 return -ENXIO; 2210 } 2211 2212 chnl_prop = DSPDMAC_CHNLPROP_AC_MASK; 2213 active = 0; 2214 2215 codec_dbg(codec, " dsp_dma_setup_common() start reg pgm\n"); 2216 2217 if (ovly) { 2218 status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET, 2219 &chnl_prop); 2220 2221 if (status < 0) { 2222 codec_dbg(codec, "read CHNLPROP Reg fail\n"); 2223 return status; 2224 } 2225 codec_dbg(codec, "dsp_dma_setup_common() Read CHNLPROP\n"); 2226 } 2227 2228 if (!code) 2229 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan)); 2230 else 2231 chnl_prop |= (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan)); 2232 2233 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan)); 2234 2235 status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop); 2236 if (status < 0) { 2237 codec_dbg(codec, "write CHNLPROP Reg fail\n"); 2238 return status; 2239 } 2240 codec_dbg(codec, " dsp_dma_setup_common() Write CHNLPROP\n"); 2241 2242 if (ovly) { 2243 status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET, 2244 &active); 2245 2246 if (status < 0) { 2247 codec_dbg(codec, "read ACTIVE Reg fail\n"); 2248 return status; 2249 } 2250 codec_dbg(codec, "dsp_dma_setup_common() Read ACTIVE\n"); 2251 } 2252 2253 active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) & 2254 DSPDMAC_ACTIVE_AAR_MASK; 2255 2256 status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active); 2257 if (status < 0) { 2258 codec_dbg(codec, "write ACTIVE Reg fail\n"); 2259 return status; 2260 } 2261 2262 codec_dbg(codec, " dsp_dma_setup_common() Write ACTIVE\n"); 2263 2264 status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan), 2265 port_map_mask); 2266 if (status < 0) { 2267 codec_dbg(codec, "write AUDCHSEL Reg fail\n"); 2268 return status; 2269 } 2270 codec_dbg(codec, " dsp_dma_setup_common() Write AUDCHSEL\n"); 2271 2272 status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan), 2273 DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK); 2274 if (status < 0) { 2275 codec_dbg(codec, "write IRQCNT Reg fail\n"); 2276 return status; 2277 } 2278 codec_dbg(codec, " dsp_dma_setup_common() Write IRQCNT\n"); 2279 2280 codec_dbg(codec, 2281 "ChipA=0x%x,DspA=0x%x,dmaCh=%u, " 2282 "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n", 2283 chip_addx, dsp_addx, dma_chan, 2284 port_map_mask, chnl_prop, active); 2285 2286 codec_dbg(codec, "-- dsp_dma_setup_common() -- Complete ------\n"); 2287 2288 return 0; 2289 } 2290 2291 /* 2292 * Setup the DSP DMA per-transfer-specific registers 2293 */ 2294 static int dsp_dma_setup(struct hda_codec *codec, 2295 unsigned int chip_addx, 2296 unsigned int count, 2297 unsigned int dma_chan) 2298 { 2299 int status = 0; 2300 bool code, yram; 2301 unsigned int dsp_addx; 2302 unsigned int addr_field; 2303 unsigned int incr_field; 2304 unsigned int base_cnt; 2305 unsigned int cur_cnt; 2306 unsigned int dma_cfg = 0; 2307 unsigned int adr_ofs = 0; 2308 unsigned int xfr_cnt = 0; 2309 const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT - 2310 DSPDMAC_XFRCNT_BCNT_LOBIT + 1); 2311 2312 codec_dbg(codec, "-- dsp_dma_setup() -- Begin ---------\n"); 2313 2314 if (count > max_dma_count) { 2315 codec_dbg(codec, "count too big\n"); 2316 return -EINVAL; 2317 } 2318 2319 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram); 2320 if (dsp_addx == INVALID_CHIP_ADDRESS) { 2321 codec_dbg(codec, "invalid chip addr\n"); 2322 return -ENXIO; 2323 } 2324 2325 codec_dbg(codec, " dsp_dma_setup() start reg pgm\n"); 2326 2327 addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT; 2328 incr_field = 0; 2329 2330 if (!code) { 2331 addr_field <<= 1; 2332 if (yram) 2333 addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT); 2334 2335 incr_field = (1 << DSPDMAC_DMACFG_AINCR_LOBIT); 2336 } 2337 2338 dma_cfg = addr_field + incr_field; 2339 status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan), 2340 dma_cfg); 2341 if (status < 0) { 2342 codec_dbg(codec, "write DMACFG Reg fail\n"); 2343 return status; 2344 } 2345 codec_dbg(codec, " dsp_dma_setup() Write DMACFG\n"); 2346 2347 adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT + 2348 (code ? 0 : 1)); 2349 2350 status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan), 2351 adr_ofs); 2352 if (status < 0) { 2353 codec_dbg(codec, "write DSPADROFS Reg fail\n"); 2354 return status; 2355 } 2356 codec_dbg(codec, " dsp_dma_setup() Write DSPADROFS\n"); 2357 2358 base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT; 2359 2360 cur_cnt = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT; 2361 2362 xfr_cnt = base_cnt | cur_cnt; 2363 2364 status = chipio_write(codec, 2365 DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt); 2366 if (status < 0) { 2367 codec_dbg(codec, "write XFRCNT Reg fail\n"); 2368 return status; 2369 } 2370 codec_dbg(codec, " dsp_dma_setup() Write XFRCNT\n"); 2371 2372 codec_dbg(codec, 2373 "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, " 2374 "ADROFS=0x%x, XFRCNT=0x%x\n", 2375 chip_addx, count, dma_cfg, adr_ofs, xfr_cnt); 2376 2377 codec_dbg(codec, "-- dsp_dma_setup() -- Complete ---------\n"); 2378 2379 return 0; 2380 } 2381 2382 /* 2383 * Start the DSP DMA 2384 */ 2385 static int dsp_dma_start(struct hda_codec *codec, 2386 unsigned int dma_chan, bool ovly) 2387 { 2388 unsigned int reg = 0; 2389 int status = 0; 2390 2391 codec_dbg(codec, "-- dsp_dma_start() -- Begin ---------\n"); 2392 2393 if (ovly) { 2394 status = chipio_read(codec, 2395 DSPDMAC_CHNLSTART_INST_OFFSET, ®); 2396 2397 if (status < 0) { 2398 codec_dbg(codec, "read CHNLSTART reg fail\n"); 2399 return status; 2400 } 2401 codec_dbg(codec, "-- dsp_dma_start() Read CHNLSTART\n"); 2402 2403 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK | 2404 DSPDMAC_CHNLSTART_DIS_MASK); 2405 } 2406 2407 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET, 2408 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT))); 2409 if (status < 0) { 2410 codec_dbg(codec, "write CHNLSTART reg fail\n"); 2411 return status; 2412 } 2413 codec_dbg(codec, "-- dsp_dma_start() -- Complete ---------\n"); 2414 2415 return status; 2416 } 2417 2418 /* 2419 * Stop the DSP DMA 2420 */ 2421 static int dsp_dma_stop(struct hda_codec *codec, 2422 unsigned int dma_chan, bool ovly) 2423 { 2424 unsigned int reg = 0; 2425 int status = 0; 2426 2427 codec_dbg(codec, "-- dsp_dma_stop() -- Begin ---------\n"); 2428 2429 if (ovly) { 2430 status = chipio_read(codec, 2431 DSPDMAC_CHNLSTART_INST_OFFSET, ®); 2432 2433 if (status < 0) { 2434 codec_dbg(codec, "read CHNLSTART reg fail\n"); 2435 return status; 2436 } 2437 codec_dbg(codec, "-- dsp_dma_stop() Read CHNLSTART\n"); 2438 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK | 2439 DSPDMAC_CHNLSTART_DIS_MASK); 2440 } 2441 2442 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET, 2443 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT))); 2444 if (status < 0) { 2445 codec_dbg(codec, "write CHNLSTART reg fail\n"); 2446 return status; 2447 } 2448 codec_dbg(codec, "-- dsp_dma_stop() -- Complete ---------\n"); 2449 2450 return status; 2451 } 2452 2453 /** 2454 * Allocate router ports 2455 * 2456 * @codec: the HDA codec 2457 * @num_chans: number of channels in the stream 2458 * @ports_per_channel: number of ports per channel 2459 * @start_device: start device 2460 * @port_map: pointer to the port list to hold the allocated ports 2461 * 2462 * Returns zero or a negative error code. 2463 */ 2464 static int dsp_allocate_router_ports(struct hda_codec *codec, 2465 unsigned int num_chans, 2466 unsigned int ports_per_channel, 2467 unsigned int start_device, 2468 unsigned int *port_map) 2469 { 2470 int status = 0; 2471 int res; 2472 u8 val; 2473 2474 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 2475 if (status < 0) 2476 return status; 2477 2478 val = start_device << 6; 2479 val |= (ports_per_channel - 1) << 4; 2480 val |= num_chans - 1; 2481 2482 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 2483 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET, 2484 val); 2485 2486 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 2487 VENDOR_CHIPIO_PORT_ALLOC_SET, 2488 MEM_CONNID_DSP); 2489 2490 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 2491 if (status < 0) 2492 return status; 2493 2494 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, 2495 VENDOR_CHIPIO_PORT_ALLOC_GET, 0); 2496 2497 *port_map = res; 2498 2499 return (res < 0) ? res : 0; 2500 } 2501 2502 /* 2503 * Free router ports 2504 */ 2505 static int dsp_free_router_ports(struct hda_codec *codec) 2506 { 2507 int status = 0; 2508 2509 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 2510 if (status < 0) 2511 return status; 2512 2513 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 2514 VENDOR_CHIPIO_PORT_FREE_SET, 2515 MEM_CONNID_DSP); 2516 2517 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 2518 2519 return status; 2520 } 2521 2522 /* 2523 * Allocate DSP ports for the download stream 2524 */ 2525 static int dsp_allocate_ports(struct hda_codec *codec, 2526 unsigned int num_chans, 2527 unsigned int rate_multi, unsigned int *port_map) 2528 { 2529 int status; 2530 2531 codec_dbg(codec, " dsp_allocate_ports() -- begin\n"); 2532 2533 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) { 2534 codec_dbg(codec, "bad rate multiple\n"); 2535 return -EINVAL; 2536 } 2537 2538 status = dsp_allocate_router_ports(codec, num_chans, 2539 rate_multi, 0, port_map); 2540 2541 codec_dbg(codec, " dsp_allocate_ports() -- complete\n"); 2542 2543 return status; 2544 } 2545 2546 static int dsp_allocate_ports_format(struct hda_codec *codec, 2547 const unsigned short fmt, 2548 unsigned int *port_map) 2549 { 2550 int status; 2551 unsigned int num_chans; 2552 2553 unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1; 2554 unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1; 2555 unsigned int rate_multi = sample_rate_mul / sample_rate_div; 2556 2557 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) { 2558 codec_dbg(codec, "bad rate multiple\n"); 2559 return -EINVAL; 2560 } 2561 2562 num_chans = get_hdafmt_chs(fmt) + 1; 2563 2564 status = dsp_allocate_ports(codec, num_chans, rate_multi, port_map); 2565 2566 return status; 2567 } 2568 2569 /* 2570 * free DSP ports 2571 */ 2572 static int dsp_free_ports(struct hda_codec *codec) 2573 { 2574 int status; 2575 2576 codec_dbg(codec, " dsp_free_ports() -- begin\n"); 2577 2578 status = dsp_free_router_ports(codec); 2579 if (status < 0) { 2580 codec_dbg(codec, "free router ports fail\n"); 2581 return status; 2582 } 2583 codec_dbg(codec, " dsp_free_ports() -- complete\n"); 2584 2585 return status; 2586 } 2587 2588 /* 2589 * HDA DMA engine stuffs for DSP code download 2590 */ 2591 struct dma_engine { 2592 struct hda_codec *codec; 2593 unsigned short m_converter_format; 2594 struct snd_dma_buffer *dmab; 2595 unsigned int buf_size; 2596 }; 2597 2598 2599 enum dma_state { 2600 DMA_STATE_STOP = 0, 2601 DMA_STATE_RUN = 1 2602 }; 2603 2604 static int dma_convert_to_hda_format(struct hda_codec *codec, 2605 unsigned int sample_rate, 2606 unsigned short channels, 2607 unsigned short *hda_format) 2608 { 2609 unsigned int format_val; 2610 2611 format_val = snd_hdac_calc_stream_format(sample_rate, 2612 channels, SNDRV_PCM_FORMAT_S32_LE, 32, 0); 2613 2614 if (hda_format) 2615 *hda_format = (unsigned short)format_val; 2616 2617 return 0; 2618 } 2619 2620 /* 2621 * Reset DMA for DSP download 2622 */ 2623 static int dma_reset(struct dma_engine *dma) 2624 { 2625 struct hda_codec *codec = dma->codec; 2626 struct ca0132_spec *spec = codec->spec; 2627 int status; 2628 2629 if (dma->dmab->area) 2630 snd_hda_codec_load_dsp_cleanup(codec, dma->dmab); 2631 2632 status = snd_hda_codec_load_dsp_prepare(codec, 2633 dma->m_converter_format, 2634 dma->buf_size, 2635 dma->dmab); 2636 if (status < 0) 2637 return status; 2638 spec->dsp_stream_id = status; 2639 return 0; 2640 } 2641 2642 static int dma_set_state(struct dma_engine *dma, enum dma_state state) 2643 { 2644 bool cmd; 2645 2646 switch (state) { 2647 case DMA_STATE_STOP: 2648 cmd = false; 2649 break; 2650 case DMA_STATE_RUN: 2651 cmd = true; 2652 break; 2653 default: 2654 return 0; 2655 } 2656 2657 snd_hda_codec_load_dsp_trigger(dma->codec, cmd); 2658 return 0; 2659 } 2660 2661 static unsigned int dma_get_buffer_size(struct dma_engine *dma) 2662 { 2663 return dma->dmab->bytes; 2664 } 2665 2666 static unsigned char *dma_get_buffer_addr(struct dma_engine *dma) 2667 { 2668 return dma->dmab->area; 2669 } 2670 2671 static int dma_xfer(struct dma_engine *dma, 2672 const unsigned int *data, 2673 unsigned int count) 2674 { 2675 memcpy(dma->dmab->area, data, count); 2676 return 0; 2677 } 2678 2679 static void dma_get_converter_format( 2680 struct dma_engine *dma, 2681 unsigned short *format) 2682 { 2683 if (format) 2684 *format = dma->m_converter_format; 2685 } 2686 2687 static unsigned int dma_get_stream_id(struct dma_engine *dma) 2688 { 2689 struct ca0132_spec *spec = dma->codec->spec; 2690 2691 return spec->dsp_stream_id; 2692 } 2693 2694 struct dsp_image_seg { 2695 u32 magic; 2696 u32 chip_addr; 2697 u32 count; 2698 u32 data[0]; 2699 }; 2700 2701 static const u32 g_magic_value = 0x4c46584d; 2702 static const u32 g_chip_addr_magic_value = 0xFFFFFF01; 2703 2704 static bool is_valid(const struct dsp_image_seg *p) 2705 { 2706 return p->magic == g_magic_value; 2707 } 2708 2709 static bool is_hci_prog_list_seg(const struct dsp_image_seg *p) 2710 { 2711 return g_chip_addr_magic_value == p->chip_addr; 2712 } 2713 2714 static bool is_last(const struct dsp_image_seg *p) 2715 { 2716 return p->count == 0; 2717 } 2718 2719 static size_t dsp_sizeof(const struct dsp_image_seg *p) 2720 { 2721 return sizeof(*p) + p->count*sizeof(u32); 2722 } 2723 2724 static const struct dsp_image_seg *get_next_seg_ptr( 2725 const struct dsp_image_seg *p) 2726 { 2727 return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p)); 2728 } 2729 2730 /* 2731 * CA0132 chip DSP transfer stuffs. For DSP download. 2732 */ 2733 #define INVALID_DMA_CHANNEL (~0U) 2734 2735 /* 2736 * Program a list of address/data pairs via the ChipIO widget. 2737 * The segment data is in the format of successive pairs of words. 2738 * These are repeated as indicated by the segment's count field. 2739 */ 2740 static int dspxfr_hci_write(struct hda_codec *codec, 2741 const struct dsp_image_seg *fls) 2742 { 2743 int status; 2744 const u32 *data; 2745 unsigned int count; 2746 2747 if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) { 2748 codec_dbg(codec, "hci_write invalid params\n"); 2749 return -EINVAL; 2750 } 2751 2752 count = fls->count; 2753 data = (u32 *)(fls->data); 2754 while (count >= 2) { 2755 status = chipio_write(codec, data[0], data[1]); 2756 if (status < 0) { 2757 codec_dbg(codec, "hci_write chipio failed\n"); 2758 return status; 2759 } 2760 count -= 2; 2761 data += 2; 2762 } 2763 return 0; 2764 } 2765 2766 /** 2767 * Write a block of data into DSP code or data RAM using pre-allocated 2768 * DMA engine. 2769 * 2770 * @codec: the HDA codec 2771 * @fls: pointer to a fast load image 2772 * @reloc: Relocation address for loading single-segment overlays, or 0 for 2773 * no relocation 2774 * @dma_engine: pointer to DMA engine to be used for DSP download 2775 * @dma_chan: The number of DMA channels used for DSP download 2776 * @port_map_mask: port mapping 2777 * @ovly: TRUE if overlay format is required 2778 * 2779 * Returns zero or a negative error code. 2780 */ 2781 static int dspxfr_one_seg(struct hda_codec *codec, 2782 const struct dsp_image_seg *fls, 2783 unsigned int reloc, 2784 struct dma_engine *dma_engine, 2785 unsigned int dma_chan, 2786 unsigned int port_map_mask, 2787 bool ovly) 2788 { 2789 int status = 0; 2790 bool comm_dma_setup_done = false; 2791 const unsigned int *data; 2792 unsigned int chip_addx; 2793 unsigned int words_to_write; 2794 unsigned int buffer_size_words; 2795 unsigned char *buffer_addx; 2796 unsigned short hda_format; 2797 unsigned int sample_rate_div; 2798 unsigned int sample_rate_mul; 2799 unsigned int num_chans; 2800 unsigned int hda_frame_size_words; 2801 unsigned int remainder_words; 2802 const u32 *data_remainder; 2803 u32 chip_addx_remainder; 2804 unsigned int run_size_words; 2805 const struct dsp_image_seg *hci_write = NULL; 2806 unsigned long timeout; 2807 bool dma_active; 2808 2809 if (fls == NULL) 2810 return -EINVAL; 2811 if (is_hci_prog_list_seg(fls)) { 2812 hci_write = fls; 2813 fls = get_next_seg_ptr(fls); 2814 } 2815 2816 if (hci_write && (!fls || is_last(fls))) { 2817 codec_dbg(codec, "hci_write\n"); 2818 return dspxfr_hci_write(codec, hci_write); 2819 } 2820 2821 if (fls == NULL || dma_engine == NULL || port_map_mask == 0) { 2822 codec_dbg(codec, "Invalid Params\n"); 2823 return -EINVAL; 2824 } 2825 2826 data = fls->data; 2827 chip_addx = fls->chip_addr, 2828 words_to_write = fls->count; 2829 2830 if (!words_to_write) 2831 return hci_write ? dspxfr_hci_write(codec, hci_write) : 0; 2832 if (reloc) 2833 chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2); 2834 2835 if (!UC_RANGE(chip_addx, words_to_write) && 2836 !X_RANGE_ALL(chip_addx, words_to_write) && 2837 !Y_RANGE_ALL(chip_addx, words_to_write)) { 2838 codec_dbg(codec, "Invalid chip_addx Params\n"); 2839 return -EINVAL; 2840 } 2841 2842 buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) / 2843 sizeof(u32); 2844 2845 buffer_addx = dma_get_buffer_addr(dma_engine); 2846 2847 if (buffer_addx == NULL) { 2848 codec_dbg(codec, "dma_engine buffer NULL\n"); 2849 return -EINVAL; 2850 } 2851 2852 dma_get_converter_format(dma_engine, &hda_format); 2853 sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1; 2854 sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1; 2855 num_chans = get_hdafmt_chs(hda_format) + 1; 2856 2857 hda_frame_size_words = ((sample_rate_div == 0) ? 0 : 2858 (num_chans * sample_rate_mul / sample_rate_div)); 2859 2860 if (hda_frame_size_words == 0) { 2861 codec_dbg(codec, "frmsz zero\n"); 2862 return -EINVAL; 2863 } 2864 2865 buffer_size_words = min(buffer_size_words, 2866 (unsigned int)(UC_RANGE(chip_addx, 1) ? 2867 65536 : 32768)); 2868 buffer_size_words -= buffer_size_words % hda_frame_size_words; 2869 codec_dbg(codec, 2870 "chpadr=0x%08x frmsz=%u nchan=%u " 2871 "rate_mul=%u div=%u bufsz=%u\n", 2872 chip_addx, hda_frame_size_words, num_chans, 2873 sample_rate_mul, sample_rate_div, buffer_size_words); 2874 2875 if (buffer_size_words < hda_frame_size_words) { 2876 codec_dbg(codec, "dspxfr_one_seg:failed\n"); 2877 return -EINVAL; 2878 } 2879 2880 remainder_words = words_to_write % hda_frame_size_words; 2881 data_remainder = data; 2882 chip_addx_remainder = chip_addx; 2883 2884 data += remainder_words; 2885 chip_addx += remainder_words*sizeof(u32); 2886 words_to_write -= remainder_words; 2887 2888 while (words_to_write != 0) { 2889 run_size_words = min(buffer_size_words, words_to_write); 2890 codec_dbg(codec, "dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n", 2891 words_to_write, run_size_words, remainder_words); 2892 dma_xfer(dma_engine, data, run_size_words*sizeof(u32)); 2893 if (!comm_dma_setup_done) { 2894 status = dsp_dma_stop(codec, dma_chan, ovly); 2895 if (status < 0) 2896 return status; 2897 status = dsp_dma_setup_common(codec, chip_addx, 2898 dma_chan, port_map_mask, ovly); 2899 if (status < 0) 2900 return status; 2901 comm_dma_setup_done = true; 2902 } 2903 2904 status = dsp_dma_setup(codec, chip_addx, 2905 run_size_words, dma_chan); 2906 if (status < 0) 2907 return status; 2908 status = dsp_dma_start(codec, dma_chan, ovly); 2909 if (status < 0) 2910 return status; 2911 if (!dsp_is_dma_active(codec, dma_chan)) { 2912 codec_dbg(codec, "dspxfr:DMA did not start\n"); 2913 return -EIO; 2914 } 2915 status = dma_set_state(dma_engine, DMA_STATE_RUN); 2916 if (status < 0) 2917 return status; 2918 if (remainder_words != 0) { 2919 status = chipio_write_multiple(codec, 2920 chip_addx_remainder, 2921 data_remainder, 2922 remainder_words); 2923 if (status < 0) 2924 return status; 2925 remainder_words = 0; 2926 } 2927 if (hci_write) { 2928 status = dspxfr_hci_write(codec, hci_write); 2929 if (status < 0) 2930 return status; 2931 hci_write = NULL; 2932 } 2933 2934 timeout = jiffies + msecs_to_jiffies(2000); 2935 do { 2936 dma_active = dsp_is_dma_active(codec, dma_chan); 2937 if (!dma_active) 2938 break; 2939 msleep(20); 2940 } while (time_before(jiffies, timeout)); 2941 if (dma_active) 2942 break; 2943 2944 codec_dbg(codec, "+++++ DMA complete\n"); 2945 dma_set_state(dma_engine, DMA_STATE_STOP); 2946 status = dma_reset(dma_engine); 2947 2948 if (status < 0) 2949 return status; 2950 2951 data += run_size_words; 2952 chip_addx += run_size_words*sizeof(u32); 2953 words_to_write -= run_size_words; 2954 } 2955 2956 if (remainder_words != 0) { 2957 status = chipio_write_multiple(codec, chip_addx_remainder, 2958 data_remainder, remainder_words); 2959 } 2960 2961 return status; 2962 } 2963 2964 /** 2965 * Write the entire DSP image of a DSP code/data overlay to DSP memories 2966 * 2967 * @codec: the HDA codec 2968 * @fls_data: pointer to a fast load image 2969 * @reloc: Relocation address for loading single-segment overlays, or 0 for 2970 * no relocation 2971 * @sample_rate: sampling rate of the stream used for DSP download 2972 * @channels: channels of the stream used for DSP download 2973 * @ovly: TRUE if overlay format is required 2974 * 2975 * Returns zero or a negative error code. 2976 */ 2977 static int dspxfr_image(struct hda_codec *codec, 2978 const struct dsp_image_seg *fls_data, 2979 unsigned int reloc, 2980 unsigned int sample_rate, 2981 unsigned short channels, 2982 bool ovly) 2983 { 2984 struct ca0132_spec *spec = codec->spec; 2985 int status; 2986 unsigned short hda_format = 0; 2987 unsigned int response; 2988 unsigned char stream_id = 0; 2989 struct dma_engine *dma_engine; 2990 unsigned int dma_chan; 2991 unsigned int port_map_mask; 2992 2993 if (fls_data == NULL) 2994 return -EINVAL; 2995 2996 dma_engine = kzalloc(sizeof(*dma_engine), GFP_KERNEL); 2997 if (!dma_engine) 2998 return -ENOMEM; 2999 3000 dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL); 3001 if (!dma_engine->dmab) { 3002 kfree(dma_engine); 3003 return -ENOMEM; 3004 } 3005 3006 dma_engine->codec = codec; 3007 dma_convert_to_hda_format(codec, sample_rate, channels, &hda_format); 3008 dma_engine->m_converter_format = hda_format; 3009 dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY : 3010 DSP_DMA_WRITE_BUFLEN_INIT) * 2; 3011 3012 dma_chan = ovly ? INVALID_DMA_CHANNEL : 0; 3013 3014 status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL, 3015 hda_format, &response); 3016 3017 if (status < 0) { 3018 codec_dbg(codec, "set converter format fail\n"); 3019 goto exit; 3020 } 3021 3022 status = snd_hda_codec_load_dsp_prepare(codec, 3023 dma_engine->m_converter_format, 3024 dma_engine->buf_size, 3025 dma_engine->dmab); 3026 if (status < 0) 3027 goto exit; 3028 spec->dsp_stream_id = status; 3029 3030 if (ovly) { 3031 status = dspio_alloc_dma_chan(codec, &dma_chan); 3032 if (status < 0) { 3033 codec_dbg(codec, "alloc dmachan fail\n"); 3034 dma_chan = INVALID_DMA_CHANNEL; 3035 goto exit; 3036 } 3037 } 3038 3039 port_map_mask = 0; 3040 status = dsp_allocate_ports_format(codec, hda_format, 3041 &port_map_mask); 3042 if (status < 0) { 3043 codec_dbg(codec, "alloc ports fail\n"); 3044 goto exit; 3045 } 3046 3047 stream_id = dma_get_stream_id(dma_engine); 3048 status = codec_set_converter_stream_channel(codec, 3049 WIDGET_CHIP_CTRL, stream_id, 0, &response); 3050 if (status < 0) { 3051 codec_dbg(codec, "set stream chan fail\n"); 3052 goto exit; 3053 } 3054 3055 while ((fls_data != NULL) && !is_last(fls_data)) { 3056 if (!is_valid(fls_data)) { 3057 codec_dbg(codec, "FLS check fail\n"); 3058 status = -EINVAL; 3059 goto exit; 3060 } 3061 status = dspxfr_one_seg(codec, fls_data, reloc, 3062 dma_engine, dma_chan, 3063 port_map_mask, ovly); 3064 if (status < 0) 3065 break; 3066 3067 if (is_hci_prog_list_seg(fls_data)) 3068 fls_data = get_next_seg_ptr(fls_data); 3069 3070 if ((fls_data != NULL) && !is_last(fls_data)) 3071 fls_data = get_next_seg_ptr(fls_data); 3072 } 3073 3074 if (port_map_mask != 0) 3075 status = dsp_free_ports(codec); 3076 3077 if (status < 0) 3078 goto exit; 3079 3080 status = codec_set_converter_stream_channel(codec, 3081 WIDGET_CHIP_CTRL, 0, 0, &response); 3082 3083 exit: 3084 if (ovly && (dma_chan != INVALID_DMA_CHANNEL)) 3085 dspio_free_dma_chan(codec, dma_chan); 3086 3087 if (dma_engine->dmab->area) 3088 snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab); 3089 kfree(dma_engine->dmab); 3090 kfree(dma_engine); 3091 3092 return status; 3093 } 3094 3095 /* 3096 * CA0132 DSP download stuffs. 3097 */ 3098 static void dspload_post_setup(struct hda_codec *codec) 3099 { 3100 struct ca0132_spec *spec = codec->spec; 3101 codec_dbg(codec, "---- dspload_post_setup ------\n"); 3102 if (!ca0132_use_alt_functions(spec)) { 3103 /*set DSP speaker to 2.0 configuration*/ 3104 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080); 3105 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000); 3106 3107 /*update write pointer*/ 3108 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002); 3109 } 3110 } 3111 3112 /** 3113 * dspload_image - Download DSP from a DSP Image Fast Load structure. 3114 * 3115 * @codec: the HDA codec 3116 * @fls: pointer to a fast load image 3117 * @ovly: TRUE if overlay format is required 3118 * @reloc: Relocation address for loading single-segment overlays, or 0 for 3119 * no relocation 3120 * @autostart: TRUE if DSP starts after loading; ignored if ovly is TRUE 3121 * @router_chans: number of audio router channels to be allocated (0 means use 3122 * internal defaults; max is 32) 3123 * 3124 * Download DSP from a DSP Image Fast Load structure. This structure is a 3125 * linear, non-constant sized element array of structures, each of which 3126 * contain the count of the data to be loaded, the data itself, and the 3127 * corresponding starting chip address of the starting data location. 3128 * Returns zero or a negative error code. 3129 */ 3130 static int dspload_image(struct hda_codec *codec, 3131 const struct dsp_image_seg *fls, 3132 bool ovly, 3133 unsigned int reloc, 3134 bool autostart, 3135 int router_chans) 3136 { 3137 int status = 0; 3138 unsigned int sample_rate; 3139 unsigned short channels; 3140 3141 codec_dbg(codec, "---- dspload_image begin ------\n"); 3142 if (router_chans == 0) { 3143 if (!ovly) 3144 router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS; 3145 else 3146 router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS; 3147 } 3148 3149 sample_rate = 48000; 3150 channels = (unsigned short)router_chans; 3151 3152 while (channels > 16) { 3153 sample_rate *= 2; 3154 channels /= 2; 3155 } 3156 3157 do { 3158 codec_dbg(codec, "Ready to program DMA\n"); 3159 if (!ovly) 3160 status = dsp_reset(codec); 3161 3162 if (status < 0) 3163 break; 3164 3165 codec_dbg(codec, "dsp_reset() complete\n"); 3166 status = dspxfr_image(codec, fls, reloc, sample_rate, channels, 3167 ovly); 3168 3169 if (status < 0) 3170 break; 3171 3172 codec_dbg(codec, "dspxfr_image() complete\n"); 3173 if (autostart && !ovly) { 3174 dspload_post_setup(codec); 3175 status = dsp_set_run_state(codec); 3176 } 3177 3178 codec_dbg(codec, "LOAD FINISHED\n"); 3179 } while (0); 3180 3181 return status; 3182 } 3183 3184 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP 3185 static bool dspload_is_loaded(struct hda_codec *codec) 3186 { 3187 unsigned int data = 0; 3188 int status = 0; 3189 3190 status = chipio_read(codec, 0x40004, &data); 3191 if ((status < 0) || (data != 1)) 3192 return false; 3193 3194 return true; 3195 } 3196 #else 3197 #define dspload_is_loaded(codec) false 3198 #endif 3199 3200 static bool dspload_wait_loaded(struct hda_codec *codec) 3201 { 3202 unsigned long timeout = jiffies + msecs_to_jiffies(2000); 3203 3204 do { 3205 if (dspload_is_loaded(codec)) { 3206 codec_info(codec, "ca0132 DSP downloaded and running\n"); 3207 return true; 3208 } 3209 msleep(20); 3210 } while (time_before(jiffies, timeout)); 3211 3212 codec_err(codec, "ca0132 failed to download DSP\n"); 3213 return false; 3214 } 3215 3216 /* 3217 * ca0113 related functions. The ca0113 acts as the HDA bus for the pci-e 3218 * based cards, and has a second mmio region, region2, that's used for special 3219 * commands. 3220 */ 3221 3222 /* 3223 * For cards with PCI-E region2 (Sound Blaster Z/ZxR, Recon3D, and AE-5) 3224 * the mmio address 0x320 is used to set GPIO pins. The format for the data 3225 * The first eight bits are just the number of the pin. So far, I've only seen 3226 * this number go to 7. 3227 * AE-5 note: The AE-5 seems to use pins 2 and 3 to somehow set the color value 3228 * of the on-card LED. It seems to use pin 2 for data, then toggles 3 to on and 3229 * then off to send that bit. 3230 */ 3231 static void ca0113_mmio_gpio_set(struct hda_codec *codec, unsigned int gpio_pin, 3232 bool enable) 3233 { 3234 struct ca0132_spec *spec = codec->spec; 3235 unsigned short gpio_data; 3236 3237 gpio_data = gpio_pin & 0xF; 3238 gpio_data |= ((enable << 8) & 0x100); 3239 3240 writew(gpio_data, spec->mem_base + 0x320); 3241 } 3242 3243 /* 3244 * Special pci region2 commands that are only used by the AE-5. They follow 3245 * a set format, and require reads at certain points to seemingly 'clear' 3246 * the response data. My first tests didn't do these reads, and would cause 3247 * the card to get locked up until the memory was read. These commands 3248 * seem to work with three distinct values that I've taken to calling group, 3249 * target-id, and value. 3250 */ 3251 static void ca0113_mmio_command_set(struct hda_codec *codec, unsigned int group, 3252 unsigned int target, unsigned int value) 3253 { 3254 struct ca0132_spec *spec = codec->spec; 3255 unsigned int write_val; 3256 3257 writel(0x0000007e, spec->mem_base + 0x210); 3258 readl(spec->mem_base + 0x210); 3259 writel(0x0000005a, spec->mem_base + 0x210); 3260 readl(spec->mem_base + 0x210); 3261 readl(spec->mem_base + 0x210); 3262 3263 writel(0x00800005, spec->mem_base + 0x20c); 3264 writel(group, spec->mem_base + 0x804); 3265 3266 writel(0x00800005, spec->mem_base + 0x20c); 3267 write_val = (target & 0xff); 3268 write_val |= (value << 8); 3269 3270 3271 writel(write_val, spec->mem_base + 0x204); 3272 /* 3273 * Need delay here or else it goes too fast and works inconsistently. 3274 */ 3275 msleep(20); 3276 3277 readl(spec->mem_base + 0x860); 3278 readl(spec->mem_base + 0x854); 3279 readl(spec->mem_base + 0x840); 3280 3281 writel(0x00800004, spec->mem_base + 0x20c); 3282 writel(0x00000000, spec->mem_base + 0x210); 3283 readl(spec->mem_base + 0x210); 3284 readl(spec->mem_base + 0x210); 3285 } 3286 3287 /* 3288 * This second type of command is used for setting the sound filter type. 3289 */ 3290 static void ca0113_mmio_command_set_type2(struct hda_codec *codec, 3291 unsigned int group, unsigned int target, unsigned int value) 3292 { 3293 struct ca0132_spec *spec = codec->spec; 3294 unsigned int write_val; 3295 3296 writel(0x0000007e, spec->mem_base + 0x210); 3297 readl(spec->mem_base + 0x210); 3298 writel(0x0000005a, spec->mem_base + 0x210); 3299 readl(spec->mem_base + 0x210); 3300 readl(spec->mem_base + 0x210); 3301 3302 writel(0x00800003, spec->mem_base + 0x20c); 3303 writel(group, spec->mem_base + 0x804); 3304 3305 writel(0x00800005, spec->mem_base + 0x20c); 3306 write_val = (target & 0xff); 3307 write_val |= (value << 8); 3308 3309 3310 writel(write_val, spec->mem_base + 0x204); 3311 msleep(20); 3312 readl(spec->mem_base + 0x860); 3313 readl(spec->mem_base + 0x854); 3314 readl(spec->mem_base + 0x840); 3315 3316 writel(0x00800004, spec->mem_base + 0x20c); 3317 writel(0x00000000, spec->mem_base + 0x210); 3318 readl(spec->mem_base + 0x210); 3319 readl(spec->mem_base + 0x210); 3320 } 3321 3322 /* 3323 * Setup GPIO for the other variants of Core3D. 3324 */ 3325 3326 /* 3327 * Sets up the GPIO pins so that they are discoverable. If this isn't done, 3328 * the card shows as having no GPIO pins. 3329 */ 3330 static void ca0132_gpio_init(struct hda_codec *codec) 3331 { 3332 struct ca0132_spec *spec = codec->spec; 3333 3334 switch (ca0132_quirk(spec)) { 3335 case QUIRK_SBZ: 3336 case QUIRK_AE5: 3337 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 3338 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53); 3339 snd_hda_codec_write(codec, 0x01, 0, 0x790, 0x23); 3340 break; 3341 case QUIRK_R3DI: 3342 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 3343 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5B); 3344 break; 3345 default: 3346 break; 3347 } 3348 3349 } 3350 3351 /* Sets the GPIO for audio output. */ 3352 static void ca0132_gpio_setup(struct hda_codec *codec) 3353 { 3354 struct ca0132_spec *spec = codec->spec; 3355 3356 switch (ca0132_quirk(spec)) { 3357 case QUIRK_SBZ: 3358 snd_hda_codec_write(codec, 0x01, 0, 3359 AC_VERB_SET_GPIO_DIRECTION, 0x07); 3360 snd_hda_codec_write(codec, 0x01, 0, 3361 AC_VERB_SET_GPIO_MASK, 0x07); 3362 snd_hda_codec_write(codec, 0x01, 0, 3363 AC_VERB_SET_GPIO_DATA, 0x04); 3364 snd_hda_codec_write(codec, 0x01, 0, 3365 AC_VERB_SET_GPIO_DATA, 0x06); 3366 break; 3367 case QUIRK_R3DI: 3368 snd_hda_codec_write(codec, 0x01, 0, 3369 AC_VERB_SET_GPIO_DIRECTION, 0x1E); 3370 snd_hda_codec_write(codec, 0x01, 0, 3371 AC_VERB_SET_GPIO_MASK, 0x1F); 3372 snd_hda_codec_write(codec, 0x01, 0, 3373 AC_VERB_SET_GPIO_DATA, 0x0C); 3374 break; 3375 default: 3376 break; 3377 } 3378 } 3379 3380 /* 3381 * GPIO control functions for the Recon3D integrated. 3382 */ 3383 3384 enum r3di_gpio_bit { 3385 /* Bit 1 - Switch between front/rear mic. 0 = rear, 1 = front */ 3386 R3DI_MIC_SELECT_BIT = 1, 3387 /* Bit 2 - Switch between headphone/line out. 0 = Headphone, 1 = Line */ 3388 R3DI_OUT_SELECT_BIT = 2, 3389 /* 3390 * I dunno what this actually does, but it stays on until the dsp 3391 * is downloaded. 3392 */ 3393 R3DI_GPIO_DSP_DOWNLOADING = 3, 3394 /* 3395 * Same as above, no clue what it does, but it comes on after the dsp 3396 * is downloaded. 3397 */ 3398 R3DI_GPIO_DSP_DOWNLOADED = 4 3399 }; 3400 3401 enum r3di_mic_select { 3402 /* Set GPIO bit 1 to 0 for rear mic */ 3403 R3DI_REAR_MIC = 0, 3404 /* Set GPIO bit 1 to 1 for front microphone*/ 3405 R3DI_FRONT_MIC = 1 3406 }; 3407 3408 enum r3di_out_select { 3409 /* Set GPIO bit 2 to 0 for headphone */ 3410 R3DI_HEADPHONE_OUT = 0, 3411 /* Set GPIO bit 2 to 1 for speaker */ 3412 R3DI_LINE_OUT = 1 3413 }; 3414 enum r3di_dsp_status { 3415 /* Set GPIO bit 3 to 1 until DSP is downloaded */ 3416 R3DI_DSP_DOWNLOADING = 0, 3417 /* Set GPIO bit 4 to 1 once DSP is downloaded */ 3418 R3DI_DSP_DOWNLOADED = 1 3419 }; 3420 3421 3422 static void r3di_gpio_mic_set(struct hda_codec *codec, 3423 enum r3di_mic_select cur_mic) 3424 { 3425 unsigned int cur_gpio; 3426 3427 /* Get the current GPIO Data setup */ 3428 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0); 3429 3430 switch (cur_mic) { 3431 case R3DI_REAR_MIC: 3432 cur_gpio &= ~(1 << R3DI_MIC_SELECT_BIT); 3433 break; 3434 case R3DI_FRONT_MIC: 3435 cur_gpio |= (1 << R3DI_MIC_SELECT_BIT); 3436 break; 3437 } 3438 snd_hda_codec_write(codec, codec->core.afg, 0, 3439 AC_VERB_SET_GPIO_DATA, cur_gpio); 3440 } 3441 3442 static void r3di_gpio_out_set(struct hda_codec *codec, 3443 enum r3di_out_select cur_out) 3444 { 3445 unsigned int cur_gpio; 3446 3447 /* Get the current GPIO Data setup */ 3448 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0); 3449 3450 switch (cur_out) { 3451 case R3DI_HEADPHONE_OUT: 3452 cur_gpio &= ~(1 << R3DI_OUT_SELECT_BIT); 3453 break; 3454 case R3DI_LINE_OUT: 3455 cur_gpio |= (1 << R3DI_OUT_SELECT_BIT); 3456 break; 3457 } 3458 snd_hda_codec_write(codec, codec->core.afg, 0, 3459 AC_VERB_SET_GPIO_DATA, cur_gpio); 3460 } 3461 3462 static void r3di_gpio_dsp_status_set(struct hda_codec *codec, 3463 enum r3di_dsp_status dsp_status) 3464 { 3465 unsigned int cur_gpio; 3466 3467 /* Get the current GPIO Data setup */ 3468 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0); 3469 3470 switch (dsp_status) { 3471 case R3DI_DSP_DOWNLOADING: 3472 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADING); 3473 snd_hda_codec_write(codec, codec->core.afg, 0, 3474 AC_VERB_SET_GPIO_DATA, cur_gpio); 3475 break; 3476 case R3DI_DSP_DOWNLOADED: 3477 /* Set DOWNLOADING bit to 0. */ 3478 cur_gpio &= ~(1 << R3DI_GPIO_DSP_DOWNLOADING); 3479 3480 snd_hda_codec_write(codec, codec->core.afg, 0, 3481 AC_VERB_SET_GPIO_DATA, cur_gpio); 3482 3483 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADED); 3484 break; 3485 } 3486 3487 snd_hda_codec_write(codec, codec->core.afg, 0, 3488 AC_VERB_SET_GPIO_DATA, cur_gpio); 3489 } 3490 3491 /* 3492 * PCM callbacks 3493 */ 3494 static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 3495 struct hda_codec *codec, 3496 unsigned int stream_tag, 3497 unsigned int format, 3498 struct snd_pcm_substream *substream) 3499 { 3500 struct ca0132_spec *spec = codec->spec; 3501 3502 snd_hda_codec_setup_stream(codec, spec->dacs[0], stream_tag, 0, format); 3503 3504 return 0; 3505 } 3506 3507 static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo, 3508 struct hda_codec *codec, 3509 struct snd_pcm_substream *substream) 3510 { 3511 struct ca0132_spec *spec = codec->spec; 3512 3513 if (spec->dsp_state == DSP_DOWNLOADING) 3514 return 0; 3515 3516 /*If Playback effects are on, allow stream some time to flush 3517 *effects tail*/ 3518 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) 3519 msleep(50); 3520 3521 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]); 3522 3523 return 0; 3524 } 3525 3526 static unsigned int ca0132_playback_pcm_delay(struct hda_pcm_stream *info, 3527 struct hda_codec *codec, 3528 struct snd_pcm_substream *substream) 3529 { 3530 struct ca0132_spec *spec = codec->spec; 3531 unsigned int latency = DSP_PLAYBACK_INIT_LATENCY; 3532 struct snd_pcm_runtime *runtime = substream->runtime; 3533 3534 if (spec->dsp_state != DSP_DOWNLOADED) 3535 return 0; 3536 3537 /* Add latency if playback enhancement and either effect is enabled. */ 3538 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) { 3539 if ((spec->effects_switch[SURROUND - EFFECT_START_NID]) || 3540 (spec->effects_switch[DIALOG_PLUS - EFFECT_START_NID])) 3541 latency += DSP_PLAY_ENHANCEMENT_LATENCY; 3542 } 3543 3544 /* Applying Speaker EQ adds latency as well. */ 3545 if (spec->cur_out_type == SPEAKER_OUT) 3546 latency += DSP_SPEAKER_OUT_LATENCY; 3547 3548 return (latency * runtime->rate) / 1000; 3549 } 3550 3551 /* 3552 * Digital out 3553 */ 3554 static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo, 3555 struct hda_codec *codec, 3556 struct snd_pcm_substream *substream) 3557 { 3558 struct ca0132_spec *spec = codec->spec; 3559 return snd_hda_multi_out_dig_open(codec, &spec->multiout); 3560 } 3561 3562 static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 3563 struct hda_codec *codec, 3564 unsigned int stream_tag, 3565 unsigned int format, 3566 struct snd_pcm_substream *substream) 3567 { 3568 struct ca0132_spec *spec = codec->spec; 3569 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout, 3570 stream_tag, format, substream); 3571 } 3572 3573 static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo, 3574 struct hda_codec *codec, 3575 struct snd_pcm_substream *substream) 3576 { 3577 struct ca0132_spec *spec = codec->spec; 3578 return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout); 3579 } 3580 3581 static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo, 3582 struct hda_codec *codec, 3583 struct snd_pcm_substream *substream) 3584 { 3585 struct ca0132_spec *spec = codec->spec; 3586 return snd_hda_multi_out_dig_close(codec, &spec->multiout); 3587 } 3588 3589 /* 3590 * Analog capture 3591 */ 3592 static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo, 3593 struct hda_codec *codec, 3594 unsigned int stream_tag, 3595 unsigned int format, 3596 struct snd_pcm_substream *substream) 3597 { 3598 snd_hda_codec_setup_stream(codec, hinfo->nid, 3599 stream_tag, 0, format); 3600 3601 return 0; 3602 } 3603 3604 static int ca0132_capture_pcm_cleanup(struct hda_pcm_stream *hinfo, 3605 struct hda_codec *codec, 3606 struct snd_pcm_substream *substream) 3607 { 3608 struct ca0132_spec *spec = codec->spec; 3609 3610 if (spec->dsp_state == DSP_DOWNLOADING) 3611 return 0; 3612 3613 snd_hda_codec_cleanup_stream(codec, hinfo->nid); 3614 return 0; 3615 } 3616 3617 static unsigned int ca0132_capture_pcm_delay(struct hda_pcm_stream *info, 3618 struct hda_codec *codec, 3619 struct snd_pcm_substream *substream) 3620 { 3621 struct ca0132_spec *spec = codec->spec; 3622 unsigned int latency = DSP_CAPTURE_INIT_LATENCY; 3623 struct snd_pcm_runtime *runtime = substream->runtime; 3624 3625 if (spec->dsp_state != DSP_DOWNLOADED) 3626 return 0; 3627 3628 if (spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]) 3629 latency += DSP_CRYSTAL_VOICE_LATENCY; 3630 3631 return (latency * runtime->rate) / 1000; 3632 } 3633 3634 /* 3635 * Controls stuffs. 3636 */ 3637 3638 /* 3639 * Mixer controls helpers. 3640 */ 3641 #define CA0132_CODEC_VOL_MONO(xname, nid, channel, dir) \ 3642 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3643 .name = xname, \ 3644 .subdevice = HDA_SUBDEV_AMP_FLAG, \ 3645 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \ 3646 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \ 3647 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \ 3648 .info = ca0132_volume_info, \ 3649 .get = ca0132_volume_get, \ 3650 .put = ca0132_volume_put, \ 3651 .tlv = { .c = ca0132_volume_tlv }, \ 3652 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) } 3653 3654 /* 3655 * Creates a mixer control that uses defaults of HDA_CODEC_VOL except for the 3656 * volume put, which is used for setting the DSP volume. This was done because 3657 * the ca0132 functions were taking too much time and causing lag. 3658 */ 3659 #define CA0132_ALT_CODEC_VOL_MONO(xname, nid, channel, dir) \ 3660 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3661 .name = xname, \ 3662 .subdevice = HDA_SUBDEV_AMP_FLAG, \ 3663 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \ 3664 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \ 3665 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \ 3666 .info = snd_hda_mixer_amp_volume_info, \ 3667 .get = snd_hda_mixer_amp_volume_get, \ 3668 .put = ca0132_alt_volume_put, \ 3669 .tlv = { .c = snd_hda_mixer_amp_tlv }, \ 3670 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) } 3671 3672 #define CA0132_CODEC_MUTE_MONO(xname, nid, channel, dir) \ 3673 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3674 .name = xname, \ 3675 .subdevice = HDA_SUBDEV_AMP_FLAG, \ 3676 .info = snd_hda_mixer_amp_switch_info, \ 3677 .get = ca0132_switch_get, \ 3678 .put = ca0132_switch_put, \ 3679 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) } 3680 3681 /* stereo */ 3682 #define CA0132_CODEC_VOL(xname, nid, dir) \ 3683 CA0132_CODEC_VOL_MONO(xname, nid, 3, dir) 3684 #define CA0132_ALT_CODEC_VOL(xname, nid, dir) \ 3685 CA0132_ALT_CODEC_VOL_MONO(xname, nid, 3, dir) 3686 #define CA0132_CODEC_MUTE(xname, nid, dir) \ 3687 CA0132_CODEC_MUTE_MONO(xname, nid, 3, dir) 3688 3689 /* lookup tables */ 3690 /* 3691 * Lookup table with decibel values for the DSP. When volume is changed in 3692 * Windows, the DSP is also sent the dB value in floating point. In Windows, 3693 * these values have decimal points, probably because the Windows driver 3694 * actually uses floating point. We can't here, so I made a lookup table of 3695 * values -90 to 9. -90 is the lowest decibel value for both the ADC's and the 3696 * DAC's, and 9 is the maximum. 3697 */ 3698 static const unsigned int float_vol_db_lookup[] = { 3699 0xC2B40000, 0xC2B20000, 0xC2B00000, 0xC2AE0000, 0xC2AC0000, 0xC2AA0000, 3700 0xC2A80000, 0xC2A60000, 0xC2A40000, 0xC2A20000, 0xC2A00000, 0xC29E0000, 3701 0xC29C0000, 0xC29A0000, 0xC2980000, 0xC2960000, 0xC2940000, 0xC2920000, 3702 0xC2900000, 0xC28E0000, 0xC28C0000, 0xC28A0000, 0xC2880000, 0xC2860000, 3703 0xC2840000, 0xC2820000, 0xC2800000, 0xC27C0000, 0xC2780000, 0xC2740000, 3704 0xC2700000, 0xC26C0000, 0xC2680000, 0xC2640000, 0xC2600000, 0xC25C0000, 3705 0xC2580000, 0xC2540000, 0xC2500000, 0xC24C0000, 0xC2480000, 0xC2440000, 3706 0xC2400000, 0xC23C0000, 0xC2380000, 0xC2340000, 0xC2300000, 0xC22C0000, 3707 0xC2280000, 0xC2240000, 0xC2200000, 0xC21C0000, 0xC2180000, 0xC2140000, 3708 0xC2100000, 0xC20C0000, 0xC2080000, 0xC2040000, 0xC2000000, 0xC1F80000, 3709 0xC1F00000, 0xC1E80000, 0xC1E00000, 0xC1D80000, 0xC1D00000, 0xC1C80000, 3710 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000, 3711 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000, 3712 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000, 3713 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000, 3714 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000, 3715 0x40C00000, 0x40E00000, 0x41000000, 0x41100000 3716 }; 3717 3718 /* 3719 * This table counts from float 0 to 1 in increments of .01, which is 3720 * useful for a few different sliders. 3721 */ 3722 static const unsigned int float_zero_to_one_lookup[] = { 3723 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD, 3724 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE, 3725 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B, 3726 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F, 3727 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1, 3728 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333, 3729 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85, 3730 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7, 3731 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14, 3732 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D, 3733 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666, 3734 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F, 3735 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8, 3736 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1, 3737 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A, 3738 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333, 3739 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000 3740 }; 3741 3742 /* 3743 * This table counts from float 10 to 1000, which is the range of the x-bass 3744 * crossover slider in Windows. 3745 */ 3746 static const unsigned int float_xbass_xover_lookup[] = { 3747 0x41200000, 0x41A00000, 0x41F00000, 0x42200000, 0x42480000, 0x42700000, 3748 0x428C0000, 0x42A00000, 0x42B40000, 0x42C80000, 0x42DC0000, 0x42F00000, 3749 0x43020000, 0x430C0000, 0x43160000, 0x43200000, 0x432A0000, 0x43340000, 3750 0x433E0000, 0x43480000, 0x43520000, 0x435C0000, 0x43660000, 0x43700000, 3751 0x437A0000, 0x43820000, 0x43870000, 0x438C0000, 0x43910000, 0x43960000, 3752 0x439B0000, 0x43A00000, 0x43A50000, 0x43AA0000, 0x43AF0000, 0x43B40000, 3753 0x43B90000, 0x43BE0000, 0x43C30000, 0x43C80000, 0x43CD0000, 0x43D20000, 3754 0x43D70000, 0x43DC0000, 0x43E10000, 0x43E60000, 0x43EB0000, 0x43F00000, 3755 0x43F50000, 0x43FA0000, 0x43FF0000, 0x44020000, 0x44048000, 0x44070000, 3756 0x44098000, 0x440C0000, 0x440E8000, 0x44110000, 0x44138000, 0x44160000, 3757 0x44188000, 0x441B0000, 0x441D8000, 0x44200000, 0x44228000, 0x44250000, 3758 0x44278000, 0x442A0000, 0x442C8000, 0x442F0000, 0x44318000, 0x44340000, 3759 0x44368000, 0x44390000, 0x443B8000, 0x443E0000, 0x44408000, 0x44430000, 3760 0x44458000, 0x44480000, 0x444A8000, 0x444D0000, 0x444F8000, 0x44520000, 3761 0x44548000, 0x44570000, 0x44598000, 0x445C0000, 0x445E8000, 0x44610000, 3762 0x44638000, 0x44660000, 0x44688000, 0x446B0000, 0x446D8000, 0x44700000, 3763 0x44728000, 0x44750000, 0x44778000, 0x447A0000 3764 }; 3765 3766 /* The following are for tuning of products */ 3767 #ifdef ENABLE_TUNING_CONTROLS 3768 3769 static unsigned int voice_focus_vals_lookup[] = { 3770 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000, 0x41C80000, 3771 0x41D00000, 0x41D80000, 0x41E00000, 0x41E80000, 0x41F00000, 0x41F80000, 3772 0x42000000, 0x42040000, 0x42080000, 0x420C0000, 0x42100000, 0x42140000, 3773 0x42180000, 0x421C0000, 0x42200000, 0x42240000, 0x42280000, 0x422C0000, 3774 0x42300000, 0x42340000, 0x42380000, 0x423C0000, 0x42400000, 0x42440000, 3775 0x42480000, 0x424C0000, 0x42500000, 0x42540000, 0x42580000, 0x425C0000, 3776 0x42600000, 0x42640000, 0x42680000, 0x426C0000, 0x42700000, 0x42740000, 3777 0x42780000, 0x427C0000, 0x42800000, 0x42820000, 0x42840000, 0x42860000, 3778 0x42880000, 0x428A0000, 0x428C0000, 0x428E0000, 0x42900000, 0x42920000, 3779 0x42940000, 0x42960000, 0x42980000, 0x429A0000, 0x429C0000, 0x429E0000, 3780 0x42A00000, 0x42A20000, 0x42A40000, 0x42A60000, 0x42A80000, 0x42AA0000, 3781 0x42AC0000, 0x42AE0000, 0x42B00000, 0x42B20000, 0x42B40000, 0x42B60000, 3782 0x42B80000, 0x42BA0000, 0x42BC0000, 0x42BE0000, 0x42C00000, 0x42C20000, 3783 0x42C40000, 0x42C60000, 0x42C80000, 0x42CA0000, 0x42CC0000, 0x42CE0000, 3784 0x42D00000, 0x42D20000, 0x42D40000, 0x42D60000, 0x42D80000, 0x42DA0000, 3785 0x42DC0000, 0x42DE0000, 0x42E00000, 0x42E20000, 0x42E40000, 0x42E60000, 3786 0x42E80000, 0x42EA0000, 0x42EC0000, 0x42EE0000, 0x42F00000, 0x42F20000, 3787 0x42F40000, 0x42F60000, 0x42F80000, 0x42FA0000, 0x42FC0000, 0x42FE0000, 3788 0x43000000, 0x43010000, 0x43020000, 0x43030000, 0x43040000, 0x43050000, 3789 0x43060000, 0x43070000, 0x43080000, 0x43090000, 0x430A0000, 0x430B0000, 3790 0x430C0000, 0x430D0000, 0x430E0000, 0x430F0000, 0x43100000, 0x43110000, 3791 0x43120000, 0x43130000, 0x43140000, 0x43150000, 0x43160000, 0x43170000, 3792 0x43180000, 0x43190000, 0x431A0000, 0x431B0000, 0x431C0000, 0x431D0000, 3793 0x431E0000, 0x431F0000, 0x43200000, 0x43210000, 0x43220000, 0x43230000, 3794 0x43240000, 0x43250000, 0x43260000, 0x43270000, 0x43280000, 0x43290000, 3795 0x432A0000, 0x432B0000, 0x432C0000, 0x432D0000, 0x432E0000, 0x432F0000, 3796 0x43300000, 0x43310000, 0x43320000, 0x43330000, 0x43340000 3797 }; 3798 3799 static unsigned int mic_svm_vals_lookup[] = { 3800 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD, 3801 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE, 3802 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B, 3803 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F, 3804 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1, 3805 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333, 3806 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85, 3807 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7, 3808 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14, 3809 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D, 3810 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666, 3811 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F, 3812 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8, 3813 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1, 3814 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A, 3815 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333, 3816 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000 3817 }; 3818 3819 static unsigned int equalizer_vals_lookup[] = { 3820 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000, 3821 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000, 3822 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000, 3823 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000, 3824 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000, 3825 0x40C00000, 0x40E00000, 0x41000000, 0x41100000, 0x41200000, 0x41300000, 3826 0x41400000, 0x41500000, 0x41600000, 0x41700000, 0x41800000, 0x41880000, 3827 0x41900000, 0x41980000, 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 3828 0x41C00000 3829 }; 3830 3831 static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid, 3832 unsigned int *lookup, int idx) 3833 { 3834 int i = 0; 3835 3836 for (i = 0; i < TUNING_CTLS_COUNT; i++) 3837 if (nid == ca0132_tuning_ctls[i].nid) 3838 break; 3839 3840 snd_hda_power_up(codec); 3841 dspio_set_param(codec, ca0132_tuning_ctls[i].mid, 0x20, 3842 ca0132_tuning_ctls[i].req, 3843 &(lookup[idx]), sizeof(unsigned int)); 3844 snd_hda_power_down(codec); 3845 3846 return 1; 3847 } 3848 3849 static int tuning_ctl_get(struct snd_kcontrol *kcontrol, 3850 struct snd_ctl_elem_value *ucontrol) 3851 { 3852 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 3853 struct ca0132_spec *spec = codec->spec; 3854 hda_nid_t nid = get_amp_nid(kcontrol); 3855 long *valp = ucontrol->value.integer.value; 3856 int idx = nid - TUNING_CTL_START_NID; 3857 3858 *valp = spec->cur_ctl_vals[idx]; 3859 return 0; 3860 } 3861 3862 static int voice_focus_ctl_info(struct snd_kcontrol *kcontrol, 3863 struct snd_ctl_elem_info *uinfo) 3864 { 3865 int chs = get_amp_channels(kcontrol); 3866 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 3867 uinfo->count = chs == 3 ? 2 : 1; 3868 uinfo->value.integer.min = 20; 3869 uinfo->value.integer.max = 180; 3870 uinfo->value.integer.step = 1; 3871 3872 return 0; 3873 } 3874 3875 static int voice_focus_ctl_put(struct snd_kcontrol *kcontrol, 3876 struct snd_ctl_elem_value *ucontrol) 3877 { 3878 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 3879 struct ca0132_spec *spec = codec->spec; 3880 hda_nid_t nid = get_amp_nid(kcontrol); 3881 long *valp = ucontrol->value.integer.value; 3882 int idx; 3883 3884 idx = nid - TUNING_CTL_START_NID; 3885 /* any change? */ 3886 if (spec->cur_ctl_vals[idx] == *valp) 3887 return 0; 3888 3889 spec->cur_ctl_vals[idx] = *valp; 3890 3891 idx = *valp - 20; 3892 tuning_ctl_set(codec, nid, voice_focus_vals_lookup, idx); 3893 3894 return 1; 3895 } 3896 3897 static int mic_svm_ctl_info(struct snd_kcontrol *kcontrol, 3898 struct snd_ctl_elem_info *uinfo) 3899 { 3900 int chs = get_amp_channels(kcontrol); 3901 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 3902 uinfo->count = chs == 3 ? 2 : 1; 3903 uinfo->value.integer.min = 0; 3904 uinfo->value.integer.max = 100; 3905 uinfo->value.integer.step = 1; 3906 3907 return 0; 3908 } 3909 3910 static int mic_svm_ctl_put(struct snd_kcontrol *kcontrol, 3911 struct snd_ctl_elem_value *ucontrol) 3912 { 3913 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 3914 struct ca0132_spec *spec = codec->spec; 3915 hda_nid_t nid = get_amp_nid(kcontrol); 3916 long *valp = ucontrol->value.integer.value; 3917 int idx; 3918 3919 idx = nid - TUNING_CTL_START_NID; 3920 /* any change? */ 3921 if (spec->cur_ctl_vals[idx] == *valp) 3922 return 0; 3923 3924 spec->cur_ctl_vals[idx] = *valp; 3925 3926 idx = *valp; 3927 tuning_ctl_set(codec, nid, mic_svm_vals_lookup, idx); 3928 3929 return 0; 3930 } 3931 3932 static int equalizer_ctl_info(struct snd_kcontrol *kcontrol, 3933 struct snd_ctl_elem_info *uinfo) 3934 { 3935 int chs = get_amp_channels(kcontrol); 3936 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 3937 uinfo->count = chs == 3 ? 2 : 1; 3938 uinfo->value.integer.min = 0; 3939 uinfo->value.integer.max = 48; 3940 uinfo->value.integer.step = 1; 3941 3942 return 0; 3943 } 3944 3945 static int equalizer_ctl_put(struct snd_kcontrol *kcontrol, 3946 struct snd_ctl_elem_value *ucontrol) 3947 { 3948 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 3949 struct ca0132_spec *spec = codec->spec; 3950 hda_nid_t nid = get_amp_nid(kcontrol); 3951 long *valp = ucontrol->value.integer.value; 3952 int idx; 3953 3954 idx = nid - TUNING_CTL_START_NID; 3955 /* any change? */ 3956 if (spec->cur_ctl_vals[idx] == *valp) 3957 return 0; 3958 3959 spec->cur_ctl_vals[idx] = *valp; 3960 3961 idx = *valp; 3962 tuning_ctl_set(codec, nid, equalizer_vals_lookup, idx); 3963 3964 return 1; 3965 } 3966 3967 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(voice_focus_db_scale, 2000, 100, 0); 3968 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(eq_db_scale, -2400, 100, 0); 3969 3970 static int add_tuning_control(struct hda_codec *codec, 3971 hda_nid_t pnid, hda_nid_t nid, 3972 const char *name, int dir) 3973 { 3974 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 3975 int type = dir ? HDA_INPUT : HDA_OUTPUT; 3976 struct snd_kcontrol_new knew = 3977 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type); 3978 3979 knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE | 3980 SNDRV_CTL_ELEM_ACCESS_TLV_READ; 3981 knew.tlv.c = 0; 3982 knew.tlv.p = 0; 3983 switch (pnid) { 3984 case VOICE_FOCUS: 3985 knew.info = voice_focus_ctl_info; 3986 knew.get = tuning_ctl_get; 3987 knew.put = voice_focus_ctl_put; 3988 knew.tlv.p = voice_focus_db_scale; 3989 break; 3990 case MIC_SVM: 3991 knew.info = mic_svm_ctl_info; 3992 knew.get = tuning_ctl_get; 3993 knew.put = mic_svm_ctl_put; 3994 break; 3995 case EQUALIZER: 3996 knew.info = equalizer_ctl_info; 3997 knew.get = tuning_ctl_get; 3998 knew.put = equalizer_ctl_put; 3999 knew.tlv.p = eq_db_scale; 4000 break; 4001 default: 4002 return 0; 4003 } 4004 knew.private_value = 4005 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type); 4006 sprintf(namestr, "%s %s Volume", name, dirstr[dir]); 4007 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec)); 4008 } 4009 4010 static int add_tuning_ctls(struct hda_codec *codec) 4011 { 4012 int i; 4013 int err; 4014 4015 for (i = 0; i < TUNING_CTLS_COUNT; i++) { 4016 err = add_tuning_control(codec, 4017 ca0132_tuning_ctls[i].parent_nid, 4018 ca0132_tuning_ctls[i].nid, 4019 ca0132_tuning_ctls[i].name, 4020 ca0132_tuning_ctls[i].direct); 4021 if (err < 0) 4022 return err; 4023 } 4024 4025 return 0; 4026 } 4027 4028 static void ca0132_init_tuning_defaults(struct hda_codec *codec) 4029 { 4030 struct ca0132_spec *spec = codec->spec; 4031 int i; 4032 4033 /* Wedge Angle defaults to 30. 10 below is 30 - 20. 20 is min. */ 4034 spec->cur_ctl_vals[WEDGE_ANGLE - TUNING_CTL_START_NID] = 10; 4035 /* SVM level defaults to 0.74. */ 4036 spec->cur_ctl_vals[SVM_LEVEL - TUNING_CTL_START_NID] = 74; 4037 4038 /* EQ defaults to 0dB. */ 4039 for (i = 2; i < TUNING_CTLS_COUNT; i++) 4040 spec->cur_ctl_vals[i] = 24; 4041 } 4042 #endif /*ENABLE_TUNING_CONTROLS*/ 4043 4044 /* 4045 * Select the active output. 4046 * If autodetect is enabled, output will be selected based on jack detection. 4047 * If jack inserted, headphone will be selected, else built-in speakers 4048 * If autodetect is disabled, output will be selected based on selection. 4049 */ 4050 static int ca0132_select_out(struct hda_codec *codec) 4051 { 4052 struct ca0132_spec *spec = codec->spec; 4053 unsigned int pin_ctl; 4054 int jack_present; 4055 int auto_jack; 4056 unsigned int tmp; 4057 int err; 4058 4059 codec_dbg(codec, "ca0132_select_out\n"); 4060 4061 snd_hda_power_up_pm(codec); 4062 4063 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID]; 4064 4065 if (auto_jack) 4066 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp); 4067 else 4068 jack_present = 4069 spec->vnode_lswitch[VNID_HP_SEL - VNODE_START_NID]; 4070 4071 if (jack_present) 4072 spec->cur_out_type = HEADPHONE_OUT; 4073 else 4074 spec->cur_out_type = SPEAKER_OUT; 4075 4076 if (spec->cur_out_type == SPEAKER_OUT) { 4077 codec_dbg(codec, "ca0132_select_out speaker\n"); 4078 /*speaker out config*/ 4079 tmp = FLOAT_ONE; 4080 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp); 4081 if (err < 0) 4082 goto exit; 4083 /*enable speaker EQ*/ 4084 tmp = FLOAT_ONE; 4085 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp); 4086 if (err < 0) 4087 goto exit; 4088 4089 /* Setup EAPD */ 4090 snd_hda_codec_write(codec, spec->out_pins[1], 0, 4091 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02); 4092 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4093 AC_VERB_SET_EAPD_BTLENABLE, 0x00); 4094 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4095 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00); 4096 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4097 AC_VERB_SET_EAPD_BTLENABLE, 0x02); 4098 4099 /* disable headphone node */ 4100 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0, 4101 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4102 snd_hda_set_pin_ctl(codec, spec->out_pins[1], 4103 pin_ctl & ~PIN_HP); 4104 /* enable speaker node */ 4105 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0, 4106 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4107 snd_hda_set_pin_ctl(codec, spec->out_pins[0], 4108 pin_ctl | PIN_OUT); 4109 } else { 4110 codec_dbg(codec, "ca0132_select_out hp\n"); 4111 /*headphone out config*/ 4112 tmp = FLOAT_ZERO; 4113 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp); 4114 if (err < 0) 4115 goto exit; 4116 /*disable speaker EQ*/ 4117 tmp = FLOAT_ZERO; 4118 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp); 4119 if (err < 0) 4120 goto exit; 4121 4122 /* Setup EAPD */ 4123 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4124 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00); 4125 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4126 AC_VERB_SET_EAPD_BTLENABLE, 0x00); 4127 snd_hda_codec_write(codec, spec->out_pins[1], 0, 4128 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02); 4129 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4130 AC_VERB_SET_EAPD_BTLENABLE, 0x02); 4131 4132 /* disable speaker*/ 4133 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0, 4134 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4135 snd_hda_set_pin_ctl(codec, spec->out_pins[0], 4136 pin_ctl & ~PIN_HP); 4137 /* enable headphone*/ 4138 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0, 4139 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4140 snd_hda_set_pin_ctl(codec, spec->out_pins[1], 4141 pin_ctl | PIN_HP); 4142 } 4143 4144 exit: 4145 snd_hda_power_down_pm(codec); 4146 4147 return err < 0 ? err : 0; 4148 } 4149 4150 static int ae5_headphone_gain_set(struct hda_codec *codec, long val); 4151 static int zxr_headphone_gain_set(struct hda_codec *codec, long val); 4152 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val); 4153 4154 static void ae5_mmio_select_out(struct hda_codec *codec) 4155 { 4156 struct ca0132_spec *spec = codec->spec; 4157 unsigned int i; 4158 4159 for (i = 0; i < AE5_CA0113_OUT_SET_COMMANDS; i++) 4160 ca0113_mmio_command_set(codec, 4161 ae5_ca0113_output_presets[spec->cur_out_type].group[i], 4162 ae5_ca0113_output_presets[spec->cur_out_type].target[i], 4163 ae5_ca0113_output_presets[spec->cur_out_type].vals[i]); 4164 } 4165 4166 /* 4167 * These are the commands needed to setup output on each of the different card 4168 * types. 4169 */ 4170 static void ca0132_alt_select_out_quirk_handler(struct hda_codec *codec) 4171 { 4172 struct ca0132_spec *spec = codec->spec; 4173 unsigned int tmp; 4174 4175 switch (spec->cur_out_type) { 4176 case SPEAKER_OUT: 4177 switch (ca0132_quirk(spec)) { 4178 case QUIRK_SBZ: 4179 ca0113_mmio_gpio_set(codec, 7, false); 4180 ca0113_mmio_gpio_set(codec, 4, true); 4181 ca0113_mmio_gpio_set(codec, 1, true); 4182 chipio_set_control_param(codec, 0x0d, 0x18); 4183 break; 4184 case QUIRK_ZXR: 4185 ca0113_mmio_gpio_set(codec, 2, true); 4186 ca0113_mmio_gpio_set(codec, 3, true); 4187 ca0113_mmio_gpio_set(codec, 5, false); 4188 zxr_headphone_gain_set(codec, 0); 4189 chipio_set_control_param(codec, 0x0d, 0x24); 4190 break; 4191 case QUIRK_R3DI: 4192 chipio_set_control_param(codec, 0x0d, 0x24); 4193 r3di_gpio_out_set(codec, R3DI_LINE_OUT); 4194 break; 4195 case QUIRK_R3D: 4196 chipio_set_control_param(codec, 0x0d, 0x24); 4197 ca0113_mmio_gpio_set(codec, 1, true); 4198 break; 4199 case QUIRK_AE5: 4200 ae5_mmio_select_out(codec); 4201 ae5_headphone_gain_set(codec, 2); 4202 tmp = FLOAT_ZERO; 4203 dspio_set_uint_param(codec, 0x96, 0x29, tmp); 4204 dspio_set_uint_param(codec, 0x96, 0x2a, tmp); 4205 chipio_set_control_param(codec, 0x0d, 0xa4); 4206 chipio_write(codec, 0x18b03c, 0x00000012); 4207 break; 4208 default: 4209 break; 4210 } 4211 break; 4212 case HEADPHONE_OUT: 4213 switch (ca0132_quirk(spec)) { 4214 case QUIRK_SBZ: 4215 ca0113_mmio_gpio_set(codec, 7, true); 4216 ca0113_mmio_gpio_set(codec, 4, true); 4217 ca0113_mmio_gpio_set(codec, 1, false); 4218 chipio_set_control_param(codec, 0x0d, 0x12); 4219 break; 4220 case QUIRK_ZXR: 4221 ca0113_mmio_gpio_set(codec, 2, false); 4222 ca0113_mmio_gpio_set(codec, 3, false); 4223 ca0113_mmio_gpio_set(codec, 5, true); 4224 zxr_headphone_gain_set(codec, spec->zxr_gain_set); 4225 chipio_set_control_param(codec, 0x0d, 0x21); 4226 break; 4227 case QUIRK_R3DI: 4228 chipio_set_control_param(codec, 0x0d, 0x21); 4229 r3di_gpio_out_set(codec, R3DI_HEADPHONE_OUT); 4230 break; 4231 case QUIRK_R3D: 4232 chipio_set_control_param(codec, 0x0d, 0x21); 4233 ca0113_mmio_gpio_set(codec, 0x1, false); 4234 break; 4235 case QUIRK_AE5: 4236 ae5_mmio_select_out(codec); 4237 ae5_headphone_gain_set(codec, 4238 spec->ae5_headphone_gain_val); 4239 tmp = FLOAT_ONE; 4240 dspio_set_uint_param(codec, 0x96, 0x29, tmp); 4241 dspio_set_uint_param(codec, 0x96, 0x2a, tmp); 4242 chipio_set_control_param(codec, 0x0d, 0xa1); 4243 chipio_write(codec, 0x18b03c, 0x00000012); 4244 break; 4245 default: 4246 break; 4247 } 4248 break; 4249 case SURROUND_OUT: 4250 switch (ca0132_quirk(spec)) { 4251 case QUIRK_SBZ: 4252 ca0113_mmio_gpio_set(codec, 7, false); 4253 ca0113_mmio_gpio_set(codec, 4, true); 4254 ca0113_mmio_gpio_set(codec, 1, true); 4255 chipio_set_control_param(codec, 0x0d, 0x18); 4256 break; 4257 case QUIRK_ZXR: 4258 ca0113_mmio_gpio_set(codec, 2, true); 4259 ca0113_mmio_gpio_set(codec, 3, true); 4260 ca0113_mmio_gpio_set(codec, 5, false); 4261 zxr_headphone_gain_set(codec, 0); 4262 chipio_set_control_param(codec, 0x0d, 0x24); 4263 break; 4264 case QUIRK_R3DI: 4265 chipio_set_control_param(codec, 0x0d, 0x24); 4266 r3di_gpio_out_set(codec, R3DI_LINE_OUT); 4267 break; 4268 case QUIRK_R3D: 4269 ca0113_mmio_gpio_set(codec, 1, true); 4270 chipio_set_control_param(codec, 0x0d, 0x24); 4271 break; 4272 case QUIRK_AE5: 4273 ae5_mmio_select_out(codec); 4274 ae5_headphone_gain_set(codec, 2); 4275 tmp = FLOAT_ZERO; 4276 dspio_set_uint_param(codec, 0x96, 0x29, tmp); 4277 dspio_set_uint_param(codec, 0x96, 0x2a, tmp); 4278 chipio_set_control_param(codec, 0x0d, 0xa4); 4279 chipio_write(codec, 0x18b03c, 0x00000012); 4280 break; 4281 default: 4282 break; 4283 } 4284 break; 4285 } 4286 } 4287 4288 /* 4289 * This function behaves similarly to the ca0132_select_out funciton above, 4290 * except with a few differences. It adds the ability to select the current 4291 * output with an enumerated control "output source" if the auto detect 4292 * mute switch is set to off. If the auto detect mute switch is enabled, it 4293 * will detect either headphone or lineout(SPEAKER_OUT) from jack detection. 4294 * It also adds the ability to auto-detect the front headphone port. The only 4295 * way to select surround is to disable auto detect, and set Surround with the 4296 * enumerated control. 4297 */ 4298 static int ca0132_alt_select_out(struct hda_codec *codec) 4299 { 4300 struct ca0132_spec *spec = codec->spec; 4301 unsigned int pin_ctl; 4302 int jack_present; 4303 int auto_jack; 4304 unsigned int i; 4305 unsigned int tmp; 4306 int err; 4307 /* Default Headphone is rear headphone */ 4308 hda_nid_t headphone_nid = spec->out_pins[1]; 4309 4310 codec_dbg(codec, "%s\n", __func__); 4311 4312 snd_hda_power_up_pm(codec); 4313 4314 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID]; 4315 4316 /* 4317 * If headphone rear or front is plugged in, set to headphone. 4318 * If neither is plugged in, set to rear line out. Only if 4319 * hp/speaker auto detect is enabled. 4320 */ 4321 if (auto_jack) { 4322 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp) || 4323 snd_hda_jack_detect(codec, spec->unsol_tag_front_hp); 4324 4325 if (jack_present) 4326 spec->cur_out_type = HEADPHONE_OUT; 4327 else 4328 spec->cur_out_type = SPEAKER_OUT; 4329 } else 4330 spec->cur_out_type = spec->out_enum_val; 4331 4332 /* Begin DSP output switch */ 4333 tmp = FLOAT_ONE; 4334 err = dspio_set_uint_param(codec, 0x96, 0x3A, tmp); 4335 if (err < 0) 4336 goto exit; 4337 4338 ca0132_alt_select_out_quirk_handler(codec); 4339 4340 switch (spec->cur_out_type) { 4341 case SPEAKER_OUT: 4342 codec_dbg(codec, "%s speaker\n", __func__); 4343 4344 /* disable headphone node */ 4345 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0, 4346 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4347 snd_hda_set_pin_ctl(codec, spec->out_pins[1], 4348 pin_ctl & ~PIN_HP); 4349 /* enable line-out node */ 4350 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0, 4351 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4352 snd_hda_set_pin_ctl(codec, spec->out_pins[0], 4353 pin_ctl | PIN_OUT); 4354 /* Enable EAPD */ 4355 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4356 AC_VERB_SET_EAPD_BTLENABLE, 0x01); 4357 4358 /* If PlayEnhancement is enabled, set different source */ 4359 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) 4360 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE); 4361 else 4362 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_EIGHT); 4363 break; 4364 case HEADPHONE_OUT: 4365 codec_dbg(codec, "%s hp\n", __func__); 4366 4367 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4368 AC_VERB_SET_EAPD_BTLENABLE, 0x00); 4369 4370 /* disable speaker*/ 4371 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0, 4372 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4373 snd_hda_set_pin_ctl(codec, spec->out_pins[0], 4374 pin_ctl & ~PIN_HP); 4375 4376 /* enable headphone, either front or rear */ 4377 4378 if (snd_hda_jack_detect(codec, spec->unsol_tag_front_hp)) 4379 headphone_nid = spec->out_pins[2]; 4380 else if (snd_hda_jack_detect(codec, spec->unsol_tag_hp)) 4381 headphone_nid = spec->out_pins[1]; 4382 4383 pin_ctl = snd_hda_codec_read(codec, headphone_nid, 0, 4384 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4385 snd_hda_set_pin_ctl(codec, headphone_nid, 4386 pin_ctl | PIN_HP); 4387 4388 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) 4389 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE); 4390 else 4391 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ZERO); 4392 break; 4393 case SURROUND_OUT: 4394 codec_dbg(codec, "%s surround\n", __func__); 4395 4396 /* enable line out node */ 4397 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0, 4398 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4399 snd_hda_set_pin_ctl(codec, spec->out_pins[0], 4400 pin_ctl | PIN_OUT); 4401 /* Disable headphone out */ 4402 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0, 4403 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4404 snd_hda_set_pin_ctl(codec, spec->out_pins[1], 4405 pin_ctl & ~PIN_HP); 4406 /* Enable EAPD on line out */ 4407 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4408 AC_VERB_SET_EAPD_BTLENABLE, 0x01); 4409 /* enable center/lfe out node */ 4410 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[2], 0, 4411 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4412 snd_hda_set_pin_ctl(codec, spec->out_pins[2], 4413 pin_ctl | PIN_OUT); 4414 /* Now set rear surround node as out. */ 4415 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[3], 0, 4416 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4417 snd_hda_set_pin_ctl(codec, spec->out_pins[3], 4418 pin_ctl | PIN_OUT); 4419 4420 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_EIGHT); 4421 break; 4422 } 4423 /* 4424 * Surround always sets it's scp command to req 0x04 to FLOAT_EIGHT. 4425 * With this set though, X_BASS cannot be enabled. So, if we have OutFX 4426 * enabled, we need to make sure X_BASS is off, otherwise everything 4427 * sounds all muffled. Running ca0132_effects_set with X_BASS as the 4428 * effect should sort this out. 4429 */ 4430 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) 4431 ca0132_effects_set(codec, X_BASS, 4432 spec->effects_switch[X_BASS - EFFECT_START_NID]); 4433 4434 /* run through the output dsp commands for the selected output. */ 4435 for (i = 0; i < alt_out_presets[spec->cur_out_type].commands; i++) { 4436 err = dspio_set_uint_param(codec, 4437 alt_out_presets[spec->cur_out_type].mids[i], 4438 alt_out_presets[spec->cur_out_type].reqs[i], 4439 alt_out_presets[spec->cur_out_type].vals[i]); 4440 4441 if (err < 0) 4442 goto exit; 4443 } 4444 4445 exit: 4446 snd_hda_power_down_pm(codec); 4447 4448 return err < 0 ? err : 0; 4449 } 4450 4451 static void ca0132_unsol_hp_delayed(struct work_struct *work) 4452 { 4453 struct ca0132_spec *spec = container_of( 4454 to_delayed_work(work), struct ca0132_spec, unsol_hp_work); 4455 struct hda_jack_tbl *jack; 4456 4457 if (ca0132_use_alt_functions(spec)) 4458 ca0132_alt_select_out(spec->codec); 4459 else 4460 ca0132_select_out(spec->codec); 4461 4462 jack = snd_hda_jack_tbl_get(spec->codec, spec->unsol_tag_hp); 4463 if (jack) { 4464 jack->block_report = 0; 4465 snd_hda_jack_report_sync(spec->codec); 4466 } 4467 } 4468 4469 static void ca0132_set_dmic(struct hda_codec *codec, int enable); 4470 static int ca0132_mic_boost_set(struct hda_codec *codec, long val); 4471 static void resume_mic1(struct hda_codec *codec, unsigned int oldval); 4472 static int stop_mic1(struct hda_codec *codec); 4473 static int ca0132_cvoice_switch_set(struct hda_codec *codec); 4474 static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val); 4475 4476 /* 4477 * Select the active VIP source 4478 */ 4479 static int ca0132_set_vipsource(struct hda_codec *codec, int val) 4480 { 4481 struct ca0132_spec *spec = codec->spec; 4482 unsigned int tmp; 4483 4484 if (spec->dsp_state != DSP_DOWNLOADED) 4485 return 0; 4486 4487 /* if CrystalVoice if off, vipsource should be 0 */ 4488 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] || 4489 (val == 0)) { 4490 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0); 4491 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 4492 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 4493 if (spec->cur_mic_type == DIGITAL_MIC) 4494 tmp = FLOAT_TWO; 4495 else 4496 tmp = FLOAT_ONE; 4497 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4498 tmp = FLOAT_ZERO; 4499 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 4500 } else { 4501 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000); 4502 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000); 4503 if (spec->cur_mic_type == DIGITAL_MIC) 4504 tmp = FLOAT_TWO; 4505 else 4506 tmp = FLOAT_ONE; 4507 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4508 tmp = FLOAT_ONE; 4509 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 4510 msleep(20); 4511 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val); 4512 } 4513 4514 return 1; 4515 } 4516 4517 static int ca0132_alt_set_vipsource(struct hda_codec *codec, int val) 4518 { 4519 struct ca0132_spec *spec = codec->spec; 4520 unsigned int tmp; 4521 4522 if (spec->dsp_state != DSP_DOWNLOADED) 4523 return 0; 4524 4525 codec_dbg(codec, "%s\n", __func__); 4526 4527 chipio_set_stream_control(codec, 0x03, 0); 4528 chipio_set_stream_control(codec, 0x04, 0); 4529 4530 /* if CrystalVoice is off, vipsource should be 0 */ 4531 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] || 4532 (val == 0) || spec->in_enum_val == REAR_LINE_IN) { 4533 codec_dbg(codec, "%s: off.", __func__); 4534 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0); 4535 4536 tmp = FLOAT_ZERO; 4537 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 4538 4539 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 4540 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 4541 if (ca0132_quirk(spec) == QUIRK_R3DI) 4542 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 4543 4544 4545 if (spec->in_enum_val == REAR_LINE_IN) 4546 tmp = FLOAT_ZERO; 4547 else { 4548 if (ca0132_quirk(spec) == QUIRK_SBZ) 4549 tmp = FLOAT_THREE; 4550 else 4551 tmp = FLOAT_ONE; 4552 } 4553 4554 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4555 4556 } else { 4557 codec_dbg(codec, "%s: on.", __func__); 4558 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000); 4559 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000); 4560 if (ca0132_quirk(spec) == QUIRK_R3DI) 4561 chipio_set_conn_rate(codec, 0x0F, SR_16_000); 4562 4563 if (spec->effects_switch[VOICE_FOCUS - EFFECT_START_NID]) 4564 tmp = FLOAT_TWO; 4565 else 4566 tmp = FLOAT_ONE; 4567 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4568 4569 tmp = FLOAT_ONE; 4570 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 4571 4572 msleep(20); 4573 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val); 4574 } 4575 4576 chipio_set_stream_control(codec, 0x03, 1); 4577 chipio_set_stream_control(codec, 0x04, 1); 4578 4579 return 1; 4580 } 4581 4582 /* 4583 * Select the active microphone. 4584 * If autodetect is enabled, mic will be selected based on jack detection. 4585 * If jack inserted, ext.mic will be selected, else built-in mic 4586 * If autodetect is disabled, mic will be selected based on selection. 4587 */ 4588 static int ca0132_select_mic(struct hda_codec *codec) 4589 { 4590 struct ca0132_spec *spec = codec->spec; 4591 int jack_present; 4592 int auto_jack; 4593 4594 codec_dbg(codec, "ca0132_select_mic\n"); 4595 4596 snd_hda_power_up_pm(codec); 4597 4598 auto_jack = spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID]; 4599 4600 if (auto_jack) 4601 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_amic1); 4602 else 4603 jack_present = 4604 spec->vnode_lswitch[VNID_AMIC1_SEL - VNODE_START_NID]; 4605 4606 if (jack_present) 4607 spec->cur_mic_type = LINE_MIC_IN; 4608 else 4609 spec->cur_mic_type = DIGITAL_MIC; 4610 4611 if (spec->cur_mic_type == DIGITAL_MIC) { 4612 /* enable digital Mic */ 4613 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_32_000); 4614 ca0132_set_dmic(codec, 1); 4615 ca0132_mic_boost_set(codec, 0); 4616 /* set voice focus */ 4617 ca0132_effects_set(codec, VOICE_FOCUS, 4618 spec->effects_switch 4619 [VOICE_FOCUS - EFFECT_START_NID]); 4620 } else { 4621 /* disable digital Mic */ 4622 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_96_000); 4623 ca0132_set_dmic(codec, 0); 4624 ca0132_mic_boost_set(codec, spec->cur_mic_boost); 4625 /* disable voice focus */ 4626 ca0132_effects_set(codec, VOICE_FOCUS, 0); 4627 } 4628 4629 snd_hda_power_down_pm(codec); 4630 4631 return 0; 4632 } 4633 4634 /* 4635 * Select the active input. 4636 * Mic detection isn't used, because it's kind of pointless on the SBZ. 4637 * The front mic has no jack-detection, so the only way to switch to it 4638 * is to do it manually in alsamixer. 4639 */ 4640 static int ca0132_alt_select_in(struct hda_codec *codec) 4641 { 4642 struct ca0132_spec *spec = codec->spec; 4643 unsigned int tmp; 4644 4645 codec_dbg(codec, "%s\n", __func__); 4646 4647 snd_hda_power_up_pm(codec); 4648 4649 chipio_set_stream_control(codec, 0x03, 0); 4650 chipio_set_stream_control(codec, 0x04, 0); 4651 4652 spec->cur_mic_type = spec->in_enum_val; 4653 4654 switch (spec->cur_mic_type) { 4655 case REAR_MIC: 4656 switch (ca0132_quirk(spec)) { 4657 case QUIRK_SBZ: 4658 case QUIRK_R3D: 4659 ca0113_mmio_gpio_set(codec, 0, false); 4660 tmp = FLOAT_THREE; 4661 break; 4662 case QUIRK_ZXR: 4663 tmp = FLOAT_THREE; 4664 break; 4665 case QUIRK_R3DI: 4666 r3di_gpio_mic_set(codec, R3DI_REAR_MIC); 4667 tmp = FLOAT_ONE; 4668 break; 4669 case QUIRK_AE5: 4670 ca0113_mmio_command_set(codec, 0x48, 0x28, 0x00); 4671 tmp = FLOAT_THREE; 4672 break; 4673 default: 4674 tmp = FLOAT_ONE; 4675 break; 4676 } 4677 4678 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 4679 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 4680 if (ca0132_quirk(spec) == QUIRK_R3DI) 4681 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 4682 4683 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4684 4685 chipio_set_stream_control(codec, 0x03, 1); 4686 chipio_set_stream_control(codec, 0x04, 1); 4687 switch (ca0132_quirk(spec)) { 4688 case QUIRK_SBZ: 4689 chipio_write(codec, 0x18B098, 0x0000000C); 4690 chipio_write(codec, 0x18B09C, 0x0000000C); 4691 break; 4692 case QUIRK_ZXR: 4693 chipio_write(codec, 0x18B098, 0x0000000C); 4694 chipio_write(codec, 0x18B09C, 0x000000CC); 4695 break; 4696 case QUIRK_AE5: 4697 chipio_write(codec, 0x18B098, 0x0000000C); 4698 chipio_write(codec, 0x18B09C, 0x0000004C); 4699 break; 4700 default: 4701 break; 4702 } 4703 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val); 4704 break; 4705 case REAR_LINE_IN: 4706 ca0132_mic_boost_set(codec, 0); 4707 switch (ca0132_quirk(spec)) { 4708 case QUIRK_SBZ: 4709 case QUIRK_R3D: 4710 ca0113_mmio_gpio_set(codec, 0, false); 4711 break; 4712 case QUIRK_R3DI: 4713 r3di_gpio_mic_set(codec, R3DI_REAR_MIC); 4714 break; 4715 case QUIRK_AE5: 4716 ca0113_mmio_command_set(codec, 0x48, 0x28, 0x00); 4717 break; 4718 default: 4719 break; 4720 } 4721 4722 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 4723 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 4724 if (ca0132_quirk(spec) == QUIRK_R3DI) 4725 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 4726 4727 tmp = FLOAT_ZERO; 4728 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4729 4730 switch (ca0132_quirk(spec)) { 4731 case QUIRK_SBZ: 4732 case QUIRK_AE5: 4733 chipio_write(codec, 0x18B098, 0x00000000); 4734 chipio_write(codec, 0x18B09C, 0x00000000); 4735 break; 4736 default: 4737 break; 4738 } 4739 chipio_set_stream_control(codec, 0x03, 1); 4740 chipio_set_stream_control(codec, 0x04, 1); 4741 break; 4742 case FRONT_MIC: 4743 switch (ca0132_quirk(spec)) { 4744 case QUIRK_SBZ: 4745 case QUIRK_R3D: 4746 ca0113_mmio_gpio_set(codec, 0, true); 4747 ca0113_mmio_gpio_set(codec, 5, false); 4748 tmp = FLOAT_THREE; 4749 break; 4750 case QUIRK_R3DI: 4751 r3di_gpio_mic_set(codec, R3DI_FRONT_MIC); 4752 tmp = FLOAT_ONE; 4753 break; 4754 case QUIRK_AE5: 4755 ca0113_mmio_command_set(codec, 0x48, 0x28, 0x3f); 4756 tmp = FLOAT_THREE; 4757 break; 4758 default: 4759 tmp = FLOAT_ONE; 4760 break; 4761 } 4762 4763 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 4764 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 4765 if (ca0132_quirk(spec) == QUIRK_R3DI) 4766 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 4767 4768 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4769 4770 chipio_set_stream_control(codec, 0x03, 1); 4771 chipio_set_stream_control(codec, 0x04, 1); 4772 4773 switch (ca0132_quirk(spec)) { 4774 case QUIRK_SBZ: 4775 chipio_write(codec, 0x18B098, 0x0000000C); 4776 chipio_write(codec, 0x18B09C, 0x000000CC); 4777 break; 4778 case QUIRK_AE5: 4779 chipio_write(codec, 0x18B098, 0x0000000C); 4780 chipio_write(codec, 0x18B09C, 0x0000004C); 4781 break; 4782 default: 4783 break; 4784 } 4785 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val); 4786 break; 4787 } 4788 ca0132_cvoice_switch_set(codec); 4789 4790 snd_hda_power_down_pm(codec); 4791 return 0; 4792 } 4793 4794 /* 4795 * Check if VNODE settings take effect immediately. 4796 */ 4797 static bool ca0132_is_vnode_effective(struct hda_codec *codec, 4798 hda_nid_t vnid, 4799 hda_nid_t *shared_nid) 4800 { 4801 struct ca0132_spec *spec = codec->spec; 4802 hda_nid_t nid; 4803 4804 switch (vnid) { 4805 case VNID_SPK: 4806 nid = spec->shared_out_nid; 4807 break; 4808 case VNID_MIC: 4809 nid = spec->shared_mic_nid; 4810 break; 4811 default: 4812 return false; 4813 } 4814 4815 if (shared_nid) 4816 *shared_nid = nid; 4817 4818 return true; 4819 } 4820 4821 /* 4822 * The following functions are control change helpers. 4823 * They return 0 if no changed. Return 1 if changed. 4824 */ 4825 static int ca0132_voicefx_set(struct hda_codec *codec, int enable) 4826 { 4827 struct ca0132_spec *spec = codec->spec; 4828 unsigned int tmp; 4829 4830 /* based on CrystalVoice state to enable VoiceFX. */ 4831 if (enable) { 4832 tmp = spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ? 4833 FLOAT_ONE : FLOAT_ZERO; 4834 } else { 4835 tmp = FLOAT_ZERO; 4836 } 4837 4838 dspio_set_uint_param(codec, ca0132_voicefx.mid, 4839 ca0132_voicefx.reqs[0], tmp); 4840 4841 return 1; 4842 } 4843 4844 /* 4845 * Set the effects parameters 4846 */ 4847 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val) 4848 { 4849 struct ca0132_spec *spec = codec->spec; 4850 unsigned int on, tmp; 4851 int num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT; 4852 int err = 0; 4853 int idx = nid - EFFECT_START_NID; 4854 4855 if ((idx < 0) || (idx >= num_fx)) 4856 return 0; /* no changed */ 4857 4858 /* for out effect, qualify with PE */ 4859 if ((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) { 4860 /* if PE if off, turn off out effects. */ 4861 if (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) 4862 val = 0; 4863 if (spec->cur_out_type == SURROUND_OUT && nid == X_BASS) 4864 val = 0; 4865 } 4866 4867 /* for in effect, qualify with CrystalVoice */ 4868 if ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID)) { 4869 /* if CrystalVoice if off, turn off in effects. */ 4870 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]) 4871 val = 0; 4872 4873 /* Voice Focus applies to 2-ch Mic, Digital Mic */ 4874 if ((nid == VOICE_FOCUS) && (spec->cur_mic_type != DIGITAL_MIC)) 4875 val = 0; 4876 4877 /* If Voice Focus on SBZ, set to two channel. */ 4878 if ((nid == VOICE_FOCUS) && ca0132_use_pci_mmio(spec) 4879 && (spec->cur_mic_type != REAR_LINE_IN)) { 4880 if (spec->effects_switch[CRYSTAL_VOICE - 4881 EFFECT_START_NID]) { 4882 4883 if (spec->effects_switch[VOICE_FOCUS - 4884 EFFECT_START_NID]) { 4885 tmp = FLOAT_TWO; 4886 val = 1; 4887 } else 4888 tmp = FLOAT_ONE; 4889 4890 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4891 } 4892 } 4893 /* 4894 * For SBZ noise reduction, there's an extra command 4895 * to module ID 0x47. No clue why. 4896 */ 4897 if ((nid == NOISE_REDUCTION) && ca0132_use_pci_mmio(spec) 4898 && (spec->cur_mic_type != REAR_LINE_IN)) { 4899 if (spec->effects_switch[CRYSTAL_VOICE - 4900 EFFECT_START_NID]) { 4901 if (spec->effects_switch[NOISE_REDUCTION - 4902 EFFECT_START_NID]) 4903 tmp = FLOAT_ONE; 4904 else 4905 tmp = FLOAT_ZERO; 4906 } else 4907 tmp = FLOAT_ZERO; 4908 4909 dspio_set_uint_param(codec, 0x47, 0x00, tmp); 4910 } 4911 4912 /* If rear line in disable effects. */ 4913 if (ca0132_use_alt_functions(spec) && 4914 spec->in_enum_val == REAR_LINE_IN) 4915 val = 0; 4916 } 4917 4918 codec_dbg(codec, "ca0132_effect_set: nid=0x%x, val=%ld\n", 4919 nid, val); 4920 4921 on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE; 4922 err = dspio_set_uint_param(codec, ca0132_effects[idx].mid, 4923 ca0132_effects[idx].reqs[0], on); 4924 4925 if (err < 0) 4926 return 0; /* no changed */ 4927 4928 return 1; 4929 } 4930 4931 /* 4932 * Turn on/off Playback Enhancements 4933 */ 4934 static int ca0132_pe_switch_set(struct hda_codec *codec) 4935 { 4936 struct ca0132_spec *spec = codec->spec; 4937 hda_nid_t nid; 4938 int i, ret = 0; 4939 4940 codec_dbg(codec, "ca0132_pe_switch_set: val=%ld\n", 4941 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]); 4942 4943 if (ca0132_use_alt_functions(spec)) 4944 ca0132_alt_select_out(codec); 4945 4946 i = OUT_EFFECT_START_NID - EFFECT_START_NID; 4947 nid = OUT_EFFECT_START_NID; 4948 /* PE affects all out effects */ 4949 for (; nid < OUT_EFFECT_END_NID; nid++, i++) 4950 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]); 4951 4952 return ret; 4953 } 4954 4955 /* Check if Mic1 is streaming, if so, stop streaming */ 4956 static int stop_mic1(struct hda_codec *codec) 4957 { 4958 struct ca0132_spec *spec = codec->spec; 4959 unsigned int oldval = snd_hda_codec_read(codec, spec->adcs[0], 0, 4960 AC_VERB_GET_CONV, 0); 4961 if (oldval != 0) 4962 snd_hda_codec_write(codec, spec->adcs[0], 0, 4963 AC_VERB_SET_CHANNEL_STREAMID, 4964 0); 4965 return oldval; 4966 } 4967 4968 /* Resume Mic1 streaming if it was stopped. */ 4969 static void resume_mic1(struct hda_codec *codec, unsigned int oldval) 4970 { 4971 struct ca0132_spec *spec = codec->spec; 4972 /* Restore the previous stream and channel */ 4973 if (oldval != 0) 4974 snd_hda_codec_write(codec, spec->adcs[0], 0, 4975 AC_VERB_SET_CHANNEL_STREAMID, 4976 oldval); 4977 } 4978 4979 /* 4980 * Turn on/off CrystalVoice 4981 */ 4982 static int ca0132_cvoice_switch_set(struct hda_codec *codec) 4983 { 4984 struct ca0132_spec *spec = codec->spec; 4985 hda_nid_t nid; 4986 int i, ret = 0; 4987 unsigned int oldval; 4988 4989 codec_dbg(codec, "ca0132_cvoice_switch_set: val=%ld\n", 4990 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]); 4991 4992 i = IN_EFFECT_START_NID - EFFECT_START_NID; 4993 nid = IN_EFFECT_START_NID; 4994 /* CrystalVoice affects all in effects */ 4995 for (; nid < IN_EFFECT_END_NID; nid++, i++) 4996 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]); 4997 4998 /* including VoiceFX */ 4999 ret |= ca0132_voicefx_set(codec, (spec->voicefx_val ? 1 : 0)); 5000 5001 /* set correct vipsource */ 5002 oldval = stop_mic1(codec); 5003 if (ca0132_use_alt_functions(spec)) 5004 ret |= ca0132_alt_set_vipsource(codec, 1); 5005 else 5006 ret |= ca0132_set_vipsource(codec, 1); 5007 resume_mic1(codec, oldval); 5008 return ret; 5009 } 5010 5011 static int ca0132_mic_boost_set(struct hda_codec *codec, long val) 5012 { 5013 struct ca0132_spec *spec = codec->spec; 5014 int ret = 0; 5015 5016 if (val) /* on */ 5017 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0, 5018 HDA_INPUT, 0, HDA_AMP_VOLMASK, 3); 5019 else /* off */ 5020 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0, 5021 HDA_INPUT, 0, HDA_AMP_VOLMASK, 0); 5022 5023 return ret; 5024 } 5025 5026 static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val) 5027 { 5028 struct ca0132_spec *spec = codec->spec; 5029 int ret = 0; 5030 5031 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0, 5032 HDA_INPUT, 0, HDA_AMP_VOLMASK, val); 5033 return ret; 5034 } 5035 5036 static int ae5_headphone_gain_set(struct hda_codec *codec, long val) 5037 { 5038 unsigned int i; 5039 5040 for (i = 0; i < 4; i++) 5041 ca0113_mmio_command_set(codec, 0x48, 0x11 + i, 5042 ae5_headphone_gain_presets[val].vals[i]); 5043 return 0; 5044 } 5045 5046 /* 5047 * gpio pin 1 is a relay that switches on/off, apparently setting the headphone 5048 * amplifier to handle a 600 ohm load. 5049 */ 5050 static int zxr_headphone_gain_set(struct hda_codec *codec, long val) 5051 { 5052 ca0113_mmio_gpio_set(codec, 1, val); 5053 5054 return 0; 5055 } 5056 5057 static int ca0132_vnode_switch_set(struct snd_kcontrol *kcontrol, 5058 struct snd_ctl_elem_value *ucontrol) 5059 { 5060 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5061 hda_nid_t nid = get_amp_nid(kcontrol); 5062 hda_nid_t shared_nid = 0; 5063 bool effective; 5064 int ret = 0; 5065 struct ca0132_spec *spec = codec->spec; 5066 int auto_jack; 5067 5068 if (nid == VNID_HP_SEL) { 5069 auto_jack = 5070 spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID]; 5071 if (!auto_jack) { 5072 if (ca0132_use_alt_functions(spec)) 5073 ca0132_alt_select_out(codec); 5074 else 5075 ca0132_select_out(codec); 5076 } 5077 return 1; 5078 } 5079 5080 if (nid == VNID_AMIC1_SEL) { 5081 auto_jack = 5082 spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID]; 5083 if (!auto_jack) 5084 ca0132_select_mic(codec); 5085 return 1; 5086 } 5087 5088 if (nid == VNID_HP_ASEL) { 5089 if (ca0132_use_alt_functions(spec)) 5090 ca0132_alt_select_out(codec); 5091 else 5092 ca0132_select_out(codec); 5093 return 1; 5094 } 5095 5096 if (nid == VNID_AMIC1_ASEL) { 5097 ca0132_select_mic(codec); 5098 return 1; 5099 } 5100 5101 /* if effective conditions, then update hw immediately. */ 5102 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid); 5103 if (effective) { 5104 int dir = get_amp_direction(kcontrol); 5105 int ch = get_amp_channels(kcontrol); 5106 unsigned long pval; 5107 5108 mutex_lock(&codec->control_mutex); 5109 pval = kcontrol->private_value; 5110 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch, 5111 0, dir); 5112 ret = snd_hda_mixer_amp_switch_put(kcontrol, ucontrol); 5113 kcontrol->private_value = pval; 5114 mutex_unlock(&codec->control_mutex); 5115 } 5116 5117 return ret; 5118 } 5119 /* End of control change helpers. */ 5120 /* 5121 * Below I've added controls to mess with the effect levels, I've only enabled 5122 * them on the Sound Blaster Z, but they would probably also work on the 5123 * Chromebook. I figured they were probably tuned specifically for it, and left 5124 * out for a reason. 5125 */ 5126 5127 /* Sets DSP effect level from the sliders above the controls */ 5128 static int ca0132_alt_slider_ctl_set(struct hda_codec *codec, hda_nid_t nid, 5129 const unsigned int *lookup, int idx) 5130 { 5131 int i = 0; 5132 unsigned int y; 5133 /* 5134 * For X_BASS, req 2 is actually crossover freq instead of 5135 * effect level 5136 */ 5137 if (nid == X_BASS) 5138 y = 2; 5139 else 5140 y = 1; 5141 5142 snd_hda_power_up(codec); 5143 if (nid == XBASS_XOVER) { 5144 for (i = 0; i < OUT_EFFECTS_COUNT; i++) 5145 if (ca0132_effects[i].nid == X_BASS) 5146 break; 5147 5148 dspio_set_param(codec, ca0132_effects[i].mid, 0x20, 5149 ca0132_effects[i].reqs[1], 5150 &(lookup[idx - 1]), sizeof(unsigned int)); 5151 } else { 5152 /* Find the actual effect structure */ 5153 for (i = 0; i < OUT_EFFECTS_COUNT; i++) 5154 if (nid == ca0132_effects[i].nid) 5155 break; 5156 5157 dspio_set_param(codec, ca0132_effects[i].mid, 0x20, 5158 ca0132_effects[i].reqs[y], 5159 &(lookup[idx]), sizeof(unsigned int)); 5160 } 5161 5162 snd_hda_power_down(codec); 5163 5164 return 0; 5165 } 5166 5167 static int ca0132_alt_xbass_xover_slider_ctl_get(struct snd_kcontrol *kcontrol, 5168 struct snd_ctl_elem_value *ucontrol) 5169 { 5170 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5171 struct ca0132_spec *spec = codec->spec; 5172 long *valp = ucontrol->value.integer.value; 5173 5174 *valp = spec->xbass_xover_freq; 5175 return 0; 5176 } 5177 5178 static int ca0132_alt_slider_ctl_get(struct snd_kcontrol *kcontrol, 5179 struct snd_ctl_elem_value *ucontrol) 5180 { 5181 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5182 struct ca0132_spec *spec = codec->spec; 5183 hda_nid_t nid = get_amp_nid(kcontrol); 5184 long *valp = ucontrol->value.integer.value; 5185 int idx = nid - OUT_EFFECT_START_NID; 5186 5187 *valp = spec->fx_ctl_val[idx]; 5188 return 0; 5189 } 5190 5191 /* 5192 * The X-bass crossover starts at 10hz, so the min is 1. The 5193 * frequency is set in multiples of 10. 5194 */ 5195 static int ca0132_alt_xbass_xover_slider_info(struct snd_kcontrol *kcontrol, 5196 struct snd_ctl_elem_info *uinfo) 5197 { 5198 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 5199 uinfo->count = 1; 5200 uinfo->value.integer.min = 1; 5201 uinfo->value.integer.max = 100; 5202 uinfo->value.integer.step = 1; 5203 5204 return 0; 5205 } 5206 5207 static int ca0132_alt_effect_slider_info(struct snd_kcontrol *kcontrol, 5208 struct snd_ctl_elem_info *uinfo) 5209 { 5210 int chs = get_amp_channels(kcontrol); 5211 5212 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 5213 uinfo->count = chs == 3 ? 2 : 1; 5214 uinfo->value.integer.min = 0; 5215 uinfo->value.integer.max = 100; 5216 uinfo->value.integer.step = 1; 5217 5218 return 0; 5219 } 5220 5221 static int ca0132_alt_xbass_xover_slider_put(struct snd_kcontrol *kcontrol, 5222 struct snd_ctl_elem_value *ucontrol) 5223 { 5224 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5225 struct ca0132_spec *spec = codec->spec; 5226 hda_nid_t nid = get_amp_nid(kcontrol); 5227 long *valp = ucontrol->value.integer.value; 5228 int idx; 5229 5230 /* any change? */ 5231 if (spec->xbass_xover_freq == *valp) 5232 return 0; 5233 5234 spec->xbass_xover_freq = *valp; 5235 5236 idx = *valp; 5237 ca0132_alt_slider_ctl_set(codec, nid, float_xbass_xover_lookup, idx); 5238 5239 return 0; 5240 } 5241 5242 static int ca0132_alt_effect_slider_put(struct snd_kcontrol *kcontrol, 5243 struct snd_ctl_elem_value *ucontrol) 5244 { 5245 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5246 struct ca0132_spec *spec = codec->spec; 5247 hda_nid_t nid = get_amp_nid(kcontrol); 5248 long *valp = ucontrol->value.integer.value; 5249 int idx; 5250 5251 idx = nid - EFFECT_START_NID; 5252 /* any change? */ 5253 if (spec->fx_ctl_val[idx] == *valp) 5254 return 0; 5255 5256 spec->fx_ctl_val[idx] = *valp; 5257 5258 idx = *valp; 5259 ca0132_alt_slider_ctl_set(codec, nid, float_zero_to_one_lookup, idx); 5260 5261 return 0; 5262 } 5263 5264 5265 /* 5266 * Mic Boost Enum for alternative ca0132 codecs. I didn't like that the original 5267 * only has off or full 30 dB, and didn't like making a volume slider that has 5268 * traditional 0-100 in alsamixer that goes in big steps. I like enum better. 5269 */ 5270 #define MIC_BOOST_NUM_OF_STEPS 4 5271 #define MIC_BOOST_ENUM_MAX_STRLEN 10 5272 5273 static int ca0132_alt_mic_boost_info(struct snd_kcontrol *kcontrol, 5274 struct snd_ctl_elem_info *uinfo) 5275 { 5276 char *sfx = "dB"; 5277 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 5278 5279 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5280 uinfo->count = 1; 5281 uinfo->value.enumerated.items = MIC_BOOST_NUM_OF_STEPS; 5282 if (uinfo->value.enumerated.item >= MIC_BOOST_NUM_OF_STEPS) 5283 uinfo->value.enumerated.item = MIC_BOOST_NUM_OF_STEPS - 1; 5284 sprintf(namestr, "%d %s", (uinfo->value.enumerated.item * 10), sfx); 5285 strcpy(uinfo->value.enumerated.name, namestr); 5286 return 0; 5287 } 5288 5289 static int ca0132_alt_mic_boost_get(struct snd_kcontrol *kcontrol, 5290 struct snd_ctl_elem_value *ucontrol) 5291 { 5292 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5293 struct ca0132_spec *spec = codec->spec; 5294 5295 ucontrol->value.enumerated.item[0] = spec->mic_boost_enum_val; 5296 return 0; 5297 } 5298 5299 static int ca0132_alt_mic_boost_put(struct snd_kcontrol *kcontrol, 5300 struct snd_ctl_elem_value *ucontrol) 5301 { 5302 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5303 struct ca0132_spec *spec = codec->spec; 5304 int sel = ucontrol->value.enumerated.item[0]; 5305 unsigned int items = MIC_BOOST_NUM_OF_STEPS; 5306 5307 if (sel >= items) 5308 return 0; 5309 5310 codec_dbg(codec, "ca0132_alt_mic_boost: boost=%d\n", 5311 sel); 5312 5313 spec->mic_boost_enum_val = sel; 5314 5315 if (spec->in_enum_val != REAR_LINE_IN) 5316 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val); 5317 5318 return 1; 5319 } 5320 5321 /* 5322 * Sound BlasterX AE-5 Headphone Gain Controls. 5323 */ 5324 #define AE5_HEADPHONE_GAIN_MAX 3 5325 static int ae5_headphone_gain_info(struct snd_kcontrol *kcontrol, 5326 struct snd_ctl_elem_info *uinfo) 5327 { 5328 char *sfx = " Ohms)"; 5329 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 5330 5331 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5332 uinfo->count = 1; 5333 uinfo->value.enumerated.items = AE5_HEADPHONE_GAIN_MAX; 5334 if (uinfo->value.enumerated.item >= AE5_HEADPHONE_GAIN_MAX) 5335 uinfo->value.enumerated.item = AE5_HEADPHONE_GAIN_MAX - 1; 5336 sprintf(namestr, "%s %s", 5337 ae5_headphone_gain_presets[uinfo->value.enumerated.item].name, 5338 sfx); 5339 strcpy(uinfo->value.enumerated.name, namestr); 5340 return 0; 5341 } 5342 5343 static int ae5_headphone_gain_get(struct snd_kcontrol *kcontrol, 5344 struct snd_ctl_elem_value *ucontrol) 5345 { 5346 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5347 struct ca0132_spec *spec = codec->spec; 5348 5349 ucontrol->value.enumerated.item[0] = spec->ae5_headphone_gain_val; 5350 return 0; 5351 } 5352 5353 static int ae5_headphone_gain_put(struct snd_kcontrol *kcontrol, 5354 struct snd_ctl_elem_value *ucontrol) 5355 { 5356 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5357 struct ca0132_spec *spec = codec->spec; 5358 int sel = ucontrol->value.enumerated.item[0]; 5359 unsigned int items = AE5_HEADPHONE_GAIN_MAX; 5360 5361 if (sel >= items) 5362 return 0; 5363 5364 codec_dbg(codec, "ae5_headphone_gain: boost=%d\n", 5365 sel); 5366 5367 spec->ae5_headphone_gain_val = sel; 5368 5369 if (spec->out_enum_val == HEADPHONE_OUT) 5370 ae5_headphone_gain_set(codec, spec->ae5_headphone_gain_val); 5371 5372 return 1; 5373 } 5374 5375 /* 5376 * Sound BlasterX AE-5 sound filter enumerated control. 5377 */ 5378 #define AE5_SOUND_FILTER_MAX 3 5379 5380 static int ae5_sound_filter_info(struct snd_kcontrol *kcontrol, 5381 struct snd_ctl_elem_info *uinfo) 5382 { 5383 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 5384 5385 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5386 uinfo->count = 1; 5387 uinfo->value.enumerated.items = AE5_SOUND_FILTER_MAX; 5388 if (uinfo->value.enumerated.item >= AE5_SOUND_FILTER_MAX) 5389 uinfo->value.enumerated.item = AE5_SOUND_FILTER_MAX - 1; 5390 sprintf(namestr, "%s", 5391 ae5_filter_presets[uinfo->value.enumerated.item].name); 5392 strcpy(uinfo->value.enumerated.name, namestr); 5393 return 0; 5394 } 5395 5396 static int ae5_sound_filter_get(struct snd_kcontrol *kcontrol, 5397 struct snd_ctl_elem_value *ucontrol) 5398 { 5399 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5400 struct ca0132_spec *spec = codec->spec; 5401 5402 ucontrol->value.enumerated.item[0] = spec->ae5_filter_val; 5403 return 0; 5404 } 5405 5406 static int ae5_sound_filter_put(struct snd_kcontrol *kcontrol, 5407 struct snd_ctl_elem_value *ucontrol) 5408 { 5409 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5410 struct ca0132_spec *spec = codec->spec; 5411 int sel = ucontrol->value.enumerated.item[0]; 5412 unsigned int items = AE5_SOUND_FILTER_MAX; 5413 5414 if (sel >= items) 5415 return 0; 5416 5417 codec_dbg(codec, "ae5_sound_filter: %s\n", 5418 ae5_filter_presets[sel].name); 5419 5420 spec->ae5_filter_val = sel; 5421 5422 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 5423 ae5_filter_presets[sel].val); 5424 5425 return 1; 5426 } 5427 5428 /* 5429 * Input Select Control for alternative ca0132 codecs. This exists because 5430 * front microphone has no auto-detect, and we need a way to set the rear 5431 * as line-in 5432 */ 5433 static int ca0132_alt_input_source_info(struct snd_kcontrol *kcontrol, 5434 struct snd_ctl_elem_info *uinfo) 5435 { 5436 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5437 uinfo->count = 1; 5438 uinfo->value.enumerated.items = IN_SRC_NUM_OF_INPUTS; 5439 if (uinfo->value.enumerated.item >= IN_SRC_NUM_OF_INPUTS) 5440 uinfo->value.enumerated.item = IN_SRC_NUM_OF_INPUTS - 1; 5441 strcpy(uinfo->value.enumerated.name, 5442 in_src_str[uinfo->value.enumerated.item]); 5443 return 0; 5444 } 5445 5446 static int ca0132_alt_input_source_get(struct snd_kcontrol *kcontrol, 5447 struct snd_ctl_elem_value *ucontrol) 5448 { 5449 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5450 struct ca0132_spec *spec = codec->spec; 5451 5452 ucontrol->value.enumerated.item[0] = spec->in_enum_val; 5453 return 0; 5454 } 5455 5456 static int ca0132_alt_input_source_put(struct snd_kcontrol *kcontrol, 5457 struct snd_ctl_elem_value *ucontrol) 5458 { 5459 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5460 struct ca0132_spec *spec = codec->spec; 5461 int sel = ucontrol->value.enumerated.item[0]; 5462 unsigned int items = IN_SRC_NUM_OF_INPUTS; 5463 5464 if (sel >= items) 5465 return 0; 5466 5467 codec_dbg(codec, "ca0132_alt_input_select: sel=%d, preset=%s\n", 5468 sel, in_src_str[sel]); 5469 5470 spec->in_enum_val = sel; 5471 5472 ca0132_alt_select_in(codec); 5473 5474 return 1; 5475 } 5476 5477 /* Sound Blaster Z Output Select Control */ 5478 static int ca0132_alt_output_select_get_info(struct snd_kcontrol *kcontrol, 5479 struct snd_ctl_elem_info *uinfo) 5480 { 5481 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5482 uinfo->count = 1; 5483 uinfo->value.enumerated.items = NUM_OF_OUTPUTS; 5484 if (uinfo->value.enumerated.item >= NUM_OF_OUTPUTS) 5485 uinfo->value.enumerated.item = NUM_OF_OUTPUTS - 1; 5486 strcpy(uinfo->value.enumerated.name, 5487 alt_out_presets[uinfo->value.enumerated.item].name); 5488 return 0; 5489 } 5490 5491 static int ca0132_alt_output_select_get(struct snd_kcontrol *kcontrol, 5492 struct snd_ctl_elem_value *ucontrol) 5493 { 5494 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5495 struct ca0132_spec *spec = codec->spec; 5496 5497 ucontrol->value.enumerated.item[0] = spec->out_enum_val; 5498 return 0; 5499 } 5500 5501 static int ca0132_alt_output_select_put(struct snd_kcontrol *kcontrol, 5502 struct snd_ctl_elem_value *ucontrol) 5503 { 5504 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5505 struct ca0132_spec *spec = codec->spec; 5506 int sel = ucontrol->value.enumerated.item[0]; 5507 unsigned int items = NUM_OF_OUTPUTS; 5508 unsigned int auto_jack; 5509 5510 if (sel >= items) 5511 return 0; 5512 5513 codec_dbg(codec, "ca0132_alt_output_select: sel=%d, preset=%s\n", 5514 sel, alt_out_presets[sel].name); 5515 5516 spec->out_enum_val = sel; 5517 5518 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID]; 5519 5520 if (!auto_jack) 5521 ca0132_alt_select_out(codec); 5522 5523 return 1; 5524 } 5525 5526 /* 5527 * Smart Volume output setting control. Three different settings, Normal, 5528 * which takes the value from the smart volume slider. The two others, loud 5529 * and night, disregard the slider value and have uneditable values. 5530 */ 5531 #define NUM_OF_SVM_SETTINGS 3 5532 static const char *const out_svm_set_enum_str[3] = {"Normal", "Loud", "Night" }; 5533 5534 static int ca0132_alt_svm_setting_info(struct snd_kcontrol *kcontrol, 5535 struct snd_ctl_elem_info *uinfo) 5536 { 5537 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5538 uinfo->count = 1; 5539 uinfo->value.enumerated.items = NUM_OF_SVM_SETTINGS; 5540 if (uinfo->value.enumerated.item >= NUM_OF_SVM_SETTINGS) 5541 uinfo->value.enumerated.item = NUM_OF_SVM_SETTINGS - 1; 5542 strcpy(uinfo->value.enumerated.name, 5543 out_svm_set_enum_str[uinfo->value.enumerated.item]); 5544 return 0; 5545 } 5546 5547 static int ca0132_alt_svm_setting_get(struct snd_kcontrol *kcontrol, 5548 struct snd_ctl_elem_value *ucontrol) 5549 { 5550 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5551 struct ca0132_spec *spec = codec->spec; 5552 5553 ucontrol->value.enumerated.item[0] = spec->smart_volume_setting; 5554 return 0; 5555 } 5556 5557 static int ca0132_alt_svm_setting_put(struct snd_kcontrol *kcontrol, 5558 struct snd_ctl_elem_value *ucontrol) 5559 { 5560 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5561 struct ca0132_spec *spec = codec->spec; 5562 int sel = ucontrol->value.enumerated.item[0]; 5563 unsigned int items = NUM_OF_SVM_SETTINGS; 5564 unsigned int idx = SMART_VOLUME - EFFECT_START_NID; 5565 unsigned int tmp; 5566 5567 if (sel >= items) 5568 return 0; 5569 5570 codec_dbg(codec, "ca0132_alt_svm_setting: sel=%d, preset=%s\n", 5571 sel, out_svm_set_enum_str[sel]); 5572 5573 spec->smart_volume_setting = sel; 5574 5575 switch (sel) { 5576 case 0: 5577 tmp = FLOAT_ZERO; 5578 break; 5579 case 1: 5580 tmp = FLOAT_ONE; 5581 break; 5582 case 2: 5583 tmp = FLOAT_TWO; 5584 break; 5585 default: 5586 tmp = FLOAT_ZERO; 5587 break; 5588 } 5589 /* Req 2 is the Smart Volume Setting req. */ 5590 dspio_set_uint_param(codec, ca0132_effects[idx].mid, 5591 ca0132_effects[idx].reqs[2], tmp); 5592 return 1; 5593 } 5594 5595 /* Sound Blaster Z EQ preset controls */ 5596 static int ca0132_alt_eq_preset_info(struct snd_kcontrol *kcontrol, 5597 struct snd_ctl_elem_info *uinfo) 5598 { 5599 unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets); 5600 5601 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5602 uinfo->count = 1; 5603 uinfo->value.enumerated.items = items; 5604 if (uinfo->value.enumerated.item >= items) 5605 uinfo->value.enumerated.item = items - 1; 5606 strcpy(uinfo->value.enumerated.name, 5607 ca0132_alt_eq_presets[uinfo->value.enumerated.item].name); 5608 return 0; 5609 } 5610 5611 static int ca0132_alt_eq_preset_get(struct snd_kcontrol *kcontrol, 5612 struct snd_ctl_elem_value *ucontrol) 5613 { 5614 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5615 struct ca0132_spec *spec = codec->spec; 5616 5617 ucontrol->value.enumerated.item[0] = spec->eq_preset_val; 5618 return 0; 5619 } 5620 5621 static int ca0132_alt_eq_preset_put(struct snd_kcontrol *kcontrol, 5622 struct snd_ctl_elem_value *ucontrol) 5623 { 5624 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5625 struct ca0132_spec *spec = codec->spec; 5626 int i, err = 0; 5627 int sel = ucontrol->value.enumerated.item[0]; 5628 unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets); 5629 5630 if (sel >= items) 5631 return 0; 5632 5633 codec_dbg(codec, "%s: sel=%d, preset=%s\n", __func__, sel, 5634 ca0132_alt_eq_presets[sel].name); 5635 /* 5636 * Idx 0 is default. 5637 * Default needs to qualify with CrystalVoice state. 5638 */ 5639 for (i = 0; i < EQ_PRESET_MAX_PARAM_COUNT; i++) { 5640 err = dspio_set_uint_param(codec, ca0132_alt_eq_enum.mid, 5641 ca0132_alt_eq_enum.reqs[i], 5642 ca0132_alt_eq_presets[sel].vals[i]); 5643 if (err < 0) 5644 break; 5645 } 5646 5647 if (err >= 0) 5648 spec->eq_preset_val = sel; 5649 5650 return 1; 5651 } 5652 5653 static int ca0132_voicefx_info(struct snd_kcontrol *kcontrol, 5654 struct snd_ctl_elem_info *uinfo) 5655 { 5656 unsigned int items = ARRAY_SIZE(ca0132_voicefx_presets); 5657 5658 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5659 uinfo->count = 1; 5660 uinfo->value.enumerated.items = items; 5661 if (uinfo->value.enumerated.item >= items) 5662 uinfo->value.enumerated.item = items - 1; 5663 strcpy(uinfo->value.enumerated.name, 5664 ca0132_voicefx_presets[uinfo->value.enumerated.item].name); 5665 return 0; 5666 } 5667 5668 static int ca0132_voicefx_get(struct snd_kcontrol *kcontrol, 5669 struct snd_ctl_elem_value *ucontrol) 5670 { 5671 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5672 struct ca0132_spec *spec = codec->spec; 5673 5674 ucontrol->value.enumerated.item[0] = spec->voicefx_val; 5675 return 0; 5676 } 5677 5678 static int ca0132_voicefx_put(struct snd_kcontrol *kcontrol, 5679 struct snd_ctl_elem_value *ucontrol) 5680 { 5681 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5682 struct ca0132_spec *spec = codec->spec; 5683 int i, err = 0; 5684 int sel = ucontrol->value.enumerated.item[0]; 5685 5686 if (sel >= ARRAY_SIZE(ca0132_voicefx_presets)) 5687 return 0; 5688 5689 codec_dbg(codec, "ca0132_voicefx_put: sel=%d, preset=%s\n", 5690 sel, ca0132_voicefx_presets[sel].name); 5691 5692 /* 5693 * Idx 0 is default. 5694 * Default needs to qualify with CrystalVoice state. 5695 */ 5696 for (i = 0; i < VOICEFX_MAX_PARAM_COUNT; i++) { 5697 err = dspio_set_uint_param(codec, ca0132_voicefx.mid, 5698 ca0132_voicefx.reqs[i], 5699 ca0132_voicefx_presets[sel].vals[i]); 5700 if (err < 0) 5701 break; 5702 } 5703 5704 if (err >= 0) { 5705 spec->voicefx_val = sel; 5706 /* enable voice fx */ 5707 ca0132_voicefx_set(codec, (sel ? 1 : 0)); 5708 } 5709 5710 return 1; 5711 } 5712 5713 static int ca0132_switch_get(struct snd_kcontrol *kcontrol, 5714 struct snd_ctl_elem_value *ucontrol) 5715 { 5716 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5717 struct ca0132_spec *spec = codec->spec; 5718 hda_nid_t nid = get_amp_nid(kcontrol); 5719 int ch = get_amp_channels(kcontrol); 5720 long *valp = ucontrol->value.integer.value; 5721 5722 /* vnode */ 5723 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) { 5724 if (ch & 1) { 5725 *valp = spec->vnode_lswitch[nid - VNODE_START_NID]; 5726 valp++; 5727 } 5728 if (ch & 2) { 5729 *valp = spec->vnode_rswitch[nid - VNODE_START_NID]; 5730 valp++; 5731 } 5732 return 0; 5733 } 5734 5735 /* effects, include PE and CrystalVoice */ 5736 if ((nid >= EFFECT_START_NID) && (nid < EFFECT_END_NID)) { 5737 *valp = spec->effects_switch[nid - EFFECT_START_NID]; 5738 return 0; 5739 } 5740 5741 /* mic boost */ 5742 if (nid == spec->input_pins[0]) { 5743 *valp = spec->cur_mic_boost; 5744 return 0; 5745 } 5746 5747 return 0; 5748 } 5749 5750 static int ca0132_switch_put(struct snd_kcontrol *kcontrol, 5751 struct snd_ctl_elem_value *ucontrol) 5752 { 5753 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5754 struct ca0132_spec *spec = codec->spec; 5755 hda_nid_t nid = get_amp_nid(kcontrol); 5756 int ch = get_amp_channels(kcontrol); 5757 long *valp = ucontrol->value.integer.value; 5758 int changed = 1; 5759 5760 codec_dbg(codec, "ca0132_switch_put: nid=0x%x, val=%ld\n", 5761 nid, *valp); 5762 5763 snd_hda_power_up(codec); 5764 /* vnode */ 5765 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) { 5766 if (ch & 1) { 5767 spec->vnode_lswitch[nid - VNODE_START_NID] = *valp; 5768 valp++; 5769 } 5770 if (ch & 2) { 5771 spec->vnode_rswitch[nid - VNODE_START_NID] = *valp; 5772 valp++; 5773 } 5774 changed = ca0132_vnode_switch_set(kcontrol, ucontrol); 5775 goto exit; 5776 } 5777 5778 /* PE */ 5779 if (nid == PLAY_ENHANCEMENT) { 5780 spec->effects_switch[nid - EFFECT_START_NID] = *valp; 5781 changed = ca0132_pe_switch_set(codec); 5782 goto exit; 5783 } 5784 5785 /* CrystalVoice */ 5786 if (nid == CRYSTAL_VOICE) { 5787 spec->effects_switch[nid - EFFECT_START_NID] = *valp; 5788 changed = ca0132_cvoice_switch_set(codec); 5789 goto exit; 5790 } 5791 5792 /* out and in effects */ 5793 if (((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) || 5794 ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID))) { 5795 spec->effects_switch[nid - EFFECT_START_NID] = *valp; 5796 changed = ca0132_effects_set(codec, nid, *valp); 5797 goto exit; 5798 } 5799 5800 /* mic boost */ 5801 if (nid == spec->input_pins[0]) { 5802 spec->cur_mic_boost = *valp; 5803 if (ca0132_use_alt_functions(spec)) { 5804 if (spec->in_enum_val != REAR_LINE_IN) 5805 changed = ca0132_mic_boost_set(codec, *valp); 5806 } else { 5807 /* Mic boost does not apply to Digital Mic */ 5808 if (spec->cur_mic_type != DIGITAL_MIC) 5809 changed = ca0132_mic_boost_set(codec, *valp); 5810 } 5811 5812 goto exit; 5813 } 5814 5815 if (nid == ZXR_HEADPHONE_GAIN) { 5816 spec->zxr_gain_set = *valp; 5817 if (spec->cur_out_type == HEADPHONE_OUT) 5818 changed = zxr_headphone_gain_set(codec, *valp); 5819 else 5820 changed = 0; 5821 5822 goto exit; 5823 } 5824 5825 exit: 5826 snd_hda_power_down(codec); 5827 return changed; 5828 } 5829 5830 /* 5831 * Volume related 5832 */ 5833 /* 5834 * Sets the internal DSP decibel level to match the DAC for output, and the 5835 * ADC for input. Currently only the SBZ sets dsp capture volume level, and 5836 * all alternative codecs set DSP playback volume. 5837 */ 5838 static void ca0132_alt_dsp_volume_put(struct hda_codec *codec, hda_nid_t nid) 5839 { 5840 struct ca0132_spec *spec = codec->spec; 5841 unsigned int dsp_dir; 5842 unsigned int lookup_val; 5843 5844 if (nid == VNID_SPK) 5845 dsp_dir = DSP_VOL_OUT; 5846 else 5847 dsp_dir = DSP_VOL_IN; 5848 5849 lookup_val = spec->vnode_lvol[nid - VNODE_START_NID]; 5850 5851 dspio_set_uint_param(codec, 5852 ca0132_alt_vol_ctls[dsp_dir].mid, 5853 ca0132_alt_vol_ctls[dsp_dir].reqs[0], 5854 float_vol_db_lookup[lookup_val]); 5855 5856 lookup_val = spec->vnode_rvol[nid - VNODE_START_NID]; 5857 5858 dspio_set_uint_param(codec, 5859 ca0132_alt_vol_ctls[dsp_dir].mid, 5860 ca0132_alt_vol_ctls[dsp_dir].reqs[1], 5861 float_vol_db_lookup[lookup_val]); 5862 5863 dspio_set_uint_param(codec, 5864 ca0132_alt_vol_ctls[dsp_dir].mid, 5865 ca0132_alt_vol_ctls[dsp_dir].reqs[2], FLOAT_ZERO); 5866 } 5867 5868 static int ca0132_volume_info(struct snd_kcontrol *kcontrol, 5869 struct snd_ctl_elem_info *uinfo) 5870 { 5871 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5872 struct ca0132_spec *spec = codec->spec; 5873 hda_nid_t nid = get_amp_nid(kcontrol); 5874 int ch = get_amp_channels(kcontrol); 5875 int dir = get_amp_direction(kcontrol); 5876 unsigned long pval; 5877 int err; 5878 5879 switch (nid) { 5880 case VNID_SPK: 5881 /* follow shared_out info */ 5882 nid = spec->shared_out_nid; 5883 mutex_lock(&codec->control_mutex); 5884 pval = kcontrol->private_value; 5885 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); 5886 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo); 5887 kcontrol->private_value = pval; 5888 mutex_unlock(&codec->control_mutex); 5889 break; 5890 case VNID_MIC: 5891 /* follow shared_mic info */ 5892 nid = spec->shared_mic_nid; 5893 mutex_lock(&codec->control_mutex); 5894 pval = kcontrol->private_value; 5895 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); 5896 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo); 5897 kcontrol->private_value = pval; 5898 mutex_unlock(&codec->control_mutex); 5899 break; 5900 default: 5901 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo); 5902 } 5903 return err; 5904 } 5905 5906 static int ca0132_volume_get(struct snd_kcontrol *kcontrol, 5907 struct snd_ctl_elem_value *ucontrol) 5908 { 5909 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5910 struct ca0132_spec *spec = codec->spec; 5911 hda_nid_t nid = get_amp_nid(kcontrol); 5912 int ch = get_amp_channels(kcontrol); 5913 long *valp = ucontrol->value.integer.value; 5914 5915 /* store the left and right volume */ 5916 if (ch & 1) { 5917 *valp = spec->vnode_lvol[nid - VNODE_START_NID]; 5918 valp++; 5919 } 5920 if (ch & 2) { 5921 *valp = spec->vnode_rvol[nid - VNODE_START_NID]; 5922 valp++; 5923 } 5924 return 0; 5925 } 5926 5927 static int ca0132_volume_put(struct snd_kcontrol *kcontrol, 5928 struct snd_ctl_elem_value *ucontrol) 5929 { 5930 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5931 struct ca0132_spec *spec = codec->spec; 5932 hda_nid_t nid = get_amp_nid(kcontrol); 5933 int ch = get_amp_channels(kcontrol); 5934 long *valp = ucontrol->value.integer.value; 5935 hda_nid_t shared_nid = 0; 5936 bool effective; 5937 int changed = 1; 5938 5939 /* store the left and right volume */ 5940 if (ch & 1) { 5941 spec->vnode_lvol[nid - VNODE_START_NID] = *valp; 5942 valp++; 5943 } 5944 if (ch & 2) { 5945 spec->vnode_rvol[nid - VNODE_START_NID] = *valp; 5946 valp++; 5947 } 5948 5949 /* if effective conditions, then update hw immediately. */ 5950 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid); 5951 if (effective) { 5952 int dir = get_amp_direction(kcontrol); 5953 unsigned long pval; 5954 5955 snd_hda_power_up(codec); 5956 mutex_lock(&codec->control_mutex); 5957 pval = kcontrol->private_value; 5958 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch, 5959 0, dir); 5960 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol); 5961 kcontrol->private_value = pval; 5962 mutex_unlock(&codec->control_mutex); 5963 snd_hda_power_down(codec); 5964 } 5965 5966 return changed; 5967 } 5968 5969 /* 5970 * This function is the same as the one above, because using an if statement 5971 * inside of the above volume control for the DSP volume would cause too much 5972 * lag. This is a lot more smooth. 5973 */ 5974 static int ca0132_alt_volume_put(struct snd_kcontrol *kcontrol, 5975 struct snd_ctl_elem_value *ucontrol) 5976 { 5977 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5978 struct ca0132_spec *spec = codec->spec; 5979 hda_nid_t nid = get_amp_nid(kcontrol); 5980 int ch = get_amp_channels(kcontrol); 5981 long *valp = ucontrol->value.integer.value; 5982 hda_nid_t vnid = 0; 5983 int changed = 1; 5984 5985 switch (nid) { 5986 case 0x02: 5987 vnid = VNID_SPK; 5988 break; 5989 case 0x07: 5990 vnid = VNID_MIC; 5991 break; 5992 } 5993 5994 /* store the left and right volume */ 5995 if (ch & 1) { 5996 spec->vnode_lvol[vnid - VNODE_START_NID] = *valp; 5997 valp++; 5998 } 5999 if (ch & 2) { 6000 spec->vnode_rvol[vnid - VNODE_START_NID] = *valp; 6001 valp++; 6002 } 6003 6004 snd_hda_power_up(codec); 6005 ca0132_alt_dsp_volume_put(codec, vnid); 6006 mutex_lock(&codec->control_mutex); 6007 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol); 6008 mutex_unlock(&codec->control_mutex); 6009 snd_hda_power_down(codec); 6010 6011 return changed; 6012 } 6013 6014 static int ca0132_volume_tlv(struct snd_kcontrol *kcontrol, int op_flag, 6015 unsigned int size, unsigned int __user *tlv) 6016 { 6017 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6018 struct ca0132_spec *spec = codec->spec; 6019 hda_nid_t nid = get_amp_nid(kcontrol); 6020 int ch = get_amp_channels(kcontrol); 6021 int dir = get_amp_direction(kcontrol); 6022 unsigned long pval; 6023 int err; 6024 6025 switch (nid) { 6026 case VNID_SPK: 6027 /* follow shared_out tlv */ 6028 nid = spec->shared_out_nid; 6029 mutex_lock(&codec->control_mutex); 6030 pval = kcontrol->private_value; 6031 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); 6032 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv); 6033 kcontrol->private_value = pval; 6034 mutex_unlock(&codec->control_mutex); 6035 break; 6036 case VNID_MIC: 6037 /* follow shared_mic tlv */ 6038 nid = spec->shared_mic_nid; 6039 mutex_lock(&codec->control_mutex); 6040 pval = kcontrol->private_value; 6041 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); 6042 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv); 6043 kcontrol->private_value = pval; 6044 mutex_unlock(&codec->control_mutex); 6045 break; 6046 default: 6047 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv); 6048 } 6049 return err; 6050 } 6051 6052 /* Add volume slider control for effect level */ 6053 static int ca0132_alt_add_effect_slider(struct hda_codec *codec, hda_nid_t nid, 6054 const char *pfx, int dir) 6055 { 6056 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 6057 int type = dir ? HDA_INPUT : HDA_OUTPUT; 6058 struct snd_kcontrol_new knew = 6059 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type); 6060 6061 sprintf(namestr, "FX: %s %s Volume", pfx, dirstr[dir]); 6062 6063 knew.tlv.c = NULL; 6064 6065 switch (nid) { 6066 case XBASS_XOVER: 6067 knew.info = ca0132_alt_xbass_xover_slider_info; 6068 knew.get = ca0132_alt_xbass_xover_slider_ctl_get; 6069 knew.put = ca0132_alt_xbass_xover_slider_put; 6070 break; 6071 default: 6072 knew.info = ca0132_alt_effect_slider_info; 6073 knew.get = ca0132_alt_slider_ctl_get; 6074 knew.put = ca0132_alt_effect_slider_put; 6075 knew.private_value = 6076 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type); 6077 break; 6078 } 6079 6080 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec)); 6081 } 6082 6083 /* 6084 * Added FX: prefix for the alternative codecs, because otherwise the surround 6085 * effect would conflict with the Surround sound volume control. Also seems more 6086 * clear as to what the switches do. Left alone for others. 6087 */ 6088 static int add_fx_switch(struct hda_codec *codec, hda_nid_t nid, 6089 const char *pfx, int dir) 6090 { 6091 struct ca0132_spec *spec = codec->spec; 6092 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 6093 int type = dir ? HDA_INPUT : HDA_OUTPUT; 6094 struct snd_kcontrol_new knew = 6095 CA0132_CODEC_MUTE_MONO(namestr, nid, 1, type); 6096 /* If using alt_controls, add FX: prefix. But, don't add FX: 6097 * prefix to OutFX or InFX enable controls. 6098 */ 6099 if (ca0132_use_alt_controls(spec) && (nid <= IN_EFFECT_END_NID)) 6100 sprintf(namestr, "FX: %s %s Switch", pfx, dirstr[dir]); 6101 else 6102 sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]); 6103 6104 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec)); 6105 } 6106 6107 static int add_voicefx(struct hda_codec *codec) 6108 { 6109 struct snd_kcontrol_new knew = 6110 HDA_CODEC_MUTE_MONO(ca0132_voicefx.name, 6111 VOICEFX, 1, 0, HDA_INPUT); 6112 knew.info = ca0132_voicefx_info; 6113 knew.get = ca0132_voicefx_get; 6114 knew.put = ca0132_voicefx_put; 6115 return snd_hda_ctl_add(codec, VOICEFX, snd_ctl_new1(&knew, codec)); 6116 } 6117 6118 /* Create the EQ Preset control */ 6119 static int add_ca0132_alt_eq_presets(struct hda_codec *codec) 6120 { 6121 struct snd_kcontrol_new knew = 6122 HDA_CODEC_MUTE_MONO(ca0132_alt_eq_enum.name, 6123 EQ_PRESET_ENUM, 1, 0, HDA_OUTPUT); 6124 knew.info = ca0132_alt_eq_preset_info; 6125 knew.get = ca0132_alt_eq_preset_get; 6126 knew.put = ca0132_alt_eq_preset_put; 6127 return snd_hda_ctl_add(codec, EQ_PRESET_ENUM, 6128 snd_ctl_new1(&knew, codec)); 6129 } 6130 6131 /* 6132 * Add enumerated control for the three different settings of the smart volume 6133 * output effect. Normal just uses the slider value, and loud and night are 6134 * their own things that ignore that value. 6135 */ 6136 static int ca0132_alt_add_svm_enum(struct hda_codec *codec) 6137 { 6138 struct snd_kcontrol_new knew = 6139 HDA_CODEC_MUTE_MONO("FX: Smart Volume Setting", 6140 SMART_VOLUME_ENUM, 1, 0, HDA_OUTPUT); 6141 knew.info = ca0132_alt_svm_setting_info; 6142 knew.get = ca0132_alt_svm_setting_get; 6143 knew.put = ca0132_alt_svm_setting_put; 6144 return snd_hda_ctl_add(codec, SMART_VOLUME_ENUM, 6145 snd_ctl_new1(&knew, codec)); 6146 6147 } 6148 6149 /* 6150 * Create an Output Select enumerated control for codecs with surround 6151 * out capabilities. 6152 */ 6153 static int ca0132_alt_add_output_enum(struct hda_codec *codec) 6154 { 6155 struct snd_kcontrol_new knew = 6156 HDA_CODEC_MUTE_MONO("Output Select", 6157 OUTPUT_SOURCE_ENUM, 1, 0, HDA_OUTPUT); 6158 knew.info = ca0132_alt_output_select_get_info; 6159 knew.get = ca0132_alt_output_select_get; 6160 knew.put = ca0132_alt_output_select_put; 6161 return snd_hda_ctl_add(codec, OUTPUT_SOURCE_ENUM, 6162 snd_ctl_new1(&knew, codec)); 6163 } 6164 6165 /* 6166 * Create an Input Source enumerated control for the alternate ca0132 codecs 6167 * because the front microphone has no auto-detect, and Line-in has to be set 6168 * somehow. 6169 */ 6170 static int ca0132_alt_add_input_enum(struct hda_codec *codec) 6171 { 6172 struct snd_kcontrol_new knew = 6173 HDA_CODEC_MUTE_MONO("Input Source", 6174 INPUT_SOURCE_ENUM, 1, 0, HDA_INPUT); 6175 knew.info = ca0132_alt_input_source_info; 6176 knew.get = ca0132_alt_input_source_get; 6177 knew.put = ca0132_alt_input_source_put; 6178 return snd_hda_ctl_add(codec, INPUT_SOURCE_ENUM, 6179 snd_ctl_new1(&knew, codec)); 6180 } 6181 6182 /* 6183 * Add mic boost enumerated control. Switches through 0dB to 30dB. This adds 6184 * more control than the original mic boost, which is either full 30dB or off. 6185 */ 6186 static int ca0132_alt_add_mic_boost_enum(struct hda_codec *codec) 6187 { 6188 struct snd_kcontrol_new knew = 6189 HDA_CODEC_MUTE_MONO("Mic Boost Capture Switch", 6190 MIC_BOOST_ENUM, 1, 0, HDA_INPUT); 6191 knew.info = ca0132_alt_mic_boost_info; 6192 knew.get = ca0132_alt_mic_boost_get; 6193 knew.put = ca0132_alt_mic_boost_put; 6194 return snd_hda_ctl_add(codec, MIC_BOOST_ENUM, 6195 snd_ctl_new1(&knew, codec)); 6196 6197 } 6198 6199 /* 6200 * Add headphone gain enumerated control for the AE-5. This switches between 6201 * three modes, low, medium, and high. When non-headphone outputs are selected, 6202 * it is automatically set to high. This is the same behavior as Windows. 6203 */ 6204 static int ae5_add_headphone_gain_enum(struct hda_codec *codec) 6205 { 6206 struct snd_kcontrol_new knew = 6207 HDA_CODEC_MUTE_MONO("AE-5: Headphone Gain", 6208 AE5_HEADPHONE_GAIN_ENUM, 1, 0, HDA_OUTPUT); 6209 knew.info = ae5_headphone_gain_info; 6210 knew.get = ae5_headphone_gain_get; 6211 knew.put = ae5_headphone_gain_put; 6212 return snd_hda_ctl_add(codec, AE5_HEADPHONE_GAIN_ENUM, 6213 snd_ctl_new1(&knew, codec)); 6214 } 6215 6216 /* 6217 * Add sound filter enumerated control for the AE-5. This adds three different 6218 * settings: Slow Roll Off, Minimum Phase, and Fast Roll Off. From what I've 6219 * read into it, it changes the DAC's interpolation filter. 6220 */ 6221 static int ae5_add_sound_filter_enum(struct hda_codec *codec) 6222 { 6223 struct snd_kcontrol_new knew = 6224 HDA_CODEC_MUTE_MONO("AE-5: Sound Filter", 6225 AE5_SOUND_FILTER_ENUM, 1, 0, HDA_OUTPUT); 6226 knew.info = ae5_sound_filter_info; 6227 knew.get = ae5_sound_filter_get; 6228 knew.put = ae5_sound_filter_put; 6229 return snd_hda_ctl_add(codec, AE5_SOUND_FILTER_ENUM, 6230 snd_ctl_new1(&knew, codec)); 6231 } 6232 6233 static int zxr_add_headphone_gain_switch(struct hda_codec *codec) 6234 { 6235 struct snd_kcontrol_new knew = 6236 CA0132_CODEC_MUTE_MONO("ZxR: 600 Ohm Gain", 6237 ZXR_HEADPHONE_GAIN, 1, HDA_OUTPUT); 6238 6239 return snd_hda_ctl_add(codec, ZXR_HEADPHONE_GAIN, 6240 snd_ctl_new1(&knew, codec)); 6241 } 6242 6243 /* 6244 * Need to create slave controls for the alternate codecs that have surround 6245 * capabilities. 6246 */ 6247 static const char * const ca0132_alt_slave_pfxs[] = { 6248 "Front", "Surround", "Center", "LFE", NULL, 6249 }; 6250 6251 /* 6252 * Also need special channel map, because the default one is incorrect. 6253 * I think this has to do with the pin for rear surround being 0x11, 6254 * and the center/lfe being 0x10. Usually the pin order is the opposite. 6255 */ 6256 static const struct snd_pcm_chmap_elem ca0132_alt_chmaps[] = { 6257 { .channels = 2, 6258 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR } }, 6259 { .channels = 4, 6260 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR, 6261 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } }, 6262 { .channels = 6, 6263 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR, 6264 SNDRV_CHMAP_FC, SNDRV_CHMAP_LFE, 6265 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } }, 6266 { } 6267 }; 6268 6269 /* Add the correct chmap for streams with 6 channels. */ 6270 static void ca0132_alt_add_chmap_ctls(struct hda_codec *codec) 6271 { 6272 int err = 0; 6273 struct hda_pcm *pcm; 6274 6275 list_for_each_entry(pcm, &codec->pcm_list_head, list) { 6276 struct hda_pcm_stream *hinfo = 6277 &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK]; 6278 struct snd_pcm_chmap *chmap; 6279 const struct snd_pcm_chmap_elem *elem; 6280 6281 elem = ca0132_alt_chmaps; 6282 if (hinfo->channels_max == 6) { 6283 err = snd_pcm_add_chmap_ctls(pcm->pcm, 6284 SNDRV_PCM_STREAM_PLAYBACK, 6285 elem, hinfo->channels_max, 0, &chmap); 6286 if (err < 0) 6287 codec_dbg(codec, "snd_pcm_add_chmap_ctls failed!"); 6288 } 6289 } 6290 } 6291 6292 /* 6293 * When changing Node IDs for Mixer Controls below, make sure to update 6294 * Node IDs in ca0132_config() as well. 6295 */ 6296 static const struct snd_kcontrol_new ca0132_mixer[] = { 6297 CA0132_CODEC_VOL("Master Playback Volume", VNID_SPK, HDA_OUTPUT), 6298 CA0132_CODEC_MUTE("Master Playback Switch", VNID_SPK, HDA_OUTPUT), 6299 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT), 6300 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT), 6301 HDA_CODEC_VOLUME("Analog-Mic2 Capture Volume", 0x08, 0, HDA_INPUT), 6302 HDA_CODEC_MUTE("Analog-Mic2 Capture Switch", 0x08, 0, HDA_INPUT), 6303 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT), 6304 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT), 6305 CA0132_CODEC_MUTE_MONO("Mic1-Boost (30dB) Capture Switch", 6306 0x12, 1, HDA_INPUT), 6307 CA0132_CODEC_MUTE_MONO("HP/Speaker Playback Switch", 6308 VNID_HP_SEL, 1, HDA_OUTPUT), 6309 CA0132_CODEC_MUTE_MONO("AMic1/DMic Capture Switch", 6310 VNID_AMIC1_SEL, 1, HDA_INPUT), 6311 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch", 6312 VNID_HP_ASEL, 1, HDA_OUTPUT), 6313 CA0132_CODEC_MUTE_MONO("AMic1/DMic Auto Detect Capture Switch", 6314 VNID_AMIC1_ASEL, 1, HDA_INPUT), 6315 { } /* end */ 6316 }; 6317 6318 /* 6319 * Desktop specific control mixer. Removes auto-detect for mic, and adds 6320 * surround controls. Also sets both the Front Playback and Capture Volume 6321 * controls to alt so they set the DSP's decibel level. 6322 */ 6323 static const struct snd_kcontrol_new desktop_mixer[] = { 6324 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT), 6325 CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT), 6326 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT), 6327 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT), 6328 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT), 6329 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT), 6330 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT), 6331 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT), 6332 CA0132_ALT_CODEC_VOL("Capture Volume", 0x07, HDA_INPUT), 6333 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT), 6334 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT), 6335 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT), 6336 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch", 6337 VNID_HP_ASEL, 1, HDA_OUTPUT), 6338 { } /* end */ 6339 }; 6340 6341 /* 6342 * Same as the Sound Blaster Z, except doesn't use the alt volume for capture 6343 * because it doesn't set decibel levels for the DSP for capture. 6344 */ 6345 static const struct snd_kcontrol_new r3di_mixer[] = { 6346 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT), 6347 CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT), 6348 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT), 6349 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT), 6350 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT), 6351 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT), 6352 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT), 6353 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT), 6354 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT), 6355 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT), 6356 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT), 6357 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT), 6358 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch", 6359 VNID_HP_ASEL, 1, HDA_OUTPUT), 6360 { } /* end */ 6361 }; 6362 6363 static int ca0132_build_controls(struct hda_codec *codec) 6364 { 6365 struct ca0132_spec *spec = codec->spec; 6366 int i, num_fx, num_sliders; 6367 int err = 0; 6368 6369 /* Add Mixer controls */ 6370 for (i = 0; i < spec->num_mixers; i++) { 6371 err = snd_hda_add_new_ctls(codec, spec->mixers[i]); 6372 if (err < 0) 6373 return err; 6374 } 6375 /* Setup vmaster with surround slaves for desktop ca0132 devices */ 6376 if (ca0132_use_alt_functions(spec)) { 6377 snd_hda_set_vmaster_tlv(codec, spec->dacs[0], HDA_OUTPUT, 6378 spec->tlv); 6379 snd_hda_add_vmaster(codec, "Master Playback Volume", 6380 spec->tlv, ca0132_alt_slave_pfxs, 6381 "Playback Volume"); 6382 err = __snd_hda_add_vmaster(codec, "Master Playback Switch", 6383 NULL, ca0132_alt_slave_pfxs, 6384 "Playback Switch", 6385 true, &spec->vmaster_mute.sw_kctl); 6386 if (err < 0) 6387 return err; 6388 } 6389 6390 /* Add in and out effects controls. 6391 * VoiceFX, PE and CrystalVoice are added separately. 6392 */ 6393 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT; 6394 for (i = 0; i < num_fx; i++) { 6395 /* Desktop cards break if Echo Cancellation is used. */ 6396 if (ca0132_use_pci_mmio(spec)) { 6397 if (i == (ECHO_CANCELLATION - IN_EFFECT_START_NID + 6398 OUT_EFFECTS_COUNT)) 6399 continue; 6400 } 6401 6402 err = add_fx_switch(codec, ca0132_effects[i].nid, 6403 ca0132_effects[i].name, 6404 ca0132_effects[i].direct); 6405 if (err < 0) 6406 return err; 6407 } 6408 /* 6409 * If codec has use_alt_controls set to true, add effect level sliders, 6410 * EQ presets, and Smart Volume presets. Also, change names to add FX 6411 * prefix, and change PlayEnhancement and CrystalVoice to match. 6412 */ 6413 if (ca0132_use_alt_controls(spec)) { 6414 err = ca0132_alt_add_svm_enum(codec); 6415 if (err < 0) 6416 return err; 6417 6418 err = add_ca0132_alt_eq_presets(codec); 6419 if (err < 0) 6420 return err; 6421 6422 err = add_fx_switch(codec, PLAY_ENHANCEMENT, 6423 "Enable OutFX", 0); 6424 if (err < 0) 6425 return err; 6426 6427 err = add_fx_switch(codec, CRYSTAL_VOICE, 6428 "Enable InFX", 1); 6429 if (err < 0) 6430 return err; 6431 6432 num_sliders = OUT_EFFECTS_COUNT - 1; 6433 for (i = 0; i < num_sliders; i++) { 6434 err = ca0132_alt_add_effect_slider(codec, 6435 ca0132_effects[i].nid, 6436 ca0132_effects[i].name, 6437 ca0132_effects[i].direct); 6438 if (err < 0) 6439 return err; 6440 } 6441 6442 err = ca0132_alt_add_effect_slider(codec, XBASS_XOVER, 6443 "X-Bass Crossover", EFX_DIR_OUT); 6444 6445 if (err < 0) 6446 return err; 6447 } else { 6448 err = add_fx_switch(codec, PLAY_ENHANCEMENT, 6449 "PlayEnhancement", 0); 6450 if (err < 0) 6451 return err; 6452 6453 err = add_fx_switch(codec, CRYSTAL_VOICE, 6454 "CrystalVoice", 1); 6455 if (err < 0) 6456 return err; 6457 } 6458 err = add_voicefx(codec); 6459 if (err < 0) 6460 return err; 6461 6462 /* 6463 * If the codec uses alt_functions, you need the enumerated controls 6464 * to select the new outputs and inputs, plus add the new mic boost 6465 * setting control. 6466 */ 6467 if (ca0132_use_alt_functions(spec)) { 6468 err = ca0132_alt_add_output_enum(codec); 6469 if (err < 0) 6470 return err; 6471 err = ca0132_alt_add_mic_boost_enum(codec); 6472 if (err < 0) 6473 return err; 6474 /* 6475 * ZxR only has microphone input, there is no front panel 6476 * header on the card, and aux-in is handled by the DBPro board. 6477 */ 6478 if (ca0132_quirk(spec) != QUIRK_ZXR) { 6479 err = ca0132_alt_add_input_enum(codec); 6480 if (err < 0) 6481 return err; 6482 } 6483 } 6484 6485 if (ca0132_quirk(spec) == QUIRK_AE5) { 6486 err = ae5_add_headphone_gain_enum(codec); 6487 if (err < 0) 6488 return err; 6489 err = ae5_add_sound_filter_enum(codec); 6490 if (err < 0) 6491 return err; 6492 } 6493 6494 if (ca0132_quirk(spec) == QUIRK_ZXR) { 6495 err = zxr_add_headphone_gain_switch(codec); 6496 if (err < 0) 6497 return err; 6498 } 6499 #ifdef ENABLE_TUNING_CONTROLS 6500 add_tuning_ctls(codec); 6501 #endif 6502 6503 err = snd_hda_jack_add_kctls(codec, &spec->autocfg); 6504 if (err < 0) 6505 return err; 6506 6507 if (spec->dig_out) { 6508 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out, 6509 spec->dig_out); 6510 if (err < 0) 6511 return err; 6512 err = snd_hda_create_spdif_share_sw(codec, &spec->multiout); 6513 if (err < 0) 6514 return err; 6515 /* spec->multiout.share_spdif = 1; */ 6516 } 6517 6518 if (spec->dig_in) { 6519 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in); 6520 if (err < 0) 6521 return err; 6522 } 6523 6524 if (ca0132_use_alt_functions(spec)) 6525 ca0132_alt_add_chmap_ctls(codec); 6526 6527 return 0; 6528 } 6529 6530 static int dbpro_build_controls(struct hda_codec *codec) 6531 { 6532 struct ca0132_spec *spec = codec->spec; 6533 int err = 0; 6534 6535 if (spec->dig_out) { 6536 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out, 6537 spec->dig_out); 6538 if (err < 0) 6539 return err; 6540 } 6541 6542 if (spec->dig_in) { 6543 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in); 6544 if (err < 0) 6545 return err; 6546 } 6547 6548 return 0; 6549 } 6550 6551 /* 6552 * PCM 6553 */ 6554 static const struct hda_pcm_stream ca0132_pcm_analog_playback = { 6555 .substreams = 1, 6556 .channels_min = 2, 6557 .channels_max = 6, 6558 .ops = { 6559 .prepare = ca0132_playback_pcm_prepare, 6560 .cleanup = ca0132_playback_pcm_cleanup, 6561 .get_delay = ca0132_playback_pcm_delay, 6562 }, 6563 }; 6564 6565 static const struct hda_pcm_stream ca0132_pcm_analog_capture = { 6566 .substreams = 1, 6567 .channels_min = 2, 6568 .channels_max = 2, 6569 .ops = { 6570 .prepare = ca0132_capture_pcm_prepare, 6571 .cleanup = ca0132_capture_pcm_cleanup, 6572 .get_delay = ca0132_capture_pcm_delay, 6573 }, 6574 }; 6575 6576 static const struct hda_pcm_stream ca0132_pcm_digital_playback = { 6577 .substreams = 1, 6578 .channels_min = 2, 6579 .channels_max = 2, 6580 .ops = { 6581 .open = ca0132_dig_playback_pcm_open, 6582 .close = ca0132_dig_playback_pcm_close, 6583 .prepare = ca0132_dig_playback_pcm_prepare, 6584 .cleanup = ca0132_dig_playback_pcm_cleanup 6585 }, 6586 }; 6587 6588 static const struct hda_pcm_stream ca0132_pcm_digital_capture = { 6589 .substreams = 1, 6590 .channels_min = 2, 6591 .channels_max = 2, 6592 }; 6593 6594 static int ca0132_build_pcms(struct hda_codec *codec) 6595 { 6596 struct ca0132_spec *spec = codec->spec; 6597 struct hda_pcm *info; 6598 6599 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog"); 6600 if (!info) 6601 return -ENOMEM; 6602 if (ca0132_use_alt_functions(spec)) { 6603 info->own_chmap = true; 6604 info->stream[SNDRV_PCM_STREAM_PLAYBACK].chmap 6605 = ca0132_alt_chmaps; 6606 } 6607 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback; 6608 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0]; 6609 info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max = 6610 spec->multiout.max_channels; 6611 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture; 6612 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1; 6613 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0]; 6614 6615 /* With the DSP enabled, desktops don't use this ADC. */ 6616 if (!ca0132_use_alt_functions(spec)) { 6617 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog Mic-In2"); 6618 if (!info) 6619 return -ENOMEM; 6620 info->stream[SNDRV_PCM_STREAM_CAPTURE] = 6621 ca0132_pcm_analog_capture; 6622 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1; 6623 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[1]; 6624 } 6625 6626 info = snd_hda_codec_pcm_new(codec, "CA0132 What U Hear"); 6627 if (!info) 6628 return -ENOMEM; 6629 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture; 6630 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1; 6631 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[2]; 6632 6633 if (!spec->dig_out && !spec->dig_in) 6634 return 0; 6635 6636 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital"); 6637 if (!info) 6638 return -ENOMEM; 6639 info->pcm_type = HDA_PCM_TYPE_SPDIF; 6640 if (spec->dig_out) { 6641 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = 6642 ca0132_pcm_digital_playback; 6643 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out; 6644 } 6645 if (spec->dig_in) { 6646 info->stream[SNDRV_PCM_STREAM_CAPTURE] = 6647 ca0132_pcm_digital_capture; 6648 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in; 6649 } 6650 6651 return 0; 6652 } 6653 6654 static int dbpro_build_pcms(struct hda_codec *codec) 6655 { 6656 struct ca0132_spec *spec = codec->spec; 6657 struct hda_pcm *info; 6658 6659 info = snd_hda_codec_pcm_new(codec, "CA0132 Alt Analog"); 6660 if (!info) 6661 return -ENOMEM; 6662 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture; 6663 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1; 6664 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0]; 6665 6666 6667 if (!spec->dig_out && !spec->dig_in) 6668 return 0; 6669 6670 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital"); 6671 if (!info) 6672 return -ENOMEM; 6673 info->pcm_type = HDA_PCM_TYPE_SPDIF; 6674 if (spec->dig_out) { 6675 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = 6676 ca0132_pcm_digital_playback; 6677 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out; 6678 } 6679 if (spec->dig_in) { 6680 info->stream[SNDRV_PCM_STREAM_CAPTURE] = 6681 ca0132_pcm_digital_capture; 6682 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in; 6683 } 6684 6685 return 0; 6686 } 6687 6688 static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac) 6689 { 6690 if (pin) { 6691 snd_hda_set_pin_ctl(codec, pin, PIN_HP); 6692 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP) 6693 snd_hda_codec_write(codec, pin, 0, 6694 AC_VERB_SET_AMP_GAIN_MUTE, 6695 AMP_OUT_UNMUTE); 6696 } 6697 if (dac && (get_wcaps(codec, dac) & AC_WCAP_OUT_AMP)) 6698 snd_hda_codec_write(codec, dac, 0, 6699 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO); 6700 } 6701 6702 static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc) 6703 { 6704 if (pin) { 6705 snd_hda_set_pin_ctl(codec, pin, PIN_VREF80); 6706 if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP) 6707 snd_hda_codec_write(codec, pin, 0, 6708 AC_VERB_SET_AMP_GAIN_MUTE, 6709 AMP_IN_UNMUTE(0)); 6710 } 6711 if (adc && (get_wcaps(codec, adc) & AC_WCAP_IN_AMP)) { 6712 snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE, 6713 AMP_IN_UNMUTE(0)); 6714 6715 /* init to 0 dB and unmute. */ 6716 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0, 6717 HDA_AMP_VOLMASK, 0x5a); 6718 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0, 6719 HDA_AMP_MUTE, 0); 6720 } 6721 } 6722 6723 static void refresh_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir) 6724 { 6725 unsigned int caps; 6726 6727 caps = snd_hda_param_read(codec, nid, dir == HDA_OUTPUT ? 6728 AC_PAR_AMP_OUT_CAP : AC_PAR_AMP_IN_CAP); 6729 snd_hda_override_amp_caps(codec, nid, dir, caps); 6730 } 6731 6732 /* 6733 * Switch between Digital built-in mic and analog mic. 6734 */ 6735 static void ca0132_set_dmic(struct hda_codec *codec, int enable) 6736 { 6737 struct ca0132_spec *spec = codec->spec; 6738 unsigned int tmp; 6739 u8 val; 6740 unsigned int oldval; 6741 6742 codec_dbg(codec, "ca0132_set_dmic: enable=%d\n", enable); 6743 6744 oldval = stop_mic1(codec); 6745 ca0132_set_vipsource(codec, 0); 6746 if (enable) { 6747 /* set DMic input as 2-ch */ 6748 tmp = FLOAT_TWO; 6749 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 6750 6751 val = spec->dmic_ctl; 6752 val |= 0x80; 6753 snd_hda_codec_write(codec, spec->input_pins[0], 0, 6754 VENDOR_CHIPIO_DMIC_CTL_SET, val); 6755 6756 if (!(spec->dmic_ctl & 0x20)) 6757 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 1); 6758 } else { 6759 /* set AMic input as mono */ 6760 tmp = FLOAT_ONE; 6761 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 6762 6763 val = spec->dmic_ctl; 6764 /* clear bit7 and bit5 to disable dmic */ 6765 val &= 0x5f; 6766 snd_hda_codec_write(codec, spec->input_pins[0], 0, 6767 VENDOR_CHIPIO_DMIC_CTL_SET, val); 6768 6769 if (!(spec->dmic_ctl & 0x20)) 6770 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0); 6771 } 6772 ca0132_set_vipsource(codec, 1); 6773 resume_mic1(codec, oldval); 6774 } 6775 6776 /* 6777 * Initialization for Digital Mic. 6778 */ 6779 static void ca0132_init_dmic(struct hda_codec *codec) 6780 { 6781 struct ca0132_spec *spec = codec->spec; 6782 u8 val; 6783 6784 /* Setup Digital Mic here, but don't enable. 6785 * Enable based on jack detect. 6786 */ 6787 6788 /* MCLK uses MPIO1, set to enable. 6789 * Bit 2-0: MPIO select 6790 * Bit 3: set to disable 6791 * Bit 7-4: reserved 6792 */ 6793 val = 0x01; 6794 snd_hda_codec_write(codec, spec->input_pins[0], 0, 6795 VENDOR_CHIPIO_DMIC_MCLK_SET, val); 6796 6797 /* Data1 uses MPIO3. Data2 not use 6798 * Bit 2-0: Data1 MPIO select 6799 * Bit 3: set disable Data1 6800 * Bit 6-4: Data2 MPIO select 6801 * Bit 7: set disable Data2 6802 */ 6803 val = 0x83; 6804 snd_hda_codec_write(codec, spec->input_pins[0], 0, 6805 VENDOR_CHIPIO_DMIC_PIN_SET, val); 6806 6807 /* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first. 6808 * Bit 3-0: Channel mask 6809 * Bit 4: set for 48KHz, clear for 32KHz 6810 * Bit 5: mode 6811 * Bit 6: set to select Data2, clear for Data1 6812 * Bit 7: set to enable DMic, clear for AMic 6813 */ 6814 if (ca0132_quirk(spec) == QUIRK_ALIENWARE_M17XR4) 6815 val = 0x33; 6816 else 6817 val = 0x23; 6818 /* keep a copy of dmic ctl val for enable/disable dmic purpuse */ 6819 spec->dmic_ctl = val; 6820 snd_hda_codec_write(codec, spec->input_pins[0], 0, 6821 VENDOR_CHIPIO_DMIC_CTL_SET, val); 6822 } 6823 6824 /* 6825 * Initialization for Analog Mic 2 6826 */ 6827 static void ca0132_init_analog_mic2(struct hda_codec *codec) 6828 { 6829 struct ca0132_spec *spec = codec->spec; 6830 6831 mutex_lock(&spec->chipio_mutex); 6832 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 6833 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20); 6834 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 6835 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19); 6836 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 6837 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00); 6838 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 6839 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x2D); 6840 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 6841 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19); 6842 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 6843 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00); 6844 mutex_unlock(&spec->chipio_mutex); 6845 } 6846 6847 static void ca0132_refresh_widget_caps(struct hda_codec *codec) 6848 { 6849 struct ca0132_spec *spec = codec->spec; 6850 int i; 6851 6852 codec_dbg(codec, "ca0132_refresh_widget_caps.\n"); 6853 snd_hda_codec_update_widgets(codec); 6854 6855 for (i = 0; i < spec->multiout.num_dacs; i++) 6856 refresh_amp_caps(codec, spec->dacs[i], HDA_OUTPUT); 6857 6858 for (i = 0; i < spec->num_outputs; i++) 6859 refresh_amp_caps(codec, spec->out_pins[i], HDA_OUTPUT); 6860 6861 for (i = 0; i < spec->num_inputs; i++) { 6862 refresh_amp_caps(codec, spec->adcs[i], HDA_INPUT); 6863 refresh_amp_caps(codec, spec->input_pins[i], HDA_INPUT); 6864 } 6865 } 6866 6867 /* 6868 * Creates a dummy stream to bind the output to. This seems to have to be done 6869 * after changing the main outputs source and destination streams. 6870 */ 6871 static void ca0132_alt_create_dummy_stream(struct hda_codec *codec) 6872 { 6873 struct ca0132_spec *spec = codec->spec; 6874 unsigned int stream_format; 6875 6876 stream_format = snd_hdac_calc_stream_format(48000, 2, 6877 SNDRV_PCM_FORMAT_S32_LE, 32, 0); 6878 6879 snd_hda_codec_setup_stream(codec, spec->dacs[0], spec->dsp_stream_id, 6880 0, stream_format); 6881 6882 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]); 6883 } 6884 6885 /* 6886 * Initialize mic for non-chromebook ca0132 implementations. 6887 */ 6888 static void ca0132_alt_init_analog_mics(struct hda_codec *codec) 6889 { 6890 struct ca0132_spec *spec = codec->spec; 6891 unsigned int tmp; 6892 6893 /* Mic 1 Setup */ 6894 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 6895 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 6896 if (ca0132_quirk(spec) == QUIRK_R3DI) { 6897 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 6898 tmp = FLOAT_ONE; 6899 } else 6900 tmp = FLOAT_THREE; 6901 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 6902 6903 /* Mic 2 setup (not present on desktop cards) */ 6904 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, SR_96_000); 6905 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, SR_96_000); 6906 if (ca0132_quirk(spec) == QUIRK_R3DI) 6907 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 6908 tmp = FLOAT_ZERO; 6909 dspio_set_uint_param(codec, 0x80, 0x01, tmp); 6910 } 6911 6912 /* 6913 * Sets the source of stream 0x14 to connpointID 0x48, and the destination 6914 * connpointID to 0x91. If this isn't done, the destination is 0x71, and 6915 * you get no sound. I'm guessing this has to do with the Sound Blaster Z 6916 * having an updated DAC, which changes the destination to that DAC. 6917 */ 6918 static void sbz_connect_streams(struct hda_codec *codec) 6919 { 6920 struct ca0132_spec *spec = codec->spec; 6921 6922 mutex_lock(&spec->chipio_mutex); 6923 6924 codec_dbg(codec, "Connect Streams entered, mutex locked and loaded.\n"); 6925 6926 chipio_set_stream_channels(codec, 0x0C, 6); 6927 chipio_set_stream_control(codec, 0x0C, 1); 6928 6929 /* This value is 0x43 for 96khz, and 0x83 for 192khz. */ 6930 chipio_write_no_mutex(codec, 0x18a020, 0x00000043); 6931 6932 /* Setup stream 0x14 with it's source and destination points */ 6933 chipio_set_stream_source_dest(codec, 0x14, 0x48, 0x91); 6934 chipio_set_conn_rate_no_mutex(codec, 0x48, SR_96_000); 6935 chipio_set_conn_rate_no_mutex(codec, 0x91, SR_96_000); 6936 chipio_set_stream_channels(codec, 0x14, 2); 6937 chipio_set_stream_control(codec, 0x14, 1); 6938 6939 codec_dbg(codec, "Connect Streams exited, mutex released.\n"); 6940 6941 mutex_unlock(&spec->chipio_mutex); 6942 } 6943 6944 /* 6945 * Write data through ChipIO to setup proper stream destinations. 6946 * Not sure how it exactly works, but it seems to direct data 6947 * to different destinations. Example is f8 to c0, e0 to c0. 6948 * All I know is, if you don't set these, you get no sound. 6949 */ 6950 static void sbz_chipio_startup_data(struct hda_codec *codec) 6951 { 6952 struct ca0132_spec *spec = codec->spec; 6953 6954 mutex_lock(&spec->chipio_mutex); 6955 codec_dbg(codec, "Startup Data entered, mutex locked and loaded.\n"); 6956 6957 /* These control audio output */ 6958 chipio_write_no_mutex(codec, 0x190060, 0x0001f8c0); 6959 chipio_write_no_mutex(codec, 0x190064, 0x0001f9c1); 6960 chipio_write_no_mutex(codec, 0x190068, 0x0001fac6); 6961 chipio_write_no_mutex(codec, 0x19006c, 0x0001fbc7); 6962 /* Signal to update I think */ 6963 chipio_write_no_mutex(codec, 0x19042c, 0x00000001); 6964 6965 chipio_set_stream_channels(codec, 0x0C, 6); 6966 chipio_set_stream_control(codec, 0x0C, 1); 6967 /* No clue what these control */ 6968 if (ca0132_quirk(spec) == QUIRK_SBZ) { 6969 chipio_write_no_mutex(codec, 0x190030, 0x0001e0c0); 6970 chipio_write_no_mutex(codec, 0x190034, 0x0001e1c1); 6971 chipio_write_no_mutex(codec, 0x190038, 0x0001e4c2); 6972 chipio_write_no_mutex(codec, 0x19003c, 0x0001e5c3); 6973 chipio_write_no_mutex(codec, 0x190040, 0x0001e2c4); 6974 chipio_write_no_mutex(codec, 0x190044, 0x0001e3c5); 6975 chipio_write_no_mutex(codec, 0x190048, 0x0001e8c6); 6976 chipio_write_no_mutex(codec, 0x19004c, 0x0001e9c7); 6977 chipio_write_no_mutex(codec, 0x190050, 0x0001ecc8); 6978 chipio_write_no_mutex(codec, 0x190054, 0x0001edc9); 6979 chipio_write_no_mutex(codec, 0x190058, 0x0001eaca); 6980 chipio_write_no_mutex(codec, 0x19005c, 0x0001ebcb); 6981 } else if (ca0132_quirk(spec) == QUIRK_ZXR) { 6982 chipio_write_no_mutex(codec, 0x190038, 0x000140c2); 6983 chipio_write_no_mutex(codec, 0x19003c, 0x000141c3); 6984 chipio_write_no_mutex(codec, 0x190040, 0x000150c4); 6985 chipio_write_no_mutex(codec, 0x190044, 0x000151c5); 6986 chipio_write_no_mutex(codec, 0x190050, 0x000142c8); 6987 chipio_write_no_mutex(codec, 0x190054, 0x000143c9); 6988 chipio_write_no_mutex(codec, 0x190058, 0x000152ca); 6989 chipio_write_no_mutex(codec, 0x19005c, 0x000153cb); 6990 } 6991 chipio_write_no_mutex(codec, 0x19042c, 0x00000001); 6992 6993 codec_dbg(codec, "Startup Data exited, mutex released.\n"); 6994 mutex_unlock(&spec->chipio_mutex); 6995 } 6996 6997 /* 6998 * Custom DSP SCP commands where the src value is 0x00 instead of 0x20. This is 6999 * done after the DSP is loaded. 7000 */ 7001 static void ca0132_alt_dsp_scp_startup(struct hda_codec *codec) 7002 { 7003 struct ca0132_spec *spec = codec->spec; 7004 unsigned int tmp, i; 7005 7006 /* 7007 * Gotta run these twice, or else mic works inconsistently. Not clear 7008 * why this is, but multiple tests have confirmed it. 7009 */ 7010 for (i = 0; i < 2; i++) { 7011 switch (ca0132_quirk(spec)) { 7012 case QUIRK_SBZ: 7013 case QUIRK_AE5: 7014 tmp = 0x00000003; 7015 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); 7016 tmp = 0x00000000; 7017 dspio_set_uint_param_no_source(codec, 0x80, 0x0A, tmp); 7018 tmp = 0x00000001; 7019 dspio_set_uint_param_no_source(codec, 0x80, 0x0B, tmp); 7020 tmp = 0x00000004; 7021 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); 7022 tmp = 0x00000005; 7023 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); 7024 tmp = 0x00000000; 7025 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); 7026 break; 7027 case QUIRK_R3D: 7028 case QUIRK_R3DI: 7029 tmp = 0x00000000; 7030 dspio_set_uint_param_no_source(codec, 0x80, 0x0A, tmp); 7031 tmp = 0x00000001; 7032 dspio_set_uint_param_no_source(codec, 0x80, 0x0B, tmp); 7033 tmp = 0x00000004; 7034 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); 7035 tmp = 0x00000005; 7036 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); 7037 tmp = 0x00000000; 7038 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); 7039 break; 7040 default: 7041 break; 7042 } 7043 msleep(100); 7044 } 7045 } 7046 7047 static void ca0132_alt_dsp_initial_mic_setup(struct hda_codec *codec) 7048 { 7049 struct ca0132_spec *spec = codec->spec; 7050 unsigned int tmp; 7051 7052 chipio_set_stream_control(codec, 0x03, 0); 7053 chipio_set_stream_control(codec, 0x04, 0); 7054 7055 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 7056 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 7057 7058 tmp = FLOAT_THREE; 7059 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 7060 7061 chipio_set_stream_control(codec, 0x03, 1); 7062 chipio_set_stream_control(codec, 0x04, 1); 7063 7064 switch (ca0132_quirk(spec)) { 7065 case QUIRK_SBZ: 7066 chipio_write(codec, 0x18b098, 0x0000000c); 7067 chipio_write(codec, 0x18b09C, 0x0000000c); 7068 break; 7069 case QUIRK_AE5: 7070 chipio_write(codec, 0x18b098, 0x0000000c); 7071 chipio_write(codec, 0x18b09c, 0x0000004c); 7072 break; 7073 default: 7074 break; 7075 } 7076 } 7077 7078 static void ae5_post_dsp_register_set(struct hda_codec *codec) 7079 { 7080 struct ca0132_spec *spec = codec->spec; 7081 7082 chipio_8051_write_direct(codec, 0x93, 0x10); 7083 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7084 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x44); 7085 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7086 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc2); 7087 7088 writeb(0xff, spec->mem_base + 0x304); 7089 writeb(0xff, spec->mem_base + 0x304); 7090 writeb(0xff, spec->mem_base + 0x304); 7091 writeb(0xff, spec->mem_base + 0x304); 7092 writeb(0x00, spec->mem_base + 0x100); 7093 writeb(0xff, spec->mem_base + 0x304); 7094 writeb(0x00, spec->mem_base + 0x100); 7095 writeb(0xff, spec->mem_base + 0x304); 7096 writeb(0x00, spec->mem_base + 0x100); 7097 writeb(0xff, spec->mem_base + 0x304); 7098 writeb(0x00, spec->mem_base + 0x100); 7099 writeb(0xff, spec->mem_base + 0x304); 7100 7101 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x3f); 7102 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f); 7103 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); 7104 } 7105 7106 static void ae5_post_dsp_param_setup(struct hda_codec *codec) 7107 { 7108 /* 7109 * Param3 in the 8051's memory is represented by the ascii string 'mch' 7110 * which seems to be 'multichannel'. This is also mentioned in the 7111 * AE-5's registry values in Windows. 7112 */ 7113 chipio_set_control_param(codec, 3, 0); 7114 /* 7115 * I believe ASI is 'audio serial interface' and that it's used to 7116 * change colors on the external LED strip connected to the AE-5. 7117 */ 7118 chipio_set_control_flag(codec, CONTROL_FLAG_ASI_96KHZ, 1); 7119 7120 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x724, 0x83); 7121 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0); 7122 7123 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7124 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x92); 7125 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7126 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0xfa); 7127 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7128 VENDOR_CHIPIO_8051_DATA_WRITE, 0x22); 7129 } 7130 7131 static void ae5_post_dsp_pll_setup(struct hda_codec *codec) 7132 { 7133 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7134 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x41); 7135 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7136 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc8); 7137 7138 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7139 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x45); 7140 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7141 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xcc); 7142 7143 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7144 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x40); 7145 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7146 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xcb); 7147 7148 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7149 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x43); 7150 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7151 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc7); 7152 7153 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7154 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x51); 7155 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7156 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x8d); 7157 } 7158 7159 static void ae5_post_dsp_stream_setup(struct hda_codec *codec) 7160 { 7161 struct ca0132_spec *spec = codec->spec; 7162 7163 mutex_lock(&spec->chipio_mutex); 7164 7165 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x81); 7166 7167 chipio_set_conn_rate_no_mutex(codec, 0x70, SR_96_000); 7168 7169 chipio_set_stream_channels(codec, 0x0C, 6); 7170 chipio_set_stream_control(codec, 0x0C, 1); 7171 7172 chipio_set_stream_source_dest(codec, 0x5, 0x43, 0x0); 7173 7174 chipio_set_stream_source_dest(codec, 0x18, 0x9, 0xd0); 7175 chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000); 7176 chipio_set_stream_channels(codec, 0x18, 6); 7177 chipio_set_stream_control(codec, 0x18, 1); 7178 7179 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 4); 7180 7181 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7182 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x43); 7183 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7184 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc7); 7185 7186 ca0113_mmio_command_set(codec, 0x48, 0x01, 0x80); 7187 7188 mutex_unlock(&spec->chipio_mutex); 7189 } 7190 7191 static void ae5_post_dsp_startup_data(struct hda_codec *codec) 7192 { 7193 struct ca0132_spec *spec = codec->spec; 7194 7195 mutex_lock(&spec->chipio_mutex); 7196 7197 chipio_write_no_mutex(codec, 0x189000, 0x0001f101); 7198 chipio_write_no_mutex(codec, 0x189004, 0x0001f101); 7199 chipio_write_no_mutex(codec, 0x189024, 0x00014004); 7200 chipio_write_no_mutex(codec, 0x189028, 0x0002000f); 7201 7202 ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05); 7203 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7); 7204 ca0113_mmio_command_set(codec, 0x48, 0x0b, 0x12); 7205 ca0113_mmio_command_set(codec, 0x48, 0x04, 0x00); 7206 ca0113_mmio_command_set(codec, 0x48, 0x06, 0x48); 7207 ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05); 7208 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); 7209 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00); 7210 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00); 7211 ca0113_mmio_gpio_set(codec, 0, true); 7212 ca0113_mmio_gpio_set(codec, 1, true); 7213 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x80); 7214 7215 chipio_write_no_mutex(codec, 0x18b03c, 0x00000012); 7216 7217 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00); 7218 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00); 7219 7220 mutex_unlock(&spec->chipio_mutex); 7221 } 7222 7223 /* 7224 * Setup default parameters for DSP 7225 */ 7226 static void ca0132_setup_defaults(struct hda_codec *codec) 7227 { 7228 struct ca0132_spec *spec = codec->spec; 7229 unsigned int tmp; 7230 int num_fx; 7231 int idx, i; 7232 7233 if (spec->dsp_state != DSP_DOWNLOADED) 7234 return; 7235 7236 /* out, in effects + voicefx */ 7237 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; 7238 for (idx = 0; idx < num_fx; idx++) { 7239 for (i = 0; i <= ca0132_effects[idx].params; i++) { 7240 dspio_set_uint_param(codec, ca0132_effects[idx].mid, 7241 ca0132_effects[idx].reqs[i], 7242 ca0132_effects[idx].def_vals[i]); 7243 } 7244 } 7245 7246 /*remove DSP headroom*/ 7247 tmp = FLOAT_ZERO; 7248 dspio_set_uint_param(codec, 0x96, 0x3C, tmp); 7249 7250 /*set speaker EQ bypass attenuation*/ 7251 dspio_set_uint_param(codec, 0x8f, 0x01, tmp); 7252 7253 /* set AMic1 and AMic2 as mono mic */ 7254 tmp = FLOAT_ONE; 7255 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 7256 dspio_set_uint_param(codec, 0x80, 0x01, tmp); 7257 7258 /* set AMic1 as CrystalVoice input */ 7259 tmp = FLOAT_ONE; 7260 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 7261 7262 /* set WUH source */ 7263 tmp = FLOAT_TWO; 7264 dspio_set_uint_param(codec, 0x31, 0x00, tmp); 7265 } 7266 7267 /* 7268 * Setup default parameters for Recon3D/Recon3Di DSP. 7269 */ 7270 7271 static void r3d_setup_defaults(struct hda_codec *codec) 7272 { 7273 struct ca0132_spec *spec = codec->spec; 7274 unsigned int tmp; 7275 int num_fx; 7276 int idx, i; 7277 7278 if (spec->dsp_state != DSP_DOWNLOADED) 7279 return; 7280 7281 ca0132_alt_dsp_scp_startup(codec); 7282 ca0132_alt_init_analog_mics(codec); 7283 7284 /*remove DSP headroom*/ 7285 tmp = FLOAT_ZERO; 7286 dspio_set_uint_param(codec, 0x96, 0x3C, tmp); 7287 7288 /* set WUH source */ 7289 tmp = FLOAT_TWO; 7290 dspio_set_uint_param(codec, 0x31, 0x00, tmp); 7291 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 7292 7293 /* Set speaker source? */ 7294 dspio_set_uint_param(codec, 0x32, 0x00, tmp); 7295 7296 if (ca0132_quirk(spec) == QUIRK_R3DI) 7297 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADED); 7298 7299 /* Setup effect defaults */ 7300 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; 7301 for (idx = 0; idx < num_fx; idx++) { 7302 for (i = 0; i <= ca0132_effects[idx].params; i++) { 7303 dspio_set_uint_param(codec, 7304 ca0132_effects[idx].mid, 7305 ca0132_effects[idx].reqs[i], 7306 ca0132_effects[idx].def_vals[i]); 7307 } 7308 } 7309 } 7310 7311 /* 7312 * Setup default parameters for the Sound Blaster Z DSP. A lot more going on 7313 * than the Chromebook setup. 7314 */ 7315 static void sbz_setup_defaults(struct hda_codec *codec) 7316 { 7317 struct ca0132_spec *spec = codec->spec; 7318 unsigned int tmp; 7319 int num_fx; 7320 int idx, i; 7321 7322 if (spec->dsp_state != DSP_DOWNLOADED) 7323 return; 7324 7325 ca0132_alt_dsp_scp_startup(codec); 7326 ca0132_alt_init_analog_mics(codec); 7327 sbz_connect_streams(codec); 7328 sbz_chipio_startup_data(codec); 7329 7330 chipio_set_stream_control(codec, 0x03, 1); 7331 chipio_set_stream_control(codec, 0x04, 1); 7332 7333 /* 7334 * Sets internal input loopback to off, used to have a switch to 7335 * enable input loopback, but turned out to be way too buggy. 7336 */ 7337 tmp = FLOAT_ONE; 7338 dspio_set_uint_param(codec, 0x37, 0x08, tmp); 7339 dspio_set_uint_param(codec, 0x37, 0x10, tmp); 7340 7341 /*remove DSP headroom*/ 7342 tmp = FLOAT_ZERO; 7343 dspio_set_uint_param(codec, 0x96, 0x3C, tmp); 7344 7345 /* set WUH source */ 7346 tmp = FLOAT_TWO; 7347 dspio_set_uint_param(codec, 0x31, 0x00, tmp); 7348 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 7349 7350 /* Set speaker source? */ 7351 dspio_set_uint_param(codec, 0x32, 0x00, tmp); 7352 7353 ca0132_alt_dsp_initial_mic_setup(codec); 7354 7355 /* out, in effects + voicefx */ 7356 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; 7357 for (idx = 0; idx < num_fx; idx++) { 7358 for (i = 0; i <= ca0132_effects[idx].params; i++) { 7359 dspio_set_uint_param(codec, 7360 ca0132_effects[idx].mid, 7361 ca0132_effects[idx].reqs[i], 7362 ca0132_effects[idx].def_vals[i]); 7363 } 7364 } 7365 7366 ca0132_alt_create_dummy_stream(codec); 7367 } 7368 7369 /* 7370 * Setup default parameters for the Sound BlasterX AE-5 DSP. 7371 */ 7372 static void ae5_setup_defaults(struct hda_codec *codec) 7373 { 7374 struct ca0132_spec *spec = codec->spec; 7375 unsigned int tmp; 7376 int num_fx; 7377 int idx, i; 7378 7379 if (spec->dsp_state != DSP_DOWNLOADED) 7380 return; 7381 7382 ca0132_alt_dsp_scp_startup(codec); 7383 ca0132_alt_init_analog_mics(codec); 7384 chipio_set_stream_control(codec, 0x03, 1); 7385 chipio_set_stream_control(codec, 0x04, 1); 7386 7387 /* New, unknown SCP req's */ 7388 tmp = FLOAT_ZERO; 7389 dspio_set_uint_param(codec, 0x96, 0x29, tmp); 7390 dspio_set_uint_param(codec, 0x96, 0x2a, tmp); 7391 dspio_set_uint_param(codec, 0x80, 0x0d, tmp); 7392 dspio_set_uint_param(codec, 0x80, 0x0e, tmp); 7393 7394 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f); 7395 ca0113_mmio_gpio_set(codec, 0, false); 7396 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00); 7397 7398 /* Internal loopback off */ 7399 tmp = FLOAT_ONE; 7400 dspio_set_uint_param(codec, 0x37, 0x08, tmp); 7401 dspio_set_uint_param(codec, 0x37, 0x10, tmp); 7402 7403 /*remove DSP headroom*/ 7404 tmp = FLOAT_ZERO; 7405 dspio_set_uint_param(codec, 0x96, 0x3C, tmp); 7406 7407 /* set WUH source */ 7408 tmp = FLOAT_TWO; 7409 dspio_set_uint_param(codec, 0x31, 0x00, tmp); 7410 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 7411 7412 /* Set speaker source? */ 7413 dspio_set_uint_param(codec, 0x32, 0x00, tmp); 7414 7415 ca0132_alt_dsp_initial_mic_setup(codec); 7416 ae5_post_dsp_register_set(codec); 7417 ae5_post_dsp_param_setup(codec); 7418 ae5_post_dsp_pll_setup(codec); 7419 ae5_post_dsp_stream_setup(codec); 7420 ae5_post_dsp_startup_data(codec); 7421 7422 /* out, in effects + voicefx */ 7423 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; 7424 for (idx = 0; idx < num_fx; idx++) { 7425 for (i = 0; i <= ca0132_effects[idx].params; i++) { 7426 dspio_set_uint_param(codec, 7427 ca0132_effects[idx].mid, 7428 ca0132_effects[idx].reqs[i], 7429 ca0132_effects[idx].def_vals[i]); 7430 } 7431 } 7432 7433 ca0132_alt_create_dummy_stream(codec); 7434 } 7435 7436 /* 7437 * Initialization of flags in chip 7438 */ 7439 static void ca0132_init_flags(struct hda_codec *codec) 7440 { 7441 struct ca0132_spec *spec = codec->spec; 7442 7443 if (ca0132_use_alt_functions(spec)) { 7444 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, 1); 7445 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, 1); 7446 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, 1); 7447 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, 1); 7448 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, 1); 7449 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0); 7450 chipio_set_control_flag(codec, CONTROL_FLAG_SPDIF2OUT, 0); 7451 chipio_set_control_flag(codec, 7452 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0); 7453 chipio_set_control_flag(codec, 7454 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 1); 7455 } else { 7456 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0); 7457 chipio_set_control_flag(codec, 7458 CONTROL_FLAG_PORT_A_COMMON_MODE, 0); 7459 chipio_set_control_flag(codec, 7460 CONTROL_FLAG_PORT_D_COMMON_MODE, 0); 7461 chipio_set_control_flag(codec, 7462 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 0); 7463 chipio_set_control_flag(codec, 7464 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0); 7465 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_HIGH_PASS, 1); 7466 } 7467 } 7468 7469 /* 7470 * Initialization of parameters in chip 7471 */ 7472 static void ca0132_init_params(struct hda_codec *codec) 7473 { 7474 struct ca0132_spec *spec = codec->spec; 7475 7476 if (ca0132_use_alt_functions(spec)) { 7477 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 7478 chipio_set_conn_rate(codec, 0x0B, SR_48_000); 7479 chipio_set_control_param(codec, CONTROL_PARAM_SPDIF1_SOURCE, 0); 7480 chipio_set_control_param(codec, 0, 0); 7481 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0); 7482 } 7483 7484 chipio_set_control_param(codec, CONTROL_PARAM_PORTA_160OHM_GAIN, 6); 7485 chipio_set_control_param(codec, CONTROL_PARAM_PORTD_160OHM_GAIN, 6); 7486 } 7487 7488 static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k) 7489 { 7490 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k); 7491 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k); 7492 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k); 7493 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k); 7494 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k); 7495 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k); 7496 7497 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 7498 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 7499 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 7500 } 7501 7502 static bool ca0132_download_dsp_images(struct hda_codec *codec) 7503 { 7504 bool dsp_loaded = false; 7505 struct ca0132_spec *spec = codec->spec; 7506 const struct dsp_image_seg *dsp_os_image; 7507 const struct firmware *fw_entry = NULL; 7508 /* 7509 * Alternate firmwares for different variants. The Recon3Di apparently 7510 * can use the default firmware, but I'll leave the option in case 7511 * it needs it again. 7512 */ 7513 switch (ca0132_quirk(spec)) { 7514 case QUIRK_SBZ: 7515 case QUIRK_R3D: 7516 case QUIRK_AE5: 7517 if (request_firmware(&fw_entry, DESKTOP_EFX_FILE, 7518 codec->card->dev) != 0) 7519 codec_dbg(codec, "Desktop firmware not found."); 7520 else 7521 codec_dbg(codec, "Desktop firmware selected."); 7522 break; 7523 case QUIRK_R3DI: 7524 if (request_firmware(&fw_entry, R3DI_EFX_FILE, 7525 codec->card->dev) != 0) 7526 codec_dbg(codec, "Recon3Di alt firmware not detected."); 7527 else 7528 codec_dbg(codec, "Recon3Di firmware selected."); 7529 break; 7530 default: 7531 break; 7532 } 7533 /* 7534 * Use default ctefx.bin if no alt firmware is detected, or if none 7535 * exists for your particular codec. 7536 */ 7537 if (!fw_entry) { 7538 codec_dbg(codec, "Default firmware selected."); 7539 if (request_firmware(&fw_entry, EFX_FILE, 7540 codec->card->dev) != 0) 7541 return false; 7542 } 7543 7544 dsp_os_image = (struct dsp_image_seg *)(fw_entry->data); 7545 if (dspload_image(codec, dsp_os_image, 0, 0, true, 0)) { 7546 codec_err(codec, "ca0132 DSP load image failed\n"); 7547 goto exit_download; 7548 } 7549 7550 dsp_loaded = dspload_wait_loaded(codec); 7551 7552 exit_download: 7553 release_firmware(fw_entry); 7554 7555 return dsp_loaded; 7556 } 7557 7558 static void ca0132_download_dsp(struct hda_codec *codec) 7559 { 7560 struct ca0132_spec *spec = codec->spec; 7561 7562 #ifndef CONFIG_SND_HDA_CODEC_CA0132_DSP 7563 return; /* NOP */ 7564 #endif 7565 7566 if (spec->dsp_state == DSP_DOWNLOAD_FAILED) 7567 return; /* don't retry failures */ 7568 7569 chipio_enable_clocks(codec); 7570 if (spec->dsp_state != DSP_DOWNLOADED) { 7571 spec->dsp_state = DSP_DOWNLOADING; 7572 7573 if (!ca0132_download_dsp_images(codec)) 7574 spec->dsp_state = DSP_DOWNLOAD_FAILED; 7575 else 7576 spec->dsp_state = DSP_DOWNLOADED; 7577 } 7578 7579 /* For codecs using alt functions, this is already done earlier */ 7580 if (spec->dsp_state == DSP_DOWNLOADED && !ca0132_use_alt_functions(spec)) 7581 ca0132_set_dsp_msr(codec, true); 7582 } 7583 7584 static void ca0132_process_dsp_response(struct hda_codec *codec, 7585 struct hda_jack_callback *callback) 7586 { 7587 struct ca0132_spec *spec = codec->spec; 7588 7589 codec_dbg(codec, "ca0132_process_dsp_response\n"); 7590 if (spec->wait_scp) { 7591 if (dspio_get_response_data(codec) >= 0) 7592 spec->wait_scp = 0; 7593 } 7594 7595 dspio_clear_response_queue(codec); 7596 } 7597 7598 static void hp_callback(struct hda_codec *codec, struct hda_jack_callback *cb) 7599 { 7600 struct ca0132_spec *spec = codec->spec; 7601 struct hda_jack_tbl *tbl; 7602 7603 /* Delay enabling the HP amp, to let the mic-detection 7604 * state machine run. 7605 */ 7606 cancel_delayed_work_sync(&spec->unsol_hp_work); 7607 schedule_delayed_work(&spec->unsol_hp_work, msecs_to_jiffies(500)); 7608 tbl = snd_hda_jack_tbl_get(codec, cb->nid); 7609 if (tbl) 7610 tbl->block_report = 1; 7611 } 7612 7613 static void amic_callback(struct hda_codec *codec, struct hda_jack_callback *cb) 7614 { 7615 struct ca0132_spec *spec = codec->spec; 7616 7617 if (ca0132_use_alt_functions(spec)) 7618 ca0132_alt_select_in(codec); 7619 else 7620 ca0132_select_mic(codec); 7621 } 7622 7623 static void ca0132_init_unsol(struct hda_codec *codec) 7624 { 7625 struct ca0132_spec *spec = codec->spec; 7626 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_hp, hp_callback); 7627 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_amic1, 7628 amic_callback); 7629 snd_hda_jack_detect_enable_callback(codec, UNSOL_TAG_DSP, 7630 ca0132_process_dsp_response); 7631 /* Front headphone jack detection */ 7632 if (ca0132_use_alt_functions(spec)) 7633 snd_hda_jack_detect_enable_callback(codec, 7634 spec->unsol_tag_front_hp, hp_callback); 7635 } 7636 7637 /* 7638 * Verbs tables. 7639 */ 7640 7641 /* Sends before DSP download. */ 7642 static struct hda_verb ca0132_base_init_verbs[] = { 7643 /*enable ct extension*/ 7644 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1}, 7645 {} 7646 }; 7647 7648 /* Send at exit. */ 7649 static struct hda_verb ca0132_base_exit_verbs[] = { 7650 /*set afg to D3*/ 7651 {0x01, AC_VERB_SET_POWER_STATE, 0x03}, 7652 /*disable ct extension*/ 7653 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0}, 7654 {} 7655 }; 7656 7657 /* Other verbs tables. Sends after DSP download. */ 7658 7659 static struct hda_verb ca0132_init_verbs0[] = { 7660 /* chip init verbs */ 7661 {0x15, 0x70D, 0xF0}, 7662 {0x15, 0x70E, 0xFE}, 7663 {0x15, 0x707, 0x75}, 7664 {0x15, 0x707, 0xD3}, 7665 {0x15, 0x707, 0x09}, 7666 {0x15, 0x707, 0x53}, 7667 {0x15, 0x707, 0xD4}, 7668 {0x15, 0x707, 0xEF}, 7669 {0x15, 0x707, 0x75}, 7670 {0x15, 0x707, 0xD3}, 7671 {0x15, 0x707, 0x09}, 7672 {0x15, 0x707, 0x02}, 7673 {0x15, 0x707, 0x37}, 7674 {0x15, 0x707, 0x78}, 7675 {0x15, 0x53C, 0xCE}, 7676 {0x15, 0x575, 0xC9}, 7677 {0x15, 0x53D, 0xCE}, 7678 {0x15, 0x5B7, 0xC9}, 7679 {0x15, 0x70D, 0xE8}, 7680 {0x15, 0x70E, 0xFE}, 7681 {0x15, 0x707, 0x02}, 7682 {0x15, 0x707, 0x68}, 7683 {0x15, 0x707, 0x62}, 7684 {0x15, 0x53A, 0xCE}, 7685 {0x15, 0x546, 0xC9}, 7686 {0x15, 0x53B, 0xCE}, 7687 {0x15, 0x5E8, 0xC9}, 7688 {} 7689 }; 7690 7691 /* Extra init verbs for desktop cards. */ 7692 static struct hda_verb ca0132_init_verbs1[] = { 7693 {0x15, 0x70D, 0x20}, 7694 {0x15, 0x70E, 0x19}, 7695 {0x15, 0x707, 0x00}, 7696 {0x15, 0x539, 0xCE}, 7697 {0x15, 0x546, 0xC9}, 7698 {0x15, 0x70D, 0xB7}, 7699 {0x15, 0x70E, 0x09}, 7700 {0x15, 0x707, 0x10}, 7701 {0x15, 0x70D, 0xAF}, 7702 {0x15, 0x70E, 0x09}, 7703 {0x15, 0x707, 0x01}, 7704 {0x15, 0x707, 0x05}, 7705 {0x15, 0x70D, 0x73}, 7706 {0x15, 0x70E, 0x09}, 7707 {0x15, 0x707, 0x14}, 7708 {0x15, 0x6FF, 0xC4}, 7709 {} 7710 }; 7711 7712 static void ca0132_init_chip(struct hda_codec *codec) 7713 { 7714 struct ca0132_spec *spec = codec->spec; 7715 int num_fx; 7716 int i; 7717 unsigned int on; 7718 7719 mutex_init(&spec->chipio_mutex); 7720 7721 spec->cur_out_type = SPEAKER_OUT; 7722 if (!ca0132_use_alt_functions(spec)) 7723 spec->cur_mic_type = DIGITAL_MIC; 7724 else 7725 spec->cur_mic_type = REAR_MIC; 7726 7727 spec->cur_mic_boost = 0; 7728 7729 for (i = 0; i < VNODES_COUNT; i++) { 7730 spec->vnode_lvol[i] = 0x5a; 7731 spec->vnode_rvol[i] = 0x5a; 7732 spec->vnode_lswitch[i] = 0; 7733 spec->vnode_rswitch[i] = 0; 7734 } 7735 7736 /* 7737 * Default states for effects are in ca0132_effects[]. 7738 */ 7739 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT; 7740 for (i = 0; i < num_fx; i++) { 7741 on = (unsigned int)ca0132_effects[i].reqs[0]; 7742 spec->effects_switch[i] = on ? 1 : 0; 7743 } 7744 /* 7745 * Sets defaults for the effect slider controls, only for alternative 7746 * ca0132 codecs. Also sets x-bass crossover frequency to 80hz. 7747 */ 7748 if (ca0132_use_alt_controls(spec)) { 7749 spec->xbass_xover_freq = 8; 7750 for (i = 0; i < EFFECT_LEVEL_SLIDERS; i++) 7751 spec->fx_ctl_val[i] = effect_slider_defaults[i]; 7752 } 7753 7754 spec->voicefx_val = 0; 7755 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID] = 1; 7756 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0; 7757 7758 /* 7759 * The ZxR doesn't have a front panel header, and it's line-in is on 7760 * the daughter board. So, there is no input enum control, and we need 7761 * to make sure that spec->in_enum_val is set properly. 7762 */ 7763 if (ca0132_quirk(spec) == QUIRK_ZXR) 7764 spec->in_enum_val = REAR_MIC; 7765 7766 #ifdef ENABLE_TUNING_CONTROLS 7767 ca0132_init_tuning_defaults(codec); 7768 #endif 7769 } 7770 7771 /* 7772 * Recon3Di exit specific commands. 7773 */ 7774 /* prevents popping noise on shutdown */ 7775 static void r3di_gpio_shutdown(struct hda_codec *codec) 7776 { 7777 snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DATA, 0x00); 7778 } 7779 7780 /* 7781 * Sound Blaster Z exit specific commands. 7782 */ 7783 static void sbz_region2_exit(struct hda_codec *codec) 7784 { 7785 struct ca0132_spec *spec = codec->spec; 7786 unsigned int i; 7787 7788 for (i = 0; i < 4; i++) 7789 writeb(0x0, spec->mem_base + 0x100); 7790 for (i = 0; i < 8; i++) 7791 writeb(0xb3, spec->mem_base + 0x304); 7792 7793 ca0113_mmio_gpio_set(codec, 0, false); 7794 ca0113_mmio_gpio_set(codec, 1, false); 7795 ca0113_mmio_gpio_set(codec, 4, true); 7796 ca0113_mmio_gpio_set(codec, 5, false); 7797 ca0113_mmio_gpio_set(codec, 7, false); 7798 } 7799 7800 static void sbz_set_pin_ctl_default(struct hda_codec *codec) 7801 { 7802 hda_nid_t pins[5] = {0x0B, 0x0C, 0x0E, 0x12, 0x13}; 7803 unsigned int i; 7804 7805 snd_hda_codec_write(codec, 0x11, 0, 7806 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x40); 7807 7808 for (i = 0; i < 5; i++) 7809 snd_hda_codec_write(codec, pins[i], 0, 7810 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x00); 7811 } 7812 7813 static void ca0132_clear_unsolicited(struct hda_codec *codec) 7814 { 7815 hda_nid_t pins[7] = {0x0B, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13}; 7816 unsigned int i; 7817 7818 for (i = 0; i < 7; i++) { 7819 snd_hda_codec_write(codec, pins[i], 0, 7820 AC_VERB_SET_UNSOLICITED_ENABLE, 0x00); 7821 } 7822 } 7823 7824 /* On shutdown, sends commands in sets of three */ 7825 static void sbz_gpio_shutdown_commands(struct hda_codec *codec, int dir, 7826 int mask, int data) 7827 { 7828 if (dir >= 0) 7829 snd_hda_codec_write(codec, 0x01, 0, 7830 AC_VERB_SET_GPIO_DIRECTION, dir); 7831 if (mask >= 0) 7832 snd_hda_codec_write(codec, 0x01, 0, 7833 AC_VERB_SET_GPIO_MASK, mask); 7834 7835 if (data >= 0) 7836 snd_hda_codec_write(codec, 0x01, 0, 7837 AC_VERB_SET_GPIO_DATA, data); 7838 } 7839 7840 static void zxr_dbpro_power_state_shutdown(struct hda_codec *codec) 7841 { 7842 hda_nid_t pins[7] = {0x05, 0x0c, 0x09, 0x0e, 0x08, 0x11, 0x01}; 7843 unsigned int i; 7844 7845 for (i = 0; i < 7; i++) 7846 snd_hda_codec_write(codec, pins[i], 0, 7847 AC_VERB_SET_POWER_STATE, 0x03); 7848 } 7849 7850 static void sbz_exit_chip(struct hda_codec *codec) 7851 { 7852 chipio_set_stream_control(codec, 0x03, 0); 7853 chipio_set_stream_control(codec, 0x04, 0); 7854 7855 /* Mess with GPIO */ 7856 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, -1); 7857 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x05); 7858 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x01); 7859 7860 chipio_set_stream_control(codec, 0x14, 0); 7861 chipio_set_stream_control(codec, 0x0C, 0); 7862 7863 chipio_set_conn_rate(codec, 0x41, SR_192_000); 7864 chipio_set_conn_rate(codec, 0x91, SR_192_000); 7865 7866 chipio_write(codec, 0x18a020, 0x00000083); 7867 7868 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x03); 7869 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x07); 7870 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x06); 7871 7872 chipio_set_stream_control(codec, 0x0C, 0); 7873 7874 chipio_set_control_param(codec, 0x0D, 0x24); 7875 7876 ca0132_clear_unsolicited(codec); 7877 sbz_set_pin_ctl_default(codec); 7878 7879 snd_hda_codec_write(codec, 0x0B, 0, 7880 AC_VERB_SET_EAPD_BTLENABLE, 0x00); 7881 7882 sbz_region2_exit(codec); 7883 } 7884 7885 static void r3d_exit_chip(struct hda_codec *codec) 7886 { 7887 ca0132_clear_unsolicited(codec); 7888 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 7889 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5b); 7890 } 7891 7892 static void ae5_exit_chip(struct hda_codec *codec) 7893 { 7894 chipio_set_stream_control(codec, 0x03, 0); 7895 chipio_set_stream_control(codec, 0x04, 0); 7896 7897 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f); 7898 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); 7899 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); 7900 ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00); 7901 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00); 7902 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x00); 7903 ca0113_mmio_gpio_set(codec, 0, false); 7904 ca0113_mmio_gpio_set(codec, 1, false); 7905 7906 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 7907 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53); 7908 7909 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0); 7910 7911 chipio_set_stream_control(codec, 0x18, 0); 7912 chipio_set_stream_control(codec, 0x0c, 0); 7913 7914 snd_hda_codec_write(codec, 0x01, 0, 0x724, 0x83); 7915 } 7916 7917 static void zxr_exit_chip(struct hda_codec *codec) 7918 { 7919 chipio_set_stream_control(codec, 0x03, 0); 7920 chipio_set_stream_control(codec, 0x04, 0); 7921 chipio_set_stream_control(codec, 0x14, 0); 7922 chipio_set_stream_control(codec, 0x0C, 0); 7923 7924 chipio_set_conn_rate(codec, 0x41, SR_192_000); 7925 chipio_set_conn_rate(codec, 0x91, SR_192_000); 7926 7927 chipio_write(codec, 0x18a020, 0x00000083); 7928 7929 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 7930 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53); 7931 7932 ca0132_clear_unsolicited(codec); 7933 sbz_set_pin_ctl_default(codec); 7934 snd_hda_codec_write(codec, 0x0B, 0, AC_VERB_SET_EAPD_BTLENABLE, 0x00); 7935 7936 ca0113_mmio_gpio_set(codec, 5, false); 7937 ca0113_mmio_gpio_set(codec, 2, false); 7938 ca0113_mmio_gpio_set(codec, 3, false); 7939 ca0113_mmio_gpio_set(codec, 0, false); 7940 ca0113_mmio_gpio_set(codec, 4, true); 7941 ca0113_mmio_gpio_set(codec, 0, true); 7942 ca0113_mmio_gpio_set(codec, 5, true); 7943 ca0113_mmio_gpio_set(codec, 2, false); 7944 ca0113_mmio_gpio_set(codec, 3, false); 7945 } 7946 7947 static void ca0132_exit_chip(struct hda_codec *codec) 7948 { 7949 /* put any chip cleanup stuffs here. */ 7950 7951 if (dspload_is_loaded(codec)) 7952 dsp_reset(codec); 7953 } 7954 7955 /* 7956 * This fixes a problem that was hard to reproduce. Very rarely, I would 7957 * boot up, and there would be no sound, but the DSP indicated it had loaded 7958 * properly. I did a few memory dumps to see if anything was different, and 7959 * there were a few areas of memory uninitialized with a1a2a3a4. This function 7960 * checks if those areas are uninitialized, and if they are, it'll attempt to 7961 * reload the card 3 times. Usually it fixes by the second. 7962 */ 7963 static void sbz_dsp_startup_check(struct hda_codec *codec) 7964 { 7965 struct ca0132_spec *spec = codec->spec; 7966 unsigned int dsp_data_check[4]; 7967 unsigned int cur_address = 0x390; 7968 unsigned int i; 7969 unsigned int failure = 0; 7970 unsigned int reload = 3; 7971 7972 if (spec->startup_check_entered) 7973 return; 7974 7975 spec->startup_check_entered = true; 7976 7977 for (i = 0; i < 4; i++) { 7978 chipio_read(codec, cur_address, &dsp_data_check[i]); 7979 cur_address += 0x4; 7980 } 7981 for (i = 0; i < 4; i++) { 7982 if (dsp_data_check[i] == 0xa1a2a3a4) 7983 failure = 1; 7984 } 7985 7986 codec_dbg(codec, "Startup Check: %d ", failure); 7987 if (failure) 7988 codec_info(codec, "DSP not initialized properly. Attempting to fix."); 7989 /* 7990 * While the failure condition is true, and we haven't reached our 7991 * three reload limit, continue trying to reload the driver and 7992 * fix the issue. 7993 */ 7994 while (failure && (reload != 0)) { 7995 codec_info(codec, "Reloading... Tries left: %d", reload); 7996 sbz_exit_chip(codec); 7997 spec->dsp_state = DSP_DOWNLOAD_INIT; 7998 codec->patch_ops.init(codec); 7999 failure = 0; 8000 for (i = 0; i < 4; i++) { 8001 chipio_read(codec, cur_address, &dsp_data_check[i]); 8002 cur_address += 0x4; 8003 } 8004 for (i = 0; i < 4; i++) { 8005 if (dsp_data_check[i] == 0xa1a2a3a4) 8006 failure = 1; 8007 } 8008 reload--; 8009 } 8010 8011 if (!failure && reload < 3) 8012 codec_info(codec, "DSP fixed."); 8013 8014 if (!failure) 8015 return; 8016 8017 codec_info(codec, "DSP failed to initialize properly. Either try a full shutdown or a suspend to clear the internal memory."); 8018 } 8019 8020 /* 8021 * This is for the extra volume verbs 0x797 (left) and 0x798 (right). These add 8022 * extra precision for decibel values. If you had the dB value in floating point 8023 * you would take the value after the decimal point, multiply by 64, and divide 8024 * by 2. So for 8.59, it's (59 * 64) / 100. Useful if someone wanted to 8025 * implement fixed point or floating point dB volumes. For now, I'll set them 8026 * to 0 just incase a value has lingered from a boot into Windows. 8027 */ 8028 static void ca0132_alt_vol_setup(struct hda_codec *codec) 8029 { 8030 snd_hda_codec_write(codec, 0x02, 0, 0x797, 0x00); 8031 snd_hda_codec_write(codec, 0x02, 0, 0x798, 0x00); 8032 snd_hda_codec_write(codec, 0x03, 0, 0x797, 0x00); 8033 snd_hda_codec_write(codec, 0x03, 0, 0x798, 0x00); 8034 snd_hda_codec_write(codec, 0x04, 0, 0x797, 0x00); 8035 snd_hda_codec_write(codec, 0x04, 0, 0x798, 0x00); 8036 snd_hda_codec_write(codec, 0x07, 0, 0x797, 0x00); 8037 snd_hda_codec_write(codec, 0x07, 0, 0x798, 0x00); 8038 } 8039 8040 /* 8041 * Extra commands that don't really fit anywhere else. 8042 */ 8043 static void sbz_pre_dsp_setup(struct hda_codec *codec) 8044 { 8045 struct ca0132_spec *spec = codec->spec; 8046 8047 writel(0x00820680, spec->mem_base + 0x01C); 8048 writel(0x00820680, spec->mem_base + 0x01C); 8049 8050 chipio_write(codec, 0x18b0a4, 0x000000c2); 8051 8052 snd_hda_codec_write(codec, 0x11, 0, 8053 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44); 8054 } 8055 8056 static void r3d_pre_dsp_setup(struct hda_codec *codec) 8057 { 8058 chipio_write(codec, 0x18b0a4, 0x000000c2); 8059 8060 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8061 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x1E); 8062 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8063 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x1C); 8064 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8065 VENDOR_CHIPIO_8051_DATA_WRITE, 0x5B); 8066 8067 snd_hda_codec_write(codec, 0x11, 0, 8068 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44); 8069 } 8070 8071 static void r3di_pre_dsp_setup(struct hda_codec *codec) 8072 { 8073 chipio_write(codec, 0x18b0a4, 0x000000c2); 8074 8075 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8076 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x1E); 8077 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8078 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x1C); 8079 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8080 VENDOR_CHIPIO_8051_DATA_WRITE, 0x5B); 8081 8082 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8083 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20); 8084 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8085 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19); 8086 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8087 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00); 8088 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8089 VENDOR_CHIPIO_8051_DATA_WRITE, 0x40); 8090 8091 snd_hda_codec_write(codec, 0x11, 0, 8092 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x04); 8093 } 8094 8095 /* 8096 * These are sent before the DSP is downloaded. Not sure 8097 * what they do, or if they're necessary. Could possibly 8098 * be removed. Figure they're better to leave in. 8099 */ 8100 static void ca0132_mmio_init(struct hda_codec *codec) 8101 { 8102 struct ca0132_spec *spec = codec->spec; 8103 8104 if (ca0132_quirk(spec) == QUIRK_AE5) 8105 writel(0x00000001, spec->mem_base + 0x400); 8106 else 8107 writel(0x00000000, spec->mem_base + 0x400); 8108 8109 if (ca0132_quirk(spec) == QUIRK_AE5) 8110 writel(0x00000001, spec->mem_base + 0x408); 8111 else 8112 writel(0x00000000, spec->mem_base + 0x408); 8113 8114 if (ca0132_quirk(spec) == QUIRK_AE5) 8115 writel(0x00000001, spec->mem_base + 0x40c); 8116 else 8117 writel(0x00000000, spec->mem_base + 0x40C); 8118 8119 if (ca0132_quirk(spec) == QUIRK_ZXR) 8120 writel(0x00880640, spec->mem_base + 0x01C); 8121 else 8122 writel(0x00880680, spec->mem_base + 0x01C); 8123 8124 if (ca0132_quirk(spec) == QUIRK_AE5) 8125 writel(0x00000080, spec->mem_base + 0xC0C); 8126 else 8127 writel(0x00000083, spec->mem_base + 0xC0C); 8128 8129 writel(0x00000030, spec->mem_base + 0xC00); 8130 writel(0x00000000, spec->mem_base + 0xC04); 8131 8132 if (ca0132_quirk(spec) == QUIRK_AE5) 8133 writel(0x00000000, spec->mem_base + 0xC0C); 8134 else 8135 writel(0x00000003, spec->mem_base + 0xC0C); 8136 8137 writel(0x00000003, spec->mem_base + 0xC0C); 8138 writel(0x00000003, spec->mem_base + 0xC0C); 8139 writel(0x00000003, spec->mem_base + 0xC0C); 8140 8141 if (ca0132_quirk(spec) == QUIRK_AE5) 8142 writel(0x00000001, spec->mem_base + 0xC08); 8143 else 8144 writel(0x000000C1, spec->mem_base + 0xC08); 8145 8146 writel(0x000000F1, spec->mem_base + 0xC08); 8147 writel(0x00000001, spec->mem_base + 0xC08); 8148 writel(0x000000C7, spec->mem_base + 0xC08); 8149 writel(0x000000C1, spec->mem_base + 0xC08); 8150 writel(0x00000080, spec->mem_base + 0xC04); 8151 8152 if (ca0132_quirk(spec) == QUIRK_AE5) { 8153 writel(0x00000000, spec->mem_base + 0x42c); 8154 writel(0x00000000, spec->mem_base + 0x46c); 8155 writel(0x00000000, spec->mem_base + 0x4ac); 8156 writel(0x00000000, spec->mem_base + 0x4ec); 8157 writel(0x00000000, spec->mem_base + 0x43c); 8158 writel(0x00000000, spec->mem_base + 0x47c); 8159 writel(0x00000000, spec->mem_base + 0x4bc); 8160 writel(0x00000000, spec->mem_base + 0x4fc); 8161 writel(0x00000600, spec->mem_base + 0x100); 8162 writel(0x00000014, spec->mem_base + 0x410); 8163 writel(0x0000060f, spec->mem_base + 0x100); 8164 writel(0x0000070f, spec->mem_base + 0x100); 8165 writel(0x00000aff, spec->mem_base + 0x830); 8166 writel(0x00000000, spec->mem_base + 0x86c); 8167 writel(0x0000006b, spec->mem_base + 0x800); 8168 writel(0x00000001, spec->mem_base + 0x86c); 8169 writel(0x0000006b, spec->mem_base + 0x800); 8170 writel(0x00000057, spec->mem_base + 0x804); 8171 writel(0x00800000, spec->mem_base + 0x20c); 8172 } 8173 } 8174 8175 /* 8176 * This function writes to some SFR's, does some region2 writes, and then 8177 * eventually resets the codec with the 0x7ff verb. Not quite sure why it does 8178 * what it does. 8179 */ 8180 static void ae5_register_set(struct hda_codec *codec) 8181 { 8182 struct ca0132_spec *spec = codec->spec; 8183 8184 chipio_8051_write_direct(codec, 0x93, 0x10); 8185 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8186 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x44); 8187 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8188 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc2); 8189 8190 writeb(0x0f, spec->mem_base + 0x304); 8191 writeb(0x0f, spec->mem_base + 0x304); 8192 writeb(0x0f, spec->mem_base + 0x304); 8193 writeb(0x0f, spec->mem_base + 0x304); 8194 writeb(0x0e, spec->mem_base + 0x100); 8195 writeb(0x1f, spec->mem_base + 0x304); 8196 writeb(0x0c, spec->mem_base + 0x100); 8197 writeb(0x3f, spec->mem_base + 0x304); 8198 writeb(0x08, spec->mem_base + 0x100); 8199 writeb(0x7f, spec->mem_base + 0x304); 8200 writeb(0x00, spec->mem_base + 0x100); 8201 writeb(0xff, spec->mem_base + 0x304); 8202 8203 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f); 8204 8205 chipio_8051_write_direct(codec, 0x90, 0x00); 8206 chipio_8051_write_direct(codec, 0x90, 0x10); 8207 8208 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); 8209 8210 chipio_write(codec, 0x18b0a4, 0x000000c2); 8211 8212 snd_hda_codec_write(codec, 0x01, 0, 0x7ff, 0x00); 8213 snd_hda_codec_write(codec, 0x01, 0, 0x7ff, 0x00); 8214 } 8215 8216 /* 8217 * Extra init functions for alternative ca0132 codecs. Done 8218 * here so they don't clutter up the main ca0132_init function 8219 * anymore than they have to. 8220 */ 8221 static void ca0132_alt_init(struct hda_codec *codec) 8222 { 8223 struct ca0132_spec *spec = codec->spec; 8224 8225 ca0132_alt_vol_setup(codec); 8226 8227 switch (ca0132_quirk(spec)) { 8228 case QUIRK_SBZ: 8229 codec_dbg(codec, "SBZ alt_init"); 8230 ca0132_gpio_init(codec); 8231 sbz_pre_dsp_setup(codec); 8232 snd_hda_sequence_write(codec, spec->chip_init_verbs); 8233 snd_hda_sequence_write(codec, spec->desktop_init_verbs); 8234 break; 8235 case QUIRK_R3DI: 8236 codec_dbg(codec, "R3DI alt_init"); 8237 ca0132_gpio_init(codec); 8238 ca0132_gpio_setup(codec); 8239 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADING); 8240 r3di_pre_dsp_setup(codec); 8241 snd_hda_sequence_write(codec, spec->chip_init_verbs); 8242 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x6FF, 0xC4); 8243 break; 8244 case QUIRK_R3D: 8245 r3d_pre_dsp_setup(codec); 8246 snd_hda_sequence_write(codec, spec->chip_init_verbs); 8247 snd_hda_sequence_write(codec, spec->desktop_init_verbs); 8248 break; 8249 case QUIRK_AE5: 8250 ca0132_gpio_init(codec); 8251 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8252 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x49); 8253 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8254 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x88); 8255 chipio_write(codec, 0x18b030, 0x00000020); 8256 snd_hda_sequence_write(codec, spec->chip_init_verbs); 8257 snd_hda_sequence_write(codec, spec->desktop_init_verbs); 8258 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f); 8259 break; 8260 case QUIRK_ZXR: 8261 snd_hda_sequence_write(codec, spec->chip_init_verbs); 8262 snd_hda_sequence_write(codec, spec->desktop_init_verbs); 8263 break; 8264 default: 8265 break; 8266 } 8267 } 8268 8269 static int ca0132_init(struct hda_codec *codec) 8270 { 8271 struct ca0132_spec *spec = codec->spec; 8272 struct auto_pin_cfg *cfg = &spec->autocfg; 8273 int i; 8274 bool dsp_loaded; 8275 8276 /* 8277 * If the DSP is already downloaded, and init has been entered again, 8278 * there's only two reasons for it. One, the codec has awaken from a 8279 * suspended state, and in that case dspload_is_loaded will return 8280 * false, and the init will be ran again. The other reason it gets 8281 * re entered is on startup for some reason it triggers a suspend and 8282 * resume state. In this case, it will check if the DSP is downloaded, 8283 * and not run the init function again. For codecs using alt_functions, 8284 * it will check if the DSP is loaded properly. 8285 */ 8286 if (spec->dsp_state == DSP_DOWNLOADED) { 8287 dsp_loaded = dspload_is_loaded(codec); 8288 if (!dsp_loaded) { 8289 spec->dsp_reload = true; 8290 spec->dsp_state = DSP_DOWNLOAD_INIT; 8291 } else { 8292 if (ca0132_quirk(spec) == QUIRK_SBZ) 8293 sbz_dsp_startup_check(codec); 8294 return 0; 8295 } 8296 } 8297 8298 if (spec->dsp_state != DSP_DOWNLOAD_FAILED) 8299 spec->dsp_state = DSP_DOWNLOAD_INIT; 8300 spec->curr_chip_addx = INVALID_CHIP_ADDRESS; 8301 8302 if (ca0132_use_pci_mmio(spec)) 8303 ca0132_mmio_init(codec); 8304 8305 snd_hda_power_up_pm(codec); 8306 8307 if (ca0132_quirk(spec) == QUIRK_AE5) 8308 ae5_register_set(codec); 8309 8310 ca0132_init_unsol(codec); 8311 ca0132_init_params(codec); 8312 ca0132_init_flags(codec); 8313 8314 snd_hda_sequence_write(codec, spec->base_init_verbs); 8315 8316 if (ca0132_use_alt_functions(spec)) 8317 ca0132_alt_init(codec); 8318 8319 ca0132_download_dsp(codec); 8320 8321 ca0132_refresh_widget_caps(codec); 8322 8323 switch (ca0132_quirk(spec)) { 8324 case QUIRK_R3DI: 8325 case QUIRK_R3D: 8326 r3d_setup_defaults(codec); 8327 break; 8328 case QUIRK_SBZ: 8329 case QUIRK_ZXR: 8330 sbz_setup_defaults(codec); 8331 break; 8332 case QUIRK_AE5: 8333 ae5_setup_defaults(codec); 8334 break; 8335 default: 8336 ca0132_setup_defaults(codec); 8337 ca0132_init_analog_mic2(codec); 8338 ca0132_init_dmic(codec); 8339 break; 8340 } 8341 8342 for (i = 0; i < spec->num_outputs; i++) 8343 init_output(codec, spec->out_pins[i], spec->dacs[0]); 8344 8345 init_output(codec, cfg->dig_out_pins[0], spec->dig_out); 8346 8347 for (i = 0; i < spec->num_inputs; i++) 8348 init_input(codec, spec->input_pins[i], spec->adcs[i]); 8349 8350 init_input(codec, cfg->dig_in_pin, spec->dig_in); 8351 8352 if (!ca0132_use_alt_functions(spec)) { 8353 snd_hda_sequence_write(codec, spec->chip_init_verbs); 8354 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8355 VENDOR_CHIPIO_PARAM_EX_ID_SET, 0x0D); 8356 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8357 VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 0x20); 8358 } 8359 8360 if (ca0132_quirk(spec) == QUIRK_SBZ) 8361 ca0132_gpio_setup(codec); 8362 8363 snd_hda_sequence_write(codec, spec->spec_init_verbs); 8364 if (ca0132_use_alt_functions(spec)) { 8365 ca0132_alt_select_out(codec); 8366 ca0132_alt_select_in(codec); 8367 } else { 8368 ca0132_select_out(codec); 8369 ca0132_select_mic(codec); 8370 } 8371 8372 snd_hda_jack_report_sync(codec); 8373 8374 /* 8375 * Re set the PlayEnhancement switch on a resume event, because the 8376 * controls will not be reloaded. 8377 */ 8378 if (spec->dsp_reload) { 8379 spec->dsp_reload = false; 8380 ca0132_pe_switch_set(codec); 8381 } 8382 8383 snd_hda_power_down_pm(codec); 8384 8385 return 0; 8386 } 8387 8388 static int dbpro_init(struct hda_codec *codec) 8389 { 8390 struct ca0132_spec *spec = codec->spec; 8391 struct auto_pin_cfg *cfg = &spec->autocfg; 8392 unsigned int i; 8393 8394 init_output(codec, cfg->dig_out_pins[0], spec->dig_out); 8395 init_input(codec, cfg->dig_in_pin, spec->dig_in); 8396 8397 for (i = 0; i < spec->num_inputs; i++) 8398 init_input(codec, spec->input_pins[i], spec->adcs[i]); 8399 8400 return 0; 8401 } 8402 8403 static void ca0132_free(struct hda_codec *codec) 8404 { 8405 struct ca0132_spec *spec = codec->spec; 8406 8407 cancel_delayed_work_sync(&spec->unsol_hp_work); 8408 snd_hda_power_up(codec); 8409 switch (ca0132_quirk(spec)) { 8410 case QUIRK_SBZ: 8411 sbz_exit_chip(codec); 8412 break; 8413 case QUIRK_ZXR: 8414 zxr_exit_chip(codec); 8415 break; 8416 case QUIRK_R3D: 8417 r3d_exit_chip(codec); 8418 break; 8419 case QUIRK_AE5: 8420 ae5_exit_chip(codec); 8421 break; 8422 case QUIRK_R3DI: 8423 r3di_gpio_shutdown(codec); 8424 break; 8425 default: 8426 break; 8427 } 8428 8429 snd_hda_sequence_write(codec, spec->base_exit_verbs); 8430 ca0132_exit_chip(codec); 8431 8432 snd_hda_power_down(codec); 8433 #ifdef CONFIG_PCI 8434 if (spec->mem_base) 8435 pci_iounmap(codec->bus->pci, spec->mem_base); 8436 #endif 8437 kfree(spec->spec_init_verbs); 8438 kfree(codec->spec); 8439 } 8440 8441 static void dbpro_free(struct hda_codec *codec) 8442 { 8443 struct ca0132_spec *spec = codec->spec; 8444 8445 zxr_dbpro_power_state_shutdown(codec); 8446 8447 kfree(spec->spec_init_verbs); 8448 kfree(codec->spec); 8449 } 8450 8451 static void ca0132_reboot_notify(struct hda_codec *codec) 8452 { 8453 codec->patch_ops.free(codec); 8454 } 8455 8456 static const struct hda_codec_ops ca0132_patch_ops = { 8457 .build_controls = ca0132_build_controls, 8458 .build_pcms = ca0132_build_pcms, 8459 .init = ca0132_init, 8460 .free = ca0132_free, 8461 .unsol_event = snd_hda_jack_unsol_event, 8462 .reboot_notify = ca0132_reboot_notify, 8463 }; 8464 8465 static const struct hda_codec_ops dbpro_patch_ops = { 8466 .build_controls = dbpro_build_controls, 8467 .build_pcms = dbpro_build_pcms, 8468 .init = dbpro_init, 8469 .free = dbpro_free, 8470 }; 8471 8472 static void ca0132_config(struct hda_codec *codec) 8473 { 8474 struct ca0132_spec *spec = codec->spec; 8475 8476 spec->dacs[0] = 0x2; 8477 spec->dacs[1] = 0x3; 8478 spec->dacs[2] = 0x4; 8479 8480 spec->multiout.dac_nids = spec->dacs; 8481 spec->multiout.num_dacs = 3; 8482 8483 if (!ca0132_use_alt_functions(spec)) 8484 spec->multiout.max_channels = 2; 8485 else 8486 spec->multiout.max_channels = 6; 8487 8488 switch (ca0132_quirk(spec)) { 8489 case QUIRK_ALIENWARE: 8490 codec_dbg(codec, "%s: QUIRK_ALIENWARE applied.\n", __func__); 8491 snd_hda_apply_pincfgs(codec, alienware_pincfgs); 8492 break; 8493 case QUIRK_SBZ: 8494 codec_dbg(codec, "%s: QUIRK_SBZ applied.\n", __func__); 8495 snd_hda_apply_pincfgs(codec, sbz_pincfgs); 8496 break; 8497 case QUIRK_ZXR: 8498 codec_dbg(codec, "%s: QUIRK_ZXR applied.\n", __func__); 8499 snd_hda_apply_pincfgs(codec, zxr_pincfgs); 8500 break; 8501 case QUIRK_R3D: 8502 codec_dbg(codec, "%s: QUIRK_R3D applied.\n", __func__); 8503 snd_hda_apply_pincfgs(codec, r3d_pincfgs); 8504 break; 8505 case QUIRK_R3DI: 8506 codec_dbg(codec, "%s: QUIRK_R3DI applied.\n", __func__); 8507 snd_hda_apply_pincfgs(codec, r3di_pincfgs); 8508 break; 8509 case QUIRK_AE5: 8510 codec_dbg(codec, "%s: QUIRK_AE5 applied.\n", __func__); 8511 snd_hda_apply_pincfgs(codec, ae5_pincfgs); 8512 break; 8513 default: 8514 break; 8515 } 8516 8517 switch (ca0132_quirk(spec)) { 8518 case QUIRK_ALIENWARE: 8519 spec->num_outputs = 2; 8520 spec->out_pins[0] = 0x0b; /* speaker out */ 8521 spec->out_pins[1] = 0x0f; 8522 spec->shared_out_nid = 0x2; 8523 spec->unsol_tag_hp = 0x0f; 8524 8525 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */ 8526 spec->adcs[1] = 0x8; /* analog mic2 */ 8527 spec->adcs[2] = 0xa; /* what u hear */ 8528 8529 spec->num_inputs = 3; 8530 spec->input_pins[0] = 0x12; 8531 spec->input_pins[1] = 0x11; 8532 spec->input_pins[2] = 0x13; 8533 spec->shared_mic_nid = 0x7; 8534 spec->unsol_tag_amic1 = 0x11; 8535 break; 8536 case QUIRK_SBZ: 8537 case QUIRK_R3D: 8538 spec->num_outputs = 2; 8539 spec->out_pins[0] = 0x0B; /* Line out */ 8540 spec->out_pins[1] = 0x0F; /* Rear headphone out */ 8541 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/ 8542 spec->out_pins[3] = 0x11; /* Rear surround */ 8543 spec->shared_out_nid = 0x2; 8544 spec->unsol_tag_hp = spec->out_pins[1]; 8545 spec->unsol_tag_front_hp = spec->out_pins[2]; 8546 8547 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */ 8548 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */ 8549 spec->adcs[2] = 0xa; /* what u hear */ 8550 8551 spec->num_inputs = 2; 8552 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */ 8553 spec->input_pins[1] = 0x13; /* What U Hear */ 8554 spec->shared_mic_nid = 0x7; 8555 spec->unsol_tag_amic1 = spec->input_pins[0]; 8556 8557 /* SPDIF I/O */ 8558 spec->dig_out = 0x05; 8559 spec->multiout.dig_out_nid = spec->dig_out; 8560 spec->dig_in = 0x09; 8561 break; 8562 case QUIRK_ZXR: 8563 spec->num_outputs = 2; 8564 spec->out_pins[0] = 0x0B; /* Line out */ 8565 spec->out_pins[1] = 0x0F; /* Rear headphone out */ 8566 spec->out_pins[2] = 0x10; /* Center/LFE */ 8567 spec->out_pins[3] = 0x11; /* Rear surround */ 8568 spec->shared_out_nid = 0x2; 8569 spec->unsol_tag_hp = spec->out_pins[1]; 8570 spec->unsol_tag_front_hp = spec->out_pins[2]; 8571 8572 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */ 8573 spec->adcs[1] = 0x8; /* Not connected, no front mic */ 8574 spec->adcs[2] = 0xa; /* what u hear */ 8575 8576 spec->num_inputs = 2; 8577 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */ 8578 spec->input_pins[1] = 0x13; /* What U Hear */ 8579 spec->shared_mic_nid = 0x7; 8580 spec->unsol_tag_amic1 = spec->input_pins[0]; 8581 break; 8582 case QUIRK_ZXR_DBPRO: 8583 spec->adcs[0] = 0x8; /* ZxR DBPro Aux In */ 8584 8585 spec->num_inputs = 1; 8586 spec->input_pins[0] = 0x11; /* RCA Line-in */ 8587 8588 spec->dig_out = 0x05; 8589 spec->multiout.dig_out_nid = spec->dig_out; 8590 8591 spec->dig_in = 0x09; 8592 break; 8593 case QUIRK_AE5: 8594 spec->num_outputs = 2; 8595 spec->out_pins[0] = 0x0B; /* Line out */ 8596 spec->out_pins[1] = 0x11; /* Rear headphone out */ 8597 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/ 8598 spec->out_pins[3] = 0x0F; /* Rear surround */ 8599 spec->shared_out_nid = 0x2; 8600 spec->unsol_tag_hp = spec->out_pins[1]; 8601 spec->unsol_tag_front_hp = spec->out_pins[2]; 8602 8603 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */ 8604 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */ 8605 spec->adcs[2] = 0xa; /* what u hear */ 8606 8607 spec->num_inputs = 2; 8608 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */ 8609 spec->input_pins[1] = 0x13; /* What U Hear */ 8610 spec->shared_mic_nid = 0x7; 8611 spec->unsol_tag_amic1 = spec->input_pins[0]; 8612 8613 /* SPDIF I/O */ 8614 spec->dig_out = 0x05; 8615 spec->multiout.dig_out_nid = spec->dig_out; 8616 break; 8617 case QUIRK_R3DI: 8618 spec->num_outputs = 2; 8619 spec->out_pins[0] = 0x0B; /* Line out */ 8620 spec->out_pins[1] = 0x0F; /* Rear headphone out */ 8621 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/ 8622 spec->out_pins[3] = 0x11; /* Rear surround */ 8623 spec->shared_out_nid = 0x2; 8624 spec->unsol_tag_hp = spec->out_pins[1]; 8625 spec->unsol_tag_front_hp = spec->out_pins[2]; 8626 8627 spec->adcs[0] = 0x07; /* Rear Mic / Line-in */ 8628 spec->adcs[1] = 0x08; /* Front Mic, but only if no DSP */ 8629 spec->adcs[2] = 0x0a; /* what u hear */ 8630 8631 spec->num_inputs = 2; 8632 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */ 8633 spec->input_pins[1] = 0x13; /* What U Hear */ 8634 spec->shared_mic_nid = 0x7; 8635 spec->unsol_tag_amic1 = spec->input_pins[0]; 8636 8637 /* SPDIF I/O */ 8638 spec->dig_out = 0x05; 8639 spec->multiout.dig_out_nid = spec->dig_out; 8640 break; 8641 default: 8642 spec->num_outputs = 2; 8643 spec->out_pins[0] = 0x0b; /* speaker out */ 8644 spec->out_pins[1] = 0x10; /* headphone out */ 8645 spec->shared_out_nid = 0x2; 8646 spec->unsol_tag_hp = spec->out_pins[1]; 8647 8648 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */ 8649 spec->adcs[1] = 0x8; /* analog mic2 */ 8650 spec->adcs[2] = 0xa; /* what u hear */ 8651 8652 spec->num_inputs = 3; 8653 spec->input_pins[0] = 0x12; 8654 spec->input_pins[1] = 0x11; 8655 spec->input_pins[2] = 0x13; 8656 spec->shared_mic_nid = 0x7; 8657 spec->unsol_tag_amic1 = spec->input_pins[0]; 8658 8659 /* SPDIF I/O */ 8660 spec->dig_out = 0x05; 8661 spec->multiout.dig_out_nid = spec->dig_out; 8662 spec->dig_in = 0x09; 8663 break; 8664 } 8665 } 8666 8667 static int ca0132_prepare_verbs(struct hda_codec *codec) 8668 { 8669 /* Verbs + terminator (an empty element) */ 8670 #define NUM_SPEC_VERBS 2 8671 struct ca0132_spec *spec = codec->spec; 8672 8673 spec->chip_init_verbs = ca0132_init_verbs0; 8674 /* 8675 * Since desktop cards use pci_mmio, this can be used to determine 8676 * whether or not to use these verbs instead of a separate bool. 8677 */ 8678 if (ca0132_use_pci_mmio(spec)) 8679 spec->desktop_init_verbs = ca0132_init_verbs1; 8680 spec->spec_init_verbs = kcalloc(NUM_SPEC_VERBS, 8681 sizeof(struct hda_verb), 8682 GFP_KERNEL); 8683 if (!spec->spec_init_verbs) 8684 return -ENOMEM; 8685 8686 /* config EAPD */ 8687 spec->spec_init_verbs[0].nid = 0x0b; 8688 spec->spec_init_verbs[0].param = 0x78D; 8689 spec->spec_init_verbs[0].verb = 0x00; 8690 8691 /* Previously commented configuration */ 8692 /* 8693 spec->spec_init_verbs[2].nid = 0x0b; 8694 spec->spec_init_verbs[2].param = AC_VERB_SET_EAPD_BTLENABLE; 8695 spec->spec_init_verbs[2].verb = 0x02; 8696 8697 spec->spec_init_verbs[3].nid = 0x10; 8698 spec->spec_init_verbs[3].param = 0x78D; 8699 spec->spec_init_verbs[3].verb = 0x02; 8700 8701 spec->spec_init_verbs[4].nid = 0x10; 8702 spec->spec_init_verbs[4].param = AC_VERB_SET_EAPD_BTLENABLE; 8703 spec->spec_init_verbs[4].verb = 0x02; 8704 */ 8705 8706 /* Terminator: spec->spec_init_verbs[NUM_SPEC_VERBS-1] */ 8707 return 0; 8708 } 8709 8710 /* 8711 * The Sound Blaster ZxR shares the same PCI subsystem ID as some regular 8712 * Sound Blaster Z cards. However, they have different HDA codec subsystem 8713 * ID's. So, we check for the ZxR's subsystem ID, as well as the DBPro 8714 * daughter boards ID. 8715 */ 8716 static void sbz_detect_quirk(struct hda_codec *codec) 8717 { 8718 struct ca0132_spec *spec = codec->spec; 8719 8720 switch (codec->core.subsystem_id) { 8721 case 0x11020033: 8722 spec->quirk = QUIRK_ZXR; 8723 break; 8724 case 0x1102003f: 8725 spec->quirk = QUIRK_ZXR_DBPRO; 8726 break; 8727 default: 8728 spec->quirk = QUIRK_SBZ; 8729 break; 8730 } 8731 } 8732 8733 static int patch_ca0132(struct hda_codec *codec) 8734 { 8735 struct ca0132_spec *spec; 8736 int err; 8737 const struct snd_pci_quirk *quirk; 8738 8739 codec_dbg(codec, "patch_ca0132\n"); 8740 8741 spec = kzalloc(sizeof(*spec), GFP_KERNEL); 8742 if (!spec) 8743 return -ENOMEM; 8744 codec->spec = spec; 8745 spec->codec = codec; 8746 8747 /* Detect codec quirk */ 8748 quirk = snd_pci_quirk_lookup(codec->bus->pci, ca0132_quirks); 8749 if (quirk) 8750 spec->quirk = quirk->value; 8751 else 8752 spec->quirk = QUIRK_NONE; 8753 if (ca0132_quirk(spec) == QUIRK_SBZ) 8754 sbz_detect_quirk(codec); 8755 8756 if (ca0132_quirk(spec) == QUIRK_ZXR_DBPRO) 8757 codec->patch_ops = dbpro_patch_ops; 8758 else 8759 codec->patch_ops = ca0132_patch_ops; 8760 8761 codec->pcm_format_first = 1; 8762 codec->no_sticky_stream = 1; 8763 8764 8765 spec->dsp_state = DSP_DOWNLOAD_INIT; 8766 spec->num_mixers = 1; 8767 8768 /* Set which mixers each quirk uses. */ 8769 switch (ca0132_quirk(spec)) { 8770 case QUIRK_SBZ: 8771 spec->mixers[0] = desktop_mixer; 8772 snd_hda_codec_set_name(codec, "Sound Blaster Z"); 8773 break; 8774 case QUIRK_ZXR: 8775 spec->mixers[0] = desktop_mixer; 8776 snd_hda_codec_set_name(codec, "Sound Blaster ZxR"); 8777 break; 8778 case QUIRK_ZXR_DBPRO: 8779 break; 8780 case QUIRK_R3D: 8781 spec->mixers[0] = desktop_mixer; 8782 snd_hda_codec_set_name(codec, "Recon3D"); 8783 break; 8784 case QUIRK_R3DI: 8785 spec->mixers[0] = r3di_mixer; 8786 snd_hda_codec_set_name(codec, "Recon3Di"); 8787 break; 8788 case QUIRK_AE5: 8789 spec->mixers[0] = desktop_mixer; 8790 snd_hda_codec_set_name(codec, "Sound BlasterX AE-5"); 8791 break; 8792 default: 8793 spec->mixers[0] = ca0132_mixer; 8794 break; 8795 } 8796 8797 /* Setup whether or not to use alt functions/controls/pci_mmio */ 8798 switch (ca0132_quirk(spec)) { 8799 case QUIRK_SBZ: 8800 case QUIRK_R3D: 8801 case QUIRK_AE5: 8802 case QUIRK_ZXR: 8803 spec->use_alt_controls = true; 8804 spec->use_alt_functions = true; 8805 spec->use_pci_mmio = true; 8806 break; 8807 case QUIRK_R3DI: 8808 spec->use_alt_controls = true; 8809 spec->use_alt_functions = true; 8810 spec->use_pci_mmio = false; 8811 break; 8812 default: 8813 spec->use_alt_controls = false; 8814 spec->use_alt_functions = false; 8815 spec->use_pci_mmio = false; 8816 break; 8817 } 8818 8819 #ifdef CONFIG_PCI 8820 if (spec->use_pci_mmio) { 8821 spec->mem_base = pci_iomap(codec->bus->pci, 2, 0xC20); 8822 if (spec->mem_base == NULL) { 8823 codec_warn(codec, "pci_iomap failed! Setting quirk to QUIRK_NONE."); 8824 spec->quirk = QUIRK_NONE; 8825 } 8826 } 8827 #endif 8828 8829 spec->base_init_verbs = ca0132_base_init_verbs; 8830 spec->base_exit_verbs = ca0132_base_exit_verbs; 8831 8832 INIT_DELAYED_WORK(&spec->unsol_hp_work, ca0132_unsol_hp_delayed); 8833 8834 ca0132_init_chip(codec); 8835 8836 ca0132_config(codec); 8837 8838 err = ca0132_prepare_verbs(codec); 8839 if (err < 0) 8840 goto error; 8841 8842 err = snd_hda_parse_pin_def_config(codec, &spec->autocfg, NULL); 8843 if (err < 0) 8844 goto error; 8845 8846 return 0; 8847 8848 error: 8849 ca0132_free(codec); 8850 return err; 8851 } 8852 8853 /* 8854 * patch entries 8855 */ 8856 static struct hda_device_id snd_hda_id_ca0132[] = { 8857 HDA_CODEC_ENTRY(0x11020011, "CA0132", patch_ca0132), 8858 {} /* terminator */ 8859 }; 8860 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_ca0132); 8861 8862 MODULE_LICENSE("GPL"); 8863 MODULE_DESCRIPTION("Creative Sound Core3D codec"); 8864 8865 static struct hda_codec_driver ca0132_driver = { 8866 .id = snd_hda_id_ca0132, 8867 }; 8868 8869 module_hda_codec_driver(ca0132_driver); 8870