1 /* 2 * 3 * Implementation of primary ALSA driver code base for NVIDIA Tegra HDA. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program. If not, see <http://www.gnu.org/licenses/>. 16 * 17 */ 18 19 #include <linux/clk.h> 20 #include <linux/clocksource.h> 21 #include <linux/completion.h> 22 #include <linux/delay.h> 23 #include <linux/dma-mapping.h> 24 #include <linux/init.h> 25 #include <linux/interrupt.h> 26 #include <linux/io.h> 27 #include <linux/kernel.h> 28 #include <linux/module.h> 29 #include <linux/moduleparam.h> 30 #include <linux/mutex.h> 31 #include <linux/of_device.h> 32 #include <linux/slab.h> 33 #include <linux/time.h> 34 35 #include <sound/core.h> 36 #include <sound/initval.h> 37 38 #include <sound/hda_codec.h> 39 #include "hda_controller.h" 40 41 /* Defines for Nvidia Tegra HDA support */ 42 #define HDA_BAR0 0x8000 43 44 #define HDA_CFG_CMD 0x1004 45 #define HDA_CFG_BAR0 0x1010 46 47 #define HDA_ENABLE_IO_SPACE (1 << 0) 48 #define HDA_ENABLE_MEM_SPACE (1 << 1) 49 #define HDA_ENABLE_BUS_MASTER (1 << 2) 50 #define HDA_ENABLE_SERR (1 << 8) 51 #define HDA_DISABLE_INTR (1 << 10) 52 #define HDA_BAR0_INIT_PROGRAM 0xFFFFFFFF 53 #define HDA_BAR0_FINAL_PROGRAM (1 << 14) 54 55 /* IPFS */ 56 #define HDA_IPFS_CONFIG 0x180 57 #define HDA_IPFS_EN_FPCI 0x1 58 59 #define HDA_IPFS_FPCI_BAR0 0x80 60 #define HDA_FPCI_BAR0_START 0x40 61 62 #define HDA_IPFS_INTR_MASK 0x188 63 #define HDA_IPFS_EN_INTR (1 << 16) 64 65 /* max number of SDs */ 66 #define NUM_CAPTURE_SD 1 67 #define NUM_PLAYBACK_SD 1 68 69 struct hda_tegra { 70 struct azx chip; 71 struct device *dev; 72 struct clk *hda_clk; 73 struct clk *hda2codec_2x_clk; 74 struct clk *hda2hdmi_clk; 75 void __iomem *regs; 76 struct work_struct probe_work; 77 }; 78 79 #ifdef CONFIG_PM 80 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT; 81 module_param(power_save, bint, 0644); 82 MODULE_PARM_DESC(power_save, 83 "Automatic power-saving timeout (in seconds, 0 = disable)."); 84 #else 85 #define power_save 0 86 #endif 87 88 /* 89 * DMA page allocation ops. 90 */ 91 static int dma_alloc_pages(struct hdac_bus *bus, int type, size_t size, 92 struct snd_dma_buffer *buf) 93 { 94 return snd_dma_alloc_pages(type, bus->dev, size, buf); 95 } 96 97 static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf) 98 { 99 snd_dma_free_pages(buf); 100 } 101 102 /* 103 * Register access ops. Tegra HDA register access is DWORD only. 104 */ 105 static void hda_tegra_writel(u32 value, u32 __iomem *addr) 106 { 107 writel(value, addr); 108 } 109 110 static u32 hda_tegra_readl(u32 __iomem *addr) 111 { 112 return readl(addr); 113 } 114 115 static void hda_tegra_writew(u16 value, u16 __iomem *addr) 116 { 117 unsigned int shift = ((unsigned long)(addr) & 0x3) << 3; 118 void __iomem *dword_addr = (void __iomem *)((unsigned long)(addr) & ~0x3); 119 u32 v; 120 121 v = readl(dword_addr); 122 v &= ~(0xffff << shift); 123 v |= value << shift; 124 writel(v, dword_addr); 125 } 126 127 static u16 hda_tegra_readw(u16 __iomem *addr) 128 { 129 unsigned int shift = ((unsigned long)(addr) & 0x3) << 3; 130 void __iomem *dword_addr = (void __iomem *)((unsigned long)(addr) & ~0x3); 131 u32 v; 132 133 v = readl(dword_addr); 134 return (v >> shift) & 0xffff; 135 } 136 137 static void hda_tegra_writeb(u8 value, u8 __iomem *addr) 138 { 139 unsigned int shift = ((unsigned long)(addr) & 0x3) << 3; 140 void __iomem *dword_addr = (void __iomem *)((unsigned long)(addr) & ~0x3); 141 u32 v; 142 143 v = readl(dword_addr); 144 v &= ~(0xff << shift); 145 v |= value << shift; 146 writel(v, dword_addr); 147 } 148 149 static u8 hda_tegra_readb(u8 __iomem *addr) 150 { 151 unsigned int shift = ((unsigned long)(addr) & 0x3) << 3; 152 void __iomem *dword_addr = (void __iomem *)((unsigned long)(addr) & ~0x3); 153 u32 v; 154 155 v = readl(dword_addr); 156 return (v >> shift) & 0xff; 157 } 158 159 static const struct hdac_io_ops hda_tegra_io_ops = { 160 .reg_writel = hda_tegra_writel, 161 .reg_readl = hda_tegra_readl, 162 .reg_writew = hda_tegra_writew, 163 .reg_readw = hda_tegra_readw, 164 .reg_writeb = hda_tegra_writeb, 165 .reg_readb = hda_tegra_readb, 166 .dma_alloc_pages = dma_alloc_pages, 167 .dma_free_pages = dma_free_pages, 168 }; 169 170 static const struct hda_controller_ops hda_tegra_ops; /* nothing special */ 171 172 static void hda_tegra_init(struct hda_tegra *hda) 173 { 174 u32 v; 175 176 /* Enable PCI access */ 177 v = readl(hda->regs + HDA_IPFS_CONFIG); 178 v |= HDA_IPFS_EN_FPCI; 179 writel(v, hda->regs + HDA_IPFS_CONFIG); 180 181 /* Enable MEM/IO space and bus master */ 182 v = readl(hda->regs + HDA_CFG_CMD); 183 v &= ~HDA_DISABLE_INTR; 184 v |= HDA_ENABLE_MEM_SPACE | HDA_ENABLE_IO_SPACE | 185 HDA_ENABLE_BUS_MASTER | HDA_ENABLE_SERR; 186 writel(v, hda->regs + HDA_CFG_CMD); 187 188 writel(HDA_BAR0_INIT_PROGRAM, hda->regs + HDA_CFG_BAR0); 189 writel(HDA_BAR0_FINAL_PROGRAM, hda->regs + HDA_CFG_BAR0); 190 writel(HDA_FPCI_BAR0_START, hda->regs + HDA_IPFS_FPCI_BAR0); 191 192 v = readl(hda->regs + HDA_IPFS_INTR_MASK); 193 v |= HDA_IPFS_EN_INTR; 194 writel(v, hda->regs + HDA_IPFS_INTR_MASK); 195 } 196 197 static int hda_tegra_enable_clocks(struct hda_tegra *data) 198 { 199 int rc; 200 201 rc = clk_prepare_enable(data->hda_clk); 202 if (rc) 203 return rc; 204 rc = clk_prepare_enable(data->hda2codec_2x_clk); 205 if (rc) 206 goto disable_hda; 207 rc = clk_prepare_enable(data->hda2hdmi_clk); 208 if (rc) 209 goto disable_codec_2x; 210 211 return 0; 212 213 disable_codec_2x: 214 clk_disable_unprepare(data->hda2codec_2x_clk); 215 disable_hda: 216 clk_disable_unprepare(data->hda_clk); 217 return rc; 218 } 219 220 #ifdef CONFIG_PM_SLEEP 221 static void hda_tegra_disable_clocks(struct hda_tegra *data) 222 { 223 clk_disable_unprepare(data->hda2hdmi_clk); 224 clk_disable_unprepare(data->hda2codec_2x_clk); 225 clk_disable_unprepare(data->hda_clk); 226 } 227 228 /* 229 * power management 230 */ 231 static int hda_tegra_suspend(struct device *dev) 232 { 233 struct snd_card *card = dev_get_drvdata(dev); 234 struct azx *chip = card->private_data; 235 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip); 236 237 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 238 239 azx_stop_chip(chip); 240 azx_enter_link_reset(chip); 241 hda_tegra_disable_clocks(hda); 242 243 return 0; 244 } 245 246 static int hda_tegra_resume(struct device *dev) 247 { 248 struct snd_card *card = dev_get_drvdata(dev); 249 struct azx *chip = card->private_data; 250 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip); 251 252 hda_tegra_enable_clocks(hda); 253 254 hda_tegra_init(hda); 255 256 azx_init_chip(chip, 1); 257 258 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 259 260 return 0; 261 } 262 #endif /* CONFIG_PM_SLEEP */ 263 264 static const struct dev_pm_ops hda_tegra_pm = { 265 SET_SYSTEM_SLEEP_PM_OPS(hda_tegra_suspend, hda_tegra_resume) 266 }; 267 268 static int hda_tegra_dev_disconnect(struct snd_device *device) 269 { 270 struct azx *chip = device->device_data; 271 272 chip->bus.shutdown = 1; 273 return 0; 274 } 275 276 /* 277 * destructor 278 */ 279 static int hda_tegra_dev_free(struct snd_device *device) 280 { 281 struct azx *chip = device->device_data; 282 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip); 283 284 cancel_work_sync(&hda->probe_work); 285 if (azx_bus(chip)->chip_init) { 286 azx_stop_all_streams(chip); 287 azx_stop_chip(chip); 288 } 289 290 azx_free_stream_pages(chip); 291 azx_free_streams(chip); 292 snd_hdac_bus_exit(azx_bus(chip)); 293 294 return 0; 295 } 296 297 static int hda_tegra_init_chip(struct azx *chip, struct platform_device *pdev) 298 { 299 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip); 300 struct hdac_bus *bus = azx_bus(chip); 301 struct device *dev = hda->dev; 302 struct resource *res; 303 int err; 304 305 hda->hda_clk = devm_clk_get(dev, "hda"); 306 if (IS_ERR(hda->hda_clk)) { 307 dev_err(dev, "failed to get hda clock\n"); 308 return PTR_ERR(hda->hda_clk); 309 } 310 hda->hda2codec_2x_clk = devm_clk_get(dev, "hda2codec_2x"); 311 if (IS_ERR(hda->hda2codec_2x_clk)) { 312 dev_err(dev, "failed to get hda2codec_2x clock\n"); 313 return PTR_ERR(hda->hda2codec_2x_clk); 314 } 315 hda->hda2hdmi_clk = devm_clk_get(dev, "hda2hdmi"); 316 if (IS_ERR(hda->hda2hdmi_clk)) { 317 dev_err(dev, "failed to get hda2hdmi clock\n"); 318 return PTR_ERR(hda->hda2hdmi_clk); 319 } 320 321 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 322 hda->regs = devm_ioremap_resource(dev, res); 323 if (IS_ERR(hda->regs)) 324 return PTR_ERR(hda->regs); 325 326 bus->remap_addr = hda->regs + HDA_BAR0; 327 bus->addr = res->start + HDA_BAR0; 328 329 err = hda_tegra_enable_clocks(hda); 330 if (err) { 331 dev_err(dev, "failed to get enable clocks\n"); 332 return err; 333 } 334 335 hda_tegra_init(hda); 336 337 return 0; 338 } 339 340 static int hda_tegra_first_init(struct azx *chip, struct platform_device *pdev) 341 { 342 struct hdac_bus *bus = azx_bus(chip); 343 struct snd_card *card = chip->card; 344 int err; 345 unsigned short gcap; 346 int irq_id = platform_get_irq(pdev, 0); 347 348 err = hda_tegra_init_chip(chip, pdev); 349 if (err) 350 return err; 351 352 err = devm_request_irq(chip->card->dev, irq_id, azx_interrupt, 353 IRQF_SHARED, KBUILD_MODNAME, chip); 354 if (err) { 355 dev_err(chip->card->dev, 356 "unable to request IRQ %d, disabling device\n", 357 irq_id); 358 return err; 359 } 360 bus->irq = irq_id; 361 362 synchronize_irq(bus->irq); 363 364 gcap = azx_readw(chip, GCAP); 365 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap); 366 367 /* read number of streams from GCAP register instead of using 368 * hardcoded value 369 */ 370 chip->capture_streams = (gcap >> 8) & 0x0f; 371 chip->playback_streams = (gcap >> 12) & 0x0f; 372 if (!chip->playback_streams && !chip->capture_streams) { 373 /* gcap didn't give any info, switching to old method */ 374 chip->playback_streams = NUM_PLAYBACK_SD; 375 chip->capture_streams = NUM_CAPTURE_SD; 376 } 377 chip->capture_index_offset = 0; 378 chip->playback_index_offset = chip->capture_streams; 379 chip->num_streams = chip->playback_streams + chip->capture_streams; 380 381 /* initialize streams */ 382 err = azx_init_streams(chip); 383 if (err < 0) { 384 dev_err(card->dev, "failed to initialize streams: %d\n", err); 385 return err; 386 } 387 388 err = azx_alloc_stream_pages(chip); 389 if (err < 0) { 390 dev_err(card->dev, "failed to allocate stream pages: %d\n", 391 err); 392 return err; 393 } 394 395 /* initialize chip */ 396 azx_init_chip(chip, 1); 397 398 /* codec detection */ 399 if (!bus->codec_mask) { 400 dev_err(card->dev, "no codecs found!\n"); 401 return -ENODEV; 402 } 403 404 strcpy(card->driver, "tegra-hda"); 405 strcpy(card->shortname, "tegra-hda"); 406 snprintf(card->longname, sizeof(card->longname), 407 "%s at 0x%lx irq %i", 408 card->shortname, bus->addr, bus->irq); 409 410 return 0; 411 } 412 413 /* 414 * constructor 415 */ 416 417 static void hda_tegra_probe_work(struct work_struct *work); 418 419 static int hda_tegra_create(struct snd_card *card, 420 unsigned int driver_caps, 421 struct hda_tegra *hda) 422 { 423 static struct snd_device_ops ops = { 424 .dev_disconnect = hda_tegra_dev_disconnect, 425 .dev_free = hda_tegra_dev_free, 426 }; 427 struct azx *chip; 428 int err; 429 430 chip = &hda->chip; 431 432 mutex_init(&chip->open_mutex); 433 chip->card = card; 434 chip->ops = &hda_tegra_ops; 435 chip->driver_caps = driver_caps; 436 chip->driver_type = driver_caps & 0xff; 437 chip->dev_index = 0; 438 INIT_LIST_HEAD(&chip->pcm_list); 439 440 chip->codec_probe_mask = -1; 441 442 chip->single_cmd = false; 443 chip->snoop = true; 444 445 INIT_WORK(&hda->probe_work, hda_tegra_probe_work); 446 447 err = azx_bus_init(chip, NULL, &hda_tegra_io_ops); 448 if (err < 0) 449 return err; 450 451 chip->bus.needs_damn_long_delay = 1; 452 453 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); 454 if (err < 0) { 455 dev_err(card->dev, "Error creating device\n"); 456 return err; 457 } 458 459 return 0; 460 } 461 462 static const struct of_device_id hda_tegra_match[] = { 463 { .compatible = "nvidia,tegra30-hda" }, 464 {}, 465 }; 466 MODULE_DEVICE_TABLE(of, hda_tegra_match); 467 468 static int hda_tegra_probe(struct platform_device *pdev) 469 { 470 const unsigned int driver_flags = AZX_DCAPS_CORBRP_SELF_CLEAR; 471 struct snd_card *card; 472 struct azx *chip; 473 struct hda_tegra *hda; 474 int err; 475 476 hda = devm_kzalloc(&pdev->dev, sizeof(*hda), GFP_KERNEL); 477 if (!hda) 478 return -ENOMEM; 479 hda->dev = &pdev->dev; 480 chip = &hda->chip; 481 482 err = snd_card_new(&pdev->dev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1, 483 THIS_MODULE, 0, &card); 484 if (err < 0) { 485 dev_err(&pdev->dev, "Error creating card!\n"); 486 return err; 487 } 488 489 err = hda_tegra_create(card, driver_flags, hda); 490 if (err < 0) 491 goto out_free; 492 card->private_data = chip; 493 494 dev_set_drvdata(&pdev->dev, card); 495 schedule_work(&hda->probe_work); 496 497 return 0; 498 499 out_free: 500 snd_card_free(card); 501 return err; 502 } 503 504 static void hda_tegra_probe_work(struct work_struct *work) 505 { 506 struct hda_tegra *hda = container_of(work, struct hda_tegra, probe_work); 507 struct azx *chip = &hda->chip; 508 struct platform_device *pdev = to_platform_device(hda->dev); 509 int err; 510 511 err = hda_tegra_first_init(chip, pdev); 512 if (err < 0) 513 goto out_free; 514 515 /* create codec instances */ 516 err = azx_probe_codecs(chip, 0); 517 if (err < 0) 518 goto out_free; 519 520 err = azx_codec_configure(chip); 521 if (err < 0) 522 goto out_free; 523 524 err = snd_card_register(chip->card); 525 if (err < 0) 526 goto out_free; 527 528 chip->running = 1; 529 snd_hda_set_power_save(&chip->bus, power_save * 1000); 530 531 out_free: 532 return; /* no error return from async probe */ 533 } 534 535 static int hda_tegra_remove(struct platform_device *pdev) 536 { 537 return snd_card_free(dev_get_drvdata(&pdev->dev)); 538 } 539 540 static void hda_tegra_shutdown(struct platform_device *pdev) 541 { 542 struct snd_card *card = dev_get_drvdata(&pdev->dev); 543 struct azx *chip; 544 545 if (!card) 546 return; 547 chip = card->private_data; 548 if (chip && chip->running) 549 azx_stop_chip(chip); 550 } 551 552 static struct platform_driver tegra_platform_hda = { 553 .driver = { 554 .name = "tegra-hda", 555 .pm = &hda_tegra_pm, 556 .of_match_table = hda_tegra_match, 557 }, 558 .probe = hda_tegra_probe, 559 .remove = hda_tegra_remove, 560 .shutdown = hda_tegra_shutdown, 561 }; 562 module_platform_driver(tegra_platform_hda); 563 564 MODULE_DESCRIPTION("Tegra HDA bus driver"); 565 MODULE_LICENSE("GPL v2"); 566