1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * 4 * Implementation of primary ALSA driver code base for NVIDIA Tegra HDA. 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/clocksource.h> 9 #include <linux/completion.h> 10 #include <linux/delay.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/init.h> 13 #include <linux/interrupt.h> 14 #include <linux/io.h> 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/moduleparam.h> 18 #include <linux/mutex.h> 19 #include <linux/of_device.h> 20 #include <linux/reset.h> 21 #include <linux/slab.h> 22 #include <linux/time.h> 23 #include <linux/string.h> 24 #include <linux/pm_runtime.h> 25 26 #include <sound/core.h> 27 #include <sound/initval.h> 28 29 #include <sound/hda_codec.h> 30 #include "hda_controller.h" 31 32 /* Defines for Nvidia Tegra HDA support */ 33 #define HDA_BAR0 0x8000 34 35 #define HDA_CFG_CMD 0x1004 36 #define HDA_CFG_BAR0 0x1010 37 38 #define HDA_ENABLE_IO_SPACE (1 << 0) 39 #define HDA_ENABLE_MEM_SPACE (1 << 1) 40 #define HDA_ENABLE_BUS_MASTER (1 << 2) 41 #define HDA_ENABLE_SERR (1 << 8) 42 #define HDA_DISABLE_INTR (1 << 10) 43 #define HDA_BAR0_INIT_PROGRAM 0xFFFFFFFF 44 #define HDA_BAR0_FINAL_PROGRAM (1 << 14) 45 46 /* IPFS */ 47 #define HDA_IPFS_CONFIG 0x180 48 #define HDA_IPFS_EN_FPCI 0x1 49 50 #define HDA_IPFS_FPCI_BAR0 0x80 51 #define HDA_FPCI_BAR0_START 0x40 52 53 #define HDA_IPFS_INTR_MASK 0x188 54 #define HDA_IPFS_EN_INTR (1 << 16) 55 56 /* FPCI */ 57 #define FPCI_DBG_CFG_2 0x10F4 58 #define FPCI_GCAP_NSDO_SHIFT 18 59 #define FPCI_GCAP_NSDO_MASK (0x3 << FPCI_GCAP_NSDO_SHIFT) 60 61 /* max number of SDs */ 62 #define NUM_CAPTURE_SD 1 63 #define NUM_PLAYBACK_SD 1 64 65 /* 66 * Tegra194 does not reflect correct number of SDO lines. Below macro 67 * is used to update the GCAP register to workaround the issue. 68 */ 69 #define TEGRA194_NUM_SDO_LINES 4 70 71 struct hda_tegra { 72 struct azx chip; 73 struct device *dev; 74 struct reset_control *reset; 75 struct clk_bulk_data clocks[3]; 76 unsigned int nclocks; 77 void __iomem *regs; 78 struct work_struct probe_work; 79 }; 80 81 #ifdef CONFIG_PM 82 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT; 83 module_param(power_save, bint, 0644); 84 MODULE_PARM_DESC(power_save, 85 "Automatic power-saving timeout (in seconds, 0 = disable)."); 86 #else 87 #define power_save 0 88 #endif 89 90 static const struct hda_controller_ops hda_tegra_ops; /* nothing special */ 91 92 static void hda_tegra_init(struct hda_tegra *hda) 93 { 94 u32 v; 95 96 /* Enable PCI access */ 97 v = readl(hda->regs + HDA_IPFS_CONFIG); 98 v |= HDA_IPFS_EN_FPCI; 99 writel(v, hda->regs + HDA_IPFS_CONFIG); 100 101 /* Enable MEM/IO space and bus master */ 102 v = readl(hda->regs + HDA_CFG_CMD); 103 v &= ~HDA_DISABLE_INTR; 104 v |= HDA_ENABLE_MEM_SPACE | HDA_ENABLE_IO_SPACE | 105 HDA_ENABLE_BUS_MASTER | HDA_ENABLE_SERR; 106 writel(v, hda->regs + HDA_CFG_CMD); 107 108 writel(HDA_BAR0_INIT_PROGRAM, hda->regs + HDA_CFG_BAR0); 109 writel(HDA_BAR0_FINAL_PROGRAM, hda->regs + HDA_CFG_BAR0); 110 writel(HDA_FPCI_BAR0_START, hda->regs + HDA_IPFS_FPCI_BAR0); 111 112 v = readl(hda->regs + HDA_IPFS_INTR_MASK); 113 v |= HDA_IPFS_EN_INTR; 114 writel(v, hda->regs + HDA_IPFS_INTR_MASK); 115 } 116 117 /* 118 * power management 119 */ 120 static int __maybe_unused hda_tegra_suspend(struct device *dev) 121 { 122 struct snd_card *card = dev_get_drvdata(dev); 123 int rc; 124 125 rc = pm_runtime_force_suspend(dev); 126 if (rc < 0) 127 return rc; 128 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 129 130 return 0; 131 } 132 133 static int __maybe_unused hda_tegra_resume(struct device *dev) 134 { 135 struct snd_card *card = dev_get_drvdata(dev); 136 int rc; 137 138 rc = pm_runtime_force_resume(dev); 139 if (rc < 0) 140 return rc; 141 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 142 143 return 0; 144 } 145 146 static int __maybe_unused hda_tegra_runtime_suspend(struct device *dev) 147 { 148 struct snd_card *card = dev_get_drvdata(dev); 149 struct azx *chip = card->private_data; 150 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip); 151 152 if (chip && chip->running) { 153 /* enable controller wake up event */ 154 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) | 155 STATESTS_INT_MASK); 156 157 azx_stop_chip(chip); 158 azx_enter_link_reset(chip); 159 } 160 clk_bulk_disable_unprepare(hda->nclocks, hda->clocks); 161 162 return 0; 163 } 164 165 static int __maybe_unused hda_tegra_runtime_resume(struct device *dev) 166 { 167 struct snd_card *card = dev_get_drvdata(dev); 168 struct azx *chip = card->private_data; 169 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip); 170 int rc; 171 172 if (!chip->running) { 173 rc = reset_control_assert(hda->reset); 174 if (rc) 175 return rc; 176 } 177 178 rc = clk_bulk_prepare_enable(hda->nclocks, hda->clocks); 179 if (rc != 0) 180 return rc; 181 if (chip->running) { 182 hda_tegra_init(hda); 183 azx_init_chip(chip, 1); 184 /* disable controller wake up event*/ 185 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) & 186 ~STATESTS_INT_MASK); 187 } else { 188 usleep_range(10, 100); 189 190 rc = reset_control_deassert(hda->reset); 191 if (rc) 192 return rc; 193 } 194 195 return 0; 196 } 197 198 static const struct dev_pm_ops hda_tegra_pm = { 199 SET_SYSTEM_SLEEP_PM_OPS(hda_tegra_suspend, hda_tegra_resume) 200 SET_RUNTIME_PM_OPS(hda_tegra_runtime_suspend, 201 hda_tegra_runtime_resume, 202 NULL) 203 }; 204 205 static int hda_tegra_dev_disconnect(struct snd_device *device) 206 { 207 struct azx *chip = device->device_data; 208 209 chip->bus.shutdown = 1; 210 return 0; 211 } 212 213 /* 214 * destructor 215 */ 216 static int hda_tegra_dev_free(struct snd_device *device) 217 { 218 struct azx *chip = device->device_data; 219 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip); 220 221 cancel_work_sync(&hda->probe_work); 222 if (azx_bus(chip)->chip_init) { 223 azx_stop_all_streams(chip); 224 azx_stop_chip(chip); 225 } 226 227 azx_free_stream_pages(chip); 228 azx_free_streams(chip); 229 snd_hdac_bus_exit(azx_bus(chip)); 230 231 return 0; 232 } 233 234 static int hda_tegra_init_chip(struct azx *chip, struct platform_device *pdev) 235 { 236 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip); 237 struct hdac_bus *bus = azx_bus(chip); 238 struct device *dev = hda->dev; 239 struct resource *res; 240 241 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 242 hda->regs = devm_ioremap_resource(dev, res); 243 if (IS_ERR(hda->regs)) 244 return PTR_ERR(hda->regs); 245 246 bus->remap_addr = hda->regs + HDA_BAR0; 247 bus->addr = res->start + HDA_BAR0; 248 249 hda_tegra_init(hda); 250 251 return 0; 252 } 253 254 static int hda_tegra_first_init(struct azx *chip, struct platform_device *pdev) 255 { 256 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip); 257 struct hdac_bus *bus = azx_bus(chip); 258 struct snd_card *card = chip->card; 259 int err; 260 unsigned short gcap; 261 int irq_id = platform_get_irq(pdev, 0); 262 const char *sname, *drv_name = "tegra-hda"; 263 struct device_node *np = pdev->dev.of_node; 264 265 err = hda_tegra_init_chip(chip, pdev); 266 if (err) 267 return err; 268 269 err = devm_request_irq(chip->card->dev, irq_id, azx_interrupt, 270 IRQF_SHARED, KBUILD_MODNAME, chip); 271 if (err) { 272 dev_err(chip->card->dev, 273 "unable to request IRQ %d, disabling device\n", 274 irq_id); 275 return err; 276 } 277 bus->irq = irq_id; 278 bus->dma_stop_delay = 100; 279 card->sync_irq = bus->irq; 280 281 /* 282 * Tegra194 has 4 SDO lines and the STRIPE can be used to 283 * indicate how many of the SDO lines the stream should be 284 * striped. But GCAP register does not reflect the true 285 * capability of HW. Below workaround helps to fix this. 286 * 287 * GCAP_NSDO is bits 19:18 in T_AZA_DBG_CFG_2, 288 * 0 for 1 SDO, 1 for 2 SDO, 2 for 4 SDO lines. 289 */ 290 if (of_device_is_compatible(np, "nvidia,tegra194-hda")) { 291 u32 val; 292 293 dev_info(card->dev, "Override SDO lines to %u\n", 294 TEGRA194_NUM_SDO_LINES); 295 296 val = readl(hda->regs + FPCI_DBG_CFG_2) & ~FPCI_GCAP_NSDO_MASK; 297 val |= (TEGRA194_NUM_SDO_LINES >> 1) << FPCI_GCAP_NSDO_SHIFT; 298 writel(val, hda->regs + FPCI_DBG_CFG_2); 299 } 300 301 gcap = azx_readw(chip, GCAP); 302 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap); 303 304 chip->align_buffer_size = 1; 305 306 /* read number of streams from GCAP register instead of using 307 * hardcoded value 308 */ 309 chip->capture_streams = (gcap >> 8) & 0x0f; 310 chip->playback_streams = (gcap >> 12) & 0x0f; 311 if (!chip->playback_streams && !chip->capture_streams) { 312 /* gcap didn't give any info, switching to old method */ 313 chip->playback_streams = NUM_PLAYBACK_SD; 314 chip->capture_streams = NUM_CAPTURE_SD; 315 } 316 chip->capture_index_offset = 0; 317 chip->playback_index_offset = chip->capture_streams; 318 chip->num_streams = chip->playback_streams + chip->capture_streams; 319 320 /* initialize streams */ 321 err = azx_init_streams(chip); 322 if (err < 0) { 323 dev_err(card->dev, "failed to initialize streams: %d\n", err); 324 return err; 325 } 326 327 err = azx_alloc_stream_pages(chip); 328 if (err < 0) { 329 dev_err(card->dev, "failed to allocate stream pages: %d\n", 330 err); 331 return err; 332 } 333 334 /* initialize chip */ 335 azx_init_chip(chip, 1); 336 337 /* 338 * Playback (for 44.1K/48K, 2-channel, 16-bps) fails with 339 * 4 SDO lines due to legacy design limitation. Following 340 * is, from HD Audio Specification (Revision 1.0a), used to 341 * control striping of the stream across multiple SDO lines 342 * for sample rates <= 48K. 343 * 344 * { ((num_channels * bits_per_sample) / number of SDOs) >= 8 } 345 * 346 * Due to legacy design issue it is recommended that above 347 * ratio must be greater than 8. Since number of SDO lines is 348 * in powers of 2, next available ratio is 16 which can be 349 * used as a limiting factor here. 350 */ 351 if (of_device_is_compatible(np, "nvidia,tegra30-hda")) 352 chip->bus.core.sdo_limit = 16; 353 354 /* codec detection */ 355 if (!bus->codec_mask) { 356 dev_err(card->dev, "no codecs found!\n"); 357 return -ENODEV; 358 } 359 360 /* driver name */ 361 strncpy(card->driver, drv_name, sizeof(card->driver)); 362 /* shortname for card */ 363 sname = of_get_property(np, "nvidia,model", NULL); 364 if (!sname) 365 sname = drv_name; 366 if (strlen(sname) > sizeof(card->shortname)) 367 dev_info(card->dev, "truncating shortname for card\n"); 368 strncpy(card->shortname, sname, sizeof(card->shortname)); 369 370 /* longname for card */ 371 snprintf(card->longname, sizeof(card->longname), 372 "%s at 0x%lx irq %i", 373 card->shortname, bus->addr, bus->irq); 374 375 return 0; 376 } 377 378 /* 379 * constructor 380 */ 381 382 static void hda_tegra_probe_work(struct work_struct *work); 383 384 static int hda_tegra_create(struct snd_card *card, 385 unsigned int driver_caps, 386 struct hda_tegra *hda) 387 { 388 static const struct snd_device_ops ops = { 389 .dev_disconnect = hda_tegra_dev_disconnect, 390 .dev_free = hda_tegra_dev_free, 391 }; 392 struct azx *chip; 393 int err; 394 395 chip = &hda->chip; 396 397 mutex_init(&chip->open_mutex); 398 chip->card = card; 399 chip->ops = &hda_tegra_ops; 400 chip->driver_caps = driver_caps; 401 chip->driver_type = driver_caps & 0xff; 402 chip->dev_index = 0; 403 INIT_LIST_HEAD(&chip->pcm_list); 404 405 chip->codec_probe_mask = -1; 406 407 chip->single_cmd = false; 408 chip->snoop = true; 409 410 INIT_WORK(&hda->probe_work, hda_tegra_probe_work); 411 412 err = azx_bus_init(chip, NULL); 413 if (err < 0) 414 return err; 415 416 chip->bus.core.sync_write = 0; 417 chip->bus.core.needs_damn_long_delay = 1; 418 chip->bus.core.aligned_mmio = 1; 419 420 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); 421 if (err < 0) { 422 dev_err(card->dev, "Error creating device\n"); 423 return err; 424 } 425 426 return 0; 427 } 428 429 static const struct of_device_id hda_tegra_match[] = { 430 { .compatible = "nvidia,tegra30-hda" }, 431 { .compatible = "nvidia,tegra194-hda" }, 432 {}, 433 }; 434 MODULE_DEVICE_TABLE(of, hda_tegra_match); 435 436 static int hda_tegra_probe(struct platform_device *pdev) 437 { 438 const unsigned int driver_flags = AZX_DCAPS_CORBRP_SELF_CLEAR | 439 AZX_DCAPS_PM_RUNTIME; 440 struct snd_card *card; 441 struct azx *chip; 442 struct hda_tegra *hda; 443 int err; 444 445 hda = devm_kzalloc(&pdev->dev, sizeof(*hda), GFP_KERNEL); 446 if (!hda) 447 return -ENOMEM; 448 hda->dev = &pdev->dev; 449 chip = &hda->chip; 450 451 err = snd_card_new(&pdev->dev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1, 452 THIS_MODULE, 0, &card); 453 if (err < 0) { 454 dev_err(&pdev->dev, "Error creating card!\n"); 455 return err; 456 } 457 458 hda->reset = devm_reset_control_array_get_exclusive(&pdev->dev); 459 if (IS_ERR(hda->reset)) { 460 err = PTR_ERR(hda->reset); 461 goto out_free; 462 } 463 464 hda->clocks[hda->nclocks++].id = "hda"; 465 hda->clocks[hda->nclocks++].id = "hda2hdmi"; 466 hda->clocks[hda->nclocks++].id = "hda2codec_2x"; 467 468 err = devm_clk_bulk_get(&pdev->dev, hda->nclocks, hda->clocks); 469 if (err < 0) 470 goto out_free; 471 472 err = hda_tegra_create(card, driver_flags, hda); 473 if (err < 0) 474 goto out_free; 475 card->private_data = chip; 476 477 dev_set_drvdata(&pdev->dev, card); 478 479 pm_runtime_enable(hda->dev); 480 if (!azx_has_pm_runtime(chip)) 481 pm_runtime_forbid(hda->dev); 482 483 schedule_work(&hda->probe_work); 484 485 return 0; 486 487 out_free: 488 snd_card_free(card); 489 return err; 490 } 491 492 static void hda_tegra_probe_work(struct work_struct *work) 493 { 494 struct hda_tegra *hda = container_of(work, struct hda_tegra, probe_work); 495 struct azx *chip = &hda->chip; 496 struct platform_device *pdev = to_platform_device(hda->dev); 497 int err; 498 499 pm_runtime_get_sync(hda->dev); 500 err = hda_tegra_first_init(chip, pdev); 501 if (err < 0) 502 goto out_free; 503 504 /* create codec instances */ 505 err = azx_probe_codecs(chip, 8); 506 if (err < 0) 507 goto out_free; 508 509 err = azx_codec_configure(chip); 510 if (err < 0) 511 goto out_free; 512 513 err = snd_card_register(chip->card); 514 if (err < 0) 515 goto out_free; 516 517 chip->running = 1; 518 snd_hda_set_power_save(&chip->bus, power_save * 1000); 519 520 out_free: 521 pm_runtime_put(hda->dev); 522 return; /* no error return from async probe */ 523 } 524 525 static int hda_tegra_remove(struct platform_device *pdev) 526 { 527 int ret; 528 529 ret = snd_card_free(dev_get_drvdata(&pdev->dev)); 530 pm_runtime_disable(&pdev->dev); 531 532 return ret; 533 } 534 535 static void hda_tegra_shutdown(struct platform_device *pdev) 536 { 537 struct snd_card *card = dev_get_drvdata(&pdev->dev); 538 struct azx *chip; 539 540 if (!card) 541 return; 542 chip = card->private_data; 543 if (chip && chip->running) 544 azx_stop_chip(chip); 545 } 546 547 static struct platform_driver tegra_platform_hda = { 548 .driver = { 549 .name = "tegra-hda", 550 .pm = &hda_tegra_pm, 551 .of_match_table = hda_tegra_match, 552 }, 553 .probe = hda_tegra_probe, 554 .remove = hda_tegra_remove, 555 .shutdown = hda_tegra_shutdown, 556 }; 557 module_platform_driver(tegra_platform_hda); 558 559 MODULE_DESCRIPTION("Tegra HDA bus driver"); 560 MODULE_LICENSE("GPL v2"); 561