1 /* 2 * 3 * hda_intel.c - Implementation of primary alsa driver code base 4 * for Intel HD Audio. 5 * 6 * Copyright(c) 2004 Intel Corporation. All rights reserved. 7 * 8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> 9 * PeiSen Hou <pshou@realtek.com.tw> 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the Free 13 * Software Foundation; either version 2 of the License, or (at your option) 14 * any later version. 15 * 16 * This program is distributed in the hope that it will be useful, but WITHOUT 17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 19 * more details. 20 * 21 * You should have received a copy of the GNU General Public License along with 22 * this program; if not, write to the Free Software Foundation, Inc., 59 23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA. 24 * 25 * CONTACTS: 26 * 27 * Matt Jared matt.jared@intel.com 28 * Andy Kopp andy.kopp@intel.com 29 * Dan Kogan dan.d.kogan@intel.com 30 * 31 * CHANGES: 32 * 33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou 34 * 35 */ 36 37 #include <linux/delay.h> 38 #include <linux/interrupt.h> 39 #include <linux/kernel.h> 40 #include <linux/module.h> 41 #include <linux/dma-mapping.h> 42 #include <linux/moduleparam.h> 43 #include <linux/init.h> 44 #include <linux/slab.h> 45 #include <linux/pci.h> 46 #include <linux/mutex.h> 47 #include <linux/reboot.h> 48 #include <linux/io.h> 49 #include <linux/pm_runtime.h> 50 #include <linux/clocksource.h> 51 #include <linux/time.h> 52 #include <linux/completion.h> 53 54 #ifdef CONFIG_X86 55 /* for snoop control */ 56 #include <asm/pgtable.h> 57 #include <asm/cacheflush.h> 58 #endif 59 #include <sound/core.h> 60 #include <sound/initval.h> 61 #include <linux/vgaarb.h> 62 #include <linux/vga_switcheroo.h> 63 #include <linux/firmware.h> 64 #include "hda_codec.h" 65 #include "hda_i915.h" 66 67 68 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; 69 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; 70 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; 71 static char *model[SNDRV_CARDS]; 72 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 73 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 74 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 75 static int probe_only[SNDRV_CARDS]; 76 static int jackpoll_ms[SNDRV_CARDS]; 77 static bool single_cmd; 78 static int enable_msi = -1; 79 #ifdef CONFIG_SND_HDA_PATCH_LOADER 80 static char *patch[SNDRV_CARDS]; 81 #endif 82 #ifdef CONFIG_SND_HDA_INPUT_BEEP 83 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = 84 CONFIG_SND_HDA_INPUT_BEEP_MODE}; 85 #endif 86 87 module_param_array(index, int, NULL, 0444); 88 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface."); 89 module_param_array(id, charp, NULL, 0444); 90 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface."); 91 module_param_array(enable, bool, NULL, 0444); 92 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface."); 93 module_param_array(model, charp, NULL, 0444); 94 MODULE_PARM_DESC(model, "Use the given board model."); 95 module_param_array(position_fix, int, NULL, 0444); 96 MODULE_PARM_DESC(position_fix, "DMA pointer read method." 97 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO)."); 98 module_param_array(bdl_pos_adj, int, NULL, 0644); 99 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset."); 100 module_param_array(probe_mask, int, NULL, 0444); 101 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1)."); 102 module_param_array(probe_only, int, NULL, 0444); 103 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization."); 104 module_param_array(jackpoll_ms, int, NULL, 0444); 105 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)"); 106 module_param(single_cmd, bool, 0444); 107 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs " 108 "(for debugging only)."); 109 module_param(enable_msi, bint, 0444); 110 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)"); 111 #ifdef CONFIG_SND_HDA_PATCH_LOADER 112 module_param_array(patch, charp, NULL, 0444); 113 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface."); 114 #endif 115 #ifdef CONFIG_SND_HDA_INPUT_BEEP 116 module_param_array(beep_mode, bool, NULL, 0444); 117 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode " 118 "(0=off, 1=on) (default=1)."); 119 #endif 120 121 #ifdef CONFIG_PM 122 static int param_set_xint(const char *val, const struct kernel_param *kp); 123 static struct kernel_param_ops param_ops_xint = { 124 .set = param_set_xint, 125 .get = param_get_int, 126 }; 127 #define param_check_xint param_check_int 128 129 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT; 130 module_param(power_save, xint, 0644); 131 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout " 132 "(in second, 0 = disable)."); 133 134 /* reset the HD-audio controller in power save mode. 135 * this may give more power-saving, but will take longer time to 136 * wake up. 137 */ 138 static bool power_save_controller = 1; 139 module_param(power_save_controller, bool, 0644); 140 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode."); 141 #endif /* CONFIG_PM */ 142 143 static int align_buffer_size = -1; 144 module_param(align_buffer_size, bint, 0644); 145 MODULE_PARM_DESC(align_buffer_size, 146 "Force buffer and period sizes to be multiple of 128 bytes."); 147 148 #ifdef CONFIG_X86 149 static bool hda_snoop = true; 150 module_param_named(snoop, hda_snoop, bool, 0444); 151 MODULE_PARM_DESC(snoop, "Enable/disable snooping"); 152 #define azx_snoop(chip) (chip)->snoop 153 #else 154 #define hda_snoop true 155 #define azx_snoop(chip) true 156 #endif 157 158 159 MODULE_LICENSE("GPL"); 160 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6}," 161 "{Intel, ICH6M}," 162 "{Intel, ICH7}," 163 "{Intel, ESB2}," 164 "{Intel, ICH8}," 165 "{Intel, ICH9}," 166 "{Intel, ICH10}," 167 "{Intel, PCH}," 168 "{Intel, CPT}," 169 "{Intel, PPT}," 170 "{Intel, LPT}," 171 "{Intel, LPT_LP}," 172 "{Intel, WPT_LP}," 173 "{Intel, HPT}," 174 "{Intel, PBG}," 175 "{Intel, SCH}," 176 "{ATI, SB450}," 177 "{ATI, SB600}," 178 "{ATI, RS600}," 179 "{ATI, RS690}," 180 "{ATI, RS780}," 181 "{ATI, R600}," 182 "{ATI, RV630}," 183 "{ATI, RV610}," 184 "{ATI, RV670}," 185 "{ATI, RV635}," 186 "{ATI, RV620}," 187 "{ATI, RV770}," 188 "{VIA, VT8251}," 189 "{VIA, VT8237A}," 190 "{SiS, SIS966}," 191 "{ULI, M5461}}"); 192 MODULE_DESCRIPTION("Intel HDA driver"); 193 194 #ifdef CONFIG_SND_VERBOSE_PRINTK 195 #define SFX /* nop */ 196 #else 197 #define SFX "hda-intel " 198 #endif 199 200 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO) 201 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI) 202 #define SUPPORT_VGA_SWITCHEROO 203 #endif 204 #endif 205 206 207 /* 208 * registers 209 */ 210 #define ICH6_REG_GCAP 0x00 211 #define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */ 212 #define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */ 213 #define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */ 214 #define ICH6_GCAP_ISS (15 << 8) /* # of input streams */ 215 #define ICH6_GCAP_OSS (15 << 12) /* # of output streams */ 216 #define ICH6_REG_VMIN 0x02 217 #define ICH6_REG_VMAJ 0x03 218 #define ICH6_REG_OUTPAY 0x04 219 #define ICH6_REG_INPAY 0x06 220 #define ICH6_REG_GCTL 0x08 221 #define ICH6_GCTL_RESET (1 << 0) /* controller reset */ 222 #define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */ 223 #define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */ 224 #define ICH6_REG_WAKEEN 0x0c 225 #define ICH6_REG_STATESTS 0x0e 226 #define ICH6_REG_GSTS 0x10 227 #define ICH6_GSTS_FSTS (1 << 1) /* flush status */ 228 #define ICH6_REG_INTCTL 0x20 229 #define ICH6_REG_INTSTS 0x24 230 #define ICH6_REG_WALLCLK 0x30 /* 24Mhz source */ 231 #define ICH6_REG_OLD_SSYNC 0x34 /* SSYNC for old ICH */ 232 #define ICH6_REG_SSYNC 0x38 233 #define ICH6_REG_CORBLBASE 0x40 234 #define ICH6_REG_CORBUBASE 0x44 235 #define ICH6_REG_CORBWP 0x48 236 #define ICH6_REG_CORBRP 0x4a 237 #define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */ 238 #define ICH6_REG_CORBCTL 0x4c 239 #define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */ 240 #define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */ 241 #define ICH6_REG_CORBSTS 0x4d 242 #define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */ 243 #define ICH6_REG_CORBSIZE 0x4e 244 245 #define ICH6_REG_RIRBLBASE 0x50 246 #define ICH6_REG_RIRBUBASE 0x54 247 #define ICH6_REG_RIRBWP 0x58 248 #define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */ 249 #define ICH6_REG_RINTCNT 0x5a 250 #define ICH6_REG_RIRBCTL 0x5c 251 #define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */ 252 #define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */ 253 #define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */ 254 #define ICH6_REG_RIRBSTS 0x5d 255 #define ICH6_RBSTS_IRQ (1 << 0) /* response irq */ 256 #define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */ 257 #define ICH6_REG_RIRBSIZE 0x5e 258 259 #define ICH6_REG_IC 0x60 260 #define ICH6_REG_IR 0x64 261 #define ICH6_REG_IRS 0x68 262 #define ICH6_IRS_VALID (1<<1) 263 #define ICH6_IRS_BUSY (1<<0) 264 265 #define ICH6_REG_DPLBASE 0x70 266 #define ICH6_REG_DPUBASE 0x74 267 #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */ 268 269 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */ 270 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 }; 271 272 /* stream register offsets from stream base */ 273 #define ICH6_REG_SD_CTL 0x00 274 #define ICH6_REG_SD_STS 0x03 275 #define ICH6_REG_SD_LPIB 0x04 276 #define ICH6_REG_SD_CBL 0x08 277 #define ICH6_REG_SD_LVI 0x0c 278 #define ICH6_REG_SD_FIFOW 0x0e 279 #define ICH6_REG_SD_FIFOSIZE 0x10 280 #define ICH6_REG_SD_FORMAT 0x12 281 #define ICH6_REG_SD_BDLPL 0x18 282 #define ICH6_REG_SD_BDLPU 0x1c 283 284 /* PCI space */ 285 #define ICH6_PCIREG_TCSEL 0x44 286 287 /* 288 * other constants 289 */ 290 291 /* max number of SDs */ 292 /* ICH, ATI and VIA have 4 playback and 4 capture */ 293 #define ICH6_NUM_CAPTURE 4 294 #define ICH6_NUM_PLAYBACK 4 295 296 /* ULI has 6 playback and 5 capture */ 297 #define ULI_NUM_CAPTURE 5 298 #define ULI_NUM_PLAYBACK 6 299 300 /* ATI HDMI may have up to 8 playbacks and 0 capture */ 301 #define ATIHDMI_NUM_CAPTURE 0 302 #define ATIHDMI_NUM_PLAYBACK 8 303 304 /* TERA has 4 playback and 3 capture */ 305 #define TERA_NUM_CAPTURE 3 306 #define TERA_NUM_PLAYBACK 4 307 308 /* this number is statically defined for simplicity */ 309 #define MAX_AZX_DEV 16 310 311 /* max number of fragments - we may use more if allocating more pages for BDL */ 312 #define BDL_SIZE 4096 313 #define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16) 314 #define AZX_MAX_FRAG 32 315 /* max buffer size - no h/w limit, you can increase as you like */ 316 #define AZX_MAX_BUF_SIZE (1024*1024*1024) 317 318 /* RIRB int mask: overrun[2], response[0] */ 319 #define RIRB_INT_RESPONSE 0x01 320 #define RIRB_INT_OVERRUN 0x04 321 #define RIRB_INT_MASK 0x05 322 323 /* STATESTS int mask: S3,SD2,SD1,SD0 */ 324 #define AZX_MAX_CODECS 8 325 #define AZX_DEFAULT_CODECS 4 326 #define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1) 327 328 /* SD_CTL bits */ 329 #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */ 330 #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */ 331 #define SD_CTL_STRIPE (3 << 16) /* stripe control */ 332 #define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */ 333 #define SD_CTL_DIR (1 << 19) /* bi-directional stream */ 334 #define SD_CTL_STREAM_TAG_MASK (0xf << 20) 335 #define SD_CTL_STREAM_TAG_SHIFT 20 336 337 /* SD_CTL and SD_STS */ 338 #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */ 339 #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */ 340 #define SD_INT_COMPLETE 0x04 /* completion interrupt */ 341 #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\ 342 SD_INT_COMPLETE) 343 344 /* SD_STS */ 345 #define SD_STS_FIFO_READY 0x20 /* FIFO ready */ 346 347 /* INTCTL and INTSTS */ 348 #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */ 349 #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */ 350 #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */ 351 352 /* below are so far hardcoded - should read registers in future */ 353 #define ICH6_MAX_CORB_ENTRIES 256 354 #define ICH6_MAX_RIRB_ENTRIES 256 355 356 /* position fix mode */ 357 enum { 358 POS_FIX_AUTO, 359 POS_FIX_LPIB, 360 POS_FIX_POSBUF, 361 POS_FIX_VIACOMBO, 362 POS_FIX_COMBO, 363 }; 364 365 /* Defines for ATI HD Audio support in SB450 south bridge */ 366 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42 367 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02 368 369 /* Defines for Nvidia HDA support */ 370 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e 371 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f 372 #define NVIDIA_HDA_ISTRM_COH 0x4d 373 #define NVIDIA_HDA_OSTRM_COH 0x4c 374 #define NVIDIA_HDA_ENABLE_COHBIT 0x01 375 376 /* Defines for Intel SCH HDA snoop control */ 377 #define INTEL_SCH_HDA_DEVC 0x78 378 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11) 379 380 /* Define IN stream 0 FIFO size offset in VIA controller */ 381 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90 382 /* Define VIA HD Audio Device ID*/ 383 #define VIA_HDAC_DEVICE_ID 0x3288 384 385 /* HD Audio class code */ 386 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403 387 388 /* 389 */ 390 391 struct azx_dev { 392 struct snd_dma_buffer bdl; /* BDL buffer */ 393 u32 *posbuf; /* position buffer pointer */ 394 395 unsigned int bufsize; /* size of the play buffer in bytes */ 396 unsigned int period_bytes; /* size of the period in bytes */ 397 unsigned int frags; /* number for period in the play buffer */ 398 unsigned int fifo_size; /* FIFO size */ 399 unsigned long start_wallclk; /* start + minimum wallclk */ 400 unsigned long period_wallclk; /* wallclk for period */ 401 402 void __iomem *sd_addr; /* stream descriptor pointer */ 403 404 u32 sd_int_sta_mask; /* stream int status mask */ 405 406 /* pcm support */ 407 struct snd_pcm_substream *substream; /* assigned substream, 408 * set in PCM open 409 */ 410 unsigned int format_val; /* format value to be set in the 411 * controller and the codec 412 */ 413 unsigned char stream_tag; /* assigned stream */ 414 unsigned char index; /* stream index */ 415 int assigned_key; /* last device# key assigned to */ 416 417 unsigned int opened :1; 418 unsigned int running :1; 419 unsigned int irq_pending :1; 420 unsigned int prepared:1; 421 unsigned int locked:1; 422 /* 423 * For VIA: 424 * A flag to ensure DMA position is 0 425 * when link position is not greater than FIFO size 426 */ 427 unsigned int insufficient :1; 428 unsigned int wc_marked:1; 429 unsigned int no_period_wakeup:1; 430 431 struct timecounter azx_tc; 432 struct cyclecounter azx_cc; 433 434 int delay_negative_threshold; 435 436 #ifdef CONFIG_SND_HDA_DSP_LOADER 437 struct mutex dsp_mutex; 438 #endif 439 }; 440 441 /* DSP lock helpers */ 442 #ifdef CONFIG_SND_HDA_DSP_LOADER 443 #define dsp_lock_init(dev) mutex_init(&(dev)->dsp_mutex) 444 #define dsp_lock(dev) mutex_lock(&(dev)->dsp_mutex) 445 #define dsp_unlock(dev) mutex_unlock(&(dev)->dsp_mutex) 446 #define dsp_is_locked(dev) ((dev)->locked) 447 #else 448 #define dsp_lock_init(dev) do {} while (0) 449 #define dsp_lock(dev) do {} while (0) 450 #define dsp_unlock(dev) do {} while (0) 451 #define dsp_is_locked(dev) 0 452 #endif 453 454 /* CORB/RIRB */ 455 struct azx_rb { 456 u32 *buf; /* CORB/RIRB buffer 457 * Each CORB entry is 4byte, RIRB is 8byte 458 */ 459 dma_addr_t addr; /* physical address of CORB/RIRB buffer */ 460 /* for RIRB */ 461 unsigned short rp, wp; /* read/write pointers */ 462 int cmds[AZX_MAX_CODECS]; /* number of pending requests */ 463 u32 res[AZX_MAX_CODECS]; /* last read value */ 464 }; 465 466 struct azx_pcm { 467 struct azx *chip; 468 struct snd_pcm *pcm; 469 struct hda_codec *codec; 470 struct hda_pcm_stream *hinfo[2]; 471 struct list_head list; 472 }; 473 474 struct azx { 475 struct snd_card *card; 476 struct pci_dev *pci; 477 int dev_index; 478 479 /* chip type specific */ 480 int driver_type; 481 unsigned int driver_caps; 482 int playback_streams; 483 int playback_index_offset; 484 int capture_streams; 485 int capture_index_offset; 486 int num_streams; 487 488 /* pci resources */ 489 unsigned long addr; 490 void __iomem *remap_addr; 491 int irq; 492 493 /* locks */ 494 spinlock_t reg_lock; 495 struct mutex open_mutex; 496 struct completion probe_wait; 497 498 /* streams (x num_streams) */ 499 struct azx_dev *azx_dev; 500 501 /* PCM */ 502 struct list_head pcm_list; /* azx_pcm list */ 503 504 /* HD codec */ 505 unsigned short codec_mask; 506 int codec_probe_mask; /* copied from probe_mask option */ 507 struct hda_bus *bus; 508 unsigned int beep_mode; 509 510 /* CORB/RIRB */ 511 struct azx_rb corb; 512 struct azx_rb rirb; 513 514 /* CORB/RIRB and position buffers */ 515 struct snd_dma_buffer rb; 516 struct snd_dma_buffer posbuf; 517 518 #ifdef CONFIG_SND_HDA_PATCH_LOADER 519 const struct firmware *fw; 520 #endif 521 522 /* flags */ 523 int position_fix[2]; /* for both playback/capture streams */ 524 int poll_count; 525 unsigned int running :1; 526 unsigned int initialized :1; 527 unsigned int single_cmd :1; 528 unsigned int polling_mode :1; 529 unsigned int msi :1; 530 unsigned int irq_pending_warned :1; 531 unsigned int probing :1; /* codec probing phase */ 532 unsigned int snoop:1; 533 unsigned int align_buffer_size:1; 534 unsigned int region_requested:1; 535 536 /* VGA-switcheroo setup */ 537 unsigned int use_vga_switcheroo:1; 538 unsigned int vga_switcheroo_registered:1; 539 unsigned int init_failed:1; /* delayed init failed */ 540 unsigned int disabled:1; /* disabled by VGA-switcher */ 541 542 /* for debugging */ 543 unsigned int last_cmd[AZX_MAX_CODECS]; 544 545 /* for pending irqs */ 546 struct work_struct irq_pending_work; 547 548 struct work_struct probe_work; 549 550 /* reboot notifier (for mysterious hangup problem at power-down) */ 551 struct notifier_block reboot_notifier; 552 553 /* card list (for power_save trigger) */ 554 struct list_head list; 555 556 #ifdef CONFIG_SND_HDA_DSP_LOADER 557 struct azx_dev saved_azx_dev; 558 #endif 559 560 /* secondary power domain for hdmi audio under vga device */ 561 struct dev_pm_domain hdmi_pm_domain; 562 }; 563 564 #define CREATE_TRACE_POINTS 565 #include "hda_intel_trace.h" 566 567 /* driver types */ 568 enum { 569 AZX_DRIVER_ICH, 570 AZX_DRIVER_PCH, 571 AZX_DRIVER_SCH, 572 AZX_DRIVER_HDMI, 573 AZX_DRIVER_ATI, 574 AZX_DRIVER_ATIHDMI, 575 AZX_DRIVER_ATIHDMI_NS, 576 AZX_DRIVER_VIA, 577 AZX_DRIVER_SIS, 578 AZX_DRIVER_ULI, 579 AZX_DRIVER_NVIDIA, 580 AZX_DRIVER_TERA, 581 AZX_DRIVER_CTX, 582 AZX_DRIVER_CTHDA, 583 AZX_DRIVER_GENERIC, 584 AZX_NUM_DRIVERS, /* keep this as last entry */ 585 }; 586 587 /* driver quirks (capabilities) */ 588 /* bits 0-7 are used for indicating driver type */ 589 #define AZX_DCAPS_NO_TCSEL (1 << 8) /* No Intel TCSEL bit */ 590 #define AZX_DCAPS_NO_MSI (1 << 9) /* No MSI support */ 591 #define AZX_DCAPS_ATI_SNOOP (1 << 10) /* ATI snoop enable */ 592 #define AZX_DCAPS_NVIDIA_SNOOP (1 << 11) /* Nvidia snoop enable */ 593 #define AZX_DCAPS_SCH_SNOOP (1 << 12) /* SCH/PCH snoop enable */ 594 #define AZX_DCAPS_RIRB_DELAY (1 << 13) /* Long delay in read loop */ 595 #define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14) /* Put a delay before read */ 596 #define AZX_DCAPS_CTX_WORKAROUND (1 << 15) /* X-Fi workaround */ 597 #define AZX_DCAPS_POSFIX_LPIB (1 << 16) /* Use LPIB as default */ 598 #define AZX_DCAPS_POSFIX_VIA (1 << 17) /* Use VIACOMBO as default */ 599 #define AZX_DCAPS_NO_64BIT (1 << 18) /* No 64bit address */ 600 #define AZX_DCAPS_SYNC_WRITE (1 << 19) /* sync each cmd write */ 601 #define AZX_DCAPS_OLD_SSYNC (1 << 20) /* Old SSYNC reg for ICH */ 602 #define AZX_DCAPS_BUFSIZE (1 << 21) /* no buffer size alignment */ 603 #define AZX_DCAPS_ALIGN_BUFSIZE (1 << 22) /* buffer size alignment */ 604 #define AZX_DCAPS_4K_BDLE_BOUNDARY (1 << 23) /* BDLE in 4k boundary */ 605 #define AZX_DCAPS_COUNT_LPIB_DELAY (1 << 25) /* Take LPIB as delay */ 606 #define AZX_DCAPS_PM_RUNTIME (1 << 26) /* runtime PM support */ 607 #define AZX_DCAPS_I915_POWERWELL (1 << 27) /* HSW i915 power well support */ 608 609 /* quirks for Intel PCH */ 610 #define AZX_DCAPS_INTEL_PCH_NOPM \ 611 (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_BUFSIZE | \ 612 AZX_DCAPS_COUNT_LPIB_DELAY) 613 614 #define AZX_DCAPS_INTEL_PCH \ 615 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME) 616 617 #define AZX_DCAPS_INTEL_HASWELL \ 618 (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_ALIGN_BUFSIZE | \ 619 AZX_DCAPS_COUNT_LPIB_DELAY | AZX_DCAPS_PM_RUNTIME | \ 620 AZX_DCAPS_I915_POWERWELL) 621 622 /* quirks for ATI SB / AMD Hudson */ 623 #define AZX_DCAPS_PRESET_ATI_SB \ 624 (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \ 625 AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB) 626 627 /* quirks for ATI/AMD HDMI */ 628 #define AZX_DCAPS_PRESET_ATI_HDMI \ 629 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB) 630 631 /* quirks for Nvidia */ 632 #define AZX_DCAPS_PRESET_NVIDIA \ 633 (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI |\ 634 AZX_DCAPS_ALIGN_BUFSIZE | AZX_DCAPS_NO_64BIT) 635 636 #define AZX_DCAPS_PRESET_CTHDA \ 637 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_4K_BDLE_BOUNDARY) 638 639 /* 640 * VGA-switcher support 641 */ 642 #ifdef SUPPORT_VGA_SWITCHEROO 643 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo) 644 #else 645 #define use_vga_switcheroo(chip) 0 646 #endif 647 648 static char *driver_short_names[] = { 649 [AZX_DRIVER_ICH] = "HDA Intel", 650 [AZX_DRIVER_PCH] = "HDA Intel PCH", 651 [AZX_DRIVER_SCH] = "HDA Intel MID", 652 [AZX_DRIVER_HDMI] = "HDA Intel HDMI", 653 [AZX_DRIVER_ATI] = "HDA ATI SB", 654 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI", 655 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI", 656 [AZX_DRIVER_VIA] = "HDA VIA VT82xx", 657 [AZX_DRIVER_SIS] = "HDA SIS966", 658 [AZX_DRIVER_ULI] = "HDA ULI M5461", 659 [AZX_DRIVER_NVIDIA] = "HDA NVidia", 660 [AZX_DRIVER_TERA] = "HDA Teradici", 661 [AZX_DRIVER_CTX] = "HDA Creative", 662 [AZX_DRIVER_CTHDA] = "HDA Creative", 663 [AZX_DRIVER_GENERIC] = "HD-Audio Generic", 664 }; 665 666 /* 667 * macros for easy use 668 */ 669 #define azx_writel(chip,reg,value) \ 670 writel(value, (chip)->remap_addr + ICH6_REG_##reg) 671 #define azx_readl(chip,reg) \ 672 readl((chip)->remap_addr + ICH6_REG_##reg) 673 #define azx_writew(chip,reg,value) \ 674 writew(value, (chip)->remap_addr + ICH6_REG_##reg) 675 #define azx_readw(chip,reg) \ 676 readw((chip)->remap_addr + ICH6_REG_##reg) 677 #define azx_writeb(chip,reg,value) \ 678 writeb(value, (chip)->remap_addr + ICH6_REG_##reg) 679 #define azx_readb(chip,reg) \ 680 readb((chip)->remap_addr + ICH6_REG_##reg) 681 682 #define azx_sd_writel(dev,reg,value) \ 683 writel(value, (dev)->sd_addr + ICH6_REG_##reg) 684 #define azx_sd_readl(dev,reg) \ 685 readl((dev)->sd_addr + ICH6_REG_##reg) 686 #define azx_sd_writew(dev,reg,value) \ 687 writew(value, (dev)->sd_addr + ICH6_REG_##reg) 688 #define azx_sd_readw(dev,reg) \ 689 readw((dev)->sd_addr + ICH6_REG_##reg) 690 #define azx_sd_writeb(dev,reg,value) \ 691 writeb(value, (dev)->sd_addr + ICH6_REG_##reg) 692 #define azx_sd_readb(dev,reg) \ 693 readb((dev)->sd_addr + ICH6_REG_##reg) 694 695 /* for pcm support */ 696 #define get_azx_dev(substream) (substream->runtime->private_data) 697 698 #ifdef CONFIG_X86 699 static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on) 700 { 701 int pages; 702 703 if (azx_snoop(chip)) 704 return; 705 if (!dmab || !dmab->area || !dmab->bytes) 706 return; 707 708 #ifdef CONFIG_SND_DMA_SGBUF 709 if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) { 710 struct snd_sg_buf *sgbuf = dmab->private_data; 711 if (on) 712 set_pages_array_wc(sgbuf->page_table, sgbuf->pages); 713 else 714 set_pages_array_wb(sgbuf->page_table, sgbuf->pages); 715 return; 716 } 717 #endif 718 719 pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT; 720 if (on) 721 set_memory_wc((unsigned long)dmab->area, pages); 722 else 723 set_memory_wb((unsigned long)dmab->area, pages); 724 } 725 726 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf, 727 bool on) 728 { 729 __mark_pages_wc(chip, buf, on); 730 } 731 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev, 732 struct snd_pcm_substream *substream, bool on) 733 { 734 if (azx_dev->wc_marked != on) { 735 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on); 736 azx_dev->wc_marked = on; 737 } 738 } 739 #else 740 /* NOP for other archs */ 741 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf, 742 bool on) 743 { 744 } 745 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev, 746 struct snd_pcm_substream *substream, bool on) 747 { 748 } 749 #endif 750 751 static int azx_acquire_irq(struct azx *chip, int do_disconnect); 752 static int azx_send_cmd(struct hda_bus *bus, unsigned int val); 753 /* 754 * Interface for HD codec 755 */ 756 757 /* 758 * CORB / RIRB interface 759 */ 760 static int azx_alloc_cmd_io(struct azx *chip) 761 { 762 int err; 763 764 /* single page (at least 4096 bytes) must suffice for both ringbuffes */ 765 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, 766 snd_dma_pci_data(chip->pci), 767 PAGE_SIZE, &chip->rb); 768 if (err < 0) { 769 snd_printk(KERN_ERR SFX "%s: cannot allocate CORB/RIRB\n", pci_name(chip->pci)); 770 return err; 771 } 772 mark_pages_wc(chip, &chip->rb, true); 773 return 0; 774 } 775 776 static void azx_init_cmd_io(struct azx *chip) 777 { 778 spin_lock_irq(&chip->reg_lock); 779 /* CORB set up */ 780 chip->corb.addr = chip->rb.addr; 781 chip->corb.buf = (u32 *)chip->rb.area; 782 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr); 783 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr)); 784 785 /* set the corb size to 256 entries (ULI requires explicitly) */ 786 azx_writeb(chip, CORBSIZE, 0x02); 787 /* set the corb write pointer to 0 */ 788 azx_writew(chip, CORBWP, 0); 789 /* reset the corb hw read pointer */ 790 azx_writew(chip, CORBRP, ICH6_CORBRP_RST); 791 /* enable corb dma */ 792 azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN); 793 794 /* RIRB set up */ 795 chip->rirb.addr = chip->rb.addr + 2048; 796 chip->rirb.buf = (u32 *)(chip->rb.area + 2048); 797 chip->rirb.wp = chip->rirb.rp = 0; 798 memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds)); 799 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr); 800 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr)); 801 802 /* set the rirb size to 256 entries (ULI requires explicitly) */ 803 azx_writeb(chip, RIRBSIZE, 0x02); 804 /* reset the rirb hw write pointer */ 805 azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST); 806 /* set N=1, get RIRB response interrupt for new entry */ 807 if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) 808 azx_writew(chip, RINTCNT, 0xc0); 809 else 810 azx_writew(chip, RINTCNT, 1); 811 /* enable rirb dma and response irq */ 812 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN); 813 spin_unlock_irq(&chip->reg_lock); 814 } 815 816 static void azx_free_cmd_io(struct azx *chip) 817 { 818 spin_lock_irq(&chip->reg_lock); 819 /* disable ringbuffer DMAs */ 820 azx_writeb(chip, RIRBCTL, 0); 821 azx_writeb(chip, CORBCTL, 0); 822 spin_unlock_irq(&chip->reg_lock); 823 } 824 825 static unsigned int azx_command_addr(u32 cmd) 826 { 827 unsigned int addr = cmd >> 28; 828 829 if (addr >= AZX_MAX_CODECS) { 830 snd_BUG(); 831 addr = 0; 832 } 833 834 return addr; 835 } 836 837 /* send a command */ 838 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val) 839 { 840 struct azx *chip = bus->private_data; 841 unsigned int addr = azx_command_addr(val); 842 unsigned int wp, rp; 843 844 spin_lock_irq(&chip->reg_lock); 845 846 /* add command to corb */ 847 wp = azx_readw(chip, CORBWP); 848 if (wp == 0xffff) { 849 /* something wrong, controller likely turned to D3 */ 850 spin_unlock_irq(&chip->reg_lock); 851 return -EIO; 852 } 853 wp++; 854 wp %= ICH6_MAX_CORB_ENTRIES; 855 856 rp = azx_readw(chip, CORBRP); 857 if (wp == rp) { 858 /* oops, it's full */ 859 spin_unlock_irq(&chip->reg_lock); 860 return -EAGAIN; 861 } 862 863 chip->rirb.cmds[addr]++; 864 chip->corb.buf[wp] = cpu_to_le32(val); 865 azx_writel(chip, CORBWP, wp); 866 867 spin_unlock_irq(&chip->reg_lock); 868 869 return 0; 870 } 871 872 #define ICH6_RIRB_EX_UNSOL_EV (1<<4) 873 874 /* retrieve RIRB entry - called from interrupt handler */ 875 static void azx_update_rirb(struct azx *chip) 876 { 877 unsigned int rp, wp; 878 unsigned int addr; 879 u32 res, res_ex; 880 881 wp = azx_readw(chip, RIRBWP); 882 if (wp == 0xffff) { 883 /* something wrong, controller likely turned to D3 */ 884 return; 885 } 886 887 if (wp == chip->rirb.wp) 888 return; 889 chip->rirb.wp = wp; 890 891 while (chip->rirb.rp != wp) { 892 chip->rirb.rp++; 893 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES; 894 895 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */ 896 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]); 897 res = le32_to_cpu(chip->rirb.buf[rp]); 898 addr = res_ex & 0xf; 899 if ((addr >= AZX_MAX_CODECS) || !(chip->codec_mask & (1 << addr))) { 900 snd_printk(KERN_ERR SFX "%s: spurious response %#x:%#x, rp = %d, wp = %d", 901 pci_name(chip->pci), 902 res, res_ex, 903 chip->rirb.rp, wp); 904 snd_BUG(); 905 } 906 else if (res_ex & ICH6_RIRB_EX_UNSOL_EV) 907 snd_hda_queue_unsol_event(chip->bus, res, res_ex); 908 else if (chip->rirb.cmds[addr]) { 909 chip->rirb.res[addr] = res; 910 smp_wmb(); 911 chip->rirb.cmds[addr]--; 912 } else if (printk_ratelimit()) { 913 snd_printk(KERN_ERR SFX "%s: spurious response %#x:%#x, last cmd=%#08x\n", 914 pci_name(chip->pci), 915 res, res_ex, 916 chip->last_cmd[addr]); 917 } 918 } 919 } 920 921 /* receive a response */ 922 static unsigned int azx_rirb_get_response(struct hda_bus *bus, 923 unsigned int addr) 924 { 925 struct azx *chip = bus->private_data; 926 unsigned long timeout; 927 unsigned long loopcounter; 928 int do_poll = 0; 929 930 again: 931 timeout = jiffies + msecs_to_jiffies(1000); 932 933 for (loopcounter = 0;; loopcounter++) { 934 if (chip->polling_mode || do_poll) { 935 spin_lock_irq(&chip->reg_lock); 936 azx_update_rirb(chip); 937 spin_unlock_irq(&chip->reg_lock); 938 } 939 if (!chip->rirb.cmds[addr]) { 940 smp_rmb(); 941 bus->rirb_error = 0; 942 943 if (!do_poll) 944 chip->poll_count = 0; 945 return chip->rirb.res[addr]; /* the last value */ 946 } 947 if (time_after(jiffies, timeout)) 948 break; 949 if (bus->needs_damn_long_delay || loopcounter > 3000) 950 msleep(2); /* temporary workaround */ 951 else { 952 udelay(10); 953 cond_resched(); 954 } 955 } 956 957 if (!bus->no_response_fallback) 958 return -1; 959 960 if (!chip->polling_mode && chip->poll_count < 2) { 961 snd_printdd(SFX "%s: azx_get_response timeout, " 962 "polling the codec once: last cmd=0x%08x\n", 963 pci_name(chip->pci), chip->last_cmd[addr]); 964 do_poll = 1; 965 chip->poll_count++; 966 goto again; 967 } 968 969 970 if (!chip->polling_mode) { 971 snd_printk(KERN_WARNING SFX "%s: azx_get_response timeout, " 972 "switching to polling mode: last cmd=0x%08x\n", 973 pci_name(chip->pci), chip->last_cmd[addr]); 974 chip->polling_mode = 1; 975 goto again; 976 } 977 978 if (chip->msi) { 979 snd_printk(KERN_WARNING SFX "%s: No response from codec, " 980 "disabling MSI: last cmd=0x%08x\n", 981 pci_name(chip->pci), chip->last_cmd[addr]); 982 free_irq(chip->irq, chip); 983 chip->irq = -1; 984 pci_disable_msi(chip->pci); 985 chip->msi = 0; 986 if (azx_acquire_irq(chip, 1) < 0) { 987 bus->rirb_error = 1; 988 return -1; 989 } 990 goto again; 991 } 992 993 if (chip->probing) { 994 /* If this critical timeout happens during the codec probing 995 * phase, this is likely an access to a non-existing codec 996 * slot. Better to return an error and reset the system. 997 */ 998 return -1; 999 } 1000 1001 /* a fatal communication error; need either to reset or to fallback 1002 * to the single_cmd mode 1003 */ 1004 bus->rirb_error = 1; 1005 if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) { 1006 bus->response_reset = 1; 1007 return -1; /* give a chance to retry */ 1008 } 1009 1010 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, " 1011 "switching to single_cmd mode: last cmd=0x%08x\n", 1012 chip->last_cmd[addr]); 1013 chip->single_cmd = 1; 1014 bus->response_reset = 0; 1015 /* release CORB/RIRB */ 1016 azx_free_cmd_io(chip); 1017 /* disable unsolicited responses */ 1018 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL); 1019 return -1; 1020 } 1021 1022 /* 1023 * Use the single immediate command instead of CORB/RIRB for simplicity 1024 * 1025 * Note: according to Intel, this is not preferred use. The command was 1026 * intended for the BIOS only, and may get confused with unsolicited 1027 * responses. So, we shouldn't use it for normal operation from the 1028 * driver. 1029 * I left the codes, however, for debugging/testing purposes. 1030 */ 1031 1032 /* receive a response */ 1033 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr) 1034 { 1035 int timeout = 50; 1036 1037 while (timeout--) { 1038 /* check IRV busy bit */ 1039 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) { 1040 /* reuse rirb.res as the response return value */ 1041 chip->rirb.res[addr] = azx_readl(chip, IR); 1042 return 0; 1043 } 1044 udelay(1); 1045 } 1046 if (printk_ratelimit()) 1047 snd_printd(SFX "%s: get_response timeout: IRS=0x%x\n", 1048 pci_name(chip->pci), azx_readw(chip, IRS)); 1049 chip->rirb.res[addr] = -1; 1050 return -EIO; 1051 } 1052 1053 /* send a command */ 1054 static int azx_single_send_cmd(struct hda_bus *bus, u32 val) 1055 { 1056 struct azx *chip = bus->private_data; 1057 unsigned int addr = azx_command_addr(val); 1058 int timeout = 50; 1059 1060 bus->rirb_error = 0; 1061 while (timeout--) { 1062 /* check ICB busy bit */ 1063 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) { 1064 /* Clear IRV valid bit */ 1065 azx_writew(chip, IRS, azx_readw(chip, IRS) | 1066 ICH6_IRS_VALID); 1067 azx_writel(chip, IC, val); 1068 azx_writew(chip, IRS, azx_readw(chip, IRS) | 1069 ICH6_IRS_BUSY); 1070 return azx_single_wait_for_response(chip, addr); 1071 } 1072 udelay(1); 1073 } 1074 if (printk_ratelimit()) 1075 snd_printd(SFX "%s: send_cmd timeout: IRS=0x%x, val=0x%x\n", 1076 pci_name(chip->pci), azx_readw(chip, IRS), val); 1077 return -EIO; 1078 } 1079 1080 /* receive a response */ 1081 static unsigned int azx_single_get_response(struct hda_bus *bus, 1082 unsigned int addr) 1083 { 1084 struct azx *chip = bus->private_data; 1085 return chip->rirb.res[addr]; 1086 } 1087 1088 /* 1089 * The below are the main callbacks from hda_codec. 1090 * 1091 * They are just the skeleton to call sub-callbacks according to the 1092 * current setting of chip->single_cmd. 1093 */ 1094 1095 /* send a command */ 1096 static int azx_send_cmd(struct hda_bus *bus, unsigned int val) 1097 { 1098 struct azx *chip = bus->private_data; 1099 1100 if (chip->disabled) 1101 return 0; 1102 chip->last_cmd[azx_command_addr(val)] = val; 1103 if (chip->single_cmd) 1104 return azx_single_send_cmd(bus, val); 1105 else 1106 return azx_corb_send_cmd(bus, val); 1107 } 1108 1109 /* get a response */ 1110 static unsigned int azx_get_response(struct hda_bus *bus, 1111 unsigned int addr) 1112 { 1113 struct azx *chip = bus->private_data; 1114 if (chip->disabled) 1115 return 0; 1116 if (chip->single_cmd) 1117 return azx_single_get_response(bus, addr); 1118 else 1119 return azx_rirb_get_response(bus, addr); 1120 } 1121 1122 #ifdef CONFIG_PM 1123 static void azx_power_notify(struct hda_bus *bus, bool power_up); 1124 #endif 1125 1126 #ifdef CONFIG_SND_HDA_DSP_LOADER 1127 static int azx_load_dsp_prepare(struct hda_bus *bus, unsigned int format, 1128 unsigned int byte_size, 1129 struct snd_dma_buffer *bufp); 1130 static void azx_load_dsp_trigger(struct hda_bus *bus, bool start); 1131 static void azx_load_dsp_cleanup(struct hda_bus *bus, 1132 struct snd_dma_buffer *dmab); 1133 #endif 1134 1135 /* enter link reset */ 1136 static void azx_enter_link_reset(struct azx *chip) 1137 { 1138 unsigned long timeout; 1139 1140 /* reset controller */ 1141 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET); 1142 1143 timeout = jiffies + msecs_to_jiffies(100); 1144 while ((azx_readb(chip, GCTL) & ICH6_GCTL_RESET) && 1145 time_before(jiffies, timeout)) 1146 usleep_range(500, 1000); 1147 } 1148 1149 /* exit link reset */ 1150 static void azx_exit_link_reset(struct azx *chip) 1151 { 1152 unsigned long timeout; 1153 1154 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET); 1155 1156 timeout = jiffies + msecs_to_jiffies(100); 1157 while (!azx_readb(chip, GCTL) && 1158 time_before(jiffies, timeout)) 1159 usleep_range(500, 1000); 1160 } 1161 1162 /* reset codec link */ 1163 static int azx_reset(struct azx *chip, int full_reset) 1164 { 1165 if (!full_reset) 1166 goto __skip; 1167 1168 /* clear STATESTS */ 1169 azx_writew(chip, STATESTS, STATESTS_INT_MASK); 1170 1171 /* reset controller */ 1172 azx_enter_link_reset(chip); 1173 1174 /* delay for >= 100us for codec PLL to settle per spec 1175 * Rev 0.9 section 5.5.1 1176 */ 1177 usleep_range(500, 1000); 1178 1179 /* Bring controller out of reset */ 1180 azx_exit_link_reset(chip); 1181 1182 /* Brent Chartrand said to wait >= 540us for codecs to initialize */ 1183 usleep_range(1000, 1200); 1184 1185 __skip: 1186 /* check to see if controller is ready */ 1187 if (!azx_readb(chip, GCTL)) { 1188 snd_printd(SFX "%s: azx_reset: controller not ready!\n", pci_name(chip->pci)); 1189 return -EBUSY; 1190 } 1191 1192 /* Accept unsolicited responses */ 1193 if (!chip->single_cmd) 1194 azx_writel(chip, GCTL, azx_readl(chip, GCTL) | 1195 ICH6_GCTL_UNSOL); 1196 1197 /* detect codecs */ 1198 if (!chip->codec_mask) { 1199 chip->codec_mask = azx_readw(chip, STATESTS); 1200 snd_printdd(SFX "%s: codec_mask = 0x%x\n", pci_name(chip->pci), chip->codec_mask); 1201 } 1202 1203 return 0; 1204 } 1205 1206 1207 /* 1208 * Lowlevel interface 1209 */ 1210 1211 /* enable interrupts */ 1212 static void azx_int_enable(struct azx *chip) 1213 { 1214 /* enable controller CIE and GIE */ 1215 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) | 1216 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN); 1217 } 1218 1219 /* disable interrupts */ 1220 static void azx_int_disable(struct azx *chip) 1221 { 1222 int i; 1223 1224 /* disable interrupts in stream descriptor */ 1225 for (i = 0; i < chip->num_streams; i++) { 1226 struct azx_dev *azx_dev = &chip->azx_dev[i]; 1227 azx_sd_writeb(azx_dev, SD_CTL, 1228 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK); 1229 } 1230 1231 /* disable SIE for all streams */ 1232 azx_writeb(chip, INTCTL, 0); 1233 1234 /* disable controller CIE and GIE */ 1235 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) & 1236 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN)); 1237 } 1238 1239 /* clear interrupts */ 1240 static void azx_int_clear(struct azx *chip) 1241 { 1242 int i; 1243 1244 /* clear stream status */ 1245 for (i = 0; i < chip->num_streams; i++) { 1246 struct azx_dev *azx_dev = &chip->azx_dev[i]; 1247 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); 1248 } 1249 1250 /* clear STATESTS */ 1251 azx_writew(chip, STATESTS, STATESTS_INT_MASK); 1252 1253 /* clear rirb status */ 1254 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK); 1255 1256 /* clear int status */ 1257 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM); 1258 } 1259 1260 /* start a stream */ 1261 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev) 1262 { 1263 /* 1264 * Before stream start, initialize parameter 1265 */ 1266 azx_dev->insufficient = 1; 1267 1268 /* enable SIE */ 1269 azx_writel(chip, INTCTL, 1270 azx_readl(chip, INTCTL) | (1 << azx_dev->index)); 1271 /* set DMA start and interrupt mask */ 1272 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) | 1273 SD_CTL_DMA_START | SD_INT_MASK); 1274 } 1275 1276 /* stop DMA */ 1277 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev) 1278 { 1279 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) & 1280 ~(SD_CTL_DMA_START | SD_INT_MASK)); 1281 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */ 1282 } 1283 1284 /* stop a stream */ 1285 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev) 1286 { 1287 azx_stream_clear(chip, azx_dev); 1288 /* disable SIE */ 1289 azx_writel(chip, INTCTL, 1290 azx_readl(chip, INTCTL) & ~(1 << azx_dev->index)); 1291 } 1292 1293 1294 /* 1295 * reset and start the controller registers 1296 */ 1297 static void azx_init_chip(struct azx *chip, int full_reset) 1298 { 1299 if (chip->initialized) 1300 return; 1301 1302 /* reset controller */ 1303 azx_reset(chip, full_reset); 1304 1305 /* initialize interrupts */ 1306 azx_int_clear(chip); 1307 azx_int_enable(chip); 1308 1309 /* initialize the codec command I/O */ 1310 if (!chip->single_cmd) 1311 azx_init_cmd_io(chip); 1312 1313 /* program the position buffer */ 1314 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr); 1315 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr)); 1316 1317 chip->initialized = 1; 1318 } 1319 1320 /* 1321 * initialize the PCI registers 1322 */ 1323 /* update bits in a PCI register byte */ 1324 static void update_pci_byte(struct pci_dev *pci, unsigned int reg, 1325 unsigned char mask, unsigned char val) 1326 { 1327 unsigned char data; 1328 1329 pci_read_config_byte(pci, reg, &data); 1330 data &= ~mask; 1331 data |= (val & mask); 1332 pci_write_config_byte(pci, reg, data); 1333 } 1334 1335 static void azx_init_pci(struct azx *chip) 1336 { 1337 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44) 1338 * TCSEL == Traffic Class Select Register, which sets PCI express QOS 1339 * Ensuring these bits are 0 clears playback static on some HD Audio 1340 * codecs. 1341 * The PCI register TCSEL is defined in the Intel manuals. 1342 */ 1343 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) { 1344 snd_printdd(SFX "%s: Clearing TCSEL\n", pci_name(chip->pci)); 1345 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0); 1346 } 1347 1348 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio, 1349 * we need to enable snoop. 1350 */ 1351 if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) { 1352 snd_printdd(SFX "%s: Setting ATI snoop: %d\n", pci_name(chip->pci), azx_snoop(chip)); 1353 update_pci_byte(chip->pci, 1354 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07, 1355 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0); 1356 } 1357 1358 /* For NVIDIA HDA, enable snoop */ 1359 if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) { 1360 snd_printdd(SFX "%s: Setting Nvidia snoop: %d\n", pci_name(chip->pci), azx_snoop(chip)); 1361 update_pci_byte(chip->pci, 1362 NVIDIA_HDA_TRANSREG_ADDR, 1363 0x0f, NVIDIA_HDA_ENABLE_COHBITS); 1364 update_pci_byte(chip->pci, 1365 NVIDIA_HDA_ISTRM_COH, 1366 0x01, NVIDIA_HDA_ENABLE_COHBIT); 1367 update_pci_byte(chip->pci, 1368 NVIDIA_HDA_OSTRM_COH, 1369 0x01, NVIDIA_HDA_ENABLE_COHBIT); 1370 } 1371 1372 /* Enable SCH/PCH snoop if needed */ 1373 if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) { 1374 unsigned short snoop; 1375 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop); 1376 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) || 1377 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) { 1378 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP; 1379 if (!azx_snoop(chip)) 1380 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP; 1381 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop); 1382 pci_read_config_word(chip->pci, 1383 INTEL_SCH_HDA_DEVC, &snoop); 1384 } 1385 snd_printdd(SFX "%s: SCH snoop: %s\n", 1386 pci_name(chip->pci), (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) 1387 ? "Disabled" : "Enabled"); 1388 } 1389 } 1390 1391 1392 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev); 1393 1394 /* 1395 * interrupt handler 1396 */ 1397 static irqreturn_t azx_interrupt(int irq, void *dev_id) 1398 { 1399 struct azx *chip = dev_id; 1400 struct azx_dev *azx_dev; 1401 u32 status; 1402 u8 sd_status; 1403 int i, ok; 1404 1405 #ifdef CONFIG_PM_RUNTIME 1406 if (chip->driver_caps & AZX_DCAPS_PM_RUNTIME) 1407 if (chip->pci->dev.power.runtime_status != RPM_ACTIVE) 1408 return IRQ_NONE; 1409 #endif 1410 1411 spin_lock(&chip->reg_lock); 1412 1413 if (chip->disabled) { 1414 spin_unlock(&chip->reg_lock); 1415 return IRQ_NONE; 1416 } 1417 1418 status = azx_readl(chip, INTSTS); 1419 if (status == 0 || status == 0xffffffff) { 1420 spin_unlock(&chip->reg_lock); 1421 return IRQ_NONE; 1422 } 1423 1424 for (i = 0; i < chip->num_streams; i++) { 1425 azx_dev = &chip->azx_dev[i]; 1426 if (status & azx_dev->sd_int_sta_mask) { 1427 sd_status = azx_sd_readb(azx_dev, SD_STS); 1428 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); 1429 if (!azx_dev->substream || !azx_dev->running || 1430 !(sd_status & SD_INT_COMPLETE)) 1431 continue; 1432 /* check whether this IRQ is really acceptable */ 1433 ok = azx_position_ok(chip, azx_dev); 1434 if (ok == 1) { 1435 azx_dev->irq_pending = 0; 1436 spin_unlock(&chip->reg_lock); 1437 snd_pcm_period_elapsed(azx_dev->substream); 1438 spin_lock(&chip->reg_lock); 1439 } else if (ok == 0 && chip->bus && chip->bus->workq) { 1440 /* bogus IRQ, process it later */ 1441 azx_dev->irq_pending = 1; 1442 queue_work(chip->bus->workq, 1443 &chip->irq_pending_work); 1444 } 1445 } 1446 } 1447 1448 /* clear rirb int */ 1449 status = azx_readb(chip, RIRBSTS); 1450 if (status & RIRB_INT_MASK) { 1451 if (status & RIRB_INT_RESPONSE) { 1452 if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY) 1453 udelay(80); 1454 azx_update_rirb(chip); 1455 } 1456 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK); 1457 } 1458 1459 #if 0 1460 /* clear state status int */ 1461 if (azx_readw(chip, STATESTS) & 0x04) 1462 azx_writew(chip, STATESTS, 0x04); 1463 #endif 1464 spin_unlock(&chip->reg_lock); 1465 1466 return IRQ_HANDLED; 1467 } 1468 1469 1470 /* 1471 * set up a BDL entry 1472 */ 1473 static int setup_bdle(struct azx *chip, 1474 struct snd_dma_buffer *dmab, 1475 struct azx_dev *azx_dev, u32 **bdlp, 1476 int ofs, int size, int with_ioc) 1477 { 1478 u32 *bdl = *bdlp; 1479 1480 while (size > 0) { 1481 dma_addr_t addr; 1482 int chunk; 1483 1484 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES) 1485 return -EINVAL; 1486 1487 addr = snd_sgbuf_get_addr(dmab, ofs); 1488 /* program the address field of the BDL entry */ 1489 bdl[0] = cpu_to_le32((u32)addr); 1490 bdl[1] = cpu_to_le32(upper_32_bits(addr)); 1491 /* program the size field of the BDL entry */ 1492 chunk = snd_sgbuf_get_chunk_size(dmab, ofs, size); 1493 /* one BDLE cannot cross 4K boundary on CTHDA chips */ 1494 if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY) { 1495 u32 remain = 0x1000 - (ofs & 0xfff); 1496 if (chunk > remain) 1497 chunk = remain; 1498 } 1499 bdl[2] = cpu_to_le32(chunk); 1500 /* program the IOC to enable interrupt 1501 * only when the whole fragment is processed 1502 */ 1503 size -= chunk; 1504 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01); 1505 bdl += 4; 1506 azx_dev->frags++; 1507 ofs += chunk; 1508 } 1509 *bdlp = bdl; 1510 return ofs; 1511 } 1512 1513 /* 1514 * set up BDL entries 1515 */ 1516 static int azx_setup_periods(struct azx *chip, 1517 struct snd_pcm_substream *substream, 1518 struct azx_dev *azx_dev) 1519 { 1520 u32 *bdl; 1521 int i, ofs, periods, period_bytes; 1522 int pos_adj; 1523 1524 /* reset BDL address */ 1525 azx_sd_writel(azx_dev, SD_BDLPL, 0); 1526 azx_sd_writel(azx_dev, SD_BDLPU, 0); 1527 1528 period_bytes = azx_dev->period_bytes; 1529 periods = azx_dev->bufsize / period_bytes; 1530 1531 /* program the initial BDL entries */ 1532 bdl = (u32 *)azx_dev->bdl.area; 1533 ofs = 0; 1534 azx_dev->frags = 0; 1535 pos_adj = bdl_pos_adj[chip->dev_index]; 1536 if (!azx_dev->no_period_wakeup && pos_adj > 0) { 1537 struct snd_pcm_runtime *runtime = substream->runtime; 1538 int pos_align = pos_adj; 1539 pos_adj = (pos_adj * runtime->rate + 47999) / 48000; 1540 if (!pos_adj) 1541 pos_adj = pos_align; 1542 else 1543 pos_adj = ((pos_adj + pos_align - 1) / pos_align) * 1544 pos_align; 1545 pos_adj = frames_to_bytes(runtime, pos_adj); 1546 if (pos_adj >= period_bytes) { 1547 snd_printk(KERN_WARNING SFX "%s: Too big adjustment %d\n", 1548 pci_name(chip->pci), bdl_pos_adj[chip->dev_index]); 1549 pos_adj = 0; 1550 } else { 1551 ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream), 1552 azx_dev, 1553 &bdl, ofs, pos_adj, true); 1554 if (ofs < 0) 1555 goto error; 1556 } 1557 } else 1558 pos_adj = 0; 1559 for (i = 0; i < periods; i++) { 1560 if (i == periods - 1 && pos_adj) 1561 ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream), 1562 azx_dev, &bdl, ofs, 1563 period_bytes - pos_adj, 0); 1564 else 1565 ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream), 1566 azx_dev, &bdl, ofs, 1567 period_bytes, 1568 !azx_dev->no_period_wakeup); 1569 if (ofs < 0) 1570 goto error; 1571 } 1572 return 0; 1573 1574 error: 1575 snd_printk(KERN_ERR SFX "%s: Too many BDL entries: buffer=%d, period=%d\n", 1576 pci_name(chip->pci), azx_dev->bufsize, period_bytes); 1577 return -EINVAL; 1578 } 1579 1580 /* reset stream */ 1581 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev) 1582 { 1583 unsigned char val; 1584 int timeout; 1585 1586 azx_stream_clear(chip, azx_dev); 1587 1588 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) | 1589 SD_CTL_STREAM_RESET); 1590 udelay(3); 1591 timeout = 300; 1592 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) && 1593 --timeout) 1594 ; 1595 val &= ~SD_CTL_STREAM_RESET; 1596 azx_sd_writeb(azx_dev, SD_CTL, val); 1597 udelay(3); 1598 1599 timeout = 300; 1600 /* waiting for hardware to report that the stream is out of reset */ 1601 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) && 1602 --timeout) 1603 ; 1604 1605 /* reset first position - may not be synced with hw at this time */ 1606 *azx_dev->posbuf = 0; 1607 } 1608 1609 /* 1610 * set up the SD for streaming 1611 */ 1612 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev) 1613 { 1614 unsigned int val; 1615 /* make sure the run bit is zero for SD */ 1616 azx_stream_clear(chip, azx_dev); 1617 /* program the stream_tag */ 1618 val = azx_sd_readl(azx_dev, SD_CTL); 1619 val = (val & ~SD_CTL_STREAM_TAG_MASK) | 1620 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT); 1621 if (!azx_snoop(chip)) 1622 val |= SD_CTL_TRAFFIC_PRIO; 1623 azx_sd_writel(azx_dev, SD_CTL, val); 1624 1625 /* program the length of samples in cyclic buffer */ 1626 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize); 1627 1628 /* program the stream format */ 1629 /* this value needs to be the same as the one programmed */ 1630 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val); 1631 1632 /* program the stream LVI (last valid index) of the BDL */ 1633 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1); 1634 1635 /* program the BDL address */ 1636 /* lower BDL address */ 1637 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr); 1638 /* upper BDL address */ 1639 azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr)); 1640 1641 /* enable the position buffer */ 1642 if (chip->position_fix[0] != POS_FIX_LPIB || 1643 chip->position_fix[1] != POS_FIX_LPIB) { 1644 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE)) 1645 azx_writel(chip, DPLBASE, 1646 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE); 1647 } 1648 1649 /* set the interrupt enable bits in the descriptor control register */ 1650 azx_sd_writel(azx_dev, SD_CTL, 1651 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK); 1652 1653 return 0; 1654 } 1655 1656 /* 1657 * Probe the given codec address 1658 */ 1659 static int probe_codec(struct azx *chip, int addr) 1660 { 1661 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) | 1662 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID; 1663 unsigned int res; 1664 1665 mutex_lock(&chip->bus->cmd_mutex); 1666 chip->probing = 1; 1667 azx_send_cmd(chip->bus, cmd); 1668 res = azx_get_response(chip->bus, addr); 1669 chip->probing = 0; 1670 mutex_unlock(&chip->bus->cmd_mutex); 1671 if (res == -1) 1672 return -EIO; 1673 snd_printdd(SFX "%s: codec #%d probed OK\n", pci_name(chip->pci), addr); 1674 return 0; 1675 } 1676 1677 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec, 1678 struct hda_pcm *cpcm); 1679 static void azx_stop_chip(struct azx *chip); 1680 1681 static void azx_bus_reset(struct hda_bus *bus) 1682 { 1683 struct azx *chip = bus->private_data; 1684 1685 bus->in_reset = 1; 1686 azx_stop_chip(chip); 1687 azx_init_chip(chip, 1); 1688 #ifdef CONFIG_PM 1689 if (chip->initialized) { 1690 struct azx_pcm *p; 1691 list_for_each_entry(p, &chip->pcm_list, list) 1692 snd_pcm_suspend_all(p->pcm); 1693 snd_hda_suspend(chip->bus); 1694 snd_hda_resume(chip->bus); 1695 } 1696 #endif 1697 bus->in_reset = 0; 1698 } 1699 1700 static int get_jackpoll_interval(struct azx *chip) 1701 { 1702 int i = jackpoll_ms[chip->dev_index]; 1703 unsigned int j; 1704 if (i == 0) 1705 return 0; 1706 if (i < 50 || i > 60000) 1707 j = 0; 1708 else 1709 j = msecs_to_jiffies(i); 1710 if (j == 0) 1711 snd_printk(KERN_WARNING SFX 1712 "jackpoll_ms value out of range: %d\n", i); 1713 return j; 1714 } 1715 1716 /* 1717 * Codec initialization 1718 */ 1719 1720 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */ 1721 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = { 1722 [AZX_DRIVER_NVIDIA] = 8, 1723 [AZX_DRIVER_TERA] = 1, 1724 }; 1725 1726 static int azx_codec_create(struct azx *chip, const char *model) 1727 { 1728 struct hda_bus_template bus_temp; 1729 int c, codecs, err; 1730 int max_slots; 1731 1732 memset(&bus_temp, 0, sizeof(bus_temp)); 1733 bus_temp.private_data = chip; 1734 bus_temp.modelname = model; 1735 bus_temp.pci = chip->pci; 1736 bus_temp.ops.command = azx_send_cmd; 1737 bus_temp.ops.get_response = azx_get_response; 1738 bus_temp.ops.attach_pcm = azx_attach_pcm_stream; 1739 bus_temp.ops.bus_reset = azx_bus_reset; 1740 #ifdef CONFIG_PM 1741 bus_temp.power_save = &power_save; 1742 bus_temp.ops.pm_notify = azx_power_notify; 1743 #endif 1744 #ifdef CONFIG_SND_HDA_DSP_LOADER 1745 bus_temp.ops.load_dsp_prepare = azx_load_dsp_prepare; 1746 bus_temp.ops.load_dsp_trigger = azx_load_dsp_trigger; 1747 bus_temp.ops.load_dsp_cleanup = azx_load_dsp_cleanup; 1748 #endif 1749 1750 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus); 1751 if (err < 0) 1752 return err; 1753 1754 if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) { 1755 snd_printd(SFX "%s: Enable delay in RIRB handling\n", pci_name(chip->pci)); 1756 chip->bus->needs_damn_long_delay = 1; 1757 } 1758 1759 codecs = 0; 1760 max_slots = azx_max_codecs[chip->driver_type]; 1761 if (!max_slots) 1762 max_slots = AZX_DEFAULT_CODECS; 1763 1764 /* First try to probe all given codec slots */ 1765 for (c = 0; c < max_slots; c++) { 1766 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) { 1767 if (probe_codec(chip, c) < 0) { 1768 /* Some BIOSen give you wrong codec addresses 1769 * that don't exist 1770 */ 1771 snd_printk(KERN_WARNING SFX 1772 "%s: Codec #%d probe error; " 1773 "disabling it...\n", pci_name(chip->pci), c); 1774 chip->codec_mask &= ~(1 << c); 1775 /* More badly, accessing to a non-existing 1776 * codec often screws up the controller chip, 1777 * and disturbs the further communications. 1778 * Thus if an error occurs during probing, 1779 * better to reset the controller chip to 1780 * get back to the sanity state. 1781 */ 1782 azx_stop_chip(chip); 1783 azx_init_chip(chip, 1); 1784 } 1785 } 1786 } 1787 1788 /* AMD chipsets often cause the communication stalls upon certain 1789 * sequence like the pin-detection. It seems that forcing the synced 1790 * access works around the stall. Grrr... 1791 */ 1792 if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) { 1793 snd_printd(SFX "%s: Enable sync_write for stable communication\n", 1794 pci_name(chip->pci)); 1795 chip->bus->sync_write = 1; 1796 chip->bus->allow_bus_reset = 1; 1797 } 1798 1799 /* Then create codec instances */ 1800 for (c = 0; c < max_slots; c++) { 1801 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) { 1802 struct hda_codec *codec; 1803 err = snd_hda_codec_new(chip->bus, c, &codec); 1804 if (err < 0) 1805 continue; 1806 codec->jackpoll_interval = get_jackpoll_interval(chip); 1807 codec->beep_mode = chip->beep_mode; 1808 codecs++; 1809 } 1810 } 1811 if (!codecs) { 1812 snd_printk(KERN_ERR SFX "%s: no codecs initialized\n", pci_name(chip->pci)); 1813 return -ENXIO; 1814 } 1815 return 0; 1816 } 1817 1818 /* configure each codec instance */ 1819 static int azx_codec_configure(struct azx *chip) 1820 { 1821 struct hda_codec *codec; 1822 list_for_each_entry(codec, &chip->bus->codec_list, list) { 1823 snd_hda_codec_configure(codec); 1824 } 1825 return 0; 1826 } 1827 1828 1829 /* 1830 * PCM support 1831 */ 1832 1833 /* assign a stream for the PCM */ 1834 static inline struct azx_dev * 1835 azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream) 1836 { 1837 int dev, i, nums; 1838 struct azx_dev *res = NULL; 1839 /* make a non-zero unique key for the substream */ 1840 int key = (substream->pcm->device << 16) | (substream->number << 2) | 1841 (substream->stream + 1); 1842 1843 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 1844 dev = chip->playback_index_offset; 1845 nums = chip->playback_streams; 1846 } else { 1847 dev = chip->capture_index_offset; 1848 nums = chip->capture_streams; 1849 } 1850 for (i = 0; i < nums; i++, dev++) { 1851 struct azx_dev *azx_dev = &chip->azx_dev[dev]; 1852 dsp_lock(azx_dev); 1853 if (!azx_dev->opened && !dsp_is_locked(azx_dev)) { 1854 res = azx_dev; 1855 if (res->assigned_key == key) { 1856 res->opened = 1; 1857 res->assigned_key = key; 1858 dsp_unlock(azx_dev); 1859 return azx_dev; 1860 } 1861 } 1862 dsp_unlock(azx_dev); 1863 } 1864 if (res) { 1865 dsp_lock(res); 1866 res->opened = 1; 1867 res->assigned_key = key; 1868 dsp_unlock(res); 1869 } 1870 return res; 1871 } 1872 1873 /* release the assigned stream */ 1874 static inline void azx_release_device(struct azx_dev *azx_dev) 1875 { 1876 azx_dev->opened = 0; 1877 } 1878 1879 static cycle_t azx_cc_read(const struct cyclecounter *cc) 1880 { 1881 struct azx_dev *azx_dev = container_of(cc, struct azx_dev, azx_cc); 1882 struct snd_pcm_substream *substream = azx_dev->substream; 1883 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 1884 struct azx *chip = apcm->chip; 1885 1886 return azx_readl(chip, WALLCLK); 1887 } 1888 1889 static void azx_timecounter_init(struct snd_pcm_substream *substream, 1890 bool force, cycle_t last) 1891 { 1892 struct azx_dev *azx_dev = get_azx_dev(substream); 1893 struct timecounter *tc = &azx_dev->azx_tc; 1894 struct cyclecounter *cc = &azx_dev->azx_cc; 1895 u64 nsec; 1896 1897 cc->read = azx_cc_read; 1898 cc->mask = CLOCKSOURCE_MASK(32); 1899 1900 /* 1901 * Converting from 24 MHz to ns means applying a 125/3 factor. 1902 * To avoid any saturation issues in intermediate operations, 1903 * the 125 factor is applied first. The division is applied 1904 * last after reading the timecounter value. 1905 * Applying the 1/3 factor as part of the multiplication 1906 * requires at least 20 bits for a decent precision, however 1907 * overflows occur after about 4 hours or less, not a option. 1908 */ 1909 1910 cc->mult = 125; /* saturation after 195 years */ 1911 cc->shift = 0; 1912 1913 nsec = 0; /* audio time is elapsed time since trigger */ 1914 timecounter_init(tc, cc, nsec); 1915 if (force) 1916 /* 1917 * force timecounter to use predefined value, 1918 * used for synchronized starts 1919 */ 1920 tc->cycle_last = last; 1921 } 1922 1923 static u64 azx_adjust_codec_delay(struct snd_pcm_substream *substream, 1924 u64 nsec) 1925 { 1926 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 1927 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; 1928 u64 codec_frames, codec_nsecs; 1929 1930 if (!hinfo->ops.get_delay) 1931 return nsec; 1932 1933 codec_frames = hinfo->ops.get_delay(hinfo, apcm->codec, substream); 1934 codec_nsecs = div_u64(codec_frames * 1000000000LL, 1935 substream->runtime->rate); 1936 1937 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 1938 return nsec + codec_nsecs; 1939 1940 return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0; 1941 } 1942 1943 static int azx_get_wallclock_tstamp(struct snd_pcm_substream *substream, 1944 struct timespec *ts) 1945 { 1946 struct azx_dev *azx_dev = get_azx_dev(substream); 1947 u64 nsec; 1948 1949 nsec = timecounter_read(&azx_dev->azx_tc); 1950 nsec = div_u64(nsec, 3); /* can be optimized */ 1951 nsec = azx_adjust_codec_delay(substream, nsec); 1952 1953 *ts = ns_to_timespec(nsec); 1954 1955 return 0; 1956 } 1957 1958 static struct snd_pcm_hardware azx_pcm_hw = { 1959 .info = (SNDRV_PCM_INFO_MMAP | 1960 SNDRV_PCM_INFO_INTERLEAVED | 1961 SNDRV_PCM_INFO_BLOCK_TRANSFER | 1962 SNDRV_PCM_INFO_MMAP_VALID | 1963 /* No full-resume yet implemented */ 1964 /* SNDRV_PCM_INFO_RESUME |*/ 1965 SNDRV_PCM_INFO_PAUSE | 1966 SNDRV_PCM_INFO_SYNC_START | 1967 SNDRV_PCM_INFO_HAS_WALL_CLOCK | 1968 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP), 1969 .formats = SNDRV_PCM_FMTBIT_S16_LE, 1970 .rates = SNDRV_PCM_RATE_48000, 1971 .rate_min = 48000, 1972 .rate_max = 48000, 1973 .channels_min = 2, 1974 .channels_max = 2, 1975 .buffer_bytes_max = AZX_MAX_BUF_SIZE, 1976 .period_bytes_min = 128, 1977 .period_bytes_max = AZX_MAX_BUF_SIZE / 2, 1978 .periods_min = 2, 1979 .periods_max = AZX_MAX_FRAG, 1980 .fifo_size = 0, 1981 }; 1982 1983 static int azx_pcm_open(struct snd_pcm_substream *substream) 1984 { 1985 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 1986 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; 1987 struct azx *chip = apcm->chip; 1988 struct azx_dev *azx_dev; 1989 struct snd_pcm_runtime *runtime = substream->runtime; 1990 unsigned long flags; 1991 int err; 1992 int buff_step; 1993 1994 mutex_lock(&chip->open_mutex); 1995 azx_dev = azx_assign_device(chip, substream); 1996 if (azx_dev == NULL) { 1997 mutex_unlock(&chip->open_mutex); 1998 return -EBUSY; 1999 } 2000 runtime->hw = azx_pcm_hw; 2001 runtime->hw.channels_min = hinfo->channels_min; 2002 runtime->hw.channels_max = hinfo->channels_max; 2003 runtime->hw.formats = hinfo->formats; 2004 runtime->hw.rates = hinfo->rates; 2005 snd_pcm_limit_hw_rates(runtime); 2006 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS); 2007 2008 /* avoid wrap-around with wall-clock */ 2009 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME, 2010 20, 2011 178000000); 2012 2013 if (chip->align_buffer_size) 2014 /* constrain buffer sizes to be multiple of 128 2015 bytes. This is more efficient in terms of memory 2016 access but isn't required by the HDA spec and 2017 prevents users from specifying exact period/buffer 2018 sizes. For example for 44.1kHz, a period size set 2019 to 20ms will be rounded to 19.59ms. */ 2020 buff_step = 128; 2021 else 2022 /* Don't enforce steps on buffer sizes, still need to 2023 be multiple of 4 bytes (HDA spec). Tested on Intel 2024 HDA controllers, may not work on all devices where 2025 option needs to be disabled */ 2026 buff_step = 4; 2027 2028 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 2029 buff_step); 2030 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 2031 buff_step); 2032 snd_hda_power_up_d3wait(apcm->codec); 2033 err = hinfo->ops.open(hinfo, apcm->codec, substream); 2034 if (err < 0) { 2035 azx_release_device(azx_dev); 2036 snd_hda_power_down(apcm->codec); 2037 mutex_unlock(&chip->open_mutex); 2038 return err; 2039 } 2040 snd_pcm_limit_hw_rates(runtime); 2041 /* sanity check */ 2042 if (snd_BUG_ON(!runtime->hw.channels_min) || 2043 snd_BUG_ON(!runtime->hw.channels_max) || 2044 snd_BUG_ON(!runtime->hw.formats) || 2045 snd_BUG_ON(!runtime->hw.rates)) { 2046 azx_release_device(azx_dev); 2047 hinfo->ops.close(hinfo, apcm->codec, substream); 2048 snd_hda_power_down(apcm->codec); 2049 mutex_unlock(&chip->open_mutex); 2050 return -EINVAL; 2051 } 2052 2053 /* disable WALLCLOCK timestamps for capture streams 2054 until we figure out how to handle digital inputs */ 2055 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 2056 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK; 2057 2058 spin_lock_irqsave(&chip->reg_lock, flags); 2059 azx_dev->substream = substream; 2060 azx_dev->running = 0; 2061 spin_unlock_irqrestore(&chip->reg_lock, flags); 2062 2063 runtime->private_data = azx_dev; 2064 snd_pcm_set_sync(substream); 2065 mutex_unlock(&chip->open_mutex); 2066 return 0; 2067 } 2068 2069 static int azx_pcm_close(struct snd_pcm_substream *substream) 2070 { 2071 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 2072 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; 2073 struct azx *chip = apcm->chip; 2074 struct azx_dev *azx_dev = get_azx_dev(substream); 2075 unsigned long flags; 2076 2077 mutex_lock(&chip->open_mutex); 2078 spin_lock_irqsave(&chip->reg_lock, flags); 2079 azx_dev->substream = NULL; 2080 azx_dev->running = 0; 2081 spin_unlock_irqrestore(&chip->reg_lock, flags); 2082 azx_release_device(azx_dev); 2083 hinfo->ops.close(hinfo, apcm->codec, substream); 2084 snd_hda_power_down(apcm->codec); 2085 mutex_unlock(&chip->open_mutex); 2086 return 0; 2087 } 2088 2089 static int azx_pcm_hw_params(struct snd_pcm_substream *substream, 2090 struct snd_pcm_hw_params *hw_params) 2091 { 2092 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 2093 struct azx *chip = apcm->chip; 2094 struct azx_dev *azx_dev = get_azx_dev(substream); 2095 int ret; 2096 2097 dsp_lock(azx_dev); 2098 if (dsp_is_locked(azx_dev)) { 2099 ret = -EBUSY; 2100 goto unlock; 2101 } 2102 2103 mark_runtime_wc(chip, azx_dev, substream, false); 2104 azx_dev->bufsize = 0; 2105 azx_dev->period_bytes = 0; 2106 azx_dev->format_val = 0; 2107 ret = snd_pcm_lib_malloc_pages(substream, 2108 params_buffer_bytes(hw_params)); 2109 if (ret < 0) 2110 goto unlock; 2111 mark_runtime_wc(chip, azx_dev, substream, true); 2112 unlock: 2113 dsp_unlock(azx_dev); 2114 return ret; 2115 } 2116 2117 static int azx_pcm_hw_free(struct snd_pcm_substream *substream) 2118 { 2119 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 2120 struct azx_dev *azx_dev = get_azx_dev(substream); 2121 struct azx *chip = apcm->chip; 2122 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; 2123 2124 /* reset BDL address */ 2125 dsp_lock(azx_dev); 2126 if (!dsp_is_locked(azx_dev)) { 2127 azx_sd_writel(azx_dev, SD_BDLPL, 0); 2128 azx_sd_writel(azx_dev, SD_BDLPU, 0); 2129 azx_sd_writel(azx_dev, SD_CTL, 0); 2130 azx_dev->bufsize = 0; 2131 azx_dev->period_bytes = 0; 2132 azx_dev->format_val = 0; 2133 } 2134 2135 snd_hda_codec_cleanup(apcm->codec, hinfo, substream); 2136 2137 mark_runtime_wc(chip, azx_dev, substream, false); 2138 azx_dev->prepared = 0; 2139 dsp_unlock(azx_dev); 2140 return snd_pcm_lib_free_pages(substream); 2141 } 2142 2143 static int azx_pcm_prepare(struct snd_pcm_substream *substream) 2144 { 2145 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 2146 struct azx *chip = apcm->chip; 2147 struct azx_dev *azx_dev = get_azx_dev(substream); 2148 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream]; 2149 struct snd_pcm_runtime *runtime = substream->runtime; 2150 unsigned int bufsize, period_bytes, format_val, stream_tag; 2151 int err; 2152 struct hda_spdif_out *spdif = 2153 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid); 2154 unsigned short ctls = spdif ? spdif->ctls : 0; 2155 2156 dsp_lock(azx_dev); 2157 if (dsp_is_locked(azx_dev)) { 2158 err = -EBUSY; 2159 goto unlock; 2160 } 2161 2162 azx_stream_reset(chip, azx_dev); 2163 format_val = snd_hda_calc_stream_format(runtime->rate, 2164 runtime->channels, 2165 runtime->format, 2166 hinfo->maxbps, 2167 ctls); 2168 if (!format_val) { 2169 snd_printk(KERN_ERR SFX 2170 "%s: invalid format_val, rate=%d, ch=%d, format=%d\n", 2171 pci_name(chip->pci), runtime->rate, runtime->channels, runtime->format); 2172 err = -EINVAL; 2173 goto unlock; 2174 } 2175 2176 bufsize = snd_pcm_lib_buffer_bytes(substream); 2177 period_bytes = snd_pcm_lib_period_bytes(substream); 2178 2179 snd_printdd(SFX "%s: azx_pcm_prepare: bufsize=0x%x, format=0x%x\n", 2180 pci_name(chip->pci), bufsize, format_val); 2181 2182 if (bufsize != azx_dev->bufsize || 2183 period_bytes != azx_dev->period_bytes || 2184 format_val != azx_dev->format_val || 2185 runtime->no_period_wakeup != azx_dev->no_period_wakeup) { 2186 azx_dev->bufsize = bufsize; 2187 azx_dev->period_bytes = period_bytes; 2188 azx_dev->format_val = format_val; 2189 azx_dev->no_period_wakeup = runtime->no_period_wakeup; 2190 err = azx_setup_periods(chip, substream, azx_dev); 2191 if (err < 0) 2192 goto unlock; 2193 } 2194 2195 /* when LPIB delay correction gives a small negative value, 2196 * we ignore it; currently set the threshold statically to 2197 * 64 frames 2198 */ 2199 if (runtime->period_size > 64) 2200 azx_dev->delay_negative_threshold = -frames_to_bytes(runtime, 64); 2201 else 2202 azx_dev->delay_negative_threshold = 0; 2203 2204 /* wallclk has 24Mhz clock source */ 2205 azx_dev->period_wallclk = (((runtime->period_size * 24000) / 2206 runtime->rate) * 1000); 2207 azx_setup_controller(chip, azx_dev); 2208 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 2209 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1; 2210 else 2211 azx_dev->fifo_size = 0; 2212 2213 stream_tag = azx_dev->stream_tag; 2214 /* CA-IBG chips need the playback stream starting from 1 */ 2215 if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) && 2216 stream_tag > chip->capture_streams) 2217 stream_tag -= chip->capture_streams; 2218 err = snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag, 2219 azx_dev->format_val, substream); 2220 2221 unlock: 2222 if (!err) 2223 azx_dev->prepared = 1; 2224 dsp_unlock(azx_dev); 2225 return err; 2226 } 2227 2228 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd) 2229 { 2230 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 2231 struct azx *chip = apcm->chip; 2232 struct azx_dev *azx_dev; 2233 struct snd_pcm_substream *s; 2234 int rstart = 0, start, nsync = 0, sbits = 0; 2235 int nwait, timeout; 2236 2237 azx_dev = get_azx_dev(substream); 2238 trace_azx_pcm_trigger(chip, azx_dev, cmd); 2239 2240 if (dsp_is_locked(azx_dev) || !azx_dev->prepared) 2241 return -EPIPE; 2242 2243 switch (cmd) { 2244 case SNDRV_PCM_TRIGGER_START: 2245 rstart = 1; 2246 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 2247 case SNDRV_PCM_TRIGGER_RESUME: 2248 start = 1; 2249 break; 2250 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 2251 case SNDRV_PCM_TRIGGER_SUSPEND: 2252 case SNDRV_PCM_TRIGGER_STOP: 2253 start = 0; 2254 break; 2255 default: 2256 return -EINVAL; 2257 } 2258 2259 snd_pcm_group_for_each_entry(s, substream) { 2260 if (s->pcm->card != substream->pcm->card) 2261 continue; 2262 azx_dev = get_azx_dev(s); 2263 sbits |= 1 << azx_dev->index; 2264 nsync++; 2265 snd_pcm_trigger_done(s, substream); 2266 } 2267 2268 spin_lock(&chip->reg_lock); 2269 2270 /* first, set SYNC bits of corresponding streams */ 2271 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC) 2272 azx_writel(chip, OLD_SSYNC, 2273 azx_readl(chip, OLD_SSYNC) | sbits); 2274 else 2275 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits); 2276 2277 snd_pcm_group_for_each_entry(s, substream) { 2278 if (s->pcm->card != substream->pcm->card) 2279 continue; 2280 azx_dev = get_azx_dev(s); 2281 if (start) { 2282 azx_dev->start_wallclk = azx_readl(chip, WALLCLK); 2283 if (!rstart) 2284 azx_dev->start_wallclk -= 2285 azx_dev->period_wallclk; 2286 azx_stream_start(chip, azx_dev); 2287 } else { 2288 azx_stream_stop(chip, azx_dev); 2289 } 2290 azx_dev->running = start; 2291 } 2292 spin_unlock(&chip->reg_lock); 2293 if (start) { 2294 /* wait until all FIFOs get ready */ 2295 for (timeout = 5000; timeout; timeout--) { 2296 nwait = 0; 2297 snd_pcm_group_for_each_entry(s, substream) { 2298 if (s->pcm->card != substream->pcm->card) 2299 continue; 2300 azx_dev = get_azx_dev(s); 2301 if (!(azx_sd_readb(azx_dev, SD_STS) & 2302 SD_STS_FIFO_READY)) 2303 nwait++; 2304 } 2305 if (!nwait) 2306 break; 2307 cpu_relax(); 2308 } 2309 } else { 2310 /* wait until all RUN bits are cleared */ 2311 for (timeout = 5000; timeout; timeout--) { 2312 nwait = 0; 2313 snd_pcm_group_for_each_entry(s, substream) { 2314 if (s->pcm->card != substream->pcm->card) 2315 continue; 2316 azx_dev = get_azx_dev(s); 2317 if (azx_sd_readb(azx_dev, SD_CTL) & 2318 SD_CTL_DMA_START) 2319 nwait++; 2320 } 2321 if (!nwait) 2322 break; 2323 cpu_relax(); 2324 } 2325 } 2326 spin_lock(&chip->reg_lock); 2327 /* reset SYNC bits */ 2328 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC) 2329 azx_writel(chip, OLD_SSYNC, 2330 azx_readl(chip, OLD_SSYNC) & ~sbits); 2331 else 2332 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits); 2333 if (start) { 2334 azx_timecounter_init(substream, 0, 0); 2335 if (nsync > 1) { 2336 cycle_t cycle_last; 2337 2338 /* same start cycle for master and group */ 2339 azx_dev = get_azx_dev(substream); 2340 cycle_last = azx_dev->azx_tc.cycle_last; 2341 2342 snd_pcm_group_for_each_entry(s, substream) { 2343 if (s->pcm->card != substream->pcm->card) 2344 continue; 2345 azx_timecounter_init(s, 1, cycle_last); 2346 } 2347 } 2348 } 2349 spin_unlock(&chip->reg_lock); 2350 return 0; 2351 } 2352 2353 /* get the current DMA position with correction on VIA chips */ 2354 static unsigned int azx_via_get_position(struct azx *chip, 2355 struct azx_dev *azx_dev) 2356 { 2357 unsigned int link_pos, mini_pos, bound_pos; 2358 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos; 2359 unsigned int fifo_size; 2360 2361 link_pos = azx_sd_readl(azx_dev, SD_LPIB); 2362 if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 2363 /* Playback, no problem using link position */ 2364 return link_pos; 2365 } 2366 2367 /* Capture */ 2368 /* For new chipset, 2369 * use mod to get the DMA position just like old chipset 2370 */ 2371 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf); 2372 mod_dma_pos %= azx_dev->period_bytes; 2373 2374 /* azx_dev->fifo_size can't get FIFO size of in stream. 2375 * Get from base address + offset. 2376 */ 2377 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET); 2378 2379 if (azx_dev->insufficient) { 2380 /* Link position never gather than FIFO size */ 2381 if (link_pos <= fifo_size) 2382 return 0; 2383 2384 azx_dev->insufficient = 0; 2385 } 2386 2387 if (link_pos <= fifo_size) 2388 mini_pos = azx_dev->bufsize + link_pos - fifo_size; 2389 else 2390 mini_pos = link_pos - fifo_size; 2391 2392 /* Find nearest previous boudary */ 2393 mod_mini_pos = mini_pos % azx_dev->period_bytes; 2394 mod_link_pos = link_pos % azx_dev->period_bytes; 2395 if (mod_link_pos >= fifo_size) 2396 bound_pos = link_pos - mod_link_pos; 2397 else if (mod_dma_pos >= mod_mini_pos) 2398 bound_pos = mini_pos - mod_mini_pos; 2399 else { 2400 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes; 2401 if (bound_pos >= azx_dev->bufsize) 2402 bound_pos = 0; 2403 } 2404 2405 /* Calculate real DMA position we want */ 2406 return bound_pos + mod_dma_pos; 2407 } 2408 2409 static unsigned int azx_get_position(struct azx *chip, 2410 struct azx_dev *azx_dev, 2411 bool with_check) 2412 { 2413 struct snd_pcm_substream *substream = azx_dev->substream; 2414 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 2415 unsigned int pos; 2416 int stream = substream->stream; 2417 struct hda_pcm_stream *hinfo = apcm->hinfo[stream]; 2418 int delay = 0; 2419 2420 switch (chip->position_fix[stream]) { 2421 case POS_FIX_LPIB: 2422 /* read LPIB */ 2423 pos = azx_sd_readl(azx_dev, SD_LPIB); 2424 break; 2425 case POS_FIX_VIACOMBO: 2426 pos = azx_via_get_position(chip, azx_dev); 2427 break; 2428 default: 2429 /* use the position buffer */ 2430 pos = le32_to_cpu(*azx_dev->posbuf); 2431 if (with_check && chip->position_fix[stream] == POS_FIX_AUTO) { 2432 if (!pos || pos == (u32)-1) { 2433 printk(KERN_WARNING 2434 "hda-intel: Invalid position buffer, " 2435 "using LPIB read method instead.\n"); 2436 chip->position_fix[stream] = POS_FIX_LPIB; 2437 pos = azx_sd_readl(azx_dev, SD_LPIB); 2438 } else 2439 chip->position_fix[stream] = POS_FIX_POSBUF; 2440 } 2441 break; 2442 } 2443 2444 if (pos >= azx_dev->bufsize) 2445 pos = 0; 2446 2447 /* calculate runtime delay from LPIB */ 2448 if (substream->runtime && 2449 chip->position_fix[stream] == POS_FIX_POSBUF && 2450 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) { 2451 unsigned int lpib_pos = azx_sd_readl(azx_dev, SD_LPIB); 2452 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 2453 delay = pos - lpib_pos; 2454 else 2455 delay = lpib_pos - pos; 2456 if (delay < 0) { 2457 if (delay >= azx_dev->delay_negative_threshold) 2458 delay = 0; 2459 else 2460 delay += azx_dev->bufsize; 2461 } 2462 if (delay >= azx_dev->period_bytes) { 2463 snd_printk(KERN_WARNING SFX 2464 "%s: Unstable LPIB (%d >= %d); " 2465 "disabling LPIB delay counting\n", 2466 pci_name(chip->pci), delay, azx_dev->period_bytes); 2467 delay = 0; 2468 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY; 2469 } 2470 delay = bytes_to_frames(substream->runtime, delay); 2471 } 2472 2473 if (substream->runtime) { 2474 if (hinfo->ops.get_delay) 2475 delay += hinfo->ops.get_delay(hinfo, apcm->codec, 2476 substream); 2477 substream->runtime->delay = delay; 2478 } 2479 2480 trace_azx_get_position(chip, azx_dev, pos, delay); 2481 return pos; 2482 } 2483 2484 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream) 2485 { 2486 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 2487 struct azx *chip = apcm->chip; 2488 struct azx_dev *azx_dev = get_azx_dev(substream); 2489 return bytes_to_frames(substream->runtime, 2490 azx_get_position(chip, azx_dev, false)); 2491 } 2492 2493 /* 2494 * Check whether the current DMA position is acceptable for updating 2495 * periods. Returns non-zero if it's OK. 2496 * 2497 * Many HD-audio controllers appear pretty inaccurate about 2498 * the update-IRQ timing. The IRQ is issued before actually the 2499 * data is processed. So, we need to process it afterwords in a 2500 * workqueue. 2501 */ 2502 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev) 2503 { 2504 u32 wallclk; 2505 unsigned int pos; 2506 2507 wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk; 2508 if (wallclk < (azx_dev->period_wallclk * 2) / 3) 2509 return -1; /* bogus (too early) interrupt */ 2510 2511 pos = azx_get_position(chip, azx_dev, true); 2512 2513 if (WARN_ONCE(!azx_dev->period_bytes, 2514 "hda-intel: zero azx_dev->period_bytes")) 2515 return -1; /* this shouldn't happen! */ 2516 if (wallclk < (azx_dev->period_wallclk * 5) / 4 && 2517 pos % azx_dev->period_bytes > azx_dev->period_bytes / 2) 2518 /* NG - it's below the first next period boundary */ 2519 return bdl_pos_adj[chip->dev_index] ? 0 : -1; 2520 azx_dev->start_wallclk += wallclk; 2521 return 1; /* OK, it's fine */ 2522 } 2523 2524 /* 2525 * The work for pending PCM period updates. 2526 */ 2527 static void azx_irq_pending_work(struct work_struct *work) 2528 { 2529 struct azx *chip = container_of(work, struct azx, irq_pending_work); 2530 int i, pending, ok; 2531 2532 if (!chip->irq_pending_warned) { 2533 printk(KERN_WARNING 2534 "hda-intel: IRQ timing workaround is activated " 2535 "for card #%d. Suggest a bigger bdl_pos_adj.\n", 2536 chip->card->number); 2537 chip->irq_pending_warned = 1; 2538 } 2539 2540 for (;;) { 2541 pending = 0; 2542 spin_lock_irq(&chip->reg_lock); 2543 for (i = 0; i < chip->num_streams; i++) { 2544 struct azx_dev *azx_dev = &chip->azx_dev[i]; 2545 if (!azx_dev->irq_pending || 2546 !azx_dev->substream || 2547 !azx_dev->running) 2548 continue; 2549 ok = azx_position_ok(chip, azx_dev); 2550 if (ok > 0) { 2551 azx_dev->irq_pending = 0; 2552 spin_unlock(&chip->reg_lock); 2553 snd_pcm_period_elapsed(azx_dev->substream); 2554 spin_lock(&chip->reg_lock); 2555 } else if (ok < 0) { 2556 pending = 0; /* too early */ 2557 } else 2558 pending++; 2559 } 2560 spin_unlock_irq(&chip->reg_lock); 2561 if (!pending) 2562 return; 2563 msleep(1); 2564 } 2565 } 2566 2567 /* clear irq_pending flags and assure no on-going workq */ 2568 static void azx_clear_irq_pending(struct azx *chip) 2569 { 2570 int i; 2571 2572 spin_lock_irq(&chip->reg_lock); 2573 for (i = 0; i < chip->num_streams; i++) 2574 chip->azx_dev[i].irq_pending = 0; 2575 spin_unlock_irq(&chip->reg_lock); 2576 } 2577 2578 #ifdef CONFIG_X86 2579 static int azx_pcm_mmap(struct snd_pcm_substream *substream, 2580 struct vm_area_struct *area) 2581 { 2582 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 2583 struct azx *chip = apcm->chip; 2584 if (!azx_snoop(chip)) 2585 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot); 2586 return snd_pcm_lib_default_mmap(substream, area); 2587 } 2588 #else 2589 #define azx_pcm_mmap NULL 2590 #endif 2591 2592 static struct snd_pcm_ops azx_pcm_ops = { 2593 .open = azx_pcm_open, 2594 .close = azx_pcm_close, 2595 .ioctl = snd_pcm_lib_ioctl, 2596 .hw_params = azx_pcm_hw_params, 2597 .hw_free = azx_pcm_hw_free, 2598 .prepare = azx_pcm_prepare, 2599 .trigger = azx_pcm_trigger, 2600 .pointer = azx_pcm_pointer, 2601 .wall_clock = azx_get_wallclock_tstamp, 2602 .mmap = azx_pcm_mmap, 2603 .page = snd_pcm_sgbuf_ops_page, 2604 }; 2605 2606 static void azx_pcm_free(struct snd_pcm *pcm) 2607 { 2608 struct azx_pcm *apcm = pcm->private_data; 2609 if (apcm) { 2610 list_del(&apcm->list); 2611 kfree(apcm); 2612 } 2613 } 2614 2615 #define MAX_PREALLOC_SIZE (32 * 1024 * 1024) 2616 2617 static int 2618 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec, 2619 struct hda_pcm *cpcm) 2620 { 2621 struct azx *chip = bus->private_data; 2622 struct snd_pcm *pcm; 2623 struct azx_pcm *apcm; 2624 int pcm_dev = cpcm->device; 2625 unsigned int size; 2626 int s, err; 2627 2628 list_for_each_entry(apcm, &chip->pcm_list, list) { 2629 if (apcm->pcm->device == pcm_dev) { 2630 snd_printk(KERN_ERR SFX "%s: PCM %d already exists\n", 2631 pci_name(chip->pci), pcm_dev); 2632 return -EBUSY; 2633 } 2634 } 2635 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev, 2636 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams, 2637 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams, 2638 &pcm); 2639 if (err < 0) 2640 return err; 2641 strlcpy(pcm->name, cpcm->name, sizeof(pcm->name)); 2642 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL); 2643 if (apcm == NULL) 2644 return -ENOMEM; 2645 apcm->chip = chip; 2646 apcm->pcm = pcm; 2647 apcm->codec = codec; 2648 pcm->private_data = apcm; 2649 pcm->private_free = azx_pcm_free; 2650 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM) 2651 pcm->dev_class = SNDRV_PCM_CLASS_MODEM; 2652 list_add_tail(&apcm->list, &chip->pcm_list); 2653 cpcm->pcm = pcm; 2654 for (s = 0; s < 2; s++) { 2655 apcm->hinfo[s] = &cpcm->stream[s]; 2656 if (cpcm->stream[s].substreams) 2657 snd_pcm_set_ops(pcm, s, &azx_pcm_ops); 2658 } 2659 /* buffer pre-allocation */ 2660 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024; 2661 if (size > MAX_PREALLOC_SIZE) 2662 size = MAX_PREALLOC_SIZE; 2663 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG, 2664 snd_dma_pci_data(chip->pci), 2665 size, MAX_PREALLOC_SIZE); 2666 return 0; 2667 } 2668 2669 /* 2670 * mixer creation - all stuff is implemented in hda module 2671 */ 2672 static int azx_mixer_create(struct azx *chip) 2673 { 2674 return snd_hda_build_controls(chip->bus); 2675 } 2676 2677 2678 /* 2679 * initialize SD streams 2680 */ 2681 static int azx_init_stream(struct azx *chip) 2682 { 2683 int i; 2684 2685 /* initialize each stream (aka device) 2686 * assign the starting bdl address to each stream (device) 2687 * and initialize 2688 */ 2689 for (i = 0; i < chip->num_streams; i++) { 2690 struct azx_dev *azx_dev = &chip->azx_dev[i]; 2691 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8); 2692 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */ 2693 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80); 2694 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */ 2695 azx_dev->sd_int_sta_mask = 1 << i; 2696 /* stream tag: must be non-zero and unique */ 2697 azx_dev->index = i; 2698 azx_dev->stream_tag = i + 1; 2699 } 2700 2701 return 0; 2702 } 2703 2704 static int azx_acquire_irq(struct azx *chip, int do_disconnect) 2705 { 2706 if (request_irq(chip->pci->irq, azx_interrupt, 2707 chip->msi ? 0 : IRQF_SHARED, 2708 KBUILD_MODNAME, chip)) { 2709 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, " 2710 "disabling device\n", chip->pci->irq); 2711 if (do_disconnect) 2712 snd_card_disconnect(chip->card); 2713 return -1; 2714 } 2715 chip->irq = chip->pci->irq; 2716 pci_intx(chip->pci, !chip->msi); 2717 return 0; 2718 } 2719 2720 2721 static void azx_stop_chip(struct azx *chip) 2722 { 2723 if (!chip->initialized) 2724 return; 2725 2726 /* disable interrupts */ 2727 azx_int_disable(chip); 2728 azx_int_clear(chip); 2729 2730 /* disable CORB/RIRB */ 2731 azx_free_cmd_io(chip); 2732 2733 /* disable position buffer */ 2734 azx_writel(chip, DPLBASE, 0); 2735 azx_writel(chip, DPUBASE, 0); 2736 2737 chip->initialized = 0; 2738 } 2739 2740 #ifdef CONFIG_SND_HDA_DSP_LOADER 2741 /* 2742 * DSP loading code (e.g. for CA0132) 2743 */ 2744 2745 /* use the first stream for loading DSP */ 2746 static struct azx_dev * 2747 azx_get_dsp_loader_dev(struct azx *chip) 2748 { 2749 return &chip->azx_dev[chip->playback_index_offset]; 2750 } 2751 2752 static int azx_load_dsp_prepare(struct hda_bus *bus, unsigned int format, 2753 unsigned int byte_size, 2754 struct snd_dma_buffer *bufp) 2755 { 2756 u32 *bdl; 2757 struct azx *chip = bus->private_data; 2758 struct azx_dev *azx_dev; 2759 int err; 2760 2761 azx_dev = azx_get_dsp_loader_dev(chip); 2762 2763 dsp_lock(azx_dev); 2764 spin_lock_irq(&chip->reg_lock); 2765 if (azx_dev->running || azx_dev->locked) { 2766 spin_unlock_irq(&chip->reg_lock); 2767 err = -EBUSY; 2768 goto unlock; 2769 } 2770 azx_dev->prepared = 0; 2771 chip->saved_azx_dev = *azx_dev; 2772 azx_dev->locked = 1; 2773 spin_unlock_irq(&chip->reg_lock); 2774 2775 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG, 2776 snd_dma_pci_data(chip->pci), 2777 byte_size, bufp); 2778 if (err < 0) 2779 goto err_alloc; 2780 2781 mark_pages_wc(chip, bufp, true); 2782 azx_dev->bufsize = byte_size; 2783 azx_dev->period_bytes = byte_size; 2784 azx_dev->format_val = format; 2785 2786 azx_stream_reset(chip, azx_dev); 2787 2788 /* reset BDL address */ 2789 azx_sd_writel(azx_dev, SD_BDLPL, 0); 2790 azx_sd_writel(azx_dev, SD_BDLPU, 0); 2791 2792 azx_dev->frags = 0; 2793 bdl = (u32 *)azx_dev->bdl.area; 2794 err = setup_bdle(chip, bufp, azx_dev, &bdl, 0, byte_size, 0); 2795 if (err < 0) 2796 goto error; 2797 2798 azx_setup_controller(chip, azx_dev); 2799 dsp_unlock(azx_dev); 2800 return azx_dev->stream_tag; 2801 2802 error: 2803 mark_pages_wc(chip, bufp, false); 2804 snd_dma_free_pages(bufp); 2805 err_alloc: 2806 spin_lock_irq(&chip->reg_lock); 2807 if (azx_dev->opened) 2808 *azx_dev = chip->saved_azx_dev; 2809 azx_dev->locked = 0; 2810 spin_unlock_irq(&chip->reg_lock); 2811 unlock: 2812 dsp_unlock(azx_dev); 2813 return err; 2814 } 2815 2816 static void azx_load_dsp_trigger(struct hda_bus *bus, bool start) 2817 { 2818 struct azx *chip = bus->private_data; 2819 struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip); 2820 2821 if (start) 2822 azx_stream_start(chip, azx_dev); 2823 else 2824 azx_stream_stop(chip, azx_dev); 2825 azx_dev->running = start; 2826 } 2827 2828 static void azx_load_dsp_cleanup(struct hda_bus *bus, 2829 struct snd_dma_buffer *dmab) 2830 { 2831 struct azx *chip = bus->private_data; 2832 struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip); 2833 2834 if (!dmab->area || !azx_dev->locked) 2835 return; 2836 2837 dsp_lock(azx_dev); 2838 /* reset BDL address */ 2839 azx_sd_writel(azx_dev, SD_BDLPL, 0); 2840 azx_sd_writel(azx_dev, SD_BDLPU, 0); 2841 azx_sd_writel(azx_dev, SD_CTL, 0); 2842 azx_dev->bufsize = 0; 2843 azx_dev->period_bytes = 0; 2844 azx_dev->format_val = 0; 2845 2846 mark_pages_wc(chip, dmab, false); 2847 snd_dma_free_pages(dmab); 2848 dmab->area = NULL; 2849 2850 spin_lock_irq(&chip->reg_lock); 2851 if (azx_dev->opened) 2852 *azx_dev = chip->saved_azx_dev; 2853 azx_dev->locked = 0; 2854 spin_unlock_irq(&chip->reg_lock); 2855 dsp_unlock(azx_dev); 2856 } 2857 #endif /* CONFIG_SND_HDA_DSP_LOADER */ 2858 2859 #ifdef CONFIG_PM 2860 /* power-up/down the controller */ 2861 static void azx_power_notify(struct hda_bus *bus, bool power_up) 2862 { 2863 struct azx *chip = bus->private_data; 2864 2865 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME)) 2866 return; 2867 2868 if (power_up) 2869 pm_runtime_get_sync(&chip->pci->dev); 2870 else 2871 pm_runtime_put_sync(&chip->pci->dev); 2872 } 2873 2874 static DEFINE_MUTEX(card_list_lock); 2875 static LIST_HEAD(card_list); 2876 2877 static void azx_add_card_list(struct azx *chip) 2878 { 2879 mutex_lock(&card_list_lock); 2880 list_add(&chip->list, &card_list); 2881 mutex_unlock(&card_list_lock); 2882 } 2883 2884 static void azx_del_card_list(struct azx *chip) 2885 { 2886 mutex_lock(&card_list_lock); 2887 list_del_init(&chip->list); 2888 mutex_unlock(&card_list_lock); 2889 } 2890 2891 /* trigger power-save check at writing parameter */ 2892 static int param_set_xint(const char *val, const struct kernel_param *kp) 2893 { 2894 struct azx *chip; 2895 struct hda_codec *c; 2896 int prev = power_save; 2897 int ret = param_set_int(val, kp); 2898 2899 if (ret || prev == power_save) 2900 return ret; 2901 2902 mutex_lock(&card_list_lock); 2903 list_for_each_entry(chip, &card_list, list) { 2904 if (!chip->bus || chip->disabled) 2905 continue; 2906 list_for_each_entry(c, &chip->bus->codec_list, list) 2907 snd_hda_power_sync(c); 2908 } 2909 mutex_unlock(&card_list_lock); 2910 return 0; 2911 } 2912 #else 2913 #define azx_add_card_list(chip) /* NOP */ 2914 #define azx_del_card_list(chip) /* NOP */ 2915 #endif /* CONFIG_PM */ 2916 2917 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO) 2918 /* 2919 * power management 2920 */ 2921 static int azx_suspend(struct device *dev) 2922 { 2923 struct pci_dev *pci = to_pci_dev(dev); 2924 struct snd_card *card = dev_get_drvdata(dev); 2925 struct azx *chip = card->private_data; 2926 struct azx_pcm *p; 2927 2928 if (chip->disabled) 2929 return 0; 2930 2931 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 2932 azx_clear_irq_pending(chip); 2933 list_for_each_entry(p, &chip->pcm_list, list) 2934 snd_pcm_suspend_all(p->pcm); 2935 if (chip->initialized) 2936 snd_hda_suspend(chip->bus); 2937 azx_stop_chip(chip); 2938 azx_enter_link_reset(chip); 2939 if (chip->irq >= 0) { 2940 free_irq(chip->irq, chip); 2941 chip->irq = -1; 2942 } 2943 if (chip->msi) 2944 pci_disable_msi(chip->pci); 2945 pci_disable_device(pci); 2946 pci_save_state(pci); 2947 pci_set_power_state(pci, PCI_D3hot); 2948 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) 2949 hda_display_power(false); 2950 return 0; 2951 } 2952 2953 static int azx_resume(struct device *dev) 2954 { 2955 struct pci_dev *pci = to_pci_dev(dev); 2956 struct snd_card *card = dev_get_drvdata(dev); 2957 struct azx *chip = card->private_data; 2958 2959 if (chip->disabled) 2960 return 0; 2961 2962 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) 2963 hda_display_power(true); 2964 pci_set_power_state(pci, PCI_D0); 2965 pci_restore_state(pci); 2966 if (pci_enable_device(pci) < 0) { 2967 printk(KERN_ERR "hda-intel: pci_enable_device failed, " 2968 "disabling device\n"); 2969 snd_card_disconnect(card); 2970 return -EIO; 2971 } 2972 pci_set_master(pci); 2973 if (chip->msi) 2974 if (pci_enable_msi(pci) < 0) 2975 chip->msi = 0; 2976 if (azx_acquire_irq(chip, 1) < 0) 2977 return -EIO; 2978 azx_init_pci(chip); 2979 2980 azx_init_chip(chip, 1); 2981 2982 snd_hda_resume(chip->bus); 2983 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 2984 return 0; 2985 } 2986 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */ 2987 2988 #ifdef CONFIG_PM_RUNTIME 2989 static int azx_runtime_suspend(struct device *dev) 2990 { 2991 struct snd_card *card = dev_get_drvdata(dev); 2992 struct azx *chip = card->private_data; 2993 2994 if (chip->disabled) 2995 return 0; 2996 2997 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME)) 2998 return 0; 2999 3000 /* enable controller wake up event */ 3001 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) | 3002 STATESTS_INT_MASK); 3003 3004 azx_stop_chip(chip); 3005 azx_enter_link_reset(chip); 3006 azx_clear_irq_pending(chip); 3007 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) 3008 hda_display_power(false); 3009 return 0; 3010 } 3011 3012 static int azx_runtime_resume(struct device *dev) 3013 { 3014 struct snd_card *card = dev_get_drvdata(dev); 3015 struct azx *chip = card->private_data; 3016 struct hda_bus *bus; 3017 struct hda_codec *codec; 3018 int status; 3019 3020 if (chip->disabled) 3021 return 0; 3022 3023 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME)) 3024 return 0; 3025 3026 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) 3027 hda_display_power(true); 3028 3029 /* Read STATESTS before controller reset */ 3030 status = azx_readw(chip, STATESTS); 3031 3032 azx_init_pci(chip); 3033 azx_init_chip(chip, 1); 3034 3035 bus = chip->bus; 3036 if (status && bus) { 3037 list_for_each_entry(codec, &bus->codec_list, list) 3038 if (status & (1 << codec->addr)) 3039 queue_delayed_work(codec->bus->workq, 3040 &codec->jackpoll_work, codec->jackpoll_interval); 3041 } 3042 3043 /* disable controller Wake Up event*/ 3044 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) & 3045 ~STATESTS_INT_MASK); 3046 3047 return 0; 3048 } 3049 3050 static int azx_runtime_idle(struct device *dev) 3051 { 3052 struct snd_card *card = dev_get_drvdata(dev); 3053 struct azx *chip = card->private_data; 3054 3055 if (chip->disabled) 3056 return 0; 3057 3058 if (!power_save_controller || 3059 !(chip->driver_caps & AZX_DCAPS_PM_RUNTIME)) 3060 return -EBUSY; 3061 3062 return 0; 3063 } 3064 3065 #endif /* CONFIG_PM_RUNTIME */ 3066 3067 #ifdef CONFIG_PM 3068 static const struct dev_pm_ops azx_pm = { 3069 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume) 3070 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle) 3071 }; 3072 3073 #define AZX_PM_OPS &azx_pm 3074 #else 3075 #define AZX_PM_OPS NULL 3076 #endif /* CONFIG_PM */ 3077 3078 3079 /* 3080 * reboot notifier for hang-up problem at power-down 3081 */ 3082 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf) 3083 { 3084 struct azx *chip = container_of(nb, struct azx, reboot_notifier); 3085 snd_hda_bus_reboot_notify(chip->bus); 3086 azx_stop_chip(chip); 3087 return NOTIFY_OK; 3088 } 3089 3090 static void azx_notifier_register(struct azx *chip) 3091 { 3092 chip->reboot_notifier.notifier_call = azx_halt; 3093 register_reboot_notifier(&chip->reboot_notifier); 3094 } 3095 3096 static void azx_notifier_unregister(struct azx *chip) 3097 { 3098 if (chip->reboot_notifier.notifier_call) 3099 unregister_reboot_notifier(&chip->reboot_notifier); 3100 } 3101 3102 static int azx_probe_continue(struct azx *chip); 3103 3104 #ifdef SUPPORT_VGA_SWITCHEROO 3105 static struct pci_dev *get_bound_vga(struct pci_dev *pci); 3106 3107 static void azx_vs_set_state(struct pci_dev *pci, 3108 enum vga_switcheroo_state state) 3109 { 3110 struct snd_card *card = pci_get_drvdata(pci); 3111 struct azx *chip = card->private_data; 3112 bool disabled; 3113 3114 wait_for_completion(&chip->probe_wait); 3115 if (chip->init_failed) 3116 return; 3117 3118 disabled = (state == VGA_SWITCHEROO_OFF); 3119 if (chip->disabled == disabled) 3120 return; 3121 3122 if (!chip->bus) { 3123 chip->disabled = disabled; 3124 if (!disabled) { 3125 snd_printk(KERN_INFO SFX 3126 "%s: Start delayed initialization\n", 3127 pci_name(chip->pci)); 3128 if (azx_probe_continue(chip) < 0) { 3129 snd_printk(KERN_ERR SFX 3130 "%s: initialization error\n", 3131 pci_name(chip->pci)); 3132 chip->init_failed = true; 3133 } 3134 } 3135 } else { 3136 snd_printk(KERN_INFO SFX 3137 "%s: %s via VGA-switcheroo\n", pci_name(chip->pci), 3138 disabled ? "Disabling" : "Enabling"); 3139 if (disabled) { 3140 pm_runtime_put_sync_suspend(&pci->dev); 3141 azx_suspend(&pci->dev); 3142 /* when we get suspended by vga switcheroo we end up in D3cold, 3143 * however we have no ACPI handle, so pci/acpi can't put us there, 3144 * put ourselves there */ 3145 pci->current_state = PCI_D3cold; 3146 chip->disabled = true; 3147 if (snd_hda_lock_devices(chip->bus)) 3148 snd_printk(KERN_WARNING SFX "%s: Cannot lock devices!\n", 3149 pci_name(chip->pci)); 3150 } else { 3151 snd_hda_unlock_devices(chip->bus); 3152 pm_runtime_get_noresume(&pci->dev); 3153 chip->disabled = false; 3154 azx_resume(&pci->dev); 3155 } 3156 } 3157 } 3158 3159 static bool azx_vs_can_switch(struct pci_dev *pci) 3160 { 3161 struct snd_card *card = pci_get_drvdata(pci); 3162 struct azx *chip = card->private_data; 3163 3164 wait_for_completion(&chip->probe_wait); 3165 if (chip->init_failed) 3166 return false; 3167 if (chip->disabled || !chip->bus) 3168 return true; 3169 if (snd_hda_lock_devices(chip->bus)) 3170 return false; 3171 snd_hda_unlock_devices(chip->bus); 3172 return true; 3173 } 3174 3175 static void init_vga_switcheroo(struct azx *chip) 3176 { 3177 struct pci_dev *p = get_bound_vga(chip->pci); 3178 if (p) { 3179 snd_printk(KERN_INFO SFX 3180 "%s: Handle VGA-switcheroo audio client\n", 3181 pci_name(chip->pci)); 3182 chip->use_vga_switcheroo = 1; 3183 pci_dev_put(p); 3184 } 3185 } 3186 3187 static const struct vga_switcheroo_client_ops azx_vs_ops = { 3188 .set_gpu_state = azx_vs_set_state, 3189 .can_switch = azx_vs_can_switch, 3190 }; 3191 3192 static int register_vga_switcheroo(struct azx *chip) 3193 { 3194 int err; 3195 3196 if (!chip->use_vga_switcheroo) 3197 return 0; 3198 /* FIXME: currently only handling DIS controller 3199 * is there any machine with two switchable HDMI audio controllers? 3200 */ 3201 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, 3202 VGA_SWITCHEROO_DIS, 3203 chip->bus != NULL); 3204 if (err < 0) 3205 return err; 3206 chip->vga_switcheroo_registered = 1; 3207 3208 /* register as an optimus hdmi audio power domain */ 3209 vga_switcheroo_init_domain_pm_optimus_hdmi_audio(&chip->pci->dev, &chip->hdmi_pm_domain); 3210 return 0; 3211 } 3212 #else 3213 #define init_vga_switcheroo(chip) /* NOP */ 3214 #define register_vga_switcheroo(chip) 0 3215 #define check_hdmi_disabled(pci) false 3216 #endif /* SUPPORT_VGA_SWITCHER */ 3217 3218 /* 3219 * destructor 3220 */ 3221 static int azx_free(struct azx *chip) 3222 { 3223 struct pci_dev *pci = chip->pci; 3224 int i; 3225 3226 if ((chip->driver_caps & AZX_DCAPS_PM_RUNTIME) 3227 && chip->running) 3228 pm_runtime_get_noresume(&pci->dev); 3229 3230 azx_del_card_list(chip); 3231 3232 azx_notifier_unregister(chip); 3233 3234 chip->init_failed = 1; /* to be sure */ 3235 complete_all(&chip->probe_wait); 3236 3237 if (use_vga_switcheroo(chip)) { 3238 if (chip->disabled && chip->bus) 3239 snd_hda_unlock_devices(chip->bus); 3240 if (chip->vga_switcheroo_registered) 3241 vga_switcheroo_unregister_client(chip->pci); 3242 } 3243 3244 if (chip->initialized) { 3245 azx_clear_irq_pending(chip); 3246 for (i = 0; i < chip->num_streams; i++) 3247 azx_stream_stop(chip, &chip->azx_dev[i]); 3248 azx_stop_chip(chip); 3249 } 3250 3251 if (chip->irq >= 0) 3252 free_irq(chip->irq, (void*)chip); 3253 if (chip->msi) 3254 pci_disable_msi(chip->pci); 3255 if (chip->remap_addr) 3256 iounmap(chip->remap_addr); 3257 3258 if (chip->azx_dev) { 3259 for (i = 0; i < chip->num_streams; i++) 3260 if (chip->azx_dev[i].bdl.area) { 3261 mark_pages_wc(chip, &chip->azx_dev[i].bdl, false); 3262 snd_dma_free_pages(&chip->azx_dev[i].bdl); 3263 } 3264 } 3265 if (chip->rb.area) { 3266 mark_pages_wc(chip, &chip->rb, false); 3267 snd_dma_free_pages(&chip->rb); 3268 } 3269 if (chip->posbuf.area) { 3270 mark_pages_wc(chip, &chip->posbuf, false); 3271 snd_dma_free_pages(&chip->posbuf); 3272 } 3273 if (chip->region_requested) 3274 pci_release_regions(chip->pci); 3275 pci_disable_device(chip->pci); 3276 kfree(chip->azx_dev); 3277 #ifdef CONFIG_SND_HDA_PATCH_LOADER 3278 if (chip->fw) 3279 release_firmware(chip->fw); 3280 #endif 3281 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) { 3282 hda_display_power(false); 3283 hda_i915_exit(); 3284 } 3285 kfree(chip); 3286 3287 return 0; 3288 } 3289 3290 static int azx_dev_free(struct snd_device *device) 3291 { 3292 return azx_free(device->device_data); 3293 } 3294 3295 #ifdef SUPPORT_VGA_SWITCHEROO 3296 /* 3297 * Check of disabled HDMI controller by vga-switcheroo 3298 */ 3299 static struct pci_dev *get_bound_vga(struct pci_dev *pci) 3300 { 3301 struct pci_dev *p; 3302 3303 /* check only discrete GPU */ 3304 switch (pci->vendor) { 3305 case PCI_VENDOR_ID_ATI: 3306 case PCI_VENDOR_ID_AMD: 3307 case PCI_VENDOR_ID_NVIDIA: 3308 if (pci->devfn == 1) { 3309 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus), 3310 pci->bus->number, 0); 3311 if (p) { 3312 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA) 3313 return p; 3314 pci_dev_put(p); 3315 } 3316 } 3317 break; 3318 } 3319 return NULL; 3320 } 3321 3322 static bool check_hdmi_disabled(struct pci_dev *pci) 3323 { 3324 bool vga_inactive = false; 3325 struct pci_dev *p = get_bound_vga(pci); 3326 3327 if (p) { 3328 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF) 3329 vga_inactive = true; 3330 pci_dev_put(p); 3331 } 3332 return vga_inactive; 3333 } 3334 #endif /* SUPPORT_VGA_SWITCHEROO */ 3335 3336 /* 3337 * white/black-listing for position_fix 3338 */ 3339 static struct snd_pci_quirk position_fix_list[] = { 3340 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB), 3341 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB), 3342 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB), 3343 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB), 3344 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB), 3345 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB), 3346 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB), 3347 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB), 3348 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB), 3349 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB), 3350 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB), 3351 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB), 3352 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB), 3353 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB), 3354 {} 3355 }; 3356 3357 static int check_position_fix(struct azx *chip, int fix) 3358 { 3359 const struct snd_pci_quirk *q; 3360 3361 switch (fix) { 3362 case POS_FIX_AUTO: 3363 case POS_FIX_LPIB: 3364 case POS_FIX_POSBUF: 3365 case POS_FIX_VIACOMBO: 3366 case POS_FIX_COMBO: 3367 return fix; 3368 } 3369 3370 q = snd_pci_quirk_lookup(chip->pci, position_fix_list); 3371 if (q) { 3372 printk(KERN_INFO 3373 "hda_intel: position_fix set to %d " 3374 "for device %04x:%04x\n", 3375 q->value, q->subvendor, q->subdevice); 3376 return q->value; 3377 } 3378 3379 /* Check VIA/ATI HD Audio Controller exist */ 3380 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) { 3381 snd_printd(SFX "%s: Using VIACOMBO position fix\n", pci_name(chip->pci)); 3382 return POS_FIX_VIACOMBO; 3383 } 3384 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) { 3385 snd_printd(SFX "%s: Using LPIB position fix\n", pci_name(chip->pci)); 3386 return POS_FIX_LPIB; 3387 } 3388 return POS_FIX_AUTO; 3389 } 3390 3391 /* 3392 * black-lists for probe_mask 3393 */ 3394 static struct snd_pci_quirk probe_mask_list[] = { 3395 /* Thinkpad often breaks the controller communication when accessing 3396 * to the non-working (or non-existing) modem codec slot. 3397 */ 3398 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01), 3399 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01), 3400 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01), 3401 /* broken BIOS */ 3402 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01), 3403 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */ 3404 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01), 3405 /* forced codec slots */ 3406 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103), 3407 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103), 3408 /* WinFast VP200 H (Teradici) user reported broken communication */ 3409 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101), 3410 {} 3411 }; 3412 3413 #define AZX_FORCE_CODEC_MASK 0x100 3414 3415 static void check_probe_mask(struct azx *chip, int dev) 3416 { 3417 const struct snd_pci_quirk *q; 3418 3419 chip->codec_probe_mask = probe_mask[dev]; 3420 if (chip->codec_probe_mask == -1) { 3421 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list); 3422 if (q) { 3423 printk(KERN_INFO 3424 "hda_intel: probe_mask set to 0x%x " 3425 "for device %04x:%04x\n", 3426 q->value, q->subvendor, q->subdevice); 3427 chip->codec_probe_mask = q->value; 3428 } 3429 } 3430 3431 /* check forced option */ 3432 if (chip->codec_probe_mask != -1 && 3433 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) { 3434 chip->codec_mask = chip->codec_probe_mask & 0xff; 3435 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n", 3436 chip->codec_mask); 3437 } 3438 } 3439 3440 /* 3441 * white/black-list for enable_msi 3442 */ 3443 static struct snd_pci_quirk msi_black_list[] = { 3444 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */ 3445 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */ 3446 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */ 3447 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */ 3448 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */ 3449 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */ 3450 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */ 3451 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */ 3452 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */ 3453 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */ 3454 {} 3455 }; 3456 3457 static void check_msi(struct azx *chip) 3458 { 3459 const struct snd_pci_quirk *q; 3460 3461 if (enable_msi >= 0) { 3462 chip->msi = !!enable_msi; 3463 return; 3464 } 3465 chip->msi = 1; /* enable MSI as default */ 3466 q = snd_pci_quirk_lookup(chip->pci, msi_black_list); 3467 if (q) { 3468 printk(KERN_INFO 3469 "hda_intel: msi for device %04x:%04x set to %d\n", 3470 q->subvendor, q->subdevice, q->value); 3471 chip->msi = q->value; 3472 return; 3473 } 3474 3475 /* NVidia chipsets seem to cause troubles with MSI */ 3476 if (chip->driver_caps & AZX_DCAPS_NO_MSI) { 3477 printk(KERN_INFO "hda_intel: Disabling MSI\n"); 3478 chip->msi = 0; 3479 } 3480 } 3481 3482 /* check the snoop mode availability */ 3483 static void azx_check_snoop_available(struct azx *chip) 3484 { 3485 bool snoop = chip->snoop; 3486 3487 switch (chip->driver_type) { 3488 case AZX_DRIVER_VIA: 3489 /* force to non-snoop mode for a new VIA controller 3490 * when BIOS is set 3491 */ 3492 if (snoop) { 3493 u8 val; 3494 pci_read_config_byte(chip->pci, 0x42, &val); 3495 if (!(val & 0x80) && chip->pci->revision == 0x30) 3496 snoop = false; 3497 } 3498 break; 3499 case AZX_DRIVER_ATIHDMI_NS: 3500 /* new ATI HDMI requires non-snoop */ 3501 snoop = false; 3502 break; 3503 case AZX_DRIVER_CTHDA: 3504 snoop = false; 3505 break; 3506 } 3507 3508 if (snoop != chip->snoop) { 3509 snd_printk(KERN_INFO SFX "%s: Force to %s mode\n", 3510 pci_name(chip->pci), snoop ? "snoop" : "non-snoop"); 3511 chip->snoop = snoop; 3512 } 3513 } 3514 3515 static void azx_probe_work(struct work_struct *work) 3516 { 3517 azx_probe_continue(container_of(work, struct azx, probe_work)); 3518 } 3519 3520 /* 3521 * constructor 3522 */ 3523 static int azx_create(struct snd_card *card, struct pci_dev *pci, 3524 int dev, unsigned int driver_caps, 3525 struct azx **rchip) 3526 { 3527 static struct snd_device_ops ops = { 3528 .dev_free = azx_dev_free, 3529 }; 3530 struct azx *chip; 3531 int err; 3532 3533 *rchip = NULL; 3534 3535 err = pci_enable_device(pci); 3536 if (err < 0) 3537 return err; 3538 3539 chip = kzalloc(sizeof(*chip), GFP_KERNEL); 3540 if (!chip) { 3541 snd_printk(KERN_ERR SFX "%s: Cannot allocate chip\n", pci_name(pci)); 3542 pci_disable_device(pci); 3543 return -ENOMEM; 3544 } 3545 3546 spin_lock_init(&chip->reg_lock); 3547 mutex_init(&chip->open_mutex); 3548 chip->card = card; 3549 chip->pci = pci; 3550 chip->irq = -1; 3551 chip->driver_caps = driver_caps; 3552 chip->driver_type = driver_caps & 0xff; 3553 check_msi(chip); 3554 chip->dev_index = dev; 3555 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work); 3556 INIT_LIST_HEAD(&chip->pcm_list); 3557 INIT_LIST_HEAD(&chip->list); 3558 init_vga_switcheroo(chip); 3559 init_completion(&chip->probe_wait); 3560 3561 chip->position_fix[0] = chip->position_fix[1] = 3562 check_position_fix(chip, position_fix[dev]); 3563 /* combo mode uses LPIB for playback */ 3564 if (chip->position_fix[0] == POS_FIX_COMBO) { 3565 chip->position_fix[0] = POS_FIX_LPIB; 3566 chip->position_fix[1] = POS_FIX_AUTO; 3567 } 3568 3569 check_probe_mask(chip, dev); 3570 3571 chip->single_cmd = single_cmd; 3572 chip->snoop = hda_snoop; 3573 azx_check_snoop_available(chip); 3574 3575 if (bdl_pos_adj[dev] < 0) { 3576 switch (chip->driver_type) { 3577 case AZX_DRIVER_ICH: 3578 case AZX_DRIVER_PCH: 3579 bdl_pos_adj[dev] = 1; 3580 break; 3581 default: 3582 bdl_pos_adj[dev] = 32; 3583 break; 3584 } 3585 } 3586 3587 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); 3588 if (err < 0) { 3589 snd_printk(KERN_ERR SFX "%s: Error creating device [card]!\n", 3590 pci_name(chip->pci)); 3591 azx_free(chip); 3592 return err; 3593 } 3594 3595 /* continue probing in work context as may trigger request module */ 3596 INIT_WORK(&chip->probe_work, azx_probe_work); 3597 3598 *rchip = chip; 3599 3600 return 0; 3601 } 3602 3603 static int azx_first_init(struct azx *chip) 3604 { 3605 int dev = chip->dev_index; 3606 struct pci_dev *pci = chip->pci; 3607 struct snd_card *card = chip->card; 3608 int i, err; 3609 unsigned short gcap; 3610 3611 #if BITS_PER_LONG != 64 3612 /* Fix up base address on ULI M5461 */ 3613 if (chip->driver_type == AZX_DRIVER_ULI) { 3614 u16 tmp3; 3615 pci_read_config_word(pci, 0x40, &tmp3); 3616 pci_write_config_word(pci, 0x40, tmp3 | 0x10); 3617 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0); 3618 } 3619 #endif 3620 3621 err = pci_request_regions(pci, "ICH HD audio"); 3622 if (err < 0) 3623 return err; 3624 chip->region_requested = 1; 3625 3626 chip->addr = pci_resource_start(pci, 0); 3627 chip->remap_addr = pci_ioremap_bar(pci, 0); 3628 if (chip->remap_addr == NULL) { 3629 snd_printk(KERN_ERR SFX "%s: ioremap error\n", pci_name(chip->pci)); 3630 return -ENXIO; 3631 } 3632 3633 if (chip->msi) 3634 if (pci_enable_msi(pci) < 0) 3635 chip->msi = 0; 3636 3637 if (azx_acquire_irq(chip, 0) < 0) 3638 return -EBUSY; 3639 3640 pci_set_master(pci); 3641 synchronize_irq(chip->irq); 3642 3643 gcap = azx_readw(chip, GCAP); 3644 snd_printdd(SFX "%s: chipset global capabilities = 0x%x\n", pci_name(chip->pci), gcap); 3645 3646 /* disable SB600 64bit support for safety */ 3647 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) { 3648 struct pci_dev *p_smbus; 3649 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI, 3650 PCI_DEVICE_ID_ATI_SBX00_SMBUS, 3651 NULL); 3652 if (p_smbus) { 3653 if (p_smbus->revision < 0x30) 3654 gcap &= ~ICH6_GCAP_64OK; 3655 pci_dev_put(p_smbus); 3656 } 3657 } 3658 3659 /* disable 64bit DMA address on some devices */ 3660 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) { 3661 snd_printd(SFX "%s: Disabling 64bit DMA\n", pci_name(chip->pci)); 3662 gcap &= ~ICH6_GCAP_64OK; 3663 } 3664 3665 /* disable buffer size rounding to 128-byte multiples if supported */ 3666 if (align_buffer_size >= 0) 3667 chip->align_buffer_size = !!align_buffer_size; 3668 else { 3669 if (chip->driver_caps & AZX_DCAPS_BUFSIZE) 3670 chip->align_buffer_size = 0; 3671 else if (chip->driver_caps & AZX_DCAPS_ALIGN_BUFSIZE) 3672 chip->align_buffer_size = 1; 3673 else 3674 chip->align_buffer_size = 1; 3675 } 3676 3677 /* allow 64bit DMA address if supported by H/W */ 3678 if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64))) 3679 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64)); 3680 else { 3681 pci_set_dma_mask(pci, DMA_BIT_MASK(32)); 3682 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32)); 3683 } 3684 3685 /* read number of streams from GCAP register instead of using 3686 * hardcoded value 3687 */ 3688 chip->capture_streams = (gcap >> 8) & 0x0f; 3689 chip->playback_streams = (gcap >> 12) & 0x0f; 3690 if (!chip->playback_streams && !chip->capture_streams) { 3691 /* gcap didn't give any info, switching to old method */ 3692 3693 switch (chip->driver_type) { 3694 case AZX_DRIVER_ULI: 3695 chip->playback_streams = ULI_NUM_PLAYBACK; 3696 chip->capture_streams = ULI_NUM_CAPTURE; 3697 break; 3698 case AZX_DRIVER_ATIHDMI: 3699 case AZX_DRIVER_ATIHDMI_NS: 3700 chip->playback_streams = ATIHDMI_NUM_PLAYBACK; 3701 chip->capture_streams = ATIHDMI_NUM_CAPTURE; 3702 break; 3703 case AZX_DRIVER_GENERIC: 3704 default: 3705 chip->playback_streams = ICH6_NUM_PLAYBACK; 3706 chip->capture_streams = ICH6_NUM_CAPTURE; 3707 break; 3708 } 3709 } 3710 chip->capture_index_offset = 0; 3711 chip->playback_index_offset = chip->capture_streams; 3712 chip->num_streams = chip->playback_streams + chip->capture_streams; 3713 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev), 3714 GFP_KERNEL); 3715 if (!chip->azx_dev) { 3716 snd_printk(KERN_ERR SFX "%s: cannot malloc azx_dev\n", pci_name(chip->pci)); 3717 return -ENOMEM; 3718 } 3719 3720 for (i = 0; i < chip->num_streams; i++) { 3721 dsp_lock_init(&chip->azx_dev[i]); 3722 /* allocate memory for the BDL for each stream */ 3723 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, 3724 snd_dma_pci_data(chip->pci), 3725 BDL_SIZE, &chip->azx_dev[i].bdl); 3726 if (err < 0) { 3727 snd_printk(KERN_ERR SFX "%s: cannot allocate BDL\n", pci_name(chip->pci)); 3728 return -ENOMEM; 3729 } 3730 mark_pages_wc(chip, &chip->azx_dev[i].bdl, true); 3731 } 3732 /* allocate memory for the position buffer */ 3733 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, 3734 snd_dma_pci_data(chip->pci), 3735 chip->num_streams * 8, &chip->posbuf); 3736 if (err < 0) { 3737 snd_printk(KERN_ERR SFX "%s: cannot allocate posbuf\n", pci_name(chip->pci)); 3738 return -ENOMEM; 3739 } 3740 mark_pages_wc(chip, &chip->posbuf, true); 3741 /* allocate CORB/RIRB */ 3742 err = azx_alloc_cmd_io(chip); 3743 if (err < 0) 3744 return err; 3745 3746 /* initialize streams */ 3747 azx_init_stream(chip); 3748 3749 /* initialize chip */ 3750 azx_init_pci(chip); 3751 azx_init_chip(chip, (probe_only[dev] & 2) == 0); 3752 3753 /* codec detection */ 3754 if (!chip->codec_mask) { 3755 snd_printk(KERN_ERR SFX "%s: no codecs found!\n", pci_name(chip->pci)); 3756 return -ENODEV; 3757 } 3758 3759 strcpy(card->driver, "HDA-Intel"); 3760 strlcpy(card->shortname, driver_short_names[chip->driver_type], 3761 sizeof(card->shortname)); 3762 snprintf(card->longname, sizeof(card->longname), 3763 "%s at 0x%lx irq %i", 3764 card->shortname, chip->addr, chip->irq); 3765 3766 return 0; 3767 } 3768 3769 static void power_down_all_codecs(struct azx *chip) 3770 { 3771 #ifdef CONFIG_PM 3772 /* The codecs were powered up in snd_hda_codec_new(). 3773 * Now all initialization done, so turn them down if possible 3774 */ 3775 struct hda_codec *codec; 3776 list_for_each_entry(codec, &chip->bus->codec_list, list) { 3777 snd_hda_power_down(codec); 3778 } 3779 #endif 3780 } 3781 3782 #ifdef CONFIG_SND_HDA_PATCH_LOADER 3783 /* callback from request_firmware_nowait() */ 3784 static void azx_firmware_cb(const struct firmware *fw, void *context) 3785 { 3786 struct snd_card *card = context; 3787 struct azx *chip = card->private_data; 3788 struct pci_dev *pci = chip->pci; 3789 3790 if (!fw) { 3791 snd_printk(KERN_ERR SFX "%s: Cannot load firmware, aborting\n", 3792 pci_name(chip->pci)); 3793 goto error; 3794 } 3795 3796 chip->fw = fw; 3797 if (!chip->disabled) { 3798 /* continue probing */ 3799 if (azx_probe_continue(chip)) 3800 goto error; 3801 } 3802 return; /* OK */ 3803 3804 error: 3805 snd_card_free(card); 3806 pci_set_drvdata(pci, NULL); 3807 } 3808 #endif 3809 3810 static int azx_probe(struct pci_dev *pci, 3811 const struct pci_device_id *pci_id) 3812 { 3813 static int dev; 3814 struct snd_card *card; 3815 struct azx *chip; 3816 bool schedule_probe; 3817 int err; 3818 3819 if (dev >= SNDRV_CARDS) 3820 return -ENODEV; 3821 if (!enable[dev]) { 3822 dev++; 3823 return -ENOENT; 3824 } 3825 3826 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE, 3827 0, &card); 3828 if (err < 0) { 3829 snd_printk(KERN_ERR "hda-intel: Error creating card!\n"); 3830 return err; 3831 } 3832 3833 err = azx_create(card, pci, dev, pci_id->driver_data, &chip); 3834 if (err < 0) 3835 goto out_free; 3836 card->private_data = chip; 3837 3838 pci_set_drvdata(pci, card); 3839 3840 err = register_vga_switcheroo(chip); 3841 if (err < 0) { 3842 snd_printk(KERN_ERR SFX 3843 "%s: Error registering VGA-switcheroo client\n", pci_name(pci)); 3844 goto out_free; 3845 } 3846 3847 if (check_hdmi_disabled(pci)) { 3848 snd_printk(KERN_INFO SFX "%s: VGA controller is disabled\n", 3849 pci_name(pci)); 3850 snd_printk(KERN_INFO SFX "%s: Delaying initialization\n", pci_name(pci)); 3851 chip->disabled = true; 3852 } 3853 3854 schedule_probe = !chip->disabled; 3855 3856 #ifdef CONFIG_SND_HDA_PATCH_LOADER 3857 if (patch[dev] && *patch[dev]) { 3858 snd_printk(KERN_ERR SFX "%s: Applying patch firmware '%s'\n", 3859 pci_name(pci), patch[dev]); 3860 err = request_firmware_nowait(THIS_MODULE, true, patch[dev], 3861 &pci->dev, GFP_KERNEL, card, 3862 azx_firmware_cb); 3863 if (err < 0) 3864 goto out_free; 3865 schedule_probe = false; /* continued in azx_firmware_cb() */ 3866 } 3867 #endif /* CONFIG_SND_HDA_PATCH_LOADER */ 3868 3869 #ifndef CONFIG_SND_HDA_I915 3870 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) 3871 snd_printk(KERN_ERR SFX "Haswell must build in CONFIG_SND_HDA_I915\n"); 3872 #endif 3873 3874 if (schedule_probe) 3875 schedule_work(&chip->probe_work); 3876 3877 dev++; 3878 if (chip->disabled) 3879 complete_all(&chip->probe_wait); 3880 return 0; 3881 3882 out_free: 3883 snd_card_free(card); 3884 return err; 3885 } 3886 3887 static int azx_probe_continue(struct azx *chip) 3888 { 3889 struct pci_dev *pci = chip->pci; 3890 int dev = chip->dev_index; 3891 int err; 3892 3893 /* Request power well for Haswell HDA controller and codec */ 3894 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) { 3895 #ifdef CONFIG_SND_HDA_I915 3896 err = hda_i915_init(); 3897 if (err < 0) { 3898 snd_printk(KERN_ERR SFX "Error request power-well from i915\n"); 3899 goto out_free; 3900 } 3901 #endif 3902 hda_display_power(true); 3903 } 3904 3905 err = azx_first_init(chip); 3906 if (err < 0) 3907 goto out_free; 3908 3909 #ifdef CONFIG_SND_HDA_INPUT_BEEP 3910 chip->beep_mode = beep_mode[dev]; 3911 #endif 3912 3913 /* create codec instances */ 3914 err = azx_codec_create(chip, model[dev]); 3915 if (err < 0) 3916 goto out_free; 3917 #ifdef CONFIG_SND_HDA_PATCH_LOADER 3918 if (chip->fw) { 3919 err = snd_hda_load_patch(chip->bus, chip->fw->size, 3920 chip->fw->data); 3921 if (err < 0) 3922 goto out_free; 3923 #ifndef CONFIG_PM 3924 release_firmware(chip->fw); /* no longer needed */ 3925 chip->fw = NULL; 3926 #endif 3927 } 3928 #endif 3929 if ((probe_only[dev] & 1) == 0) { 3930 err = azx_codec_configure(chip); 3931 if (err < 0) 3932 goto out_free; 3933 } 3934 3935 /* create PCM streams */ 3936 err = snd_hda_build_pcms(chip->bus); 3937 if (err < 0) 3938 goto out_free; 3939 3940 /* create mixer controls */ 3941 err = azx_mixer_create(chip); 3942 if (err < 0) 3943 goto out_free; 3944 3945 err = snd_card_register(chip->card); 3946 if (err < 0) 3947 goto out_free; 3948 3949 chip->running = 1; 3950 power_down_all_codecs(chip); 3951 azx_notifier_register(chip); 3952 azx_add_card_list(chip); 3953 if ((chip->driver_caps & AZX_DCAPS_PM_RUNTIME) || chip->use_vga_switcheroo) 3954 pm_runtime_put_noidle(&pci->dev); 3955 3956 out_free: 3957 if (err < 0) 3958 chip->init_failed = 1; 3959 complete_all(&chip->probe_wait); 3960 return err; 3961 } 3962 3963 static void azx_remove(struct pci_dev *pci) 3964 { 3965 struct snd_card *card = pci_get_drvdata(pci); 3966 3967 if (card) 3968 snd_card_free(card); 3969 } 3970 3971 /* PCI IDs */ 3972 static DEFINE_PCI_DEVICE_TABLE(azx_ids) = { 3973 /* CPT */ 3974 { PCI_DEVICE(0x8086, 0x1c20), 3975 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 3976 /* PBG */ 3977 { PCI_DEVICE(0x8086, 0x1d20), 3978 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 3979 /* Panther Point */ 3980 { PCI_DEVICE(0x8086, 0x1e20), 3981 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 3982 /* Lynx Point */ 3983 { PCI_DEVICE(0x8086, 0x8c20), 3984 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 3985 /* Wellsburg */ 3986 { PCI_DEVICE(0x8086, 0x8d20), 3987 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 3988 { PCI_DEVICE(0x8086, 0x8d21), 3989 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 3990 /* Lynx Point-LP */ 3991 { PCI_DEVICE(0x8086, 0x9c20), 3992 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 3993 /* Lynx Point-LP */ 3994 { PCI_DEVICE(0x8086, 0x9c21), 3995 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 3996 /* Wildcat Point-LP */ 3997 { PCI_DEVICE(0x8086, 0x9ca0), 3998 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 3999 /* Haswell */ 4000 { PCI_DEVICE(0x8086, 0x0a0c), 4001 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 4002 { PCI_DEVICE(0x8086, 0x0c0c), 4003 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 4004 { PCI_DEVICE(0x8086, 0x0d0c), 4005 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 4006 /* Broadwell */ 4007 { PCI_DEVICE(0x8086, 0x160c), 4008 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 4009 /* 5 Series/3400 */ 4010 { PCI_DEVICE(0x8086, 0x3b56), 4011 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM }, 4012 /* Poulsbo */ 4013 { PCI_DEVICE(0x8086, 0x811b), 4014 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM }, 4015 /* Oaktrail */ 4016 { PCI_DEVICE(0x8086, 0x080a), 4017 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM }, 4018 /* BayTrail */ 4019 { PCI_DEVICE(0x8086, 0x0f04), 4020 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 4021 /* ICH */ 4022 { PCI_DEVICE(0x8086, 0x2668), 4023 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC | 4024 AZX_DCAPS_BUFSIZE }, /* ICH6 */ 4025 { PCI_DEVICE(0x8086, 0x27d8), 4026 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC | 4027 AZX_DCAPS_BUFSIZE }, /* ICH7 */ 4028 { PCI_DEVICE(0x8086, 0x269a), 4029 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC | 4030 AZX_DCAPS_BUFSIZE }, /* ESB2 */ 4031 { PCI_DEVICE(0x8086, 0x284b), 4032 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC | 4033 AZX_DCAPS_BUFSIZE }, /* ICH8 */ 4034 { PCI_DEVICE(0x8086, 0x293e), 4035 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC | 4036 AZX_DCAPS_BUFSIZE }, /* ICH9 */ 4037 { PCI_DEVICE(0x8086, 0x293f), 4038 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC | 4039 AZX_DCAPS_BUFSIZE }, /* ICH9 */ 4040 { PCI_DEVICE(0x8086, 0x3a3e), 4041 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC | 4042 AZX_DCAPS_BUFSIZE }, /* ICH10 */ 4043 { PCI_DEVICE(0x8086, 0x3a6e), 4044 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC | 4045 AZX_DCAPS_BUFSIZE }, /* ICH10 */ 4046 /* Generic Intel */ 4047 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID), 4048 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 4049 .class_mask = 0xffffff, 4050 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE }, 4051 /* ATI SB 450/600/700/800/900 */ 4052 { PCI_DEVICE(0x1002, 0x437b), 4053 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, 4054 { PCI_DEVICE(0x1002, 0x4383), 4055 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, 4056 /* AMD Hudson */ 4057 { PCI_DEVICE(0x1022, 0x780d), 4058 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB }, 4059 /* ATI HDMI */ 4060 { PCI_DEVICE(0x1002, 0x793b), 4061 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 4062 { PCI_DEVICE(0x1002, 0x7919), 4063 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 4064 { PCI_DEVICE(0x1002, 0x960f), 4065 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 4066 { PCI_DEVICE(0x1002, 0x970f), 4067 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 4068 { PCI_DEVICE(0x1002, 0xaa00), 4069 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 4070 { PCI_DEVICE(0x1002, 0xaa08), 4071 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 4072 { PCI_DEVICE(0x1002, 0xaa10), 4073 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 4074 { PCI_DEVICE(0x1002, 0xaa18), 4075 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 4076 { PCI_DEVICE(0x1002, 0xaa20), 4077 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 4078 { PCI_DEVICE(0x1002, 0xaa28), 4079 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 4080 { PCI_DEVICE(0x1002, 0xaa30), 4081 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 4082 { PCI_DEVICE(0x1002, 0xaa38), 4083 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 4084 { PCI_DEVICE(0x1002, 0xaa40), 4085 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 4086 { PCI_DEVICE(0x1002, 0xaa48), 4087 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 4088 { PCI_DEVICE(0x1002, 0xaa50), 4089 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 4090 { PCI_DEVICE(0x1002, 0xaa58), 4091 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 4092 { PCI_DEVICE(0x1002, 0xaa60), 4093 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 4094 { PCI_DEVICE(0x1002, 0xaa68), 4095 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 4096 { PCI_DEVICE(0x1002, 0xaa80), 4097 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 4098 { PCI_DEVICE(0x1002, 0xaa88), 4099 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 4100 { PCI_DEVICE(0x1002, 0xaa90), 4101 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 4102 { PCI_DEVICE(0x1002, 0xaa98), 4103 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 4104 { PCI_DEVICE(0x1002, 0x9902), 4105 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI }, 4106 { PCI_DEVICE(0x1002, 0xaaa0), 4107 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI }, 4108 { PCI_DEVICE(0x1002, 0xaaa8), 4109 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI }, 4110 { PCI_DEVICE(0x1002, 0xaab0), 4111 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI }, 4112 /* VIA VT8251/VT8237A */ 4113 { PCI_DEVICE(0x1106, 0x3288), 4114 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA }, 4115 /* VIA GFX VT7122/VX900 */ 4116 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC }, 4117 /* VIA GFX VT6122/VX11 */ 4118 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC }, 4119 /* SIS966 */ 4120 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS }, 4121 /* ULI M5461 */ 4122 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI }, 4123 /* NVIDIA MCP */ 4124 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID), 4125 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 4126 .class_mask = 0xffffff, 4127 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA }, 4128 /* Teradici */ 4129 { PCI_DEVICE(0x6549, 0x1200), 4130 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, 4131 { PCI_DEVICE(0x6549, 0x2200), 4132 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, 4133 /* Creative X-Fi (CA0110-IBG) */ 4134 /* CTHDA chips */ 4135 { PCI_DEVICE(0x1102, 0x0010), 4136 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, 4137 { PCI_DEVICE(0x1102, 0x0012), 4138 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, 4139 #if !IS_ENABLED(CONFIG_SND_CTXFI) 4140 /* the following entry conflicts with snd-ctxfi driver, 4141 * as ctxfi driver mutates from HD-audio to native mode with 4142 * a special command sequence. 4143 */ 4144 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID), 4145 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 4146 .class_mask = 0xffffff, 4147 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | 4148 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB }, 4149 #else 4150 /* this entry seems still valid -- i.e. without emu20kx chip */ 4151 { PCI_DEVICE(0x1102, 0x0009), 4152 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | 4153 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB }, 4154 #endif 4155 /* Vortex86MX */ 4156 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC }, 4157 /* VMware HDAudio */ 4158 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC }, 4159 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */ 4160 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID), 4161 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 4162 .class_mask = 0xffffff, 4163 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, 4164 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID), 4165 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 4166 .class_mask = 0xffffff, 4167 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, 4168 { 0, } 4169 }; 4170 MODULE_DEVICE_TABLE(pci, azx_ids); 4171 4172 /* pci_driver definition */ 4173 static struct pci_driver azx_driver = { 4174 .name = KBUILD_MODNAME, 4175 .id_table = azx_ids, 4176 .probe = azx_probe, 4177 .remove = azx_remove, 4178 .driver = { 4179 .pm = AZX_PM_OPS, 4180 }, 4181 }; 4182 4183 module_pci_driver(azx_driver); 4184