1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * 4 * hda_intel.c - Implementation of primary alsa driver code base 5 * for Intel HD Audio. 6 * 7 * Copyright(c) 2004 Intel Corporation 8 * 9 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> 10 * PeiSen Hou <pshou@realtek.com.tw> 11 * 12 * CONTACTS: 13 * 14 * Matt Jared matt.jared@intel.com 15 * Andy Kopp andy.kopp@intel.com 16 * Dan Kogan dan.d.kogan@intel.com 17 * 18 * CHANGES: 19 * 20 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou 21 */ 22 23 #include <linux/delay.h> 24 #include <linux/interrupt.h> 25 #include <linux/kernel.h> 26 #include <linux/module.h> 27 #include <linux/dma-mapping.h> 28 #include <linux/moduleparam.h> 29 #include <linux/init.h> 30 #include <linux/slab.h> 31 #include <linux/pci.h> 32 #include <linux/mutex.h> 33 #include <linux/io.h> 34 #include <linux/pm_runtime.h> 35 #include <linux/clocksource.h> 36 #include <linux/time.h> 37 #include <linux/completion.h> 38 #include <linux/acpi.h> 39 #include <linux/pgtable.h> 40 41 #ifdef CONFIG_X86 42 /* for snoop control */ 43 #include <asm/set_memory.h> 44 #include <asm/cpufeature.h> 45 #endif 46 #include <sound/core.h> 47 #include <sound/initval.h> 48 #include <sound/hdaudio.h> 49 #include <sound/hda_i915.h> 50 #include <sound/intel-dsp-config.h> 51 #include <linux/vgaarb.h> 52 #include <linux/vga_switcheroo.h> 53 #include <linux/apple-gmux.h> 54 #include <linux/firmware.h> 55 #include <sound/hda_codec.h> 56 #include "hda_controller.h" 57 #include "hda_intel.h" 58 59 #define CREATE_TRACE_POINTS 60 #include "hda_intel_trace.h" 61 62 /* position fix mode */ 63 enum { 64 POS_FIX_AUTO, 65 POS_FIX_LPIB, 66 POS_FIX_POSBUF, 67 POS_FIX_VIACOMBO, 68 POS_FIX_COMBO, 69 POS_FIX_SKL, 70 POS_FIX_FIFO, 71 }; 72 73 /* Defines for ATI HD Audio support in SB450 south bridge */ 74 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42 75 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02 76 77 /* Defines for Nvidia HDA support */ 78 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e 79 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f 80 #define NVIDIA_HDA_ISTRM_COH 0x4d 81 #define NVIDIA_HDA_OSTRM_COH 0x4c 82 #define NVIDIA_HDA_ENABLE_COHBIT 0x01 83 84 /* Defines for Intel SCH HDA snoop control */ 85 #define INTEL_HDA_CGCTL 0x48 86 #define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6) 87 #define INTEL_SCH_HDA_DEVC 0x78 88 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11) 89 90 /* max number of SDs */ 91 /* ICH, ATI and VIA have 4 playback and 4 capture */ 92 #define ICH6_NUM_CAPTURE 4 93 #define ICH6_NUM_PLAYBACK 4 94 95 /* ULI has 6 playback and 5 capture */ 96 #define ULI_NUM_CAPTURE 5 97 #define ULI_NUM_PLAYBACK 6 98 99 /* ATI HDMI may have up to 8 playbacks and 0 capture */ 100 #define ATIHDMI_NUM_CAPTURE 0 101 #define ATIHDMI_NUM_PLAYBACK 8 102 103 104 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; 105 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; 106 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; 107 static char *model[SNDRV_CARDS]; 108 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 109 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 110 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 111 static int probe_only[SNDRV_CARDS]; 112 static int jackpoll_ms[SNDRV_CARDS]; 113 static int single_cmd = -1; 114 static int enable_msi = -1; 115 #ifdef CONFIG_SND_HDA_PATCH_LOADER 116 static char *patch[SNDRV_CARDS]; 117 #endif 118 #ifdef CONFIG_SND_HDA_INPUT_BEEP 119 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = 120 CONFIG_SND_HDA_INPUT_BEEP_MODE}; 121 #endif 122 static bool dmic_detect = 1; 123 static bool ctl_dev_id = IS_ENABLED(CONFIG_SND_HDA_CTL_DEV_ID) ? 1 : 0; 124 125 module_param_array(index, int, NULL, 0444); 126 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface."); 127 module_param_array(id, charp, NULL, 0444); 128 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface."); 129 module_param_array(enable, bool, NULL, 0444); 130 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface."); 131 module_param_array(model, charp, NULL, 0444); 132 MODULE_PARM_DESC(model, "Use the given board model."); 133 module_param_array(position_fix, int, NULL, 0444); 134 MODULE_PARM_DESC(position_fix, "DMA pointer read method." 135 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+, 6 = FIFO)."); 136 module_param_array(bdl_pos_adj, int, NULL, 0644); 137 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset."); 138 module_param_array(probe_mask, int, NULL, 0444); 139 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1)."); 140 module_param_array(probe_only, int, NULL, 0444); 141 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization."); 142 module_param_array(jackpoll_ms, int, NULL, 0444); 143 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)"); 144 module_param(single_cmd, bint, 0444); 145 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs " 146 "(for debugging only)."); 147 module_param(enable_msi, bint, 0444); 148 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)"); 149 #ifdef CONFIG_SND_HDA_PATCH_LOADER 150 module_param_array(patch, charp, NULL, 0444); 151 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface."); 152 #endif 153 #ifdef CONFIG_SND_HDA_INPUT_BEEP 154 module_param_array(beep_mode, bool, NULL, 0444); 155 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode " 156 "(0=off, 1=on) (default=1)."); 157 #endif 158 module_param(dmic_detect, bool, 0444); 159 MODULE_PARM_DESC(dmic_detect, "Allow DSP driver selection (bypass this driver) " 160 "(0=off, 1=on) (default=1); " 161 "deprecated, use snd-intel-dspcfg.dsp_driver option instead"); 162 module_param(ctl_dev_id, bool, 0444); 163 MODULE_PARM_DESC(ctl_dev_id, "Use control device identifier (based on codec address)."); 164 165 #ifdef CONFIG_PM 166 static int param_set_xint(const char *val, const struct kernel_param *kp); 167 static const struct kernel_param_ops param_ops_xint = { 168 .set = param_set_xint, 169 .get = param_get_int, 170 }; 171 #define param_check_xint param_check_int 172 173 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT; 174 module_param(power_save, xint, 0644); 175 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout " 176 "(in second, 0 = disable)."); 177 178 static bool pm_blacklist = true; 179 module_param(pm_blacklist, bool, 0644); 180 MODULE_PARM_DESC(pm_blacklist, "Enable power-management denylist"); 181 182 /* reset the HD-audio controller in power save mode. 183 * this may give more power-saving, but will take longer time to 184 * wake up. 185 */ 186 static bool power_save_controller = 1; 187 module_param(power_save_controller, bool, 0644); 188 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode."); 189 #else /* CONFIG_PM */ 190 #define power_save 0 191 #define pm_blacklist false 192 #define power_save_controller false 193 #endif /* CONFIG_PM */ 194 195 static int align_buffer_size = -1; 196 module_param(align_buffer_size, bint, 0644); 197 MODULE_PARM_DESC(align_buffer_size, 198 "Force buffer and period sizes to be multiple of 128 bytes."); 199 200 #ifdef CONFIG_X86 201 static int hda_snoop = -1; 202 module_param_named(snoop, hda_snoop, bint, 0444); 203 MODULE_PARM_DESC(snoop, "Enable/disable snooping"); 204 #else 205 #define hda_snoop true 206 #endif 207 208 209 MODULE_LICENSE("GPL"); 210 MODULE_DESCRIPTION("Intel HDA driver"); 211 212 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO) 213 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI) 214 #define SUPPORT_VGA_SWITCHEROO 215 #endif 216 #endif 217 218 219 /* 220 */ 221 222 /* driver types */ 223 enum { 224 AZX_DRIVER_ICH, 225 AZX_DRIVER_PCH, 226 AZX_DRIVER_SCH, 227 AZX_DRIVER_SKL, 228 AZX_DRIVER_HDMI, 229 AZX_DRIVER_ATI, 230 AZX_DRIVER_ATIHDMI, 231 AZX_DRIVER_ATIHDMI_NS, 232 AZX_DRIVER_GFHDMI, 233 AZX_DRIVER_VIA, 234 AZX_DRIVER_SIS, 235 AZX_DRIVER_ULI, 236 AZX_DRIVER_NVIDIA, 237 AZX_DRIVER_TERA, 238 AZX_DRIVER_CTX, 239 AZX_DRIVER_CTHDA, 240 AZX_DRIVER_CMEDIA, 241 AZX_DRIVER_ZHAOXIN, 242 AZX_DRIVER_LOONGSON, 243 AZX_DRIVER_GENERIC, 244 AZX_NUM_DRIVERS, /* keep this as last entry */ 245 }; 246 247 #define azx_get_snoop_type(chip) \ 248 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10) 249 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10) 250 251 /* quirks for old Intel chipsets */ 252 #define AZX_DCAPS_INTEL_ICH \ 253 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE) 254 255 /* quirks for Intel PCH */ 256 #define AZX_DCAPS_INTEL_PCH_BASE \ 257 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\ 258 AZX_DCAPS_SNOOP_TYPE(SCH)) 259 260 /* PCH up to IVB; no runtime PM; bind with i915 gfx */ 261 #define AZX_DCAPS_INTEL_PCH_NOPM \ 262 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT) 263 264 /* PCH for HSW/BDW; with runtime PM */ 265 /* no i915 binding for this as HSW/BDW has another controller for HDMI */ 266 #define AZX_DCAPS_INTEL_PCH \ 267 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME) 268 269 /* HSW HDMI */ 270 #define AZX_DCAPS_INTEL_HASWELL \ 271 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\ 272 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\ 273 AZX_DCAPS_SNOOP_TYPE(SCH)) 274 275 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */ 276 #define AZX_DCAPS_INTEL_BROADWELL \ 277 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\ 278 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\ 279 AZX_DCAPS_SNOOP_TYPE(SCH)) 280 281 #define AZX_DCAPS_INTEL_BAYTRAIL \ 282 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT) 283 284 #define AZX_DCAPS_INTEL_BRASWELL \ 285 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\ 286 AZX_DCAPS_I915_COMPONENT) 287 288 #define AZX_DCAPS_INTEL_SKYLAKE \ 289 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\ 290 AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT) 291 292 #define AZX_DCAPS_INTEL_BROXTON AZX_DCAPS_INTEL_SKYLAKE 293 294 #define AZX_DCAPS_INTEL_LNL \ 295 (AZX_DCAPS_INTEL_SKYLAKE | AZX_DCAPS_PIO_COMMANDS) 296 297 /* quirks for ATI SB / AMD Hudson */ 298 #define AZX_DCAPS_PRESET_ATI_SB \ 299 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB |\ 300 AZX_DCAPS_SNOOP_TYPE(ATI)) 301 302 /* quirks for ATI/AMD HDMI */ 303 #define AZX_DCAPS_PRESET_ATI_HDMI \ 304 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB|\ 305 AZX_DCAPS_NO_MSI64) 306 307 /* quirks for ATI HDMI with snoop off */ 308 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \ 309 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF) 310 311 /* quirks for AMD SB */ 312 #define AZX_DCAPS_PRESET_AMD_SB \ 313 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_AMD_WORKAROUND |\ 314 AZX_DCAPS_SNOOP_TYPE(ATI) | AZX_DCAPS_PM_RUNTIME |\ 315 AZX_DCAPS_RETRY_PROBE) 316 317 /* quirks for Nvidia */ 318 #define AZX_DCAPS_PRESET_NVIDIA \ 319 (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\ 320 AZX_DCAPS_SNOOP_TYPE(NVIDIA)) 321 322 #define AZX_DCAPS_PRESET_CTHDA \ 323 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\ 324 AZX_DCAPS_NO_64BIT |\ 325 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF) 326 327 /* 328 * vga_switcheroo support 329 */ 330 #ifdef SUPPORT_VGA_SWITCHEROO 331 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo) 332 #define needs_eld_notify_link(chip) ((chip)->bus.keep_power) 333 #else 334 #define use_vga_switcheroo(chip) 0 335 #define needs_eld_notify_link(chip) false 336 #endif 337 338 static const char * const driver_short_names[] = { 339 [AZX_DRIVER_ICH] = "HDA Intel", 340 [AZX_DRIVER_PCH] = "HDA Intel PCH", 341 [AZX_DRIVER_SCH] = "HDA Intel MID", 342 [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */ 343 [AZX_DRIVER_HDMI] = "HDA Intel HDMI", 344 [AZX_DRIVER_ATI] = "HDA ATI SB", 345 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI", 346 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI", 347 [AZX_DRIVER_GFHDMI] = "HDA GF HDMI", 348 [AZX_DRIVER_VIA] = "HDA VIA VT82xx", 349 [AZX_DRIVER_SIS] = "HDA SIS966", 350 [AZX_DRIVER_ULI] = "HDA ULI M5461", 351 [AZX_DRIVER_NVIDIA] = "HDA NVidia", 352 [AZX_DRIVER_TERA] = "HDA Teradici", 353 [AZX_DRIVER_CTX] = "HDA Creative", 354 [AZX_DRIVER_CTHDA] = "HDA Creative", 355 [AZX_DRIVER_CMEDIA] = "HDA C-Media", 356 [AZX_DRIVER_ZHAOXIN] = "HDA Zhaoxin", 357 [AZX_DRIVER_LOONGSON] = "HDA Loongson", 358 [AZX_DRIVER_GENERIC] = "HD-Audio Generic", 359 }; 360 361 static int azx_acquire_irq(struct azx *chip, int do_disconnect); 362 static void set_default_power_save(struct azx *chip); 363 364 /* 365 * initialize the PCI registers 366 */ 367 /* update bits in a PCI register byte */ 368 static void update_pci_byte(struct pci_dev *pci, unsigned int reg, 369 unsigned char mask, unsigned char val) 370 { 371 unsigned char data; 372 373 pci_read_config_byte(pci, reg, &data); 374 data &= ~mask; 375 data |= (val & mask); 376 pci_write_config_byte(pci, reg, data); 377 } 378 379 static void azx_init_pci(struct azx *chip) 380 { 381 int snoop_type = azx_get_snoop_type(chip); 382 383 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44) 384 * TCSEL == Traffic Class Select Register, which sets PCI express QOS 385 * Ensuring these bits are 0 clears playback static on some HD Audio 386 * codecs. 387 * The PCI register TCSEL is defined in the Intel manuals. 388 */ 389 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) { 390 dev_dbg(chip->card->dev, "Clearing TCSEL\n"); 391 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0); 392 } 393 394 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio, 395 * we need to enable snoop. 396 */ 397 if (snoop_type == AZX_SNOOP_TYPE_ATI) { 398 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n", 399 azx_snoop(chip)); 400 update_pci_byte(chip->pci, 401 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07, 402 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0); 403 } 404 405 /* For NVIDIA HDA, enable snoop */ 406 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) { 407 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n", 408 azx_snoop(chip)); 409 update_pci_byte(chip->pci, 410 NVIDIA_HDA_TRANSREG_ADDR, 411 0x0f, NVIDIA_HDA_ENABLE_COHBITS); 412 update_pci_byte(chip->pci, 413 NVIDIA_HDA_ISTRM_COH, 414 0x01, NVIDIA_HDA_ENABLE_COHBIT); 415 update_pci_byte(chip->pci, 416 NVIDIA_HDA_OSTRM_COH, 417 0x01, NVIDIA_HDA_ENABLE_COHBIT); 418 } 419 420 /* Enable SCH/PCH snoop if needed */ 421 if (snoop_type == AZX_SNOOP_TYPE_SCH) { 422 unsigned short snoop; 423 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop); 424 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) || 425 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) { 426 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP; 427 if (!azx_snoop(chip)) 428 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP; 429 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop); 430 pci_read_config_word(chip->pci, 431 INTEL_SCH_HDA_DEVC, &snoop); 432 } 433 dev_dbg(chip->card->dev, "SCH snoop: %s\n", 434 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ? 435 "Disabled" : "Enabled"); 436 } 437 } 438 439 /* 440 * In BXT-P A0, HD-Audio DMA requests is later than expected, 441 * and makes an audio stream sensitive to system latencies when 442 * 24/32 bits are playing. 443 * Adjusting threshold of DMA fifo to force the DMA request 444 * sooner to improve latency tolerance at the expense of power. 445 */ 446 static void bxt_reduce_dma_latency(struct azx *chip) 447 { 448 u32 val; 449 450 val = azx_readl(chip, VS_EM4L); 451 val &= (0x3 << 20); 452 azx_writel(chip, VS_EM4L, val); 453 } 454 455 /* 456 * ML_LCAP bits: 457 * bit 0: 6 MHz Supported 458 * bit 1: 12 MHz Supported 459 * bit 2: 24 MHz Supported 460 * bit 3: 48 MHz Supported 461 * bit 4: 96 MHz Supported 462 * bit 5: 192 MHz Supported 463 */ 464 static int intel_get_lctl_scf(struct azx *chip) 465 { 466 struct hdac_bus *bus = azx_bus(chip); 467 static const int preferred_bits[] = { 2, 3, 1, 4, 5 }; 468 u32 val, t; 469 int i; 470 471 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP); 472 473 for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) { 474 t = preferred_bits[i]; 475 if (val & (1 << t)) 476 return t; 477 } 478 479 dev_warn(chip->card->dev, "set audio clock frequency to 6MHz"); 480 return 0; 481 } 482 483 static int intel_ml_lctl_set_power(struct azx *chip, int state) 484 { 485 struct hdac_bus *bus = azx_bus(chip); 486 u32 val; 487 int timeout; 488 489 /* 490 * Changes to LCTL.SCF are only needed for the first multi-link dealing 491 * with external codecs 492 */ 493 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 494 val &= ~AZX_ML_LCTL_SPA; 495 val |= state << AZX_ML_LCTL_SPA_SHIFT; 496 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 497 /* wait for CPA */ 498 timeout = 50; 499 while (timeout) { 500 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) & 501 AZX_ML_LCTL_CPA) == (state << AZX_ML_LCTL_CPA_SHIFT)) 502 return 0; 503 timeout--; 504 udelay(10); 505 } 506 507 return -1; 508 } 509 510 static void intel_init_lctl(struct azx *chip) 511 { 512 struct hdac_bus *bus = azx_bus(chip); 513 u32 val; 514 int ret; 515 516 /* 0. check lctl register value is correct or not */ 517 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 518 /* only perform additional configurations if the SCF is initially based on 6MHz */ 519 if ((val & AZX_ML_LCTL_SCF) != 0) 520 return; 521 522 /* 523 * Before operating on SPA, CPA must match SPA. 524 * Any deviation may result in undefined behavior. 525 */ 526 if (((val & AZX_ML_LCTL_SPA) >> AZX_ML_LCTL_SPA_SHIFT) != 527 ((val & AZX_ML_LCTL_CPA) >> AZX_ML_LCTL_CPA_SHIFT)) 528 return; 529 530 /* 1. turn link down: set SPA to 0 and wait CPA to 0 */ 531 ret = intel_ml_lctl_set_power(chip, 0); 532 udelay(100); 533 if (ret) 534 goto set_spa; 535 536 /* 2. update SCF to select an audio clock different from 6MHz */ 537 val &= ~AZX_ML_LCTL_SCF; 538 val |= intel_get_lctl_scf(chip); 539 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 540 541 set_spa: 542 /* 4. turn link up: set SPA to 1 and wait CPA to 1 */ 543 intel_ml_lctl_set_power(chip, 1); 544 udelay(100); 545 } 546 547 static void hda_intel_init_chip(struct azx *chip, bool full_reset) 548 { 549 struct hdac_bus *bus = azx_bus(chip); 550 struct pci_dev *pci = chip->pci; 551 u32 val; 552 553 snd_hdac_set_codec_wakeup(bus, true); 554 if (chip->driver_type == AZX_DRIVER_SKL) { 555 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val); 556 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE; 557 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val); 558 } 559 azx_init_chip(chip, full_reset); 560 if (chip->driver_type == AZX_DRIVER_SKL) { 561 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val); 562 val = val | INTEL_HDA_CGCTL_MISCBDCGE; 563 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val); 564 } 565 566 snd_hdac_set_codec_wakeup(bus, false); 567 568 /* reduce dma latency to avoid noise */ 569 if (HDA_CONTROLLER_IS_APL(pci)) 570 bxt_reduce_dma_latency(chip); 571 572 if (bus->mlcap != NULL) 573 intel_init_lctl(chip); 574 } 575 576 /* calculate runtime delay from LPIB */ 577 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev, 578 unsigned int pos) 579 { 580 struct snd_pcm_substream *substream = azx_dev->core.substream; 581 int stream = substream->stream; 582 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev); 583 int delay; 584 585 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 586 delay = pos - lpib_pos; 587 else 588 delay = lpib_pos - pos; 589 if (delay < 0) { 590 if (delay >= azx_dev->core.delay_negative_threshold) 591 delay = 0; 592 else 593 delay += azx_dev->core.bufsize; 594 } 595 596 if (delay >= azx_dev->core.period_bytes) { 597 dev_info(chip->card->dev, 598 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n", 599 delay, azx_dev->core.period_bytes); 600 delay = 0; 601 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY; 602 chip->get_delay[stream] = NULL; 603 } 604 605 return bytes_to_frames(substream->runtime, delay); 606 } 607 608 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev); 609 610 /* called from IRQ */ 611 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev) 612 { 613 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 614 int ok; 615 616 ok = azx_position_ok(chip, azx_dev); 617 if (ok == 1) { 618 azx_dev->irq_pending = 0; 619 return ok; 620 } else if (ok == 0) { 621 /* bogus IRQ, process it later */ 622 azx_dev->irq_pending = 1; 623 schedule_work(&hda->irq_pending_work); 624 } 625 return 0; 626 } 627 628 #define display_power(chip, enable) \ 629 snd_hdac_display_power(azx_bus(chip), HDA_CODEC_IDX_CONTROLLER, enable) 630 631 /* 632 * Check whether the current DMA position is acceptable for updating 633 * periods. Returns non-zero if it's OK. 634 * 635 * Many HD-audio controllers appear pretty inaccurate about 636 * the update-IRQ timing. The IRQ is issued before actually the 637 * data is processed. So, we need to process it afterwords in a 638 * workqueue. 639 * 640 * Returns 1 if OK to proceed, 0 for delay handling, -1 for skipping update 641 */ 642 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev) 643 { 644 struct snd_pcm_substream *substream = azx_dev->core.substream; 645 struct snd_pcm_runtime *runtime = substream->runtime; 646 int stream = substream->stream; 647 u32 wallclk; 648 unsigned int pos; 649 snd_pcm_uframes_t hwptr, target; 650 651 /* 652 * The value of the WALLCLK register is always 0 653 * on the Loongson controller, so we return directly. 654 */ 655 if (chip->driver_type == AZX_DRIVER_LOONGSON) 656 return 1; 657 658 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk; 659 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3) 660 return -1; /* bogus (too early) interrupt */ 661 662 if (chip->get_position[stream]) 663 pos = chip->get_position[stream](chip, azx_dev); 664 else { /* use the position buffer as default */ 665 pos = azx_get_pos_posbuf(chip, azx_dev); 666 if (!pos || pos == (u32)-1) { 667 dev_info(chip->card->dev, 668 "Invalid position buffer, using LPIB read method instead.\n"); 669 chip->get_position[stream] = azx_get_pos_lpib; 670 if (chip->get_position[0] == azx_get_pos_lpib && 671 chip->get_position[1] == azx_get_pos_lpib) 672 azx_bus(chip)->use_posbuf = false; 673 pos = azx_get_pos_lpib(chip, azx_dev); 674 chip->get_delay[stream] = NULL; 675 } else { 676 chip->get_position[stream] = azx_get_pos_posbuf; 677 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY) 678 chip->get_delay[stream] = azx_get_delay_from_lpib; 679 } 680 } 681 682 if (pos >= azx_dev->core.bufsize) 683 pos = 0; 684 685 if (WARN_ONCE(!azx_dev->core.period_bytes, 686 "hda-intel: zero azx_dev->period_bytes")) 687 return -1; /* this shouldn't happen! */ 688 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 && 689 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2) 690 /* NG - it's below the first next period boundary */ 691 return chip->bdl_pos_adj ? 0 : -1; 692 azx_dev->core.start_wallclk += wallclk; 693 694 if (azx_dev->core.no_period_wakeup) 695 return 1; /* OK, no need to check period boundary */ 696 697 if (runtime->hw_ptr_base != runtime->hw_ptr_interrupt) 698 return 1; /* OK, already in hwptr updating process */ 699 700 /* check whether the period gets really elapsed */ 701 pos = bytes_to_frames(runtime, pos); 702 hwptr = runtime->hw_ptr_base + pos; 703 if (hwptr < runtime->status->hw_ptr) 704 hwptr += runtime->buffer_size; 705 target = runtime->hw_ptr_interrupt + runtime->period_size; 706 if (hwptr < target) { 707 /* too early wakeup, process it later */ 708 return chip->bdl_pos_adj ? 0 : -1; 709 } 710 711 return 1; /* OK, it's fine */ 712 } 713 714 /* 715 * The work for pending PCM period updates. 716 */ 717 static void azx_irq_pending_work(struct work_struct *work) 718 { 719 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work); 720 struct azx *chip = &hda->chip; 721 struct hdac_bus *bus = azx_bus(chip); 722 struct hdac_stream *s; 723 int pending, ok; 724 725 if (!hda->irq_pending_warned) { 726 dev_info(chip->card->dev, 727 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n", 728 chip->card->number); 729 hda->irq_pending_warned = 1; 730 } 731 732 for (;;) { 733 pending = 0; 734 spin_lock_irq(&bus->reg_lock); 735 list_for_each_entry(s, &bus->stream_list, list) { 736 struct azx_dev *azx_dev = stream_to_azx_dev(s); 737 if (!azx_dev->irq_pending || 738 !s->substream || 739 !s->running) 740 continue; 741 ok = azx_position_ok(chip, azx_dev); 742 if (ok > 0) { 743 azx_dev->irq_pending = 0; 744 spin_unlock(&bus->reg_lock); 745 snd_pcm_period_elapsed(s->substream); 746 spin_lock(&bus->reg_lock); 747 } else if (ok < 0) { 748 pending = 0; /* too early */ 749 } else 750 pending++; 751 } 752 spin_unlock_irq(&bus->reg_lock); 753 if (!pending) 754 return; 755 msleep(1); 756 } 757 } 758 759 /* clear irq_pending flags and assure no on-going workq */ 760 static void azx_clear_irq_pending(struct azx *chip) 761 { 762 struct hdac_bus *bus = azx_bus(chip); 763 struct hdac_stream *s; 764 765 spin_lock_irq(&bus->reg_lock); 766 list_for_each_entry(s, &bus->stream_list, list) { 767 struct azx_dev *azx_dev = stream_to_azx_dev(s); 768 azx_dev->irq_pending = 0; 769 } 770 spin_unlock_irq(&bus->reg_lock); 771 } 772 773 static int azx_acquire_irq(struct azx *chip, int do_disconnect) 774 { 775 struct hdac_bus *bus = azx_bus(chip); 776 777 if (request_irq(chip->pci->irq, azx_interrupt, 778 chip->msi ? 0 : IRQF_SHARED, 779 chip->card->irq_descr, chip)) { 780 dev_err(chip->card->dev, 781 "unable to grab IRQ %d, disabling device\n", 782 chip->pci->irq); 783 if (do_disconnect) 784 snd_card_disconnect(chip->card); 785 return -1; 786 } 787 bus->irq = chip->pci->irq; 788 chip->card->sync_irq = bus->irq; 789 pci_intx(chip->pci, !chip->msi); 790 return 0; 791 } 792 793 /* get the current DMA position with correction on VIA chips */ 794 static unsigned int azx_via_get_position(struct azx *chip, 795 struct azx_dev *azx_dev) 796 { 797 unsigned int link_pos, mini_pos, bound_pos; 798 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos; 799 unsigned int fifo_size; 800 801 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev)); 802 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 803 /* Playback, no problem using link position */ 804 return link_pos; 805 } 806 807 /* Capture */ 808 /* For new chipset, 809 * use mod to get the DMA position just like old chipset 810 */ 811 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf); 812 mod_dma_pos %= azx_dev->core.period_bytes; 813 814 fifo_size = azx_stream(azx_dev)->fifo_size; 815 816 if (azx_dev->insufficient) { 817 /* Link position never gather than FIFO size */ 818 if (link_pos <= fifo_size) 819 return 0; 820 821 azx_dev->insufficient = 0; 822 } 823 824 if (link_pos <= fifo_size) 825 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size; 826 else 827 mini_pos = link_pos - fifo_size; 828 829 /* Find nearest previous boudary */ 830 mod_mini_pos = mini_pos % azx_dev->core.period_bytes; 831 mod_link_pos = link_pos % azx_dev->core.period_bytes; 832 if (mod_link_pos >= fifo_size) 833 bound_pos = link_pos - mod_link_pos; 834 else if (mod_dma_pos >= mod_mini_pos) 835 bound_pos = mini_pos - mod_mini_pos; 836 else { 837 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes; 838 if (bound_pos >= azx_dev->core.bufsize) 839 bound_pos = 0; 840 } 841 842 /* Calculate real DMA position we want */ 843 return bound_pos + mod_dma_pos; 844 } 845 846 #define AMD_FIFO_SIZE 32 847 848 /* get the current DMA position with FIFO size correction */ 849 static unsigned int azx_get_pos_fifo(struct azx *chip, struct azx_dev *azx_dev) 850 { 851 struct snd_pcm_substream *substream = azx_dev->core.substream; 852 struct snd_pcm_runtime *runtime = substream->runtime; 853 unsigned int pos, delay; 854 855 pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev)); 856 if (!runtime) 857 return pos; 858 859 runtime->delay = AMD_FIFO_SIZE; 860 delay = frames_to_bytes(runtime, AMD_FIFO_SIZE); 861 if (azx_dev->insufficient) { 862 if (pos < delay) { 863 delay = pos; 864 runtime->delay = bytes_to_frames(runtime, pos); 865 } else { 866 azx_dev->insufficient = 0; 867 } 868 } 869 870 /* correct the DMA position for capture stream */ 871 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { 872 if (pos < delay) 873 pos += azx_dev->core.bufsize; 874 pos -= delay; 875 } 876 877 return pos; 878 } 879 880 static int azx_get_delay_from_fifo(struct azx *chip, struct azx_dev *azx_dev, 881 unsigned int pos) 882 { 883 struct snd_pcm_substream *substream = azx_dev->core.substream; 884 885 /* just read back the calculated value in the above */ 886 return substream->runtime->delay; 887 } 888 889 static void __azx_shutdown_chip(struct azx *chip, bool skip_link_reset) 890 { 891 azx_stop_chip(chip); 892 if (!skip_link_reset) 893 azx_enter_link_reset(chip); 894 azx_clear_irq_pending(chip); 895 display_power(chip, false); 896 } 897 898 static DEFINE_MUTEX(card_list_lock); 899 static LIST_HEAD(card_list); 900 901 static void azx_shutdown_chip(struct azx *chip) 902 { 903 __azx_shutdown_chip(chip, false); 904 } 905 906 static void azx_add_card_list(struct azx *chip) 907 { 908 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 909 mutex_lock(&card_list_lock); 910 list_add(&hda->list, &card_list); 911 mutex_unlock(&card_list_lock); 912 } 913 914 static void azx_del_card_list(struct azx *chip) 915 { 916 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 917 mutex_lock(&card_list_lock); 918 list_del_init(&hda->list); 919 mutex_unlock(&card_list_lock); 920 } 921 922 /* trigger power-save check at writing parameter */ 923 static int __maybe_unused param_set_xint(const char *val, const struct kernel_param *kp) 924 { 925 struct hda_intel *hda; 926 struct azx *chip; 927 int prev = power_save; 928 int ret = param_set_int(val, kp); 929 930 if (ret || prev == power_save) 931 return ret; 932 933 mutex_lock(&card_list_lock); 934 list_for_each_entry(hda, &card_list, list) { 935 chip = &hda->chip; 936 if (!hda->probe_continued || chip->disabled) 937 continue; 938 snd_hda_set_power_save(&chip->bus, power_save * 1000); 939 } 940 mutex_unlock(&card_list_lock); 941 return 0; 942 } 943 944 /* 945 * power management 946 */ 947 static bool azx_is_pm_ready(struct snd_card *card) 948 { 949 struct azx *chip; 950 struct hda_intel *hda; 951 952 if (!card) 953 return false; 954 chip = card->private_data; 955 hda = container_of(chip, struct hda_intel, chip); 956 if (chip->disabled || hda->init_failed || !chip->running) 957 return false; 958 return true; 959 } 960 961 static void __azx_runtime_resume(struct azx *chip) 962 { 963 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 964 struct hdac_bus *bus = azx_bus(chip); 965 struct hda_codec *codec; 966 int status; 967 968 display_power(chip, true); 969 if (hda->need_i915_power) 970 snd_hdac_i915_set_bclk(bus); 971 972 /* Read STATESTS before controller reset */ 973 status = azx_readw(chip, STATESTS); 974 975 azx_init_pci(chip); 976 hda_intel_init_chip(chip, true); 977 978 /* Avoid codec resume if runtime resume is for system suspend */ 979 if (!chip->pm_prepared) { 980 list_for_each_codec(codec, &chip->bus) { 981 if (codec->relaxed_resume) 982 continue; 983 984 if (codec->forced_resume || (status & (1 << codec->addr))) 985 pm_request_resume(hda_codec_dev(codec)); 986 } 987 } 988 989 /* power down again for link-controlled chips */ 990 if (!hda->need_i915_power) 991 display_power(chip, false); 992 } 993 994 static int azx_prepare(struct device *dev) 995 { 996 struct snd_card *card = dev_get_drvdata(dev); 997 struct azx *chip; 998 999 if (!azx_is_pm_ready(card)) 1000 return 0; 1001 1002 chip = card->private_data; 1003 chip->pm_prepared = 1; 1004 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 1005 1006 flush_work(&azx_bus(chip)->unsol_work); 1007 1008 /* HDA controller always requires different WAKEEN for runtime suspend 1009 * and system suspend, so don't use direct-complete here. 1010 */ 1011 return 0; 1012 } 1013 1014 static void azx_complete(struct device *dev) 1015 { 1016 struct snd_card *card = dev_get_drvdata(dev); 1017 struct azx *chip; 1018 1019 if (!azx_is_pm_ready(card)) 1020 return; 1021 1022 chip = card->private_data; 1023 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 1024 chip->pm_prepared = 0; 1025 } 1026 1027 static int azx_suspend(struct device *dev) 1028 { 1029 struct snd_card *card = dev_get_drvdata(dev); 1030 struct azx *chip; 1031 struct hdac_bus *bus; 1032 1033 if (!azx_is_pm_ready(card)) 1034 return 0; 1035 1036 chip = card->private_data; 1037 bus = azx_bus(chip); 1038 azx_shutdown_chip(chip); 1039 if (bus->irq >= 0) { 1040 free_irq(bus->irq, chip); 1041 bus->irq = -1; 1042 chip->card->sync_irq = -1; 1043 } 1044 1045 if (chip->msi) 1046 pci_disable_msi(chip->pci); 1047 1048 trace_azx_suspend(chip); 1049 return 0; 1050 } 1051 1052 static int __maybe_unused azx_resume(struct device *dev) 1053 { 1054 struct snd_card *card = dev_get_drvdata(dev); 1055 struct azx *chip; 1056 1057 if (!azx_is_pm_ready(card)) 1058 return 0; 1059 1060 chip = card->private_data; 1061 if (chip->msi) 1062 if (pci_enable_msi(chip->pci) < 0) 1063 chip->msi = 0; 1064 if (azx_acquire_irq(chip, 1) < 0) 1065 return -EIO; 1066 1067 __azx_runtime_resume(chip); 1068 1069 trace_azx_resume(chip); 1070 return 0; 1071 } 1072 1073 /* put codec down to D3 at hibernation for Intel SKL+; 1074 * otherwise BIOS may still access the codec and screw up the driver 1075 */ 1076 static int azx_freeze_noirq(struct device *dev) 1077 { 1078 struct snd_card *card = dev_get_drvdata(dev); 1079 struct azx *chip = card->private_data; 1080 struct pci_dev *pci = to_pci_dev(dev); 1081 1082 if (!azx_is_pm_ready(card)) 1083 return 0; 1084 if (chip->driver_type == AZX_DRIVER_SKL) 1085 pci_set_power_state(pci, PCI_D3hot); 1086 1087 return 0; 1088 } 1089 1090 static int azx_thaw_noirq(struct device *dev) 1091 { 1092 struct snd_card *card = dev_get_drvdata(dev); 1093 struct azx *chip = card->private_data; 1094 struct pci_dev *pci = to_pci_dev(dev); 1095 1096 if (!azx_is_pm_ready(card)) 1097 return 0; 1098 if (chip->driver_type == AZX_DRIVER_SKL) 1099 pci_set_power_state(pci, PCI_D0); 1100 1101 return 0; 1102 } 1103 1104 static int __maybe_unused azx_runtime_suspend(struct device *dev) 1105 { 1106 struct snd_card *card = dev_get_drvdata(dev); 1107 struct azx *chip; 1108 1109 if (!azx_is_pm_ready(card)) 1110 return 0; 1111 chip = card->private_data; 1112 1113 /* enable controller wake up event */ 1114 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) | STATESTS_INT_MASK); 1115 1116 azx_shutdown_chip(chip); 1117 trace_azx_runtime_suspend(chip); 1118 return 0; 1119 } 1120 1121 static int __maybe_unused azx_runtime_resume(struct device *dev) 1122 { 1123 struct snd_card *card = dev_get_drvdata(dev); 1124 struct azx *chip; 1125 1126 if (!azx_is_pm_ready(card)) 1127 return 0; 1128 chip = card->private_data; 1129 __azx_runtime_resume(chip); 1130 1131 /* disable controller Wake Up event*/ 1132 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) & ~STATESTS_INT_MASK); 1133 1134 trace_azx_runtime_resume(chip); 1135 return 0; 1136 } 1137 1138 static int __maybe_unused azx_runtime_idle(struct device *dev) 1139 { 1140 struct snd_card *card = dev_get_drvdata(dev); 1141 struct azx *chip; 1142 struct hda_intel *hda; 1143 1144 if (!card) 1145 return 0; 1146 1147 chip = card->private_data; 1148 hda = container_of(chip, struct hda_intel, chip); 1149 if (chip->disabled || hda->init_failed) 1150 return 0; 1151 1152 if (!power_save_controller || !azx_has_pm_runtime(chip) || 1153 azx_bus(chip)->codec_powered || !chip->running) 1154 return -EBUSY; 1155 1156 /* ELD notification gets broken when HD-audio bus is off */ 1157 if (needs_eld_notify_link(chip)) 1158 return -EBUSY; 1159 1160 return 0; 1161 } 1162 1163 static const struct dev_pm_ops azx_pm = { 1164 SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume) 1165 .prepare = pm_sleep_ptr(azx_prepare), 1166 .complete = pm_sleep_ptr(azx_complete), 1167 .freeze_noirq = pm_sleep_ptr(azx_freeze_noirq), 1168 .thaw_noirq = pm_sleep_ptr(azx_thaw_noirq), 1169 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle) 1170 }; 1171 1172 1173 static int azx_probe_continue(struct azx *chip); 1174 1175 #ifdef SUPPORT_VGA_SWITCHEROO 1176 static struct pci_dev *get_bound_vga(struct pci_dev *pci); 1177 1178 static void azx_vs_set_state(struct pci_dev *pci, 1179 enum vga_switcheroo_state state) 1180 { 1181 struct snd_card *card = pci_get_drvdata(pci); 1182 struct azx *chip = card->private_data; 1183 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1184 struct hda_codec *codec; 1185 bool disabled; 1186 1187 wait_for_completion(&hda->probe_wait); 1188 if (hda->init_failed) 1189 return; 1190 1191 disabled = (state == VGA_SWITCHEROO_OFF); 1192 if (chip->disabled == disabled) 1193 return; 1194 1195 if (!hda->probe_continued) { 1196 chip->disabled = disabled; 1197 if (!disabled) { 1198 dev_info(chip->card->dev, 1199 "Start delayed initialization\n"); 1200 if (azx_probe_continue(chip) < 0) 1201 dev_err(chip->card->dev, "initialization error\n"); 1202 } 1203 } else { 1204 dev_info(chip->card->dev, "%s via vga_switcheroo\n", 1205 disabled ? "Disabling" : "Enabling"); 1206 if (disabled) { 1207 list_for_each_codec(codec, &chip->bus) { 1208 pm_runtime_suspend(hda_codec_dev(codec)); 1209 pm_runtime_disable(hda_codec_dev(codec)); 1210 } 1211 pm_runtime_suspend(card->dev); 1212 pm_runtime_disable(card->dev); 1213 /* when we get suspended by vga_switcheroo we end up in D3cold, 1214 * however we have no ACPI handle, so pci/acpi can't put us there, 1215 * put ourselves there */ 1216 pci->current_state = PCI_D3cold; 1217 chip->disabled = true; 1218 if (snd_hda_lock_devices(&chip->bus)) 1219 dev_warn(chip->card->dev, 1220 "Cannot lock devices!\n"); 1221 } else { 1222 snd_hda_unlock_devices(&chip->bus); 1223 chip->disabled = false; 1224 pm_runtime_enable(card->dev); 1225 list_for_each_codec(codec, &chip->bus) { 1226 pm_runtime_enable(hda_codec_dev(codec)); 1227 pm_runtime_resume(hda_codec_dev(codec)); 1228 } 1229 } 1230 } 1231 } 1232 1233 static bool azx_vs_can_switch(struct pci_dev *pci) 1234 { 1235 struct snd_card *card = pci_get_drvdata(pci); 1236 struct azx *chip = card->private_data; 1237 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1238 1239 wait_for_completion(&hda->probe_wait); 1240 if (hda->init_failed) 1241 return false; 1242 if (chip->disabled || !hda->probe_continued) 1243 return true; 1244 if (snd_hda_lock_devices(&chip->bus)) 1245 return false; 1246 snd_hda_unlock_devices(&chip->bus); 1247 return true; 1248 } 1249 1250 /* 1251 * The discrete GPU cannot power down unless the HDA controller runtime 1252 * suspends, so activate runtime PM on codecs even if power_save == 0. 1253 */ 1254 static void setup_vga_switcheroo_runtime_pm(struct azx *chip) 1255 { 1256 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1257 struct hda_codec *codec; 1258 1259 if (hda->use_vga_switcheroo && !needs_eld_notify_link(chip)) { 1260 list_for_each_codec(codec, &chip->bus) 1261 codec->auto_runtime_pm = 1; 1262 /* reset the power save setup */ 1263 if (chip->running) 1264 set_default_power_save(chip); 1265 } 1266 } 1267 1268 static void azx_vs_gpu_bound(struct pci_dev *pci, 1269 enum vga_switcheroo_client_id client_id) 1270 { 1271 struct snd_card *card = pci_get_drvdata(pci); 1272 struct azx *chip = card->private_data; 1273 1274 if (client_id == VGA_SWITCHEROO_DIS) 1275 chip->bus.keep_power = 0; 1276 setup_vga_switcheroo_runtime_pm(chip); 1277 } 1278 1279 static void init_vga_switcheroo(struct azx *chip) 1280 { 1281 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1282 struct pci_dev *p = get_bound_vga(chip->pci); 1283 struct pci_dev *parent; 1284 if (p) { 1285 dev_info(chip->card->dev, 1286 "Handle vga_switcheroo audio client\n"); 1287 hda->use_vga_switcheroo = 1; 1288 1289 /* cleared in either gpu_bound op or codec probe, or when its 1290 * upstream port has _PR3 (i.e. dGPU). 1291 */ 1292 parent = pci_upstream_bridge(p); 1293 chip->bus.keep_power = parent ? !pci_pr3_present(parent) : 1; 1294 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME; 1295 pci_dev_put(p); 1296 } 1297 } 1298 1299 static const struct vga_switcheroo_client_ops azx_vs_ops = { 1300 .set_gpu_state = azx_vs_set_state, 1301 .can_switch = azx_vs_can_switch, 1302 .gpu_bound = azx_vs_gpu_bound, 1303 }; 1304 1305 static int register_vga_switcheroo(struct azx *chip) 1306 { 1307 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1308 struct pci_dev *p; 1309 int err; 1310 1311 if (!hda->use_vga_switcheroo) 1312 return 0; 1313 1314 p = get_bound_vga(chip->pci); 1315 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p); 1316 pci_dev_put(p); 1317 1318 if (err < 0) 1319 return err; 1320 hda->vga_switcheroo_registered = 1; 1321 1322 return 0; 1323 } 1324 #else 1325 #define init_vga_switcheroo(chip) /* NOP */ 1326 #define register_vga_switcheroo(chip) 0 1327 #define check_hdmi_disabled(pci) false 1328 #define setup_vga_switcheroo_runtime_pm(chip) /* NOP */ 1329 #endif /* SUPPORT_VGA_SWITCHER */ 1330 1331 /* 1332 * destructor 1333 */ 1334 static void azx_free(struct azx *chip) 1335 { 1336 struct pci_dev *pci = chip->pci; 1337 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1338 struct hdac_bus *bus = azx_bus(chip); 1339 1340 if (hda->freed) 1341 return; 1342 1343 if (azx_has_pm_runtime(chip) && chip->running) { 1344 pm_runtime_get_noresume(&pci->dev); 1345 pm_runtime_forbid(&pci->dev); 1346 pm_runtime_dont_use_autosuspend(&pci->dev); 1347 } 1348 1349 chip->running = 0; 1350 1351 azx_del_card_list(chip); 1352 1353 hda->init_failed = 1; /* to be sure */ 1354 complete_all(&hda->probe_wait); 1355 1356 if (use_vga_switcheroo(hda)) { 1357 if (chip->disabled && hda->probe_continued) 1358 snd_hda_unlock_devices(&chip->bus); 1359 if (hda->vga_switcheroo_registered) 1360 vga_switcheroo_unregister_client(chip->pci); 1361 } 1362 1363 if (bus->chip_init) { 1364 azx_clear_irq_pending(chip); 1365 azx_stop_all_streams(chip); 1366 azx_stop_chip(chip); 1367 } 1368 1369 if (bus->irq >= 0) 1370 free_irq(bus->irq, (void*)chip); 1371 1372 azx_free_stream_pages(chip); 1373 azx_free_streams(chip); 1374 snd_hdac_bus_exit(bus); 1375 1376 #ifdef CONFIG_SND_HDA_PATCH_LOADER 1377 release_firmware(chip->fw); 1378 #endif 1379 display_power(chip, false); 1380 1381 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) 1382 snd_hdac_i915_exit(bus); 1383 1384 hda->freed = 1; 1385 } 1386 1387 static int azx_dev_disconnect(struct snd_device *device) 1388 { 1389 struct azx *chip = device->device_data; 1390 struct hdac_bus *bus = azx_bus(chip); 1391 1392 chip->bus.shutdown = 1; 1393 cancel_work_sync(&bus->unsol_work); 1394 1395 return 0; 1396 } 1397 1398 static int azx_dev_free(struct snd_device *device) 1399 { 1400 azx_free(device->device_data); 1401 return 0; 1402 } 1403 1404 #ifdef SUPPORT_VGA_SWITCHEROO 1405 #ifdef CONFIG_ACPI 1406 /* ATPX is in the integrated GPU's namespace */ 1407 static bool atpx_present(void) 1408 { 1409 struct pci_dev *pdev = NULL; 1410 acpi_handle dhandle, atpx_handle; 1411 acpi_status status; 1412 1413 while ((pdev = pci_get_base_class(PCI_BASE_CLASS_DISPLAY, pdev))) { 1414 if ((pdev->class != PCI_CLASS_DISPLAY_VGA << 8) && 1415 (pdev->class != PCI_CLASS_DISPLAY_OTHER << 8)) 1416 continue; 1417 1418 dhandle = ACPI_HANDLE(&pdev->dev); 1419 if (dhandle) { 1420 status = acpi_get_handle(dhandle, "ATPX", &atpx_handle); 1421 if (ACPI_SUCCESS(status)) { 1422 pci_dev_put(pdev); 1423 return true; 1424 } 1425 } 1426 } 1427 return false; 1428 } 1429 #else 1430 static bool atpx_present(void) 1431 { 1432 return false; 1433 } 1434 #endif 1435 1436 /* 1437 * Check of disabled HDMI controller by vga_switcheroo 1438 */ 1439 static struct pci_dev *get_bound_vga(struct pci_dev *pci) 1440 { 1441 struct pci_dev *p; 1442 1443 /* check only discrete GPU */ 1444 switch (pci->vendor) { 1445 case PCI_VENDOR_ID_ATI: 1446 case PCI_VENDOR_ID_AMD: 1447 if (pci->devfn == 1) { 1448 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus), 1449 pci->bus->number, 0); 1450 if (p) { 1451 /* ATPX is in the integrated GPU's ACPI namespace 1452 * rather than the dGPU's namespace. However, 1453 * the dGPU is the one who is involved in 1454 * vgaswitcheroo. 1455 */ 1456 if (((p->class >> 16) == PCI_BASE_CLASS_DISPLAY) && 1457 (atpx_present() || apple_gmux_detect(NULL, NULL))) 1458 return p; 1459 pci_dev_put(p); 1460 } 1461 } 1462 break; 1463 case PCI_VENDOR_ID_NVIDIA: 1464 if (pci->devfn == 1) { 1465 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus), 1466 pci->bus->number, 0); 1467 if (p) { 1468 if ((p->class >> 16) == PCI_BASE_CLASS_DISPLAY) 1469 return p; 1470 pci_dev_put(p); 1471 } 1472 } 1473 break; 1474 } 1475 return NULL; 1476 } 1477 1478 static bool check_hdmi_disabled(struct pci_dev *pci) 1479 { 1480 bool vga_inactive = false; 1481 struct pci_dev *p = get_bound_vga(pci); 1482 1483 if (p) { 1484 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF) 1485 vga_inactive = true; 1486 pci_dev_put(p); 1487 } 1488 return vga_inactive; 1489 } 1490 #endif /* SUPPORT_VGA_SWITCHEROO */ 1491 1492 /* 1493 * allow/deny-listing for position_fix 1494 */ 1495 static const struct snd_pci_quirk position_fix_list[] = { 1496 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB), 1497 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB), 1498 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB), 1499 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB), 1500 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB), 1501 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB), 1502 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB), 1503 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB), 1504 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB), 1505 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB), 1506 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB), 1507 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB), 1508 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB), 1509 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB), 1510 {} 1511 }; 1512 1513 static int check_position_fix(struct azx *chip, int fix) 1514 { 1515 const struct snd_pci_quirk *q; 1516 1517 switch (fix) { 1518 case POS_FIX_AUTO: 1519 case POS_FIX_LPIB: 1520 case POS_FIX_POSBUF: 1521 case POS_FIX_VIACOMBO: 1522 case POS_FIX_COMBO: 1523 case POS_FIX_SKL: 1524 case POS_FIX_FIFO: 1525 return fix; 1526 } 1527 1528 q = snd_pci_quirk_lookup(chip->pci, position_fix_list); 1529 if (q) { 1530 dev_info(chip->card->dev, 1531 "position_fix set to %d for device %04x:%04x\n", 1532 q->value, q->subvendor, q->subdevice); 1533 return q->value; 1534 } 1535 1536 /* Check VIA/ATI HD Audio Controller exist */ 1537 if (chip->driver_type == AZX_DRIVER_VIA) { 1538 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n"); 1539 return POS_FIX_VIACOMBO; 1540 } 1541 if (chip->driver_caps & AZX_DCAPS_AMD_WORKAROUND) { 1542 dev_dbg(chip->card->dev, "Using FIFO position fix\n"); 1543 return POS_FIX_FIFO; 1544 } 1545 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) { 1546 dev_dbg(chip->card->dev, "Using LPIB position fix\n"); 1547 return POS_FIX_LPIB; 1548 } 1549 if (chip->driver_type == AZX_DRIVER_SKL) { 1550 dev_dbg(chip->card->dev, "Using SKL position fix\n"); 1551 return POS_FIX_SKL; 1552 } 1553 return POS_FIX_AUTO; 1554 } 1555 1556 static void assign_position_fix(struct azx *chip, int fix) 1557 { 1558 static const azx_get_pos_callback_t callbacks[] = { 1559 [POS_FIX_AUTO] = NULL, 1560 [POS_FIX_LPIB] = azx_get_pos_lpib, 1561 [POS_FIX_POSBUF] = azx_get_pos_posbuf, 1562 [POS_FIX_VIACOMBO] = azx_via_get_position, 1563 [POS_FIX_COMBO] = azx_get_pos_lpib, 1564 [POS_FIX_SKL] = azx_get_pos_posbuf, 1565 [POS_FIX_FIFO] = azx_get_pos_fifo, 1566 }; 1567 1568 chip->get_position[0] = chip->get_position[1] = callbacks[fix]; 1569 1570 /* combo mode uses LPIB only for playback */ 1571 if (fix == POS_FIX_COMBO) 1572 chip->get_position[1] = NULL; 1573 1574 if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) && 1575 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) { 1576 chip->get_delay[0] = chip->get_delay[1] = 1577 azx_get_delay_from_lpib; 1578 } 1579 1580 if (fix == POS_FIX_FIFO) 1581 chip->get_delay[0] = chip->get_delay[1] = 1582 azx_get_delay_from_fifo; 1583 } 1584 1585 /* 1586 * deny-lists for probe_mask 1587 */ 1588 static const struct snd_pci_quirk probe_mask_list[] = { 1589 /* Thinkpad often breaks the controller communication when accessing 1590 * to the non-working (or non-existing) modem codec slot. 1591 */ 1592 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01), 1593 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01), 1594 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01), 1595 /* broken BIOS */ 1596 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01), 1597 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */ 1598 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01), 1599 /* forced codec slots */ 1600 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103), 1601 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103), 1602 SND_PCI_QUIRK(0x1558, 0x0351, "Schenker Dock 15", 0x105), 1603 /* WinFast VP200 H (Teradici) user reported broken communication */ 1604 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101), 1605 {} 1606 }; 1607 1608 #define AZX_FORCE_CODEC_MASK 0x100 1609 1610 static void check_probe_mask(struct azx *chip, int dev) 1611 { 1612 const struct snd_pci_quirk *q; 1613 1614 chip->codec_probe_mask = probe_mask[dev]; 1615 if (chip->codec_probe_mask == -1) { 1616 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list); 1617 if (q) { 1618 dev_info(chip->card->dev, 1619 "probe_mask set to 0x%x for device %04x:%04x\n", 1620 q->value, q->subvendor, q->subdevice); 1621 chip->codec_probe_mask = q->value; 1622 } 1623 } 1624 1625 /* check forced option */ 1626 if (chip->codec_probe_mask != -1 && 1627 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) { 1628 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff; 1629 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n", 1630 (int)azx_bus(chip)->codec_mask); 1631 } 1632 } 1633 1634 /* 1635 * allow/deny-list for enable_msi 1636 */ 1637 static const struct snd_pci_quirk msi_deny_list[] = { 1638 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */ 1639 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */ 1640 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */ 1641 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */ 1642 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */ 1643 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */ 1644 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */ 1645 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */ 1646 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */ 1647 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */ 1648 {} 1649 }; 1650 1651 static void check_msi(struct azx *chip) 1652 { 1653 const struct snd_pci_quirk *q; 1654 1655 if (enable_msi >= 0) { 1656 chip->msi = !!enable_msi; 1657 return; 1658 } 1659 chip->msi = 1; /* enable MSI as default */ 1660 q = snd_pci_quirk_lookup(chip->pci, msi_deny_list); 1661 if (q) { 1662 dev_info(chip->card->dev, 1663 "msi for device %04x:%04x set to %d\n", 1664 q->subvendor, q->subdevice, q->value); 1665 chip->msi = q->value; 1666 return; 1667 } 1668 1669 /* NVidia chipsets seem to cause troubles with MSI */ 1670 if (chip->driver_caps & AZX_DCAPS_NO_MSI) { 1671 dev_info(chip->card->dev, "Disabling MSI\n"); 1672 chip->msi = 0; 1673 } 1674 } 1675 1676 /* check the snoop mode availability */ 1677 static void azx_check_snoop_available(struct azx *chip) 1678 { 1679 int snoop = hda_snoop; 1680 1681 if (snoop >= 0) { 1682 dev_info(chip->card->dev, "Force to %s mode by module option\n", 1683 snoop ? "snoop" : "non-snoop"); 1684 chip->snoop = snoop; 1685 chip->uc_buffer = !snoop; 1686 return; 1687 } 1688 1689 snoop = true; 1690 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE && 1691 chip->driver_type == AZX_DRIVER_VIA) { 1692 /* force to non-snoop mode for a new VIA controller 1693 * when BIOS is set 1694 */ 1695 u8 val; 1696 pci_read_config_byte(chip->pci, 0x42, &val); 1697 if (!(val & 0x80) && (chip->pci->revision == 0x30 || 1698 chip->pci->revision == 0x20)) 1699 snoop = false; 1700 } 1701 1702 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF) 1703 snoop = false; 1704 1705 chip->snoop = snoop; 1706 if (!snoop) { 1707 dev_info(chip->card->dev, "Force to non-snoop mode\n"); 1708 /* C-Media requires non-cached pages only for CORB/RIRB */ 1709 if (chip->driver_type != AZX_DRIVER_CMEDIA) 1710 chip->uc_buffer = true; 1711 } 1712 } 1713 1714 static void azx_probe_work(struct work_struct *work) 1715 { 1716 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work.work); 1717 azx_probe_continue(&hda->chip); 1718 } 1719 1720 static int default_bdl_pos_adj(struct azx *chip) 1721 { 1722 /* some exceptions: Atoms seem problematic with value 1 */ 1723 if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) { 1724 switch (chip->pci->device) { 1725 case PCI_DEVICE_ID_INTEL_HDA_BYT: 1726 case PCI_DEVICE_ID_INTEL_HDA_BSW: 1727 return 32; 1728 case PCI_DEVICE_ID_INTEL_HDA_APL: 1729 return 64; 1730 } 1731 } 1732 1733 switch (chip->driver_type) { 1734 /* 1735 * increase the bdl size for Glenfly Gpus for hardware 1736 * limitation on hdac interrupt interval 1737 */ 1738 case AZX_DRIVER_GFHDMI: 1739 return 128; 1740 case AZX_DRIVER_ICH: 1741 case AZX_DRIVER_PCH: 1742 return 1; 1743 default: 1744 return 32; 1745 } 1746 } 1747 1748 /* 1749 * constructor 1750 */ 1751 static const struct hda_controller_ops pci_hda_ops; 1752 1753 static int azx_create(struct snd_card *card, struct pci_dev *pci, 1754 int dev, unsigned int driver_caps, 1755 struct azx **rchip) 1756 { 1757 static const struct snd_device_ops ops = { 1758 .dev_disconnect = azx_dev_disconnect, 1759 .dev_free = azx_dev_free, 1760 }; 1761 struct hda_intel *hda; 1762 struct azx *chip; 1763 int err; 1764 1765 *rchip = NULL; 1766 1767 err = pcim_enable_device(pci); 1768 if (err < 0) 1769 return err; 1770 1771 hda = devm_kzalloc(&pci->dev, sizeof(*hda), GFP_KERNEL); 1772 if (!hda) 1773 return -ENOMEM; 1774 1775 chip = &hda->chip; 1776 mutex_init(&chip->open_mutex); 1777 chip->card = card; 1778 chip->pci = pci; 1779 chip->ops = &pci_hda_ops; 1780 chip->driver_caps = driver_caps; 1781 chip->driver_type = driver_caps & 0xff; 1782 check_msi(chip); 1783 chip->dev_index = dev; 1784 if (jackpoll_ms[dev] >= 50 && jackpoll_ms[dev] <= 60000) 1785 chip->jackpoll_interval = msecs_to_jiffies(jackpoll_ms[dev]); 1786 INIT_LIST_HEAD(&chip->pcm_list); 1787 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work); 1788 INIT_LIST_HEAD(&hda->list); 1789 init_vga_switcheroo(chip); 1790 init_completion(&hda->probe_wait); 1791 1792 assign_position_fix(chip, check_position_fix(chip, position_fix[dev])); 1793 1794 if (single_cmd < 0) /* allow fallback to single_cmd at errors */ 1795 chip->fallback_to_single_cmd = 1; 1796 else /* explicitly set to single_cmd or not */ 1797 chip->single_cmd = single_cmd; 1798 1799 azx_check_snoop_available(chip); 1800 1801 if (bdl_pos_adj[dev] < 0) 1802 chip->bdl_pos_adj = default_bdl_pos_adj(chip); 1803 else 1804 chip->bdl_pos_adj = bdl_pos_adj[dev]; 1805 1806 err = azx_bus_init(chip, model[dev]); 1807 if (err < 0) 1808 return err; 1809 1810 /* use the non-cached pages in non-snoop mode */ 1811 if (!azx_snoop(chip)) 1812 azx_bus(chip)->dma_type = SNDRV_DMA_TYPE_DEV_WC_SG; 1813 1814 if (chip->driver_type == AZX_DRIVER_NVIDIA) { 1815 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n"); 1816 chip->bus.core.needs_damn_long_delay = 1; 1817 } 1818 1819 check_probe_mask(chip, dev); 1820 1821 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); 1822 if (err < 0) { 1823 dev_err(card->dev, "Error creating device [card]!\n"); 1824 azx_free(chip); 1825 return err; 1826 } 1827 1828 /* continue probing in work context as may trigger request module */ 1829 INIT_DELAYED_WORK(&hda->probe_work, azx_probe_work); 1830 1831 *rchip = chip; 1832 1833 return 0; 1834 } 1835 1836 static int azx_first_init(struct azx *chip) 1837 { 1838 int dev = chip->dev_index; 1839 struct pci_dev *pci = chip->pci; 1840 struct snd_card *card = chip->card; 1841 struct hdac_bus *bus = azx_bus(chip); 1842 int err; 1843 unsigned short gcap; 1844 unsigned int dma_bits = 64; 1845 1846 #if BITS_PER_LONG != 64 1847 /* Fix up base address on ULI M5461 */ 1848 if (chip->driver_type == AZX_DRIVER_ULI) { 1849 u16 tmp3; 1850 pci_read_config_word(pci, 0x40, &tmp3); 1851 pci_write_config_word(pci, 0x40, tmp3 | 0x10); 1852 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0); 1853 } 1854 #endif 1855 /* 1856 * Fix response write request not synced to memory when handle 1857 * hdac interrupt on Glenfly Gpus 1858 */ 1859 if (chip->driver_type == AZX_DRIVER_GFHDMI) 1860 bus->polling_mode = 1; 1861 1862 if (chip->driver_type == AZX_DRIVER_LOONGSON) { 1863 bus->polling_mode = 1; 1864 bus->not_use_interrupts = 1; 1865 bus->access_sdnctl_in_dword = 1; 1866 } 1867 1868 err = pcim_iomap_regions(pci, 1 << 0, "ICH HD audio"); 1869 if (err < 0) 1870 return err; 1871 1872 bus->addr = pci_resource_start(pci, 0); 1873 bus->remap_addr = pcim_iomap_table(pci)[0]; 1874 1875 if (chip->driver_type == AZX_DRIVER_SKL) 1876 snd_hdac_bus_parse_capabilities(bus); 1877 1878 /* 1879 * Some Intel CPUs has always running timer (ART) feature and 1880 * controller may have Global time sync reporting capability, so 1881 * check both of these before declaring synchronized time reporting 1882 * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME 1883 */ 1884 chip->gts_present = false; 1885 1886 #ifdef CONFIG_X86 1887 if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART)) 1888 chip->gts_present = true; 1889 #endif 1890 1891 if (chip->msi) { 1892 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) { 1893 dev_dbg(card->dev, "Disabling 64bit MSI\n"); 1894 pci->no_64bit_msi = true; 1895 } 1896 if (pci_enable_msi(pci) < 0) 1897 chip->msi = 0; 1898 } 1899 1900 pci_set_master(pci); 1901 1902 gcap = azx_readw(chip, GCAP); 1903 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap); 1904 1905 /* AMD devices support 40 or 48bit DMA, take the safe one */ 1906 if (chip->pci->vendor == PCI_VENDOR_ID_AMD) 1907 dma_bits = 40; 1908 1909 /* disable SB600 64bit support for safety */ 1910 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) { 1911 struct pci_dev *p_smbus; 1912 dma_bits = 40; 1913 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI, 1914 PCI_DEVICE_ID_ATI_SBX00_SMBUS, 1915 NULL); 1916 if (p_smbus) { 1917 if (p_smbus->revision < 0x30) 1918 gcap &= ~AZX_GCAP_64OK; 1919 pci_dev_put(p_smbus); 1920 } 1921 } 1922 1923 /* NVidia hardware normally only supports up to 40 bits of DMA */ 1924 if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA) 1925 dma_bits = 40; 1926 1927 /* disable 64bit DMA address on some devices */ 1928 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) { 1929 dev_dbg(card->dev, "Disabling 64bit DMA\n"); 1930 gcap &= ~AZX_GCAP_64OK; 1931 } 1932 1933 /* disable buffer size rounding to 128-byte multiples if supported */ 1934 if (align_buffer_size >= 0) 1935 chip->align_buffer_size = !!align_buffer_size; 1936 else { 1937 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE) 1938 chip->align_buffer_size = 0; 1939 else 1940 chip->align_buffer_size = 1; 1941 } 1942 1943 /* allow 64bit DMA address if supported by H/W */ 1944 if (!(gcap & AZX_GCAP_64OK)) 1945 dma_bits = 32; 1946 if (dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(dma_bits))) 1947 dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(32)); 1948 dma_set_max_seg_size(&pci->dev, UINT_MAX); 1949 1950 /* read number of streams from GCAP register instead of using 1951 * hardcoded value 1952 */ 1953 chip->capture_streams = (gcap >> 8) & 0x0f; 1954 chip->playback_streams = (gcap >> 12) & 0x0f; 1955 if (!chip->playback_streams && !chip->capture_streams) { 1956 /* gcap didn't give any info, switching to old method */ 1957 1958 switch (chip->driver_type) { 1959 case AZX_DRIVER_ULI: 1960 chip->playback_streams = ULI_NUM_PLAYBACK; 1961 chip->capture_streams = ULI_NUM_CAPTURE; 1962 break; 1963 case AZX_DRIVER_ATIHDMI: 1964 case AZX_DRIVER_ATIHDMI_NS: 1965 chip->playback_streams = ATIHDMI_NUM_PLAYBACK; 1966 chip->capture_streams = ATIHDMI_NUM_CAPTURE; 1967 break; 1968 case AZX_DRIVER_GFHDMI: 1969 case AZX_DRIVER_GENERIC: 1970 default: 1971 chip->playback_streams = ICH6_NUM_PLAYBACK; 1972 chip->capture_streams = ICH6_NUM_CAPTURE; 1973 break; 1974 } 1975 } 1976 chip->capture_index_offset = 0; 1977 chip->playback_index_offset = chip->capture_streams; 1978 chip->num_streams = chip->playback_streams + chip->capture_streams; 1979 1980 /* sanity check for the SDxCTL.STRM field overflow */ 1981 if (chip->num_streams > 15 && 1982 (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) { 1983 dev_warn(chip->card->dev, "number of I/O streams is %d, " 1984 "forcing separate stream tags", chip->num_streams); 1985 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG; 1986 } 1987 1988 /* initialize streams */ 1989 err = azx_init_streams(chip); 1990 if (err < 0) 1991 return err; 1992 1993 err = azx_alloc_stream_pages(chip); 1994 if (err < 0) 1995 return err; 1996 1997 /* initialize chip */ 1998 azx_init_pci(chip); 1999 2000 snd_hdac_i915_set_bclk(bus); 2001 2002 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0); 2003 2004 /* codec detection */ 2005 if (!azx_bus(chip)->codec_mask) { 2006 dev_err(card->dev, "no codecs found!\n"); 2007 /* keep running the rest for the runtime PM */ 2008 } 2009 2010 if (azx_acquire_irq(chip, 0) < 0) 2011 return -EBUSY; 2012 2013 strcpy(card->driver, "HDA-Intel"); 2014 strscpy(card->shortname, driver_short_names[chip->driver_type], 2015 sizeof(card->shortname)); 2016 snprintf(card->longname, sizeof(card->longname), 2017 "%s at 0x%lx irq %i", 2018 card->shortname, bus->addr, bus->irq); 2019 2020 return 0; 2021 } 2022 2023 #ifdef CONFIG_SND_HDA_PATCH_LOADER 2024 /* callback from request_firmware_nowait() */ 2025 static void azx_firmware_cb(const struct firmware *fw, void *context) 2026 { 2027 struct snd_card *card = context; 2028 struct azx *chip = card->private_data; 2029 2030 if (fw) 2031 chip->fw = fw; 2032 else 2033 dev_err(card->dev, "Cannot load firmware, continue without patching\n"); 2034 if (!chip->disabled) { 2035 /* continue probing */ 2036 azx_probe_continue(chip); 2037 } 2038 } 2039 #endif 2040 2041 static int disable_msi_reset_irq(struct azx *chip) 2042 { 2043 struct hdac_bus *bus = azx_bus(chip); 2044 int err; 2045 2046 free_irq(bus->irq, chip); 2047 bus->irq = -1; 2048 chip->card->sync_irq = -1; 2049 pci_disable_msi(chip->pci); 2050 chip->msi = 0; 2051 err = azx_acquire_irq(chip, 1); 2052 if (err < 0) 2053 return err; 2054 2055 return 0; 2056 } 2057 2058 /* Denylist for skipping the whole probe: 2059 * some HD-audio PCI entries are exposed without any codecs, and such devices 2060 * should be ignored from the beginning. 2061 */ 2062 static const struct pci_device_id driver_denylist[] = { 2063 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1043, 0x874f) }, /* ASUS ROG Zenith II / Strix */ 2064 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb59) }, /* MSI TRX40 Creator */ 2065 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb60) }, /* MSI TRX40 */ 2066 { PCI_DEVICE_SUB(0x1022, 0x15e3, 0x1022, 0xd601) }, /* ASRock X670E Taichi */ 2067 {} 2068 }; 2069 2070 static const struct hda_controller_ops pci_hda_ops = { 2071 .disable_msi_reset_irq = disable_msi_reset_irq, 2072 .position_check = azx_position_check, 2073 }; 2074 2075 static DECLARE_BITMAP(probed_devs, SNDRV_CARDS); 2076 2077 static int azx_probe(struct pci_dev *pci, 2078 const struct pci_device_id *pci_id) 2079 { 2080 struct snd_card *card; 2081 struct hda_intel *hda; 2082 struct azx *chip; 2083 bool schedule_probe; 2084 int dev; 2085 int err; 2086 2087 if (pci_match_id(driver_denylist, pci)) { 2088 dev_info(&pci->dev, "Skipping the device on the denylist\n"); 2089 return -ENODEV; 2090 } 2091 2092 dev = find_first_zero_bit(probed_devs, SNDRV_CARDS); 2093 if (dev >= SNDRV_CARDS) 2094 return -ENODEV; 2095 if (!enable[dev]) { 2096 set_bit(dev, probed_devs); 2097 return -ENOENT; 2098 } 2099 2100 /* 2101 * stop probe if another Intel's DSP driver should be activated 2102 */ 2103 if (dmic_detect) { 2104 err = snd_intel_dsp_driver_probe(pci); 2105 if (err != SND_INTEL_DSP_DRIVER_ANY && err != SND_INTEL_DSP_DRIVER_LEGACY) { 2106 dev_dbg(&pci->dev, "HDAudio driver not selected, aborting probe\n"); 2107 return -ENODEV; 2108 } 2109 } else { 2110 dev_warn(&pci->dev, "dmic_detect option is deprecated, pass snd-intel-dspcfg.dsp_driver=1 option instead\n"); 2111 } 2112 2113 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE, 2114 0, &card); 2115 if (err < 0) { 2116 dev_err(&pci->dev, "Error creating card!\n"); 2117 return err; 2118 } 2119 2120 err = azx_create(card, pci, dev, pci_id->driver_data, &chip); 2121 if (err < 0) 2122 goto out_free; 2123 card->private_data = chip; 2124 hda = container_of(chip, struct hda_intel, chip); 2125 2126 pci_set_drvdata(pci, card); 2127 2128 #ifdef CONFIG_SND_HDA_I915 2129 /* bind with i915 if needed */ 2130 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) { 2131 err = snd_hdac_i915_init(azx_bus(chip)); 2132 if (err < 0) { 2133 if (err == -EPROBE_DEFER) 2134 goto out_free; 2135 2136 /* if the controller is bound only with HDMI/DP 2137 * (for HSW and BDW), we need to abort the probe; 2138 * for other chips, still continue probing as other 2139 * codecs can be on the same link. 2140 */ 2141 if (HDA_CONTROLLER_IN_GPU(pci)) { 2142 dev_err_probe(card->dev, err, 2143 "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n"); 2144 2145 goto out_free; 2146 } else { 2147 /* don't bother any longer */ 2148 chip->driver_caps &= ~AZX_DCAPS_I915_COMPONENT; 2149 } 2150 } 2151 2152 /* HSW/BDW controllers need this power */ 2153 if (HDA_CONTROLLER_IN_GPU(pci)) 2154 hda->need_i915_power = true; 2155 } 2156 #else 2157 if (HDA_CONTROLLER_IN_GPU(pci)) 2158 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n"); 2159 #endif 2160 2161 err = register_vga_switcheroo(chip); 2162 if (err < 0) { 2163 dev_err(card->dev, "Error registering vga_switcheroo client\n"); 2164 goto out_free; 2165 } 2166 2167 if (check_hdmi_disabled(pci)) { 2168 dev_info(card->dev, "VGA controller is disabled\n"); 2169 dev_info(card->dev, "Delaying initialization\n"); 2170 chip->disabled = true; 2171 } 2172 2173 schedule_probe = !chip->disabled; 2174 2175 #ifdef CONFIG_SND_HDA_PATCH_LOADER 2176 if (patch[dev] && *patch[dev]) { 2177 dev_info(card->dev, "Applying patch firmware '%s'\n", 2178 patch[dev]); 2179 err = request_firmware_nowait(THIS_MODULE, true, patch[dev], 2180 &pci->dev, GFP_KERNEL, card, 2181 azx_firmware_cb); 2182 if (err < 0) 2183 goto out_free; 2184 schedule_probe = false; /* continued in azx_firmware_cb() */ 2185 } 2186 #endif /* CONFIG_SND_HDA_PATCH_LOADER */ 2187 2188 if (schedule_probe) 2189 schedule_delayed_work(&hda->probe_work, 0); 2190 2191 set_bit(dev, probed_devs); 2192 if (chip->disabled) 2193 complete_all(&hda->probe_wait); 2194 return 0; 2195 2196 out_free: 2197 pci_set_drvdata(pci, NULL); 2198 snd_card_free(card); 2199 return err; 2200 } 2201 2202 /* On some boards setting power_save to a non 0 value leads to clicking / 2203 * popping sounds when ever we enter/leave powersaving mode. Ideally we would 2204 * figure out how to avoid these sounds, but that is not always feasible. 2205 * So we keep a list of devices where we disable powersaving as its known 2206 * to causes problems on these devices. 2207 */ 2208 static const struct snd_pci_quirk power_save_denylist[] = { 2209 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2210 SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0), 2211 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2212 SND_PCI_QUIRK(0x1849, 0x0397, "Asrock N68C-S UCC", 0), 2213 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2214 SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0), 2215 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2216 SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0), 2217 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2218 SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0), 2219 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2220 /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */ 2221 SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0), 2222 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2223 SND_PCI_QUIRK(0x8086, 0x2040, "Intel DZ77BH-55K", 0), 2224 /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */ 2225 SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0), 2226 /* https://bugs.launchpad.net/bugs/1821663 */ 2227 SND_PCI_QUIRK(0x8086, 0x2064, "Intel SDP 8086:2064", 0), 2228 /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */ 2229 SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0), 2230 /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */ 2231 SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0), 2232 SND_PCI_QUIRK(0x17aa, 0x316e, "Lenovo ThinkCentre M70q", 0), 2233 /* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */ 2234 SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0), 2235 /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */ 2236 SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0), 2237 /* https://bugs.launchpad.net/bugs/1821663 */ 2238 SND_PCI_QUIRK(0x1631, 0xe017, "Packard Bell NEC IMEDIA 5204", 0), 2239 /* KONTRON SinglePC may cause a stall at runtime resume */ 2240 SND_PCI_QUIRK(0x1734, 0x1232, "KONTRON SinglePC", 0), 2241 {} 2242 }; 2243 2244 static void set_default_power_save(struct azx *chip) 2245 { 2246 int val = power_save; 2247 2248 if (pm_blacklist) { 2249 const struct snd_pci_quirk *q; 2250 2251 q = snd_pci_quirk_lookup(chip->pci, power_save_denylist); 2252 if (q && val) { 2253 dev_info(chip->card->dev, "device %04x:%04x is on the power_save denylist, forcing power_save to 0\n", 2254 q->subvendor, q->subdevice); 2255 val = 0; 2256 } 2257 } 2258 snd_hda_set_power_save(&chip->bus, val * 1000); 2259 } 2260 2261 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */ 2262 static const unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = { 2263 [AZX_DRIVER_NVIDIA] = 8, 2264 [AZX_DRIVER_TERA] = 1, 2265 }; 2266 2267 static int azx_probe_continue(struct azx *chip) 2268 { 2269 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 2270 struct hdac_bus *bus = azx_bus(chip); 2271 struct pci_dev *pci = chip->pci; 2272 int dev = chip->dev_index; 2273 int err; 2274 2275 if (chip->disabled || hda->init_failed) 2276 return -EIO; 2277 if (hda->probe_retry) 2278 goto probe_retry; 2279 2280 to_hda_bus(bus)->bus_probing = 1; 2281 hda->probe_continued = 1; 2282 2283 /* Request display power well for the HDA controller or codec. For 2284 * Haswell/Broadwell, both the display HDA controller and codec need 2285 * this power. For other platforms, like Baytrail/Braswell, only the 2286 * display codec needs the power and it can be released after probe. 2287 */ 2288 display_power(chip, true); 2289 2290 err = azx_first_init(chip); 2291 if (err < 0) 2292 goto out_free; 2293 2294 #ifdef CONFIG_SND_HDA_INPUT_BEEP 2295 chip->beep_mode = beep_mode[dev]; 2296 #endif 2297 2298 chip->ctl_dev_id = ctl_dev_id; 2299 2300 /* create codec instances */ 2301 if (bus->codec_mask) { 2302 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]); 2303 if (err < 0) 2304 goto out_free; 2305 } 2306 2307 #ifdef CONFIG_SND_HDA_PATCH_LOADER 2308 if (chip->fw) { 2309 err = snd_hda_load_patch(&chip->bus, chip->fw->size, 2310 chip->fw->data); 2311 if (err < 0) 2312 goto out_free; 2313 } 2314 #endif 2315 2316 probe_retry: 2317 if (bus->codec_mask && !(probe_only[dev] & 1)) { 2318 err = azx_codec_configure(chip); 2319 if (err) { 2320 if ((chip->driver_caps & AZX_DCAPS_RETRY_PROBE) && 2321 ++hda->probe_retry < 60) { 2322 schedule_delayed_work(&hda->probe_work, 2323 msecs_to_jiffies(1000)); 2324 return 0; /* keep things up */ 2325 } 2326 dev_err(chip->card->dev, "Cannot probe codecs, giving up\n"); 2327 goto out_free; 2328 } 2329 } 2330 2331 err = snd_card_register(chip->card); 2332 if (err < 0) 2333 goto out_free; 2334 2335 setup_vga_switcheroo_runtime_pm(chip); 2336 2337 chip->running = 1; 2338 azx_add_card_list(chip); 2339 2340 set_default_power_save(chip); 2341 2342 if (azx_has_pm_runtime(chip)) { 2343 pm_runtime_use_autosuspend(&pci->dev); 2344 pm_runtime_allow(&pci->dev); 2345 pm_runtime_put_autosuspend(&pci->dev); 2346 } 2347 2348 out_free: 2349 if (err < 0) { 2350 pci_set_drvdata(pci, NULL); 2351 snd_card_free(chip->card); 2352 return err; 2353 } 2354 2355 if (!hda->need_i915_power) 2356 display_power(chip, false); 2357 complete_all(&hda->probe_wait); 2358 to_hda_bus(bus)->bus_probing = 0; 2359 hda->probe_retry = 0; 2360 return 0; 2361 } 2362 2363 static void azx_remove(struct pci_dev *pci) 2364 { 2365 struct snd_card *card = pci_get_drvdata(pci); 2366 struct azx *chip; 2367 struct hda_intel *hda; 2368 2369 if (card) { 2370 /* cancel the pending probing work */ 2371 chip = card->private_data; 2372 hda = container_of(chip, struct hda_intel, chip); 2373 /* FIXME: below is an ugly workaround. 2374 * Both device_release_driver() and driver_probe_device() 2375 * take *both* the device's and its parent's lock before 2376 * calling the remove() and probe() callbacks. The codec 2377 * probe takes the locks of both the codec itself and its 2378 * parent, i.e. the PCI controller dev. Meanwhile, when 2379 * the PCI controller is unbound, it takes its lock, too 2380 * ==> ouch, a deadlock! 2381 * As a workaround, we unlock temporarily here the controller 2382 * device during cancel_work_sync() call. 2383 */ 2384 device_unlock(&pci->dev); 2385 cancel_delayed_work_sync(&hda->probe_work); 2386 device_lock(&pci->dev); 2387 2388 clear_bit(chip->dev_index, probed_devs); 2389 pci_set_drvdata(pci, NULL); 2390 snd_card_free(card); 2391 } 2392 } 2393 2394 static void azx_shutdown(struct pci_dev *pci) 2395 { 2396 struct snd_card *card = pci_get_drvdata(pci); 2397 struct azx *chip; 2398 2399 if (!card) 2400 return; 2401 chip = card->private_data; 2402 if (chip && chip->running) 2403 __azx_shutdown_chip(chip, true); 2404 } 2405 2406 /* PCI IDs */ 2407 static const struct pci_device_id azx_ids[] = { 2408 /* CPT */ 2409 { PCI_DEVICE_DATA(INTEL, HDA_CPT, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM) }, 2410 /* PBG */ 2411 { PCI_DEVICE_DATA(INTEL, HDA_PBG, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM) }, 2412 /* Panther Point */ 2413 { PCI_DEVICE_DATA(INTEL, HDA_PPT, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM) }, 2414 /* Lynx Point */ 2415 { PCI_DEVICE_DATA(INTEL, HDA_LPT, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) }, 2416 /* 9 Series */ 2417 { PCI_DEVICE_DATA(INTEL, HDA_9_SERIES, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) }, 2418 /* Wellsburg */ 2419 { PCI_DEVICE_DATA(INTEL, HDA_WBG_0, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) }, 2420 { PCI_DEVICE_DATA(INTEL, HDA_WBG_1, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) }, 2421 /* Lewisburg */ 2422 { PCI_DEVICE_DATA(INTEL, HDA_LBG_0, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE) }, 2423 { PCI_DEVICE_DATA(INTEL, HDA_LBG_1, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE) }, 2424 /* Lynx Point-LP */ 2425 { PCI_DEVICE_DATA(INTEL, HDA_LPT_LP_0, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) }, 2426 /* Lynx Point-LP */ 2427 { PCI_DEVICE_DATA(INTEL, HDA_LPT_LP_1, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) }, 2428 /* Wildcat Point-LP */ 2429 { PCI_DEVICE_DATA(INTEL, HDA_WPT_LP, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) }, 2430 /* Skylake (Sunrise Point) */ 2431 { PCI_DEVICE_DATA(INTEL, HDA_SKL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2432 /* Skylake-LP (Sunrise Point-LP) */ 2433 { PCI_DEVICE_DATA(INTEL, HDA_SKL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2434 /* Kabylake */ 2435 { PCI_DEVICE_DATA(INTEL, HDA_KBL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2436 /* Kabylake-LP */ 2437 { PCI_DEVICE_DATA(INTEL, HDA_KBL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2438 /* Kabylake-H */ 2439 { PCI_DEVICE_DATA(INTEL, HDA_KBL_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2440 /* Coffelake */ 2441 { PCI_DEVICE_DATA(INTEL, HDA_CNL_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2442 /* Cannonlake */ 2443 { PCI_DEVICE_DATA(INTEL, HDA_CNL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2444 /* CometLake-LP */ 2445 { PCI_DEVICE_DATA(INTEL, HDA_CML_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2446 /* CometLake-H */ 2447 { PCI_DEVICE_DATA(INTEL, HDA_CML_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2448 { PCI_DEVICE_DATA(INTEL, HDA_RKL_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2449 /* CometLake-S */ 2450 { PCI_DEVICE_DATA(INTEL, HDA_CML_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2451 /* CometLake-R */ 2452 { PCI_DEVICE_DATA(INTEL, HDA_CML_R, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2453 /* Icelake */ 2454 { PCI_DEVICE_DATA(INTEL, HDA_ICL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2455 /* Icelake-H */ 2456 { PCI_DEVICE_DATA(INTEL, HDA_ICL_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2457 /* Jasperlake */ 2458 { PCI_DEVICE_DATA(INTEL, HDA_ICL_N, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2459 { PCI_DEVICE_DATA(INTEL, HDA_JSL_N, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2460 /* Tigerlake */ 2461 { PCI_DEVICE_DATA(INTEL, HDA_TGL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2462 /* Tigerlake-H */ 2463 { PCI_DEVICE_DATA(INTEL, HDA_TGL_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2464 /* DG1 */ 2465 { PCI_DEVICE_DATA(INTEL, HDA_DG1, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2466 /* DG2 */ 2467 { PCI_DEVICE_DATA(INTEL, HDA_DG2_0, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2468 { PCI_DEVICE_DATA(INTEL, HDA_DG2_1, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2469 { PCI_DEVICE_DATA(INTEL, HDA_DG2_2, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2470 /* Alderlake-S */ 2471 { PCI_DEVICE_DATA(INTEL, HDA_ADL_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2472 /* Alderlake-P */ 2473 { PCI_DEVICE_DATA(INTEL, HDA_ADL_P, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2474 { PCI_DEVICE_DATA(INTEL, HDA_ADL_PS, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2475 { PCI_DEVICE_DATA(INTEL, HDA_ADL_PX, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2476 /* Alderlake-M */ 2477 { PCI_DEVICE_DATA(INTEL, HDA_ADL_M, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2478 /* Alderlake-N */ 2479 { PCI_DEVICE_DATA(INTEL, HDA_ADL_N, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2480 /* Elkhart Lake */ 2481 { PCI_DEVICE_DATA(INTEL, HDA_EHL_0, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2482 { PCI_DEVICE_DATA(INTEL, HDA_EHL_3, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2483 /* Raptor Lake */ 2484 { PCI_DEVICE_DATA(INTEL, HDA_RPL_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2485 { PCI_DEVICE_DATA(INTEL, HDA_RPL_P_0, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2486 { PCI_DEVICE_DATA(INTEL, HDA_RPL_P_1, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2487 { PCI_DEVICE_DATA(INTEL, HDA_RPL_M, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2488 { PCI_DEVICE_DATA(INTEL, HDA_RPL_PX, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2489 { PCI_DEVICE_DATA(INTEL, HDA_MTL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2490 /* Battlemage */ 2491 { PCI_DEVICE_DATA(INTEL, HDA_BMG, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2492 /* Lunarlake-P */ 2493 { PCI_DEVICE_DATA(INTEL, HDA_LNL_P, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_LNL) }, 2494 /* Arrow Lake-S */ 2495 { PCI_DEVICE_DATA(INTEL, HDA_ARL_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2496 /* Arrow Lake */ 2497 { PCI_DEVICE_DATA(INTEL, HDA_ARL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2498 /* Apollolake (Broxton-P) */ 2499 { PCI_DEVICE_DATA(INTEL, HDA_APL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON) }, 2500 /* Gemini-Lake */ 2501 { PCI_DEVICE_DATA(INTEL, HDA_GML, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON) }, 2502 /* Haswell */ 2503 { PCI_DEVICE_DATA(INTEL, HDA_HSW_0, AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL) }, 2504 { PCI_DEVICE_DATA(INTEL, HDA_HSW_2, AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL) }, 2505 { PCI_DEVICE_DATA(INTEL, HDA_HSW_3, AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL) }, 2506 /* Broadwell */ 2507 { PCI_DEVICE_DATA(INTEL, HDA_BDW, AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL) }, 2508 /* 5 Series/3400 */ 2509 { PCI_DEVICE_DATA(INTEL, HDA_5_3400_SERIES_0, AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM) }, 2510 { PCI_DEVICE_DATA(INTEL, HDA_5_3400_SERIES_1, AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM) }, 2511 /* Poulsbo */ 2512 { PCI_DEVICE_DATA(INTEL, HDA_POULSBO, AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE | 2513 AZX_DCAPS_POSFIX_LPIB) }, 2514 /* Oaktrail */ 2515 { PCI_DEVICE_DATA(INTEL, HDA_OAKTRAIL, AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE) }, 2516 /* BayTrail */ 2517 { PCI_DEVICE_DATA(INTEL, HDA_BYT, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL) }, 2518 /* Braswell */ 2519 { PCI_DEVICE_DATA(INTEL, HDA_BSW, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL) }, 2520 /* ICH6 */ 2521 { PCI_DEVICE_DATA(INTEL, HDA_ICH6, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) }, 2522 /* ICH7 */ 2523 { PCI_DEVICE_DATA(INTEL, HDA_ICH7, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) }, 2524 /* ESB2 */ 2525 { PCI_DEVICE_DATA(INTEL, HDA_ESB2, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) }, 2526 /* ICH8 */ 2527 { PCI_DEVICE_DATA(INTEL, HDA_ICH8, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) }, 2528 /* ICH9 */ 2529 { PCI_DEVICE_DATA(INTEL, HDA_ICH9_0, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) }, 2530 /* ICH9 */ 2531 { PCI_DEVICE_DATA(INTEL, HDA_ICH9_1, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) }, 2532 /* ICH10 */ 2533 { PCI_DEVICE_DATA(INTEL, HDA_ICH10_0, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) }, 2534 /* ICH10 */ 2535 { PCI_DEVICE_DATA(INTEL, HDA_ICH10_1, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) }, 2536 /* Generic Intel */ 2537 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID), 2538 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2539 .class_mask = 0xffffff, 2540 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE }, 2541 /* ATI SB 450/600/700/800/900 */ 2542 { PCI_VDEVICE(ATI, 0x437b), 2543 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, 2544 { PCI_VDEVICE(ATI, 0x4383), 2545 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, 2546 /* AMD Hudson */ 2547 { PCI_VDEVICE(AMD, 0x780d), 2548 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB }, 2549 /* AMD, X370 & co */ 2550 { PCI_VDEVICE(AMD, 0x1457), 2551 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB }, 2552 /* AMD, X570 & co */ 2553 { PCI_VDEVICE(AMD, 0x1487), 2554 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB }, 2555 /* AMD Stoney */ 2556 { PCI_VDEVICE(AMD, 0x157a), 2557 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB | 2558 AZX_DCAPS_PM_RUNTIME }, 2559 /* AMD Raven */ 2560 { PCI_VDEVICE(AMD, 0x15e3), 2561 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB }, 2562 /* ATI HDMI */ 2563 { PCI_VDEVICE(ATI, 0x0002), 2564 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2565 AZX_DCAPS_PM_RUNTIME }, 2566 { PCI_VDEVICE(ATI, 0x1308), 2567 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2568 { PCI_VDEVICE(ATI, 0x157a), 2569 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2570 { PCI_VDEVICE(ATI, 0x15b3), 2571 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2572 { PCI_VDEVICE(ATI, 0x793b), 2573 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2574 { PCI_VDEVICE(ATI, 0x7919), 2575 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2576 { PCI_VDEVICE(ATI, 0x960f), 2577 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2578 { PCI_VDEVICE(ATI, 0x970f), 2579 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2580 { PCI_VDEVICE(ATI, 0x9840), 2581 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2582 { PCI_VDEVICE(ATI, 0xaa00), 2583 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2584 { PCI_VDEVICE(ATI, 0xaa08), 2585 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2586 { PCI_VDEVICE(ATI, 0xaa10), 2587 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2588 { PCI_VDEVICE(ATI, 0xaa18), 2589 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2590 { PCI_VDEVICE(ATI, 0xaa20), 2591 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2592 { PCI_VDEVICE(ATI, 0xaa28), 2593 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2594 { PCI_VDEVICE(ATI, 0xaa30), 2595 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2596 { PCI_VDEVICE(ATI, 0xaa38), 2597 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2598 { PCI_VDEVICE(ATI, 0xaa40), 2599 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2600 { PCI_VDEVICE(ATI, 0xaa48), 2601 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2602 { PCI_VDEVICE(ATI, 0xaa50), 2603 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2604 { PCI_VDEVICE(ATI, 0xaa58), 2605 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2606 { PCI_VDEVICE(ATI, 0xaa60), 2607 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2608 { PCI_VDEVICE(ATI, 0xaa68), 2609 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2610 { PCI_VDEVICE(ATI, 0xaa80), 2611 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2612 { PCI_VDEVICE(ATI, 0xaa88), 2613 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2614 { PCI_VDEVICE(ATI, 0xaa90), 2615 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2616 { PCI_VDEVICE(ATI, 0xaa98), 2617 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2618 { PCI_VDEVICE(ATI, 0x9902), 2619 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2620 { PCI_VDEVICE(ATI, 0xaaa0), 2621 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2622 { PCI_VDEVICE(ATI, 0xaaa8), 2623 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2624 { PCI_VDEVICE(ATI, 0xaab0), 2625 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2626 { PCI_VDEVICE(ATI, 0xaac0), 2627 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2628 AZX_DCAPS_PM_RUNTIME }, 2629 { PCI_VDEVICE(ATI, 0xaac8), 2630 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2631 AZX_DCAPS_PM_RUNTIME }, 2632 { PCI_VDEVICE(ATI, 0xaad8), 2633 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2634 AZX_DCAPS_PM_RUNTIME }, 2635 { PCI_VDEVICE(ATI, 0xaae0), 2636 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2637 AZX_DCAPS_PM_RUNTIME }, 2638 { PCI_VDEVICE(ATI, 0xaae8), 2639 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2640 AZX_DCAPS_PM_RUNTIME }, 2641 { PCI_VDEVICE(ATI, 0xaaf0), 2642 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2643 AZX_DCAPS_PM_RUNTIME }, 2644 { PCI_VDEVICE(ATI, 0xaaf8), 2645 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2646 AZX_DCAPS_PM_RUNTIME }, 2647 { PCI_VDEVICE(ATI, 0xab00), 2648 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2649 AZX_DCAPS_PM_RUNTIME }, 2650 { PCI_VDEVICE(ATI, 0xab08), 2651 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2652 AZX_DCAPS_PM_RUNTIME }, 2653 { PCI_VDEVICE(ATI, 0xab10), 2654 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2655 AZX_DCAPS_PM_RUNTIME }, 2656 { PCI_VDEVICE(ATI, 0xab18), 2657 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2658 AZX_DCAPS_PM_RUNTIME }, 2659 { PCI_VDEVICE(ATI, 0xab20), 2660 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2661 AZX_DCAPS_PM_RUNTIME }, 2662 { PCI_VDEVICE(ATI, 0xab28), 2663 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2664 AZX_DCAPS_PM_RUNTIME }, 2665 { PCI_VDEVICE(ATI, 0xab30), 2666 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2667 AZX_DCAPS_PM_RUNTIME }, 2668 { PCI_VDEVICE(ATI, 0xab38), 2669 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2670 AZX_DCAPS_PM_RUNTIME }, 2671 /* GLENFLY */ 2672 { PCI_DEVICE(0x6766, PCI_ANY_ID), 2673 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2674 .class_mask = 0xffffff, 2675 .driver_data = AZX_DRIVER_GFHDMI | AZX_DCAPS_POSFIX_LPIB | 2676 AZX_DCAPS_NO_MSI | AZX_DCAPS_NO_64BIT }, 2677 /* VIA VT8251/VT8237A */ 2678 { PCI_VDEVICE(VIA, 0x3288), .driver_data = AZX_DRIVER_VIA }, 2679 /* VIA GFX VT7122/VX900 */ 2680 { PCI_VDEVICE(VIA, 0x9170), .driver_data = AZX_DRIVER_GENERIC }, 2681 /* VIA GFX VT6122/VX11 */ 2682 { PCI_VDEVICE(VIA, 0x9140), .driver_data = AZX_DRIVER_GENERIC }, 2683 /* SIS966 */ 2684 { PCI_VDEVICE(SI, 0x7502), .driver_data = AZX_DRIVER_SIS }, 2685 /* ULI M5461 */ 2686 { PCI_VDEVICE(AL, 0x5461), .driver_data = AZX_DRIVER_ULI }, 2687 /* NVIDIA MCP */ 2688 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID), 2689 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2690 .class_mask = 0xffffff, 2691 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA }, 2692 /* Teradici */ 2693 { PCI_DEVICE(0x6549, 0x1200), 2694 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, 2695 { PCI_DEVICE(0x6549, 0x2200), 2696 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, 2697 /* Creative X-Fi (CA0110-IBG) */ 2698 /* CTHDA chips */ 2699 { PCI_VDEVICE(CREATIVE, 0x0010), 2700 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, 2701 { PCI_VDEVICE(CREATIVE, 0x0012), 2702 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, 2703 #if !IS_ENABLED(CONFIG_SND_CTXFI) 2704 /* the following entry conflicts with snd-ctxfi driver, 2705 * as ctxfi driver mutates from HD-audio to native mode with 2706 * a special command sequence. 2707 */ 2708 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID), 2709 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2710 .class_mask = 0xffffff, 2711 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | 2712 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB }, 2713 #else 2714 /* this entry seems still valid -- i.e. without emu20kx chip */ 2715 { PCI_VDEVICE(CREATIVE, 0x0009), 2716 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | 2717 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB }, 2718 #endif 2719 /* CM8888 */ 2720 { PCI_VDEVICE(CMEDIA, 0x5011), 2721 .driver_data = AZX_DRIVER_CMEDIA | 2722 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF }, 2723 /* Vortex86MX */ 2724 { PCI_VDEVICE(RDC, 0x3010), .driver_data = AZX_DRIVER_GENERIC }, 2725 /* VMware HDAudio */ 2726 { PCI_VDEVICE(VMWARE, 0x1977), .driver_data = AZX_DRIVER_GENERIC }, 2727 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */ 2728 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID), 2729 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2730 .class_mask = 0xffffff, 2731 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, 2732 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID), 2733 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2734 .class_mask = 0xffffff, 2735 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, 2736 /* Zhaoxin */ 2737 { PCI_VDEVICE(ZHAOXIN, 0x3288), .driver_data = AZX_DRIVER_ZHAOXIN }, 2738 /* Loongson HDAudio*/ 2739 { PCI_VDEVICE(LOONGSON, PCI_DEVICE_ID_LOONGSON_HDA), 2740 .driver_data = AZX_DRIVER_LOONGSON }, 2741 { PCI_VDEVICE(LOONGSON, PCI_DEVICE_ID_LOONGSON_HDMI), 2742 .driver_data = AZX_DRIVER_LOONGSON }, 2743 { 0, } 2744 }; 2745 MODULE_DEVICE_TABLE(pci, azx_ids); 2746 2747 /* pci_driver definition */ 2748 static struct pci_driver azx_driver = { 2749 .name = KBUILD_MODNAME, 2750 .id_table = azx_ids, 2751 .probe = azx_probe, 2752 .remove = azx_remove, 2753 .shutdown = azx_shutdown, 2754 .driver = { 2755 .pm = &azx_pm, 2756 }, 2757 }; 2758 2759 module_pci_driver(azx_driver); 2760