1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * 4 * hda_intel.c - Implementation of primary alsa driver code base 5 * for Intel HD Audio. 6 * 7 * Copyright(c) 2004 Intel Corporation 8 * 9 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> 10 * PeiSen Hou <pshou@realtek.com.tw> 11 * 12 * CONTACTS: 13 * 14 * Matt Jared matt.jared@intel.com 15 * Andy Kopp andy.kopp@intel.com 16 * Dan Kogan dan.d.kogan@intel.com 17 * 18 * CHANGES: 19 * 20 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou 21 */ 22 23 #include <linux/delay.h> 24 #include <linux/interrupt.h> 25 #include <linux/kernel.h> 26 #include <linux/module.h> 27 #include <linux/dma-mapping.h> 28 #include <linux/moduleparam.h> 29 #include <linux/init.h> 30 #include <linux/slab.h> 31 #include <linux/pci.h> 32 #include <linux/mutex.h> 33 #include <linux/io.h> 34 #include <linux/pm_runtime.h> 35 #include <linux/clocksource.h> 36 #include <linux/time.h> 37 #include <linux/completion.h> 38 #include <linux/acpi.h> 39 #include <linux/pgtable.h> 40 41 #ifdef CONFIG_X86 42 /* for snoop control */ 43 #include <linux/dma-map-ops.h> 44 #include <asm/set_memory.h> 45 #include <asm/cpufeature.h> 46 #endif 47 #include <sound/core.h> 48 #include <sound/initval.h> 49 #include <sound/hdaudio.h> 50 #include <sound/hda_i915.h> 51 #include <sound/intel-dsp-config.h> 52 #include <linux/vgaarb.h> 53 #include <linux/vga_switcheroo.h> 54 #include <linux/apple-gmux.h> 55 #include <linux/firmware.h> 56 #include <sound/hda_codec.h> 57 #include "hda_controller.h" 58 #include "hda_intel.h" 59 60 #define CREATE_TRACE_POINTS 61 #include "hda_intel_trace.h" 62 63 /* position fix mode */ 64 enum { 65 POS_FIX_AUTO, 66 POS_FIX_LPIB, 67 POS_FIX_POSBUF, 68 POS_FIX_VIACOMBO, 69 POS_FIX_COMBO, 70 POS_FIX_SKL, 71 POS_FIX_FIFO, 72 }; 73 74 /* Defines for ATI HD Audio support in SB450 south bridge */ 75 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42 76 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02 77 78 /* Defines for Nvidia HDA support */ 79 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e 80 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f 81 #define NVIDIA_HDA_ISTRM_COH 0x4d 82 #define NVIDIA_HDA_OSTRM_COH 0x4c 83 #define NVIDIA_HDA_ENABLE_COHBIT 0x01 84 85 /* Defines for Intel SCH HDA snoop control */ 86 #define INTEL_HDA_CGCTL 0x48 87 #define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6) 88 #define INTEL_SCH_HDA_DEVC 0x78 89 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11) 90 91 /* max number of SDs */ 92 /* ICH, ATI and VIA have 4 playback and 4 capture */ 93 #define ICH6_NUM_CAPTURE 4 94 #define ICH6_NUM_PLAYBACK 4 95 96 /* ULI has 6 playback and 5 capture */ 97 #define ULI_NUM_CAPTURE 5 98 #define ULI_NUM_PLAYBACK 6 99 100 /* ATI HDMI may have up to 8 playbacks and 0 capture */ 101 #define ATIHDMI_NUM_CAPTURE 0 102 #define ATIHDMI_NUM_PLAYBACK 8 103 104 105 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; 106 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; 107 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; 108 static char *model[SNDRV_CARDS]; 109 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 110 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 111 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 112 static int probe_only[SNDRV_CARDS]; 113 static int jackpoll_ms[SNDRV_CARDS]; 114 static int single_cmd = -1; 115 static int enable_msi = -1; 116 #ifdef CONFIG_SND_HDA_PATCH_LOADER 117 static char *patch[SNDRV_CARDS]; 118 #endif 119 #ifdef CONFIG_SND_HDA_INPUT_BEEP 120 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = 121 CONFIG_SND_HDA_INPUT_BEEP_MODE}; 122 #endif 123 static bool dmic_detect = 1; 124 static bool ctl_dev_id = IS_ENABLED(CONFIG_SND_HDA_CTL_DEV_ID) ? 1 : 0; 125 126 module_param_array(index, int, NULL, 0444); 127 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface."); 128 module_param_array(id, charp, NULL, 0444); 129 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface."); 130 module_param_array(enable, bool, NULL, 0444); 131 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface."); 132 module_param_array(model, charp, NULL, 0444); 133 MODULE_PARM_DESC(model, "Use the given board model."); 134 module_param_array(position_fix, int, NULL, 0444); 135 MODULE_PARM_DESC(position_fix, "DMA pointer read method." 136 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+, 6 = FIFO)."); 137 module_param_array(bdl_pos_adj, int, NULL, 0644); 138 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset."); 139 module_param_array(probe_mask, int, NULL, 0444); 140 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1)."); 141 module_param_array(probe_only, int, NULL, 0444); 142 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization."); 143 module_param_array(jackpoll_ms, int, NULL, 0444); 144 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)"); 145 module_param(single_cmd, bint, 0444); 146 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs " 147 "(for debugging only)."); 148 module_param(enable_msi, bint, 0444); 149 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)"); 150 #ifdef CONFIG_SND_HDA_PATCH_LOADER 151 module_param_array(patch, charp, NULL, 0444); 152 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface."); 153 #endif 154 #ifdef CONFIG_SND_HDA_INPUT_BEEP 155 module_param_array(beep_mode, bool, NULL, 0444); 156 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode " 157 "(0=off, 1=on) (default=1)."); 158 #endif 159 module_param(dmic_detect, bool, 0444); 160 MODULE_PARM_DESC(dmic_detect, "Allow DSP driver selection (bypass this driver) " 161 "(0=off, 1=on) (default=1); " 162 "deprecated, use snd-intel-dspcfg.dsp_driver option instead"); 163 module_param(ctl_dev_id, bool, 0444); 164 MODULE_PARM_DESC(ctl_dev_id, "Use control device identifier (based on codec address)."); 165 166 #ifdef CONFIG_PM 167 static int param_set_xint(const char *val, const struct kernel_param *kp); 168 static const struct kernel_param_ops param_ops_xint = { 169 .set = param_set_xint, 170 .get = param_get_int, 171 }; 172 #define param_check_xint param_check_int 173 174 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT; 175 module_param(power_save, xint, 0644); 176 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout " 177 "(in second, 0 = disable)."); 178 179 static int pm_blacklist = -1; 180 module_param(pm_blacklist, bint, 0644); 181 MODULE_PARM_DESC(pm_blacklist, "Enable power-management denylist"); 182 183 /* reset the HD-audio controller in power save mode. 184 * this may give more power-saving, but will take longer time to 185 * wake up. 186 */ 187 static bool power_save_controller = 1; 188 module_param(power_save_controller, bool, 0644); 189 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode."); 190 #else /* CONFIG_PM */ 191 #define power_save 0 192 #define pm_blacklist 0 193 #define power_save_controller false 194 #endif /* CONFIG_PM */ 195 196 static int align_buffer_size = -1; 197 module_param(align_buffer_size, bint, 0644); 198 MODULE_PARM_DESC(align_buffer_size, 199 "Force buffer and period sizes to be multiple of 128 bytes."); 200 201 #ifdef CONFIG_X86 202 static int hda_snoop = -1; 203 module_param_named(snoop, hda_snoop, bint, 0444); 204 MODULE_PARM_DESC(snoop, "Enable/disable snooping"); 205 #else 206 #define hda_snoop true 207 #endif 208 209 210 MODULE_LICENSE("GPL"); 211 MODULE_DESCRIPTION("Intel HDA driver"); 212 213 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO) 214 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI) 215 #define SUPPORT_VGA_SWITCHEROO 216 #endif 217 #endif 218 219 220 /* 221 */ 222 223 /* driver types */ 224 enum { 225 AZX_DRIVER_ICH, 226 AZX_DRIVER_PCH, 227 AZX_DRIVER_SCH, 228 AZX_DRIVER_SKL, 229 AZX_DRIVER_HDMI, 230 AZX_DRIVER_ATI, 231 AZX_DRIVER_ATIHDMI, 232 AZX_DRIVER_ATIHDMI_NS, 233 AZX_DRIVER_GFHDMI, 234 AZX_DRIVER_VIA, 235 AZX_DRIVER_SIS, 236 AZX_DRIVER_ULI, 237 AZX_DRIVER_NVIDIA, 238 AZX_DRIVER_TERA, 239 AZX_DRIVER_CTX, 240 AZX_DRIVER_CTHDA, 241 AZX_DRIVER_CMEDIA, 242 AZX_DRIVER_ZHAOXIN, 243 AZX_DRIVER_LOONGSON, 244 AZX_DRIVER_GENERIC, 245 AZX_NUM_DRIVERS, /* keep this as last entry */ 246 }; 247 248 #define azx_get_snoop_type(chip) \ 249 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10) 250 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10) 251 252 /* quirks for old Intel chipsets */ 253 #define AZX_DCAPS_INTEL_ICH \ 254 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE) 255 256 /* quirks for Intel PCH */ 257 #define AZX_DCAPS_INTEL_PCH_BASE \ 258 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\ 259 AZX_DCAPS_SNOOP_TYPE(SCH)) 260 261 /* PCH up to IVB; no runtime PM; bind with i915 gfx */ 262 #define AZX_DCAPS_INTEL_PCH_NOPM \ 263 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT) 264 265 /* PCH for HSW/BDW; with runtime PM */ 266 /* no i915 binding for this as HSW/BDW has another controller for HDMI */ 267 #define AZX_DCAPS_INTEL_PCH \ 268 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME) 269 270 /* HSW HDMI */ 271 #define AZX_DCAPS_INTEL_HASWELL \ 272 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\ 273 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\ 274 AZX_DCAPS_SNOOP_TYPE(SCH)) 275 276 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */ 277 #define AZX_DCAPS_INTEL_BROADWELL \ 278 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\ 279 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\ 280 AZX_DCAPS_SNOOP_TYPE(SCH)) 281 282 #define AZX_DCAPS_INTEL_BAYTRAIL \ 283 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT) 284 285 #define AZX_DCAPS_INTEL_BRASWELL \ 286 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\ 287 AZX_DCAPS_I915_COMPONENT) 288 289 #define AZX_DCAPS_INTEL_SKYLAKE \ 290 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\ 291 AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT) 292 293 #define AZX_DCAPS_INTEL_BROXTON AZX_DCAPS_INTEL_SKYLAKE 294 295 #define AZX_DCAPS_INTEL_LNL \ 296 (AZX_DCAPS_INTEL_SKYLAKE | AZX_DCAPS_PIO_COMMANDS) 297 298 /* quirks for ATI SB / AMD Hudson */ 299 #define AZX_DCAPS_PRESET_ATI_SB \ 300 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB |\ 301 AZX_DCAPS_SNOOP_TYPE(ATI)) 302 303 /* quirks for ATI/AMD HDMI */ 304 #define AZX_DCAPS_PRESET_ATI_HDMI \ 305 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB|\ 306 AZX_DCAPS_NO_MSI64) 307 308 /* quirks for ATI HDMI with snoop off */ 309 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \ 310 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_AMD_ALLOC_FIX) 311 312 /* quirks for AMD SB */ 313 #define AZX_DCAPS_PRESET_AMD_SB \ 314 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_AMD_WORKAROUND |\ 315 AZX_DCAPS_SNOOP_TYPE(ATI) | AZX_DCAPS_PM_RUNTIME |\ 316 AZX_DCAPS_RETRY_PROBE) 317 318 /* quirks for Nvidia */ 319 #define AZX_DCAPS_PRESET_NVIDIA \ 320 (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\ 321 AZX_DCAPS_SNOOP_TYPE(NVIDIA)) 322 323 #define AZX_DCAPS_PRESET_CTHDA \ 324 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\ 325 AZX_DCAPS_NO_64BIT |\ 326 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF) 327 328 /* 329 * vga_switcheroo support 330 */ 331 #ifdef SUPPORT_VGA_SWITCHEROO 332 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo) 333 #define needs_eld_notify_link(chip) ((chip)->bus.keep_power) 334 #else 335 #define use_vga_switcheroo(chip) 0 336 #define needs_eld_notify_link(chip) false 337 #endif 338 339 static const char * const driver_short_names[] = { 340 [AZX_DRIVER_ICH] = "HDA Intel", 341 [AZX_DRIVER_PCH] = "HDA Intel PCH", 342 [AZX_DRIVER_SCH] = "HDA Intel MID", 343 [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */ 344 [AZX_DRIVER_HDMI] = "HDA Intel HDMI", 345 [AZX_DRIVER_ATI] = "HDA ATI SB", 346 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI", 347 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI", 348 [AZX_DRIVER_GFHDMI] = "HDA GF HDMI", 349 [AZX_DRIVER_VIA] = "HDA VIA VT82xx", 350 [AZX_DRIVER_SIS] = "HDA SIS966", 351 [AZX_DRIVER_ULI] = "HDA ULI M5461", 352 [AZX_DRIVER_NVIDIA] = "HDA NVidia", 353 [AZX_DRIVER_TERA] = "HDA Teradici", 354 [AZX_DRIVER_CTX] = "HDA Creative", 355 [AZX_DRIVER_CTHDA] = "HDA Creative", 356 [AZX_DRIVER_CMEDIA] = "HDA C-Media", 357 [AZX_DRIVER_ZHAOXIN] = "HDA Zhaoxin", 358 [AZX_DRIVER_LOONGSON] = "HDA Loongson", 359 [AZX_DRIVER_GENERIC] = "HD-Audio Generic", 360 }; 361 362 static int azx_acquire_irq(struct azx *chip, int do_disconnect); 363 static void set_default_power_save(struct azx *chip); 364 365 /* 366 * initialize the PCI registers 367 */ 368 /* update bits in a PCI register byte */ 369 static void update_pci_byte(struct pci_dev *pci, unsigned int reg, 370 unsigned char mask, unsigned char val) 371 { 372 unsigned char data; 373 374 pci_read_config_byte(pci, reg, &data); 375 data &= ~mask; 376 data |= (val & mask); 377 pci_write_config_byte(pci, reg, data); 378 } 379 380 static void azx_init_pci(struct azx *chip) 381 { 382 int snoop_type = azx_get_snoop_type(chip); 383 384 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44) 385 * TCSEL == Traffic Class Select Register, which sets PCI express QOS 386 * Ensuring these bits are 0 clears playback static on some HD Audio 387 * codecs. 388 * The PCI register TCSEL is defined in the Intel manuals. 389 */ 390 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) { 391 dev_dbg(chip->card->dev, "Clearing TCSEL\n"); 392 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0); 393 } 394 395 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio, 396 * we need to enable snoop. 397 */ 398 if (snoop_type == AZX_SNOOP_TYPE_ATI) { 399 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n", 400 azx_snoop(chip)); 401 update_pci_byte(chip->pci, 402 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07, 403 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0); 404 } 405 406 /* For NVIDIA HDA, enable snoop */ 407 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) { 408 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n", 409 azx_snoop(chip)); 410 update_pci_byte(chip->pci, 411 NVIDIA_HDA_TRANSREG_ADDR, 412 0x0f, NVIDIA_HDA_ENABLE_COHBITS); 413 update_pci_byte(chip->pci, 414 NVIDIA_HDA_ISTRM_COH, 415 0x01, NVIDIA_HDA_ENABLE_COHBIT); 416 update_pci_byte(chip->pci, 417 NVIDIA_HDA_OSTRM_COH, 418 0x01, NVIDIA_HDA_ENABLE_COHBIT); 419 } 420 421 /* Enable SCH/PCH snoop if needed */ 422 if (snoop_type == AZX_SNOOP_TYPE_SCH) { 423 unsigned short snoop; 424 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop); 425 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) || 426 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) { 427 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP; 428 if (!azx_snoop(chip)) 429 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP; 430 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop); 431 pci_read_config_word(chip->pci, 432 INTEL_SCH_HDA_DEVC, &snoop); 433 } 434 dev_dbg(chip->card->dev, "SCH snoop: %s\n", 435 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ? 436 "Disabled" : "Enabled"); 437 } 438 } 439 440 /* 441 * In BXT-P A0, HD-Audio DMA requests is later than expected, 442 * and makes an audio stream sensitive to system latencies when 443 * 24/32 bits are playing. 444 * Adjusting threshold of DMA fifo to force the DMA request 445 * sooner to improve latency tolerance at the expense of power. 446 */ 447 static void bxt_reduce_dma_latency(struct azx *chip) 448 { 449 u32 val; 450 451 val = azx_readl(chip, VS_EM4L); 452 val &= (0x3 << 20); 453 azx_writel(chip, VS_EM4L, val); 454 } 455 456 /* 457 * ML_LCAP bits: 458 * bit 0: 6 MHz Supported 459 * bit 1: 12 MHz Supported 460 * bit 2: 24 MHz Supported 461 * bit 3: 48 MHz Supported 462 * bit 4: 96 MHz Supported 463 * bit 5: 192 MHz Supported 464 */ 465 static int intel_get_lctl_scf(struct azx *chip) 466 { 467 struct hdac_bus *bus = azx_bus(chip); 468 static const int preferred_bits[] = { 2, 3, 1, 4, 5 }; 469 u32 val, t; 470 int i; 471 472 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP); 473 474 for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) { 475 t = preferred_bits[i]; 476 if (val & (1 << t)) 477 return t; 478 } 479 480 dev_warn(chip->card->dev, "set audio clock frequency to 6MHz"); 481 return 0; 482 } 483 484 static int intel_ml_lctl_set_power(struct azx *chip, int state) 485 { 486 struct hdac_bus *bus = azx_bus(chip); 487 u32 val; 488 int timeout; 489 490 /* 491 * Changes to LCTL.SCF are only needed for the first multi-link dealing 492 * with external codecs 493 */ 494 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 495 val &= ~AZX_ML_LCTL_SPA; 496 val |= state << AZX_ML_LCTL_SPA_SHIFT; 497 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 498 /* wait for CPA */ 499 timeout = 50; 500 while (timeout) { 501 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) & 502 AZX_ML_LCTL_CPA) == (state << AZX_ML_LCTL_CPA_SHIFT)) 503 return 0; 504 timeout--; 505 udelay(10); 506 } 507 508 return -1; 509 } 510 511 static void intel_init_lctl(struct azx *chip) 512 { 513 struct hdac_bus *bus = azx_bus(chip); 514 u32 val; 515 int ret; 516 517 /* 0. check lctl register value is correct or not */ 518 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 519 /* only perform additional configurations if the SCF is initially based on 6MHz */ 520 if ((val & AZX_ML_LCTL_SCF) != 0) 521 return; 522 523 /* 524 * Before operating on SPA, CPA must match SPA. 525 * Any deviation may result in undefined behavior. 526 */ 527 if (((val & AZX_ML_LCTL_SPA) >> AZX_ML_LCTL_SPA_SHIFT) != 528 ((val & AZX_ML_LCTL_CPA) >> AZX_ML_LCTL_CPA_SHIFT)) 529 return; 530 531 /* 1. turn link down: set SPA to 0 and wait CPA to 0 */ 532 ret = intel_ml_lctl_set_power(chip, 0); 533 udelay(100); 534 if (ret) 535 goto set_spa; 536 537 /* 2. update SCF to select an audio clock different from 6MHz */ 538 val &= ~AZX_ML_LCTL_SCF; 539 val |= intel_get_lctl_scf(chip); 540 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 541 542 set_spa: 543 /* 4. turn link up: set SPA to 1 and wait CPA to 1 */ 544 intel_ml_lctl_set_power(chip, 1); 545 udelay(100); 546 } 547 548 static void hda_intel_init_chip(struct azx *chip, bool full_reset) 549 { 550 struct hdac_bus *bus = azx_bus(chip); 551 struct pci_dev *pci = chip->pci; 552 u32 val; 553 554 snd_hdac_set_codec_wakeup(bus, true); 555 if (chip->driver_type == AZX_DRIVER_SKL) { 556 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val); 557 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE; 558 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val); 559 } 560 azx_init_chip(chip, full_reset); 561 if (chip->driver_type == AZX_DRIVER_SKL) { 562 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val); 563 val = val | INTEL_HDA_CGCTL_MISCBDCGE; 564 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val); 565 } 566 567 snd_hdac_set_codec_wakeup(bus, false); 568 569 /* reduce dma latency to avoid noise */ 570 if (HDA_CONTROLLER_IS_APL(pci)) 571 bxt_reduce_dma_latency(chip); 572 573 if (bus->mlcap != NULL) 574 intel_init_lctl(chip); 575 } 576 577 /* calculate runtime delay from LPIB */ 578 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev, 579 unsigned int pos) 580 { 581 struct snd_pcm_substream *substream = azx_dev->core.substream; 582 int stream = substream->stream; 583 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev); 584 int delay; 585 586 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 587 delay = pos - lpib_pos; 588 else 589 delay = lpib_pos - pos; 590 if (delay < 0) { 591 if (delay >= azx_dev->core.delay_negative_threshold) 592 delay = 0; 593 else 594 delay += azx_dev->core.bufsize; 595 } 596 597 if (delay >= azx_dev->core.period_bytes) { 598 dev_info(chip->card->dev, 599 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n", 600 delay, azx_dev->core.period_bytes); 601 delay = 0; 602 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY; 603 chip->get_delay[stream] = NULL; 604 } 605 606 return bytes_to_frames(substream->runtime, delay); 607 } 608 609 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev); 610 611 /* called from IRQ */ 612 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev) 613 { 614 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 615 int ok; 616 617 ok = azx_position_ok(chip, azx_dev); 618 if (ok == 1) { 619 azx_dev->irq_pending = 0; 620 return ok; 621 } else if (ok == 0) { 622 /* bogus IRQ, process it later */ 623 azx_dev->irq_pending = 1; 624 schedule_work(&hda->irq_pending_work); 625 } 626 return 0; 627 } 628 629 #define display_power(chip, enable) \ 630 snd_hdac_display_power(azx_bus(chip), HDA_CODEC_IDX_CONTROLLER, enable) 631 632 /* 633 * Check whether the current DMA position is acceptable for updating 634 * periods. Returns non-zero if it's OK. 635 * 636 * Many HD-audio controllers appear pretty inaccurate about 637 * the update-IRQ timing. The IRQ is issued before actually the 638 * data is processed. So, we need to process it afterwords in a 639 * workqueue. 640 * 641 * Returns 1 if OK to proceed, 0 for delay handling, -1 for skipping update 642 */ 643 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev) 644 { 645 struct snd_pcm_substream *substream = azx_dev->core.substream; 646 struct snd_pcm_runtime *runtime = substream->runtime; 647 int stream = substream->stream; 648 u32 wallclk; 649 unsigned int pos; 650 snd_pcm_uframes_t hwptr, target; 651 652 /* 653 * The value of the WALLCLK register is always 0 654 * on the Loongson controller, so we return directly. 655 */ 656 if (chip->driver_type == AZX_DRIVER_LOONGSON) 657 return 1; 658 659 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk; 660 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3) 661 return -1; /* bogus (too early) interrupt */ 662 663 if (chip->get_position[stream]) 664 pos = chip->get_position[stream](chip, azx_dev); 665 else { /* use the position buffer as default */ 666 pos = azx_get_pos_posbuf(chip, azx_dev); 667 if (!pos || pos == (u32)-1) { 668 dev_info(chip->card->dev, 669 "Invalid position buffer, using LPIB read method instead.\n"); 670 chip->get_position[stream] = azx_get_pos_lpib; 671 if (chip->get_position[0] == azx_get_pos_lpib && 672 chip->get_position[1] == azx_get_pos_lpib) 673 azx_bus(chip)->use_posbuf = false; 674 pos = azx_get_pos_lpib(chip, azx_dev); 675 chip->get_delay[stream] = NULL; 676 } else { 677 chip->get_position[stream] = azx_get_pos_posbuf; 678 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY) 679 chip->get_delay[stream] = azx_get_delay_from_lpib; 680 } 681 } 682 683 if (pos >= azx_dev->core.bufsize) 684 pos = 0; 685 686 if (WARN_ONCE(!azx_dev->core.period_bytes, 687 "hda-intel: zero azx_dev->period_bytes")) 688 return -1; /* this shouldn't happen! */ 689 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 && 690 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2) 691 /* NG - it's below the first next period boundary */ 692 return chip->bdl_pos_adj ? 0 : -1; 693 azx_dev->core.start_wallclk += wallclk; 694 695 if (azx_dev->core.no_period_wakeup) 696 return 1; /* OK, no need to check period boundary */ 697 698 if (runtime->hw_ptr_base != runtime->hw_ptr_interrupt) 699 return 1; /* OK, already in hwptr updating process */ 700 701 /* check whether the period gets really elapsed */ 702 pos = bytes_to_frames(runtime, pos); 703 hwptr = runtime->hw_ptr_base + pos; 704 if (hwptr < runtime->status->hw_ptr) 705 hwptr += runtime->buffer_size; 706 target = runtime->hw_ptr_interrupt + runtime->period_size; 707 if (hwptr < target) { 708 /* too early wakeup, process it later */ 709 return chip->bdl_pos_adj ? 0 : -1; 710 } 711 712 return 1; /* OK, it's fine */ 713 } 714 715 /* 716 * The work for pending PCM period updates. 717 */ 718 static void azx_irq_pending_work(struct work_struct *work) 719 { 720 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work); 721 struct azx *chip = &hda->chip; 722 struct hdac_bus *bus = azx_bus(chip); 723 struct hdac_stream *s; 724 int pending, ok; 725 726 if (!hda->irq_pending_warned) { 727 dev_info(chip->card->dev, 728 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n", 729 chip->card->number); 730 hda->irq_pending_warned = 1; 731 } 732 733 for (;;) { 734 pending = 0; 735 spin_lock_irq(&bus->reg_lock); 736 list_for_each_entry(s, &bus->stream_list, list) { 737 struct azx_dev *azx_dev = stream_to_azx_dev(s); 738 if (!azx_dev->irq_pending || 739 !s->substream || 740 !s->running) 741 continue; 742 ok = azx_position_ok(chip, azx_dev); 743 if (ok > 0) { 744 azx_dev->irq_pending = 0; 745 spin_unlock(&bus->reg_lock); 746 snd_pcm_period_elapsed(s->substream); 747 spin_lock(&bus->reg_lock); 748 } else if (ok < 0) { 749 pending = 0; /* too early */ 750 } else 751 pending++; 752 } 753 spin_unlock_irq(&bus->reg_lock); 754 if (!pending) 755 return; 756 msleep(1); 757 } 758 } 759 760 /* clear irq_pending flags and assure no on-going workq */ 761 static void azx_clear_irq_pending(struct azx *chip) 762 { 763 struct hdac_bus *bus = azx_bus(chip); 764 struct hdac_stream *s; 765 766 spin_lock_irq(&bus->reg_lock); 767 list_for_each_entry(s, &bus->stream_list, list) { 768 struct azx_dev *azx_dev = stream_to_azx_dev(s); 769 azx_dev->irq_pending = 0; 770 } 771 spin_unlock_irq(&bus->reg_lock); 772 } 773 774 static int azx_acquire_irq(struct azx *chip, int do_disconnect) 775 { 776 struct hdac_bus *bus = azx_bus(chip); 777 778 if (request_irq(chip->pci->irq, azx_interrupt, 779 chip->msi ? 0 : IRQF_SHARED, 780 chip->card->irq_descr, chip)) { 781 dev_err(chip->card->dev, 782 "unable to grab IRQ %d, disabling device\n", 783 chip->pci->irq); 784 if (do_disconnect) 785 snd_card_disconnect(chip->card); 786 return -1; 787 } 788 bus->irq = chip->pci->irq; 789 chip->card->sync_irq = bus->irq; 790 pci_intx(chip->pci, !chip->msi); 791 return 0; 792 } 793 794 /* get the current DMA position with correction on VIA chips */ 795 static unsigned int azx_via_get_position(struct azx *chip, 796 struct azx_dev *azx_dev) 797 { 798 unsigned int link_pos, mini_pos, bound_pos; 799 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos; 800 unsigned int fifo_size; 801 802 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev)); 803 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 804 /* Playback, no problem using link position */ 805 return link_pos; 806 } 807 808 /* Capture */ 809 /* For new chipset, 810 * use mod to get the DMA position just like old chipset 811 */ 812 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf); 813 mod_dma_pos %= azx_dev->core.period_bytes; 814 815 fifo_size = azx_stream(azx_dev)->fifo_size; 816 817 if (azx_dev->insufficient) { 818 /* Link position never gather than FIFO size */ 819 if (link_pos <= fifo_size) 820 return 0; 821 822 azx_dev->insufficient = 0; 823 } 824 825 if (link_pos <= fifo_size) 826 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size; 827 else 828 mini_pos = link_pos - fifo_size; 829 830 /* Find nearest previous boudary */ 831 mod_mini_pos = mini_pos % azx_dev->core.period_bytes; 832 mod_link_pos = link_pos % azx_dev->core.period_bytes; 833 if (mod_link_pos >= fifo_size) 834 bound_pos = link_pos - mod_link_pos; 835 else if (mod_dma_pos >= mod_mini_pos) 836 bound_pos = mini_pos - mod_mini_pos; 837 else { 838 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes; 839 if (bound_pos >= azx_dev->core.bufsize) 840 bound_pos = 0; 841 } 842 843 /* Calculate real DMA position we want */ 844 return bound_pos + mod_dma_pos; 845 } 846 847 #define AMD_FIFO_SIZE 32 848 849 /* get the current DMA position with FIFO size correction */ 850 static unsigned int azx_get_pos_fifo(struct azx *chip, struct azx_dev *azx_dev) 851 { 852 struct snd_pcm_substream *substream = azx_dev->core.substream; 853 struct snd_pcm_runtime *runtime = substream->runtime; 854 unsigned int pos, delay; 855 856 pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev)); 857 if (!runtime) 858 return pos; 859 860 runtime->delay = AMD_FIFO_SIZE; 861 delay = frames_to_bytes(runtime, AMD_FIFO_SIZE); 862 if (azx_dev->insufficient) { 863 if (pos < delay) { 864 delay = pos; 865 runtime->delay = bytes_to_frames(runtime, pos); 866 } else { 867 azx_dev->insufficient = 0; 868 } 869 } 870 871 /* correct the DMA position for capture stream */ 872 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { 873 if (pos < delay) 874 pos += azx_dev->core.bufsize; 875 pos -= delay; 876 } 877 878 return pos; 879 } 880 881 static int azx_get_delay_from_fifo(struct azx *chip, struct azx_dev *azx_dev, 882 unsigned int pos) 883 { 884 struct snd_pcm_substream *substream = azx_dev->core.substream; 885 886 /* just read back the calculated value in the above */ 887 return substream->runtime->delay; 888 } 889 890 static void __azx_shutdown_chip(struct azx *chip, bool skip_link_reset) 891 { 892 azx_stop_chip(chip); 893 if (!skip_link_reset) 894 azx_enter_link_reset(chip); 895 azx_clear_irq_pending(chip); 896 display_power(chip, false); 897 } 898 899 static DEFINE_MUTEX(card_list_lock); 900 static LIST_HEAD(card_list); 901 902 static void azx_shutdown_chip(struct azx *chip) 903 { 904 __azx_shutdown_chip(chip, false); 905 } 906 907 static void azx_add_card_list(struct azx *chip) 908 { 909 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 910 mutex_lock(&card_list_lock); 911 list_add(&hda->list, &card_list); 912 mutex_unlock(&card_list_lock); 913 } 914 915 static void azx_del_card_list(struct azx *chip) 916 { 917 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 918 mutex_lock(&card_list_lock); 919 list_del_init(&hda->list); 920 mutex_unlock(&card_list_lock); 921 } 922 923 /* trigger power-save check at writing parameter */ 924 static int __maybe_unused param_set_xint(const char *val, const struct kernel_param *kp) 925 { 926 struct hda_intel *hda; 927 struct azx *chip; 928 int prev = power_save; 929 int ret = param_set_int(val, kp); 930 931 if (ret || prev == power_save) 932 return ret; 933 934 if (pm_blacklist > 0) 935 return 0; 936 937 mutex_lock(&card_list_lock); 938 list_for_each_entry(hda, &card_list, list) { 939 chip = &hda->chip; 940 if (!hda->probe_continued || chip->disabled || 941 hda->runtime_pm_disabled) 942 continue; 943 snd_hda_set_power_save(&chip->bus, power_save * 1000); 944 } 945 mutex_unlock(&card_list_lock); 946 return 0; 947 } 948 949 /* 950 * power management 951 */ 952 static bool azx_is_pm_ready(struct snd_card *card) 953 { 954 struct azx *chip; 955 struct hda_intel *hda; 956 957 if (!card) 958 return false; 959 chip = card->private_data; 960 hda = container_of(chip, struct hda_intel, chip); 961 if (chip->disabled || hda->init_failed || !chip->running) 962 return false; 963 return true; 964 } 965 966 static void __azx_runtime_resume(struct azx *chip) 967 { 968 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 969 struct hdac_bus *bus = azx_bus(chip); 970 struct hda_codec *codec; 971 int status; 972 973 display_power(chip, true); 974 if (hda->need_i915_power) 975 snd_hdac_i915_set_bclk(bus); 976 977 /* Read STATESTS before controller reset */ 978 status = azx_readw(chip, STATESTS); 979 980 azx_init_pci(chip); 981 hda_intel_init_chip(chip, true); 982 983 /* Avoid codec resume if runtime resume is for system suspend */ 984 if (!chip->pm_prepared) { 985 list_for_each_codec(codec, &chip->bus) { 986 if (codec->relaxed_resume) 987 continue; 988 989 if (codec->forced_resume || (status & (1 << codec->addr))) 990 pm_request_resume(hda_codec_dev(codec)); 991 } 992 } 993 994 /* power down again for link-controlled chips */ 995 if (!hda->need_i915_power) 996 display_power(chip, false); 997 } 998 999 static int azx_prepare(struct device *dev) 1000 { 1001 struct snd_card *card = dev_get_drvdata(dev); 1002 struct azx *chip; 1003 1004 if (!azx_is_pm_ready(card)) 1005 return 0; 1006 1007 chip = card->private_data; 1008 chip->pm_prepared = 1; 1009 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 1010 1011 flush_work(&azx_bus(chip)->unsol_work); 1012 1013 /* HDA controller always requires different WAKEEN for runtime suspend 1014 * and system suspend, so don't use direct-complete here. 1015 */ 1016 return 0; 1017 } 1018 1019 static void azx_complete(struct device *dev) 1020 { 1021 struct snd_card *card = dev_get_drvdata(dev); 1022 struct azx *chip; 1023 1024 if (!azx_is_pm_ready(card)) 1025 return; 1026 1027 chip = card->private_data; 1028 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 1029 chip->pm_prepared = 0; 1030 } 1031 1032 static int azx_suspend(struct device *dev) 1033 { 1034 struct snd_card *card = dev_get_drvdata(dev); 1035 struct azx *chip; 1036 struct hdac_bus *bus; 1037 1038 if (!azx_is_pm_ready(card)) 1039 return 0; 1040 1041 chip = card->private_data; 1042 bus = azx_bus(chip); 1043 azx_shutdown_chip(chip); 1044 if (bus->irq >= 0) { 1045 free_irq(bus->irq, chip); 1046 bus->irq = -1; 1047 chip->card->sync_irq = -1; 1048 } 1049 1050 if (chip->msi) 1051 pci_disable_msi(chip->pci); 1052 1053 trace_azx_suspend(chip); 1054 return 0; 1055 } 1056 1057 static int __maybe_unused azx_resume(struct device *dev) 1058 { 1059 struct snd_card *card = dev_get_drvdata(dev); 1060 struct azx *chip; 1061 1062 if (!azx_is_pm_ready(card)) 1063 return 0; 1064 1065 chip = card->private_data; 1066 if (chip->msi) 1067 if (pci_enable_msi(chip->pci) < 0) 1068 chip->msi = 0; 1069 if (azx_acquire_irq(chip, 1) < 0) 1070 return -EIO; 1071 1072 __azx_runtime_resume(chip); 1073 1074 trace_azx_resume(chip); 1075 return 0; 1076 } 1077 1078 /* put codec down to D3 at hibernation for Intel SKL+; 1079 * otherwise BIOS may still access the codec and screw up the driver 1080 */ 1081 static int azx_freeze_noirq(struct device *dev) 1082 { 1083 struct snd_card *card = dev_get_drvdata(dev); 1084 struct azx *chip = card->private_data; 1085 struct pci_dev *pci = to_pci_dev(dev); 1086 1087 if (!azx_is_pm_ready(card)) 1088 return 0; 1089 if (chip->driver_type == AZX_DRIVER_SKL) 1090 pci_set_power_state(pci, PCI_D3hot); 1091 1092 return 0; 1093 } 1094 1095 static int azx_thaw_noirq(struct device *dev) 1096 { 1097 struct snd_card *card = dev_get_drvdata(dev); 1098 struct azx *chip = card->private_data; 1099 struct pci_dev *pci = to_pci_dev(dev); 1100 1101 if (!azx_is_pm_ready(card)) 1102 return 0; 1103 if (chip->driver_type == AZX_DRIVER_SKL) 1104 pci_set_power_state(pci, PCI_D0); 1105 1106 return 0; 1107 } 1108 1109 static int __maybe_unused azx_runtime_suspend(struct device *dev) 1110 { 1111 struct snd_card *card = dev_get_drvdata(dev); 1112 struct azx *chip; 1113 1114 if (!azx_is_pm_ready(card)) 1115 return 0; 1116 chip = card->private_data; 1117 1118 /* enable controller wake up event */ 1119 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) | STATESTS_INT_MASK); 1120 1121 azx_shutdown_chip(chip); 1122 trace_azx_runtime_suspend(chip); 1123 return 0; 1124 } 1125 1126 static int __maybe_unused azx_runtime_resume(struct device *dev) 1127 { 1128 struct snd_card *card = dev_get_drvdata(dev); 1129 struct azx *chip; 1130 1131 if (!azx_is_pm_ready(card)) 1132 return 0; 1133 chip = card->private_data; 1134 __azx_runtime_resume(chip); 1135 1136 /* disable controller Wake Up event*/ 1137 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) & ~STATESTS_INT_MASK); 1138 1139 trace_azx_runtime_resume(chip); 1140 return 0; 1141 } 1142 1143 static int __maybe_unused azx_runtime_idle(struct device *dev) 1144 { 1145 struct snd_card *card = dev_get_drvdata(dev); 1146 struct azx *chip; 1147 struct hda_intel *hda; 1148 1149 if (!card) 1150 return 0; 1151 1152 chip = card->private_data; 1153 hda = container_of(chip, struct hda_intel, chip); 1154 if (chip->disabled || hda->init_failed) 1155 return 0; 1156 1157 if (!power_save_controller || !azx_has_pm_runtime(chip) || 1158 azx_bus(chip)->codec_powered || !chip->running) 1159 return -EBUSY; 1160 1161 /* ELD notification gets broken when HD-audio bus is off */ 1162 if (needs_eld_notify_link(chip)) 1163 return -EBUSY; 1164 1165 return 0; 1166 } 1167 1168 static const struct dev_pm_ops azx_pm = { 1169 SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume) 1170 .prepare = pm_sleep_ptr(azx_prepare), 1171 .complete = pm_sleep_ptr(azx_complete), 1172 .freeze_noirq = pm_sleep_ptr(azx_freeze_noirq), 1173 .thaw_noirq = pm_sleep_ptr(azx_thaw_noirq), 1174 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle) 1175 }; 1176 1177 1178 static int azx_probe_continue(struct azx *chip); 1179 1180 #ifdef SUPPORT_VGA_SWITCHEROO 1181 static struct pci_dev *get_bound_vga(struct pci_dev *pci); 1182 1183 static void azx_vs_set_state(struct pci_dev *pci, 1184 enum vga_switcheroo_state state) 1185 { 1186 struct snd_card *card = pci_get_drvdata(pci); 1187 struct azx *chip = card->private_data; 1188 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1189 struct hda_codec *codec; 1190 bool disabled; 1191 1192 wait_for_completion(&hda->probe_wait); 1193 if (hda->init_failed) 1194 return; 1195 1196 disabled = (state == VGA_SWITCHEROO_OFF); 1197 if (chip->disabled == disabled) 1198 return; 1199 1200 if (!hda->probe_continued) { 1201 chip->disabled = disabled; 1202 if (!disabled) { 1203 dev_info(chip->card->dev, 1204 "Start delayed initialization\n"); 1205 if (azx_probe_continue(chip) < 0) 1206 dev_err(chip->card->dev, "initialization error\n"); 1207 } 1208 } else { 1209 dev_info(chip->card->dev, "%s via vga_switcheroo\n", 1210 disabled ? "Disabling" : "Enabling"); 1211 if (disabled) { 1212 list_for_each_codec(codec, &chip->bus) { 1213 pm_runtime_suspend(hda_codec_dev(codec)); 1214 pm_runtime_disable(hda_codec_dev(codec)); 1215 } 1216 pm_runtime_suspend(card->dev); 1217 pm_runtime_disable(card->dev); 1218 /* when we get suspended by vga_switcheroo we end up in D3cold, 1219 * however we have no ACPI handle, so pci/acpi can't put us there, 1220 * put ourselves there */ 1221 pci->current_state = PCI_D3cold; 1222 chip->disabled = true; 1223 if (snd_hda_lock_devices(&chip->bus)) 1224 dev_warn(chip->card->dev, 1225 "Cannot lock devices!\n"); 1226 } else { 1227 snd_hda_unlock_devices(&chip->bus); 1228 chip->disabled = false; 1229 pm_runtime_enable(card->dev); 1230 list_for_each_codec(codec, &chip->bus) { 1231 pm_runtime_enable(hda_codec_dev(codec)); 1232 pm_runtime_resume(hda_codec_dev(codec)); 1233 } 1234 } 1235 } 1236 } 1237 1238 static bool azx_vs_can_switch(struct pci_dev *pci) 1239 { 1240 struct snd_card *card = pci_get_drvdata(pci); 1241 struct azx *chip = card->private_data; 1242 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1243 1244 wait_for_completion(&hda->probe_wait); 1245 if (hda->init_failed) 1246 return false; 1247 if (chip->disabled || !hda->probe_continued) 1248 return true; 1249 if (snd_hda_lock_devices(&chip->bus)) 1250 return false; 1251 snd_hda_unlock_devices(&chip->bus); 1252 return true; 1253 } 1254 1255 /* 1256 * The discrete GPU cannot power down unless the HDA controller runtime 1257 * suspends, so activate runtime PM on codecs even if power_save == 0. 1258 */ 1259 static void setup_vga_switcheroo_runtime_pm(struct azx *chip) 1260 { 1261 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1262 struct hda_codec *codec; 1263 1264 if (hda->use_vga_switcheroo && !needs_eld_notify_link(chip)) { 1265 list_for_each_codec(codec, &chip->bus) 1266 codec->auto_runtime_pm = 1; 1267 /* reset the power save setup */ 1268 if (chip->running) 1269 set_default_power_save(chip); 1270 } 1271 } 1272 1273 static void azx_vs_gpu_bound(struct pci_dev *pci, 1274 enum vga_switcheroo_client_id client_id) 1275 { 1276 struct snd_card *card = pci_get_drvdata(pci); 1277 struct azx *chip = card->private_data; 1278 1279 if (client_id == VGA_SWITCHEROO_DIS) 1280 chip->bus.keep_power = 0; 1281 setup_vga_switcheroo_runtime_pm(chip); 1282 } 1283 1284 static void init_vga_switcheroo(struct azx *chip) 1285 { 1286 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1287 struct pci_dev *p = get_bound_vga(chip->pci); 1288 struct pci_dev *parent; 1289 if (p) { 1290 dev_info(chip->card->dev, 1291 "Handle vga_switcheroo audio client\n"); 1292 hda->use_vga_switcheroo = 1; 1293 1294 /* cleared in either gpu_bound op or codec probe, or when its 1295 * upstream port has _PR3 (i.e. dGPU). 1296 */ 1297 parent = pci_upstream_bridge(p); 1298 chip->bus.keep_power = parent ? !pci_pr3_present(parent) : 1; 1299 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME; 1300 pci_dev_put(p); 1301 } 1302 } 1303 1304 static const struct vga_switcheroo_client_ops azx_vs_ops = { 1305 .set_gpu_state = azx_vs_set_state, 1306 .can_switch = azx_vs_can_switch, 1307 .gpu_bound = azx_vs_gpu_bound, 1308 }; 1309 1310 static int register_vga_switcheroo(struct azx *chip) 1311 { 1312 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1313 struct pci_dev *p; 1314 int err; 1315 1316 if (!hda->use_vga_switcheroo) 1317 return 0; 1318 1319 p = get_bound_vga(chip->pci); 1320 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p); 1321 pci_dev_put(p); 1322 1323 if (err < 0) 1324 return err; 1325 hda->vga_switcheroo_registered = 1; 1326 1327 return 0; 1328 } 1329 #else 1330 #define init_vga_switcheroo(chip) /* NOP */ 1331 #define register_vga_switcheroo(chip) 0 1332 #define check_hdmi_disabled(pci) false 1333 #define setup_vga_switcheroo_runtime_pm(chip) /* NOP */ 1334 #endif /* SUPPORT_VGA_SWITCHER */ 1335 1336 /* 1337 * destructor 1338 */ 1339 static void azx_free(struct azx *chip) 1340 { 1341 struct pci_dev *pci = chip->pci; 1342 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1343 struct hdac_bus *bus = azx_bus(chip); 1344 1345 if (hda->freed) 1346 return; 1347 1348 if (azx_has_pm_runtime(chip) && chip->running) { 1349 pm_runtime_get_noresume(&pci->dev); 1350 pm_runtime_forbid(&pci->dev); 1351 pm_runtime_dont_use_autosuspend(&pci->dev); 1352 } 1353 1354 chip->running = 0; 1355 1356 azx_del_card_list(chip); 1357 1358 hda->init_failed = 1; /* to be sure */ 1359 complete_all(&hda->probe_wait); 1360 1361 if (use_vga_switcheroo(hda)) { 1362 if (chip->disabled && hda->probe_continued) 1363 snd_hda_unlock_devices(&chip->bus); 1364 if (hda->vga_switcheroo_registered) 1365 vga_switcheroo_unregister_client(chip->pci); 1366 } 1367 1368 if (bus->chip_init) { 1369 azx_clear_irq_pending(chip); 1370 azx_stop_all_streams(chip); 1371 azx_stop_chip(chip); 1372 } 1373 1374 if (bus->irq >= 0) 1375 free_irq(bus->irq, (void*)chip); 1376 1377 azx_free_stream_pages(chip); 1378 azx_free_streams(chip); 1379 snd_hdac_bus_exit(bus); 1380 1381 #ifdef CONFIG_SND_HDA_PATCH_LOADER 1382 release_firmware(chip->fw); 1383 #endif 1384 display_power(chip, false); 1385 1386 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) 1387 snd_hdac_i915_exit(bus); 1388 1389 hda->freed = 1; 1390 } 1391 1392 static int azx_dev_disconnect(struct snd_device *device) 1393 { 1394 struct azx *chip = device->device_data; 1395 struct hdac_bus *bus = azx_bus(chip); 1396 1397 chip->bus.shutdown = 1; 1398 cancel_work_sync(&bus->unsol_work); 1399 1400 return 0; 1401 } 1402 1403 static int azx_dev_free(struct snd_device *device) 1404 { 1405 azx_free(device->device_data); 1406 return 0; 1407 } 1408 1409 #ifdef SUPPORT_VGA_SWITCHEROO 1410 #ifdef CONFIG_ACPI 1411 /* ATPX is in the integrated GPU's namespace */ 1412 static bool atpx_present(void) 1413 { 1414 struct pci_dev *pdev = NULL; 1415 acpi_handle dhandle, atpx_handle; 1416 acpi_status status; 1417 1418 while ((pdev = pci_get_base_class(PCI_BASE_CLASS_DISPLAY, pdev))) { 1419 if ((pdev->class != PCI_CLASS_DISPLAY_VGA << 8) && 1420 (pdev->class != PCI_CLASS_DISPLAY_OTHER << 8)) 1421 continue; 1422 1423 dhandle = ACPI_HANDLE(&pdev->dev); 1424 if (dhandle) { 1425 status = acpi_get_handle(dhandle, "ATPX", &atpx_handle); 1426 if (ACPI_SUCCESS(status)) { 1427 pci_dev_put(pdev); 1428 return true; 1429 } 1430 } 1431 } 1432 return false; 1433 } 1434 #else 1435 static bool atpx_present(void) 1436 { 1437 return false; 1438 } 1439 #endif 1440 1441 /* 1442 * Check of disabled HDMI controller by vga_switcheroo 1443 */ 1444 static struct pci_dev *get_bound_vga(struct pci_dev *pci) 1445 { 1446 struct pci_dev *p; 1447 1448 /* check only discrete GPU */ 1449 switch (pci->vendor) { 1450 case PCI_VENDOR_ID_ATI: 1451 case PCI_VENDOR_ID_AMD: 1452 if (pci->devfn == 1) { 1453 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus), 1454 pci->bus->number, 0); 1455 if (p) { 1456 /* ATPX is in the integrated GPU's ACPI namespace 1457 * rather than the dGPU's namespace. However, 1458 * the dGPU is the one who is involved in 1459 * vgaswitcheroo. 1460 */ 1461 if (((p->class >> 16) == PCI_BASE_CLASS_DISPLAY) && 1462 (atpx_present() || apple_gmux_detect(NULL, NULL))) 1463 return p; 1464 pci_dev_put(p); 1465 } 1466 } 1467 break; 1468 case PCI_VENDOR_ID_NVIDIA: 1469 if (pci->devfn == 1) { 1470 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus), 1471 pci->bus->number, 0); 1472 if (p) { 1473 if ((p->class >> 16) == PCI_BASE_CLASS_DISPLAY) 1474 return p; 1475 pci_dev_put(p); 1476 } 1477 } 1478 break; 1479 } 1480 return NULL; 1481 } 1482 1483 static bool check_hdmi_disabled(struct pci_dev *pci) 1484 { 1485 bool vga_inactive = false; 1486 struct pci_dev *p = get_bound_vga(pci); 1487 1488 if (p) { 1489 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF) 1490 vga_inactive = true; 1491 pci_dev_put(p); 1492 } 1493 return vga_inactive; 1494 } 1495 #endif /* SUPPORT_VGA_SWITCHEROO */ 1496 1497 /* 1498 * allow/deny-listing for position_fix 1499 */ 1500 static const struct snd_pci_quirk position_fix_list[] = { 1501 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB), 1502 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB), 1503 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB), 1504 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB), 1505 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB), 1506 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB), 1507 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB), 1508 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB), 1509 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB), 1510 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB), 1511 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB), 1512 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB), 1513 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB), 1514 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB), 1515 {} 1516 }; 1517 1518 static int check_position_fix(struct azx *chip, int fix) 1519 { 1520 const struct snd_pci_quirk *q; 1521 1522 switch (fix) { 1523 case POS_FIX_AUTO: 1524 case POS_FIX_LPIB: 1525 case POS_FIX_POSBUF: 1526 case POS_FIX_VIACOMBO: 1527 case POS_FIX_COMBO: 1528 case POS_FIX_SKL: 1529 case POS_FIX_FIFO: 1530 return fix; 1531 } 1532 1533 q = snd_pci_quirk_lookup(chip->pci, position_fix_list); 1534 if (q) { 1535 dev_info(chip->card->dev, 1536 "position_fix set to %d for device %04x:%04x\n", 1537 q->value, q->subvendor, q->subdevice); 1538 return q->value; 1539 } 1540 1541 /* Check VIA/ATI HD Audio Controller exist */ 1542 if (chip->driver_type == AZX_DRIVER_VIA) { 1543 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n"); 1544 return POS_FIX_VIACOMBO; 1545 } 1546 if (chip->driver_caps & AZX_DCAPS_AMD_WORKAROUND) { 1547 dev_dbg(chip->card->dev, "Using FIFO position fix\n"); 1548 return POS_FIX_FIFO; 1549 } 1550 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) { 1551 dev_dbg(chip->card->dev, "Using LPIB position fix\n"); 1552 return POS_FIX_LPIB; 1553 } 1554 if (chip->driver_type == AZX_DRIVER_SKL) { 1555 dev_dbg(chip->card->dev, "Using SKL position fix\n"); 1556 return POS_FIX_SKL; 1557 } 1558 return POS_FIX_AUTO; 1559 } 1560 1561 static void assign_position_fix(struct azx *chip, int fix) 1562 { 1563 static const azx_get_pos_callback_t callbacks[] = { 1564 [POS_FIX_AUTO] = NULL, 1565 [POS_FIX_LPIB] = azx_get_pos_lpib, 1566 [POS_FIX_POSBUF] = azx_get_pos_posbuf, 1567 [POS_FIX_VIACOMBO] = azx_via_get_position, 1568 [POS_FIX_COMBO] = azx_get_pos_lpib, 1569 [POS_FIX_SKL] = azx_get_pos_posbuf, 1570 [POS_FIX_FIFO] = azx_get_pos_fifo, 1571 }; 1572 1573 chip->get_position[0] = chip->get_position[1] = callbacks[fix]; 1574 1575 /* combo mode uses LPIB only for playback */ 1576 if (fix == POS_FIX_COMBO) 1577 chip->get_position[1] = NULL; 1578 1579 if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) && 1580 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) { 1581 chip->get_delay[0] = chip->get_delay[1] = 1582 azx_get_delay_from_lpib; 1583 } 1584 1585 if (fix == POS_FIX_FIFO) 1586 chip->get_delay[0] = chip->get_delay[1] = 1587 azx_get_delay_from_fifo; 1588 } 1589 1590 /* 1591 * deny-lists for probe_mask 1592 */ 1593 static const struct snd_pci_quirk probe_mask_list[] = { 1594 /* Thinkpad often breaks the controller communication when accessing 1595 * to the non-working (or non-existing) modem codec slot. 1596 */ 1597 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01), 1598 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01), 1599 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01), 1600 /* broken BIOS */ 1601 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01), 1602 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */ 1603 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01), 1604 /* forced codec slots */ 1605 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103), 1606 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103), 1607 SND_PCI_QUIRK(0x1558, 0x0351, "Schenker Dock 15", 0x105), 1608 /* WinFast VP200 H (Teradici) user reported broken communication */ 1609 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101), 1610 {} 1611 }; 1612 1613 #define AZX_FORCE_CODEC_MASK 0x100 1614 1615 static void check_probe_mask(struct azx *chip, int dev) 1616 { 1617 const struct snd_pci_quirk *q; 1618 1619 chip->codec_probe_mask = probe_mask[dev]; 1620 if (chip->codec_probe_mask == -1) { 1621 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list); 1622 if (q) { 1623 dev_info(chip->card->dev, 1624 "probe_mask set to 0x%x for device %04x:%04x\n", 1625 q->value, q->subvendor, q->subdevice); 1626 chip->codec_probe_mask = q->value; 1627 } 1628 } 1629 1630 /* check forced option */ 1631 if (chip->codec_probe_mask != -1 && 1632 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) { 1633 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff; 1634 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n", 1635 (int)azx_bus(chip)->codec_mask); 1636 } 1637 } 1638 1639 /* 1640 * allow/deny-list for enable_msi 1641 */ 1642 static const struct snd_pci_quirk msi_deny_list[] = { 1643 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */ 1644 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */ 1645 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */ 1646 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */ 1647 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */ 1648 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */ 1649 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */ 1650 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */ 1651 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */ 1652 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */ 1653 {} 1654 }; 1655 1656 static void check_msi(struct azx *chip) 1657 { 1658 const struct snd_pci_quirk *q; 1659 1660 if (enable_msi >= 0) { 1661 chip->msi = !!enable_msi; 1662 return; 1663 } 1664 chip->msi = 1; /* enable MSI as default */ 1665 q = snd_pci_quirk_lookup(chip->pci, msi_deny_list); 1666 if (q) { 1667 dev_info(chip->card->dev, 1668 "msi for device %04x:%04x set to %d\n", 1669 q->subvendor, q->subdevice, q->value); 1670 chip->msi = q->value; 1671 return; 1672 } 1673 1674 /* NVidia chipsets seem to cause troubles with MSI */ 1675 if (chip->driver_caps & AZX_DCAPS_NO_MSI) { 1676 dev_info(chip->card->dev, "Disabling MSI\n"); 1677 chip->msi = 0; 1678 } 1679 } 1680 1681 /* check the snoop mode availability */ 1682 static void azx_check_snoop_available(struct azx *chip) 1683 { 1684 int snoop = hda_snoop; 1685 1686 if (snoop >= 0) { 1687 dev_info(chip->card->dev, "Force to %s mode by module option\n", 1688 snoop ? "snoop" : "non-snoop"); 1689 chip->snoop = snoop; 1690 chip->uc_buffer = !snoop; 1691 return; 1692 } 1693 1694 snoop = true; 1695 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE && 1696 chip->driver_type == AZX_DRIVER_VIA) { 1697 /* force to non-snoop mode for a new VIA controller 1698 * when BIOS is set 1699 */ 1700 u8 val; 1701 pci_read_config_byte(chip->pci, 0x42, &val); 1702 if (!(val & 0x80) && (chip->pci->revision == 0x30 || 1703 chip->pci->revision == 0x20)) 1704 snoop = false; 1705 } 1706 1707 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF) 1708 snoop = false; 1709 1710 #ifdef CONFIG_X86 1711 /* check the presence of DMA ops (i.e. IOMMU), disable snoop conditionally */ 1712 if ((chip->driver_caps & AZX_DCAPS_AMD_ALLOC_FIX) && 1713 !get_dma_ops(chip->card->dev)) 1714 snoop = false; 1715 #endif 1716 1717 chip->snoop = snoop; 1718 if (!snoop) { 1719 dev_info(chip->card->dev, "Force to non-snoop mode\n"); 1720 /* C-Media requires non-cached pages only for CORB/RIRB */ 1721 if (chip->driver_type != AZX_DRIVER_CMEDIA) 1722 chip->uc_buffer = true; 1723 } 1724 } 1725 1726 static void azx_probe_work(struct work_struct *work) 1727 { 1728 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work.work); 1729 azx_probe_continue(&hda->chip); 1730 } 1731 1732 static int default_bdl_pos_adj(struct azx *chip) 1733 { 1734 /* some exceptions: Atoms seem problematic with value 1 */ 1735 if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) { 1736 switch (chip->pci->device) { 1737 case PCI_DEVICE_ID_INTEL_HDA_BYT: 1738 case PCI_DEVICE_ID_INTEL_HDA_BSW: 1739 return 32; 1740 case PCI_DEVICE_ID_INTEL_HDA_APL: 1741 return 64; 1742 } 1743 } 1744 1745 switch (chip->driver_type) { 1746 /* 1747 * increase the bdl size for Glenfly Gpus for hardware 1748 * limitation on hdac interrupt interval 1749 */ 1750 case AZX_DRIVER_GFHDMI: 1751 return 128; 1752 case AZX_DRIVER_ICH: 1753 case AZX_DRIVER_PCH: 1754 return 1; 1755 default: 1756 return 32; 1757 } 1758 } 1759 1760 /* 1761 * constructor 1762 */ 1763 static const struct hda_controller_ops pci_hda_ops; 1764 1765 static int azx_create(struct snd_card *card, struct pci_dev *pci, 1766 int dev, unsigned int driver_caps, 1767 struct azx **rchip) 1768 { 1769 static const struct snd_device_ops ops = { 1770 .dev_disconnect = azx_dev_disconnect, 1771 .dev_free = azx_dev_free, 1772 }; 1773 struct hda_intel *hda; 1774 struct azx *chip; 1775 int err; 1776 1777 *rchip = NULL; 1778 1779 err = pcim_enable_device(pci); 1780 if (err < 0) 1781 return err; 1782 1783 hda = devm_kzalloc(&pci->dev, sizeof(*hda), GFP_KERNEL); 1784 if (!hda) 1785 return -ENOMEM; 1786 1787 chip = &hda->chip; 1788 mutex_init(&chip->open_mutex); 1789 chip->card = card; 1790 chip->pci = pci; 1791 chip->ops = &pci_hda_ops; 1792 chip->driver_caps = driver_caps; 1793 chip->driver_type = driver_caps & 0xff; 1794 check_msi(chip); 1795 chip->dev_index = dev; 1796 if (jackpoll_ms[dev] >= 50 && jackpoll_ms[dev] <= 60000) 1797 chip->jackpoll_interval = msecs_to_jiffies(jackpoll_ms[dev]); 1798 INIT_LIST_HEAD(&chip->pcm_list); 1799 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work); 1800 INIT_LIST_HEAD(&hda->list); 1801 init_vga_switcheroo(chip); 1802 init_completion(&hda->probe_wait); 1803 1804 assign_position_fix(chip, check_position_fix(chip, position_fix[dev])); 1805 1806 if (single_cmd < 0) /* allow fallback to single_cmd at errors */ 1807 chip->fallback_to_single_cmd = 1; 1808 else /* explicitly set to single_cmd or not */ 1809 chip->single_cmd = single_cmd; 1810 1811 azx_check_snoop_available(chip); 1812 1813 if (bdl_pos_adj[dev] < 0) 1814 chip->bdl_pos_adj = default_bdl_pos_adj(chip); 1815 else 1816 chip->bdl_pos_adj = bdl_pos_adj[dev]; 1817 1818 err = azx_bus_init(chip, model[dev]); 1819 if (err < 0) 1820 return err; 1821 1822 /* use the non-cached pages in non-snoop mode */ 1823 if (!azx_snoop(chip)) 1824 azx_bus(chip)->dma_type = SNDRV_DMA_TYPE_DEV_WC; 1825 1826 if (chip->driver_type == AZX_DRIVER_NVIDIA) { 1827 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n"); 1828 chip->bus.core.needs_damn_long_delay = 1; 1829 } 1830 1831 check_probe_mask(chip, dev); 1832 1833 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); 1834 if (err < 0) { 1835 dev_err(card->dev, "Error creating device [card]!\n"); 1836 azx_free(chip); 1837 return err; 1838 } 1839 1840 /* continue probing in work context as may trigger request module */ 1841 INIT_DELAYED_WORK(&hda->probe_work, azx_probe_work); 1842 1843 *rchip = chip; 1844 1845 return 0; 1846 } 1847 1848 static int azx_first_init(struct azx *chip) 1849 { 1850 int dev = chip->dev_index; 1851 struct pci_dev *pci = chip->pci; 1852 struct snd_card *card = chip->card; 1853 struct hdac_bus *bus = azx_bus(chip); 1854 int err; 1855 unsigned short gcap; 1856 unsigned int dma_bits = 64; 1857 1858 #if BITS_PER_LONG != 64 1859 /* Fix up base address on ULI M5461 */ 1860 if (chip->driver_type == AZX_DRIVER_ULI) { 1861 u16 tmp3; 1862 pci_read_config_word(pci, 0x40, &tmp3); 1863 pci_write_config_word(pci, 0x40, tmp3 | 0x10); 1864 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0); 1865 } 1866 #endif 1867 /* 1868 * Fix response write request not synced to memory when handle 1869 * hdac interrupt on Glenfly Gpus 1870 */ 1871 if (chip->driver_type == AZX_DRIVER_GFHDMI) 1872 bus->polling_mode = 1; 1873 1874 if (chip->driver_type == AZX_DRIVER_LOONGSON) { 1875 bus->polling_mode = 1; 1876 bus->not_use_interrupts = 1; 1877 bus->access_sdnctl_in_dword = 1; 1878 } 1879 1880 err = pcim_iomap_regions(pci, 1 << 0, "ICH HD audio"); 1881 if (err < 0) 1882 return err; 1883 1884 bus->addr = pci_resource_start(pci, 0); 1885 bus->remap_addr = pcim_iomap_table(pci)[0]; 1886 1887 if (chip->driver_type == AZX_DRIVER_SKL) 1888 snd_hdac_bus_parse_capabilities(bus); 1889 1890 /* 1891 * Some Intel CPUs has always running timer (ART) feature and 1892 * controller may have Global time sync reporting capability, so 1893 * check both of these before declaring synchronized time reporting 1894 * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME 1895 */ 1896 chip->gts_present = false; 1897 1898 #ifdef CONFIG_X86 1899 if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART)) 1900 chip->gts_present = true; 1901 #endif 1902 1903 if (chip->msi) { 1904 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) { 1905 dev_dbg(card->dev, "Disabling 64bit MSI\n"); 1906 pci->no_64bit_msi = true; 1907 } 1908 if (pci_enable_msi(pci) < 0) 1909 chip->msi = 0; 1910 } 1911 1912 pci_set_master(pci); 1913 1914 gcap = azx_readw(chip, GCAP); 1915 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap); 1916 1917 /* AMD devices support 40 or 48bit DMA, take the safe one */ 1918 if (chip->pci->vendor == PCI_VENDOR_ID_AMD) 1919 dma_bits = 40; 1920 1921 /* disable SB600 64bit support for safety */ 1922 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) { 1923 struct pci_dev *p_smbus; 1924 dma_bits = 40; 1925 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI, 1926 PCI_DEVICE_ID_ATI_SBX00_SMBUS, 1927 NULL); 1928 if (p_smbus) { 1929 if (p_smbus->revision < 0x30) 1930 gcap &= ~AZX_GCAP_64OK; 1931 pci_dev_put(p_smbus); 1932 } 1933 } 1934 1935 /* NVidia hardware normally only supports up to 40 bits of DMA */ 1936 if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA) 1937 dma_bits = 40; 1938 1939 /* disable 64bit DMA address on some devices */ 1940 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) { 1941 dev_dbg(card->dev, "Disabling 64bit DMA\n"); 1942 gcap &= ~AZX_GCAP_64OK; 1943 } 1944 1945 /* disable buffer size rounding to 128-byte multiples if supported */ 1946 if (align_buffer_size >= 0) 1947 chip->align_buffer_size = !!align_buffer_size; 1948 else { 1949 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE) 1950 chip->align_buffer_size = 0; 1951 else 1952 chip->align_buffer_size = 1; 1953 } 1954 1955 /* allow 64bit DMA address if supported by H/W */ 1956 if (!(gcap & AZX_GCAP_64OK)) 1957 dma_bits = 32; 1958 if (dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(dma_bits))) 1959 dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(32)); 1960 dma_set_max_seg_size(&pci->dev, UINT_MAX); 1961 1962 /* read number of streams from GCAP register instead of using 1963 * hardcoded value 1964 */ 1965 chip->capture_streams = (gcap >> 8) & 0x0f; 1966 chip->playback_streams = (gcap >> 12) & 0x0f; 1967 if (!chip->playback_streams && !chip->capture_streams) { 1968 /* gcap didn't give any info, switching to old method */ 1969 1970 switch (chip->driver_type) { 1971 case AZX_DRIVER_ULI: 1972 chip->playback_streams = ULI_NUM_PLAYBACK; 1973 chip->capture_streams = ULI_NUM_CAPTURE; 1974 break; 1975 case AZX_DRIVER_ATIHDMI: 1976 case AZX_DRIVER_ATIHDMI_NS: 1977 chip->playback_streams = ATIHDMI_NUM_PLAYBACK; 1978 chip->capture_streams = ATIHDMI_NUM_CAPTURE; 1979 break; 1980 case AZX_DRIVER_GFHDMI: 1981 case AZX_DRIVER_GENERIC: 1982 default: 1983 chip->playback_streams = ICH6_NUM_PLAYBACK; 1984 chip->capture_streams = ICH6_NUM_CAPTURE; 1985 break; 1986 } 1987 } 1988 chip->capture_index_offset = 0; 1989 chip->playback_index_offset = chip->capture_streams; 1990 chip->num_streams = chip->playback_streams + chip->capture_streams; 1991 1992 /* sanity check for the SDxCTL.STRM field overflow */ 1993 if (chip->num_streams > 15 && 1994 (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) { 1995 dev_warn(chip->card->dev, "number of I/O streams is %d, " 1996 "forcing separate stream tags", chip->num_streams); 1997 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG; 1998 } 1999 2000 /* initialize streams */ 2001 err = azx_init_streams(chip); 2002 if (err < 0) 2003 return err; 2004 2005 err = azx_alloc_stream_pages(chip); 2006 if (err < 0) 2007 return err; 2008 2009 /* initialize chip */ 2010 azx_init_pci(chip); 2011 2012 snd_hdac_i915_set_bclk(bus); 2013 2014 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0); 2015 2016 /* codec detection */ 2017 if (!azx_bus(chip)->codec_mask) { 2018 dev_err(card->dev, "no codecs found!\n"); 2019 /* keep running the rest for the runtime PM */ 2020 } 2021 2022 if (azx_acquire_irq(chip, 0) < 0) 2023 return -EBUSY; 2024 2025 strcpy(card->driver, "HDA-Intel"); 2026 strscpy(card->shortname, driver_short_names[chip->driver_type], 2027 sizeof(card->shortname)); 2028 snprintf(card->longname, sizeof(card->longname), 2029 "%s at 0x%lx irq %i", 2030 card->shortname, bus->addr, bus->irq); 2031 2032 return 0; 2033 } 2034 2035 #ifdef CONFIG_SND_HDA_PATCH_LOADER 2036 /* callback from request_firmware_nowait() */ 2037 static void azx_firmware_cb(const struct firmware *fw, void *context) 2038 { 2039 struct snd_card *card = context; 2040 struct azx *chip = card->private_data; 2041 2042 if (fw) 2043 chip->fw = fw; 2044 else 2045 dev_err(card->dev, "Cannot load firmware, continue without patching\n"); 2046 if (!chip->disabled) { 2047 /* continue probing */ 2048 azx_probe_continue(chip); 2049 } 2050 } 2051 #endif 2052 2053 static int disable_msi_reset_irq(struct azx *chip) 2054 { 2055 struct hdac_bus *bus = azx_bus(chip); 2056 int err; 2057 2058 free_irq(bus->irq, chip); 2059 bus->irq = -1; 2060 chip->card->sync_irq = -1; 2061 pci_disable_msi(chip->pci); 2062 chip->msi = 0; 2063 err = azx_acquire_irq(chip, 1); 2064 if (err < 0) 2065 return err; 2066 2067 return 0; 2068 } 2069 2070 /* Denylist for skipping the whole probe: 2071 * some HD-audio PCI entries are exposed without any codecs, and such devices 2072 * should be ignored from the beginning. 2073 */ 2074 static const struct pci_device_id driver_denylist[] = { 2075 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1043, 0x874f) }, /* ASUS ROG Zenith II / Strix */ 2076 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb59) }, /* MSI TRX40 Creator */ 2077 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb60) }, /* MSI TRX40 */ 2078 { PCI_DEVICE_SUB(0x1022, 0x15e3, 0x1022, 0xd601) }, /* ASRock X670E Taichi */ 2079 {} 2080 }; 2081 2082 static const struct hda_controller_ops pci_hda_ops = { 2083 .disable_msi_reset_irq = disable_msi_reset_irq, 2084 .position_check = azx_position_check, 2085 }; 2086 2087 static DECLARE_BITMAP(probed_devs, SNDRV_CARDS); 2088 2089 static int azx_probe(struct pci_dev *pci, 2090 const struct pci_device_id *pci_id) 2091 { 2092 struct snd_card *card; 2093 struct hda_intel *hda; 2094 struct azx *chip; 2095 bool schedule_probe; 2096 int dev; 2097 int err; 2098 2099 if (pci_match_id(driver_denylist, pci)) { 2100 dev_info(&pci->dev, "Skipping the device on the denylist\n"); 2101 return -ENODEV; 2102 } 2103 2104 dev = find_first_zero_bit(probed_devs, SNDRV_CARDS); 2105 if (dev >= SNDRV_CARDS) 2106 return -ENODEV; 2107 if (!enable[dev]) { 2108 set_bit(dev, probed_devs); 2109 return -ENOENT; 2110 } 2111 2112 /* 2113 * stop probe if another Intel's DSP driver should be activated 2114 */ 2115 if (dmic_detect) { 2116 err = snd_intel_dsp_driver_probe(pci); 2117 if (err != SND_INTEL_DSP_DRIVER_ANY && err != SND_INTEL_DSP_DRIVER_LEGACY) { 2118 dev_dbg(&pci->dev, "HDAudio driver not selected, aborting probe\n"); 2119 return -ENODEV; 2120 } 2121 } else { 2122 dev_warn(&pci->dev, "dmic_detect option is deprecated, pass snd-intel-dspcfg.dsp_driver=1 option instead\n"); 2123 } 2124 2125 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE, 2126 0, &card); 2127 if (err < 0) { 2128 dev_err(&pci->dev, "Error creating card!\n"); 2129 return err; 2130 } 2131 2132 err = azx_create(card, pci, dev, pci_id->driver_data, &chip); 2133 if (err < 0) 2134 goto out_free; 2135 card->private_data = chip; 2136 hda = container_of(chip, struct hda_intel, chip); 2137 2138 pci_set_drvdata(pci, card); 2139 2140 #ifdef CONFIG_SND_HDA_I915 2141 /* bind with i915 if needed */ 2142 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) { 2143 err = snd_hdac_i915_init(azx_bus(chip)); 2144 if (err < 0) { 2145 if (err == -EPROBE_DEFER) 2146 goto out_free; 2147 2148 /* if the controller is bound only with HDMI/DP 2149 * (for HSW and BDW), we need to abort the probe; 2150 * for other chips, still continue probing as other 2151 * codecs can be on the same link. 2152 */ 2153 if (HDA_CONTROLLER_IN_GPU(pci)) { 2154 dev_err_probe(card->dev, err, 2155 "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n"); 2156 2157 goto out_free; 2158 } else { 2159 /* don't bother any longer */ 2160 chip->driver_caps &= ~AZX_DCAPS_I915_COMPONENT; 2161 } 2162 } 2163 2164 /* HSW/BDW controllers need this power */ 2165 if (HDA_CONTROLLER_IN_GPU(pci)) 2166 hda->need_i915_power = true; 2167 } 2168 #else 2169 if (HDA_CONTROLLER_IN_GPU(pci)) 2170 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n"); 2171 #endif 2172 2173 err = register_vga_switcheroo(chip); 2174 if (err < 0) { 2175 dev_err(card->dev, "Error registering vga_switcheroo client\n"); 2176 goto out_free; 2177 } 2178 2179 if (check_hdmi_disabled(pci)) { 2180 dev_info(card->dev, "VGA controller is disabled\n"); 2181 dev_info(card->dev, "Delaying initialization\n"); 2182 chip->disabled = true; 2183 } 2184 2185 schedule_probe = !chip->disabled; 2186 2187 #ifdef CONFIG_SND_HDA_PATCH_LOADER 2188 if (patch[dev] && *patch[dev]) { 2189 dev_info(card->dev, "Applying patch firmware '%s'\n", 2190 patch[dev]); 2191 err = request_firmware_nowait(THIS_MODULE, true, patch[dev], 2192 &pci->dev, GFP_KERNEL, card, 2193 azx_firmware_cb); 2194 if (err < 0) 2195 goto out_free; 2196 schedule_probe = false; /* continued in azx_firmware_cb() */ 2197 } 2198 #endif /* CONFIG_SND_HDA_PATCH_LOADER */ 2199 2200 if (schedule_probe) 2201 schedule_delayed_work(&hda->probe_work, 0); 2202 2203 set_bit(dev, probed_devs); 2204 if (chip->disabled) 2205 complete_all(&hda->probe_wait); 2206 return 0; 2207 2208 out_free: 2209 pci_set_drvdata(pci, NULL); 2210 snd_card_free(card); 2211 return err; 2212 } 2213 2214 /* On some boards setting power_save to a non 0 value leads to clicking / 2215 * popping sounds when ever we enter/leave powersaving mode. Ideally we would 2216 * figure out how to avoid these sounds, but that is not always feasible. 2217 * So we keep a list of devices where we disable powersaving as its known 2218 * to causes problems on these devices. 2219 */ 2220 static const struct snd_pci_quirk power_save_denylist[] = { 2221 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2222 SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0), 2223 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2224 SND_PCI_QUIRK(0x1849, 0x0397, "Asrock N68C-S UCC", 0), 2225 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2226 SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0), 2227 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2228 SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0), 2229 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2230 SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0), 2231 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2232 /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */ 2233 SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0), 2234 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2235 SND_PCI_QUIRK(0x8086, 0x2040, "Intel DZ77BH-55K", 0), 2236 /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */ 2237 SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0), 2238 /* https://bugs.launchpad.net/bugs/1821663 */ 2239 SND_PCI_QUIRK(0x8086, 0x2064, "Intel SDP 8086:2064", 0), 2240 /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */ 2241 SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0), 2242 /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */ 2243 SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0), 2244 SND_PCI_QUIRK(0x17aa, 0x316e, "Lenovo ThinkCentre M70q", 0), 2245 /* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */ 2246 SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0), 2247 /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */ 2248 SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0), 2249 /* https://bugs.launchpad.net/bugs/1821663 */ 2250 SND_PCI_QUIRK(0x1631, 0xe017, "Packard Bell NEC IMEDIA 5204", 0), 2251 /* KONTRON SinglePC may cause a stall at runtime resume */ 2252 SND_PCI_QUIRK(0x1734, 0x1232, "KONTRON SinglePC", 0), 2253 {} 2254 }; 2255 2256 static void set_default_power_save(struct azx *chip) 2257 { 2258 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 2259 int val = power_save; 2260 2261 if (pm_blacklist < 0) { 2262 const struct snd_pci_quirk *q; 2263 2264 q = snd_pci_quirk_lookup(chip->pci, power_save_denylist); 2265 if (q && val) { 2266 dev_info(chip->card->dev, "device %04x:%04x is on the power_save denylist, forcing power_save to 0\n", 2267 q->subvendor, q->subdevice); 2268 val = 0; 2269 hda->runtime_pm_disabled = 1; 2270 } 2271 } else if (pm_blacklist > 0) { 2272 dev_info(chip->card->dev, "Forcing power_save to 0 via option\n"); 2273 val = 0; 2274 } 2275 snd_hda_set_power_save(&chip->bus, val * 1000); 2276 } 2277 2278 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */ 2279 static const unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = { 2280 [AZX_DRIVER_NVIDIA] = 8, 2281 [AZX_DRIVER_TERA] = 1, 2282 }; 2283 2284 static int azx_probe_continue(struct azx *chip) 2285 { 2286 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 2287 struct hdac_bus *bus = azx_bus(chip); 2288 struct pci_dev *pci = chip->pci; 2289 int dev = chip->dev_index; 2290 int err; 2291 2292 if (chip->disabled || hda->init_failed) 2293 return -EIO; 2294 if (hda->probe_retry) 2295 goto probe_retry; 2296 2297 to_hda_bus(bus)->bus_probing = 1; 2298 hda->probe_continued = 1; 2299 2300 /* Request display power well for the HDA controller or codec. For 2301 * Haswell/Broadwell, both the display HDA controller and codec need 2302 * this power. For other platforms, like Baytrail/Braswell, only the 2303 * display codec needs the power and it can be released after probe. 2304 */ 2305 display_power(chip, true); 2306 2307 err = azx_first_init(chip); 2308 if (err < 0) 2309 goto out_free; 2310 2311 #ifdef CONFIG_SND_HDA_INPUT_BEEP 2312 chip->beep_mode = beep_mode[dev]; 2313 #endif 2314 2315 chip->ctl_dev_id = ctl_dev_id; 2316 2317 /* create codec instances */ 2318 if (bus->codec_mask) { 2319 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]); 2320 if (err < 0) 2321 goto out_free; 2322 } 2323 2324 #ifdef CONFIG_SND_HDA_PATCH_LOADER 2325 if (chip->fw) { 2326 err = snd_hda_load_patch(&chip->bus, chip->fw->size, 2327 chip->fw->data); 2328 if (err < 0) 2329 goto out_free; 2330 } 2331 #endif 2332 2333 probe_retry: 2334 if (bus->codec_mask && !(probe_only[dev] & 1)) { 2335 err = azx_codec_configure(chip); 2336 if (err) { 2337 if ((chip->driver_caps & AZX_DCAPS_RETRY_PROBE) && 2338 ++hda->probe_retry < 60) { 2339 schedule_delayed_work(&hda->probe_work, 2340 msecs_to_jiffies(1000)); 2341 return 0; /* keep things up */ 2342 } 2343 dev_err(chip->card->dev, "Cannot probe codecs, giving up\n"); 2344 goto out_free; 2345 } 2346 } 2347 2348 err = snd_card_register(chip->card); 2349 if (err < 0) 2350 goto out_free; 2351 2352 setup_vga_switcheroo_runtime_pm(chip); 2353 2354 chip->running = 1; 2355 azx_add_card_list(chip); 2356 2357 set_default_power_save(chip); 2358 2359 if (azx_has_pm_runtime(chip)) { 2360 pm_runtime_use_autosuspend(&pci->dev); 2361 pm_runtime_allow(&pci->dev); 2362 pm_runtime_put_autosuspend(&pci->dev); 2363 } 2364 2365 out_free: 2366 if (err < 0) { 2367 pci_set_drvdata(pci, NULL); 2368 snd_card_free(chip->card); 2369 return err; 2370 } 2371 2372 if (!hda->need_i915_power) 2373 display_power(chip, false); 2374 complete_all(&hda->probe_wait); 2375 to_hda_bus(bus)->bus_probing = 0; 2376 hda->probe_retry = 0; 2377 return 0; 2378 } 2379 2380 static void azx_remove(struct pci_dev *pci) 2381 { 2382 struct snd_card *card = pci_get_drvdata(pci); 2383 struct azx *chip; 2384 struct hda_intel *hda; 2385 2386 if (card) { 2387 /* cancel the pending probing work */ 2388 chip = card->private_data; 2389 hda = container_of(chip, struct hda_intel, chip); 2390 /* FIXME: below is an ugly workaround. 2391 * Both device_release_driver() and driver_probe_device() 2392 * take *both* the device's and its parent's lock before 2393 * calling the remove() and probe() callbacks. The codec 2394 * probe takes the locks of both the codec itself and its 2395 * parent, i.e. the PCI controller dev. Meanwhile, when 2396 * the PCI controller is unbound, it takes its lock, too 2397 * ==> ouch, a deadlock! 2398 * As a workaround, we unlock temporarily here the controller 2399 * device during cancel_work_sync() call. 2400 */ 2401 device_unlock(&pci->dev); 2402 cancel_delayed_work_sync(&hda->probe_work); 2403 device_lock(&pci->dev); 2404 2405 clear_bit(chip->dev_index, probed_devs); 2406 pci_set_drvdata(pci, NULL); 2407 snd_card_free(card); 2408 } 2409 } 2410 2411 static void azx_shutdown(struct pci_dev *pci) 2412 { 2413 struct snd_card *card = pci_get_drvdata(pci); 2414 struct azx *chip; 2415 2416 if (!card) 2417 return; 2418 chip = card->private_data; 2419 if (chip && chip->running) 2420 __azx_shutdown_chip(chip, true); 2421 } 2422 2423 /* PCI IDs */ 2424 static const struct pci_device_id azx_ids[] = { 2425 /* CPT */ 2426 { PCI_DEVICE_DATA(INTEL, HDA_CPT, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM) }, 2427 /* PBG */ 2428 { PCI_DEVICE_DATA(INTEL, HDA_PBG, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM) }, 2429 /* Panther Point */ 2430 { PCI_DEVICE_DATA(INTEL, HDA_PPT, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM) }, 2431 /* Lynx Point */ 2432 { PCI_DEVICE_DATA(INTEL, HDA_LPT, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) }, 2433 /* 9 Series */ 2434 { PCI_DEVICE_DATA(INTEL, HDA_9_SERIES, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) }, 2435 /* Wellsburg */ 2436 { PCI_DEVICE_DATA(INTEL, HDA_WBG_0, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) }, 2437 { PCI_DEVICE_DATA(INTEL, HDA_WBG_1, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) }, 2438 /* Lewisburg */ 2439 { PCI_DEVICE_DATA(INTEL, HDA_LBG_0, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE) }, 2440 { PCI_DEVICE_DATA(INTEL, HDA_LBG_1, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE) }, 2441 /* Lynx Point-LP */ 2442 { PCI_DEVICE_DATA(INTEL, HDA_LPT_LP_0, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) }, 2443 /* Lynx Point-LP */ 2444 { PCI_DEVICE_DATA(INTEL, HDA_LPT_LP_1, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) }, 2445 /* Wildcat Point-LP */ 2446 { PCI_DEVICE_DATA(INTEL, HDA_WPT_LP, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) }, 2447 /* Skylake (Sunrise Point) */ 2448 { PCI_DEVICE_DATA(INTEL, HDA_SKL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2449 /* Skylake-LP (Sunrise Point-LP) */ 2450 { PCI_DEVICE_DATA(INTEL, HDA_SKL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2451 /* Kabylake */ 2452 { PCI_DEVICE_DATA(INTEL, HDA_KBL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2453 /* Kabylake-LP */ 2454 { PCI_DEVICE_DATA(INTEL, HDA_KBL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2455 /* Kabylake-H */ 2456 { PCI_DEVICE_DATA(INTEL, HDA_KBL_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2457 /* Coffelake */ 2458 { PCI_DEVICE_DATA(INTEL, HDA_CNL_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2459 /* Cannonlake */ 2460 { PCI_DEVICE_DATA(INTEL, HDA_CNL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2461 /* CometLake-LP */ 2462 { PCI_DEVICE_DATA(INTEL, HDA_CML_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2463 /* CometLake-H */ 2464 { PCI_DEVICE_DATA(INTEL, HDA_CML_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2465 { PCI_DEVICE_DATA(INTEL, HDA_RKL_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2466 /* CometLake-S */ 2467 { PCI_DEVICE_DATA(INTEL, HDA_CML_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2468 /* CometLake-R */ 2469 { PCI_DEVICE_DATA(INTEL, HDA_CML_R, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2470 /* Icelake */ 2471 { PCI_DEVICE_DATA(INTEL, HDA_ICL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2472 /* Icelake-H */ 2473 { PCI_DEVICE_DATA(INTEL, HDA_ICL_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2474 /* Jasperlake */ 2475 { PCI_DEVICE_DATA(INTEL, HDA_ICL_N, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2476 { PCI_DEVICE_DATA(INTEL, HDA_JSL_N, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2477 /* Tigerlake */ 2478 { PCI_DEVICE_DATA(INTEL, HDA_TGL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2479 /* Tigerlake-H */ 2480 { PCI_DEVICE_DATA(INTEL, HDA_TGL_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2481 /* DG1 */ 2482 { PCI_DEVICE_DATA(INTEL, HDA_DG1, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2483 /* DG2 */ 2484 { PCI_DEVICE_DATA(INTEL, HDA_DG2_0, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2485 { PCI_DEVICE_DATA(INTEL, HDA_DG2_1, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2486 { PCI_DEVICE_DATA(INTEL, HDA_DG2_2, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2487 /* Alderlake-S */ 2488 { PCI_DEVICE_DATA(INTEL, HDA_ADL_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2489 /* Alderlake-P */ 2490 { PCI_DEVICE_DATA(INTEL, HDA_ADL_P, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2491 { PCI_DEVICE_DATA(INTEL, HDA_ADL_PS, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2492 { PCI_DEVICE_DATA(INTEL, HDA_ADL_PX, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2493 /* Alderlake-M */ 2494 { PCI_DEVICE_DATA(INTEL, HDA_ADL_M, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2495 /* Alderlake-N */ 2496 { PCI_DEVICE_DATA(INTEL, HDA_ADL_N, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2497 /* Elkhart Lake */ 2498 { PCI_DEVICE_DATA(INTEL, HDA_EHL_0, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2499 { PCI_DEVICE_DATA(INTEL, HDA_EHL_3, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2500 /* Raptor Lake */ 2501 { PCI_DEVICE_DATA(INTEL, HDA_RPL_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2502 { PCI_DEVICE_DATA(INTEL, HDA_RPL_P_0, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2503 { PCI_DEVICE_DATA(INTEL, HDA_RPL_P_1, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2504 { PCI_DEVICE_DATA(INTEL, HDA_RPL_M, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2505 { PCI_DEVICE_DATA(INTEL, HDA_RPL_PX, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2506 { PCI_DEVICE_DATA(INTEL, HDA_MTL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2507 /* Battlemage */ 2508 { PCI_DEVICE_DATA(INTEL, HDA_BMG, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2509 /* Lunarlake-P */ 2510 { PCI_DEVICE_DATA(INTEL, HDA_LNL_P, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_LNL) }, 2511 /* Arrow Lake-S */ 2512 { PCI_DEVICE_DATA(INTEL, HDA_ARL_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2513 /* Arrow Lake */ 2514 { PCI_DEVICE_DATA(INTEL, HDA_ARL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2515 /* Panther Lake */ 2516 { PCI_DEVICE_DATA(INTEL, HDA_PTL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_LNL) }, 2517 /* Apollolake (Broxton-P) */ 2518 { PCI_DEVICE_DATA(INTEL, HDA_APL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON) }, 2519 /* Gemini-Lake */ 2520 { PCI_DEVICE_DATA(INTEL, HDA_GML, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON) }, 2521 /* Haswell */ 2522 { PCI_DEVICE_DATA(INTEL, HDA_HSW_0, AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL) }, 2523 { PCI_DEVICE_DATA(INTEL, HDA_HSW_2, AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL) }, 2524 { PCI_DEVICE_DATA(INTEL, HDA_HSW_3, AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL) }, 2525 /* Broadwell */ 2526 { PCI_DEVICE_DATA(INTEL, HDA_BDW, AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL) }, 2527 /* 5 Series/3400 */ 2528 { PCI_DEVICE_DATA(INTEL, HDA_5_3400_SERIES_0, AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM) }, 2529 { PCI_DEVICE_DATA(INTEL, HDA_5_3400_SERIES_1, AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM) }, 2530 /* Poulsbo */ 2531 { PCI_DEVICE_DATA(INTEL, HDA_POULSBO, AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE | 2532 AZX_DCAPS_POSFIX_LPIB) }, 2533 /* Oaktrail */ 2534 { PCI_DEVICE_DATA(INTEL, HDA_OAKTRAIL, AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE) }, 2535 /* BayTrail */ 2536 { PCI_DEVICE_DATA(INTEL, HDA_BYT, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL) }, 2537 /* Braswell */ 2538 { PCI_DEVICE_DATA(INTEL, HDA_BSW, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL) }, 2539 /* ICH6 */ 2540 { PCI_DEVICE_DATA(INTEL, HDA_ICH6, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) }, 2541 /* ICH7 */ 2542 { PCI_DEVICE_DATA(INTEL, HDA_ICH7, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) }, 2543 /* ESB2 */ 2544 { PCI_DEVICE_DATA(INTEL, HDA_ESB2, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) }, 2545 /* ICH8 */ 2546 { PCI_DEVICE_DATA(INTEL, HDA_ICH8, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) }, 2547 /* ICH9 */ 2548 { PCI_DEVICE_DATA(INTEL, HDA_ICH9_0, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) }, 2549 /* ICH9 */ 2550 { PCI_DEVICE_DATA(INTEL, HDA_ICH9_1, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) }, 2551 /* ICH10 */ 2552 { PCI_DEVICE_DATA(INTEL, HDA_ICH10_0, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) }, 2553 /* ICH10 */ 2554 { PCI_DEVICE_DATA(INTEL, HDA_ICH10_1, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) }, 2555 /* Generic Intel */ 2556 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID), 2557 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2558 .class_mask = 0xffffff, 2559 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE }, 2560 /* ATI SB 450/600/700/800/900 */ 2561 { PCI_VDEVICE(ATI, 0x437b), 2562 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, 2563 { PCI_VDEVICE(ATI, 0x4383), 2564 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, 2565 /* AMD Hudson */ 2566 { PCI_VDEVICE(AMD, 0x780d), 2567 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB }, 2568 /* AMD, X370 & co */ 2569 { PCI_VDEVICE(AMD, 0x1457), 2570 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB }, 2571 /* AMD, X570 & co */ 2572 { PCI_VDEVICE(AMD, 0x1487), 2573 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB }, 2574 /* AMD Stoney */ 2575 { PCI_VDEVICE(AMD, 0x157a), 2576 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB | 2577 AZX_DCAPS_PM_RUNTIME }, 2578 /* AMD Raven */ 2579 { PCI_VDEVICE(AMD, 0x15e3), 2580 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB }, 2581 /* ATI HDMI */ 2582 { PCI_VDEVICE(ATI, 0x0002), 2583 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2584 AZX_DCAPS_PM_RUNTIME }, 2585 { PCI_VDEVICE(ATI, 0x1308), 2586 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2587 { PCI_VDEVICE(ATI, 0x157a), 2588 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2589 { PCI_VDEVICE(ATI, 0x15b3), 2590 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2591 { PCI_VDEVICE(ATI, 0x793b), 2592 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2593 { PCI_VDEVICE(ATI, 0x7919), 2594 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2595 { PCI_VDEVICE(ATI, 0x960f), 2596 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2597 { PCI_VDEVICE(ATI, 0x970f), 2598 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2599 { PCI_VDEVICE(ATI, 0x9840), 2600 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2601 { PCI_VDEVICE(ATI, 0xaa00), 2602 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2603 { PCI_VDEVICE(ATI, 0xaa08), 2604 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2605 { PCI_VDEVICE(ATI, 0xaa10), 2606 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2607 { PCI_VDEVICE(ATI, 0xaa18), 2608 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2609 { PCI_VDEVICE(ATI, 0xaa20), 2610 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2611 { PCI_VDEVICE(ATI, 0xaa28), 2612 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2613 { PCI_VDEVICE(ATI, 0xaa30), 2614 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2615 { PCI_VDEVICE(ATI, 0xaa38), 2616 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2617 { PCI_VDEVICE(ATI, 0xaa40), 2618 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2619 { PCI_VDEVICE(ATI, 0xaa48), 2620 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2621 { PCI_VDEVICE(ATI, 0xaa50), 2622 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2623 { PCI_VDEVICE(ATI, 0xaa58), 2624 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2625 { PCI_VDEVICE(ATI, 0xaa60), 2626 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2627 { PCI_VDEVICE(ATI, 0xaa68), 2628 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2629 { PCI_VDEVICE(ATI, 0xaa80), 2630 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2631 { PCI_VDEVICE(ATI, 0xaa88), 2632 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2633 { PCI_VDEVICE(ATI, 0xaa90), 2634 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2635 { PCI_VDEVICE(ATI, 0xaa98), 2636 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2637 { PCI_VDEVICE(ATI, 0x9902), 2638 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2639 { PCI_VDEVICE(ATI, 0xaaa0), 2640 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2641 { PCI_VDEVICE(ATI, 0xaaa8), 2642 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2643 { PCI_VDEVICE(ATI, 0xaab0), 2644 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2645 { PCI_VDEVICE(ATI, 0xaac0), 2646 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2647 AZX_DCAPS_PM_RUNTIME }, 2648 { PCI_VDEVICE(ATI, 0xaac8), 2649 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2650 AZX_DCAPS_PM_RUNTIME }, 2651 { PCI_VDEVICE(ATI, 0xaad8), 2652 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2653 AZX_DCAPS_PM_RUNTIME }, 2654 { PCI_VDEVICE(ATI, 0xaae0), 2655 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2656 AZX_DCAPS_PM_RUNTIME }, 2657 { PCI_VDEVICE(ATI, 0xaae8), 2658 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2659 AZX_DCAPS_PM_RUNTIME }, 2660 { PCI_VDEVICE(ATI, 0xaaf0), 2661 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2662 AZX_DCAPS_PM_RUNTIME }, 2663 { PCI_VDEVICE(ATI, 0xaaf8), 2664 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2665 AZX_DCAPS_PM_RUNTIME }, 2666 { PCI_VDEVICE(ATI, 0xab00), 2667 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2668 AZX_DCAPS_PM_RUNTIME }, 2669 { PCI_VDEVICE(ATI, 0xab08), 2670 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2671 AZX_DCAPS_PM_RUNTIME }, 2672 { PCI_VDEVICE(ATI, 0xab10), 2673 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2674 AZX_DCAPS_PM_RUNTIME }, 2675 { PCI_VDEVICE(ATI, 0xab18), 2676 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2677 AZX_DCAPS_PM_RUNTIME }, 2678 { PCI_VDEVICE(ATI, 0xab20), 2679 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2680 AZX_DCAPS_PM_RUNTIME }, 2681 { PCI_VDEVICE(ATI, 0xab28), 2682 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2683 AZX_DCAPS_PM_RUNTIME }, 2684 { PCI_VDEVICE(ATI, 0xab30), 2685 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2686 AZX_DCAPS_PM_RUNTIME }, 2687 { PCI_VDEVICE(ATI, 0xab38), 2688 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2689 AZX_DCAPS_PM_RUNTIME }, 2690 /* GLENFLY */ 2691 { PCI_DEVICE(PCI_VENDOR_ID_GLENFLY, PCI_ANY_ID), 2692 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2693 .class_mask = 0xffffff, 2694 .driver_data = AZX_DRIVER_GFHDMI | AZX_DCAPS_POSFIX_LPIB | 2695 AZX_DCAPS_NO_MSI | AZX_DCAPS_NO_64BIT }, 2696 /* VIA VT8251/VT8237A */ 2697 { PCI_VDEVICE(VIA, 0x3288), .driver_data = AZX_DRIVER_VIA }, 2698 /* VIA GFX VT7122/VX900 */ 2699 { PCI_VDEVICE(VIA, 0x9170), .driver_data = AZX_DRIVER_GENERIC }, 2700 /* VIA GFX VT6122/VX11 */ 2701 { PCI_VDEVICE(VIA, 0x9140), .driver_data = AZX_DRIVER_GENERIC }, 2702 /* SIS966 */ 2703 { PCI_VDEVICE(SI, 0x7502), .driver_data = AZX_DRIVER_SIS }, 2704 /* ULI M5461 */ 2705 { PCI_VDEVICE(AL, 0x5461), .driver_data = AZX_DRIVER_ULI }, 2706 /* NVIDIA MCP */ 2707 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID), 2708 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2709 .class_mask = 0xffffff, 2710 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA }, 2711 /* Teradici */ 2712 { PCI_DEVICE(0x6549, 0x1200), 2713 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, 2714 { PCI_DEVICE(0x6549, 0x2200), 2715 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, 2716 /* Creative X-Fi (CA0110-IBG) */ 2717 /* CTHDA chips */ 2718 { PCI_VDEVICE(CREATIVE, 0x0010), 2719 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, 2720 { PCI_VDEVICE(CREATIVE, 0x0012), 2721 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, 2722 #if !IS_ENABLED(CONFIG_SND_CTXFI) 2723 /* the following entry conflicts with snd-ctxfi driver, 2724 * as ctxfi driver mutates from HD-audio to native mode with 2725 * a special command sequence. 2726 */ 2727 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID), 2728 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2729 .class_mask = 0xffffff, 2730 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | 2731 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB }, 2732 #else 2733 /* this entry seems still valid -- i.e. without emu20kx chip */ 2734 { PCI_VDEVICE(CREATIVE, 0x0009), 2735 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | 2736 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB }, 2737 #endif 2738 /* CM8888 */ 2739 { PCI_VDEVICE(CMEDIA, 0x5011), 2740 .driver_data = AZX_DRIVER_CMEDIA | 2741 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF }, 2742 /* Vortex86MX */ 2743 { PCI_VDEVICE(RDC, 0x3010), .driver_data = AZX_DRIVER_GENERIC }, 2744 /* VMware HDAudio */ 2745 { PCI_VDEVICE(VMWARE, 0x1977), .driver_data = AZX_DRIVER_GENERIC }, 2746 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */ 2747 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID), 2748 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2749 .class_mask = 0xffffff, 2750 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, 2751 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID), 2752 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2753 .class_mask = 0xffffff, 2754 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, 2755 /* Zhaoxin */ 2756 { PCI_VDEVICE(ZHAOXIN, 0x3288), .driver_data = AZX_DRIVER_ZHAOXIN }, 2757 /* Loongson HDAudio*/ 2758 { PCI_VDEVICE(LOONGSON, PCI_DEVICE_ID_LOONGSON_HDA), 2759 .driver_data = AZX_DRIVER_LOONGSON }, 2760 { PCI_VDEVICE(LOONGSON, PCI_DEVICE_ID_LOONGSON_HDMI), 2761 .driver_data = AZX_DRIVER_LOONGSON }, 2762 { 0, } 2763 }; 2764 MODULE_DEVICE_TABLE(pci, azx_ids); 2765 2766 /* pci_driver definition */ 2767 static struct pci_driver azx_driver = { 2768 .name = KBUILD_MODNAME, 2769 .id_table = azx_ids, 2770 .probe = azx_probe, 2771 .remove = azx_remove, 2772 .shutdown = azx_shutdown, 2773 .driver = { 2774 .pm = &azx_pm, 2775 }, 2776 }; 2777 2778 module_pci_driver(azx_driver); 2779