1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * 4 * hda_intel.c - Implementation of primary alsa driver code base 5 * for Intel HD Audio. 6 * 7 * Copyright(c) 2004 Intel Corporation 8 * 9 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> 10 * PeiSen Hou <pshou@realtek.com.tw> 11 * 12 * CONTACTS: 13 * 14 * Matt Jared matt.jared@intel.com 15 * Andy Kopp andy.kopp@intel.com 16 * Dan Kogan dan.d.kogan@intel.com 17 * 18 * CHANGES: 19 * 20 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou 21 */ 22 23 #include <linux/delay.h> 24 #include <linux/interrupt.h> 25 #include <linux/kernel.h> 26 #include <linux/module.h> 27 #include <linux/dma-mapping.h> 28 #include <linux/moduleparam.h> 29 #include <linux/init.h> 30 #include <linux/slab.h> 31 #include <linux/pci.h> 32 #include <linux/mutex.h> 33 #include <linux/io.h> 34 #include <linux/pm_runtime.h> 35 #include <linux/clocksource.h> 36 #include <linux/time.h> 37 #include <linux/completion.h> 38 #include <linux/acpi.h> 39 #include <linux/pgtable.h> 40 41 #ifdef CONFIG_X86 42 /* for snoop control */ 43 #include <asm/set_memory.h> 44 #include <asm/cpufeature.h> 45 #endif 46 #include <sound/core.h> 47 #include <sound/initval.h> 48 #include <sound/hdaudio.h> 49 #include <sound/hda_i915.h> 50 #include <sound/intel-dsp-config.h> 51 #include <linux/vgaarb.h> 52 #include <linux/vga_switcheroo.h> 53 #include <linux/apple-gmux.h> 54 #include <linux/firmware.h> 55 #include <sound/hda_codec.h> 56 #include "hda_controller.h" 57 #include "hda_intel.h" 58 59 #define CREATE_TRACE_POINTS 60 #include "hda_intel_trace.h" 61 62 /* position fix mode */ 63 enum { 64 POS_FIX_AUTO, 65 POS_FIX_LPIB, 66 POS_FIX_POSBUF, 67 POS_FIX_VIACOMBO, 68 POS_FIX_COMBO, 69 POS_FIX_SKL, 70 POS_FIX_FIFO, 71 }; 72 73 /* Defines for ATI HD Audio support in SB450 south bridge */ 74 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42 75 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02 76 77 /* Defines for Nvidia HDA support */ 78 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e 79 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f 80 #define NVIDIA_HDA_ISTRM_COH 0x4d 81 #define NVIDIA_HDA_OSTRM_COH 0x4c 82 #define NVIDIA_HDA_ENABLE_COHBIT 0x01 83 84 /* Defines for Intel SCH HDA snoop control */ 85 #define INTEL_HDA_CGCTL 0x48 86 #define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6) 87 #define INTEL_SCH_HDA_DEVC 0x78 88 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11) 89 90 /* max number of SDs */ 91 /* ICH, ATI and VIA have 4 playback and 4 capture */ 92 #define ICH6_NUM_CAPTURE 4 93 #define ICH6_NUM_PLAYBACK 4 94 95 /* ULI has 6 playback and 5 capture */ 96 #define ULI_NUM_CAPTURE 5 97 #define ULI_NUM_PLAYBACK 6 98 99 /* ATI HDMI may have up to 8 playbacks and 0 capture */ 100 #define ATIHDMI_NUM_CAPTURE 0 101 #define ATIHDMI_NUM_PLAYBACK 8 102 103 104 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; 105 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; 106 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; 107 static char *model[SNDRV_CARDS]; 108 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 109 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 110 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 111 static int probe_only[SNDRV_CARDS]; 112 static int jackpoll_ms[SNDRV_CARDS]; 113 static int single_cmd = -1; 114 static int enable_msi = -1; 115 #ifdef CONFIG_SND_HDA_PATCH_LOADER 116 static char *patch[SNDRV_CARDS]; 117 #endif 118 #ifdef CONFIG_SND_HDA_INPUT_BEEP 119 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = 120 CONFIG_SND_HDA_INPUT_BEEP_MODE}; 121 #endif 122 static bool dmic_detect = 1; 123 static bool ctl_dev_id = IS_ENABLED(CONFIG_SND_HDA_CTL_DEV_ID) ? 1 : 0; 124 125 module_param_array(index, int, NULL, 0444); 126 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface."); 127 module_param_array(id, charp, NULL, 0444); 128 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface."); 129 module_param_array(enable, bool, NULL, 0444); 130 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface."); 131 module_param_array(model, charp, NULL, 0444); 132 MODULE_PARM_DESC(model, "Use the given board model."); 133 module_param_array(position_fix, int, NULL, 0444); 134 MODULE_PARM_DESC(position_fix, "DMA pointer read method." 135 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+, 6 = FIFO)."); 136 module_param_array(bdl_pos_adj, int, NULL, 0644); 137 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset."); 138 module_param_array(probe_mask, int, NULL, 0444); 139 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1)."); 140 module_param_array(probe_only, int, NULL, 0444); 141 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization."); 142 module_param_array(jackpoll_ms, int, NULL, 0444); 143 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)"); 144 module_param(single_cmd, bint, 0444); 145 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs " 146 "(for debugging only)."); 147 module_param(enable_msi, bint, 0444); 148 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)"); 149 #ifdef CONFIG_SND_HDA_PATCH_LOADER 150 module_param_array(patch, charp, NULL, 0444); 151 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface."); 152 #endif 153 #ifdef CONFIG_SND_HDA_INPUT_BEEP 154 module_param_array(beep_mode, bool, NULL, 0444); 155 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode " 156 "(0=off, 1=on) (default=1)."); 157 #endif 158 module_param(dmic_detect, bool, 0444); 159 MODULE_PARM_DESC(dmic_detect, "Allow DSP driver selection (bypass this driver) " 160 "(0=off, 1=on) (default=1); " 161 "deprecated, use snd-intel-dspcfg.dsp_driver option instead"); 162 module_param(ctl_dev_id, bool, 0444); 163 MODULE_PARM_DESC(ctl_dev_id, "Use control device identifier (based on codec address)."); 164 165 #ifdef CONFIG_PM 166 static int param_set_xint(const char *val, const struct kernel_param *kp); 167 static const struct kernel_param_ops param_ops_xint = { 168 .set = param_set_xint, 169 .get = param_get_int, 170 }; 171 #define param_check_xint param_check_int 172 173 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT; 174 module_param(power_save, xint, 0644); 175 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout " 176 "(in second, 0 = disable)."); 177 178 static int pm_blacklist = -1; 179 module_param(pm_blacklist, bint, 0644); 180 MODULE_PARM_DESC(pm_blacklist, "Enable power-management denylist"); 181 182 /* reset the HD-audio controller in power save mode. 183 * this may give more power-saving, but will take longer time to 184 * wake up. 185 */ 186 static bool power_save_controller = 1; 187 module_param(power_save_controller, bool, 0644); 188 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode."); 189 #else /* CONFIG_PM */ 190 #define power_save 0 191 #define pm_blacklist 0 192 #define power_save_controller false 193 #endif /* CONFIG_PM */ 194 195 static int align_buffer_size = -1; 196 module_param(align_buffer_size, bint, 0644); 197 MODULE_PARM_DESC(align_buffer_size, 198 "Force buffer and period sizes to be multiple of 128 bytes."); 199 200 #ifdef CONFIG_X86 201 static int hda_snoop = -1; 202 module_param_named(snoop, hda_snoop, bint, 0444); 203 MODULE_PARM_DESC(snoop, "Enable/disable snooping"); 204 #else 205 #define hda_snoop true 206 #endif 207 208 209 MODULE_LICENSE("GPL"); 210 MODULE_DESCRIPTION("Intel HDA driver"); 211 212 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO) 213 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI) 214 #define SUPPORT_VGA_SWITCHEROO 215 #endif 216 #endif 217 218 219 /* 220 */ 221 222 /* driver types */ 223 enum { 224 AZX_DRIVER_ICH, 225 AZX_DRIVER_PCH, 226 AZX_DRIVER_SCH, 227 AZX_DRIVER_SKL, 228 AZX_DRIVER_HDMI, 229 AZX_DRIVER_ATI, 230 AZX_DRIVER_ATIHDMI, 231 AZX_DRIVER_ATIHDMI_NS, 232 AZX_DRIVER_GFHDMI, 233 AZX_DRIVER_VIA, 234 AZX_DRIVER_SIS, 235 AZX_DRIVER_ULI, 236 AZX_DRIVER_NVIDIA, 237 AZX_DRIVER_TERA, 238 AZX_DRIVER_CTX, 239 AZX_DRIVER_CTHDA, 240 AZX_DRIVER_CMEDIA, 241 AZX_DRIVER_ZHAOXIN, 242 AZX_DRIVER_LOONGSON, 243 AZX_DRIVER_GENERIC, 244 AZX_NUM_DRIVERS, /* keep this as last entry */ 245 }; 246 247 #define azx_get_snoop_type(chip) \ 248 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10) 249 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10) 250 251 /* quirks for old Intel chipsets */ 252 #define AZX_DCAPS_INTEL_ICH \ 253 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE) 254 255 /* quirks for Intel PCH */ 256 #define AZX_DCAPS_INTEL_PCH_BASE \ 257 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\ 258 AZX_DCAPS_SNOOP_TYPE(SCH)) 259 260 /* PCH up to IVB; no runtime PM; bind with i915 gfx */ 261 #define AZX_DCAPS_INTEL_PCH_NOPM \ 262 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT) 263 264 /* PCH for HSW/BDW; with runtime PM */ 265 /* no i915 binding for this as HSW/BDW has another controller for HDMI */ 266 #define AZX_DCAPS_INTEL_PCH \ 267 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME) 268 269 /* HSW HDMI */ 270 #define AZX_DCAPS_INTEL_HASWELL \ 271 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\ 272 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\ 273 AZX_DCAPS_SNOOP_TYPE(SCH)) 274 275 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */ 276 #define AZX_DCAPS_INTEL_BROADWELL \ 277 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\ 278 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\ 279 AZX_DCAPS_SNOOP_TYPE(SCH)) 280 281 #define AZX_DCAPS_INTEL_BAYTRAIL \ 282 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT) 283 284 #define AZX_DCAPS_INTEL_BRASWELL \ 285 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\ 286 AZX_DCAPS_I915_COMPONENT) 287 288 #define AZX_DCAPS_INTEL_SKYLAKE \ 289 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\ 290 AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT) 291 292 #define AZX_DCAPS_INTEL_BROXTON AZX_DCAPS_INTEL_SKYLAKE 293 294 #define AZX_DCAPS_INTEL_LNL \ 295 (AZX_DCAPS_INTEL_SKYLAKE | AZX_DCAPS_PIO_COMMANDS) 296 297 /* quirks for ATI SB / AMD Hudson */ 298 #define AZX_DCAPS_PRESET_ATI_SB \ 299 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB |\ 300 AZX_DCAPS_SNOOP_TYPE(ATI)) 301 302 /* quirks for ATI/AMD HDMI */ 303 #define AZX_DCAPS_PRESET_ATI_HDMI \ 304 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB|\ 305 AZX_DCAPS_NO_MSI64) 306 307 /* quirks for ATI HDMI with snoop off */ 308 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \ 309 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF) 310 311 /* quirks for AMD SB */ 312 #define AZX_DCAPS_PRESET_AMD_SB \ 313 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_AMD_WORKAROUND |\ 314 AZX_DCAPS_SNOOP_TYPE(ATI) | AZX_DCAPS_PM_RUNTIME |\ 315 AZX_DCAPS_RETRY_PROBE) 316 317 /* quirks for Nvidia */ 318 #define AZX_DCAPS_PRESET_NVIDIA \ 319 (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\ 320 AZX_DCAPS_SNOOP_TYPE(NVIDIA)) 321 322 #define AZX_DCAPS_PRESET_CTHDA \ 323 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\ 324 AZX_DCAPS_NO_64BIT |\ 325 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF) 326 327 /* 328 * vga_switcheroo support 329 */ 330 #ifdef SUPPORT_VGA_SWITCHEROO 331 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo) 332 #define needs_eld_notify_link(chip) ((chip)->bus.keep_power) 333 #else 334 #define use_vga_switcheroo(chip) 0 335 #define needs_eld_notify_link(chip) false 336 #endif 337 338 static const char * const driver_short_names[] = { 339 [AZX_DRIVER_ICH] = "HDA Intel", 340 [AZX_DRIVER_PCH] = "HDA Intel PCH", 341 [AZX_DRIVER_SCH] = "HDA Intel MID", 342 [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */ 343 [AZX_DRIVER_HDMI] = "HDA Intel HDMI", 344 [AZX_DRIVER_ATI] = "HDA ATI SB", 345 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI", 346 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI", 347 [AZX_DRIVER_GFHDMI] = "HDA GF HDMI", 348 [AZX_DRIVER_VIA] = "HDA VIA VT82xx", 349 [AZX_DRIVER_SIS] = "HDA SIS966", 350 [AZX_DRIVER_ULI] = "HDA ULI M5461", 351 [AZX_DRIVER_NVIDIA] = "HDA NVidia", 352 [AZX_DRIVER_TERA] = "HDA Teradici", 353 [AZX_DRIVER_CTX] = "HDA Creative", 354 [AZX_DRIVER_CTHDA] = "HDA Creative", 355 [AZX_DRIVER_CMEDIA] = "HDA C-Media", 356 [AZX_DRIVER_ZHAOXIN] = "HDA Zhaoxin", 357 [AZX_DRIVER_LOONGSON] = "HDA Loongson", 358 [AZX_DRIVER_GENERIC] = "HD-Audio Generic", 359 }; 360 361 static int azx_acquire_irq(struct azx *chip, int do_disconnect); 362 static void set_default_power_save(struct azx *chip); 363 364 /* 365 * initialize the PCI registers 366 */ 367 /* update bits in a PCI register byte */ 368 static void update_pci_byte(struct pci_dev *pci, unsigned int reg, 369 unsigned char mask, unsigned char val) 370 { 371 unsigned char data; 372 373 pci_read_config_byte(pci, reg, &data); 374 data &= ~mask; 375 data |= (val & mask); 376 pci_write_config_byte(pci, reg, data); 377 } 378 379 static void azx_init_pci(struct azx *chip) 380 { 381 int snoop_type = azx_get_snoop_type(chip); 382 383 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44) 384 * TCSEL == Traffic Class Select Register, which sets PCI express QOS 385 * Ensuring these bits are 0 clears playback static on some HD Audio 386 * codecs. 387 * The PCI register TCSEL is defined in the Intel manuals. 388 */ 389 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) { 390 dev_dbg(chip->card->dev, "Clearing TCSEL\n"); 391 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0); 392 } 393 394 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio, 395 * we need to enable snoop. 396 */ 397 if (snoop_type == AZX_SNOOP_TYPE_ATI) { 398 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n", 399 azx_snoop(chip)); 400 update_pci_byte(chip->pci, 401 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07, 402 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0); 403 } 404 405 /* For NVIDIA HDA, enable snoop */ 406 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) { 407 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n", 408 azx_snoop(chip)); 409 update_pci_byte(chip->pci, 410 NVIDIA_HDA_TRANSREG_ADDR, 411 0x0f, NVIDIA_HDA_ENABLE_COHBITS); 412 update_pci_byte(chip->pci, 413 NVIDIA_HDA_ISTRM_COH, 414 0x01, NVIDIA_HDA_ENABLE_COHBIT); 415 update_pci_byte(chip->pci, 416 NVIDIA_HDA_OSTRM_COH, 417 0x01, NVIDIA_HDA_ENABLE_COHBIT); 418 } 419 420 /* Enable SCH/PCH snoop if needed */ 421 if (snoop_type == AZX_SNOOP_TYPE_SCH) { 422 unsigned short snoop; 423 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop); 424 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) || 425 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) { 426 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP; 427 if (!azx_snoop(chip)) 428 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP; 429 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop); 430 pci_read_config_word(chip->pci, 431 INTEL_SCH_HDA_DEVC, &snoop); 432 } 433 dev_dbg(chip->card->dev, "SCH snoop: %s\n", 434 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ? 435 "Disabled" : "Enabled"); 436 } 437 } 438 439 /* 440 * In BXT-P A0, HD-Audio DMA requests is later than expected, 441 * and makes an audio stream sensitive to system latencies when 442 * 24/32 bits are playing. 443 * Adjusting threshold of DMA fifo to force the DMA request 444 * sooner to improve latency tolerance at the expense of power. 445 */ 446 static void bxt_reduce_dma_latency(struct azx *chip) 447 { 448 u32 val; 449 450 val = azx_readl(chip, VS_EM4L); 451 val &= (0x3 << 20); 452 azx_writel(chip, VS_EM4L, val); 453 } 454 455 /* 456 * ML_LCAP bits: 457 * bit 0: 6 MHz Supported 458 * bit 1: 12 MHz Supported 459 * bit 2: 24 MHz Supported 460 * bit 3: 48 MHz Supported 461 * bit 4: 96 MHz Supported 462 * bit 5: 192 MHz Supported 463 */ 464 static int intel_get_lctl_scf(struct azx *chip) 465 { 466 struct hdac_bus *bus = azx_bus(chip); 467 static const int preferred_bits[] = { 2, 3, 1, 4, 5 }; 468 u32 val, t; 469 int i; 470 471 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP); 472 473 for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) { 474 t = preferred_bits[i]; 475 if (val & (1 << t)) 476 return t; 477 } 478 479 dev_warn(chip->card->dev, "set audio clock frequency to 6MHz"); 480 return 0; 481 } 482 483 static int intel_ml_lctl_set_power(struct azx *chip, int state) 484 { 485 struct hdac_bus *bus = azx_bus(chip); 486 u32 val; 487 int timeout; 488 489 /* 490 * Changes to LCTL.SCF are only needed for the first multi-link dealing 491 * with external codecs 492 */ 493 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 494 val &= ~AZX_ML_LCTL_SPA; 495 val |= state << AZX_ML_LCTL_SPA_SHIFT; 496 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 497 /* wait for CPA */ 498 timeout = 50; 499 while (timeout) { 500 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) & 501 AZX_ML_LCTL_CPA) == (state << AZX_ML_LCTL_CPA_SHIFT)) 502 return 0; 503 timeout--; 504 udelay(10); 505 } 506 507 return -1; 508 } 509 510 static void intel_init_lctl(struct azx *chip) 511 { 512 struct hdac_bus *bus = azx_bus(chip); 513 u32 val; 514 int ret; 515 516 /* 0. check lctl register value is correct or not */ 517 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 518 /* only perform additional configurations if the SCF is initially based on 6MHz */ 519 if ((val & AZX_ML_LCTL_SCF) != 0) 520 return; 521 522 /* 523 * Before operating on SPA, CPA must match SPA. 524 * Any deviation may result in undefined behavior. 525 */ 526 if (((val & AZX_ML_LCTL_SPA) >> AZX_ML_LCTL_SPA_SHIFT) != 527 ((val & AZX_ML_LCTL_CPA) >> AZX_ML_LCTL_CPA_SHIFT)) 528 return; 529 530 /* 1. turn link down: set SPA to 0 and wait CPA to 0 */ 531 ret = intel_ml_lctl_set_power(chip, 0); 532 udelay(100); 533 if (ret) 534 goto set_spa; 535 536 /* 2. update SCF to select an audio clock different from 6MHz */ 537 val &= ~AZX_ML_LCTL_SCF; 538 val |= intel_get_lctl_scf(chip); 539 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 540 541 set_spa: 542 /* 4. turn link up: set SPA to 1 and wait CPA to 1 */ 543 intel_ml_lctl_set_power(chip, 1); 544 udelay(100); 545 } 546 547 static void hda_intel_init_chip(struct azx *chip, bool full_reset) 548 { 549 struct hdac_bus *bus = azx_bus(chip); 550 struct pci_dev *pci = chip->pci; 551 u32 val; 552 553 snd_hdac_set_codec_wakeup(bus, true); 554 if (chip->driver_type == AZX_DRIVER_SKL) { 555 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val); 556 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE; 557 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val); 558 } 559 azx_init_chip(chip, full_reset); 560 if (chip->driver_type == AZX_DRIVER_SKL) { 561 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val); 562 val = val | INTEL_HDA_CGCTL_MISCBDCGE; 563 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val); 564 } 565 566 snd_hdac_set_codec_wakeup(bus, false); 567 568 /* reduce dma latency to avoid noise */ 569 if (HDA_CONTROLLER_IS_APL(pci)) 570 bxt_reduce_dma_latency(chip); 571 572 if (bus->mlcap != NULL) 573 intel_init_lctl(chip); 574 } 575 576 /* calculate runtime delay from LPIB */ 577 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev, 578 unsigned int pos) 579 { 580 struct snd_pcm_substream *substream = azx_dev->core.substream; 581 int stream = substream->stream; 582 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev); 583 int delay; 584 585 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 586 delay = pos - lpib_pos; 587 else 588 delay = lpib_pos - pos; 589 if (delay < 0) { 590 if (delay >= azx_dev->core.delay_negative_threshold) 591 delay = 0; 592 else 593 delay += azx_dev->core.bufsize; 594 } 595 596 if (delay >= azx_dev->core.period_bytes) { 597 dev_info(chip->card->dev, 598 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n", 599 delay, azx_dev->core.period_bytes); 600 delay = 0; 601 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY; 602 chip->get_delay[stream] = NULL; 603 } 604 605 return bytes_to_frames(substream->runtime, delay); 606 } 607 608 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev); 609 610 /* called from IRQ */ 611 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev) 612 { 613 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 614 int ok; 615 616 ok = azx_position_ok(chip, azx_dev); 617 if (ok == 1) { 618 azx_dev->irq_pending = 0; 619 return ok; 620 } else if (ok == 0) { 621 /* bogus IRQ, process it later */ 622 azx_dev->irq_pending = 1; 623 schedule_work(&hda->irq_pending_work); 624 } 625 return 0; 626 } 627 628 #define display_power(chip, enable) \ 629 snd_hdac_display_power(azx_bus(chip), HDA_CODEC_IDX_CONTROLLER, enable) 630 631 /* 632 * Check whether the current DMA position is acceptable for updating 633 * periods. Returns non-zero if it's OK. 634 * 635 * Many HD-audio controllers appear pretty inaccurate about 636 * the update-IRQ timing. The IRQ is issued before actually the 637 * data is processed. So, we need to process it afterwords in a 638 * workqueue. 639 * 640 * Returns 1 if OK to proceed, 0 for delay handling, -1 for skipping update 641 */ 642 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev) 643 { 644 struct snd_pcm_substream *substream = azx_dev->core.substream; 645 struct snd_pcm_runtime *runtime = substream->runtime; 646 int stream = substream->stream; 647 u32 wallclk; 648 unsigned int pos; 649 snd_pcm_uframes_t hwptr, target; 650 651 /* 652 * The value of the WALLCLK register is always 0 653 * on the Loongson controller, so we return directly. 654 */ 655 if (chip->driver_type == AZX_DRIVER_LOONGSON) 656 return 1; 657 658 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk; 659 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3) 660 return -1; /* bogus (too early) interrupt */ 661 662 if (chip->get_position[stream]) 663 pos = chip->get_position[stream](chip, azx_dev); 664 else { /* use the position buffer as default */ 665 pos = azx_get_pos_posbuf(chip, azx_dev); 666 if (!pos || pos == (u32)-1) { 667 dev_info(chip->card->dev, 668 "Invalid position buffer, using LPIB read method instead.\n"); 669 chip->get_position[stream] = azx_get_pos_lpib; 670 if (chip->get_position[0] == azx_get_pos_lpib && 671 chip->get_position[1] == azx_get_pos_lpib) 672 azx_bus(chip)->use_posbuf = false; 673 pos = azx_get_pos_lpib(chip, azx_dev); 674 chip->get_delay[stream] = NULL; 675 } else { 676 chip->get_position[stream] = azx_get_pos_posbuf; 677 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY) 678 chip->get_delay[stream] = azx_get_delay_from_lpib; 679 } 680 } 681 682 if (pos >= azx_dev->core.bufsize) 683 pos = 0; 684 685 if (WARN_ONCE(!azx_dev->core.period_bytes, 686 "hda-intel: zero azx_dev->period_bytes")) 687 return -1; /* this shouldn't happen! */ 688 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 && 689 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2) 690 /* NG - it's below the first next period boundary */ 691 return chip->bdl_pos_adj ? 0 : -1; 692 azx_dev->core.start_wallclk += wallclk; 693 694 if (azx_dev->core.no_period_wakeup) 695 return 1; /* OK, no need to check period boundary */ 696 697 if (runtime->hw_ptr_base != runtime->hw_ptr_interrupt) 698 return 1; /* OK, already in hwptr updating process */ 699 700 /* check whether the period gets really elapsed */ 701 pos = bytes_to_frames(runtime, pos); 702 hwptr = runtime->hw_ptr_base + pos; 703 if (hwptr < runtime->status->hw_ptr) 704 hwptr += runtime->buffer_size; 705 target = runtime->hw_ptr_interrupt + runtime->period_size; 706 if (hwptr < target) { 707 /* too early wakeup, process it later */ 708 return chip->bdl_pos_adj ? 0 : -1; 709 } 710 711 return 1; /* OK, it's fine */ 712 } 713 714 /* 715 * The work for pending PCM period updates. 716 */ 717 static void azx_irq_pending_work(struct work_struct *work) 718 { 719 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work); 720 struct azx *chip = &hda->chip; 721 struct hdac_bus *bus = azx_bus(chip); 722 struct hdac_stream *s; 723 int pending, ok; 724 725 if (!hda->irq_pending_warned) { 726 dev_info(chip->card->dev, 727 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n", 728 chip->card->number); 729 hda->irq_pending_warned = 1; 730 } 731 732 for (;;) { 733 pending = 0; 734 spin_lock_irq(&bus->reg_lock); 735 list_for_each_entry(s, &bus->stream_list, list) { 736 struct azx_dev *azx_dev = stream_to_azx_dev(s); 737 if (!azx_dev->irq_pending || 738 !s->substream || 739 !s->running) 740 continue; 741 ok = azx_position_ok(chip, azx_dev); 742 if (ok > 0) { 743 azx_dev->irq_pending = 0; 744 spin_unlock(&bus->reg_lock); 745 snd_pcm_period_elapsed(s->substream); 746 spin_lock(&bus->reg_lock); 747 } else if (ok < 0) { 748 pending = 0; /* too early */ 749 } else 750 pending++; 751 } 752 spin_unlock_irq(&bus->reg_lock); 753 if (!pending) 754 return; 755 msleep(1); 756 } 757 } 758 759 /* clear irq_pending flags and assure no on-going workq */ 760 static void azx_clear_irq_pending(struct azx *chip) 761 { 762 struct hdac_bus *bus = azx_bus(chip); 763 struct hdac_stream *s; 764 765 spin_lock_irq(&bus->reg_lock); 766 list_for_each_entry(s, &bus->stream_list, list) { 767 struct azx_dev *azx_dev = stream_to_azx_dev(s); 768 azx_dev->irq_pending = 0; 769 } 770 spin_unlock_irq(&bus->reg_lock); 771 } 772 773 static int azx_acquire_irq(struct azx *chip, int do_disconnect) 774 { 775 struct hdac_bus *bus = azx_bus(chip); 776 int ret; 777 778 if (!chip->msi || pci_alloc_irq_vectors(chip->pci, 1, 1, PCI_IRQ_MSI) < 0) { 779 ret = pci_alloc_irq_vectors(chip->pci, 1, 1, PCI_IRQ_INTX); 780 if (ret < 0) 781 return ret; 782 chip->msi = 0; 783 } 784 785 if (request_irq(chip->pci->irq, azx_interrupt, 786 chip->msi ? 0 : IRQF_SHARED, 787 chip->card->irq_descr, chip)) { 788 dev_err(chip->card->dev, 789 "unable to grab IRQ %d, disabling device\n", 790 chip->pci->irq); 791 if (do_disconnect) 792 snd_card_disconnect(chip->card); 793 return -1; 794 } 795 bus->irq = chip->pci->irq; 796 chip->card->sync_irq = bus->irq; 797 return 0; 798 } 799 800 /* get the current DMA position with correction on VIA chips */ 801 static unsigned int azx_via_get_position(struct azx *chip, 802 struct azx_dev *azx_dev) 803 { 804 unsigned int link_pos, mini_pos, bound_pos; 805 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos; 806 unsigned int fifo_size; 807 808 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev)); 809 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 810 /* Playback, no problem using link position */ 811 return link_pos; 812 } 813 814 /* Capture */ 815 /* For new chipset, 816 * use mod to get the DMA position just like old chipset 817 */ 818 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf); 819 mod_dma_pos %= azx_dev->core.period_bytes; 820 821 fifo_size = azx_stream(azx_dev)->fifo_size; 822 823 if (azx_dev->insufficient) { 824 /* Link position never gather than FIFO size */ 825 if (link_pos <= fifo_size) 826 return 0; 827 828 azx_dev->insufficient = 0; 829 } 830 831 if (link_pos <= fifo_size) 832 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size; 833 else 834 mini_pos = link_pos - fifo_size; 835 836 /* Find nearest previous boudary */ 837 mod_mini_pos = mini_pos % azx_dev->core.period_bytes; 838 mod_link_pos = link_pos % azx_dev->core.period_bytes; 839 if (mod_link_pos >= fifo_size) 840 bound_pos = link_pos - mod_link_pos; 841 else if (mod_dma_pos >= mod_mini_pos) 842 bound_pos = mini_pos - mod_mini_pos; 843 else { 844 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes; 845 if (bound_pos >= azx_dev->core.bufsize) 846 bound_pos = 0; 847 } 848 849 /* Calculate real DMA position we want */ 850 return bound_pos + mod_dma_pos; 851 } 852 853 #define AMD_FIFO_SIZE 32 854 855 /* get the current DMA position with FIFO size correction */ 856 static unsigned int azx_get_pos_fifo(struct azx *chip, struct azx_dev *azx_dev) 857 { 858 struct snd_pcm_substream *substream = azx_dev->core.substream; 859 struct snd_pcm_runtime *runtime = substream->runtime; 860 unsigned int pos, delay; 861 862 pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev)); 863 if (!runtime) 864 return pos; 865 866 runtime->delay = AMD_FIFO_SIZE; 867 delay = frames_to_bytes(runtime, AMD_FIFO_SIZE); 868 if (azx_dev->insufficient) { 869 if (pos < delay) { 870 delay = pos; 871 runtime->delay = bytes_to_frames(runtime, pos); 872 } else { 873 azx_dev->insufficient = 0; 874 } 875 } 876 877 /* correct the DMA position for capture stream */ 878 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { 879 if (pos < delay) 880 pos += azx_dev->core.bufsize; 881 pos -= delay; 882 } 883 884 return pos; 885 } 886 887 static int azx_get_delay_from_fifo(struct azx *chip, struct azx_dev *azx_dev, 888 unsigned int pos) 889 { 890 struct snd_pcm_substream *substream = azx_dev->core.substream; 891 892 /* just read back the calculated value in the above */ 893 return substream->runtime->delay; 894 } 895 896 static void __azx_shutdown_chip(struct azx *chip, bool skip_link_reset) 897 { 898 azx_stop_chip(chip); 899 if (!skip_link_reset) 900 azx_enter_link_reset(chip); 901 azx_clear_irq_pending(chip); 902 display_power(chip, false); 903 } 904 905 static DEFINE_MUTEX(card_list_lock); 906 static LIST_HEAD(card_list); 907 908 static void azx_shutdown_chip(struct azx *chip) 909 { 910 __azx_shutdown_chip(chip, false); 911 } 912 913 static void azx_add_card_list(struct azx *chip) 914 { 915 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 916 mutex_lock(&card_list_lock); 917 list_add(&hda->list, &card_list); 918 mutex_unlock(&card_list_lock); 919 } 920 921 static void azx_del_card_list(struct azx *chip) 922 { 923 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 924 mutex_lock(&card_list_lock); 925 list_del_init(&hda->list); 926 mutex_unlock(&card_list_lock); 927 } 928 929 /* trigger power-save check at writing parameter */ 930 static int __maybe_unused param_set_xint(const char *val, const struct kernel_param *kp) 931 { 932 struct hda_intel *hda; 933 struct azx *chip; 934 int prev = power_save; 935 int ret = param_set_int(val, kp); 936 937 if (ret || prev == power_save) 938 return ret; 939 940 if (pm_blacklist > 0) 941 return 0; 942 943 mutex_lock(&card_list_lock); 944 list_for_each_entry(hda, &card_list, list) { 945 chip = &hda->chip; 946 if (!hda->probe_continued || chip->disabled || 947 hda->runtime_pm_disabled) 948 continue; 949 snd_hda_set_power_save(&chip->bus, power_save * 1000); 950 } 951 mutex_unlock(&card_list_lock); 952 return 0; 953 } 954 955 /* 956 * power management 957 */ 958 static bool azx_is_pm_ready(struct snd_card *card) 959 { 960 struct azx *chip; 961 struct hda_intel *hda; 962 963 if (!card) 964 return false; 965 chip = card->private_data; 966 hda = container_of(chip, struct hda_intel, chip); 967 if (chip->disabled || hda->init_failed || !chip->running) 968 return false; 969 return true; 970 } 971 972 static void __azx_runtime_resume(struct azx *chip) 973 { 974 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 975 struct hdac_bus *bus = azx_bus(chip); 976 struct hda_codec *codec; 977 int status; 978 979 display_power(chip, true); 980 if (hda->need_i915_power) 981 snd_hdac_i915_set_bclk(bus); 982 983 /* Read STATESTS before controller reset */ 984 status = azx_readw(chip, STATESTS); 985 986 azx_init_pci(chip); 987 hda_intel_init_chip(chip, true); 988 989 /* Avoid codec resume if runtime resume is for system suspend */ 990 if (!chip->pm_prepared) { 991 list_for_each_codec(codec, &chip->bus) { 992 if (codec->relaxed_resume) 993 continue; 994 995 if (codec->forced_resume || (status & (1 << codec->addr))) 996 pm_request_resume(hda_codec_dev(codec)); 997 } 998 } 999 1000 /* power down again for link-controlled chips */ 1001 if (!hda->need_i915_power) 1002 display_power(chip, false); 1003 } 1004 1005 static int azx_prepare(struct device *dev) 1006 { 1007 struct snd_card *card = dev_get_drvdata(dev); 1008 struct azx *chip; 1009 1010 if (!azx_is_pm_ready(card)) 1011 return 0; 1012 1013 chip = card->private_data; 1014 chip->pm_prepared = 1; 1015 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 1016 1017 flush_work(&azx_bus(chip)->unsol_work); 1018 1019 /* HDA controller always requires different WAKEEN for runtime suspend 1020 * and system suspend, so don't use direct-complete here. 1021 */ 1022 return 0; 1023 } 1024 1025 static void azx_complete(struct device *dev) 1026 { 1027 struct snd_card *card = dev_get_drvdata(dev); 1028 struct azx *chip; 1029 1030 if (!azx_is_pm_ready(card)) 1031 return; 1032 1033 chip = card->private_data; 1034 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 1035 chip->pm_prepared = 0; 1036 } 1037 1038 static int azx_suspend(struct device *dev) 1039 { 1040 struct snd_card *card = dev_get_drvdata(dev); 1041 struct azx *chip; 1042 1043 if (!azx_is_pm_ready(card)) 1044 return 0; 1045 1046 chip = card->private_data; 1047 azx_shutdown_chip(chip); 1048 1049 trace_azx_suspend(chip); 1050 return 0; 1051 } 1052 1053 static int __maybe_unused azx_resume(struct device *dev) 1054 { 1055 struct snd_card *card = dev_get_drvdata(dev); 1056 struct azx *chip; 1057 1058 if (!azx_is_pm_ready(card)) 1059 return 0; 1060 1061 chip = card->private_data; 1062 1063 __azx_runtime_resume(chip); 1064 1065 trace_azx_resume(chip); 1066 return 0; 1067 } 1068 1069 /* put codec down to D3 at hibernation for Intel SKL+; 1070 * otherwise BIOS may still access the codec and screw up the driver 1071 */ 1072 static int azx_freeze_noirq(struct device *dev) 1073 { 1074 struct snd_card *card = dev_get_drvdata(dev); 1075 struct azx *chip = card->private_data; 1076 struct pci_dev *pci = to_pci_dev(dev); 1077 1078 if (!azx_is_pm_ready(card)) 1079 return 0; 1080 if (chip->driver_type == AZX_DRIVER_SKL) 1081 pci_set_power_state(pci, PCI_D3hot); 1082 1083 return 0; 1084 } 1085 1086 static int azx_thaw_noirq(struct device *dev) 1087 { 1088 struct snd_card *card = dev_get_drvdata(dev); 1089 struct azx *chip = card->private_data; 1090 struct pci_dev *pci = to_pci_dev(dev); 1091 1092 if (!azx_is_pm_ready(card)) 1093 return 0; 1094 if (chip->driver_type == AZX_DRIVER_SKL) 1095 pci_set_power_state(pci, PCI_D0); 1096 1097 return 0; 1098 } 1099 1100 static int __maybe_unused azx_runtime_suspend(struct device *dev) 1101 { 1102 struct snd_card *card = dev_get_drvdata(dev); 1103 struct azx *chip; 1104 1105 if (!azx_is_pm_ready(card)) 1106 return 0; 1107 chip = card->private_data; 1108 1109 /* enable controller wake up event */ 1110 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) | STATESTS_INT_MASK); 1111 1112 azx_shutdown_chip(chip); 1113 trace_azx_runtime_suspend(chip); 1114 return 0; 1115 } 1116 1117 static int __maybe_unused azx_runtime_resume(struct device *dev) 1118 { 1119 struct snd_card *card = dev_get_drvdata(dev); 1120 struct azx *chip; 1121 1122 if (!azx_is_pm_ready(card)) 1123 return 0; 1124 chip = card->private_data; 1125 __azx_runtime_resume(chip); 1126 1127 /* disable controller Wake Up event*/ 1128 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) & ~STATESTS_INT_MASK); 1129 1130 trace_azx_runtime_resume(chip); 1131 return 0; 1132 } 1133 1134 static int __maybe_unused azx_runtime_idle(struct device *dev) 1135 { 1136 struct snd_card *card = dev_get_drvdata(dev); 1137 struct azx *chip; 1138 struct hda_intel *hda; 1139 1140 if (!card) 1141 return 0; 1142 1143 chip = card->private_data; 1144 hda = container_of(chip, struct hda_intel, chip); 1145 if (chip->disabled || hda->init_failed) 1146 return 0; 1147 1148 if (!power_save_controller || !azx_has_pm_runtime(chip) || 1149 azx_bus(chip)->codec_powered || !chip->running) 1150 return -EBUSY; 1151 1152 /* ELD notification gets broken when HD-audio bus is off */ 1153 if (needs_eld_notify_link(chip)) 1154 return -EBUSY; 1155 1156 return 0; 1157 } 1158 1159 static const struct dev_pm_ops azx_pm = { 1160 SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume) 1161 .prepare = pm_sleep_ptr(azx_prepare), 1162 .complete = pm_sleep_ptr(azx_complete), 1163 .freeze_noirq = pm_sleep_ptr(azx_freeze_noirq), 1164 .thaw_noirq = pm_sleep_ptr(azx_thaw_noirq), 1165 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle) 1166 }; 1167 1168 1169 static int azx_probe_continue(struct azx *chip); 1170 1171 #ifdef SUPPORT_VGA_SWITCHEROO 1172 static struct pci_dev *get_bound_vga(struct pci_dev *pci); 1173 1174 static void azx_vs_set_state(struct pci_dev *pci, 1175 enum vga_switcheroo_state state) 1176 { 1177 struct snd_card *card = pci_get_drvdata(pci); 1178 struct azx *chip = card->private_data; 1179 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1180 struct hda_codec *codec; 1181 bool disabled; 1182 1183 wait_for_completion(&hda->probe_wait); 1184 if (hda->init_failed) 1185 return; 1186 1187 disabled = (state == VGA_SWITCHEROO_OFF); 1188 if (chip->disabled == disabled) 1189 return; 1190 1191 if (!hda->probe_continued) { 1192 chip->disabled = disabled; 1193 if (!disabled) { 1194 dev_info(chip->card->dev, 1195 "Start delayed initialization\n"); 1196 if (azx_probe_continue(chip) < 0) 1197 dev_err(chip->card->dev, "initialization error\n"); 1198 } 1199 } else { 1200 dev_info(chip->card->dev, "%s via vga_switcheroo\n", 1201 disabled ? "Disabling" : "Enabling"); 1202 if (disabled) { 1203 list_for_each_codec(codec, &chip->bus) { 1204 pm_runtime_suspend(hda_codec_dev(codec)); 1205 pm_runtime_disable(hda_codec_dev(codec)); 1206 } 1207 pm_runtime_suspend(card->dev); 1208 pm_runtime_disable(card->dev); 1209 /* when we get suspended by vga_switcheroo we end up in D3cold, 1210 * however we have no ACPI handle, so pci/acpi can't put us there, 1211 * put ourselves there */ 1212 pci->current_state = PCI_D3cold; 1213 chip->disabled = true; 1214 if (snd_hda_lock_devices(&chip->bus)) 1215 dev_warn(chip->card->dev, 1216 "Cannot lock devices!\n"); 1217 } else { 1218 snd_hda_unlock_devices(&chip->bus); 1219 chip->disabled = false; 1220 pm_runtime_enable(card->dev); 1221 list_for_each_codec(codec, &chip->bus) { 1222 pm_runtime_enable(hda_codec_dev(codec)); 1223 pm_runtime_resume(hda_codec_dev(codec)); 1224 } 1225 } 1226 } 1227 } 1228 1229 static bool azx_vs_can_switch(struct pci_dev *pci) 1230 { 1231 struct snd_card *card = pci_get_drvdata(pci); 1232 struct azx *chip = card->private_data; 1233 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1234 1235 wait_for_completion(&hda->probe_wait); 1236 if (hda->init_failed) 1237 return false; 1238 if (chip->disabled || !hda->probe_continued) 1239 return true; 1240 if (snd_hda_lock_devices(&chip->bus)) 1241 return false; 1242 snd_hda_unlock_devices(&chip->bus); 1243 return true; 1244 } 1245 1246 /* 1247 * The discrete GPU cannot power down unless the HDA controller runtime 1248 * suspends, so activate runtime PM on codecs even if power_save == 0. 1249 */ 1250 static void setup_vga_switcheroo_runtime_pm(struct azx *chip) 1251 { 1252 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1253 struct hda_codec *codec; 1254 1255 if (hda->use_vga_switcheroo && !needs_eld_notify_link(chip)) { 1256 list_for_each_codec(codec, &chip->bus) 1257 codec->auto_runtime_pm = 1; 1258 /* reset the power save setup */ 1259 if (chip->running) 1260 set_default_power_save(chip); 1261 } 1262 } 1263 1264 static void azx_vs_gpu_bound(struct pci_dev *pci, 1265 enum vga_switcheroo_client_id client_id) 1266 { 1267 struct snd_card *card = pci_get_drvdata(pci); 1268 struct azx *chip = card->private_data; 1269 1270 if (client_id == VGA_SWITCHEROO_DIS) 1271 chip->bus.keep_power = 0; 1272 setup_vga_switcheroo_runtime_pm(chip); 1273 } 1274 1275 static void init_vga_switcheroo(struct azx *chip) 1276 { 1277 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1278 struct pci_dev *p = get_bound_vga(chip->pci); 1279 struct pci_dev *parent; 1280 if (p) { 1281 dev_info(chip->card->dev, 1282 "Handle vga_switcheroo audio client\n"); 1283 hda->use_vga_switcheroo = 1; 1284 1285 /* cleared in either gpu_bound op or codec probe, or when its 1286 * upstream port has _PR3 (i.e. dGPU). 1287 */ 1288 parent = pci_upstream_bridge(p); 1289 chip->bus.keep_power = parent ? !pci_pr3_present(parent) : 1; 1290 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME; 1291 pci_dev_put(p); 1292 } 1293 } 1294 1295 static const struct vga_switcheroo_client_ops azx_vs_ops = { 1296 .set_gpu_state = azx_vs_set_state, 1297 .can_switch = azx_vs_can_switch, 1298 .gpu_bound = azx_vs_gpu_bound, 1299 }; 1300 1301 static int register_vga_switcheroo(struct azx *chip) 1302 { 1303 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1304 struct pci_dev *p; 1305 int err; 1306 1307 if (!hda->use_vga_switcheroo) 1308 return 0; 1309 1310 p = get_bound_vga(chip->pci); 1311 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p); 1312 pci_dev_put(p); 1313 1314 if (err < 0) 1315 return err; 1316 hda->vga_switcheroo_registered = 1; 1317 1318 return 0; 1319 } 1320 #else 1321 #define init_vga_switcheroo(chip) /* NOP */ 1322 #define register_vga_switcheroo(chip) 0 1323 #define check_hdmi_disabled(pci) false 1324 #define setup_vga_switcheroo_runtime_pm(chip) /* NOP */ 1325 #endif /* SUPPORT_VGA_SWITCHER */ 1326 1327 /* 1328 * destructor 1329 */ 1330 static void azx_free(struct azx *chip) 1331 { 1332 struct pci_dev *pci = chip->pci; 1333 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1334 struct hdac_bus *bus = azx_bus(chip); 1335 1336 if (hda->freed) 1337 return; 1338 1339 if (azx_has_pm_runtime(chip) && chip->running) { 1340 pm_runtime_get_noresume(&pci->dev); 1341 pm_runtime_forbid(&pci->dev); 1342 pm_runtime_dont_use_autosuspend(&pci->dev); 1343 } 1344 1345 chip->running = 0; 1346 1347 azx_del_card_list(chip); 1348 1349 hda->init_failed = 1; /* to be sure */ 1350 complete_all(&hda->probe_wait); 1351 1352 if (use_vga_switcheroo(hda)) { 1353 if (chip->disabled && hda->probe_continued) 1354 snd_hda_unlock_devices(&chip->bus); 1355 if (hda->vga_switcheroo_registered) 1356 vga_switcheroo_unregister_client(chip->pci); 1357 } 1358 1359 if (bus->chip_init) { 1360 azx_clear_irq_pending(chip); 1361 azx_stop_all_streams(chip); 1362 azx_stop_chip(chip); 1363 } 1364 1365 if (bus->irq >= 0) 1366 free_irq(bus->irq, (void*)chip); 1367 1368 azx_free_stream_pages(chip); 1369 azx_free_streams(chip); 1370 snd_hdac_bus_exit(bus); 1371 1372 #ifdef CONFIG_SND_HDA_PATCH_LOADER 1373 release_firmware(chip->fw); 1374 #endif 1375 display_power(chip, false); 1376 1377 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) 1378 snd_hdac_i915_exit(bus); 1379 1380 hda->freed = 1; 1381 } 1382 1383 static int azx_dev_disconnect(struct snd_device *device) 1384 { 1385 struct azx *chip = device->device_data; 1386 struct hdac_bus *bus = azx_bus(chip); 1387 1388 chip->bus.shutdown = 1; 1389 cancel_work_sync(&bus->unsol_work); 1390 1391 return 0; 1392 } 1393 1394 static int azx_dev_free(struct snd_device *device) 1395 { 1396 azx_free(device->device_data); 1397 return 0; 1398 } 1399 1400 #ifdef SUPPORT_VGA_SWITCHEROO 1401 #ifdef CONFIG_ACPI 1402 /* ATPX is in the integrated GPU's namespace */ 1403 static bool atpx_present(void) 1404 { 1405 struct pci_dev *pdev = NULL; 1406 acpi_handle dhandle, atpx_handle; 1407 acpi_status status; 1408 1409 while ((pdev = pci_get_base_class(PCI_BASE_CLASS_DISPLAY, pdev))) { 1410 if ((pdev->class != PCI_CLASS_DISPLAY_VGA << 8) && 1411 (pdev->class != PCI_CLASS_DISPLAY_OTHER << 8)) 1412 continue; 1413 1414 dhandle = ACPI_HANDLE(&pdev->dev); 1415 if (dhandle) { 1416 status = acpi_get_handle(dhandle, "ATPX", &atpx_handle); 1417 if (ACPI_SUCCESS(status)) { 1418 pci_dev_put(pdev); 1419 return true; 1420 } 1421 } 1422 } 1423 return false; 1424 } 1425 #else 1426 static bool atpx_present(void) 1427 { 1428 return false; 1429 } 1430 #endif 1431 1432 /* 1433 * Check of disabled HDMI controller by vga_switcheroo 1434 */ 1435 static struct pci_dev *get_bound_vga(struct pci_dev *pci) 1436 { 1437 struct pci_dev *p; 1438 1439 /* check only discrete GPU */ 1440 switch (pci->vendor) { 1441 case PCI_VENDOR_ID_ATI: 1442 case PCI_VENDOR_ID_AMD: 1443 if (pci->devfn == 1) { 1444 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus), 1445 pci->bus->number, 0); 1446 if (p) { 1447 /* ATPX is in the integrated GPU's ACPI namespace 1448 * rather than the dGPU's namespace. However, 1449 * the dGPU is the one who is involved in 1450 * vgaswitcheroo. 1451 */ 1452 if (((p->class >> 16) == PCI_BASE_CLASS_DISPLAY) && 1453 (atpx_present() || apple_gmux_detect(NULL, NULL))) 1454 return p; 1455 pci_dev_put(p); 1456 } 1457 } 1458 break; 1459 case PCI_VENDOR_ID_NVIDIA: 1460 if (pci->devfn == 1) { 1461 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus), 1462 pci->bus->number, 0); 1463 if (p) { 1464 if ((p->class >> 16) == PCI_BASE_CLASS_DISPLAY) 1465 return p; 1466 pci_dev_put(p); 1467 } 1468 } 1469 break; 1470 } 1471 return NULL; 1472 } 1473 1474 static bool check_hdmi_disabled(struct pci_dev *pci) 1475 { 1476 bool vga_inactive = false; 1477 struct pci_dev *p = get_bound_vga(pci); 1478 1479 if (p) { 1480 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF) 1481 vga_inactive = true; 1482 pci_dev_put(p); 1483 } 1484 return vga_inactive; 1485 } 1486 #endif /* SUPPORT_VGA_SWITCHEROO */ 1487 1488 /* 1489 * allow/deny-listing for position_fix 1490 */ 1491 static const struct snd_pci_quirk position_fix_list[] = { 1492 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB), 1493 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB), 1494 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB), 1495 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB), 1496 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB), 1497 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB), 1498 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB), 1499 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB), 1500 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB), 1501 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB), 1502 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB), 1503 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB), 1504 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB), 1505 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB), 1506 {} 1507 }; 1508 1509 static int check_position_fix(struct azx *chip, int fix) 1510 { 1511 const struct snd_pci_quirk *q; 1512 1513 switch (fix) { 1514 case POS_FIX_AUTO: 1515 case POS_FIX_LPIB: 1516 case POS_FIX_POSBUF: 1517 case POS_FIX_VIACOMBO: 1518 case POS_FIX_COMBO: 1519 case POS_FIX_SKL: 1520 case POS_FIX_FIFO: 1521 return fix; 1522 } 1523 1524 q = snd_pci_quirk_lookup(chip->pci, position_fix_list); 1525 if (q) { 1526 dev_info(chip->card->dev, 1527 "position_fix set to %d for device %04x:%04x\n", 1528 q->value, q->subvendor, q->subdevice); 1529 return q->value; 1530 } 1531 1532 /* Check VIA/ATI HD Audio Controller exist */ 1533 if (chip->driver_type == AZX_DRIVER_VIA) { 1534 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n"); 1535 return POS_FIX_VIACOMBO; 1536 } 1537 if (chip->driver_caps & AZX_DCAPS_AMD_WORKAROUND) { 1538 dev_dbg(chip->card->dev, "Using FIFO position fix\n"); 1539 return POS_FIX_FIFO; 1540 } 1541 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) { 1542 dev_dbg(chip->card->dev, "Using LPIB position fix\n"); 1543 return POS_FIX_LPIB; 1544 } 1545 if (chip->driver_type == AZX_DRIVER_SKL) { 1546 dev_dbg(chip->card->dev, "Using SKL position fix\n"); 1547 return POS_FIX_SKL; 1548 } 1549 return POS_FIX_AUTO; 1550 } 1551 1552 static void assign_position_fix(struct azx *chip, int fix) 1553 { 1554 static const azx_get_pos_callback_t callbacks[] = { 1555 [POS_FIX_AUTO] = NULL, 1556 [POS_FIX_LPIB] = azx_get_pos_lpib, 1557 [POS_FIX_POSBUF] = azx_get_pos_posbuf, 1558 [POS_FIX_VIACOMBO] = azx_via_get_position, 1559 [POS_FIX_COMBO] = azx_get_pos_lpib, 1560 [POS_FIX_SKL] = azx_get_pos_posbuf, 1561 [POS_FIX_FIFO] = azx_get_pos_fifo, 1562 }; 1563 1564 chip->get_position[0] = chip->get_position[1] = callbacks[fix]; 1565 1566 /* combo mode uses LPIB only for playback */ 1567 if (fix == POS_FIX_COMBO) 1568 chip->get_position[1] = NULL; 1569 1570 if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) && 1571 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) { 1572 chip->get_delay[0] = chip->get_delay[1] = 1573 azx_get_delay_from_lpib; 1574 } 1575 1576 if (fix == POS_FIX_FIFO) 1577 chip->get_delay[0] = chip->get_delay[1] = 1578 azx_get_delay_from_fifo; 1579 } 1580 1581 /* 1582 * deny-lists for probe_mask 1583 */ 1584 static const struct snd_pci_quirk probe_mask_list[] = { 1585 /* Thinkpad often breaks the controller communication when accessing 1586 * to the non-working (or non-existing) modem codec slot. 1587 */ 1588 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01), 1589 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01), 1590 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01), 1591 /* broken BIOS */ 1592 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01), 1593 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */ 1594 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01), 1595 /* forced codec slots */ 1596 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103), 1597 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103), 1598 SND_PCI_QUIRK(0x1558, 0x0351, "Schenker Dock 15", 0x105), 1599 /* WinFast VP200 H (Teradici) user reported broken communication */ 1600 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101), 1601 {} 1602 }; 1603 1604 #define AZX_FORCE_CODEC_MASK 0x100 1605 1606 static void check_probe_mask(struct azx *chip, int dev) 1607 { 1608 const struct snd_pci_quirk *q; 1609 1610 chip->codec_probe_mask = probe_mask[dev]; 1611 if (chip->codec_probe_mask == -1) { 1612 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list); 1613 if (q) { 1614 dev_info(chip->card->dev, 1615 "probe_mask set to 0x%x for device %04x:%04x\n", 1616 q->value, q->subvendor, q->subdevice); 1617 chip->codec_probe_mask = q->value; 1618 } 1619 } 1620 1621 /* check forced option */ 1622 if (chip->codec_probe_mask != -1 && 1623 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) { 1624 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff; 1625 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n", 1626 (int)azx_bus(chip)->codec_mask); 1627 } 1628 } 1629 1630 /* 1631 * allow/deny-list for enable_msi 1632 */ 1633 static const struct snd_pci_quirk msi_deny_list[] = { 1634 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */ 1635 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */ 1636 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */ 1637 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */ 1638 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */ 1639 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */ 1640 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */ 1641 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */ 1642 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */ 1643 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */ 1644 {} 1645 }; 1646 1647 static void check_msi(struct azx *chip) 1648 { 1649 const struct snd_pci_quirk *q; 1650 1651 if (enable_msi >= 0) { 1652 chip->msi = !!enable_msi; 1653 return; 1654 } 1655 chip->msi = 1; /* enable MSI as default */ 1656 q = snd_pci_quirk_lookup(chip->pci, msi_deny_list); 1657 if (q) { 1658 dev_info(chip->card->dev, 1659 "msi for device %04x:%04x set to %d\n", 1660 q->subvendor, q->subdevice, q->value); 1661 chip->msi = q->value; 1662 return; 1663 } 1664 1665 /* NVidia chipsets seem to cause troubles with MSI */ 1666 if (chip->driver_caps & AZX_DCAPS_NO_MSI) { 1667 dev_info(chip->card->dev, "Disabling MSI\n"); 1668 chip->msi = 0; 1669 } 1670 } 1671 1672 /* check the snoop mode availability */ 1673 static void azx_check_snoop_available(struct azx *chip) 1674 { 1675 int snoop = hda_snoop; 1676 1677 if (snoop >= 0) { 1678 dev_info(chip->card->dev, "Force to %s mode by module option\n", 1679 snoop ? "snoop" : "non-snoop"); 1680 chip->snoop = snoop; 1681 chip->uc_buffer = !snoop; 1682 return; 1683 } 1684 1685 snoop = true; 1686 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE && 1687 chip->driver_type == AZX_DRIVER_VIA) { 1688 /* force to non-snoop mode for a new VIA controller 1689 * when BIOS is set 1690 */ 1691 u8 val; 1692 pci_read_config_byte(chip->pci, 0x42, &val); 1693 if (!(val & 0x80) && (chip->pci->revision == 0x30 || 1694 chip->pci->revision == 0x20)) 1695 snoop = false; 1696 } 1697 1698 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF) 1699 snoop = false; 1700 1701 chip->snoop = snoop; 1702 if (!snoop) { 1703 dev_info(chip->card->dev, "Force to non-snoop mode\n"); 1704 /* C-Media requires non-cached pages only for CORB/RIRB */ 1705 if (chip->driver_type != AZX_DRIVER_CMEDIA) 1706 chip->uc_buffer = true; 1707 } 1708 } 1709 1710 static void azx_probe_work(struct work_struct *work) 1711 { 1712 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work.work); 1713 azx_probe_continue(&hda->chip); 1714 } 1715 1716 static int default_bdl_pos_adj(struct azx *chip) 1717 { 1718 /* some exceptions: Atoms seem problematic with value 1 */ 1719 if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) { 1720 switch (chip->pci->device) { 1721 case PCI_DEVICE_ID_INTEL_HDA_BYT: 1722 case PCI_DEVICE_ID_INTEL_HDA_BSW: 1723 return 32; 1724 case PCI_DEVICE_ID_INTEL_HDA_APL: 1725 return 64; 1726 } 1727 } 1728 1729 switch (chip->driver_type) { 1730 /* 1731 * increase the bdl size for Glenfly Gpus for hardware 1732 * limitation on hdac interrupt interval 1733 */ 1734 case AZX_DRIVER_GFHDMI: 1735 return 128; 1736 case AZX_DRIVER_ICH: 1737 case AZX_DRIVER_PCH: 1738 return 1; 1739 default: 1740 return 32; 1741 } 1742 } 1743 1744 /* 1745 * constructor 1746 */ 1747 static const struct hda_controller_ops pci_hda_ops; 1748 1749 static int azx_create(struct snd_card *card, struct pci_dev *pci, 1750 int dev, unsigned int driver_caps, 1751 struct azx **rchip) 1752 { 1753 static const struct snd_device_ops ops = { 1754 .dev_disconnect = azx_dev_disconnect, 1755 .dev_free = azx_dev_free, 1756 }; 1757 struct hda_intel *hda; 1758 struct azx *chip; 1759 int err; 1760 1761 *rchip = NULL; 1762 1763 err = pcim_enable_device(pci); 1764 if (err < 0) 1765 return err; 1766 1767 hda = devm_kzalloc(&pci->dev, sizeof(*hda), GFP_KERNEL); 1768 if (!hda) 1769 return -ENOMEM; 1770 1771 chip = &hda->chip; 1772 mutex_init(&chip->open_mutex); 1773 chip->card = card; 1774 chip->pci = pci; 1775 chip->ops = &pci_hda_ops; 1776 chip->driver_caps = driver_caps; 1777 chip->driver_type = driver_caps & 0xff; 1778 check_msi(chip); 1779 chip->dev_index = dev; 1780 if (jackpoll_ms[dev] >= 50 && jackpoll_ms[dev] <= 60000) 1781 chip->jackpoll_interval = msecs_to_jiffies(jackpoll_ms[dev]); 1782 INIT_LIST_HEAD(&chip->pcm_list); 1783 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work); 1784 INIT_LIST_HEAD(&hda->list); 1785 init_vga_switcheroo(chip); 1786 init_completion(&hda->probe_wait); 1787 1788 assign_position_fix(chip, check_position_fix(chip, position_fix[dev])); 1789 1790 if (single_cmd < 0) /* allow fallback to single_cmd at errors */ 1791 chip->fallback_to_single_cmd = 1; 1792 else /* explicitly set to single_cmd or not */ 1793 chip->single_cmd = single_cmd; 1794 1795 azx_check_snoop_available(chip); 1796 1797 if (bdl_pos_adj[dev] < 0) 1798 chip->bdl_pos_adj = default_bdl_pos_adj(chip); 1799 else 1800 chip->bdl_pos_adj = bdl_pos_adj[dev]; 1801 1802 err = azx_bus_init(chip, model[dev]); 1803 if (err < 0) 1804 return err; 1805 1806 /* use the non-cached pages in non-snoop mode */ 1807 if (!azx_snoop(chip)) 1808 azx_bus(chip)->dma_type = SNDRV_DMA_TYPE_DEV_WC; 1809 1810 if (chip->driver_type == AZX_DRIVER_NVIDIA) { 1811 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n"); 1812 chip->bus.core.needs_damn_long_delay = 1; 1813 } 1814 1815 check_probe_mask(chip, dev); 1816 1817 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); 1818 if (err < 0) { 1819 dev_err(card->dev, "Error creating device [card]!\n"); 1820 azx_free(chip); 1821 return err; 1822 } 1823 1824 /* continue probing in work context as may trigger request module */ 1825 INIT_DELAYED_WORK(&hda->probe_work, azx_probe_work); 1826 1827 *rchip = chip; 1828 1829 return 0; 1830 } 1831 1832 static int azx_first_init(struct azx *chip) 1833 { 1834 int dev = chip->dev_index; 1835 struct pci_dev *pci = chip->pci; 1836 struct snd_card *card = chip->card; 1837 struct hdac_bus *bus = azx_bus(chip); 1838 int err; 1839 unsigned short gcap; 1840 unsigned int dma_bits = 64; 1841 1842 #if BITS_PER_LONG != 64 1843 /* Fix up base address on ULI M5461 */ 1844 if (chip->driver_type == AZX_DRIVER_ULI) { 1845 u16 tmp3; 1846 pci_read_config_word(pci, 0x40, &tmp3); 1847 pci_write_config_word(pci, 0x40, tmp3 | 0x10); 1848 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0); 1849 } 1850 #endif 1851 /* 1852 * Fix response write request not synced to memory when handle 1853 * hdac interrupt on Glenfly Gpus 1854 */ 1855 if (chip->driver_type == AZX_DRIVER_GFHDMI) 1856 bus->polling_mode = 1; 1857 1858 if (chip->driver_type == AZX_DRIVER_LOONGSON) { 1859 bus->polling_mode = 1; 1860 bus->not_use_interrupts = 1; 1861 bus->access_sdnctl_in_dword = 1; 1862 if (!chip->jackpoll_interval) 1863 chip->jackpoll_interval = msecs_to_jiffies(1500); 1864 } 1865 1866 err = pcim_iomap_regions(pci, 1 << 0, "ICH HD audio"); 1867 if (err < 0) 1868 return err; 1869 1870 bus->addr = pci_resource_start(pci, 0); 1871 bus->remap_addr = pcim_iomap_table(pci)[0]; 1872 1873 if (chip->driver_type == AZX_DRIVER_SKL) 1874 snd_hdac_bus_parse_capabilities(bus); 1875 1876 /* 1877 * Some Intel CPUs has always running timer (ART) feature and 1878 * controller may have Global time sync reporting capability, so 1879 * check both of these before declaring synchronized time reporting 1880 * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME 1881 */ 1882 chip->gts_present = false; 1883 1884 #ifdef CONFIG_X86 1885 if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART)) 1886 chip->gts_present = true; 1887 #endif 1888 1889 if (chip->msi && chip->driver_caps & AZX_DCAPS_NO_MSI64) { 1890 dev_dbg(card->dev, "Disabling 64bit MSI\n"); 1891 pci->no_64bit_msi = true; 1892 } 1893 1894 pci_set_master(pci); 1895 1896 gcap = azx_readw(chip, GCAP); 1897 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap); 1898 1899 /* AMD devices support 40 or 48bit DMA, take the safe one */ 1900 if (chip->pci->vendor == PCI_VENDOR_ID_AMD) 1901 dma_bits = 40; 1902 1903 /* disable SB600 64bit support for safety */ 1904 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) { 1905 struct pci_dev *p_smbus; 1906 dma_bits = 40; 1907 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI, 1908 PCI_DEVICE_ID_ATI_SBX00_SMBUS, 1909 NULL); 1910 if (p_smbus) { 1911 if (p_smbus->revision < 0x30) 1912 gcap &= ~AZX_GCAP_64OK; 1913 pci_dev_put(p_smbus); 1914 } 1915 } 1916 1917 /* NVidia hardware normally only supports up to 40 bits of DMA */ 1918 if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA) 1919 dma_bits = 40; 1920 1921 /* disable 64bit DMA address on some devices */ 1922 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) { 1923 dev_dbg(card->dev, "Disabling 64bit DMA\n"); 1924 gcap &= ~AZX_GCAP_64OK; 1925 } 1926 1927 /* disable buffer size rounding to 128-byte multiples if supported */ 1928 if (align_buffer_size >= 0) 1929 chip->align_buffer_size = !!align_buffer_size; 1930 else { 1931 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE) 1932 chip->align_buffer_size = 0; 1933 else 1934 chip->align_buffer_size = 1; 1935 } 1936 1937 /* allow 64bit DMA address if supported by H/W */ 1938 if (!(gcap & AZX_GCAP_64OK)) 1939 dma_bits = 32; 1940 if (dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(dma_bits))) 1941 dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(32)); 1942 dma_set_max_seg_size(&pci->dev, UINT_MAX); 1943 1944 /* read number of streams from GCAP register instead of using 1945 * hardcoded value 1946 */ 1947 chip->capture_streams = (gcap >> 8) & 0x0f; 1948 chip->playback_streams = (gcap >> 12) & 0x0f; 1949 if (!chip->playback_streams && !chip->capture_streams) { 1950 /* gcap didn't give any info, switching to old method */ 1951 1952 switch (chip->driver_type) { 1953 case AZX_DRIVER_ULI: 1954 chip->playback_streams = ULI_NUM_PLAYBACK; 1955 chip->capture_streams = ULI_NUM_CAPTURE; 1956 break; 1957 case AZX_DRIVER_ATIHDMI: 1958 case AZX_DRIVER_ATIHDMI_NS: 1959 chip->playback_streams = ATIHDMI_NUM_PLAYBACK; 1960 chip->capture_streams = ATIHDMI_NUM_CAPTURE; 1961 break; 1962 case AZX_DRIVER_GFHDMI: 1963 case AZX_DRIVER_GENERIC: 1964 default: 1965 chip->playback_streams = ICH6_NUM_PLAYBACK; 1966 chip->capture_streams = ICH6_NUM_CAPTURE; 1967 break; 1968 } 1969 } 1970 chip->capture_index_offset = 0; 1971 chip->playback_index_offset = chip->capture_streams; 1972 chip->num_streams = chip->playback_streams + chip->capture_streams; 1973 1974 /* sanity check for the SDxCTL.STRM field overflow */ 1975 if (chip->num_streams > 15 && 1976 (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) { 1977 dev_warn(chip->card->dev, "number of I/O streams is %d, " 1978 "forcing separate stream tags", chip->num_streams); 1979 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG; 1980 } 1981 1982 /* initialize streams */ 1983 err = azx_init_streams(chip); 1984 if (err < 0) 1985 return err; 1986 1987 err = azx_alloc_stream_pages(chip); 1988 if (err < 0) 1989 return err; 1990 1991 /* initialize chip */ 1992 azx_init_pci(chip); 1993 1994 snd_hdac_i915_set_bclk(bus); 1995 1996 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0); 1997 1998 /* codec detection */ 1999 if (!azx_bus(chip)->codec_mask) { 2000 dev_err(card->dev, "no codecs found!\n"); 2001 /* keep running the rest for the runtime PM */ 2002 } 2003 2004 if (azx_acquire_irq(chip, 0) < 0) 2005 return -EBUSY; 2006 2007 strcpy(card->driver, "HDA-Intel"); 2008 strscpy(card->shortname, driver_short_names[chip->driver_type], 2009 sizeof(card->shortname)); 2010 snprintf(card->longname, sizeof(card->longname), 2011 "%s at 0x%lx irq %i", 2012 card->shortname, bus->addr, bus->irq); 2013 2014 return 0; 2015 } 2016 2017 #ifdef CONFIG_SND_HDA_PATCH_LOADER 2018 /* callback from request_firmware_nowait() */ 2019 static void azx_firmware_cb(const struct firmware *fw, void *context) 2020 { 2021 struct snd_card *card = context; 2022 struct azx *chip = card->private_data; 2023 2024 if (fw) 2025 chip->fw = fw; 2026 else 2027 dev_err(card->dev, "Cannot load firmware, continue without patching\n"); 2028 if (!chip->disabled) { 2029 /* continue probing */ 2030 azx_probe_continue(chip); 2031 } 2032 } 2033 #endif 2034 2035 static int disable_msi_reset_irq(struct azx *chip) 2036 { 2037 struct hdac_bus *bus = azx_bus(chip); 2038 int err; 2039 2040 free_irq(bus->irq, chip); 2041 bus->irq = -1; 2042 chip->card->sync_irq = -1; 2043 pci_free_irq_vectors(chip->pci); 2044 chip->msi = 0; 2045 err = azx_acquire_irq(chip, 1); 2046 if (err < 0) 2047 return err; 2048 2049 return 0; 2050 } 2051 2052 /* Denylist for skipping the whole probe: 2053 * some HD-audio PCI entries are exposed without any codecs, and such devices 2054 * should be ignored from the beginning. 2055 */ 2056 static const struct pci_device_id driver_denylist[] = { 2057 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1043, 0x874f) }, /* ASUS ROG Zenith II / Strix */ 2058 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb59) }, /* MSI TRX40 Creator */ 2059 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb60) }, /* MSI TRX40 */ 2060 { PCI_DEVICE_SUB(0x1022, 0x15e3, 0x1022, 0xd601) }, /* ASRock X670E Taichi */ 2061 {} 2062 }; 2063 2064 static const struct hda_controller_ops pci_hda_ops = { 2065 .disable_msi_reset_irq = disable_msi_reset_irq, 2066 .position_check = azx_position_check, 2067 }; 2068 2069 static DECLARE_BITMAP(probed_devs, SNDRV_CARDS); 2070 2071 static int azx_probe(struct pci_dev *pci, 2072 const struct pci_device_id *pci_id) 2073 { 2074 struct snd_card *card; 2075 struct hda_intel *hda; 2076 struct azx *chip; 2077 bool schedule_probe; 2078 int dev; 2079 int err; 2080 2081 if (pci_match_id(driver_denylist, pci)) { 2082 dev_info(&pci->dev, "Skipping the device on the denylist\n"); 2083 return -ENODEV; 2084 } 2085 2086 dev = find_first_zero_bit(probed_devs, SNDRV_CARDS); 2087 if (dev >= SNDRV_CARDS) 2088 return -ENODEV; 2089 if (!enable[dev]) { 2090 set_bit(dev, probed_devs); 2091 return -ENOENT; 2092 } 2093 2094 /* 2095 * stop probe if another Intel's DSP driver should be activated 2096 */ 2097 if (dmic_detect) { 2098 err = snd_intel_dsp_driver_probe(pci); 2099 if (err != SND_INTEL_DSP_DRIVER_ANY && err != SND_INTEL_DSP_DRIVER_LEGACY) { 2100 dev_dbg(&pci->dev, "HDAudio driver not selected, aborting probe\n"); 2101 return -ENODEV; 2102 } 2103 } else { 2104 dev_warn(&pci->dev, "dmic_detect option is deprecated, pass snd-intel-dspcfg.dsp_driver=1 option instead\n"); 2105 } 2106 2107 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE, 2108 0, &card); 2109 if (err < 0) { 2110 dev_err(&pci->dev, "Error creating card!\n"); 2111 return err; 2112 } 2113 2114 err = azx_create(card, pci, dev, pci_id->driver_data, &chip); 2115 if (err < 0) 2116 goto out_free; 2117 card->private_data = chip; 2118 hda = container_of(chip, struct hda_intel, chip); 2119 2120 pci_set_drvdata(pci, card); 2121 2122 #ifdef CONFIG_SND_HDA_I915 2123 /* bind with i915 if needed */ 2124 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) { 2125 err = snd_hdac_i915_init(azx_bus(chip)); 2126 if (err < 0) { 2127 if (err == -EPROBE_DEFER) 2128 goto out_free; 2129 2130 /* if the controller is bound only with HDMI/DP 2131 * (for HSW and BDW), we need to abort the probe; 2132 * for other chips, still continue probing as other 2133 * codecs can be on the same link. 2134 */ 2135 if (HDA_CONTROLLER_IN_GPU(pci)) { 2136 dev_err_probe(card->dev, err, 2137 "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n"); 2138 2139 goto out_free; 2140 } else { 2141 /* don't bother any longer */ 2142 chip->driver_caps &= ~AZX_DCAPS_I915_COMPONENT; 2143 } 2144 } 2145 2146 /* HSW/BDW controllers need this power */ 2147 if (HDA_CONTROLLER_IN_GPU(pci)) 2148 hda->need_i915_power = true; 2149 } 2150 #else 2151 if (HDA_CONTROLLER_IN_GPU(pci)) 2152 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n"); 2153 #endif 2154 2155 err = register_vga_switcheroo(chip); 2156 if (err < 0) { 2157 dev_err(card->dev, "Error registering vga_switcheroo client\n"); 2158 goto out_free; 2159 } 2160 2161 if (check_hdmi_disabled(pci)) { 2162 dev_info(card->dev, "VGA controller is disabled\n"); 2163 dev_info(card->dev, "Delaying initialization\n"); 2164 chip->disabled = true; 2165 } 2166 2167 schedule_probe = !chip->disabled; 2168 2169 #ifdef CONFIG_SND_HDA_PATCH_LOADER 2170 if (patch[dev] && *patch[dev]) { 2171 dev_info(card->dev, "Applying patch firmware '%s'\n", 2172 patch[dev]); 2173 err = request_firmware_nowait(THIS_MODULE, true, patch[dev], 2174 &pci->dev, GFP_KERNEL, card, 2175 azx_firmware_cb); 2176 if (err < 0) 2177 goto out_free; 2178 schedule_probe = false; /* continued in azx_firmware_cb() */ 2179 } 2180 #endif /* CONFIG_SND_HDA_PATCH_LOADER */ 2181 2182 if (schedule_probe) 2183 schedule_delayed_work(&hda->probe_work, 0); 2184 2185 set_bit(dev, probed_devs); 2186 if (chip->disabled) 2187 complete_all(&hda->probe_wait); 2188 return 0; 2189 2190 out_free: 2191 pci_set_drvdata(pci, NULL); 2192 snd_card_free(card); 2193 return err; 2194 } 2195 2196 /* On some boards setting power_save to a non 0 value leads to clicking / 2197 * popping sounds when ever we enter/leave powersaving mode. Ideally we would 2198 * figure out how to avoid these sounds, but that is not always feasible. 2199 * So we keep a list of devices where we disable powersaving as its known 2200 * to causes problems on these devices. 2201 */ 2202 static const struct snd_pci_quirk power_save_denylist[] = { 2203 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2204 SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0), 2205 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2206 SND_PCI_QUIRK(0x1849, 0x0397, "Asrock N68C-S UCC", 0), 2207 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2208 SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0), 2209 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2210 SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0), 2211 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2212 SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0), 2213 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2214 /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */ 2215 SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0), 2216 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2217 SND_PCI_QUIRK(0x8086, 0x2040, "Intel DZ77BH-55K", 0), 2218 /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */ 2219 SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0), 2220 /* https://bugs.launchpad.net/bugs/1821663 */ 2221 SND_PCI_QUIRK(0x8086, 0x2064, "Intel SDP 8086:2064", 0), 2222 /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */ 2223 SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0), 2224 /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */ 2225 SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0), 2226 SND_PCI_QUIRK(0x17aa, 0x316e, "Lenovo ThinkCentre M70q", 0), 2227 /* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */ 2228 SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0), 2229 /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */ 2230 SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0), 2231 /* https://bugs.launchpad.net/bugs/1821663 */ 2232 SND_PCI_QUIRK(0x1631, 0xe017, "Packard Bell NEC IMEDIA 5204", 0), 2233 /* KONTRON SinglePC may cause a stall at runtime resume */ 2234 SND_PCI_QUIRK(0x1734, 0x1232, "KONTRON SinglePC", 0), 2235 {} 2236 }; 2237 2238 static void set_default_power_save(struct azx *chip) 2239 { 2240 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 2241 int val = power_save; 2242 2243 if (pm_blacklist < 0) { 2244 const struct snd_pci_quirk *q; 2245 2246 q = snd_pci_quirk_lookup(chip->pci, power_save_denylist); 2247 if (q && val) { 2248 dev_info(chip->card->dev, "device %04x:%04x is on the power_save denylist, forcing power_save to 0\n", 2249 q->subvendor, q->subdevice); 2250 val = 0; 2251 hda->runtime_pm_disabled = 1; 2252 } 2253 } else if (pm_blacklist > 0) { 2254 dev_info(chip->card->dev, "Forcing power_save to 0 via option\n"); 2255 val = 0; 2256 } 2257 snd_hda_set_power_save(&chip->bus, val * 1000); 2258 } 2259 2260 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */ 2261 static const unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = { 2262 [AZX_DRIVER_NVIDIA] = 8, 2263 [AZX_DRIVER_TERA] = 1, 2264 }; 2265 2266 static int azx_probe_continue(struct azx *chip) 2267 { 2268 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 2269 struct hdac_bus *bus = azx_bus(chip); 2270 struct pci_dev *pci = chip->pci; 2271 int dev = chip->dev_index; 2272 int err; 2273 2274 if (chip->disabled || hda->init_failed) 2275 return -EIO; 2276 if (hda->probe_retry) 2277 goto probe_retry; 2278 2279 to_hda_bus(bus)->bus_probing = 1; 2280 hda->probe_continued = 1; 2281 2282 /* Request display power well for the HDA controller or codec. For 2283 * Haswell/Broadwell, both the display HDA controller and codec need 2284 * this power. For other platforms, like Baytrail/Braswell, only the 2285 * display codec needs the power and it can be released after probe. 2286 */ 2287 display_power(chip, true); 2288 2289 err = azx_first_init(chip); 2290 if (err < 0) 2291 goto out_free; 2292 2293 #ifdef CONFIG_SND_HDA_INPUT_BEEP 2294 chip->beep_mode = beep_mode[dev]; 2295 #endif 2296 2297 chip->ctl_dev_id = ctl_dev_id; 2298 2299 /* create codec instances */ 2300 if (bus->codec_mask) { 2301 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]); 2302 if (err < 0) 2303 goto out_free; 2304 } 2305 2306 #ifdef CONFIG_SND_HDA_PATCH_LOADER 2307 if (chip->fw) { 2308 err = snd_hda_load_patch(&chip->bus, chip->fw->size, 2309 chip->fw->data); 2310 if (err < 0) 2311 goto out_free; 2312 } 2313 #endif 2314 2315 probe_retry: 2316 if (bus->codec_mask && !(probe_only[dev] & 1)) { 2317 err = azx_codec_configure(chip); 2318 if (err) { 2319 if ((chip->driver_caps & AZX_DCAPS_RETRY_PROBE) && 2320 ++hda->probe_retry < 60) { 2321 schedule_delayed_work(&hda->probe_work, 2322 msecs_to_jiffies(1000)); 2323 return 0; /* keep things up */ 2324 } 2325 dev_err(chip->card->dev, "Cannot probe codecs, giving up\n"); 2326 goto out_free; 2327 } 2328 } 2329 2330 err = snd_card_register(chip->card); 2331 if (err < 0) 2332 goto out_free; 2333 2334 setup_vga_switcheroo_runtime_pm(chip); 2335 2336 chip->running = 1; 2337 azx_add_card_list(chip); 2338 2339 set_default_power_save(chip); 2340 2341 if (azx_has_pm_runtime(chip)) { 2342 pm_runtime_use_autosuspend(&pci->dev); 2343 pm_runtime_allow(&pci->dev); 2344 pm_runtime_put_autosuspend(&pci->dev); 2345 } 2346 2347 out_free: 2348 if (err < 0) { 2349 pci_set_drvdata(pci, NULL); 2350 snd_card_free(chip->card); 2351 return err; 2352 } 2353 2354 if (!hda->need_i915_power) 2355 display_power(chip, false); 2356 complete_all(&hda->probe_wait); 2357 to_hda_bus(bus)->bus_probing = 0; 2358 hda->probe_retry = 0; 2359 return 0; 2360 } 2361 2362 static void azx_remove(struct pci_dev *pci) 2363 { 2364 struct snd_card *card = pci_get_drvdata(pci); 2365 struct azx *chip; 2366 struct hda_intel *hda; 2367 2368 if (card) { 2369 /* cancel the pending probing work */ 2370 chip = card->private_data; 2371 hda = container_of(chip, struct hda_intel, chip); 2372 /* FIXME: below is an ugly workaround. 2373 * Both device_release_driver() and driver_probe_device() 2374 * take *both* the device's and its parent's lock before 2375 * calling the remove() and probe() callbacks. The codec 2376 * probe takes the locks of both the codec itself and its 2377 * parent, i.e. the PCI controller dev. Meanwhile, when 2378 * the PCI controller is unbound, it takes its lock, too 2379 * ==> ouch, a deadlock! 2380 * As a workaround, we unlock temporarily here the controller 2381 * device during cancel_work_sync() call. 2382 */ 2383 device_unlock(&pci->dev); 2384 cancel_delayed_work_sync(&hda->probe_work); 2385 device_lock(&pci->dev); 2386 2387 clear_bit(chip->dev_index, probed_devs); 2388 pci_set_drvdata(pci, NULL); 2389 snd_card_free(card); 2390 } 2391 } 2392 2393 static void azx_shutdown(struct pci_dev *pci) 2394 { 2395 struct snd_card *card = pci_get_drvdata(pci); 2396 struct azx *chip; 2397 2398 if (!card) 2399 return; 2400 chip = card->private_data; 2401 if (chip && chip->running) 2402 __azx_shutdown_chip(chip, true); 2403 } 2404 2405 /* PCI IDs */ 2406 static const struct pci_device_id azx_ids[] = { 2407 /* CPT */ 2408 { PCI_DEVICE_DATA(INTEL, HDA_CPT, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM) }, 2409 /* PBG */ 2410 { PCI_DEVICE_DATA(INTEL, HDA_PBG, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM) }, 2411 /* Panther Point */ 2412 { PCI_DEVICE_DATA(INTEL, HDA_PPT, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM) }, 2413 /* Lynx Point */ 2414 { PCI_DEVICE_DATA(INTEL, HDA_LPT, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) }, 2415 /* 9 Series */ 2416 { PCI_DEVICE_DATA(INTEL, HDA_9_SERIES, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) }, 2417 /* Wellsburg */ 2418 { PCI_DEVICE_DATA(INTEL, HDA_WBG_0, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) }, 2419 { PCI_DEVICE_DATA(INTEL, HDA_WBG_1, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) }, 2420 /* Lewisburg */ 2421 { PCI_DEVICE_DATA(INTEL, HDA_LBG_0, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE) }, 2422 { PCI_DEVICE_DATA(INTEL, HDA_LBG_1, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE) }, 2423 /* Lynx Point-LP */ 2424 { PCI_DEVICE_DATA(INTEL, HDA_LPT_LP_0, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) }, 2425 /* Lynx Point-LP */ 2426 { PCI_DEVICE_DATA(INTEL, HDA_LPT_LP_1, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) }, 2427 /* Wildcat Point-LP */ 2428 { PCI_DEVICE_DATA(INTEL, HDA_WPT_LP, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) }, 2429 /* Skylake (Sunrise Point) */ 2430 { PCI_DEVICE_DATA(INTEL, HDA_SKL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2431 /* Skylake-LP (Sunrise Point-LP) */ 2432 { PCI_DEVICE_DATA(INTEL, HDA_SKL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2433 /* Kabylake */ 2434 { PCI_DEVICE_DATA(INTEL, HDA_KBL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2435 /* Kabylake-LP */ 2436 { PCI_DEVICE_DATA(INTEL, HDA_KBL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2437 /* Kabylake-H */ 2438 { PCI_DEVICE_DATA(INTEL, HDA_KBL_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2439 /* Coffelake */ 2440 { PCI_DEVICE_DATA(INTEL, HDA_CNL_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2441 /* Cannonlake */ 2442 { PCI_DEVICE_DATA(INTEL, HDA_CNL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2443 /* CometLake-LP */ 2444 { PCI_DEVICE_DATA(INTEL, HDA_CML_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2445 /* CometLake-H */ 2446 { PCI_DEVICE_DATA(INTEL, HDA_CML_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2447 { PCI_DEVICE_DATA(INTEL, HDA_RKL_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2448 /* CometLake-S */ 2449 { PCI_DEVICE_DATA(INTEL, HDA_CML_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2450 /* CometLake-R */ 2451 { PCI_DEVICE_DATA(INTEL, HDA_CML_R, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2452 /* Icelake */ 2453 { PCI_DEVICE_DATA(INTEL, HDA_ICL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2454 /* Icelake-H */ 2455 { PCI_DEVICE_DATA(INTEL, HDA_ICL_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2456 /* Jasperlake */ 2457 { PCI_DEVICE_DATA(INTEL, HDA_ICL_N, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2458 { PCI_DEVICE_DATA(INTEL, HDA_JSL_N, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2459 /* Tigerlake */ 2460 { PCI_DEVICE_DATA(INTEL, HDA_TGL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2461 /* Tigerlake-H */ 2462 { PCI_DEVICE_DATA(INTEL, HDA_TGL_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2463 /* DG1 */ 2464 { PCI_DEVICE_DATA(INTEL, HDA_DG1, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2465 /* DG2 */ 2466 { PCI_DEVICE_DATA(INTEL, HDA_DG2_0, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2467 { PCI_DEVICE_DATA(INTEL, HDA_DG2_1, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2468 { PCI_DEVICE_DATA(INTEL, HDA_DG2_2, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2469 /* Alderlake-S */ 2470 { PCI_DEVICE_DATA(INTEL, HDA_ADL_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2471 /* Alderlake-P */ 2472 { PCI_DEVICE_DATA(INTEL, HDA_ADL_P, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2473 { PCI_DEVICE_DATA(INTEL, HDA_ADL_PS, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2474 { PCI_DEVICE_DATA(INTEL, HDA_ADL_PX, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2475 /* Alderlake-M */ 2476 { PCI_DEVICE_DATA(INTEL, HDA_ADL_M, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2477 /* Alderlake-N */ 2478 { PCI_DEVICE_DATA(INTEL, HDA_ADL_N, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2479 /* Elkhart Lake */ 2480 { PCI_DEVICE_DATA(INTEL, HDA_EHL_0, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2481 { PCI_DEVICE_DATA(INTEL, HDA_EHL_3, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2482 /* Raptor Lake */ 2483 { PCI_DEVICE_DATA(INTEL, HDA_RPL_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2484 { PCI_DEVICE_DATA(INTEL, HDA_RPL_P_0, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2485 { PCI_DEVICE_DATA(INTEL, HDA_RPL_P_1, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2486 { PCI_DEVICE_DATA(INTEL, HDA_RPL_M, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2487 { PCI_DEVICE_DATA(INTEL, HDA_RPL_PX, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2488 { PCI_DEVICE_DATA(INTEL, HDA_MTL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2489 /* Battlemage */ 2490 { PCI_DEVICE_DATA(INTEL, HDA_BMG, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2491 /* Lunarlake-P */ 2492 { PCI_DEVICE_DATA(INTEL, HDA_LNL_P, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_LNL) }, 2493 /* Arrow Lake-S */ 2494 { PCI_DEVICE_DATA(INTEL, HDA_ARL_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2495 /* Arrow Lake */ 2496 { PCI_DEVICE_DATA(INTEL, HDA_ARL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2497 /* Panther Lake */ 2498 { PCI_DEVICE_DATA(INTEL, HDA_PTL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_LNL) }, 2499 /* Apollolake (Broxton-P) */ 2500 { PCI_DEVICE_DATA(INTEL, HDA_APL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON) }, 2501 /* Gemini-Lake */ 2502 { PCI_DEVICE_DATA(INTEL, HDA_GML, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON) }, 2503 /* Haswell */ 2504 { PCI_DEVICE_DATA(INTEL, HDA_HSW_0, AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL) }, 2505 { PCI_DEVICE_DATA(INTEL, HDA_HSW_2, AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL) }, 2506 { PCI_DEVICE_DATA(INTEL, HDA_HSW_3, AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL) }, 2507 /* Broadwell */ 2508 { PCI_DEVICE_DATA(INTEL, HDA_BDW, AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL) }, 2509 /* 5 Series/3400 */ 2510 { PCI_DEVICE_DATA(INTEL, HDA_5_3400_SERIES_0, AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM) }, 2511 { PCI_DEVICE_DATA(INTEL, HDA_5_3400_SERIES_1, AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM) }, 2512 /* Poulsbo */ 2513 { PCI_DEVICE_DATA(INTEL, HDA_POULSBO, AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE | 2514 AZX_DCAPS_POSFIX_LPIB) }, 2515 /* Oaktrail */ 2516 { PCI_DEVICE_DATA(INTEL, HDA_OAKTRAIL, AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE) }, 2517 /* BayTrail */ 2518 { PCI_DEVICE_DATA(INTEL, HDA_BYT, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL) }, 2519 /* Braswell */ 2520 { PCI_DEVICE_DATA(INTEL, HDA_BSW, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL) }, 2521 /* ICH6 */ 2522 { PCI_DEVICE_DATA(INTEL, HDA_ICH6, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) }, 2523 /* ICH7 */ 2524 { PCI_DEVICE_DATA(INTEL, HDA_ICH7, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) }, 2525 /* ESB2 */ 2526 { PCI_DEVICE_DATA(INTEL, HDA_ESB2, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) }, 2527 /* ICH8 */ 2528 { PCI_DEVICE_DATA(INTEL, HDA_ICH8, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) }, 2529 /* ICH9 */ 2530 { PCI_DEVICE_DATA(INTEL, HDA_ICH9_0, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) }, 2531 /* ICH9 */ 2532 { PCI_DEVICE_DATA(INTEL, HDA_ICH9_1, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) }, 2533 /* ICH10 */ 2534 { PCI_DEVICE_DATA(INTEL, HDA_ICH10_0, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) }, 2535 /* ICH10 */ 2536 { PCI_DEVICE_DATA(INTEL, HDA_ICH10_1, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) }, 2537 /* Generic Intel */ 2538 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID), 2539 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2540 .class_mask = 0xffffff, 2541 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE }, 2542 /* ATI SB 450/600/700/800/900 */ 2543 { PCI_VDEVICE(ATI, 0x437b), 2544 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, 2545 { PCI_VDEVICE(ATI, 0x4383), 2546 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, 2547 /* AMD Hudson */ 2548 { PCI_VDEVICE(AMD, 0x780d), 2549 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB }, 2550 /* AMD, X370 & co */ 2551 { PCI_VDEVICE(AMD, 0x1457), 2552 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB }, 2553 /* AMD, X570 & co */ 2554 { PCI_VDEVICE(AMD, 0x1487), 2555 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB }, 2556 /* AMD Stoney */ 2557 { PCI_VDEVICE(AMD, 0x157a), 2558 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB | 2559 AZX_DCAPS_PM_RUNTIME }, 2560 /* AMD Raven */ 2561 { PCI_VDEVICE(AMD, 0x15e3), 2562 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB }, 2563 /* ATI HDMI */ 2564 { PCI_VDEVICE(ATI, 0x0002), 2565 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2566 AZX_DCAPS_PM_RUNTIME }, 2567 { PCI_VDEVICE(ATI, 0x1308), 2568 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2569 { PCI_VDEVICE(ATI, 0x157a), 2570 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2571 { PCI_VDEVICE(ATI, 0x15b3), 2572 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2573 { PCI_VDEVICE(ATI, 0x793b), 2574 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2575 { PCI_VDEVICE(ATI, 0x7919), 2576 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2577 { PCI_VDEVICE(ATI, 0x960f), 2578 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2579 { PCI_VDEVICE(ATI, 0x970f), 2580 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2581 { PCI_VDEVICE(ATI, 0x9840), 2582 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2583 { PCI_VDEVICE(ATI, 0xaa00), 2584 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2585 { PCI_VDEVICE(ATI, 0xaa08), 2586 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2587 { PCI_VDEVICE(ATI, 0xaa10), 2588 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2589 { PCI_VDEVICE(ATI, 0xaa18), 2590 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2591 { PCI_VDEVICE(ATI, 0xaa20), 2592 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2593 { PCI_VDEVICE(ATI, 0xaa28), 2594 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2595 { PCI_VDEVICE(ATI, 0xaa30), 2596 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2597 { PCI_VDEVICE(ATI, 0xaa38), 2598 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2599 { PCI_VDEVICE(ATI, 0xaa40), 2600 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2601 { PCI_VDEVICE(ATI, 0xaa48), 2602 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2603 { PCI_VDEVICE(ATI, 0xaa50), 2604 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2605 { PCI_VDEVICE(ATI, 0xaa58), 2606 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2607 { PCI_VDEVICE(ATI, 0xaa60), 2608 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2609 { PCI_VDEVICE(ATI, 0xaa68), 2610 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2611 { PCI_VDEVICE(ATI, 0xaa80), 2612 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2613 { PCI_VDEVICE(ATI, 0xaa88), 2614 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2615 { PCI_VDEVICE(ATI, 0xaa90), 2616 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2617 { PCI_VDEVICE(ATI, 0xaa98), 2618 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2619 { PCI_VDEVICE(ATI, 0x9902), 2620 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2621 { PCI_VDEVICE(ATI, 0xaaa0), 2622 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2623 { PCI_VDEVICE(ATI, 0xaaa8), 2624 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2625 { PCI_VDEVICE(ATI, 0xaab0), 2626 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2627 { PCI_VDEVICE(ATI, 0xaac0), 2628 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2629 AZX_DCAPS_PM_RUNTIME }, 2630 { PCI_VDEVICE(ATI, 0xaac8), 2631 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2632 AZX_DCAPS_PM_RUNTIME }, 2633 { PCI_VDEVICE(ATI, 0xaad8), 2634 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2635 AZX_DCAPS_PM_RUNTIME }, 2636 { PCI_VDEVICE(ATI, 0xaae0), 2637 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2638 AZX_DCAPS_PM_RUNTIME }, 2639 { PCI_VDEVICE(ATI, 0xaae8), 2640 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2641 AZX_DCAPS_PM_RUNTIME }, 2642 { PCI_VDEVICE(ATI, 0xaaf0), 2643 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2644 AZX_DCAPS_PM_RUNTIME }, 2645 { PCI_VDEVICE(ATI, 0xaaf8), 2646 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2647 AZX_DCAPS_PM_RUNTIME }, 2648 { PCI_VDEVICE(ATI, 0xab00), 2649 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2650 AZX_DCAPS_PM_RUNTIME }, 2651 { PCI_VDEVICE(ATI, 0xab08), 2652 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2653 AZX_DCAPS_PM_RUNTIME }, 2654 { PCI_VDEVICE(ATI, 0xab10), 2655 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2656 AZX_DCAPS_PM_RUNTIME }, 2657 { PCI_VDEVICE(ATI, 0xab18), 2658 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2659 AZX_DCAPS_PM_RUNTIME }, 2660 { PCI_VDEVICE(ATI, 0xab20), 2661 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2662 AZX_DCAPS_PM_RUNTIME }, 2663 { PCI_VDEVICE(ATI, 0xab28), 2664 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2665 AZX_DCAPS_PM_RUNTIME }, 2666 { PCI_VDEVICE(ATI, 0xab30), 2667 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2668 AZX_DCAPS_PM_RUNTIME }, 2669 { PCI_VDEVICE(ATI, 0xab38), 2670 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2671 AZX_DCAPS_PM_RUNTIME }, 2672 /* GLENFLY */ 2673 { PCI_DEVICE(PCI_VENDOR_ID_GLENFLY, PCI_ANY_ID), 2674 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2675 .class_mask = 0xffffff, 2676 .driver_data = AZX_DRIVER_GFHDMI | AZX_DCAPS_POSFIX_LPIB | 2677 AZX_DCAPS_NO_MSI | AZX_DCAPS_NO_64BIT }, 2678 /* VIA VT8251/VT8237A */ 2679 { PCI_VDEVICE(VIA, 0x3288), .driver_data = AZX_DRIVER_VIA }, 2680 /* VIA GFX VT7122/VX900 */ 2681 { PCI_VDEVICE(VIA, 0x9170), .driver_data = AZX_DRIVER_GENERIC }, 2682 /* VIA GFX VT6122/VX11 */ 2683 { PCI_VDEVICE(VIA, 0x9140), .driver_data = AZX_DRIVER_GENERIC }, 2684 /* SIS966 */ 2685 { PCI_VDEVICE(SI, 0x7502), .driver_data = AZX_DRIVER_SIS }, 2686 /* ULI M5461 */ 2687 { PCI_VDEVICE(AL, 0x5461), .driver_data = AZX_DRIVER_ULI }, 2688 /* NVIDIA MCP */ 2689 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID), 2690 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2691 .class_mask = 0xffffff, 2692 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA }, 2693 /* Teradici */ 2694 { PCI_DEVICE(0x6549, 0x1200), 2695 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, 2696 { PCI_DEVICE(0x6549, 0x2200), 2697 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, 2698 /* Creative X-Fi (CA0110-IBG) */ 2699 /* CTHDA chips */ 2700 { PCI_VDEVICE(CREATIVE, 0x0010), 2701 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, 2702 { PCI_VDEVICE(CREATIVE, 0x0012), 2703 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, 2704 #if !IS_ENABLED(CONFIG_SND_CTXFI) 2705 /* the following entry conflicts with snd-ctxfi driver, 2706 * as ctxfi driver mutates from HD-audio to native mode with 2707 * a special command sequence. 2708 */ 2709 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID), 2710 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2711 .class_mask = 0xffffff, 2712 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | 2713 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB }, 2714 #else 2715 /* this entry seems still valid -- i.e. without emu20kx chip */ 2716 { PCI_VDEVICE(CREATIVE, 0x0009), 2717 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | 2718 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB }, 2719 #endif 2720 /* CM8888 */ 2721 { PCI_VDEVICE(CMEDIA, 0x5011), 2722 .driver_data = AZX_DRIVER_CMEDIA | 2723 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF }, 2724 /* Vortex86MX */ 2725 { PCI_VDEVICE(RDC, 0x3010), .driver_data = AZX_DRIVER_GENERIC }, 2726 /* VMware HDAudio */ 2727 { PCI_VDEVICE(VMWARE, 0x1977), .driver_data = AZX_DRIVER_GENERIC }, 2728 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */ 2729 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID), 2730 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2731 .class_mask = 0xffffff, 2732 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, 2733 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID), 2734 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2735 .class_mask = 0xffffff, 2736 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, 2737 /* Zhaoxin */ 2738 { PCI_VDEVICE(ZHAOXIN, 0x3288), .driver_data = AZX_DRIVER_ZHAOXIN }, 2739 /* Loongson HDAudio*/ 2740 { PCI_VDEVICE(LOONGSON, PCI_DEVICE_ID_LOONGSON_HDA), 2741 .driver_data = AZX_DRIVER_LOONGSON }, 2742 { PCI_VDEVICE(LOONGSON, PCI_DEVICE_ID_LOONGSON_HDMI), 2743 .driver_data = AZX_DRIVER_LOONGSON }, 2744 { 0, } 2745 }; 2746 MODULE_DEVICE_TABLE(pci, azx_ids); 2747 2748 /* pci_driver definition */ 2749 static struct pci_driver azx_driver = { 2750 .name = KBUILD_MODNAME, 2751 .id_table = azx_ids, 2752 .probe = azx_probe, 2753 .remove = azx_remove, 2754 .shutdown = azx_shutdown, 2755 .driver = { 2756 .pm = &azx_pm, 2757 }, 2758 }; 2759 2760 module_pci_driver(azx_driver); 2761