1 /* 2 * 3 * hda_intel.c - Implementation of primary alsa driver code base 4 * for Intel HD Audio. 5 * 6 * Copyright(c) 2004 Intel Corporation. All rights reserved. 7 * 8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> 9 * PeiSen Hou <pshou@realtek.com.tw> 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the Free 13 * Software Foundation; either version 2 of the License, or (at your option) 14 * any later version. 15 * 16 * This program is distributed in the hope that it will be useful, but WITHOUT 17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 19 * more details. 20 * 21 * You should have received a copy of the GNU General Public License along with 22 * this program; if not, write to the Free Software Foundation, Inc., 59 23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA. 24 * 25 * CONTACTS: 26 * 27 * Matt Jared matt.jared@intel.com 28 * Andy Kopp andy.kopp@intel.com 29 * Dan Kogan dan.d.kogan@intel.com 30 * 31 * CHANGES: 32 * 33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou 34 * 35 */ 36 37 #include <linux/delay.h> 38 #include <linux/interrupt.h> 39 #include <linux/kernel.h> 40 #include <linux/module.h> 41 #include <linux/dma-mapping.h> 42 #include <linux/moduleparam.h> 43 #include <linux/init.h> 44 #include <linux/slab.h> 45 #include <linux/pci.h> 46 #include <linux/mutex.h> 47 #include <linux/io.h> 48 #include <linux/pm_runtime.h> 49 #include <linux/clocksource.h> 50 #include <linux/time.h> 51 #include <linux/completion.h> 52 53 #ifdef CONFIG_X86 54 /* for snoop control */ 55 #include <asm/pgtable.h> 56 #include <asm/cacheflush.h> 57 #endif 58 #include <sound/core.h> 59 #include <sound/initval.h> 60 #include <linux/vgaarb.h> 61 #include <linux/vga_switcheroo.h> 62 #include <linux/firmware.h> 63 #include "hda_codec.h" 64 #include "hda_controller.h" 65 #include "hda_priv.h" 66 #include "hda_i915.h" 67 68 /* position fix mode */ 69 enum { 70 POS_FIX_AUTO, 71 POS_FIX_LPIB, 72 POS_FIX_POSBUF, 73 POS_FIX_VIACOMBO, 74 POS_FIX_COMBO, 75 }; 76 77 /* Defines for ATI HD Audio support in SB450 south bridge */ 78 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42 79 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02 80 81 /* Defines for Nvidia HDA support */ 82 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e 83 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f 84 #define NVIDIA_HDA_ISTRM_COH 0x4d 85 #define NVIDIA_HDA_OSTRM_COH 0x4c 86 #define NVIDIA_HDA_ENABLE_COHBIT 0x01 87 88 /* Defines for Intel SCH HDA snoop control */ 89 #define INTEL_SCH_HDA_DEVC 0x78 90 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11) 91 92 /* Define IN stream 0 FIFO size offset in VIA controller */ 93 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90 94 /* Define VIA HD Audio Device ID*/ 95 #define VIA_HDAC_DEVICE_ID 0x3288 96 97 /* max number of SDs */ 98 /* ICH, ATI and VIA have 4 playback and 4 capture */ 99 #define ICH6_NUM_CAPTURE 4 100 #define ICH6_NUM_PLAYBACK 4 101 102 /* ULI has 6 playback and 5 capture */ 103 #define ULI_NUM_CAPTURE 5 104 #define ULI_NUM_PLAYBACK 6 105 106 /* ATI HDMI may have up to 8 playbacks and 0 capture */ 107 #define ATIHDMI_NUM_CAPTURE 0 108 #define ATIHDMI_NUM_PLAYBACK 8 109 110 /* TERA has 4 playback and 3 capture */ 111 #define TERA_NUM_CAPTURE 3 112 #define TERA_NUM_PLAYBACK 4 113 114 115 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; 116 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; 117 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; 118 static char *model[SNDRV_CARDS]; 119 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 120 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 121 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 122 static int probe_only[SNDRV_CARDS]; 123 static int jackpoll_ms[SNDRV_CARDS]; 124 static bool single_cmd; 125 static int enable_msi = -1; 126 #ifdef CONFIG_SND_HDA_PATCH_LOADER 127 static char *patch[SNDRV_CARDS]; 128 #endif 129 #ifdef CONFIG_SND_HDA_INPUT_BEEP 130 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = 131 CONFIG_SND_HDA_INPUT_BEEP_MODE}; 132 #endif 133 134 module_param_array(index, int, NULL, 0444); 135 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface."); 136 module_param_array(id, charp, NULL, 0444); 137 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface."); 138 module_param_array(enable, bool, NULL, 0444); 139 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface."); 140 module_param_array(model, charp, NULL, 0444); 141 MODULE_PARM_DESC(model, "Use the given board model."); 142 module_param_array(position_fix, int, NULL, 0444); 143 MODULE_PARM_DESC(position_fix, "DMA pointer read method." 144 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO)."); 145 module_param_array(bdl_pos_adj, int, NULL, 0644); 146 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset."); 147 module_param_array(probe_mask, int, NULL, 0444); 148 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1)."); 149 module_param_array(probe_only, int, NULL, 0444); 150 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization."); 151 module_param_array(jackpoll_ms, int, NULL, 0444); 152 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)"); 153 module_param(single_cmd, bool, 0444); 154 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs " 155 "(for debugging only)."); 156 module_param(enable_msi, bint, 0444); 157 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)"); 158 #ifdef CONFIG_SND_HDA_PATCH_LOADER 159 module_param_array(patch, charp, NULL, 0444); 160 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface."); 161 #endif 162 #ifdef CONFIG_SND_HDA_INPUT_BEEP 163 module_param_array(beep_mode, bool, NULL, 0444); 164 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode " 165 "(0=off, 1=on) (default=1)."); 166 #endif 167 168 #ifdef CONFIG_PM 169 static int param_set_xint(const char *val, const struct kernel_param *kp); 170 static struct kernel_param_ops param_ops_xint = { 171 .set = param_set_xint, 172 .get = param_get_int, 173 }; 174 #define param_check_xint param_check_int 175 176 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT; 177 static int *power_save_addr = &power_save; 178 module_param(power_save, xint, 0644); 179 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout " 180 "(in second, 0 = disable)."); 181 182 /* reset the HD-audio controller in power save mode. 183 * this may give more power-saving, but will take longer time to 184 * wake up. 185 */ 186 static bool power_save_controller = 1; 187 module_param(power_save_controller, bool, 0644); 188 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode."); 189 #else 190 static int *power_save_addr; 191 #endif /* CONFIG_PM */ 192 193 static int align_buffer_size = -1; 194 module_param(align_buffer_size, bint, 0644); 195 MODULE_PARM_DESC(align_buffer_size, 196 "Force buffer and period sizes to be multiple of 128 bytes."); 197 198 #ifdef CONFIG_X86 199 static bool hda_snoop = true; 200 module_param_named(snoop, hda_snoop, bool, 0444); 201 MODULE_PARM_DESC(snoop, "Enable/disable snooping"); 202 #else 203 #define hda_snoop true 204 #endif 205 206 207 MODULE_LICENSE("GPL"); 208 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6}," 209 "{Intel, ICH6M}," 210 "{Intel, ICH7}," 211 "{Intel, ESB2}," 212 "{Intel, ICH8}," 213 "{Intel, ICH9}," 214 "{Intel, ICH10}," 215 "{Intel, PCH}," 216 "{Intel, CPT}," 217 "{Intel, PPT}," 218 "{Intel, LPT}," 219 "{Intel, LPT_LP}," 220 "{Intel, WPT_LP}," 221 "{Intel, HPT}," 222 "{Intel, PBG}," 223 "{Intel, SCH}," 224 "{ATI, SB450}," 225 "{ATI, SB600}," 226 "{ATI, RS600}," 227 "{ATI, RS690}," 228 "{ATI, RS780}," 229 "{ATI, R600}," 230 "{ATI, RV630}," 231 "{ATI, RV610}," 232 "{ATI, RV670}," 233 "{ATI, RV635}," 234 "{ATI, RV620}," 235 "{ATI, RV770}," 236 "{VIA, VT8251}," 237 "{VIA, VT8237A}," 238 "{SiS, SIS966}," 239 "{ULI, M5461}}"); 240 MODULE_DESCRIPTION("Intel HDA driver"); 241 242 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO) 243 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI) 244 #define SUPPORT_VGA_SWITCHEROO 245 #endif 246 #endif 247 248 249 /* 250 */ 251 252 /* driver types */ 253 enum { 254 AZX_DRIVER_ICH, 255 AZX_DRIVER_PCH, 256 AZX_DRIVER_SCH, 257 AZX_DRIVER_HDMI, 258 AZX_DRIVER_ATI, 259 AZX_DRIVER_ATIHDMI, 260 AZX_DRIVER_ATIHDMI_NS, 261 AZX_DRIVER_VIA, 262 AZX_DRIVER_SIS, 263 AZX_DRIVER_ULI, 264 AZX_DRIVER_NVIDIA, 265 AZX_DRIVER_TERA, 266 AZX_DRIVER_CTX, 267 AZX_DRIVER_CTHDA, 268 AZX_DRIVER_CMEDIA, 269 AZX_DRIVER_GENERIC, 270 AZX_NUM_DRIVERS, /* keep this as last entry */ 271 }; 272 273 /* quirks for Intel PCH */ 274 #define AZX_DCAPS_INTEL_PCH_NOPM \ 275 (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_BUFSIZE | \ 276 AZX_DCAPS_COUNT_LPIB_DELAY | AZX_DCAPS_REVERSE_ASSIGN) 277 278 #define AZX_DCAPS_INTEL_PCH \ 279 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME) 280 281 #define AZX_DCAPS_INTEL_HASWELL \ 282 (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_ALIGN_BUFSIZE | \ 283 AZX_DCAPS_COUNT_LPIB_DELAY | AZX_DCAPS_PM_RUNTIME | \ 284 AZX_DCAPS_I915_POWERWELL) 285 286 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */ 287 #define AZX_DCAPS_INTEL_BROADWELL \ 288 (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_ALIGN_BUFSIZE | \ 289 AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_PM_RUNTIME | \ 290 AZX_DCAPS_I915_POWERWELL) 291 292 /* quirks for ATI SB / AMD Hudson */ 293 #define AZX_DCAPS_PRESET_ATI_SB \ 294 (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \ 295 AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB) 296 297 /* quirks for ATI/AMD HDMI */ 298 #define AZX_DCAPS_PRESET_ATI_HDMI \ 299 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB) 300 301 /* quirks for Nvidia */ 302 #define AZX_DCAPS_PRESET_NVIDIA \ 303 (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI |\ 304 AZX_DCAPS_ALIGN_BUFSIZE | AZX_DCAPS_NO_64BIT |\ 305 AZX_DCAPS_CORBRP_SELF_CLEAR) 306 307 #define AZX_DCAPS_PRESET_CTHDA \ 308 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_4K_BDLE_BOUNDARY) 309 310 /* 311 * VGA-switcher support 312 */ 313 #ifdef SUPPORT_VGA_SWITCHEROO 314 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo) 315 #else 316 #define use_vga_switcheroo(chip) 0 317 #endif 318 319 static char *driver_short_names[] = { 320 [AZX_DRIVER_ICH] = "HDA Intel", 321 [AZX_DRIVER_PCH] = "HDA Intel PCH", 322 [AZX_DRIVER_SCH] = "HDA Intel MID", 323 [AZX_DRIVER_HDMI] = "HDA Intel HDMI", 324 [AZX_DRIVER_ATI] = "HDA ATI SB", 325 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI", 326 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI", 327 [AZX_DRIVER_VIA] = "HDA VIA VT82xx", 328 [AZX_DRIVER_SIS] = "HDA SIS966", 329 [AZX_DRIVER_ULI] = "HDA ULI M5461", 330 [AZX_DRIVER_NVIDIA] = "HDA NVidia", 331 [AZX_DRIVER_TERA] = "HDA Teradici", 332 [AZX_DRIVER_CTX] = "HDA Creative", 333 [AZX_DRIVER_CTHDA] = "HDA Creative", 334 [AZX_DRIVER_CMEDIA] = "HDA C-Media", 335 [AZX_DRIVER_GENERIC] = "HD-Audio Generic", 336 }; 337 338 struct hda_intel { 339 struct azx chip; 340 341 /* for pending irqs */ 342 struct work_struct irq_pending_work; 343 344 /* sync probing */ 345 struct completion probe_wait; 346 struct work_struct probe_work; 347 348 /* card list (for power_save trigger) */ 349 struct list_head list; 350 351 /* extra flags */ 352 unsigned int irq_pending_warned:1; 353 354 /* VGA-switcheroo setup */ 355 unsigned int use_vga_switcheroo:1; 356 unsigned int vga_switcheroo_registered:1; 357 unsigned int init_failed:1; /* delayed init failed */ 358 359 /* secondary power domain for hdmi audio under vga device */ 360 struct dev_pm_domain hdmi_pm_domain; 361 }; 362 363 #ifdef CONFIG_X86 364 static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on) 365 { 366 int pages; 367 368 if (azx_snoop(chip)) 369 return; 370 if (!dmab || !dmab->area || !dmab->bytes) 371 return; 372 373 #ifdef CONFIG_SND_DMA_SGBUF 374 if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) { 375 struct snd_sg_buf *sgbuf = dmab->private_data; 376 if (on) 377 set_pages_array_wc(sgbuf->page_table, sgbuf->pages); 378 else 379 set_pages_array_wb(sgbuf->page_table, sgbuf->pages); 380 return; 381 } 382 #endif 383 384 pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT; 385 if (on) 386 set_memory_wc((unsigned long)dmab->area, pages); 387 else 388 set_memory_wb((unsigned long)dmab->area, pages); 389 } 390 391 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf, 392 bool on) 393 { 394 __mark_pages_wc(chip, buf, on); 395 } 396 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev, 397 struct snd_pcm_substream *substream, bool on) 398 { 399 if (azx_dev->wc_marked != on) { 400 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on); 401 azx_dev->wc_marked = on; 402 } 403 } 404 #else 405 /* NOP for other archs */ 406 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf, 407 bool on) 408 { 409 } 410 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev, 411 struct snd_pcm_substream *substream, bool on) 412 { 413 } 414 #endif 415 416 static int azx_acquire_irq(struct azx *chip, int do_disconnect); 417 418 /* 419 * initialize the PCI registers 420 */ 421 /* update bits in a PCI register byte */ 422 static void update_pci_byte(struct pci_dev *pci, unsigned int reg, 423 unsigned char mask, unsigned char val) 424 { 425 unsigned char data; 426 427 pci_read_config_byte(pci, reg, &data); 428 data &= ~mask; 429 data |= (val & mask); 430 pci_write_config_byte(pci, reg, data); 431 } 432 433 static void azx_init_pci(struct azx *chip) 434 { 435 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44) 436 * TCSEL == Traffic Class Select Register, which sets PCI express QOS 437 * Ensuring these bits are 0 clears playback static on some HD Audio 438 * codecs. 439 * The PCI register TCSEL is defined in the Intel manuals. 440 */ 441 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) { 442 dev_dbg(chip->card->dev, "Clearing TCSEL\n"); 443 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0); 444 } 445 446 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio, 447 * we need to enable snoop. 448 */ 449 if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) { 450 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n", 451 azx_snoop(chip)); 452 update_pci_byte(chip->pci, 453 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07, 454 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0); 455 } 456 457 /* For NVIDIA HDA, enable snoop */ 458 if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) { 459 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n", 460 azx_snoop(chip)); 461 update_pci_byte(chip->pci, 462 NVIDIA_HDA_TRANSREG_ADDR, 463 0x0f, NVIDIA_HDA_ENABLE_COHBITS); 464 update_pci_byte(chip->pci, 465 NVIDIA_HDA_ISTRM_COH, 466 0x01, NVIDIA_HDA_ENABLE_COHBIT); 467 update_pci_byte(chip->pci, 468 NVIDIA_HDA_OSTRM_COH, 469 0x01, NVIDIA_HDA_ENABLE_COHBIT); 470 } 471 472 /* Enable SCH/PCH snoop if needed */ 473 if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) { 474 unsigned short snoop; 475 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop); 476 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) || 477 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) { 478 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP; 479 if (!azx_snoop(chip)) 480 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP; 481 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop); 482 pci_read_config_word(chip->pci, 483 INTEL_SCH_HDA_DEVC, &snoop); 484 } 485 dev_dbg(chip->card->dev, "SCH snoop: %s\n", 486 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ? 487 "Disabled" : "Enabled"); 488 } 489 } 490 491 /* calculate runtime delay from LPIB */ 492 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev, 493 unsigned int pos) 494 { 495 struct snd_pcm_substream *substream = azx_dev->substream; 496 int stream = substream->stream; 497 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev); 498 int delay; 499 500 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 501 delay = pos - lpib_pos; 502 else 503 delay = lpib_pos - pos; 504 if (delay < 0) { 505 if (delay >= azx_dev->delay_negative_threshold) 506 delay = 0; 507 else 508 delay += azx_dev->bufsize; 509 } 510 511 if (delay >= azx_dev->period_bytes) { 512 dev_info(chip->card->dev, 513 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n", 514 delay, azx_dev->period_bytes); 515 delay = 0; 516 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY; 517 chip->get_delay[stream] = NULL; 518 } 519 520 return bytes_to_frames(substream->runtime, delay); 521 } 522 523 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev); 524 525 /* called from IRQ */ 526 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev) 527 { 528 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 529 int ok; 530 531 ok = azx_position_ok(chip, azx_dev); 532 if (ok == 1) { 533 azx_dev->irq_pending = 0; 534 return ok; 535 } else if (ok == 0 && chip->bus && chip->bus->workq) { 536 /* bogus IRQ, process it later */ 537 azx_dev->irq_pending = 1; 538 queue_work(chip->bus->workq, &hda->irq_pending_work); 539 } 540 return 0; 541 } 542 543 /* 544 * Check whether the current DMA position is acceptable for updating 545 * periods. Returns non-zero if it's OK. 546 * 547 * Many HD-audio controllers appear pretty inaccurate about 548 * the update-IRQ timing. The IRQ is issued before actually the 549 * data is processed. So, we need to process it afterwords in a 550 * workqueue. 551 */ 552 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev) 553 { 554 struct snd_pcm_substream *substream = azx_dev->substream; 555 int stream = substream->stream; 556 u32 wallclk; 557 unsigned int pos; 558 559 wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk; 560 if (wallclk < (azx_dev->period_wallclk * 2) / 3) 561 return -1; /* bogus (too early) interrupt */ 562 563 if (chip->get_position[stream]) 564 pos = chip->get_position[stream](chip, azx_dev); 565 else { /* use the position buffer as default */ 566 pos = azx_get_pos_posbuf(chip, azx_dev); 567 if (!pos || pos == (u32)-1) { 568 dev_info(chip->card->dev, 569 "Invalid position buffer, using LPIB read method instead.\n"); 570 chip->get_position[stream] = azx_get_pos_lpib; 571 pos = azx_get_pos_lpib(chip, azx_dev); 572 chip->get_delay[stream] = NULL; 573 } else { 574 chip->get_position[stream] = azx_get_pos_posbuf; 575 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY) 576 chip->get_delay[stream] = azx_get_delay_from_lpib; 577 } 578 } 579 580 if (pos >= azx_dev->bufsize) 581 pos = 0; 582 583 if (WARN_ONCE(!azx_dev->period_bytes, 584 "hda-intel: zero azx_dev->period_bytes")) 585 return -1; /* this shouldn't happen! */ 586 if (wallclk < (azx_dev->period_wallclk * 5) / 4 && 587 pos % azx_dev->period_bytes > azx_dev->period_bytes / 2) 588 /* NG - it's below the first next period boundary */ 589 return chip->bdl_pos_adj[chip->dev_index] ? 0 : -1; 590 azx_dev->start_wallclk += wallclk; 591 return 1; /* OK, it's fine */ 592 } 593 594 /* 595 * The work for pending PCM period updates. 596 */ 597 static void azx_irq_pending_work(struct work_struct *work) 598 { 599 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work); 600 struct azx *chip = &hda->chip; 601 int i, pending, ok; 602 603 if (!hda->irq_pending_warned) { 604 dev_info(chip->card->dev, 605 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n", 606 chip->card->number); 607 hda->irq_pending_warned = 1; 608 } 609 610 for (;;) { 611 pending = 0; 612 spin_lock_irq(&chip->reg_lock); 613 for (i = 0; i < chip->num_streams; i++) { 614 struct azx_dev *azx_dev = &chip->azx_dev[i]; 615 if (!azx_dev->irq_pending || 616 !azx_dev->substream || 617 !azx_dev->running) 618 continue; 619 ok = azx_position_ok(chip, azx_dev); 620 if (ok > 0) { 621 azx_dev->irq_pending = 0; 622 spin_unlock(&chip->reg_lock); 623 snd_pcm_period_elapsed(azx_dev->substream); 624 spin_lock(&chip->reg_lock); 625 } else if (ok < 0) { 626 pending = 0; /* too early */ 627 } else 628 pending++; 629 } 630 spin_unlock_irq(&chip->reg_lock); 631 if (!pending) 632 return; 633 msleep(1); 634 } 635 } 636 637 /* clear irq_pending flags and assure no on-going workq */ 638 static void azx_clear_irq_pending(struct azx *chip) 639 { 640 int i; 641 642 spin_lock_irq(&chip->reg_lock); 643 for (i = 0; i < chip->num_streams; i++) 644 chip->azx_dev[i].irq_pending = 0; 645 spin_unlock_irq(&chip->reg_lock); 646 } 647 648 static int azx_acquire_irq(struct azx *chip, int do_disconnect) 649 { 650 if (request_irq(chip->pci->irq, azx_interrupt, 651 chip->msi ? 0 : IRQF_SHARED, 652 KBUILD_MODNAME, chip)) { 653 dev_err(chip->card->dev, 654 "unable to grab IRQ %d, disabling device\n", 655 chip->pci->irq); 656 if (do_disconnect) 657 snd_card_disconnect(chip->card); 658 return -1; 659 } 660 chip->irq = chip->pci->irq; 661 pci_intx(chip->pci, !chip->msi); 662 return 0; 663 } 664 665 /* get the current DMA position with correction on VIA chips */ 666 static unsigned int azx_via_get_position(struct azx *chip, 667 struct azx_dev *azx_dev) 668 { 669 unsigned int link_pos, mini_pos, bound_pos; 670 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos; 671 unsigned int fifo_size; 672 673 link_pos = azx_sd_readl(chip, azx_dev, SD_LPIB); 674 if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 675 /* Playback, no problem using link position */ 676 return link_pos; 677 } 678 679 /* Capture */ 680 /* For new chipset, 681 * use mod to get the DMA position just like old chipset 682 */ 683 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf); 684 mod_dma_pos %= azx_dev->period_bytes; 685 686 /* azx_dev->fifo_size can't get FIFO size of in stream. 687 * Get from base address + offset. 688 */ 689 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET); 690 691 if (azx_dev->insufficient) { 692 /* Link position never gather than FIFO size */ 693 if (link_pos <= fifo_size) 694 return 0; 695 696 azx_dev->insufficient = 0; 697 } 698 699 if (link_pos <= fifo_size) 700 mini_pos = azx_dev->bufsize + link_pos - fifo_size; 701 else 702 mini_pos = link_pos - fifo_size; 703 704 /* Find nearest previous boudary */ 705 mod_mini_pos = mini_pos % azx_dev->period_bytes; 706 mod_link_pos = link_pos % azx_dev->period_bytes; 707 if (mod_link_pos >= fifo_size) 708 bound_pos = link_pos - mod_link_pos; 709 else if (mod_dma_pos >= mod_mini_pos) 710 bound_pos = mini_pos - mod_mini_pos; 711 else { 712 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes; 713 if (bound_pos >= azx_dev->bufsize) 714 bound_pos = 0; 715 } 716 717 /* Calculate real DMA position we want */ 718 return bound_pos + mod_dma_pos; 719 } 720 721 #ifdef CONFIG_PM 722 static DEFINE_MUTEX(card_list_lock); 723 static LIST_HEAD(card_list); 724 725 static void azx_add_card_list(struct azx *chip) 726 { 727 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 728 mutex_lock(&card_list_lock); 729 list_add(&hda->list, &card_list); 730 mutex_unlock(&card_list_lock); 731 } 732 733 static void azx_del_card_list(struct azx *chip) 734 { 735 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 736 mutex_lock(&card_list_lock); 737 list_del_init(&hda->list); 738 mutex_unlock(&card_list_lock); 739 } 740 741 /* trigger power-save check at writing parameter */ 742 static int param_set_xint(const char *val, const struct kernel_param *kp) 743 { 744 struct hda_intel *hda; 745 struct azx *chip; 746 struct hda_codec *c; 747 int prev = power_save; 748 int ret = param_set_int(val, kp); 749 750 if (ret || prev == power_save) 751 return ret; 752 753 mutex_lock(&card_list_lock); 754 list_for_each_entry(hda, &card_list, list) { 755 chip = &hda->chip; 756 if (!chip->bus || chip->disabled) 757 continue; 758 list_for_each_entry(c, &chip->bus->codec_list, list) 759 snd_hda_power_sync(c); 760 } 761 mutex_unlock(&card_list_lock); 762 return 0; 763 } 764 #else 765 #define azx_add_card_list(chip) /* NOP */ 766 #define azx_del_card_list(chip) /* NOP */ 767 #endif /* CONFIG_PM */ 768 769 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO) 770 /* 771 * power management 772 */ 773 static int azx_suspend(struct device *dev) 774 { 775 struct pci_dev *pci = to_pci_dev(dev); 776 struct snd_card *card = dev_get_drvdata(dev); 777 struct azx *chip; 778 struct hda_intel *hda; 779 struct azx_pcm *p; 780 781 if (!card) 782 return 0; 783 784 chip = card->private_data; 785 hda = container_of(chip, struct hda_intel, chip); 786 if (chip->disabled || hda->init_failed) 787 return 0; 788 789 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 790 azx_clear_irq_pending(chip); 791 list_for_each_entry(p, &chip->pcm_list, list) 792 snd_pcm_suspend_all(p->pcm); 793 if (chip->initialized) 794 snd_hda_suspend(chip->bus); 795 azx_stop_chip(chip); 796 azx_enter_link_reset(chip); 797 if (chip->irq >= 0) { 798 free_irq(chip->irq, chip); 799 chip->irq = -1; 800 } 801 802 if (chip->msi) 803 pci_disable_msi(chip->pci); 804 pci_disable_device(pci); 805 pci_save_state(pci); 806 pci_set_power_state(pci, PCI_D3hot); 807 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) 808 hda_display_power(false); 809 return 0; 810 } 811 812 static int azx_resume(struct device *dev) 813 { 814 struct pci_dev *pci = to_pci_dev(dev); 815 struct snd_card *card = dev_get_drvdata(dev); 816 struct azx *chip; 817 struct hda_intel *hda; 818 819 if (!card) 820 return 0; 821 822 chip = card->private_data; 823 hda = container_of(chip, struct hda_intel, chip); 824 if (chip->disabled || hda->init_failed) 825 return 0; 826 827 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) { 828 hda_display_power(true); 829 haswell_set_bclk(chip); 830 } 831 pci_set_power_state(pci, PCI_D0); 832 pci_restore_state(pci); 833 if (pci_enable_device(pci) < 0) { 834 dev_err(chip->card->dev, 835 "pci_enable_device failed, disabling device\n"); 836 snd_card_disconnect(card); 837 return -EIO; 838 } 839 pci_set_master(pci); 840 if (chip->msi) 841 if (pci_enable_msi(pci) < 0) 842 chip->msi = 0; 843 if (azx_acquire_irq(chip, 1) < 0) 844 return -EIO; 845 azx_init_pci(chip); 846 847 azx_init_chip(chip, true); 848 849 snd_hda_resume(chip->bus); 850 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 851 return 0; 852 } 853 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */ 854 855 #ifdef CONFIG_PM_RUNTIME 856 static int azx_runtime_suspend(struct device *dev) 857 { 858 struct snd_card *card = dev_get_drvdata(dev); 859 struct azx *chip; 860 struct hda_intel *hda; 861 862 if (!card) 863 return 0; 864 865 chip = card->private_data; 866 hda = container_of(chip, struct hda_intel, chip); 867 if (chip->disabled || hda->init_failed) 868 return 0; 869 870 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME)) 871 return 0; 872 873 /* enable controller wake up event */ 874 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) | 875 STATESTS_INT_MASK); 876 877 azx_stop_chip(chip); 878 azx_enter_link_reset(chip); 879 azx_clear_irq_pending(chip); 880 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) 881 hda_display_power(false); 882 883 return 0; 884 } 885 886 static int azx_runtime_resume(struct device *dev) 887 { 888 struct snd_card *card = dev_get_drvdata(dev); 889 struct azx *chip; 890 struct hda_intel *hda; 891 struct hda_bus *bus; 892 struct hda_codec *codec; 893 int status; 894 895 if (!card) 896 return 0; 897 898 chip = card->private_data; 899 hda = container_of(chip, struct hda_intel, chip); 900 if (chip->disabled || hda->init_failed) 901 return 0; 902 903 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME)) 904 return 0; 905 906 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) { 907 hda_display_power(true); 908 haswell_set_bclk(chip); 909 } 910 911 /* Read STATESTS before controller reset */ 912 status = azx_readw(chip, STATESTS); 913 914 azx_init_pci(chip); 915 azx_init_chip(chip, true); 916 917 bus = chip->bus; 918 if (status && bus) { 919 list_for_each_entry(codec, &bus->codec_list, list) 920 if (status & (1 << codec->addr)) 921 queue_delayed_work(codec->bus->workq, 922 &codec->jackpoll_work, codec->jackpoll_interval); 923 } 924 925 /* disable controller Wake Up event*/ 926 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) & 927 ~STATESTS_INT_MASK); 928 929 return 0; 930 } 931 932 static int azx_runtime_idle(struct device *dev) 933 { 934 struct snd_card *card = dev_get_drvdata(dev); 935 struct azx *chip; 936 struct hda_intel *hda; 937 938 if (!card) 939 return 0; 940 941 chip = card->private_data; 942 hda = container_of(chip, struct hda_intel, chip); 943 if (chip->disabled || hda->init_failed) 944 return 0; 945 946 if (!power_save_controller || 947 !(chip->driver_caps & AZX_DCAPS_PM_RUNTIME)) 948 return -EBUSY; 949 950 return 0; 951 } 952 953 #endif /* CONFIG_PM_RUNTIME */ 954 955 #ifdef CONFIG_PM 956 static const struct dev_pm_ops azx_pm = { 957 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume) 958 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle) 959 }; 960 961 #define AZX_PM_OPS &azx_pm 962 #else 963 #define AZX_PM_OPS NULL 964 #endif /* CONFIG_PM */ 965 966 967 static int azx_probe_continue(struct azx *chip); 968 969 #ifdef SUPPORT_VGA_SWITCHEROO 970 static struct pci_dev *get_bound_vga(struct pci_dev *pci); 971 972 static void azx_vs_set_state(struct pci_dev *pci, 973 enum vga_switcheroo_state state) 974 { 975 struct snd_card *card = pci_get_drvdata(pci); 976 struct azx *chip = card->private_data; 977 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 978 bool disabled; 979 980 wait_for_completion(&hda->probe_wait); 981 if (hda->init_failed) 982 return; 983 984 disabled = (state == VGA_SWITCHEROO_OFF); 985 if (chip->disabled == disabled) 986 return; 987 988 if (!chip->bus) { 989 chip->disabled = disabled; 990 if (!disabled) { 991 dev_info(chip->card->dev, 992 "Start delayed initialization\n"); 993 if (azx_probe_continue(chip) < 0) { 994 dev_err(chip->card->dev, "initialization error\n"); 995 hda->init_failed = true; 996 } 997 } 998 } else { 999 dev_info(chip->card->dev, "%s via VGA-switcheroo\n", 1000 disabled ? "Disabling" : "Enabling"); 1001 if (disabled) { 1002 pm_runtime_put_sync_suspend(card->dev); 1003 azx_suspend(card->dev); 1004 /* when we get suspended by vga switcheroo we end up in D3cold, 1005 * however we have no ACPI handle, so pci/acpi can't put us there, 1006 * put ourselves there */ 1007 pci->current_state = PCI_D3cold; 1008 chip->disabled = true; 1009 if (snd_hda_lock_devices(chip->bus)) 1010 dev_warn(chip->card->dev, 1011 "Cannot lock devices!\n"); 1012 } else { 1013 snd_hda_unlock_devices(chip->bus); 1014 pm_runtime_get_noresume(card->dev); 1015 chip->disabled = false; 1016 azx_resume(card->dev); 1017 } 1018 } 1019 } 1020 1021 static bool azx_vs_can_switch(struct pci_dev *pci) 1022 { 1023 struct snd_card *card = pci_get_drvdata(pci); 1024 struct azx *chip = card->private_data; 1025 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1026 1027 wait_for_completion(&hda->probe_wait); 1028 if (hda->init_failed) 1029 return false; 1030 if (chip->disabled || !chip->bus) 1031 return true; 1032 if (snd_hda_lock_devices(chip->bus)) 1033 return false; 1034 snd_hda_unlock_devices(chip->bus); 1035 return true; 1036 } 1037 1038 static void init_vga_switcheroo(struct azx *chip) 1039 { 1040 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1041 struct pci_dev *p = get_bound_vga(chip->pci); 1042 if (p) { 1043 dev_info(chip->card->dev, 1044 "Handle VGA-switcheroo audio client\n"); 1045 hda->use_vga_switcheroo = 1; 1046 pci_dev_put(p); 1047 } 1048 } 1049 1050 static const struct vga_switcheroo_client_ops azx_vs_ops = { 1051 .set_gpu_state = azx_vs_set_state, 1052 .can_switch = azx_vs_can_switch, 1053 }; 1054 1055 static int register_vga_switcheroo(struct azx *chip) 1056 { 1057 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1058 int err; 1059 1060 if (!hda->use_vga_switcheroo) 1061 return 0; 1062 /* FIXME: currently only handling DIS controller 1063 * is there any machine with two switchable HDMI audio controllers? 1064 */ 1065 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, 1066 VGA_SWITCHEROO_DIS, 1067 chip->bus != NULL); 1068 if (err < 0) 1069 return err; 1070 hda->vga_switcheroo_registered = 1; 1071 1072 /* register as an optimus hdmi audio power domain */ 1073 vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev, 1074 &hda->hdmi_pm_domain); 1075 return 0; 1076 } 1077 #else 1078 #define init_vga_switcheroo(chip) /* NOP */ 1079 #define register_vga_switcheroo(chip) 0 1080 #define check_hdmi_disabled(pci) false 1081 #endif /* SUPPORT_VGA_SWITCHER */ 1082 1083 /* 1084 * destructor 1085 */ 1086 static int azx_free(struct azx *chip) 1087 { 1088 struct pci_dev *pci = chip->pci; 1089 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1090 int i; 1091 1092 if ((chip->driver_caps & AZX_DCAPS_PM_RUNTIME) 1093 && chip->running) 1094 pm_runtime_get_noresume(&pci->dev); 1095 1096 azx_del_card_list(chip); 1097 1098 azx_notifier_unregister(chip); 1099 1100 hda->init_failed = 1; /* to be sure */ 1101 complete_all(&hda->probe_wait); 1102 1103 if (use_vga_switcheroo(hda)) { 1104 if (chip->disabled && chip->bus) 1105 snd_hda_unlock_devices(chip->bus); 1106 if (hda->vga_switcheroo_registered) 1107 vga_switcheroo_unregister_client(chip->pci); 1108 } 1109 1110 if (chip->initialized) { 1111 azx_clear_irq_pending(chip); 1112 for (i = 0; i < chip->num_streams; i++) 1113 azx_stream_stop(chip, &chip->azx_dev[i]); 1114 azx_stop_chip(chip); 1115 } 1116 1117 if (chip->irq >= 0) 1118 free_irq(chip->irq, (void*)chip); 1119 if (chip->msi) 1120 pci_disable_msi(chip->pci); 1121 if (chip->remap_addr) 1122 iounmap(chip->remap_addr); 1123 1124 azx_free_stream_pages(chip); 1125 if (chip->region_requested) 1126 pci_release_regions(chip->pci); 1127 pci_disable_device(chip->pci); 1128 kfree(chip->azx_dev); 1129 #ifdef CONFIG_SND_HDA_PATCH_LOADER 1130 if (chip->fw) 1131 release_firmware(chip->fw); 1132 #endif 1133 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) { 1134 hda_display_power(false); 1135 hda_i915_exit(); 1136 } 1137 kfree(hda); 1138 1139 return 0; 1140 } 1141 1142 static int azx_dev_free(struct snd_device *device) 1143 { 1144 return azx_free(device->device_data); 1145 } 1146 1147 #ifdef SUPPORT_VGA_SWITCHEROO 1148 /* 1149 * Check of disabled HDMI controller by vga-switcheroo 1150 */ 1151 static struct pci_dev *get_bound_vga(struct pci_dev *pci) 1152 { 1153 struct pci_dev *p; 1154 1155 /* check only discrete GPU */ 1156 switch (pci->vendor) { 1157 case PCI_VENDOR_ID_ATI: 1158 case PCI_VENDOR_ID_AMD: 1159 case PCI_VENDOR_ID_NVIDIA: 1160 if (pci->devfn == 1) { 1161 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus), 1162 pci->bus->number, 0); 1163 if (p) { 1164 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA) 1165 return p; 1166 pci_dev_put(p); 1167 } 1168 } 1169 break; 1170 } 1171 return NULL; 1172 } 1173 1174 static bool check_hdmi_disabled(struct pci_dev *pci) 1175 { 1176 bool vga_inactive = false; 1177 struct pci_dev *p = get_bound_vga(pci); 1178 1179 if (p) { 1180 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF) 1181 vga_inactive = true; 1182 pci_dev_put(p); 1183 } 1184 return vga_inactive; 1185 } 1186 #endif /* SUPPORT_VGA_SWITCHEROO */ 1187 1188 /* 1189 * white/black-listing for position_fix 1190 */ 1191 static struct snd_pci_quirk position_fix_list[] = { 1192 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB), 1193 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB), 1194 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB), 1195 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB), 1196 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB), 1197 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB), 1198 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB), 1199 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB), 1200 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB), 1201 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB), 1202 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB), 1203 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB), 1204 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB), 1205 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB), 1206 {} 1207 }; 1208 1209 static int check_position_fix(struct azx *chip, int fix) 1210 { 1211 const struct snd_pci_quirk *q; 1212 1213 switch (fix) { 1214 case POS_FIX_AUTO: 1215 case POS_FIX_LPIB: 1216 case POS_FIX_POSBUF: 1217 case POS_FIX_VIACOMBO: 1218 case POS_FIX_COMBO: 1219 return fix; 1220 } 1221 1222 q = snd_pci_quirk_lookup(chip->pci, position_fix_list); 1223 if (q) { 1224 dev_info(chip->card->dev, 1225 "position_fix set to %d for device %04x:%04x\n", 1226 q->value, q->subvendor, q->subdevice); 1227 return q->value; 1228 } 1229 1230 /* Check VIA/ATI HD Audio Controller exist */ 1231 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) { 1232 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n"); 1233 return POS_FIX_VIACOMBO; 1234 } 1235 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) { 1236 dev_dbg(chip->card->dev, "Using LPIB position fix\n"); 1237 return POS_FIX_LPIB; 1238 } 1239 return POS_FIX_AUTO; 1240 } 1241 1242 static void assign_position_fix(struct azx *chip, int fix) 1243 { 1244 static azx_get_pos_callback_t callbacks[] = { 1245 [POS_FIX_AUTO] = NULL, 1246 [POS_FIX_LPIB] = azx_get_pos_lpib, 1247 [POS_FIX_POSBUF] = azx_get_pos_posbuf, 1248 [POS_FIX_VIACOMBO] = azx_via_get_position, 1249 [POS_FIX_COMBO] = azx_get_pos_lpib, 1250 }; 1251 1252 chip->get_position[0] = chip->get_position[1] = callbacks[fix]; 1253 1254 /* combo mode uses LPIB only for playback */ 1255 if (fix == POS_FIX_COMBO) 1256 chip->get_position[1] = NULL; 1257 1258 if (fix == POS_FIX_POSBUF && 1259 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) { 1260 chip->get_delay[0] = chip->get_delay[1] = 1261 azx_get_delay_from_lpib; 1262 } 1263 1264 } 1265 1266 /* 1267 * black-lists for probe_mask 1268 */ 1269 static struct snd_pci_quirk probe_mask_list[] = { 1270 /* Thinkpad often breaks the controller communication when accessing 1271 * to the non-working (or non-existing) modem codec slot. 1272 */ 1273 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01), 1274 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01), 1275 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01), 1276 /* broken BIOS */ 1277 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01), 1278 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */ 1279 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01), 1280 /* forced codec slots */ 1281 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103), 1282 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103), 1283 /* WinFast VP200 H (Teradici) user reported broken communication */ 1284 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101), 1285 {} 1286 }; 1287 1288 #define AZX_FORCE_CODEC_MASK 0x100 1289 1290 static void check_probe_mask(struct azx *chip, int dev) 1291 { 1292 const struct snd_pci_quirk *q; 1293 1294 chip->codec_probe_mask = probe_mask[dev]; 1295 if (chip->codec_probe_mask == -1) { 1296 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list); 1297 if (q) { 1298 dev_info(chip->card->dev, 1299 "probe_mask set to 0x%x for device %04x:%04x\n", 1300 q->value, q->subvendor, q->subdevice); 1301 chip->codec_probe_mask = q->value; 1302 } 1303 } 1304 1305 /* check forced option */ 1306 if (chip->codec_probe_mask != -1 && 1307 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) { 1308 chip->codec_mask = chip->codec_probe_mask & 0xff; 1309 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n", 1310 chip->codec_mask); 1311 } 1312 } 1313 1314 /* 1315 * white/black-list for enable_msi 1316 */ 1317 static struct snd_pci_quirk msi_black_list[] = { 1318 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */ 1319 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */ 1320 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */ 1321 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */ 1322 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */ 1323 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */ 1324 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */ 1325 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */ 1326 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */ 1327 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */ 1328 {} 1329 }; 1330 1331 static void check_msi(struct azx *chip) 1332 { 1333 const struct snd_pci_quirk *q; 1334 1335 if (enable_msi >= 0) { 1336 chip->msi = !!enable_msi; 1337 return; 1338 } 1339 chip->msi = 1; /* enable MSI as default */ 1340 q = snd_pci_quirk_lookup(chip->pci, msi_black_list); 1341 if (q) { 1342 dev_info(chip->card->dev, 1343 "msi for device %04x:%04x set to %d\n", 1344 q->subvendor, q->subdevice, q->value); 1345 chip->msi = q->value; 1346 return; 1347 } 1348 1349 /* NVidia chipsets seem to cause troubles with MSI */ 1350 if (chip->driver_caps & AZX_DCAPS_NO_MSI) { 1351 dev_info(chip->card->dev, "Disabling MSI\n"); 1352 chip->msi = 0; 1353 } 1354 } 1355 1356 /* check the snoop mode availability */ 1357 static void azx_check_snoop_available(struct azx *chip) 1358 { 1359 bool snoop = chip->snoop; 1360 1361 switch (chip->driver_type) { 1362 case AZX_DRIVER_VIA: 1363 /* force to non-snoop mode for a new VIA controller 1364 * when BIOS is set 1365 */ 1366 if (snoop) { 1367 u8 val; 1368 pci_read_config_byte(chip->pci, 0x42, &val); 1369 if (!(val & 0x80) && chip->pci->revision == 0x30) 1370 snoop = false; 1371 } 1372 break; 1373 case AZX_DRIVER_ATIHDMI_NS: 1374 /* new ATI HDMI requires non-snoop */ 1375 snoop = false; 1376 break; 1377 case AZX_DRIVER_CTHDA: 1378 case AZX_DRIVER_CMEDIA: 1379 snoop = false; 1380 break; 1381 } 1382 1383 if (snoop != chip->snoop) { 1384 dev_info(chip->card->dev, "Force to %s mode\n", 1385 snoop ? "snoop" : "non-snoop"); 1386 chip->snoop = snoop; 1387 } 1388 } 1389 1390 static void azx_probe_work(struct work_struct *work) 1391 { 1392 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work); 1393 azx_probe_continue(&hda->chip); 1394 } 1395 1396 /* 1397 * constructor 1398 */ 1399 static int azx_create(struct snd_card *card, struct pci_dev *pci, 1400 int dev, unsigned int driver_caps, 1401 const struct hda_controller_ops *hda_ops, 1402 struct azx **rchip) 1403 { 1404 static struct snd_device_ops ops = { 1405 .dev_free = azx_dev_free, 1406 }; 1407 struct hda_intel *hda; 1408 struct azx *chip; 1409 int err; 1410 1411 *rchip = NULL; 1412 1413 err = pci_enable_device(pci); 1414 if (err < 0) 1415 return err; 1416 1417 hda = kzalloc(sizeof(*hda), GFP_KERNEL); 1418 if (!hda) { 1419 dev_err(card->dev, "Cannot allocate hda\n"); 1420 pci_disable_device(pci); 1421 return -ENOMEM; 1422 } 1423 1424 chip = &hda->chip; 1425 spin_lock_init(&chip->reg_lock); 1426 mutex_init(&chip->open_mutex); 1427 chip->card = card; 1428 chip->pci = pci; 1429 chip->ops = hda_ops; 1430 chip->irq = -1; 1431 chip->driver_caps = driver_caps; 1432 chip->driver_type = driver_caps & 0xff; 1433 check_msi(chip); 1434 chip->dev_index = dev; 1435 chip->jackpoll_ms = jackpoll_ms; 1436 INIT_LIST_HEAD(&chip->pcm_list); 1437 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work); 1438 INIT_LIST_HEAD(&hda->list); 1439 init_vga_switcheroo(chip); 1440 init_completion(&hda->probe_wait); 1441 1442 assign_position_fix(chip, check_position_fix(chip, position_fix[dev])); 1443 1444 check_probe_mask(chip, dev); 1445 1446 chip->single_cmd = single_cmd; 1447 chip->snoop = hda_snoop; 1448 azx_check_snoop_available(chip); 1449 1450 if (bdl_pos_adj[dev] < 0) { 1451 switch (chip->driver_type) { 1452 case AZX_DRIVER_ICH: 1453 case AZX_DRIVER_PCH: 1454 bdl_pos_adj[dev] = 1; 1455 break; 1456 default: 1457 bdl_pos_adj[dev] = 32; 1458 break; 1459 } 1460 } 1461 chip->bdl_pos_adj = bdl_pos_adj; 1462 1463 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); 1464 if (err < 0) { 1465 dev_err(card->dev, "Error creating device [card]!\n"); 1466 azx_free(chip); 1467 return err; 1468 } 1469 1470 /* continue probing in work context as may trigger request module */ 1471 INIT_WORK(&hda->probe_work, azx_probe_work); 1472 1473 *rchip = chip; 1474 1475 return 0; 1476 } 1477 1478 static int azx_first_init(struct azx *chip) 1479 { 1480 int dev = chip->dev_index; 1481 struct pci_dev *pci = chip->pci; 1482 struct snd_card *card = chip->card; 1483 int err; 1484 unsigned short gcap; 1485 1486 #if BITS_PER_LONG != 64 1487 /* Fix up base address on ULI M5461 */ 1488 if (chip->driver_type == AZX_DRIVER_ULI) { 1489 u16 tmp3; 1490 pci_read_config_word(pci, 0x40, &tmp3); 1491 pci_write_config_word(pci, 0x40, tmp3 | 0x10); 1492 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0); 1493 } 1494 #endif 1495 1496 err = pci_request_regions(pci, "ICH HD audio"); 1497 if (err < 0) 1498 return err; 1499 chip->region_requested = 1; 1500 1501 chip->addr = pci_resource_start(pci, 0); 1502 chip->remap_addr = pci_ioremap_bar(pci, 0); 1503 if (chip->remap_addr == NULL) { 1504 dev_err(card->dev, "ioremap error\n"); 1505 return -ENXIO; 1506 } 1507 1508 if (chip->msi) 1509 if (pci_enable_msi(pci) < 0) 1510 chip->msi = 0; 1511 1512 if (azx_acquire_irq(chip, 0) < 0) 1513 return -EBUSY; 1514 1515 pci_set_master(pci); 1516 synchronize_irq(chip->irq); 1517 1518 gcap = azx_readw(chip, GCAP); 1519 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap); 1520 1521 /* disable SB600 64bit support for safety */ 1522 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) { 1523 struct pci_dev *p_smbus; 1524 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI, 1525 PCI_DEVICE_ID_ATI_SBX00_SMBUS, 1526 NULL); 1527 if (p_smbus) { 1528 if (p_smbus->revision < 0x30) 1529 gcap &= ~AZX_GCAP_64OK; 1530 pci_dev_put(p_smbus); 1531 } 1532 } 1533 1534 /* disable 64bit DMA address on some devices */ 1535 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) { 1536 dev_dbg(card->dev, "Disabling 64bit DMA\n"); 1537 gcap &= ~AZX_GCAP_64OK; 1538 } 1539 1540 /* disable buffer size rounding to 128-byte multiples if supported */ 1541 if (align_buffer_size >= 0) 1542 chip->align_buffer_size = !!align_buffer_size; 1543 else { 1544 if (chip->driver_caps & AZX_DCAPS_BUFSIZE) 1545 chip->align_buffer_size = 0; 1546 else if (chip->driver_caps & AZX_DCAPS_ALIGN_BUFSIZE) 1547 chip->align_buffer_size = 1; 1548 else 1549 chip->align_buffer_size = 1; 1550 } 1551 1552 /* allow 64bit DMA address if supported by H/W */ 1553 if ((gcap & AZX_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64))) 1554 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64)); 1555 else { 1556 pci_set_dma_mask(pci, DMA_BIT_MASK(32)); 1557 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32)); 1558 } 1559 1560 /* read number of streams from GCAP register instead of using 1561 * hardcoded value 1562 */ 1563 chip->capture_streams = (gcap >> 8) & 0x0f; 1564 chip->playback_streams = (gcap >> 12) & 0x0f; 1565 if (!chip->playback_streams && !chip->capture_streams) { 1566 /* gcap didn't give any info, switching to old method */ 1567 1568 switch (chip->driver_type) { 1569 case AZX_DRIVER_ULI: 1570 chip->playback_streams = ULI_NUM_PLAYBACK; 1571 chip->capture_streams = ULI_NUM_CAPTURE; 1572 break; 1573 case AZX_DRIVER_ATIHDMI: 1574 case AZX_DRIVER_ATIHDMI_NS: 1575 chip->playback_streams = ATIHDMI_NUM_PLAYBACK; 1576 chip->capture_streams = ATIHDMI_NUM_CAPTURE; 1577 break; 1578 case AZX_DRIVER_GENERIC: 1579 default: 1580 chip->playback_streams = ICH6_NUM_PLAYBACK; 1581 chip->capture_streams = ICH6_NUM_CAPTURE; 1582 break; 1583 } 1584 } 1585 chip->capture_index_offset = 0; 1586 chip->playback_index_offset = chip->capture_streams; 1587 chip->num_streams = chip->playback_streams + chip->capture_streams; 1588 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev), 1589 GFP_KERNEL); 1590 if (!chip->azx_dev) { 1591 dev_err(card->dev, "cannot malloc azx_dev\n"); 1592 return -ENOMEM; 1593 } 1594 1595 err = azx_alloc_stream_pages(chip); 1596 if (err < 0) 1597 return err; 1598 1599 /* initialize streams */ 1600 azx_init_stream(chip); 1601 1602 /* initialize chip */ 1603 azx_init_pci(chip); 1604 1605 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) 1606 haswell_set_bclk(chip); 1607 1608 azx_init_chip(chip, (probe_only[dev] & 2) == 0); 1609 1610 /* codec detection */ 1611 if (!chip->codec_mask) { 1612 dev_err(card->dev, "no codecs found!\n"); 1613 return -ENODEV; 1614 } 1615 1616 strcpy(card->driver, "HDA-Intel"); 1617 strlcpy(card->shortname, driver_short_names[chip->driver_type], 1618 sizeof(card->shortname)); 1619 snprintf(card->longname, sizeof(card->longname), 1620 "%s at 0x%lx irq %i", 1621 card->shortname, chip->addr, chip->irq); 1622 1623 return 0; 1624 } 1625 1626 static void power_down_all_codecs(struct azx *chip) 1627 { 1628 #ifdef CONFIG_PM 1629 /* The codecs were powered up in snd_hda_codec_new(). 1630 * Now all initialization done, so turn them down if possible 1631 */ 1632 struct hda_codec *codec; 1633 list_for_each_entry(codec, &chip->bus->codec_list, list) { 1634 snd_hda_power_down(codec); 1635 } 1636 #endif 1637 } 1638 1639 #ifdef CONFIG_SND_HDA_PATCH_LOADER 1640 /* callback from request_firmware_nowait() */ 1641 static void azx_firmware_cb(const struct firmware *fw, void *context) 1642 { 1643 struct snd_card *card = context; 1644 struct azx *chip = card->private_data; 1645 struct pci_dev *pci = chip->pci; 1646 1647 if (!fw) { 1648 dev_err(card->dev, "Cannot load firmware, aborting\n"); 1649 goto error; 1650 } 1651 1652 chip->fw = fw; 1653 if (!chip->disabled) { 1654 /* continue probing */ 1655 if (azx_probe_continue(chip)) 1656 goto error; 1657 } 1658 return; /* OK */ 1659 1660 error: 1661 snd_card_free(card); 1662 pci_set_drvdata(pci, NULL); 1663 } 1664 #endif 1665 1666 /* 1667 * HDA controller ops. 1668 */ 1669 1670 /* PCI register access. */ 1671 static void pci_azx_writel(u32 value, u32 __iomem *addr) 1672 { 1673 writel(value, addr); 1674 } 1675 1676 static u32 pci_azx_readl(u32 __iomem *addr) 1677 { 1678 return readl(addr); 1679 } 1680 1681 static void pci_azx_writew(u16 value, u16 __iomem *addr) 1682 { 1683 writew(value, addr); 1684 } 1685 1686 static u16 pci_azx_readw(u16 __iomem *addr) 1687 { 1688 return readw(addr); 1689 } 1690 1691 static void pci_azx_writeb(u8 value, u8 __iomem *addr) 1692 { 1693 writeb(value, addr); 1694 } 1695 1696 static u8 pci_azx_readb(u8 __iomem *addr) 1697 { 1698 return readb(addr); 1699 } 1700 1701 static int disable_msi_reset_irq(struct azx *chip) 1702 { 1703 int err; 1704 1705 free_irq(chip->irq, chip); 1706 chip->irq = -1; 1707 pci_disable_msi(chip->pci); 1708 chip->msi = 0; 1709 err = azx_acquire_irq(chip, 1); 1710 if (err < 0) 1711 return err; 1712 1713 return 0; 1714 } 1715 1716 /* DMA page allocation helpers. */ 1717 static int dma_alloc_pages(struct azx *chip, 1718 int type, 1719 size_t size, 1720 struct snd_dma_buffer *buf) 1721 { 1722 int err; 1723 1724 err = snd_dma_alloc_pages(type, 1725 chip->card->dev, 1726 size, buf); 1727 if (err < 0) 1728 return err; 1729 mark_pages_wc(chip, buf, true); 1730 return 0; 1731 } 1732 1733 static void dma_free_pages(struct azx *chip, struct snd_dma_buffer *buf) 1734 { 1735 mark_pages_wc(chip, buf, false); 1736 snd_dma_free_pages(buf); 1737 } 1738 1739 static int substream_alloc_pages(struct azx *chip, 1740 struct snd_pcm_substream *substream, 1741 size_t size) 1742 { 1743 struct azx_dev *azx_dev = get_azx_dev(substream); 1744 int ret; 1745 1746 mark_runtime_wc(chip, azx_dev, substream, false); 1747 azx_dev->bufsize = 0; 1748 azx_dev->period_bytes = 0; 1749 azx_dev->format_val = 0; 1750 ret = snd_pcm_lib_malloc_pages(substream, size); 1751 if (ret < 0) 1752 return ret; 1753 mark_runtime_wc(chip, azx_dev, substream, true); 1754 return 0; 1755 } 1756 1757 static int substream_free_pages(struct azx *chip, 1758 struct snd_pcm_substream *substream) 1759 { 1760 struct azx_dev *azx_dev = get_azx_dev(substream); 1761 mark_runtime_wc(chip, azx_dev, substream, false); 1762 return snd_pcm_lib_free_pages(substream); 1763 } 1764 1765 static void pcm_mmap_prepare(struct snd_pcm_substream *substream, 1766 struct vm_area_struct *area) 1767 { 1768 #ifdef CONFIG_X86 1769 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 1770 struct azx *chip = apcm->chip; 1771 if (!azx_snoop(chip)) 1772 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot); 1773 #endif 1774 } 1775 1776 static const struct hda_controller_ops pci_hda_ops = { 1777 .reg_writel = pci_azx_writel, 1778 .reg_readl = pci_azx_readl, 1779 .reg_writew = pci_azx_writew, 1780 .reg_readw = pci_azx_readw, 1781 .reg_writeb = pci_azx_writeb, 1782 .reg_readb = pci_azx_readb, 1783 .disable_msi_reset_irq = disable_msi_reset_irq, 1784 .dma_alloc_pages = dma_alloc_pages, 1785 .dma_free_pages = dma_free_pages, 1786 .substream_alloc_pages = substream_alloc_pages, 1787 .substream_free_pages = substream_free_pages, 1788 .pcm_mmap_prepare = pcm_mmap_prepare, 1789 .position_check = azx_position_check, 1790 }; 1791 1792 static int azx_probe(struct pci_dev *pci, 1793 const struct pci_device_id *pci_id) 1794 { 1795 static int dev; 1796 struct snd_card *card; 1797 struct hda_intel *hda; 1798 struct azx *chip; 1799 bool schedule_probe; 1800 int err; 1801 1802 if (dev >= SNDRV_CARDS) 1803 return -ENODEV; 1804 if (!enable[dev]) { 1805 dev++; 1806 return -ENOENT; 1807 } 1808 1809 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE, 1810 0, &card); 1811 if (err < 0) { 1812 dev_err(&pci->dev, "Error creating card!\n"); 1813 return err; 1814 } 1815 1816 err = azx_create(card, pci, dev, pci_id->driver_data, 1817 &pci_hda_ops, &chip); 1818 if (err < 0) 1819 goto out_free; 1820 card->private_data = chip; 1821 hda = container_of(chip, struct hda_intel, chip); 1822 1823 pci_set_drvdata(pci, card); 1824 1825 err = register_vga_switcheroo(chip); 1826 if (err < 0) { 1827 dev_err(card->dev, "Error registering VGA-switcheroo client\n"); 1828 goto out_free; 1829 } 1830 1831 if (check_hdmi_disabled(pci)) { 1832 dev_info(card->dev, "VGA controller is disabled\n"); 1833 dev_info(card->dev, "Delaying initialization\n"); 1834 chip->disabled = true; 1835 } 1836 1837 schedule_probe = !chip->disabled; 1838 1839 #ifdef CONFIG_SND_HDA_PATCH_LOADER 1840 if (patch[dev] && *patch[dev]) { 1841 dev_info(card->dev, "Applying patch firmware '%s'\n", 1842 patch[dev]); 1843 err = request_firmware_nowait(THIS_MODULE, true, patch[dev], 1844 &pci->dev, GFP_KERNEL, card, 1845 azx_firmware_cb); 1846 if (err < 0) 1847 goto out_free; 1848 schedule_probe = false; /* continued in azx_firmware_cb() */ 1849 } 1850 #endif /* CONFIG_SND_HDA_PATCH_LOADER */ 1851 1852 #ifndef CONFIG_SND_HDA_I915 1853 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) 1854 dev_err(card->dev, "Haswell must build in CONFIG_SND_HDA_I915\n"); 1855 #endif 1856 1857 if (schedule_probe) 1858 schedule_work(&hda->probe_work); 1859 1860 dev++; 1861 if (chip->disabled) 1862 complete_all(&hda->probe_wait); 1863 return 0; 1864 1865 out_free: 1866 snd_card_free(card); 1867 return err; 1868 } 1869 1870 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */ 1871 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = { 1872 [AZX_DRIVER_NVIDIA] = 8, 1873 [AZX_DRIVER_TERA] = 1, 1874 }; 1875 1876 static int azx_probe_continue(struct azx *chip) 1877 { 1878 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1879 struct pci_dev *pci = chip->pci; 1880 int dev = chip->dev_index; 1881 int err; 1882 1883 /* Request power well for Haswell HDA controller and codec */ 1884 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) { 1885 #ifdef CONFIG_SND_HDA_I915 1886 err = hda_i915_init(); 1887 if (err < 0) { 1888 dev_err(chip->card->dev, 1889 "Error request power-well from i915\n"); 1890 goto out_free; 1891 } 1892 err = hda_display_power(true); 1893 if (err < 0) { 1894 dev_err(chip->card->dev, 1895 "Cannot turn on display power on i915\n"); 1896 goto out_free; 1897 } 1898 #endif 1899 } 1900 1901 err = azx_first_init(chip); 1902 if (err < 0) 1903 goto out_free; 1904 1905 #ifdef CONFIG_SND_HDA_INPUT_BEEP 1906 chip->beep_mode = beep_mode[dev]; 1907 #endif 1908 1909 /* create codec instances */ 1910 err = azx_codec_create(chip, model[dev], 1911 azx_max_codecs[chip->driver_type], 1912 power_save_addr); 1913 1914 if (err < 0) 1915 goto out_free; 1916 #ifdef CONFIG_SND_HDA_PATCH_LOADER 1917 if (chip->fw) { 1918 err = snd_hda_load_patch(chip->bus, chip->fw->size, 1919 chip->fw->data); 1920 if (err < 0) 1921 goto out_free; 1922 #ifndef CONFIG_PM 1923 release_firmware(chip->fw); /* no longer needed */ 1924 chip->fw = NULL; 1925 #endif 1926 } 1927 #endif 1928 if ((probe_only[dev] & 1) == 0) { 1929 err = azx_codec_configure(chip); 1930 if (err < 0) 1931 goto out_free; 1932 } 1933 1934 /* create PCM streams */ 1935 err = snd_hda_build_pcms(chip->bus); 1936 if (err < 0) 1937 goto out_free; 1938 1939 /* create mixer controls */ 1940 err = azx_mixer_create(chip); 1941 if (err < 0) 1942 goto out_free; 1943 1944 err = snd_card_register(chip->card); 1945 if (err < 0) 1946 goto out_free; 1947 1948 chip->running = 1; 1949 power_down_all_codecs(chip); 1950 azx_notifier_register(chip); 1951 azx_add_card_list(chip); 1952 if ((chip->driver_caps & AZX_DCAPS_PM_RUNTIME) || hda->use_vga_switcheroo) 1953 pm_runtime_put_noidle(&pci->dev); 1954 1955 out_free: 1956 if (err < 0) 1957 hda->init_failed = 1; 1958 complete_all(&hda->probe_wait); 1959 return err; 1960 } 1961 1962 static void azx_remove(struct pci_dev *pci) 1963 { 1964 struct snd_card *card = pci_get_drvdata(pci); 1965 1966 if (card) 1967 snd_card_free(card); 1968 } 1969 1970 /* PCI IDs */ 1971 static const struct pci_device_id azx_ids[] = { 1972 /* CPT */ 1973 { PCI_DEVICE(0x8086, 0x1c20), 1974 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 1975 /* PBG */ 1976 { PCI_DEVICE(0x8086, 0x1d20), 1977 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 1978 /* Panther Point */ 1979 { PCI_DEVICE(0x8086, 0x1e20), 1980 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 1981 /* Lynx Point */ 1982 { PCI_DEVICE(0x8086, 0x8c20), 1983 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 1984 /* 9 Series */ 1985 { PCI_DEVICE(0x8086, 0x8ca0), 1986 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 1987 /* Wellsburg */ 1988 { PCI_DEVICE(0x8086, 0x8d20), 1989 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 1990 { PCI_DEVICE(0x8086, 0x8d21), 1991 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 1992 /* Lynx Point-LP */ 1993 { PCI_DEVICE(0x8086, 0x9c20), 1994 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 1995 /* Lynx Point-LP */ 1996 { PCI_DEVICE(0x8086, 0x9c21), 1997 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 1998 /* Wildcat Point-LP */ 1999 { PCI_DEVICE(0x8086, 0x9ca0), 2000 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2001 /* Haswell */ 2002 { PCI_DEVICE(0x8086, 0x0a0c), 2003 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 2004 { PCI_DEVICE(0x8086, 0x0c0c), 2005 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 2006 { PCI_DEVICE(0x8086, 0x0d0c), 2007 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 2008 /* Broadwell */ 2009 { PCI_DEVICE(0x8086, 0x160c), 2010 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL }, 2011 /* 5 Series/3400 */ 2012 { PCI_DEVICE(0x8086, 0x3b56), 2013 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2014 /* Poulsbo */ 2015 { PCI_DEVICE(0x8086, 0x811b), 2016 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2017 /* Oaktrail */ 2018 { PCI_DEVICE(0x8086, 0x080a), 2019 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2020 /* BayTrail */ 2021 { PCI_DEVICE(0x8086, 0x0f04), 2022 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2023 /* Braswell */ 2024 { PCI_DEVICE(0x8086, 0x2284), 2025 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2026 /* ICH */ 2027 { PCI_DEVICE(0x8086, 0x2668), 2028 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC | 2029 AZX_DCAPS_BUFSIZE }, /* ICH6 */ 2030 { PCI_DEVICE(0x8086, 0x27d8), 2031 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC | 2032 AZX_DCAPS_BUFSIZE }, /* ICH7 */ 2033 { PCI_DEVICE(0x8086, 0x269a), 2034 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC | 2035 AZX_DCAPS_BUFSIZE }, /* ESB2 */ 2036 { PCI_DEVICE(0x8086, 0x284b), 2037 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC | 2038 AZX_DCAPS_BUFSIZE }, /* ICH8 */ 2039 { PCI_DEVICE(0x8086, 0x293e), 2040 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC | 2041 AZX_DCAPS_BUFSIZE }, /* ICH9 */ 2042 { PCI_DEVICE(0x8086, 0x293f), 2043 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC | 2044 AZX_DCAPS_BUFSIZE }, /* ICH9 */ 2045 { PCI_DEVICE(0x8086, 0x3a3e), 2046 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC | 2047 AZX_DCAPS_BUFSIZE }, /* ICH10 */ 2048 { PCI_DEVICE(0x8086, 0x3a6e), 2049 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC | 2050 AZX_DCAPS_BUFSIZE }, /* ICH10 */ 2051 /* Generic Intel */ 2052 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID), 2053 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2054 .class_mask = 0xffffff, 2055 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE }, 2056 /* ATI SB 450/600/700/800/900 */ 2057 { PCI_DEVICE(0x1002, 0x437b), 2058 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, 2059 { PCI_DEVICE(0x1002, 0x4383), 2060 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, 2061 /* AMD Hudson */ 2062 { PCI_DEVICE(0x1022, 0x780d), 2063 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB }, 2064 /* ATI HDMI */ 2065 { PCI_DEVICE(0x1002, 0x793b), 2066 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2067 { PCI_DEVICE(0x1002, 0x7919), 2068 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2069 { PCI_DEVICE(0x1002, 0x960f), 2070 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2071 { PCI_DEVICE(0x1002, 0x970f), 2072 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2073 { PCI_DEVICE(0x1002, 0xaa00), 2074 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2075 { PCI_DEVICE(0x1002, 0xaa08), 2076 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2077 { PCI_DEVICE(0x1002, 0xaa10), 2078 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2079 { PCI_DEVICE(0x1002, 0xaa18), 2080 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2081 { PCI_DEVICE(0x1002, 0xaa20), 2082 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2083 { PCI_DEVICE(0x1002, 0xaa28), 2084 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2085 { PCI_DEVICE(0x1002, 0xaa30), 2086 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2087 { PCI_DEVICE(0x1002, 0xaa38), 2088 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2089 { PCI_DEVICE(0x1002, 0xaa40), 2090 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2091 { PCI_DEVICE(0x1002, 0xaa48), 2092 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2093 { PCI_DEVICE(0x1002, 0xaa50), 2094 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2095 { PCI_DEVICE(0x1002, 0xaa58), 2096 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2097 { PCI_DEVICE(0x1002, 0xaa60), 2098 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2099 { PCI_DEVICE(0x1002, 0xaa68), 2100 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2101 { PCI_DEVICE(0x1002, 0xaa80), 2102 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2103 { PCI_DEVICE(0x1002, 0xaa88), 2104 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2105 { PCI_DEVICE(0x1002, 0xaa90), 2106 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2107 { PCI_DEVICE(0x1002, 0xaa98), 2108 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2109 { PCI_DEVICE(0x1002, 0x9902), 2110 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI }, 2111 { PCI_DEVICE(0x1002, 0xaaa0), 2112 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI }, 2113 { PCI_DEVICE(0x1002, 0xaaa8), 2114 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI }, 2115 { PCI_DEVICE(0x1002, 0xaab0), 2116 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI }, 2117 /* VIA VT8251/VT8237A */ 2118 { PCI_DEVICE(0x1106, 0x3288), 2119 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA }, 2120 /* VIA GFX VT7122/VX900 */ 2121 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC }, 2122 /* VIA GFX VT6122/VX11 */ 2123 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC }, 2124 /* SIS966 */ 2125 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS }, 2126 /* ULI M5461 */ 2127 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI }, 2128 /* NVIDIA MCP */ 2129 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID), 2130 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2131 .class_mask = 0xffffff, 2132 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA }, 2133 /* Teradici */ 2134 { PCI_DEVICE(0x6549, 0x1200), 2135 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, 2136 { PCI_DEVICE(0x6549, 0x2200), 2137 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, 2138 /* Creative X-Fi (CA0110-IBG) */ 2139 /* CTHDA chips */ 2140 { PCI_DEVICE(0x1102, 0x0010), 2141 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, 2142 { PCI_DEVICE(0x1102, 0x0012), 2143 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, 2144 #if !IS_ENABLED(CONFIG_SND_CTXFI) 2145 /* the following entry conflicts with snd-ctxfi driver, 2146 * as ctxfi driver mutates from HD-audio to native mode with 2147 * a special command sequence. 2148 */ 2149 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID), 2150 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2151 .class_mask = 0xffffff, 2152 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | 2153 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB }, 2154 #else 2155 /* this entry seems still valid -- i.e. without emu20kx chip */ 2156 { PCI_DEVICE(0x1102, 0x0009), 2157 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | 2158 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB }, 2159 #endif 2160 /* CM8888 */ 2161 { PCI_DEVICE(0x13f6, 0x5011), 2162 .driver_data = AZX_DRIVER_CMEDIA | 2163 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB }, 2164 /* Vortex86MX */ 2165 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC }, 2166 /* VMware HDAudio */ 2167 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC }, 2168 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */ 2169 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID), 2170 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2171 .class_mask = 0xffffff, 2172 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, 2173 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID), 2174 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2175 .class_mask = 0xffffff, 2176 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, 2177 { 0, } 2178 }; 2179 MODULE_DEVICE_TABLE(pci, azx_ids); 2180 2181 /* pci_driver definition */ 2182 static struct pci_driver azx_driver = { 2183 .name = KBUILD_MODNAME, 2184 .id_table = azx_ids, 2185 .probe = azx_probe, 2186 .remove = azx_remove, 2187 .driver = { 2188 .pm = AZX_PM_OPS, 2189 }, 2190 }; 2191 2192 module_pci_driver(azx_driver); 2193