1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * 4 * hda_intel.c - Implementation of primary alsa driver code base 5 * for Intel HD Audio. 6 * 7 * Copyright(c) 2004 Intel Corporation 8 * 9 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> 10 * PeiSen Hou <pshou@realtek.com.tw> 11 * 12 * CONTACTS: 13 * 14 * Matt Jared matt.jared@intel.com 15 * Andy Kopp andy.kopp@intel.com 16 * Dan Kogan dan.d.kogan@intel.com 17 * 18 * CHANGES: 19 * 20 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou 21 */ 22 23 #include <linux/delay.h> 24 #include <linux/interrupt.h> 25 #include <linux/kernel.h> 26 #include <linux/module.h> 27 #include <linux/dma-mapping.h> 28 #include <linux/moduleparam.h> 29 #include <linux/init.h> 30 #include <linux/slab.h> 31 #include <linux/pci.h> 32 #include <linux/mutex.h> 33 #include <linux/io.h> 34 #include <linux/pm_runtime.h> 35 #include <linux/clocksource.h> 36 #include <linux/time.h> 37 #include <linux/completion.h> 38 #include <linux/acpi.h> 39 #include <linux/pgtable.h> 40 41 #ifdef CONFIG_X86 42 /* for snoop control */ 43 #include <linux/dma-map-ops.h> 44 #include <asm/set_memory.h> 45 #include <asm/cpufeature.h> 46 #endif 47 #include <sound/core.h> 48 #include <sound/initval.h> 49 #include <sound/hdaudio.h> 50 #include <sound/hda_i915.h> 51 #include <sound/intel-dsp-config.h> 52 #include <linux/vgaarb.h> 53 #include <linux/vga_switcheroo.h> 54 #include <linux/apple-gmux.h> 55 #include <linux/firmware.h> 56 #include <sound/hda_codec.h> 57 #include "hda_controller.h" 58 #include "hda_intel.h" 59 60 #define CREATE_TRACE_POINTS 61 #include "hda_intel_trace.h" 62 63 /* position fix mode */ 64 enum { 65 POS_FIX_AUTO, 66 POS_FIX_LPIB, 67 POS_FIX_POSBUF, 68 POS_FIX_VIACOMBO, 69 POS_FIX_COMBO, 70 POS_FIX_SKL, 71 POS_FIX_FIFO, 72 }; 73 74 /* Defines for ATI HD Audio support in SB450 south bridge */ 75 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42 76 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02 77 78 /* Defines for Nvidia HDA support */ 79 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e 80 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f 81 #define NVIDIA_HDA_ISTRM_COH 0x4d 82 #define NVIDIA_HDA_OSTRM_COH 0x4c 83 #define NVIDIA_HDA_ENABLE_COHBIT 0x01 84 85 /* Defines for Intel SCH HDA snoop control */ 86 #define INTEL_HDA_CGCTL 0x48 87 #define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6) 88 #define INTEL_SCH_HDA_DEVC 0x78 89 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11) 90 91 /* max number of SDs */ 92 /* ICH, ATI and VIA have 4 playback and 4 capture */ 93 #define ICH6_NUM_CAPTURE 4 94 #define ICH6_NUM_PLAYBACK 4 95 96 /* ULI has 6 playback and 5 capture */ 97 #define ULI_NUM_CAPTURE 5 98 #define ULI_NUM_PLAYBACK 6 99 100 /* ATI HDMI may have up to 8 playbacks and 0 capture */ 101 #define ATIHDMI_NUM_CAPTURE 0 102 #define ATIHDMI_NUM_PLAYBACK 8 103 104 105 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; 106 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; 107 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; 108 static char *model[SNDRV_CARDS]; 109 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 110 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 111 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 112 static int probe_only[SNDRV_CARDS]; 113 static int jackpoll_ms[SNDRV_CARDS]; 114 static int single_cmd = -1; 115 static int enable_msi = -1; 116 #ifdef CONFIG_SND_HDA_PATCH_LOADER 117 static char *patch[SNDRV_CARDS]; 118 #endif 119 #ifdef CONFIG_SND_HDA_INPUT_BEEP 120 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = 121 CONFIG_SND_HDA_INPUT_BEEP_MODE}; 122 #endif 123 static bool dmic_detect = 1; 124 static bool ctl_dev_id = IS_ENABLED(CONFIG_SND_HDA_CTL_DEV_ID) ? 1 : 0; 125 126 module_param_array(index, int, NULL, 0444); 127 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface."); 128 module_param_array(id, charp, NULL, 0444); 129 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface."); 130 module_param_array(enable, bool, NULL, 0444); 131 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface."); 132 module_param_array(model, charp, NULL, 0444); 133 MODULE_PARM_DESC(model, "Use the given board model."); 134 module_param_array(position_fix, int, NULL, 0444); 135 MODULE_PARM_DESC(position_fix, "DMA pointer read method." 136 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+, 6 = FIFO)."); 137 module_param_array(bdl_pos_adj, int, NULL, 0644); 138 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset."); 139 module_param_array(probe_mask, int, NULL, 0444); 140 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1)."); 141 module_param_array(probe_only, int, NULL, 0444); 142 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization."); 143 module_param_array(jackpoll_ms, int, NULL, 0444); 144 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)"); 145 module_param(single_cmd, bint, 0444); 146 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs " 147 "(for debugging only)."); 148 module_param(enable_msi, bint, 0444); 149 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)"); 150 #ifdef CONFIG_SND_HDA_PATCH_LOADER 151 module_param_array(patch, charp, NULL, 0444); 152 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface."); 153 #endif 154 #ifdef CONFIG_SND_HDA_INPUT_BEEP 155 module_param_array(beep_mode, bool, NULL, 0444); 156 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode " 157 "(0=off, 1=on) (default=1)."); 158 #endif 159 module_param(dmic_detect, bool, 0444); 160 MODULE_PARM_DESC(dmic_detect, "Allow DSP driver selection (bypass this driver) " 161 "(0=off, 1=on) (default=1); " 162 "deprecated, use snd-intel-dspcfg.dsp_driver option instead"); 163 module_param(ctl_dev_id, bool, 0444); 164 MODULE_PARM_DESC(ctl_dev_id, "Use control device identifier (based on codec address)."); 165 166 #ifdef CONFIG_PM 167 static int param_set_xint(const char *val, const struct kernel_param *kp); 168 static const struct kernel_param_ops param_ops_xint = { 169 .set = param_set_xint, 170 .get = param_get_int, 171 }; 172 #define param_check_xint param_check_int 173 174 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT; 175 module_param(power_save, xint, 0644); 176 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout " 177 "(in second, 0 = disable)."); 178 179 static bool pm_blacklist = true; 180 module_param(pm_blacklist, bool, 0644); 181 MODULE_PARM_DESC(pm_blacklist, "Enable power-management denylist"); 182 183 /* reset the HD-audio controller in power save mode. 184 * this may give more power-saving, but will take longer time to 185 * wake up. 186 */ 187 static bool power_save_controller = 1; 188 module_param(power_save_controller, bool, 0644); 189 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode."); 190 #else /* CONFIG_PM */ 191 #define power_save 0 192 #define pm_blacklist false 193 #define power_save_controller false 194 #endif /* CONFIG_PM */ 195 196 static int align_buffer_size = -1; 197 module_param(align_buffer_size, bint, 0644); 198 MODULE_PARM_DESC(align_buffer_size, 199 "Force buffer and period sizes to be multiple of 128 bytes."); 200 201 #ifdef CONFIG_X86 202 static int hda_snoop = -1; 203 module_param_named(snoop, hda_snoop, bint, 0444); 204 MODULE_PARM_DESC(snoop, "Enable/disable snooping"); 205 #else 206 #define hda_snoop true 207 #endif 208 209 210 MODULE_LICENSE("GPL"); 211 MODULE_DESCRIPTION("Intel HDA driver"); 212 213 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO) 214 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI) 215 #define SUPPORT_VGA_SWITCHEROO 216 #endif 217 #endif 218 219 220 /* 221 */ 222 223 /* driver types */ 224 enum { 225 AZX_DRIVER_ICH, 226 AZX_DRIVER_PCH, 227 AZX_DRIVER_SCH, 228 AZX_DRIVER_SKL, 229 AZX_DRIVER_HDMI, 230 AZX_DRIVER_ATI, 231 AZX_DRIVER_ATIHDMI, 232 AZX_DRIVER_ATIHDMI_NS, 233 AZX_DRIVER_GFHDMI, 234 AZX_DRIVER_VIA, 235 AZX_DRIVER_SIS, 236 AZX_DRIVER_ULI, 237 AZX_DRIVER_NVIDIA, 238 AZX_DRIVER_TERA, 239 AZX_DRIVER_CTX, 240 AZX_DRIVER_CTHDA, 241 AZX_DRIVER_CMEDIA, 242 AZX_DRIVER_ZHAOXIN, 243 AZX_DRIVER_LOONGSON, 244 AZX_DRIVER_GENERIC, 245 AZX_NUM_DRIVERS, /* keep this as last entry */ 246 }; 247 248 #define azx_get_snoop_type(chip) \ 249 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10) 250 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10) 251 252 /* quirks for old Intel chipsets */ 253 #define AZX_DCAPS_INTEL_ICH \ 254 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE) 255 256 /* quirks for Intel PCH */ 257 #define AZX_DCAPS_INTEL_PCH_BASE \ 258 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\ 259 AZX_DCAPS_SNOOP_TYPE(SCH)) 260 261 /* PCH up to IVB; no runtime PM; bind with i915 gfx */ 262 #define AZX_DCAPS_INTEL_PCH_NOPM \ 263 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT) 264 265 /* PCH for HSW/BDW; with runtime PM */ 266 /* no i915 binding for this as HSW/BDW has another controller for HDMI */ 267 #define AZX_DCAPS_INTEL_PCH \ 268 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME) 269 270 /* HSW HDMI */ 271 #define AZX_DCAPS_INTEL_HASWELL \ 272 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\ 273 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\ 274 AZX_DCAPS_SNOOP_TYPE(SCH)) 275 276 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */ 277 #define AZX_DCAPS_INTEL_BROADWELL \ 278 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\ 279 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\ 280 AZX_DCAPS_SNOOP_TYPE(SCH)) 281 282 #define AZX_DCAPS_INTEL_BAYTRAIL \ 283 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT) 284 285 #define AZX_DCAPS_INTEL_BRASWELL \ 286 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\ 287 AZX_DCAPS_I915_COMPONENT) 288 289 #define AZX_DCAPS_INTEL_SKYLAKE \ 290 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\ 291 AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT) 292 293 #define AZX_DCAPS_INTEL_BROXTON AZX_DCAPS_INTEL_SKYLAKE 294 295 #define AZX_DCAPS_INTEL_LNL \ 296 (AZX_DCAPS_INTEL_SKYLAKE | AZX_DCAPS_PIO_COMMANDS) 297 298 /* quirks for ATI SB / AMD Hudson */ 299 #define AZX_DCAPS_PRESET_ATI_SB \ 300 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB |\ 301 AZX_DCAPS_SNOOP_TYPE(ATI)) 302 303 /* quirks for ATI/AMD HDMI */ 304 #define AZX_DCAPS_PRESET_ATI_HDMI \ 305 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB|\ 306 AZX_DCAPS_NO_MSI64) 307 308 /* quirks for ATI HDMI with snoop off */ 309 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \ 310 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_AMD_ALLOC_FIX) 311 312 /* quirks for AMD SB */ 313 #define AZX_DCAPS_PRESET_AMD_SB \ 314 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_AMD_WORKAROUND |\ 315 AZX_DCAPS_SNOOP_TYPE(ATI) | AZX_DCAPS_PM_RUNTIME |\ 316 AZX_DCAPS_RETRY_PROBE) 317 318 /* quirks for Nvidia */ 319 #define AZX_DCAPS_PRESET_NVIDIA \ 320 (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\ 321 AZX_DCAPS_SNOOP_TYPE(NVIDIA)) 322 323 #define AZX_DCAPS_PRESET_CTHDA \ 324 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\ 325 AZX_DCAPS_NO_64BIT |\ 326 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF) 327 328 /* 329 * vga_switcheroo support 330 */ 331 #ifdef SUPPORT_VGA_SWITCHEROO 332 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo) 333 #define needs_eld_notify_link(chip) ((chip)->bus.keep_power) 334 #else 335 #define use_vga_switcheroo(chip) 0 336 #define needs_eld_notify_link(chip) false 337 #endif 338 339 static const char * const driver_short_names[] = { 340 [AZX_DRIVER_ICH] = "HDA Intel", 341 [AZX_DRIVER_PCH] = "HDA Intel PCH", 342 [AZX_DRIVER_SCH] = "HDA Intel MID", 343 [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */ 344 [AZX_DRIVER_HDMI] = "HDA Intel HDMI", 345 [AZX_DRIVER_ATI] = "HDA ATI SB", 346 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI", 347 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI", 348 [AZX_DRIVER_GFHDMI] = "HDA GF HDMI", 349 [AZX_DRIVER_VIA] = "HDA VIA VT82xx", 350 [AZX_DRIVER_SIS] = "HDA SIS966", 351 [AZX_DRIVER_ULI] = "HDA ULI M5461", 352 [AZX_DRIVER_NVIDIA] = "HDA NVidia", 353 [AZX_DRIVER_TERA] = "HDA Teradici", 354 [AZX_DRIVER_CTX] = "HDA Creative", 355 [AZX_DRIVER_CTHDA] = "HDA Creative", 356 [AZX_DRIVER_CMEDIA] = "HDA C-Media", 357 [AZX_DRIVER_ZHAOXIN] = "HDA Zhaoxin", 358 [AZX_DRIVER_LOONGSON] = "HDA Loongson", 359 [AZX_DRIVER_GENERIC] = "HD-Audio Generic", 360 }; 361 362 static int azx_acquire_irq(struct azx *chip, int do_disconnect); 363 static void set_default_power_save(struct azx *chip); 364 365 /* 366 * initialize the PCI registers 367 */ 368 /* update bits in a PCI register byte */ 369 static void update_pci_byte(struct pci_dev *pci, unsigned int reg, 370 unsigned char mask, unsigned char val) 371 { 372 unsigned char data; 373 374 pci_read_config_byte(pci, reg, &data); 375 data &= ~mask; 376 data |= (val & mask); 377 pci_write_config_byte(pci, reg, data); 378 } 379 380 static void azx_init_pci(struct azx *chip) 381 { 382 int snoop_type = azx_get_snoop_type(chip); 383 384 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44) 385 * TCSEL == Traffic Class Select Register, which sets PCI express QOS 386 * Ensuring these bits are 0 clears playback static on some HD Audio 387 * codecs. 388 * The PCI register TCSEL is defined in the Intel manuals. 389 */ 390 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) { 391 dev_dbg(chip->card->dev, "Clearing TCSEL\n"); 392 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0); 393 } 394 395 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio, 396 * we need to enable snoop. 397 */ 398 if (snoop_type == AZX_SNOOP_TYPE_ATI) { 399 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n", 400 azx_snoop(chip)); 401 update_pci_byte(chip->pci, 402 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07, 403 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0); 404 } 405 406 /* For NVIDIA HDA, enable snoop */ 407 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) { 408 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n", 409 azx_snoop(chip)); 410 update_pci_byte(chip->pci, 411 NVIDIA_HDA_TRANSREG_ADDR, 412 0x0f, NVIDIA_HDA_ENABLE_COHBITS); 413 update_pci_byte(chip->pci, 414 NVIDIA_HDA_ISTRM_COH, 415 0x01, NVIDIA_HDA_ENABLE_COHBIT); 416 update_pci_byte(chip->pci, 417 NVIDIA_HDA_OSTRM_COH, 418 0x01, NVIDIA_HDA_ENABLE_COHBIT); 419 } 420 421 /* Enable SCH/PCH snoop if needed */ 422 if (snoop_type == AZX_SNOOP_TYPE_SCH) { 423 unsigned short snoop; 424 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop); 425 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) || 426 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) { 427 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP; 428 if (!azx_snoop(chip)) 429 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP; 430 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop); 431 pci_read_config_word(chip->pci, 432 INTEL_SCH_HDA_DEVC, &snoop); 433 } 434 dev_dbg(chip->card->dev, "SCH snoop: %s\n", 435 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ? 436 "Disabled" : "Enabled"); 437 } 438 } 439 440 /* 441 * In BXT-P A0, HD-Audio DMA requests is later than expected, 442 * and makes an audio stream sensitive to system latencies when 443 * 24/32 bits are playing. 444 * Adjusting threshold of DMA fifo to force the DMA request 445 * sooner to improve latency tolerance at the expense of power. 446 */ 447 static void bxt_reduce_dma_latency(struct azx *chip) 448 { 449 u32 val; 450 451 val = azx_readl(chip, VS_EM4L); 452 val &= (0x3 << 20); 453 azx_writel(chip, VS_EM4L, val); 454 } 455 456 /* 457 * ML_LCAP bits: 458 * bit 0: 6 MHz Supported 459 * bit 1: 12 MHz Supported 460 * bit 2: 24 MHz Supported 461 * bit 3: 48 MHz Supported 462 * bit 4: 96 MHz Supported 463 * bit 5: 192 MHz Supported 464 */ 465 static int intel_get_lctl_scf(struct azx *chip) 466 { 467 struct hdac_bus *bus = azx_bus(chip); 468 static const int preferred_bits[] = { 2, 3, 1, 4, 5 }; 469 u32 val, t; 470 int i; 471 472 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP); 473 474 for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) { 475 t = preferred_bits[i]; 476 if (val & (1 << t)) 477 return t; 478 } 479 480 dev_warn(chip->card->dev, "set audio clock frequency to 6MHz"); 481 return 0; 482 } 483 484 static int intel_ml_lctl_set_power(struct azx *chip, int state) 485 { 486 struct hdac_bus *bus = azx_bus(chip); 487 u32 val; 488 int timeout; 489 490 /* 491 * Changes to LCTL.SCF are only needed for the first multi-link dealing 492 * with external codecs 493 */ 494 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 495 val &= ~AZX_ML_LCTL_SPA; 496 val |= state << AZX_ML_LCTL_SPA_SHIFT; 497 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 498 /* wait for CPA */ 499 timeout = 50; 500 while (timeout) { 501 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) & 502 AZX_ML_LCTL_CPA) == (state << AZX_ML_LCTL_CPA_SHIFT)) 503 return 0; 504 timeout--; 505 udelay(10); 506 } 507 508 return -1; 509 } 510 511 static void intel_init_lctl(struct azx *chip) 512 { 513 struct hdac_bus *bus = azx_bus(chip); 514 u32 val; 515 int ret; 516 517 /* 0. check lctl register value is correct or not */ 518 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 519 /* only perform additional configurations if the SCF is initially based on 6MHz */ 520 if ((val & AZX_ML_LCTL_SCF) != 0) 521 return; 522 523 /* 524 * Before operating on SPA, CPA must match SPA. 525 * Any deviation may result in undefined behavior. 526 */ 527 if (((val & AZX_ML_LCTL_SPA) >> AZX_ML_LCTL_SPA_SHIFT) != 528 ((val & AZX_ML_LCTL_CPA) >> AZX_ML_LCTL_CPA_SHIFT)) 529 return; 530 531 /* 1. turn link down: set SPA to 0 and wait CPA to 0 */ 532 ret = intel_ml_lctl_set_power(chip, 0); 533 udelay(100); 534 if (ret) 535 goto set_spa; 536 537 /* 2. update SCF to select an audio clock different from 6MHz */ 538 val &= ~AZX_ML_LCTL_SCF; 539 val |= intel_get_lctl_scf(chip); 540 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 541 542 set_spa: 543 /* 4. turn link up: set SPA to 1 and wait CPA to 1 */ 544 intel_ml_lctl_set_power(chip, 1); 545 udelay(100); 546 } 547 548 static void hda_intel_init_chip(struct azx *chip, bool full_reset) 549 { 550 struct hdac_bus *bus = azx_bus(chip); 551 struct pci_dev *pci = chip->pci; 552 u32 val; 553 554 snd_hdac_set_codec_wakeup(bus, true); 555 if (chip->driver_type == AZX_DRIVER_SKL) { 556 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val); 557 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE; 558 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val); 559 } 560 azx_init_chip(chip, full_reset); 561 if (chip->driver_type == AZX_DRIVER_SKL) { 562 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val); 563 val = val | INTEL_HDA_CGCTL_MISCBDCGE; 564 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val); 565 } 566 567 snd_hdac_set_codec_wakeup(bus, false); 568 569 /* reduce dma latency to avoid noise */ 570 if (HDA_CONTROLLER_IS_APL(pci)) 571 bxt_reduce_dma_latency(chip); 572 573 if (bus->mlcap != NULL) 574 intel_init_lctl(chip); 575 } 576 577 /* calculate runtime delay from LPIB */ 578 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev, 579 unsigned int pos) 580 { 581 struct snd_pcm_substream *substream = azx_dev->core.substream; 582 int stream = substream->stream; 583 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev); 584 int delay; 585 586 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 587 delay = pos - lpib_pos; 588 else 589 delay = lpib_pos - pos; 590 if (delay < 0) { 591 if (delay >= azx_dev->core.delay_negative_threshold) 592 delay = 0; 593 else 594 delay += azx_dev->core.bufsize; 595 } 596 597 if (delay >= azx_dev->core.period_bytes) { 598 dev_info(chip->card->dev, 599 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n", 600 delay, azx_dev->core.period_bytes); 601 delay = 0; 602 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY; 603 chip->get_delay[stream] = NULL; 604 } 605 606 return bytes_to_frames(substream->runtime, delay); 607 } 608 609 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev); 610 611 /* called from IRQ */ 612 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev) 613 { 614 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 615 int ok; 616 617 ok = azx_position_ok(chip, azx_dev); 618 if (ok == 1) { 619 azx_dev->irq_pending = 0; 620 return ok; 621 } else if (ok == 0) { 622 /* bogus IRQ, process it later */ 623 azx_dev->irq_pending = 1; 624 schedule_work(&hda->irq_pending_work); 625 } 626 return 0; 627 } 628 629 #define display_power(chip, enable) \ 630 snd_hdac_display_power(azx_bus(chip), HDA_CODEC_IDX_CONTROLLER, enable) 631 632 /* 633 * Check whether the current DMA position is acceptable for updating 634 * periods. Returns non-zero if it's OK. 635 * 636 * Many HD-audio controllers appear pretty inaccurate about 637 * the update-IRQ timing. The IRQ is issued before actually the 638 * data is processed. So, we need to process it afterwords in a 639 * workqueue. 640 * 641 * Returns 1 if OK to proceed, 0 for delay handling, -1 for skipping update 642 */ 643 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev) 644 { 645 struct snd_pcm_substream *substream = azx_dev->core.substream; 646 struct snd_pcm_runtime *runtime = substream->runtime; 647 int stream = substream->stream; 648 u32 wallclk; 649 unsigned int pos; 650 snd_pcm_uframes_t hwptr, target; 651 652 /* 653 * The value of the WALLCLK register is always 0 654 * on the Loongson controller, so we return directly. 655 */ 656 if (chip->driver_type == AZX_DRIVER_LOONGSON) 657 return 1; 658 659 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk; 660 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3) 661 return -1; /* bogus (too early) interrupt */ 662 663 if (chip->get_position[stream]) 664 pos = chip->get_position[stream](chip, azx_dev); 665 else { /* use the position buffer as default */ 666 pos = azx_get_pos_posbuf(chip, azx_dev); 667 if (!pos || pos == (u32)-1) { 668 dev_info(chip->card->dev, 669 "Invalid position buffer, using LPIB read method instead.\n"); 670 chip->get_position[stream] = azx_get_pos_lpib; 671 if (chip->get_position[0] == azx_get_pos_lpib && 672 chip->get_position[1] == azx_get_pos_lpib) 673 azx_bus(chip)->use_posbuf = false; 674 pos = azx_get_pos_lpib(chip, azx_dev); 675 chip->get_delay[stream] = NULL; 676 } else { 677 chip->get_position[stream] = azx_get_pos_posbuf; 678 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY) 679 chip->get_delay[stream] = azx_get_delay_from_lpib; 680 } 681 } 682 683 if (pos >= azx_dev->core.bufsize) 684 pos = 0; 685 686 if (WARN_ONCE(!azx_dev->core.period_bytes, 687 "hda-intel: zero azx_dev->period_bytes")) 688 return -1; /* this shouldn't happen! */ 689 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 && 690 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2) 691 /* NG - it's below the first next period boundary */ 692 return chip->bdl_pos_adj ? 0 : -1; 693 azx_dev->core.start_wallclk += wallclk; 694 695 if (azx_dev->core.no_period_wakeup) 696 return 1; /* OK, no need to check period boundary */ 697 698 if (runtime->hw_ptr_base != runtime->hw_ptr_interrupt) 699 return 1; /* OK, already in hwptr updating process */ 700 701 /* check whether the period gets really elapsed */ 702 pos = bytes_to_frames(runtime, pos); 703 hwptr = runtime->hw_ptr_base + pos; 704 if (hwptr < runtime->status->hw_ptr) 705 hwptr += runtime->buffer_size; 706 target = runtime->hw_ptr_interrupt + runtime->period_size; 707 if (hwptr < target) { 708 /* too early wakeup, process it later */ 709 return chip->bdl_pos_adj ? 0 : -1; 710 } 711 712 return 1; /* OK, it's fine */ 713 } 714 715 /* 716 * The work for pending PCM period updates. 717 */ 718 static void azx_irq_pending_work(struct work_struct *work) 719 { 720 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work); 721 struct azx *chip = &hda->chip; 722 struct hdac_bus *bus = azx_bus(chip); 723 struct hdac_stream *s; 724 int pending, ok; 725 726 if (!hda->irq_pending_warned) { 727 dev_info(chip->card->dev, 728 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n", 729 chip->card->number); 730 hda->irq_pending_warned = 1; 731 } 732 733 for (;;) { 734 pending = 0; 735 spin_lock_irq(&bus->reg_lock); 736 list_for_each_entry(s, &bus->stream_list, list) { 737 struct azx_dev *azx_dev = stream_to_azx_dev(s); 738 if (!azx_dev->irq_pending || 739 !s->substream || 740 !s->running) 741 continue; 742 ok = azx_position_ok(chip, azx_dev); 743 if (ok > 0) { 744 azx_dev->irq_pending = 0; 745 spin_unlock(&bus->reg_lock); 746 snd_pcm_period_elapsed(s->substream); 747 spin_lock(&bus->reg_lock); 748 } else if (ok < 0) { 749 pending = 0; /* too early */ 750 } else 751 pending++; 752 } 753 spin_unlock_irq(&bus->reg_lock); 754 if (!pending) 755 return; 756 msleep(1); 757 } 758 } 759 760 /* clear irq_pending flags and assure no on-going workq */ 761 static void azx_clear_irq_pending(struct azx *chip) 762 { 763 struct hdac_bus *bus = azx_bus(chip); 764 struct hdac_stream *s; 765 766 spin_lock_irq(&bus->reg_lock); 767 list_for_each_entry(s, &bus->stream_list, list) { 768 struct azx_dev *azx_dev = stream_to_azx_dev(s); 769 azx_dev->irq_pending = 0; 770 } 771 spin_unlock_irq(&bus->reg_lock); 772 } 773 774 static int azx_acquire_irq(struct azx *chip, int do_disconnect) 775 { 776 struct hdac_bus *bus = azx_bus(chip); 777 778 if (request_irq(chip->pci->irq, azx_interrupt, 779 chip->msi ? 0 : IRQF_SHARED, 780 chip->card->irq_descr, chip)) { 781 dev_err(chip->card->dev, 782 "unable to grab IRQ %d, disabling device\n", 783 chip->pci->irq); 784 if (do_disconnect) 785 snd_card_disconnect(chip->card); 786 return -1; 787 } 788 bus->irq = chip->pci->irq; 789 chip->card->sync_irq = bus->irq; 790 pci_intx(chip->pci, !chip->msi); 791 return 0; 792 } 793 794 /* get the current DMA position with correction on VIA chips */ 795 static unsigned int azx_via_get_position(struct azx *chip, 796 struct azx_dev *azx_dev) 797 { 798 unsigned int link_pos, mini_pos, bound_pos; 799 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos; 800 unsigned int fifo_size; 801 802 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev)); 803 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 804 /* Playback, no problem using link position */ 805 return link_pos; 806 } 807 808 /* Capture */ 809 /* For new chipset, 810 * use mod to get the DMA position just like old chipset 811 */ 812 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf); 813 mod_dma_pos %= azx_dev->core.period_bytes; 814 815 fifo_size = azx_stream(azx_dev)->fifo_size; 816 817 if (azx_dev->insufficient) { 818 /* Link position never gather than FIFO size */ 819 if (link_pos <= fifo_size) 820 return 0; 821 822 azx_dev->insufficient = 0; 823 } 824 825 if (link_pos <= fifo_size) 826 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size; 827 else 828 mini_pos = link_pos - fifo_size; 829 830 /* Find nearest previous boudary */ 831 mod_mini_pos = mini_pos % azx_dev->core.period_bytes; 832 mod_link_pos = link_pos % azx_dev->core.period_bytes; 833 if (mod_link_pos >= fifo_size) 834 bound_pos = link_pos - mod_link_pos; 835 else if (mod_dma_pos >= mod_mini_pos) 836 bound_pos = mini_pos - mod_mini_pos; 837 else { 838 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes; 839 if (bound_pos >= azx_dev->core.bufsize) 840 bound_pos = 0; 841 } 842 843 /* Calculate real DMA position we want */ 844 return bound_pos + mod_dma_pos; 845 } 846 847 #define AMD_FIFO_SIZE 32 848 849 /* get the current DMA position with FIFO size correction */ 850 static unsigned int azx_get_pos_fifo(struct azx *chip, struct azx_dev *azx_dev) 851 { 852 struct snd_pcm_substream *substream = azx_dev->core.substream; 853 struct snd_pcm_runtime *runtime = substream->runtime; 854 unsigned int pos, delay; 855 856 pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev)); 857 if (!runtime) 858 return pos; 859 860 runtime->delay = AMD_FIFO_SIZE; 861 delay = frames_to_bytes(runtime, AMD_FIFO_SIZE); 862 if (azx_dev->insufficient) { 863 if (pos < delay) { 864 delay = pos; 865 runtime->delay = bytes_to_frames(runtime, pos); 866 } else { 867 azx_dev->insufficient = 0; 868 } 869 } 870 871 /* correct the DMA position for capture stream */ 872 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { 873 if (pos < delay) 874 pos += azx_dev->core.bufsize; 875 pos -= delay; 876 } 877 878 return pos; 879 } 880 881 static int azx_get_delay_from_fifo(struct azx *chip, struct azx_dev *azx_dev, 882 unsigned int pos) 883 { 884 struct snd_pcm_substream *substream = azx_dev->core.substream; 885 886 /* just read back the calculated value in the above */ 887 return substream->runtime->delay; 888 } 889 890 static void __azx_shutdown_chip(struct azx *chip, bool skip_link_reset) 891 { 892 azx_stop_chip(chip); 893 if (!skip_link_reset) 894 azx_enter_link_reset(chip); 895 azx_clear_irq_pending(chip); 896 display_power(chip, false); 897 } 898 899 static DEFINE_MUTEX(card_list_lock); 900 static LIST_HEAD(card_list); 901 902 static void azx_shutdown_chip(struct azx *chip) 903 { 904 __azx_shutdown_chip(chip, false); 905 } 906 907 static void azx_add_card_list(struct azx *chip) 908 { 909 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 910 mutex_lock(&card_list_lock); 911 list_add(&hda->list, &card_list); 912 mutex_unlock(&card_list_lock); 913 } 914 915 static void azx_del_card_list(struct azx *chip) 916 { 917 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 918 mutex_lock(&card_list_lock); 919 list_del_init(&hda->list); 920 mutex_unlock(&card_list_lock); 921 } 922 923 /* trigger power-save check at writing parameter */ 924 static int __maybe_unused param_set_xint(const char *val, const struct kernel_param *kp) 925 { 926 struct hda_intel *hda; 927 struct azx *chip; 928 int prev = power_save; 929 int ret = param_set_int(val, kp); 930 931 if (ret || prev == power_save) 932 return ret; 933 934 mutex_lock(&card_list_lock); 935 list_for_each_entry(hda, &card_list, list) { 936 chip = &hda->chip; 937 if (!hda->probe_continued || chip->disabled) 938 continue; 939 snd_hda_set_power_save(&chip->bus, power_save * 1000); 940 } 941 mutex_unlock(&card_list_lock); 942 return 0; 943 } 944 945 /* 946 * power management 947 */ 948 static bool azx_is_pm_ready(struct snd_card *card) 949 { 950 struct azx *chip; 951 struct hda_intel *hda; 952 953 if (!card) 954 return false; 955 chip = card->private_data; 956 hda = container_of(chip, struct hda_intel, chip); 957 if (chip->disabled || hda->init_failed || !chip->running) 958 return false; 959 return true; 960 } 961 962 static void __azx_runtime_resume(struct azx *chip) 963 { 964 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 965 struct hdac_bus *bus = azx_bus(chip); 966 struct hda_codec *codec; 967 int status; 968 969 display_power(chip, true); 970 if (hda->need_i915_power) 971 snd_hdac_i915_set_bclk(bus); 972 973 /* Read STATESTS before controller reset */ 974 status = azx_readw(chip, STATESTS); 975 976 azx_init_pci(chip); 977 hda_intel_init_chip(chip, true); 978 979 /* Avoid codec resume if runtime resume is for system suspend */ 980 if (!chip->pm_prepared) { 981 list_for_each_codec(codec, &chip->bus) { 982 if (codec->relaxed_resume) 983 continue; 984 985 if (codec->forced_resume || (status & (1 << codec->addr))) 986 pm_request_resume(hda_codec_dev(codec)); 987 } 988 } 989 990 /* power down again for link-controlled chips */ 991 if (!hda->need_i915_power) 992 display_power(chip, false); 993 } 994 995 static int azx_prepare(struct device *dev) 996 { 997 struct snd_card *card = dev_get_drvdata(dev); 998 struct azx *chip; 999 1000 if (!azx_is_pm_ready(card)) 1001 return 0; 1002 1003 chip = card->private_data; 1004 chip->pm_prepared = 1; 1005 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 1006 1007 flush_work(&azx_bus(chip)->unsol_work); 1008 1009 /* HDA controller always requires different WAKEEN for runtime suspend 1010 * and system suspend, so don't use direct-complete here. 1011 */ 1012 return 0; 1013 } 1014 1015 static void azx_complete(struct device *dev) 1016 { 1017 struct snd_card *card = dev_get_drvdata(dev); 1018 struct azx *chip; 1019 1020 if (!azx_is_pm_ready(card)) 1021 return; 1022 1023 chip = card->private_data; 1024 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 1025 chip->pm_prepared = 0; 1026 } 1027 1028 static int azx_suspend(struct device *dev) 1029 { 1030 struct snd_card *card = dev_get_drvdata(dev); 1031 struct azx *chip; 1032 struct hdac_bus *bus; 1033 1034 if (!azx_is_pm_ready(card)) 1035 return 0; 1036 1037 chip = card->private_data; 1038 bus = azx_bus(chip); 1039 azx_shutdown_chip(chip); 1040 if (bus->irq >= 0) { 1041 free_irq(bus->irq, chip); 1042 bus->irq = -1; 1043 chip->card->sync_irq = -1; 1044 } 1045 1046 if (chip->msi) 1047 pci_disable_msi(chip->pci); 1048 1049 trace_azx_suspend(chip); 1050 return 0; 1051 } 1052 1053 static int __maybe_unused azx_resume(struct device *dev) 1054 { 1055 struct snd_card *card = dev_get_drvdata(dev); 1056 struct azx *chip; 1057 1058 if (!azx_is_pm_ready(card)) 1059 return 0; 1060 1061 chip = card->private_data; 1062 if (chip->msi) 1063 if (pci_enable_msi(chip->pci) < 0) 1064 chip->msi = 0; 1065 if (azx_acquire_irq(chip, 1) < 0) 1066 return -EIO; 1067 1068 __azx_runtime_resume(chip); 1069 1070 trace_azx_resume(chip); 1071 return 0; 1072 } 1073 1074 /* put codec down to D3 at hibernation for Intel SKL+; 1075 * otherwise BIOS may still access the codec and screw up the driver 1076 */ 1077 static int azx_freeze_noirq(struct device *dev) 1078 { 1079 struct snd_card *card = dev_get_drvdata(dev); 1080 struct azx *chip = card->private_data; 1081 struct pci_dev *pci = to_pci_dev(dev); 1082 1083 if (!azx_is_pm_ready(card)) 1084 return 0; 1085 if (chip->driver_type == AZX_DRIVER_SKL) 1086 pci_set_power_state(pci, PCI_D3hot); 1087 1088 return 0; 1089 } 1090 1091 static int azx_thaw_noirq(struct device *dev) 1092 { 1093 struct snd_card *card = dev_get_drvdata(dev); 1094 struct azx *chip = card->private_data; 1095 struct pci_dev *pci = to_pci_dev(dev); 1096 1097 if (!azx_is_pm_ready(card)) 1098 return 0; 1099 if (chip->driver_type == AZX_DRIVER_SKL) 1100 pci_set_power_state(pci, PCI_D0); 1101 1102 return 0; 1103 } 1104 1105 static int __maybe_unused azx_runtime_suspend(struct device *dev) 1106 { 1107 struct snd_card *card = dev_get_drvdata(dev); 1108 struct azx *chip; 1109 1110 if (!azx_is_pm_ready(card)) 1111 return 0; 1112 chip = card->private_data; 1113 1114 /* enable controller wake up event */ 1115 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) | STATESTS_INT_MASK); 1116 1117 azx_shutdown_chip(chip); 1118 trace_azx_runtime_suspend(chip); 1119 return 0; 1120 } 1121 1122 static int __maybe_unused azx_runtime_resume(struct device *dev) 1123 { 1124 struct snd_card *card = dev_get_drvdata(dev); 1125 struct azx *chip; 1126 1127 if (!azx_is_pm_ready(card)) 1128 return 0; 1129 chip = card->private_data; 1130 __azx_runtime_resume(chip); 1131 1132 /* disable controller Wake Up event*/ 1133 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) & ~STATESTS_INT_MASK); 1134 1135 trace_azx_runtime_resume(chip); 1136 return 0; 1137 } 1138 1139 static int __maybe_unused azx_runtime_idle(struct device *dev) 1140 { 1141 struct snd_card *card = dev_get_drvdata(dev); 1142 struct azx *chip; 1143 struct hda_intel *hda; 1144 1145 if (!card) 1146 return 0; 1147 1148 chip = card->private_data; 1149 hda = container_of(chip, struct hda_intel, chip); 1150 if (chip->disabled || hda->init_failed) 1151 return 0; 1152 1153 if (!power_save_controller || !azx_has_pm_runtime(chip) || 1154 azx_bus(chip)->codec_powered || !chip->running) 1155 return -EBUSY; 1156 1157 /* ELD notification gets broken when HD-audio bus is off */ 1158 if (needs_eld_notify_link(chip)) 1159 return -EBUSY; 1160 1161 return 0; 1162 } 1163 1164 static const struct dev_pm_ops azx_pm = { 1165 SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume) 1166 .prepare = pm_sleep_ptr(azx_prepare), 1167 .complete = pm_sleep_ptr(azx_complete), 1168 .freeze_noirq = pm_sleep_ptr(azx_freeze_noirq), 1169 .thaw_noirq = pm_sleep_ptr(azx_thaw_noirq), 1170 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle) 1171 }; 1172 1173 1174 static int azx_probe_continue(struct azx *chip); 1175 1176 #ifdef SUPPORT_VGA_SWITCHEROO 1177 static struct pci_dev *get_bound_vga(struct pci_dev *pci); 1178 1179 static void azx_vs_set_state(struct pci_dev *pci, 1180 enum vga_switcheroo_state state) 1181 { 1182 struct snd_card *card = pci_get_drvdata(pci); 1183 struct azx *chip = card->private_data; 1184 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1185 struct hda_codec *codec; 1186 bool disabled; 1187 1188 wait_for_completion(&hda->probe_wait); 1189 if (hda->init_failed) 1190 return; 1191 1192 disabled = (state == VGA_SWITCHEROO_OFF); 1193 if (chip->disabled == disabled) 1194 return; 1195 1196 if (!hda->probe_continued) { 1197 chip->disabled = disabled; 1198 if (!disabled) { 1199 dev_info(chip->card->dev, 1200 "Start delayed initialization\n"); 1201 if (azx_probe_continue(chip) < 0) 1202 dev_err(chip->card->dev, "initialization error\n"); 1203 } 1204 } else { 1205 dev_info(chip->card->dev, "%s via vga_switcheroo\n", 1206 disabled ? "Disabling" : "Enabling"); 1207 if (disabled) { 1208 list_for_each_codec(codec, &chip->bus) { 1209 pm_runtime_suspend(hda_codec_dev(codec)); 1210 pm_runtime_disable(hda_codec_dev(codec)); 1211 } 1212 pm_runtime_suspend(card->dev); 1213 pm_runtime_disable(card->dev); 1214 /* when we get suspended by vga_switcheroo we end up in D3cold, 1215 * however we have no ACPI handle, so pci/acpi can't put us there, 1216 * put ourselves there */ 1217 pci->current_state = PCI_D3cold; 1218 chip->disabled = true; 1219 if (snd_hda_lock_devices(&chip->bus)) 1220 dev_warn(chip->card->dev, 1221 "Cannot lock devices!\n"); 1222 } else { 1223 snd_hda_unlock_devices(&chip->bus); 1224 chip->disabled = false; 1225 pm_runtime_enable(card->dev); 1226 list_for_each_codec(codec, &chip->bus) { 1227 pm_runtime_enable(hda_codec_dev(codec)); 1228 pm_runtime_resume(hda_codec_dev(codec)); 1229 } 1230 } 1231 } 1232 } 1233 1234 static bool azx_vs_can_switch(struct pci_dev *pci) 1235 { 1236 struct snd_card *card = pci_get_drvdata(pci); 1237 struct azx *chip = card->private_data; 1238 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1239 1240 wait_for_completion(&hda->probe_wait); 1241 if (hda->init_failed) 1242 return false; 1243 if (chip->disabled || !hda->probe_continued) 1244 return true; 1245 if (snd_hda_lock_devices(&chip->bus)) 1246 return false; 1247 snd_hda_unlock_devices(&chip->bus); 1248 return true; 1249 } 1250 1251 /* 1252 * The discrete GPU cannot power down unless the HDA controller runtime 1253 * suspends, so activate runtime PM on codecs even if power_save == 0. 1254 */ 1255 static void setup_vga_switcheroo_runtime_pm(struct azx *chip) 1256 { 1257 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1258 struct hda_codec *codec; 1259 1260 if (hda->use_vga_switcheroo && !needs_eld_notify_link(chip)) { 1261 list_for_each_codec(codec, &chip->bus) 1262 codec->auto_runtime_pm = 1; 1263 /* reset the power save setup */ 1264 if (chip->running) 1265 set_default_power_save(chip); 1266 } 1267 } 1268 1269 static void azx_vs_gpu_bound(struct pci_dev *pci, 1270 enum vga_switcheroo_client_id client_id) 1271 { 1272 struct snd_card *card = pci_get_drvdata(pci); 1273 struct azx *chip = card->private_data; 1274 1275 if (client_id == VGA_SWITCHEROO_DIS) 1276 chip->bus.keep_power = 0; 1277 setup_vga_switcheroo_runtime_pm(chip); 1278 } 1279 1280 static void init_vga_switcheroo(struct azx *chip) 1281 { 1282 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1283 struct pci_dev *p = get_bound_vga(chip->pci); 1284 struct pci_dev *parent; 1285 if (p) { 1286 dev_info(chip->card->dev, 1287 "Handle vga_switcheroo audio client\n"); 1288 hda->use_vga_switcheroo = 1; 1289 1290 /* cleared in either gpu_bound op or codec probe, or when its 1291 * upstream port has _PR3 (i.e. dGPU). 1292 */ 1293 parent = pci_upstream_bridge(p); 1294 chip->bus.keep_power = parent ? !pci_pr3_present(parent) : 1; 1295 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME; 1296 pci_dev_put(p); 1297 } 1298 } 1299 1300 static const struct vga_switcheroo_client_ops azx_vs_ops = { 1301 .set_gpu_state = azx_vs_set_state, 1302 .can_switch = azx_vs_can_switch, 1303 .gpu_bound = azx_vs_gpu_bound, 1304 }; 1305 1306 static int register_vga_switcheroo(struct azx *chip) 1307 { 1308 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1309 struct pci_dev *p; 1310 int err; 1311 1312 if (!hda->use_vga_switcheroo) 1313 return 0; 1314 1315 p = get_bound_vga(chip->pci); 1316 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p); 1317 pci_dev_put(p); 1318 1319 if (err < 0) 1320 return err; 1321 hda->vga_switcheroo_registered = 1; 1322 1323 return 0; 1324 } 1325 #else 1326 #define init_vga_switcheroo(chip) /* NOP */ 1327 #define register_vga_switcheroo(chip) 0 1328 #define check_hdmi_disabled(pci) false 1329 #define setup_vga_switcheroo_runtime_pm(chip) /* NOP */ 1330 #endif /* SUPPORT_VGA_SWITCHER */ 1331 1332 /* 1333 * destructor 1334 */ 1335 static void azx_free(struct azx *chip) 1336 { 1337 struct pci_dev *pci = chip->pci; 1338 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1339 struct hdac_bus *bus = azx_bus(chip); 1340 1341 if (hda->freed) 1342 return; 1343 1344 if (azx_has_pm_runtime(chip) && chip->running) { 1345 pm_runtime_get_noresume(&pci->dev); 1346 pm_runtime_forbid(&pci->dev); 1347 pm_runtime_dont_use_autosuspend(&pci->dev); 1348 } 1349 1350 chip->running = 0; 1351 1352 azx_del_card_list(chip); 1353 1354 hda->init_failed = 1; /* to be sure */ 1355 complete_all(&hda->probe_wait); 1356 1357 if (use_vga_switcheroo(hda)) { 1358 if (chip->disabled && hda->probe_continued) 1359 snd_hda_unlock_devices(&chip->bus); 1360 if (hda->vga_switcheroo_registered) 1361 vga_switcheroo_unregister_client(chip->pci); 1362 } 1363 1364 if (bus->chip_init) { 1365 azx_clear_irq_pending(chip); 1366 azx_stop_all_streams(chip); 1367 azx_stop_chip(chip); 1368 } 1369 1370 if (bus->irq >= 0) 1371 free_irq(bus->irq, (void*)chip); 1372 1373 azx_free_stream_pages(chip); 1374 azx_free_streams(chip); 1375 snd_hdac_bus_exit(bus); 1376 1377 #ifdef CONFIG_SND_HDA_PATCH_LOADER 1378 release_firmware(chip->fw); 1379 #endif 1380 display_power(chip, false); 1381 1382 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) 1383 snd_hdac_i915_exit(bus); 1384 1385 hda->freed = 1; 1386 } 1387 1388 static int azx_dev_disconnect(struct snd_device *device) 1389 { 1390 struct azx *chip = device->device_data; 1391 struct hdac_bus *bus = azx_bus(chip); 1392 1393 chip->bus.shutdown = 1; 1394 cancel_work_sync(&bus->unsol_work); 1395 1396 return 0; 1397 } 1398 1399 static int azx_dev_free(struct snd_device *device) 1400 { 1401 azx_free(device->device_data); 1402 return 0; 1403 } 1404 1405 #ifdef SUPPORT_VGA_SWITCHEROO 1406 #ifdef CONFIG_ACPI 1407 /* ATPX is in the integrated GPU's namespace */ 1408 static bool atpx_present(void) 1409 { 1410 struct pci_dev *pdev = NULL; 1411 acpi_handle dhandle, atpx_handle; 1412 acpi_status status; 1413 1414 while ((pdev = pci_get_base_class(PCI_BASE_CLASS_DISPLAY, pdev))) { 1415 if ((pdev->class != PCI_CLASS_DISPLAY_VGA << 8) && 1416 (pdev->class != PCI_CLASS_DISPLAY_OTHER << 8)) 1417 continue; 1418 1419 dhandle = ACPI_HANDLE(&pdev->dev); 1420 if (dhandle) { 1421 status = acpi_get_handle(dhandle, "ATPX", &atpx_handle); 1422 if (ACPI_SUCCESS(status)) { 1423 pci_dev_put(pdev); 1424 return true; 1425 } 1426 } 1427 } 1428 return false; 1429 } 1430 #else 1431 static bool atpx_present(void) 1432 { 1433 return false; 1434 } 1435 #endif 1436 1437 /* 1438 * Check of disabled HDMI controller by vga_switcheroo 1439 */ 1440 static struct pci_dev *get_bound_vga(struct pci_dev *pci) 1441 { 1442 struct pci_dev *p; 1443 1444 /* check only discrete GPU */ 1445 switch (pci->vendor) { 1446 case PCI_VENDOR_ID_ATI: 1447 case PCI_VENDOR_ID_AMD: 1448 if (pci->devfn == 1) { 1449 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus), 1450 pci->bus->number, 0); 1451 if (p) { 1452 /* ATPX is in the integrated GPU's ACPI namespace 1453 * rather than the dGPU's namespace. However, 1454 * the dGPU is the one who is involved in 1455 * vgaswitcheroo. 1456 */ 1457 if (((p->class >> 16) == PCI_BASE_CLASS_DISPLAY) && 1458 (atpx_present() || apple_gmux_detect(NULL, NULL))) 1459 return p; 1460 pci_dev_put(p); 1461 } 1462 } 1463 break; 1464 case PCI_VENDOR_ID_NVIDIA: 1465 if (pci->devfn == 1) { 1466 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus), 1467 pci->bus->number, 0); 1468 if (p) { 1469 if ((p->class >> 16) == PCI_BASE_CLASS_DISPLAY) 1470 return p; 1471 pci_dev_put(p); 1472 } 1473 } 1474 break; 1475 } 1476 return NULL; 1477 } 1478 1479 static bool check_hdmi_disabled(struct pci_dev *pci) 1480 { 1481 bool vga_inactive = false; 1482 struct pci_dev *p = get_bound_vga(pci); 1483 1484 if (p) { 1485 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF) 1486 vga_inactive = true; 1487 pci_dev_put(p); 1488 } 1489 return vga_inactive; 1490 } 1491 #endif /* SUPPORT_VGA_SWITCHEROO */ 1492 1493 /* 1494 * allow/deny-listing for position_fix 1495 */ 1496 static const struct snd_pci_quirk position_fix_list[] = { 1497 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB), 1498 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB), 1499 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB), 1500 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB), 1501 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB), 1502 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB), 1503 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB), 1504 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB), 1505 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB), 1506 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB), 1507 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB), 1508 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB), 1509 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB), 1510 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB), 1511 {} 1512 }; 1513 1514 static int check_position_fix(struct azx *chip, int fix) 1515 { 1516 const struct snd_pci_quirk *q; 1517 1518 switch (fix) { 1519 case POS_FIX_AUTO: 1520 case POS_FIX_LPIB: 1521 case POS_FIX_POSBUF: 1522 case POS_FIX_VIACOMBO: 1523 case POS_FIX_COMBO: 1524 case POS_FIX_SKL: 1525 case POS_FIX_FIFO: 1526 return fix; 1527 } 1528 1529 q = snd_pci_quirk_lookup(chip->pci, position_fix_list); 1530 if (q) { 1531 dev_info(chip->card->dev, 1532 "position_fix set to %d for device %04x:%04x\n", 1533 q->value, q->subvendor, q->subdevice); 1534 return q->value; 1535 } 1536 1537 /* Check VIA/ATI HD Audio Controller exist */ 1538 if (chip->driver_type == AZX_DRIVER_VIA) { 1539 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n"); 1540 return POS_FIX_VIACOMBO; 1541 } 1542 if (chip->driver_caps & AZX_DCAPS_AMD_WORKAROUND) { 1543 dev_dbg(chip->card->dev, "Using FIFO position fix\n"); 1544 return POS_FIX_FIFO; 1545 } 1546 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) { 1547 dev_dbg(chip->card->dev, "Using LPIB position fix\n"); 1548 return POS_FIX_LPIB; 1549 } 1550 if (chip->driver_type == AZX_DRIVER_SKL) { 1551 dev_dbg(chip->card->dev, "Using SKL position fix\n"); 1552 return POS_FIX_SKL; 1553 } 1554 return POS_FIX_AUTO; 1555 } 1556 1557 static void assign_position_fix(struct azx *chip, int fix) 1558 { 1559 static const azx_get_pos_callback_t callbacks[] = { 1560 [POS_FIX_AUTO] = NULL, 1561 [POS_FIX_LPIB] = azx_get_pos_lpib, 1562 [POS_FIX_POSBUF] = azx_get_pos_posbuf, 1563 [POS_FIX_VIACOMBO] = azx_via_get_position, 1564 [POS_FIX_COMBO] = azx_get_pos_lpib, 1565 [POS_FIX_SKL] = azx_get_pos_posbuf, 1566 [POS_FIX_FIFO] = azx_get_pos_fifo, 1567 }; 1568 1569 chip->get_position[0] = chip->get_position[1] = callbacks[fix]; 1570 1571 /* combo mode uses LPIB only for playback */ 1572 if (fix == POS_FIX_COMBO) 1573 chip->get_position[1] = NULL; 1574 1575 if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) && 1576 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) { 1577 chip->get_delay[0] = chip->get_delay[1] = 1578 azx_get_delay_from_lpib; 1579 } 1580 1581 if (fix == POS_FIX_FIFO) 1582 chip->get_delay[0] = chip->get_delay[1] = 1583 azx_get_delay_from_fifo; 1584 } 1585 1586 /* 1587 * deny-lists for probe_mask 1588 */ 1589 static const struct snd_pci_quirk probe_mask_list[] = { 1590 /* Thinkpad often breaks the controller communication when accessing 1591 * to the non-working (or non-existing) modem codec slot. 1592 */ 1593 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01), 1594 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01), 1595 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01), 1596 /* broken BIOS */ 1597 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01), 1598 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */ 1599 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01), 1600 /* forced codec slots */ 1601 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103), 1602 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103), 1603 SND_PCI_QUIRK(0x1558, 0x0351, "Schenker Dock 15", 0x105), 1604 /* WinFast VP200 H (Teradici) user reported broken communication */ 1605 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101), 1606 {} 1607 }; 1608 1609 #define AZX_FORCE_CODEC_MASK 0x100 1610 1611 static void check_probe_mask(struct azx *chip, int dev) 1612 { 1613 const struct snd_pci_quirk *q; 1614 1615 chip->codec_probe_mask = probe_mask[dev]; 1616 if (chip->codec_probe_mask == -1) { 1617 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list); 1618 if (q) { 1619 dev_info(chip->card->dev, 1620 "probe_mask set to 0x%x for device %04x:%04x\n", 1621 q->value, q->subvendor, q->subdevice); 1622 chip->codec_probe_mask = q->value; 1623 } 1624 } 1625 1626 /* check forced option */ 1627 if (chip->codec_probe_mask != -1 && 1628 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) { 1629 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff; 1630 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n", 1631 (int)azx_bus(chip)->codec_mask); 1632 } 1633 } 1634 1635 /* 1636 * allow/deny-list for enable_msi 1637 */ 1638 static const struct snd_pci_quirk msi_deny_list[] = { 1639 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */ 1640 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */ 1641 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */ 1642 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */ 1643 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */ 1644 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */ 1645 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */ 1646 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */ 1647 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */ 1648 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */ 1649 {} 1650 }; 1651 1652 static void check_msi(struct azx *chip) 1653 { 1654 const struct snd_pci_quirk *q; 1655 1656 if (enable_msi >= 0) { 1657 chip->msi = !!enable_msi; 1658 return; 1659 } 1660 chip->msi = 1; /* enable MSI as default */ 1661 q = snd_pci_quirk_lookup(chip->pci, msi_deny_list); 1662 if (q) { 1663 dev_info(chip->card->dev, 1664 "msi for device %04x:%04x set to %d\n", 1665 q->subvendor, q->subdevice, q->value); 1666 chip->msi = q->value; 1667 return; 1668 } 1669 1670 /* NVidia chipsets seem to cause troubles with MSI */ 1671 if (chip->driver_caps & AZX_DCAPS_NO_MSI) { 1672 dev_info(chip->card->dev, "Disabling MSI\n"); 1673 chip->msi = 0; 1674 } 1675 } 1676 1677 /* check the snoop mode availability */ 1678 static void azx_check_snoop_available(struct azx *chip) 1679 { 1680 int snoop = hda_snoop; 1681 1682 if (snoop >= 0) { 1683 dev_info(chip->card->dev, "Force to %s mode by module option\n", 1684 snoop ? "snoop" : "non-snoop"); 1685 chip->snoop = snoop; 1686 chip->uc_buffer = !snoop; 1687 return; 1688 } 1689 1690 snoop = true; 1691 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE && 1692 chip->driver_type == AZX_DRIVER_VIA) { 1693 /* force to non-snoop mode for a new VIA controller 1694 * when BIOS is set 1695 */ 1696 u8 val; 1697 pci_read_config_byte(chip->pci, 0x42, &val); 1698 if (!(val & 0x80) && (chip->pci->revision == 0x30 || 1699 chip->pci->revision == 0x20)) 1700 snoop = false; 1701 } 1702 1703 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF) 1704 snoop = false; 1705 1706 #ifdef CONFIG_X86 1707 /* check the presence of DMA ops (i.e. IOMMU), disable snoop conditionally */ 1708 if ((chip->driver_caps & AZX_DCAPS_AMD_ALLOC_FIX) && 1709 !get_dma_ops(chip->card->dev)) 1710 snoop = false; 1711 #endif 1712 1713 chip->snoop = snoop; 1714 if (!snoop) { 1715 dev_info(chip->card->dev, "Force to non-snoop mode\n"); 1716 /* C-Media requires non-cached pages only for CORB/RIRB */ 1717 if (chip->driver_type != AZX_DRIVER_CMEDIA) 1718 chip->uc_buffer = true; 1719 } 1720 } 1721 1722 static void azx_probe_work(struct work_struct *work) 1723 { 1724 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work.work); 1725 azx_probe_continue(&hda->chip); 1726 } 1727 1728 static int default_bdl_pos_adj(struct azx *chip) 1729 { 1730 /* some exceptions: Atoms seem problematic with value 1 */ 1731 if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) { 1732 switch (chip->pci->device) { 1733 case PCI_DEVICE_ID_INTEL_HDA_BYT: 1734 case PCI_DEVICE_ID_INTEL_HDA_BSW: 1735 return 32; 1736 case PCI_DEVICE_ID_INTEL_HDA_APL: 1737 return 64; 1738 } 1739 } 1740 1741 switch (chip->driver_type) { 1742 /* 1743 * increase the bdl size for Glenfly Gpus for hardware 1744 * limitation on hdac interrupt interval 1745 */ 1746 case AZX_DRIVER_GFHDMI: 1747 return 128; 1748 case AZX_DRIVER_ICH: 1749 case AZX_DRIVER_PCH: 1750 return 1; 1751 default: 1752 return 32; 1753 } 1754 } 1755 1756 /* 1757 * constructor 1758 */ 1759 static const struct hda_controller_ops pci_hda_ops; 1760 1761 static int azx_create(struct snd_card *card, struct pci_dev *pci, 1762 int dev, unsigned int driver_caps, 1763 struct azx **rchip) 1764 { 1765 static const struct snd_device_ops ops = { 1766 .dev_disconnect = azx_dev_disconnect, 1767 .dev_free = azx_dev_free, 1768 }; 1769 struct hda_intel *hda; 1770 struct azx *chip; 1771 int err; 1772 1773 *rchip = NULL; 1774 1775 err = pcim_enable_device(pci); 1776 if (err < 0) 1777 return err; 1778 1779 hda = devm_kzalloc(&pci->dev, sizeof(*hda), GFP_KERNEL); 1780 if (!hda) 1781 return -ENOMEM; 1782 1783 chip = &hda->chip; 1784 mutex_init(&chip->open_mutex); 1785 chip->card = card; 1786 chip->pci = pci; 1787 chip->ops = &pci_hda_ops; 1788 chip->driver_caps = driver_caps; 1789 chip->driver_type = driver_caps & 0xff; 1790 check_msi(chip); 1791 chip->dev_index = dev; 1792 if (jackpoll_ms[dev] >= 50 && jackpoll_ms[dev] <= 60000) 1793 chip->jackpoll_interval = msecs_to_jiffies(jackpoll_ms[dev]); 1794 INIT_LIST_HEAD(&chip->pcm_list); 1795 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work); 1796 INIT_LIST_HEAD(&hda->list); 1797 init_vga_switcheroo(chip); 1798 init_completion(&hda->probe_wait); 1799 1800 assign_position_fix(chip, check_position_fix(chip, position_fix[dev])); 1801 1802 if (single_cmd < 0) /* allow fallback to single_cmd at errors */ 1803 chip->fallback_to_single_cmd = 1; 1804 else /* explicitly set to single_cmd or not */ 1805 chip->single_cmd = single_cmd; 1806 1807 azx_check_snoop_available(chip); 1808 1809 if (bdl_pos_adj[dev] < 0) 1810 chip->bdl_pos_adj = default_bdl_pos_adj(chip); 1811 else 1812 chip->bdl_pos_adj = bdl_pos_adj[dev]; 1813 1814 err = azx_bus_init(chip, model[dev]); 1815 if (err < 0) 1816 return err; 1817 1818 /* use the non-cached pages in non-snoop mode */ 1819 if (!azx_snoop(chip)) 1820 azx_bus(chip)->dma_type = SNDRV_DMA_TYPE_DEV_WC_SG; 1821 1822 if (chip->driver_type == AZX_DRIVER_NVIDIA) { 1823 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n"); 1824 chip->bus.core.needs_damn_long_delay = 1; 1825 } 1826 1827 check_probe_mask(chip, dev); 1828 1829 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); 1830 if (err < 0) { 1831 dev_err(card->dev, "Error creating device [card]!\n"); 1832 azx_free(chip); 1833 return err; 1834 } 1835 1836 /* continue probing in work context as may trigger request module */ 1837 INIT_DELAYED_WORK(&hda->probe_work, azx_probe_work); 1838 1839 *rchip = chip; 1840 1841 return 0; 1842 } 1843 1844 static int azx_first_init(struct azx *chip) 1845 { 1846 int dev = chip->dev_index; 1847 struct pci_dev *pci = chip->pci; 1848 struct snd_card *card = chip->card; 1849 struct hdac_bus *bus = azx_bus(chip); 1850 int err; 1851 unsigned short gcap; 1852 unsigned int dma_bits = 64; 1853 1854 #if BITS_PER_LONG != 64 1855 /* Fix up base address on ULI M5461 */ 1856 if (chip->driver_type == AZX_DRIVER_ULI) { 1857 u16 tmp3; 1858 pci_read_config_word(pci, 0x40, &tmp3); 1859 pci_write_config_word(pci, 0x40, tmp3 | 0x10); 1860 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0); 1861 } 1862 #endif 1863 /* 1864 * Fix response write request not synced to memory when handle 1865 * hdac interrupt on Glenfly Gpus 1866 */ 1867 if (chip->driver_type == AZX_DRIVER_GFHDMI) 1868 bus->polling_mode = 1; 1869 1870 if (chip->driver_type == AZX_DRIVER_LOONGSON) { 1871 bus->polling_mode = 1; 1872 bus->not_use_interrupts = 1; 1873 bus->access_sdnctl_in_dword = 1; 1874 } 1875 1876 err = pcim_iomap_regions(pci, 1 << 0, "ICH HD audio"); 1877 if (err < 0) 1878 return err; 1879 1880 bus->addr = pci_resource_start(pci, 0); 1881 bus->remap_addr = pcim_iomap_table(pci)[0]; 1882 1883 if (chip->driver_type == AZX_DRIVER_SKL) 1884 snd_hdac_bus_parse_capabilities(bus); 1885 1886 /* 1887 * Some Intel CPUs has always running timer (ART) feature and 1888 * controller may have Global time sync reporting capability, so 1889 * check both of these before declaring synchronized time reporting 1890 * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME 1891 */ 1892 chip->gts_present = false; 1893 1894 #ifdef CONFIG_X86 1895 if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART)) 1896 chip->gts_present = true; 1897 #endif 1898 1899 if (chip->msi) { 1900 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) { 1901 dev_dbg(card->dev, "Disabling 64bit MSI\n"); 1902 pci->no_64bit_msi = true; 1903 } 1904 if (pci_enable_msi(pci) < 0) 1905 chip->msi = 0; 1906 } 1907 1908 pci_set_master(pci); 1909 1910 gcap = azx_readw(chip, GCAP); 1911 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap); 1912 1913 /* AMD devices support 40 or 48bit DMA, take the safe one */ 1914 if (chip->pci->vendor == PCI_VENDOR_ID_AMD) 1915 dma_bits = 40; 1916 1917 /* disable SB600 64bit support for safety */ 1918 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) { 1919 struct pci_dev *p_smbus; 1920 dma_bits = 40; 1921 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI, 1922 PCI_DEVICE_ID_ATI_SBX00_SMBUS, 1923 NULL); 1924 if (p_smbus) { 1925 if (p_smbus->revision < 0x30) 1926 gcap &= ~AZX_GCAP_64OK; 1927 pci_dev_put(p_smbus); 1928 } 1929 } 1930 1931 /* NVidia hardware normally only supports up to 40 bits of DMA */ 1932 if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA) 1933 dma_bits = 40; 1934 1935 /* disable 64bit DMA address on some devices */ 1936 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) { 1937 dev_dbg(card->dev, "Disabling 64bit DMA\n"); 1938 gcap &= ~AZX_GCAP_64OK; 1939 } 1940 1941 /* disable buffer size rounding to 128-byte multiples if supported */ 1942 if (align_buffer_size >= 0) 1943 chip->align_buffer_size = !!align_buffer_size; 1944 else { 1945 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE) 1946 chip->align_buffer_size = 0; 1947 else 1948 chip->align_buffer_size = 1; 1949 } 1950 1951 /* allow 64bit DMA address if supported by H/W */ 1952 if (!(gcap & AZX_GCAP_64OK)) 1953 dma_bits = 32; 1954 if (dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(dma_bits))) 1955 dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(32)); 1956 dma_set_max_seg_size(&pci->dev, UINT_MAX); 1957 1958 /* read number of streams from GCAP register instead of using 1959 * hardcoded value 1960 */ 1961 chip->capture_streams = (gcap >> 8) & 0x0f; 1962 chip->playback_streams = (gcap >> 12) & 0x0f; 1963 if (!chip->playback_streams && !chip->capture_streams) { 1964 /* gcap didn't give any info, switching to old method */ 1965 1966 switch (chip->driver_type) { 1967 case AZX_DRIVER_ULI: 1968 chip->playback_streams = ULI_NUM_PLAYBACK; 1969 chip->capture_streams = ULI_NUM_CAPTURE; 1970 break; 1971 case AZX_DRIVER_ATIHDMI: 1972 case AZX_DRIVER_ATIHDMI_NS: 1973 chip->playback_streams = ATIHDMI_NUM_PLAYBACK; 1974 chip->capture_streams = ATIHDMI_NUM_CAPTURE; 1975 break; 1976 case AZX_DRIVER_GFHDMI: 1977 case AZX_DRIVER_GENERIC: 1978 default: 1979 chip->playback_streams = ICH6_NUM_PLAYBACK; 1980 chip->capture_streams = ICH6_NUM_CAPTURE; 1981 break; 1982 } 1983 } 1984 chip->capture_index_offset = 0; 1985 chip->playback_index_offset = chip->capture_streams; 1986 chip->num_streams = chip->playback_streams + chip->capture_streams; 1987 1988 /* sanity check for the SDxCTL.STRM field overflow */ 1989 if (chip->num_streams > 15 && 1990 (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) { 1991 dev_warn(chip->card->dev, "number of I/O streams is %d, " 1992 "forcing separate stream tags", chip->num_streams); 1993 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG; 1994 } 1995 1996 /* initialize streams */ 1997 err = azx_init_streams(chip); 1998 if (err < 0) 1999 return err; 2000 2001 err = azx_alloc_stream_pages(chip); 2002 if (err < 0) 2003 return err; 2004 2005 /* initialize chip */ 2006 azx_init_pci(chip); 2007 2008 snd_hdac_i915_set_bclk(bus); 2009 2010 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0); 2011 2012 /* codec detection */ 2013 if (!azx_bus(chip)->codec_mask) { 2014 dev_err(card->dev, "no codecs found!\n"); 2015 /* keep running the rest for the runtime PM */ 2016 } 2017 2018 if (azx_acquire_irq(chip, 0) < 0) 2019 return -EBUSY; 2020 2021 strcpy(card->driver, "HDA-Intel"); 2022 strscpy(card->shortname, driver_short_names[chip->driver_type], 2023 sizeof(card->shortname)); 2024 snprintf(card->longname, sizeof(card->longname), 2025 "%s at 0x%lx irq %i", 2026 card->shortname, bus->addr, bus->irq); 2027 2028 return 0; 2029 } 2030 2031 #ifdef CONFIG_SND_HDA_PATCH_LOADER 2032 /* callback from request_firmware_nowait() */ 2033 static void azx_firmware_cb(const struct firmware *fw, void *context) 2034 { 2035 struct snd_card *card = context; 2036 struct azx *chip = card->private_data; 2037 2038 if (fw) 2039 chip->fw = fw; 2040 else 2041 dev_err(card->dev, "Cannot load firmware, continue without patching\n"); 2042 if (!chip->disabled) { 2043 /* continue probing */ 2044 azx_probe_continue(chip); 2045 } 2046 } 2047 #endif 2048 2049 static int disable_msi_reset_irq(struct azx *chip) 2050 { 2051 struct hdac_bus *bus = azx_bus(chip); 2052 int err; 2053 2054 free_irq(bus->irq, chip); 2055 bus->irq = -1; 2056 chip->card->sync_irq = -1; 2057 pci_disable_msi(chip->pci); 2058 chip->msi = 0; 2059 err = azx_acquire_irq(chip, 1); 2060 if (err < 0) 2061 return err; 2062 2063 return 0; 2064 } 2065 2066 /* Denylist for skipping the whole probe: 2067 * some HD-audio PCI entries are exposed without any codecs, and such devices 2068 * should be ignored from the beginning. 2069 */ 2070 static const struct pci_device_id driver_denylist[] = { 2071 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1043, 0x874f) }, /* ASUS ROG Zenith II / Strix */ 2072 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb59) }, /* MSI TRX40 Creator */ 2073 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb60) }, /* MSI TRX40 */ 2074 { PCI_DEVICE_SUB(0x1022, 0x15e3, 0x1022, 0xd601) }, /* ASRock X670E Taichi */ 2075 {} 2076 }; 2077 2078 static const struct hda_controller_ops pci_hda_ops = { 2079 .disable_msi_reset_irq = disable_msi_reset_irq, 2080 .position_check = azx_position_check, 2081 }; 2082 2083 static DECLARE_BITMAP(probed_devs, SNDRV_CARDS); 2084 2085 static int azx_probe(struct pci_dev *pci, 2086 const struct pci_device_id *pci_id) 2087 { 2088 struct snd_card *card; 2089 struct hda_intel *hda; 2090 struct azx *chip; 2091 bool schedule_probe; 2092 int dev; 2093 int err; 2094 2095 if (pci_match_id(driver_denylist, pci)) { 2096 dev_info(&pci->dev, "Skipping the device on the denylist\n"); 2097 return -ENODEV; 2098 } 2099 2100 dev = find_first_zero_bit(probed_devs, SNDRV_CARDS); 2101 if (dev >= SNDRV_CARDS) 2102 return -ENODEV; 2103 if (!enable[dev]) { 2104 set_bit(dev, probed_devs); 2105 return -ENOENT; 2106 } 2107 2108 /* 2109 * stop probe if another Intel's DSP driver should be activated 2110 */ 2111 if (dmic_detect) { 2112 err = snd_intel_dsp_driver_probe(pci); 2113 if (err != SND_INTEL_DSP_DRIVER_ANY && err != SND_INTEL_DSP_DRIVER_LEGACY) { 2114 dev_dbg(&pci->dev, "HDAudio driver not selected, aborting probe\n"); 2115 return -ENODEV; 2116 } 2117 } else { 2118 dev_warn(&pci->dev, "dmic_detect option is deprecated, pass snd-intel-dspcfg.dsp_driver=1 option instead\n"); 2119 } 2120 2121 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE, 2122 0, &card); 2123 if (err < 0) { 2124 dev_err(&pci->dev, "Error creating card!\n"); 2125 return err; 2126 } 2127 2128 err = azx_create(card, pci, dev, pci_id->driver_data, &chip); 2129 if (err < 0) 2130 goto out_free; 2131 card->private_data = chip; 2132 hda = container_of(chip, struct hda_intel, chip); 2133 2134 pci_set_drvdata(pci, card); 2135 2136 #ifdef CONFIG_SND_HDA_I915 2137 /* bind with i915 if needed */ 2138 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) { 2139 err = snd_hdac_i915_init(azx_bus(chip)); 2140 if (err < 0) { 2141 if (err == -EPROBE_DEFER) 2142 goto out_free; 2143 2144 /* if the controller is bound only with HDMI/DP 2145 * (for HSW and BDW), we need to abort the probe; 2146 * for other chips, still continue probing as other 2147 * codecs can be on the same link. 2148 */ 2149 if (HDA_CONTROLLER_IN_GPU(pci)) { 2150 dev_err_probe(card->dev, err, 2151 "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n"); 2152 2153 goto out_free; 2154 } else { 2155 /* don't bother any longer */ 2156 chip->driver_caps &= ~AZX_DCAPS_I915_COMPONENT; 2157 } 2158 } 2159 2160 /* HSW/BDW controllers need this power */ 2161 if (HDA_CONTROLLER_IN_GPU(pci)) 2162 hda->need_i915_power = true; 2163 } 2164 #else 2165 if (HDA_CONTROLLER_IN_GPU(pci)) 2166 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n"); 2167 #endif 2168 2169 err = register_vga_switcheroo(chip); 2170 if (err < 0) { 2171 dev_err(card->dev, "Error registering vga_switcheroo client\n"); 2172 goto out_free; 2173 } 2174 2175 if (check_hdmi_disabled(pci)) { 2176 dev_info(card->dev, "VGA controller is disabled\n"); 2177 dev_info(card->dev, "Delaying initialization\n"); 2178 chip->disabled = true; 2179 } 2180 2181 schedule_probe = !chip->disabled; 2182 2183 #ifdef CONFIG_SND_HDA_PATCH_LOADER 2184 if (patch[dev] && *patch[dev]) { 2185 dev_info(card->dev, "Applying patch firmware '%s'\n", 2186 patch[dev]); 2187 err = request_firmware_nowait(THIS_MODULE, true, patch[dev], 2188 &pci->dev, GFP_KERNEL, card, 2189 azx_firmware_cb); 2190 if (err < 0) 2191 goto out_free; 2192 schedule_probe = false; /* continued in azx_firmware_cb() */ 2193 } 2194 #endif /* CONFIG_SND_HDA_PATCH_LOADER */ 2195 2196 if (schedule_probe) 2197 schedule_delayed_work(&hda->probe_work, 0); 2198 2199 set_bit(dev, probed_devs); 2200 if (chip->disabled) 2201 complete_all(&hda->probe_wait); 2202 return 0; 2203 2204 out_free: 2205 pci_set_drvdata(pci, NULL); 2206 snd_card_free(card); 2207 return err; 2208 } 2209 2210 /* On some boards setting power_save to a non 0 value leads to clicking / 2211 * popping sounds when ever we enter/leave powersaving mode. Ideally we would 2212 * figure out how to avoid these sounds, but that is not always feasible. 2213 * So we keep a list of devices where we disable powersaving as its known 2214 * to causes problems on these devices. 2215 */ 2216 static const struct snd_pci_quirk power_save_denylist[] = { 2217 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2218 SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0), 2219 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2220 SND_PCI_QUIRK(0x1849, 0x0397, "Asrock N68C-S UCC", 0), 2221 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2222 SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0), 2223 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2224 SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0), 2225 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2226 SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0), 2227 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2228 /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */ 2229 SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0), 2230 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2231 SND_PCI_QUIRK(0x8086, 0x2040, "Intel DZ77BH-55K", 0), 2232 /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */ 2233 SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0), 2234 /* https://bugs.launchpad.net/bugs/1821663 */ 2235 SND_PCI_QUIRK(0x8086, 0x2064, "Intel SDP 8086:2064", 0), 2236 /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */ 2237 SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0), 2238 /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */ 2239 SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0), 2240 SND_PCI_QUIRK(0x17aa, 0x316e, "Lenovo ThinkCentre M70q", 0), 2241 /* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */ 2242 SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0), 2243 /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */ 2244 SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0), 2245 /* https://bugs.launchpad.net/bugs/1821663 */ 2246 SND_PCI_QUIRK(0x1631, 0xe017, "Packard Bell NEC IMEDIA 5204", 0), 2247 /* KONTRON SinglePC may cause a stall at runtime resume */ 2248 SND_PCI_QUIRK(0x1734, 0x1232, "KONTRON SinglePC", 0), 2249 {} 2250 }; 2251 2252 static void set_default_power_save(struct azx *chip) 2253 { 2254 int val = power_save; 2255 2256 if (pm_blacklist) { 2257 const struct snd_pci_quirk *q; 2258 2259 q = snd_pci_quirk_lookup(chip->pci, power_save_denylist); 2260 if (q && val) { 2261 dev_info(chip->card->dev, "device %04x:%04x is on the power_save denylist, forcing power_save to 0\n", 2262 q->subvendor, q->subdevice); 2263 val = 0; 2264 } 2265 } 2266 snd_hda_set_power_save(&chip->bus, val * 1000); 2267 } 2268 2269 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */ 2270 static const unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = { 2271 [AZX_DRIVER_NVIDIA] = 8, 2272 [AZX_DRIVER_TERA] = 1, 2273 }; 2274 2275 static int azx_probe_continue(struct azx *chip) 2276 { 2277 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 2278 struct hdac_bus *bus = azx_bus(chip); 2279 struct pci_dev *pci = chip->pci; 2280 int dev = chip->dev_index; 2281 int err; 2282 2283 if (chip->disabled || hda->init_failed) 2284 return -EIO; 2285 if (hda->probe_retry) 2286 goto probe_retry; 2287 2288 to_hda_bus(bus)->bus_probing = 1; 2289 hda->probe_continued = 1; 2290 2291 /* Request display power well for the HDA controller or codec. For 2292 * Haswell/Broadwell, both the display HDA controller and codec need 2293 * this power. For other platforms, like Baytrail/Braswell, only the 2294 * display codec needs the power and it can be released after probe. 2295 */ 2296 display_power(chip, true); 2297 2298 err = azx_first_init(chip); 2299 if (err < 0) 2300 goto out_free; 2301 2302 #ifdef CONFIG_SND_HDA_INPUT_BEEP 2303 chip->beep_mode = beep_mode[dev]; 2304 #endif 2305 2306 chip->ctl_dev_id = ctl_dev_id; 2307 2308 /* create codec instances */ 2309 if (bus->codec_mask) { 2310 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]); 2311 if (err < 0) 2312 goto out_free; 2313 } 2314 2315 #ifdef CONFIG_SND_HDA_PATCH_LOADER 2316 if (chip->fw) { 2317 err = snd_hda_load_patch(&chip->bus, chip->fw->size, 2318 chip->fw->data); 2319 if (err < 0) 2320 goto out_free; 2321 } 2322 #endif 2323 2324 probe_retry: 2325 if (bus->codec_mask && !(probe_only[dev] & 1)) { 2326 err = azx_codec_configure(chip); 2327 if (err) { 2328 if ((chip->driver_caps & AZX_DCAPS_RETRY_PROBE) && 2329 ++hda->probe_retry < 60) { 2330 schedule_delayed_work(&hda->probe_work, 2331 msecs_to_jiffies(1000)); 2332 return 0; /* keep things up */ 2333 } 2334 dev_err(chip->card->dev, "Cannot probe codecs, giving up\n"); 2335 goto out_free; 2336 } 2337 } 2338 2339 err = snd_card_register(chip->card); 2340 if (err < 0) 2341 goto out_free; 2342 2343 setup_vga_switcheroo_runtime_pm(chip); 2344 2345 chip->running = 1; 2346 azx_add_card_list(chip); 2347 2348 set_default_power_save(chip); 2349 2350 if (azx_has_pm_runtime(chip)) { 2351 pm_runtime_use_autosuspend(&pci->dev); 2352 pm_runtime_allow(&pci->dev); 2353 pm_runtime_put_autosuspend(&pci->dev); 2354 } 2355 2356 out_free: 2357 if (err < 0) { 2358 pci_set_drvdata(pci, NULL); 2359 snd_card_free(chip->card); 2360 return err; 2361 } 2362 2363 if (!hda->need_i915_power) 2364 display_power(chip, false); 2365 complete_all(&hda->probe_wait); 2366 to_hda_bus(bus)->bus_probing = 0; 2367 hda->probe_retry = 0; 2368 return 0; 2369 } 2370 2371 static void azx_remove(struct pci_dev *pci) 2372 { 2373 struct snd_card *card = pci_get_drvdata(pci); 2374 struct azx *chip; 2375 struct hda_intel *hda; 2376 2377 if (card) { 2378 /* cancel the pending probing work */ 2379 chip = card->private_data; 2380 hda = container_of(chip, struct hda_intel, chip); 2381 /* FIXME: below is an ugly workaround. 2382 * Both device_release_driver() and driver_probe_device() 2383 * take *both* the device's and its parent's lock before 2384 * calling the remove() and probe() callbacks. The codec 2385 * probe takes the locks of both the codec itself and its 2386 * parent, i.e. the PCI controller dev. Meanwhile, when 2387 * the PCI controller is unbound, it takes its lock, too 2388 * ==> ouch, a deadlock! 2389 * As a workaround, we unlock temporarily here the controller 2390 * device during cancel_work_sync() call. 2391 */ 2392 device_unlock(&pci->dev); 2393 cancel_delayed_work_sync(&hda->probe_work); 2394 device_lock(&pci->dev); 2395 2396 clear_bit(chip->dev_index, probed_devs); 2397 pci_set_drvdata(pci, NULL); 2398 snd_card_free(card); 2399 } 2400 } 2401 2402 static void azx_shutdown(struct pci_dev *pci) 2403 { 2404 struct snd_card *card = pci_get_drvdata(pci); 2405 struct azx *chip; 2406 2407 if (!card) 2408 return; 2409 chip = card->private_data; 2410 if (chip && chip->running) 2411 __azx_shutdown_chip(chip, true); 2412 } 2413 2414 /* PCI IDs */ 2415 static const struct pci_device_id azx_ids[] = { 2416 /* CPT */ 2417 { PCI_DEVICE_DATA(INTEL, HDA_CPT, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM) }, 2418 /* PBG */ 2419 { PCI_DEVICE_DATA(INTEL, HDA_PBG, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM) }, 2420 /* Panther Point */ 2421 { PCI_DEVICE_DATA(INTEL, HDA_PPT, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM) }, 2422 /* Lynx Point */ 2423 { PCI_DEVICE_DATA(INTEL, HDA_LPT, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) }, 2424 /* 9 Series */ 2425 { PCI_DEVICE_DATA(INTEL, HDA_9_SERIES, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) }, 2426 /* Wellsburg */ 2427 { PCI_DEVICE_DATA(INTEL, HDA_WBG_0, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) }, 2428 { PCI_DEVICE_DATA(INTEL, HDA_WBG_1, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) }, 2429 /* Lewisburg */ 2430 { PCI_DEVICE_DATA(INTEL, HDA_LBG_0, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE) }, 2431 { PCI_DEVICE_DATA(INTEL, HDA_LBG_1, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE) }, 2432 /* Lynx Point-LP */ 2433 { PCI_DEVICE_DATA(INTEL, HDA_LPT_LP_0, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) }, 2434 /* Lynx Point-LP */ 2435 { PCI_DEVICE_DATA(INTEL, HDA_LPT_LP_1, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) }, 2436 /* Wildcat Point-LP */ 2437 { PCI_DEVICE_DATA(INTEL, HDA_WPT_LP, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH) }, 2438 /* Skylake (Sunrise Point) */ 2439 { PCI_DEVICE_DATA(INTEL, HDA_SKL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2440 /* Skylake-LP (Sunrise Point-LP) */ 2441 { PCI_DEVICE_DATA(INTEL, HDA_SKL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2442 /* Kabylake */ 2443 { PCI_DEVICE_DATA(INTEL, HDA_KBL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2444 /* Kabylake-LP */ 2445 { PCI_DEVICE_DATA(INTEL, HDA_KBL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2446 /* Kabylake-H */ 2447 { PCI_DEVICE_DATA(INTEL, HDA_KBL_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2448 /* Coffelake */ 2449 { PCI_DEVICE_DATA(INTEL, HDA_CNL_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2450 /* Cannonlake */ 2451 { PCI_DEVICE_DATA(INTEL, HDA_CNL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2452 /* CometLake-LP */ 2453 { PCI_DEVICE_DATA(INTEL, HDA_CML_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2454 /* CometLake-H */ 2455 { PCI_DEVICE_DATA(INTEL, HDA_CML_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2456 { PCI_DEVICE_DATA(INTEL, HDA_RKL_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2457 /* CometLake-S */ 2458 { PCI_DEVICE_DATA(INTEL, HDA_CML_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2459 /* CometLake-R */ 2460 { PCI_DEVICE_DATA(INTEL, HDA_CML_R, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2461 /* Icelake */ 2462 { PCI_DEVICE_DATA(INTEL, HDA_ICL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2463 /* Icelake-H */ 2464 { PCI_DEVICE_DATA(INTEL, HDA_ICL_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2465 /* Jasperlake */ 2466 { PCI_DEVICE_DATA(INTEL, HDA_ICL_N, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2467 { PCI_DEVICE_DATA(INTEL, HDA_JSL_N, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2468 /* Tigerlake */ 2469 { PCI_DEVICE_DATA(INTEL, HDA_TGL_LP, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2470 /* Tigerlake-H */ 2471 { PCI_DEVICE_DATA(INTEL, HDA_TGL_H, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2472 /* DG1 */ 2473 { PCI_DEVICE_DATA(INTEL, HDA_DG1, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2474 /* DG2 */ 2475 { PCI_DEVICE_DATA(INTEL, HDA_DG2_0, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2476 { PCI_DEVICE_DATA(INTEL, HDA_DG2_1, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2477 { PCI_DEVICE_DATA(INTEL, HDA_DG2_2, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2478 /* Alderlake-S */ 2479 { PCI_DEVICE_DATA(INTEL, HDA_ADL_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2480 /* Alderlake-P */ 2481 { PCI_DEVICE_DATA(INTEL, HDA_ADL_P, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2482 { PCI_DEVICE_DATA(INTEL, HDA_ADL_PS, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2483 { PCI_DEVICE_DATA(INTEL, HDA_ADL_PX, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2484 /* Alderlake-M */ 2485 { PCI_DEVICE_DATA(INTEL, HDA_ADL_M, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2486 /* Alderlake-N */ 2487 { PCI_DEVICE_DATA(INTEL, HDA_ADL_N, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2488 /* Elkhart Lake */ 2489 { PCI_DEVICE_DATA(INTEL, HDA_EHL_0, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2490 { PCI_DEVICE_DATA(INTEL, HDA_EHL_3, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2491 /* Raptor Lake */ 2492 { PCI_DEVICE_DATA(INTEL, HDA_RPL_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2493 { PCI_DEVICE_DATA(INTEL, HDA_RPL_P_0, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2494 { PCI_DEVICE_DATA(INTEL, HDA_RPL_P_1, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2495 { PCI_DEVICE_DATA(INTEL, HDA_RPL_M, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2496 { PCI_DEVICE_DATA(INTEL, HDA_RPL_PX, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2497 { PCI_DEVICE_DATA(INTEL, HDA_MTL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2498 /* Battlemage */ 2499 { PCI_DEVICE_DATA(INTEL, HDA_BMG, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2500 /* Lunarlake-P */ 2501 { PCI_DEVICE_DATA(INTEL, HDA_LNL_P, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_LNL) }, 2502 /* Arrow Lake-S */ 2503 { PCI_DEVICE_DATA(INTEL, HDA_ARL_S, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2504 /* Arrow Lake */ 2505 { PCI_DEVICE_DATA(INTEL, HDA_ARL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE) }, 2506 /* Panther Lake */ 2507 { PCI_DEVICE_DATA(INTEL, HDA_PTL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_LNL) }, 2508 /* Apollolake (Broxton-P) */ 2509 { PCI_DEVICE_DATA(INTEL, HDA_APL, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON) }, 2510 /* Gemini-Lake */ 2511 { PCI_DEVICE_DATA(INTEL, HDA_GML, AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON) }, 2512 /* Haswell */ 2513 { PCI_DEVICE_DATA(INTEL, HDA_HSW_0, AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL) }, 2514 { PCI_DEVICE_DATA(INTEL, HDA_HSW_2, AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL) }, 2515 { PCI_DEVICE_DATA(INTEL, HDA_HSW_3, AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL) }, 2516 /* Broadwell */ 2517 { PCI_DEVICE_DATA(INTEL, HDA_BDW, AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL) }, 2518 /* 5 Series/3400 */ 2519 { PCI_DEVICE_DATA(INTEL, HDA_5_3400_SERIES_0, AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM) }, 2520 { PCI_DEVICE_DATA(INTEL, HDA_5_3400_SERIES_1, AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM) }, 2521 /* Poulsbo */ 2522 { PCI_DEVICE_DATA(INTEL, HDA_POULSBO, AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE | 2523 AZX_DCAPS_POSFIX_LPIB) }, 2524 /* Oaktrail */ 2525 { PCI_DEVICE_DATA(INTEL, HDA_OAKTRAIL, AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE) }, 2526 /* BayTrail */ 2527 { PCI_DEVICE_DATA(INTEL, HDA_BYT, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL) }, 2528 /* Braswell */ 2529 { PCI_DEVICE_DATA(INTEL, HDA_BSW, AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL) }, 2530 /* ICH6 */ 2531 { PCI_DEVICE_DATA(INTEL, HDA_ICH6, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) }, 2532 /* ICH7 */ 2533 { PCI_DEVICE_DATA(INTEL, HDA_ICH7, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) }, 2534 /* ESB2 */ 2535 { PCI_DEVICE_DATA(INTEL, HDA_ESB2, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) }, 2536 /* ICH8 */ 2537 { PCI_DEVICE_DATA(INTEL, HDA_ICH8, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) }, 2538 /* ICH9 */ 2539 { PCI_DEVICE_DATA(INTEL, HDA_ICH9_0, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) }, 2540 /* ICH9 */ 2541 { PCI_DEVICE_DATA(INTEL, HDA_ICH9_1, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) }, 2542 /* ICH10 */ 2543 { PCI_DEVICE_DATA(INTEL, HDA_ICH10_0, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) }, 2544 /* ICH10 */ 2545 { PCI_DEVICE_DATA(INTEL, HDA_ICH10_1, AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH) }, 2546 /* Generic Intel */ 2547 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID), 2548 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2549 .class_mask = 0xffffff, 2550 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE }, 2551 /* ATI SB 450/600/700/800/900 */ 2552 { PCI_VDEVICE(ATI, 0x437b), 2553 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, 2554 { PCI_VDEVICE(ATI, 0x4383), 2555 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, 2556 /* AMD Hudson */ 2557 { PCI_VDEVICE(AMD, 0x780d), 2558 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB }, 2559 /* AMD, X370 & co */ 2560 { PCI_VDEVICE(AMD, 0x1457), 2561 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB }, 2562 /* AMD, X570 & co */ 2563 { PCI_VDEVICE(AMD, 0x1487), 2564 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB }, 2565 /* AMD Stoney */ 2566 { PCI_VDEVICE(AMD, 0x157a), 2567 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB | 2568 AZX_DCAPS_PM_RUNTIME }, 2569 /* AMD Raven */ 2570 { PCI_VDEVICE(AMD, 0x15e3), 2571 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB }, 2572 /* ATI HDMI */ 2573 { PCI_VDEVICE(ATI, 0x0002), 2574 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2575 AZX_DCAPS_PM_RUNTIME }, 2576 { PCI_VDEVICE(ATI, 0x1308), 2577 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2578 { PCI_VDEVICE(ATI, 0x157a), 2579 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2580 { PCI_VDEVICE(ATI, 0x15b3), 2581 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2582 { PCI_VDEVICE(ATI, 0x793b), 2583 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2584 { PCI_VDEVICE(ATI, 0x7919), 2585 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2586 { PCI_VDEVICE(ATI, 0x960f), 2587 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2588 { PCI_VDEVICE(ATI, 0x970f), 2589 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2590 { PCI_VDEVICE(ATI, 0x9840), 2591 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2592 { PCI_VDEVICE(ATI, 0xaa00), 2593 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2594 { PCI_VDEVICE(ATI, 0xaa08), 2595 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2596 { PCI_VDEVICE(ATI, 0xaa10), 2597 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2598 { PCI_VDEVICE(ATI, 0xaa18), 2599 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2600 { PCI_VDEVICE(ATI, 0xaa20), 2601 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2602 { PCI_VDEVICE(ATI, 0xaa28), 2603 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2604 { PCI_VDEVICE(ATI, 0xaa30), 2605 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2606 { PCI_VDEVICE(ATI, 0xaa38), 2607 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2608 { PCI_VDEVICE(ATI, 0xaa40), 2609 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2610 { PCI_VDEVICE(ATI, 0xaa48), 2611 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2612 { PCI_VDEVICE(ATI, 0xaa50), 2613 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2614 { PCI_VDEVICE(ATI, 0xaa58), 2615 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2616 { PCI_VDEVICE(ATI, 0xaa60), 2617 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2618 { PCI_VDEVICE(ATI, 0xaa68), 2619 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2620 { PCI_VDEVICE(ATI, 0xaa80), 2621 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2622 { PCI_VDEVICE(ATI, 0xaa88), 2623 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2624 { PCI_VDEVICE(ATI, 0xaa90), 2625 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2626 { PCI_VDEVICE(ATI, 0xaa98), 2627 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2628 { PCI_VDEVICE(ATI, 0x9902), 2629 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2630 { PCI_VDEVICE(ATI, 0xaaa0), 2631 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2632 { PCI_VDEVICE(ATI, 0xaaa8), 2633 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2634 { PCI_VDEVICE(ATI, 0xaab0), 2635 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2636 { PCI_VDEVICE(ATI, 0xaac0), 2637 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2638 AZX_DCAPS_PM_RUNTIME }, 2639 { PCI_VDEVICE(ATI, 0xaac8), 2640 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2641 AZX_DCAPS_PM_RUNTIME }, 2642 { PCI_VDEVICE(ATI, 0xaad8), 2643 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2644 AZX_DCAPS_PM_RUNTIME }, 2645 { PCI_VDEVICE(ATI, 0xaae0), 2646 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2647 AZX_DCAPS_PM_RUNTIME }, 2648 { PCI_VDEVICE(ATI, 0xaae8), 2649 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2650 AZX_DCAPS_PM_RUNTIME }, 2651 { PCI_VDEVICE(ATI, 0xaaf0), 2652 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2653 AZX_DCAPS_PM_RUNTIME }, 2654 { PCI_VDEVICE(ATI, 0xaaf8), 2655 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2656 AZX_DCAPS_PM_RUNTIME }, 2657 { PCI_VDEVICE(ATI, 0xab00), 2658 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2659 AZX_DCAPS_PM_RUNTIME }, 2660 { PCI_VDEVICE(ATI, 0xab08), 2661 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2662 AZX_DCAPS_PM_RUNTIME }, 2663 { PCI_VDEVICE(ATI, 0xab10), 2664 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2665 AZX_DCAPS_PM_RUNTIME }, 2666 { PCI_VDEVICE(ATI, 0xab18), 2667 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2668 AZX_DCAPS_PM_RUNTIME }, 2669 { PCI_VDEVICE(ATI, 0xab20), 2670 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2671 AZX_DCAPS_PM_RUNTIME }, 2672 { PCI_VDEVICE(ATI, 0xab28), 2673 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2674 AZX_DCAPS_PM_RUNTIME }, 2675 { PCI_VDEVICE(ATI, 0xab30), 2676 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2677 AZX_DCAPS_PM_RUNTIME }, 2678 { PCI_VDEVICE(ATI, 0xab38), 2679 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2680 AZX_DCAPS_PM_RUNTIME }, 2681 /* GLENFLY */ 2682 { PCI_DEVICE(0x6766, PCI_ANY_ID), 2683 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2684 .class_mask = 0xffffff, 2685 .driver_data = AZX_DRIVER_GFHDMI | AZX_DCAPS_POSFIX_LPIB | 2686 AZX_DCAPS_NO_MSI | AZX_DCAPS_NO_64BIT }, 2687 /* VIA VT8251/VT8237A */ 2688 { PCI_VDEVICE(VIA, 0x3288), .driver_data = AZX_DRIVER_VIA }, 2689 /* VIA GFX VT7122/VX900 */ 2690 { PCI_VDEVICE(VIA, 0x9170), .driver_data = AZX_DRIVER_GENERIC }, 2691 /* VIA GFX VT6122/VX11 */ 2692 { PCI_VDEVICE(VIA, 0x9140), .driver_data = AZX_DRIVER_GENERIC }, 2693 /* SIS966 */ 2694 { PCI_VDEVICE(SI, 0x7502), .driver_data = AZX_DRIVER_SIS }, 2695 /* ULI M5461 */ 2696 { PCI_VDEVICE(AL, 0x5461), .driver_data = AZX_DRIVER_ULI }, 2697 /* NVIDIA MCP */ 2698 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID), 2699 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2700 .class_mask = 0xffffff, 2701 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA }, 2702 /* Teradici */ 2703 { PCI_DEVICE(0x6549, 0x1200), 2704 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, 2705 { PCI_DEVICE(0x6549, 0x2200), 2706 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, 2707 /* Creative X-Fi (CA0110-IBG) */ 2708 /* CTHDA chips */ 2709 { PCI_VDEVICE(CREATIVE, 0x0010), 2710 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, 2711 { PCI_VDEVICE(CREATIVE, 0x0012), 2712 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, 2713 #if !IS_ENABLED(CONFIG_SND_CTXFI) 2714 /* the following entry conflicts with snd-ctxfi driver, 2715 * as ctxfi driver mutates from HD-audio to native mode with 2716 * a special command sequence. 2717 */ 2718 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID), 2719 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2720 .class_mask = 0xffffff, 2721 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | 2722 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB }, 2723 #else 2724 /* this entry seems still valid -- i.e. without emu20kx chip */ 2725 { PCI_VDEVICE(CREATIVE, 0x0009), 2726 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | 2727 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB }, 2728 #endif 2729 /* CM8888 */ 2730 { PCI_VDEVICE(CMEDIA, 0x5011), 2731 .driver_data = AZX_DRIVER_CMEDIA | 2732 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF }, 2733 /* Vortex86MX */ 2734 { PCI_VDEVICE(RDC, 0x3010), .driver_data = AZX_DRIVER_GENERIC }, 2735 /* VMware HDAudio */ 2736 { PCI_VDEVICE(VMWARE, 0x1977), .driver_data = AZX_DRIVER_GENERIC }, 2737 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */ 2738 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID), 2739 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2740 .class_mask = 0xffffff, 2741 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, 2742 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID), 2743 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2744 .class_mask = 0xffffff, 2745 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, 2746 /* Zhaoxin */ 2747 { PCI_VDEVICE(ZHAOXIN, 0x3288), .driver_data = AZX_DRIVER_ZHAOXIN }, 2748 /* Loongson HDAudio*/ 2749 { PCI_VDEVICE(LOONGSON, PCI_DEVICE_ID_LOONGSON_HDA), 2750 .driver_data = AZX_DRIVER_LOONGSON }, 2751 { PCI_VDEVICE(LOONGSON, PCI_DEVICE_ID_LOONGSON_HDMI), 2752 .driver_data = AZX_DRIVER_LOONGSON }, 2753 { 0, } 2754 }; 2755 MODULE_DEVICE_TABLE(pci, azx_ids); 2756 2757 /* pci_driver definition */ 2758 static struct pci_driver azx_driver = { 2759 .name = KBUILD_MODNAME, 2760 .id_table = azx_ids, 2761 .probe = azx_probe, 2762 .remove = azx_remove, 2763 .shutdown = azx_shutdown, 2764 .driver = { 2765 .pm = &azx_pm, 2766 }, 2767 }; 2768 2769 module_pci_driver(azx_driver); 2770