1 /* 2 * Driver for ESS Maestro 1/2/2E Sound Card (started 21.8.99) 3 * Copyright (c) by Matze Braun <MatzeBraun@gmx.de>. 4 * Takashi Iwai <tiwai@suse.de> 5 * 6 * Most of the driver code comes from Zach Brown(zab@redhat.com) 7 * Alan Cox OSS Driver 8 * Rewritted from card-es1938.c source. 9 * 10 * TODO: 11 * Perhaps Synth 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of the GNU General Public License as published by 15 * the Free Software Foundation; either version 2 of the License, or 16 * (at your option) any later version. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License 24 * along with this program; if not, write to the Free Software 25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 26 * 27 * 28 * Notes from Zach Brown about the driver code 29 * 30 * Hardware Description 31 * 32 * A working Maestro setup contains the Maestro chip wired to a 33 * codec or 2. In the Maestro we have the APUs, the ASSP, and the 34 * Wavecache. The APUs can be though of as virtual audio routing 35 * channels. They can take data from a number of sources and perform 36 * basic encodings of the data. The wavecache is a storehouse for 37 * PCM data. Typically it deals with PCI and interracts with the 38 * APUs. The ASSP is a wacky DSP like device that ESS is loth 39 * to release docs on. Thankfully it isn't required on the Maestro 40 * until you start doing insane things like FM emulation and surround 41 * encoding. The codecs are almost always AC-97 compliant codecs, 42 * but it appears that early Maestros may have had PT101 (an ESS 43 * part?) wired to them. The only real difference in the Maestro 44 * families is external goop like docking capability, memory for 45 * the ASSP, and initialization differences. 46 * 47 * Driver Operation 48 * 49 * We only drive the APU/Wavecache as typical DACs and drive the 50 * mixers in the codecs. There are 64 APUs. We assign 6 to each 51 * /dev/dsp? device. 2 channels for output, and 4 channels for 52 * input. 53 * 54 * Each APU can do a number of things, but we only really use 55 * 3 basic functions. For playback we use them to convert PCM 56 * data fetched over PCI by the wavecahche into analog data that 57 * is handed to the codec. One APU for mono, and a pair for stereo. 58 * When in stereo, the combination of smarts in the APU and Wavecache 59 * decide which wavecache gets the left or right channel. 60 * 61 * For record we still use the old overly mono system. For each in 62 * coming channel the data comes in from the codec, through a 'input' 63 * APU, through another rate converter APU, and then into memory via 64 * the wavecache and PCI. If its stereo, we mash it back into LRLR in 65 * software. The pass between the 2 APUs is supposedly what requires us 66 * to have a 512 byte buffer sitting around in wavecache/memory. 67 * 68 * The wavecache makes our life even more fun. First off, it can 69 * only address the first 28 bits of PCI address space, making it 70 * useless on quite a few architectures. Secondly, its insane. 71 * It claims to fetch from 4 regions of PCI space, each 4 meg in length. 72 * But that doesn't really work. You can only use 1 region. So all our 73 * allocations have to be in 4meg of each other. Booo. Hiss. 74 * So we have a module parameter, dsps_order, that is the order of 75 * the number of dsps to provide. All their buffer space is allocated 76 * on open time. The sonicvibes OSS routines we inherited really want 77 * power of 2 buffers, so we have all those next to each other, then 78 * 512 byte regions for the recording wavecaches. This ends up 79 * wasting quite a bit of memory. The only fixes I can see would be 80 * getting a kernel allocator that could work in zones, or figuring out 81 * just how to coerce the WP into doing what we want. 82 * 83 * The indirection of the various registers means we have to spinlock 84 * nearly all register accesses. We have the main register indirection 85 * like the wave cache, maestro registers, etc. Then we have beasts 86 * like the APU interface that is indirect registers gotten at through 87 * the main maestro indirection. Ouch. We spinlock around the actual 88 * ports on a per card basis. This means spinlock activity at each IO 89 * operation, but the only IO operation clusters are in non critical 90 * paths and it makes the code far easier to follow. Interrupts are 91 * blocked while holding the locks because the int handler has to 92 * get at some of them :(. The mixer interface doesn't, however. 93 * We also have an OSS state lock that is thrown around in a few 94 * places. 95 */ 96 97 #include <sound/driver.h> 98 #include <asm/io.h> 99 #include <linux/delay.h> 100 #include <linux/interrupt.h> 101 #include <linux/init.h> 102 #include <linux/pci.h> 103 #include <linux/slab.h> 104 #include <linux/gameport.h> 105 #include <linux/moduleparam.h> 106 #include <sound/core.h> 107 #include <sound/pcm.h> 108 #include <sound/mpu401.h> 109 #include <sound/ac97_codec.h> 110 #include <sound/initval.h> 111 112 #define CARD_NAME "ESS Maestro1/2" 113 #define DRIVER_NAME "ES1968" 114 115 MODULE_DESCRIPTION("ESS Maestro"); 116 MODULE_LICENSE("GPL"); 117 MODULE_SUPPORTED_DEVICE("{{ESS,Maestro 2e}," 118 "{ESS,Maestro 2}," 119 "{ESS,Maestro 1}," 120 "{TerraTec,DMX}}"); 121 122 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE)) 123 #define SUPPORT_JOYSTICK 1 124 #endif 125 126 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 1-MAX */ 127 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ 128 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */ 129 static int total_bufsize[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1024 }; 130 static int pcm_substreams_p[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 4 }; 131 static int pcm_substreams_c[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1 }; 132 static int clock[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 0}; 133 static int use_pm[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 2}; 134 static int enable_mpu[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 2}; 135 #ifdef SUPPORT_JOYSTICK 136 static int joystick[SNDRV_CARDS]; 137 #endif 138 139 module_param_array(index, int, NULL, 0444); 140 MODULE_PARM_DESC(index, "Index value for " CARD_NAME " soundcard."); 141 module_param_array(id, charp, NULL, 0444); 142 MODULE_PARM_DESC(id, "ID string for " CARD_NAME " soundcard."); 143 module_param_array(enable, bool, NULL, 0444); 144 MODULE_PARM_DESC(enable, "Enable " CARD_NAME " soundcard."); 145 module_param_array(total_bufsize, int, NULL, 0444); 146 MODULE_PARM_DESC(total_bufsize, "Total buffer size in kB."); 147 module_param_array(pcm_substreams_p, int, NULL, 0444); 148 MODULE_PARM_DESC(pcm_substreams_p, "PCM Playback substreams for " CARD_NAME " soundcard."); 149 module_param_array(pcm_substreams_c, int, NULL, 0444); 150 MODULE_PARM_DESC(pcm_substreams_c, "PCM Capture substreams for " CARD_NAME " soundcard."); 151 module_param_array(clock, int, NULL, 0444); 152 MODULE_PARM_DESC(clock, "Clock on " CARD_NAME " soundcard. (0 = auto-detect)"); 153 module_param_array(use_pm, int, NULL, 0444); 154 MODULE_PARM_DESC(use_pm, "Toggle power-management. (0 = off, 1 = on, 2 = auto)"); 155 module_param_array(enable_mpu, int, NULL, 0444); 156 MODULE_PARM_DESC(enable_mpu, "Enable MPU401. (0 = off, 1 = on, 2 = auto)"); 157 #ifdef SUPPORT_JOYSTICK 158 module_param_array(joystick, bool, NULL, 0444); 159 MODULE_PARM_DESC(joystick, "Enable joystick."); 160 #endif 161 162 163 /* PCI Dev ID's */ 164 165 #ifndef PCI_VENDOR_ID_ESS 166 #define PCI_VENDOR_ID_ESS 0x125D 167 #endif 168 169 #define PCI_VENDOR_ID_ESS_OLD 0x1285 /* Platform Tech, the people the ESS 170 was bought form */ 171 172 #ifndef PCI_DEVICE_ID_ESS_M2E 173 #define PCI_DEVICE_ID_ESS_M2E 0x1978 174 #endif 175 #ifndef PCI_DEVICE_ID_ESS_M2 176 #define PCI_DEVICE_ID_ESS_M2 0x1968 177 #endif 178 #ifndef PCI_DEVICE_ID_ESS_M1 179 #define PCI_DEVICE_ID_ESS_M1 0x0100 180 #endif 181 182 #define NR_APUS 64 183 #define NR_APU_REGS 16 184 185 /* NEC Versas ? */ 186 #define NEC_VERSA_SUBID1 0x80581033 187 #define NEC_VERSA_SUBID2 0x803c1033 188 189 /* Mode Flags */ 190 #define ESS_FMT_STEREO 0x01 191 #define ESS_FMT_16BIT 0x02 192 193 #define DAC_RUNNING 1 194 #define ADC_RUNNING 2 195 196 /* Values for the ESM_LEGACY_AUDIO_CONTROL */ 197 198 #define ESS_ENABLE_AUDIO 0x8000 199 #define ESS_ENABLE_SERIAL_IRQ 0x4000 200 #define IO_ADRESS_ALIAS 0x0020 201 #define MPU401_IRQ_ENABLE 0x0010 202 #define MPU401_IO_ENABLE 0x0008 203 #define GAME_IO_ENABLE 0x0004 204 #define FM_IO_ENABLE 0x0002 205 #define SB_IO_ENABLE 0x0001 206 207 /* Values for the ESM_CONFIG_A */ 208 209 #define PIC_SNOOP1 0x4000 210 #define PIC_SNOOP2 0x2000 211 #define SAFEGUARD 0x0800 212 #define DMA_CLEAR 0x0700 213 #define DMA_DDMA 0x0000 214 #define DMA_TDMA 0x0100 215 #define DMA_PCPCI 0x0200 216 #define POST_WRITE 0x0080 217 #define ISA_TIMING 0x0040 218 #define SWAP_LR 0x0020 219 #define SUBTR_DECODE 0x0002 220 221 /* Values for the ESM_CONFIG_B */ 222 223 #define SPDIF_CONFB 0x0100 224 #define HWV_CONFB 0x0080 225 #define DEBOUNCE 0x0040 226 #define GPIO_CONFB 0x0020 227 #define CHI_CONFB 0x0010 228 #define IDMA_CONFB 0x0008 /*undoc */ 229 #define MIDI_FIX 0x0004 /*undoc */ 230 #define IRQ_TO_ISA 0x0001 /*undoc */ 231 232 /* Values for Ring Bus Control B */ 233 #define RINGB_2CODEC_ID_MASK 0x0003 234 #define RINGB_DIS_VALIDATION 0x0008 235 #define RINGB_EN_SPDIF 0x0010 236 #define RINGB_EN_2CODEC 0x0020 237 #define RINGB_SING_BIT_DUAL 0x0040 238 239 /* ****Port Adresses**** */ 240 241 /* Write & Read */ 242 #define ESM_INDEX 0x02 243 #define ESM_DATA 0x00 244 245 /* AC97 + RingBus */ 246 #define ESM_AC97_INDEX 0x30 247 #define ESM_AC97_DATA 0x32 248 #define ESM_RING_BUS_DEST 0x34 249 #define ESM_RING_BUS_CONTR_A 0x36 250 #define ESM_RING_BUS_CONTR_B 0x38 251 #define ESM_RING_BUS_SDO 0x3A 252 253 /* WaveCache*/ 254 #define WC_INDEX 0x10 255 #define WC_DATA 0x12 256 #define WC_CONTROL 0x14 257 258 /* ASSP*/ 259 #define ASSP_INDEX 0x80 260 #define ASSP_MEMORY 0x82 261 #define ASSP_DATA 0x84 262 #define ASSP_CONTROL_A 0xA2 263 #define ASSP_CONTROL_B 0xA4 264 #define ASSP_CONTROL_C 0xA6 265 #define ASSP_HOSTW_INDEX 0xA8 266 #define ASSP_HOSTW_DATA 0xAA 267 #define ASSP_HOSTW_IRQ 0xAC 268 /* Midi */ 269 #define ESM_MPU401_PORT 0x98 270 /* Others */ 271 #define ESM_PORT_HOST_IRQ 0x18 272 273 #define IDR0_DATA_PORT 0x00 274 #define IDR1_CRAM_POINTER 0x01 275 #define IDR2_CRAM_DATA 0x02 276 #define IDR3_WAVE_DATA 0x03 277 #define IDR4_WAVE_PTR_LOW 0x04 278 #define IDR5_WAVE_PTR_HI 0x05 279 #define IDR6_TIMER_CTRL 0x06 280 #define IDR7_WAVE_ROMRAM 0x07 281 282 #define WRITEABLE_MAP 0xEFFFFF 283 #define READABLE_MAP 0x64003F 284 285 /* PCI Register */ 286 287 #define ESM_LEGACY_AUDIO_CONTROL 0x40 288 #define ESM_ACPI_COMMAND 0x54 289 #define ESM_CONFIG_A 0x50 290 #define ESM_CONFIG_B 0x52 291 #define ESM_DDMA 0x60 292 293 /* Bob Bits */ 294 #define ESM_BOB_ENABLE 0x0001 295 #define ESM_BOB_START 0x0001 296 297 /* Host IRQ Control Bits */ 298 #define ESM_RESET_MAESTRO 0x8000 299 #define ESM_RESET_DIRECTSOUND 0x4000 300 #define ESM_HIRQ_ClkRun 0x0100 301 #define ESM_HIRQ_HW_VOLUME 0x0040 302 #define ESM_HIRQ_HARPO 0x0030 /* What's that? */ 303 #define ESM_HIRQ_ASSP 0x0010 304 #define ESM_HIRQ_DSIE 0x0004 305 #define ESM_HIRQ_MPU401 0x0002 306 #define ESM_HIRQ_SB 0x0001 307 308 /* Host IRQ Status Bits */ 309 #define ESM_MPU401_IRQ 0x02 310 #define ESM_SB_IRQ 0x01 311 #define ESM_SOUND_IRQ 0x04 312 #define ESM_ASSP_IRQ 0x10 313 #define ESM_HWVOL_IRQ 0x40 314 315 #define ESS_SYSCLK 50000000 316 #define ESM_BOB_FREQ 200 317 #define ESM_BOB_FREQ_MAX 800 318 319 #define ESM_FREQ_ESM1 (49152000L / 1024L) /* default rate 48000 */ 320 #define ESM_FREQ_ESM2 (50000000L / 1024L) 321 322 /* APU Modes: reg 0x00, bit 4-7 */ 323 #define ESM_APU_MODE_SHIFT 4 324 #define ESM_APU_MODE_MASK (0xf << 4) 325 #define ESM_APU_OFF 0x00 326 #define ESM_APU_16BITLINEAR 0x01 /* 16-Bit Linear Sample Player */ 327 #define ESM_APU_16BITSTEREO 0x02 /* 16-Bit Stereo Sample Player */ 328 #define ESM_APU_8BITLINEAR 0x03 /* 8-Bit Linear Sample Player */ 329 #define ESM_APU_8BITSTEREO 0x04 /* 8-Bit Stereo Sample Player */ 330 #define ESM_APU_8BITDIFF 0x05 /* 8-Bit Differential Sample Playrer */ 331 #define ESM_APU_DIGITALDELAY 0x06 /* Digital Delay Line */ 332 #define ESM_APU_DUALTAP 0x07 /* Dual Tap Reader */ 333 #define ESM_APU_CORRELATOR 0x08 /* Correlator */ 334 #define ESM_APU_INPUTMIXER 0x09 /* Input Mixer */ 335 #define ESM_APU_WAVETABLE 0x0A /* Wave Table Mode */ 336 #define ESM_APU_SRCONVERTOR 0x0B /* Sample Rate Convertor */ 337 #define ESM_APU_16BITPINGPONG 0x0C /* 16-Bit Ping-Pong Sample Player */ 338 #define ESM_APU_RESERVED1 0x0D /* Reserved 1 */ 339 #define ESM_APU_RESERVED2 0x0E /* Reserved 2 */ 340 #define ESM_APU_RESERVED3 0x0F /* Reserved 3 */ 341 342 /* reg 0x00 */ 343 #define ESM_APU_FILTER_Q_SHIFT 0 344 #define ESM_APU_FILTER_Q_MASK (3 << 0) 345 /* APU Filtey Q Control */ 346 #define ESM_APU_FILTER_LESSQ 0x00 347 #define ESM_APU_FILTER_MOREQ 0x03 348 349 #define ESM_APU_FILTER_TYPE_SHIFT 2 350 #define ESM_APU_FILTER_TYPE_MASK (3 << 2) 351 #define ESM_APU_ENV_TYPE_SHIFT 8 352 #define ESM_APU_ENV_TYPE_MASK (3 << 8) 353 #define ESM_APU_ENV_STATE_SHIFT 10 354 #define ESM_APU_ENV_STATE_MASK (3 << 10) 355 #define ESM_APU_END_CURVE (1 << 12) 356 #define ESM_APU_INT_ON_LOOP (1 << 13) 357 #define ESM_APU_DMA_ENABLE (1 << 14) 358 359 /* reg 0x02 */ 360 #define ESM_APU_SUBMIX_GROUP_SHIRT 0 361 #define ESM_APU_SUBMIX_GROUP_MASK (7 << 0) 362 #define ESM_APU_SUBMIX_MODE (1 << 3) 363 #define ESM_APU_6dB (1 << 4) 364 #define ESM_APU_DUAL_EFFECT (1 << 5) 365 #define ESM_APU_EFFECT_CHANNELS_SHIFT 6 366 #define ESM_APU_EFFECT_CHANNELS_MASK (3 << 6) 367 368 /* reg 0x03 */ 369 #define ESM_APU_STEP_SIZE_MASK 0x0fff 370 371 /* reg 0x04 */ 372 #define ESM_APU_PHASE_SHIFT 0 373 #define ESM_APU_PHASE_MASK (0xff << 0) 374 #define ESM_APU_WAVE64K_PAGE_SHIFT 8 /* most 8bit of wave start offset */ 375 #define ESM_APU_WAVE64K_PAGE_MASK (0xff << 8) 376 377 /* reg 0x05 - wave start offset */ 378 /* reg 0x06 - wave end offset */ 379 /* reg 0x07 - wave loop length */ 380 381 /* reg 0x08 */ 382 #define ESM_APU_EFFECT_GAIN_SHIFT 0 383 #define ESM_APU_EFFECT_GAIN_MASK (0xff << 0) 384 #define ESM_APU_TREMOLO_DEPTH_SHIFT 8 385 #define ESM_APU_TREMOLO_DEPTH_MASK (0xf << 8) 386 #define ESM_APU_TREMOLO_RATE_SHIFT 12 387 #define ESM_APU_TREMOLO_RATE_MASK (0xf << 12) 388 389 /* reg 0x09 */ 390 /* bit 0-7 amplitude dest? */ 391 #define ESM_APU_AMPLITUDE_NOW_SHIFT 8 392 #define ESM_APU_AMPLITUDE_NOW_MASK (0xff << 8) 393 394 /* reg 0x0a */ 395 #define ESM_APU_POLAR_PAN_SHIFT 0 396 #define ESM_APU_POLAR_PAN_MASK (0x3f << 0) 397 /* Polar Pan Control */ 398 #define ESM_APU_PAN_CENTER_CIRCLE 0x00 399 #define ESM_APU_PAN_MIDDLE_RADIUS 0x01 400 #define ESM_APU_PAN_OUTSIDE_RADIUS 0x02 401 402 #define ESM_APU_FILTER_TUNING_SHIFT 8 403 #define ESM_APU_FILTER_TUNING_MASK (0xff << 8) 404 405 /* reg 0x0b */ 406 #define ESM_APU_DATA_SRC_A_SHIFT 0 407 #define ESM_APU_DATA_SRC_A_MASK (0x7f << 0) 408 #define ESM_APU_INV_POL_A (1 << 7) 409 #define ESM_APU_DATA_SRC_B_SHIFT 8 410 #define ESM_APU_DATA_SRC_B_MASK (0x7f << 8) 411 #define ESM_APU_INV_POL_B (1 << 15) 412 413 #define ESM_APU_VIBRATO_RATE_SHIFT 0 414 #define ESM_APU_VIBRATO_RATE_MASK (0xf << 0) 415 #define ESM_APU_VIBRATO_DEPTH_SHIFT 4 416 #define ESM_APU_VIBRATO_DEPTH_MASK (0xf << 4) 417 #define ESM_APU_VIBRATO_PHASE_SHIFT 8 418 #define ESM_APU_VIBRATO_PHASE_MASK (0xff << 8) 419 420 /* reg 0x0c */ 421 #define ESM_APU_RADIUS_SELECT (1 << 6) 422 423 /* APU Filter Control */ 424 #define ESM_APU_FILTER_2POLE_LOPASS 0x00 425 #define ESM_APU_FILTER_2POLE_BANDPASS 0x01 426 #define ESM_APU_FILTER_2POLE_HIPASS 0x02 427 #define ESM_APU_FILTER_1POLE_LOPASS 0x03 428 #define ESM_APU_FILTER_1POLE_HIPASS 0x04 429 #define ESM_APU_FILTER_OFF 0x05 430 431 /* APU ATFP Type */ 432 #define ESM_APU_ATFP_AMPLITUDE 0x00 433 #define ESM_APU_ATFP_TREMELO 0x01 434 #define ESM_APU_ATFP_FILTER 0x02 435 #define ESM_APU_ATFP_PAN 0x03 436 437 /* APU ATFP Flags */ 438 #define ESM_APU_ATFP_FLG_OFF 0x00 439 #define ESM_APU_ATFP_FLG_WAIT 0x01 440 #define ESM_APU_ATFP_FLG_DONE 0x02 441 #define ESM_APU_ATFP_FLG_INPROCESS 0x03 442 443 444 /* capture mixing buffer size */ 445 #define ESM_MEM_ALIGN 0x1000 446 #define ESM_MIXBUF_SIZE 0x400 447 448 #define ESM_MODE_PLAY 0 449 #define ESM_MODE_CAPTURE 1 450 451 /* acpi states */ 452 enum { 453 ACPI_D0=0, 454 ACPI_D1, 455 ACPI_D2, 456 ACPI_D3 457 }; 458 459 /* bits in the acpi masks */ 460 #define ACPI_12MHZ ( 1 << 15) 461 #define ACPI_24MHZ ( 1 << 14) 462 #define ACPI_978 ( 1 << 13) 463 #define ACPI_SPDIF ( 1 << 12) 464 #define ACPI_GLUE ( 1 << 11) 465 #define ACPI__10 ( 1 << 10) /* reserved */ 466 #define ACPI_PCIINT ( 1 << 9) 467 #define ACPI_HV ( 1 << 8) /* hardware volume */ 468 #define ACPI_GPIO ( 1 << 7) 469 #define ACPI_ASSP ( 1 << 6) 470 #define ACPI_SB ( 1 << 5) /* sb emul */ 471 #define ACPI_FM ( 1 << 4) /* fm emul */ 472 #define ACPI_RB ( 1 << 3) /* ringbus / aclink */ 473 #define ACPI_MIDI ( 1 << 2) 474 #define ACPI_GP ( 1 << 1) /* game port */ 475 #define ACPI_WP ( 1 << 0) /* wave processor */ 476 477 #define ACPI_ALL (0xffff) 478 #define ACPI_SLEEP (~(ACPI_SPDIF|ACPI_ASSP|ACPI_SB|ACPI_FM| \ 479 ACPI_MIDI|ACPI_GP|ACPI_WP)) 480 #define ACPI_NONE (ACPI__10) 481 482 /* these masks indicate which units we care about at 483 which states */ 484 static u16 acpi_state_mask[] = { 485 [ACPI_D0] = ACPI_ALL, 486 [ACPI_D1] = ACPI_SLEEP, 487 [ACPI_D2] = ACPI_SLEEP, 488 [ACPI_D3] = ACPI_NONE 489 }; 490 491 492 typedef struct snd_es1968 es1968_t; 493 typedef struct snd_esschan esschan_t; 494 typedef struct snd_esm_memory esm_memory_t; 495 496 /* APU use in the driver */ 497 enum snd_enum_apu_type { 498 ESM_APU_PCM_PLAY, 499 ESM_APU_PCM_CAPTURE, 500 ESM_APU_PCM_RATECONV, 501 ESM_APU_FREE 502 }; 503 504 /* chip type */ 505 enum { 506 TYPE_MAESTRO, TYPE_MAESTRO2, TYPE_MAESTRO2E 507 }; 508 509 /* DMA Hack! */ 510 struct snd_esm_memory { 511 struct snd_dma_buffer buf; 512 int empty; /* status */ 513 struct list_head list; 514 }; 515 516 /* Playback Channel */ 517 struct snd_esschan { 518 int running; 519 520 u8 apu[4]; 521 u8 apu_mode[4]; 522 523 /* playback/capture pcm buffer */ 524 esm_memory_t *memory; 525 /* capture mixer buffer */ 526 esm_memory_t *mixbuf; 527 528 unsigned int hwptr; /* current hw pointer in bytes */ 529 unsigned int count; /* sample counter in bytes */ 530 unsigned int dma_size; /* total buffer size in bytes */ 531 unsigned int frag_size; /* period size in bytes */ 532 unsigned int wav_shift; 533 u16 base[4]; /* offset for ptr */ 534 535 /* stereo/16bit flag */ 536 unsigned char fmt; 537 int mode; /* playback / capture */ 538 539 int bob_freq; /* required timer frequency */ 540 541 snd_pcm_substream_t *substream; 542 543 /* linked list */ 544 struct list_head list; 545 546 #ifdef CONFIG_PM 547 u16 wc_map[4]; 548 #endif 549 }; 550 551 struct snd_es1968 { 552 /* Module Config */ 553 int total_bufsize; /* in bytes */ 554 555 int playback_streams, capture_streams; 556 557 unsigned int clock; /* clock */ 558 /* for clock measurement */ 559 unsigned int in_measurement: 1; 560 unsigned int measure_apu; 561 unsigned int measure_lastpos; 562 unsigned int measure_count; 563 564 /* buffer */ 565 struct snd_dma_buffer dma; 566 567 /* Resources... */ 568 int irq; 569 unsigned long io_port; 570 int type; 571 struct pci_dev *pci; 572 snd_card_t *card; 573 snd_pcm_t *pcm; 574 int do_pm; /* power-management enabled */ 575 576 /* DMA memory block */ 577 struct list_head buf_list; 578 579 /* ALSA Stuff */ 580 ac97_t *ac97; 581 snd_kcontrol_t *master_switch; /* for h/w volume control */ 582 snd_kcontrol_t *master_volume; 583 584 snd_rawmidi_t *rmidi; 585 586 spinlock_t reg_lock; 587 spinlock_t ac97_lock; 588 struct tasklet_struct hwvol_tq; 589 unsigned int in_suspend; 590 591 /* Maestro Stuff */ 592 u16 maestro_map[32]; 593 int bobclient; /* active timer instancs */ 594 int bob_freq; /* timer frequency */ 595 struct semaphore memory_mutex; /* memory lock */ 596 597 /* APU states */ 598 unsigned char apu[NR_APUS]; 599 600 /* active substreams */ 601 struct list_head substream_list; 602 spinlock_t substream_lock; 603 604 #ifdef CONFIG_PM 605 u16 apu_map[NR_APUS][NR_APU_REGS]; 606 #endif 607 608 #ifdef SUPPORT_JOYSTICK 609 struct gameport *gameport; 610 #endif 611 }; 612 613 static irqreturn_t snd_es1968_interrupt(int irq, void *dev_id, struct pt_regs *regs); 614 615 static struct pci_device_id snd_es1968_ids[] = { 616 /* Maestro 1 */ 617 { 0x1285, 0x0100, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, TYPE_MAESTRO }, 618 /* Maestro 2 */ 619 { 0x125d, 0x1968, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, TYPE_MAESTRO2 }, 620 /* Maestro 2E */ 621 { 0x125d, 0x1978, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, TYPE_MAESTRO2E }, 622 { 0, } 623 }; 624 625 MODULE_DEVICE_TABLE(pci, snd_es1968_ids); 626 627 /* ********************* 628 * Low Level Funcs! * 629 *********************/ 630 631 /* no spinlock */ 632 static void __maestro_write(es1968_t *chip, u16 reg, u16 data) 633 { 634 outw(reg, chip->io_port + ESM_INDEX); 635 outw(data, chip->io_port + ESM_DATA); 636 chip->maestro_map[reg] = data; 637 } 638 639 static inline void maestro_write(es1968_t *chip, u16 reg, u16 data) 640 { 641 unsigned long flags; 642 spin_lock_irqsave(&chip->reg_lock, flags); 643 __maestro_write(chip, reg, data); 644 spin_unlock_irqrestore(&chip->reg_lock, flags); 645 } 646 647 /* no spinlock */ 648 static u16 __maestro_read(es1968_t *chip, u16 reg) 649 { 650 if (READABLE_MAP & (1 << reg)) { 651 outw(reg, chip->io_port + ESM_INDEX); 652 chip->maestro_map[reg] = inw(chip->io_port + ESM_DATA); 653 } 654 return chip->maestro_map[reg]; 655 } 656 657 static inline u16 maestro_read(es1968_t *chip, u16 reg) 658 { 659 unsigned long flags; 660 u16 result; 661 spin_lock_irqsave(&chip->reg_lock, flags); 662 result = __maestro_read(chip, reg); 663 spin_unlock_irqrestore(&chip->reg_lock, flags); 664 return result; 665 } 666 667 /* Wait for the codec bus to be free */ 668 static int snd_es1968_ac97_wait(es1968_t *chip) 669 { 670 int timeout = 100000; 671 672 while (timeout-- > 0) { 673 if (!(inb(chip->io_port + ESM_AC97_INDEX) & 1)) 674 return 0; 675 cond_resched(); 676 } 677 snd_printd("es1968: ac97 timeout\n"); 678 return 1; /* timeout */ 679 } 680 681 static void snd_es1968_ac97_write(ac97_t *ac97, unsigned short reg, unsigned short val) 682 { 683 es1968_t *chip = ac97->private_data; 684 unsigned long flags; 685 686 snd_es1968_ac97_wait(chip); 687 688 /* Write the bus */ 689 spin_lock_irqsave(&chip->ac97_lock, flags); 690 outw(val, chip->io_port + ESM_AC97_DATA); 691 /*msleep(1);*/ 692 outb(reg, chip->io_port + ESM_AC97_INDEX); 693 /*msleep(1);*/ 694 spin_unlock_irqrestore(&chip->ac97_lock, flags); 695 } 696 697 static unsigned short snd_es1968_ac97_read(ac97_t *ac97, unsigned short reg) 698 { 699 u16 data = 0; 700 es1968_t *chip = ac97->private_data; 701 unsigned long flags; 702 703 snd_es1968_ac97_wait(chip); 704 705 spin_lock_irqsave(&chip->ac97_lock, flags); 706 outb(reg | 0x80, chip->io_port + ESM_AC97_INDEX); 707 /*msleep(1);*/ 708 709 if (! snd_es1968_ac97_wait(chip)) { 710 data = inw(chip->io_port + ESM_AC97_DATA); 711 /*msleep(1);*/ 712 } 713 spin_unlock_irqrestore(&chip->ac97_lock, flags); 714 715 return data; 716 } 717 718 /* no spinlock */ 719 static void apu_index_set(es1968_t *chip, u16 index) 720 { 721 int i; 722 __maestro_write(chip, IDR1_CRAM_POINTER, index); 723 for (i = 0; i < 1000; i++) 724 if (__maestro_read(chip, IDR1_CRAM_POINTER) == index) 725 return; 726 snd_printd("es1968: APU register select failed. (Timeout)\n"); 727 } 728 729 /* no spinlock */ 730 static void apu_data_set(es1968_t *chip, u16 data) 731 { 732 int i; 733 for (i = 0; i < 1000; i++) { 734 if (__maestro_read(chip, IDR0_DATA_PORT) == data) 735 return; 736 __maestro_write(chip, IDR0_DATA_PORT, data); 737 } 738 snd_printd("es1968: APU register set probably failed (Timeout)!\n"); 739 } 740 741 /* no spinlock */ 742 static void __apu_set_register(es1968_t *chip, u16 channel, u8 reg, u16 data) 743 { 744 snd_assert(channel < NR_APUS, return); 745 #ifdef CONFIG_PM 746 chip->apu_map[channel][reg] = data; 747 #endif 748 reg |= (channel << 4); 749 apu_index_set(chip, reg); 750 apu_data_set(chip, data); 751 } 752 753 static inline void apu_set_register(es1968_t *chip, u16 channel, u8 reg, u16 data) 754 { 755 unsigned long flags; 756 spin_lock_irqsave(&chip->reg_lock, flags); 757 __apu_set_register(chip, channel, reg, data); 758 spin_unlock_irqrestore(&chip->reg_lock, flags); 759 } 760 761 static u16 __apu_get_register(es1968_t *chip, u16 channel, u8 reg) 762 { 763 snd_assert(channel < NR_APUS, return 0); 764 reg |= (channel << 4); 765 apu_index_set(chip, reg); 766 return __maestro_read(chip, IDR0_DATA_PORT); 767 } 768 769 static inline u16 apu_get_register(es1968_t *chip, u16 channel, u8 reg) 770 { 771 unsigned long flags; 772 u16 v; 773 spin_lock_irqsave(&chip->reg_lock, flags); 774 v = __apu_get_register(chip, channel, reg); 775 spin_unlock_irqrestore(&chip->reg_lock, flags); 776 return v; 777 } 778 779 #if 0 /* ASSP is not supported */ 780 781 static void assp_set_register(es1968_t *chip, u32 reg, u32 value) 782 { 783 unsigned long flags; 784 785 spin_lock_irqsave(&chip->reg_lock, flags); 786 outl(reg, chip->io_port + ASSP_INDEX); 787 outl(value, chip->io_port + ASSP_DATA); 788 spin_unlock_irqrestore(&chip->reg_lock, flags); 789 } 790 791 static u32 assp_get_register(es1968_t *chip, u32 reg) 792 { 793 unsigned long flags; 794 u32 value; 795 796 spin_lock_irqsave(&chip->reg_lock, flags); 797 outl(reg, chip->io_port + ASSP_INDEX); 798 value = inl(chip->io_port + ASSP_DATA); 799 spin_unlock_irqrestore(&chip->reg_lock, flags); 800 801 return value; 802 } 803 804 #endif 805 806 static void wave_set_register(es1968_t *chip, u16 reg, u16 value) 807 { 808 unsigned long flags; 809 810 spin_lock_irqsave(&chip->reg_lock, flags); 811 outw(reg, chip->io_port + WC_INDEX); 812 outw(value, chip->io_port + WC_DATA); 813 spin_unlock_irqrestore(&chip->reg_lock, flags); 814 } 815 816 static u16 wave_get_register(es1968_t *chip, u16 reg) 817 { 818 unsigned long flags; 819 u16 value; 820 821 spin_lock_irqsave(&chip->reg_lock, flags); 822 outw(reg, chip->io_port + WC_INDEX); 823 value = inw(chip->io_port + WC_DATA); 824 spin_unlock_irqrestore(&chip->reg_lock, flags); 825 826 return value; 827 } 828 829 /* ******************* 830 * Bob the Timer! * 831 *******************/ 832 833 static void snd_es1968_bob_stop(es1968_t *chip) 834 { 835 u16 reg; 836 837 reg = __maestro_read(chip, 0x11); 838 reg &= ~ESM_BOB_ENABLE; 839 __maestro_write(chip, 0x11, reg); 840 reg = __maestro_read(chip, 0x17); 841 reg &= ~ESM_BOB_START; 842 __maestro_write(chip, 0x17, reg); 843 } 844 845 static void snd_es1968_bob_start(es1968_t *chip) 846 { 847 int prescale; 848 int divide; 849 850 /* compute ideal interrupt frequency for buffer size & play rate */ 851 /* first, find best prescaler value to match freq */ 852 for (prescale = 5; prescale < 12; prescale++) 853 if (chip->bob_freq > (ESS_SYSCLK >> (prescale + 9))) 854 break; 855 856 /* next, back off prescaler whilst getting divider into optimum range */ 857 divide = 1; 858 while ((prescale > 5) && (divide < 32)) { 859 prescale--; 860 divide <<= 1; 861 } 862 divide >>= 1; 863 864 /* now fine-tune the divider for best match */ 865 for (; divide < 31; divide++) 866 if (chip->bob_freq > 867 ((ESS_SYSCLK >> (prescale + 9)) / (divide + 1))) break; 868 869 /* divide = 0 is illegal, but don't let prescale = 4! */ 870 if (divide == 0) { 871 divide++; 872 if (prescale > 5) 873 prescale--; 874 } else if (divide > 1) 875 divide--; 876 877 __maestro_write(chip, 6, 0x9000 | (prescale << 5) | divide); /* set reg */ 878 879 /* Now set IDR 11/17 */ 880 __maestro_write(chip, 0x11, __maestro_read(chip, 0x11) | 1); 881 __maestro_write(chip, 0x17, __maestro_read(chip, 0x17) | 1); 882 } 883 884 /* call with substream spinlock */ 885 static void snd_es1968_bob_inc(es1968_t *chip, int freq) 886 { 887 chip->bobclient++; 888 if (chip->bobclient == 1) { 889 chip->bob_freq = freq; 890 snd_es1968_bob_start(chip); 891 } else if (chip->bob_freq < freq) { 892 snd_es1968_bob_stop(chip); 893 chip->bob_freq = freq; 894 snd_es1968_bob_start(chip); 895 } 896 } 897 898 /* call with substream spinlock */ 899 static void snd_es1968_bob_dec(es1968_t *chip) 900 { 901 chip->bobclient--; 902 if (chip->bobclient <= 0) 903 snd_es1968_bob_stop(chip); 904 else if (chip->bob_freq > ESM_BOB_FREQ) { 905 /* check reduction of timer frequency */ 906 struct list_head *p; 907 int max_freq = ESM_BOB_FREQ; 908 list_for_each(p, &chip->substream_list) { 909 esschan_t *es = list_entry(p, esschan_t, list); 910 if (max_freq < es->bob_freq) 911 max_freq = es->bob_freq; 912 } 913 if (max_freq != chip->bob_freq) { 914 snd_es1968_bob_stop(chip); 915 chip->bob_freq = max_freq; 916 snd_es1968_bob_start(chip); 917 } 918 } 919 } 920 921 static int 922 snd_es1968_calc_bob_rate(es1968_t *chip, esschan_t *es, 923 snd_pcm_runtime_t *runtime) 924 { 925 /* we acquire 4 interrupts per period for precise control.. */ 926 int freq = runtime->rate * 4; 927 if (es->fmt & ESS_FMT_STEREO) 928 freq <<= 1; 929 if (es->fmt & ESS_FMT_16BIT) 930 freq <<= 1; 931 freq /= es->frag_size; 932 if (freq < ESM_BOB_FREQ) 933 freq = ESM_BOB_FREQ; 934 else if (freq > ESM_BOB_FREQ_MAX) 935 freq = ESM_BOB_FREQ_MAX; 936 return freq; 937 } 938 939 940 /************* 941 * PCM Part * 942 *************/ 943 944 static u32 snd_es1968_compute_rate(es1968_t *chip, u32 freq) 945 { 946 u32 rate = (freq << 16) / chip->clock; 947 #if 0 /* XXX: do we need this? */ 948 if (rate > 0x10000) 949 rate = 0x10000; 950 #endif 951 return rate; 952 } 953 954 /* get current pointer */ 955 static inline unsigned int 956 snd_es1968_get_dma_ptr(es1968_t *chip, esschan_t *es) 957 { 958 unsigned int offset; 959 960 offset = apu_get_register(chip, es->apu[0], 5); 961 962 offset -= es->base[0]; 963 964 return (offset & 0xFFFE); /* hardware is in words */ 965 } 966 967 static void snd_es1968_apu_set_freq(es1968_t *chip, int apu, int freq) 968 { 969 apu_set_register(chip, apu, 2, 970 (apu_get_register(chip, apu, 2) & 0x00FF) | 971 ((freq & 0xff) << 8) | 0x10); 972 apu_set_register(chip, apu, 3, freq >> 8); 973 } 974 975 /* spin lock held */ 976 static inline void snd_es1968_trigger_apu(es1968_t *esm, int apu, int mode) 977 { 978 /* set the APU mode */ 979 __apu_set_register(esm, apu, 0, 980 (__apu_get_register(esm, apu, 0) & 0xff0f) | 981 (mode << 4)); 982 } 983 984 static void snd_es1968_pcm_start(es1968_t *chip, esschan_t *es) 985 { 986 spin_lock(&chip->reg_lock); 987 __apu_set_register(chip, es->apu[0], 5, es->base[0]); 988 snd_es1968_trigger_apu(chip, es->apu[0], es->apu_mode[0]); 989 if (es->mode == ESM_MODE_CAPTURE) { 990 __apu_set_register(chip, es->apu[2], 5, es->base[2]); 991 snd_es1968_trigger_apu(chip, es->apu[2], es->apu_mode[2]); 992 } 993 if (es->fmt & ESS_FMT_STEREO) { 994 __apu_set_register(chip, es->apu[1], 5, es->base[1]); 995 snd_es1968_trigger_apu(chip, es->apu[1], es->apu_mode[1]); 996 if (es->mode == ESM_MODE_CAPTURE) { 997 __apu_set_register(chip, es->apu[3], 5, es->base[3]); 998 snd_es1968_trigger_apu(chip, es->apu[3], es->apu_mode[3]); 999 } 1000 } 1001 spin_unlock(&chip->reg_lock); 1002 } 1003 1004 static void snd_es1968_pcm_stop(es1968_t *chip, esschan_t *es) 1005 { 1006 spin_lock(&chip->reg_lock); 1007 snd_es1968_trigger_apu(chip, es->apu[0], 0); 1008 snd_es1968_trigger_apu(chip, es->apu[1], 0); 1009 if (es->mode == ESM_MODE_CAPTURE) { 1010 snd_es1968_trigger_apu(chip, es->apu[2], 0); 1011 snd_es1968_trigger_apu(chip, es->apu[3], 0); 1012 } 1013 spin_unlock(&chip->reg_lock); 1014 } 1015 1016 /* set the wavecache control reg */ 1017 static void snd_es1968_program_wavecache(es1968_t *chip, esschan_t *es, 1018 int channel, u32 addr, int capture) 1019 { 1020 u32 tmpval = (addr - 0x10) & 0xFFF8; 1021 1022 if (! capture) { 1023 if (!(es->fmt & ESS_FMT_16BIT)) 1024 tmpval |= 4; /* 8bit */ 1025 if (es->fmt & ESS_FMT_STEREO) 1026 tmpval |= 2; /* stereo */ 1027 } 1028 1029 /* set the wavecache control reg */ 1030 wave_set_register(chip, es->apu[channel] << 3, tmpval); 1031 1032 #ifdef CONFIG_PM 1033 es->wc_map[channel] = tmpval; 1034 #endif 1035 } 1036 1037 1038 static void snd_es1968_playback_setup(es1968_t *chip, esschan_t *es, 1039 snd_pcm_runtime_t *runtime) 1040 { 1041 u32 pa; 1042 int high_apu = 0; 1043 int channel, apu; 1044 int i, size; 1045 unsigned long flags; 1046 u32 freq; 1047 1048 size = es->dma_size >> es->wav_shift; 1049 1050 if (es->fmt & ESS_FMT_STEREO) 1051 high_apu++; 1052 1053 for (channel = 0; channel <= high_apu; channel++) { 1054 apu = es->apu[channel]; 1055 1056 snd_es1968_program_wavecache(chip, es, channel, es->memory->buf.addr, 0); 1057 1058 /* Offset to PCMBAR */ 1059 pa = es->memory->buf.addr; 1060 pa -= chip->dma.addr; 1061 pa >>= 1; /* words */ 1062 1063 pa |= 0x00400000; /* System RAM (Bit 22) */ 1064 1065 if (es->fmt & ESS_FMT_STEREO) { 1066 /* Enable stereo */ 1067 if (channel) 1068 pa |= 0x00800000; /* (Bit 23) */ 1069 if (es->fmt & ESS_FMT_16BIT) 1070 pa >>= 1; 1071 } 1072 1073 /* base offset of dma calcs when reading the pointer 1074 on this left one */ 1075 es->base[channel] = pa & 0xFFFF; 1076 1077 for (i = 0; i < 16; i++) 1078 apu_set_register(chip, apu, i, 0x0000); 1079 1080 /* Load the buffer into the wave engine */ 1081 apu_set_register(chip, apu, 4, ((pa >> 16) & 0xFF) << 8); 1082 apu_set_register(chip, apu, 5, pa & 0xFFFF); 1083 apu_set_register(chip, apu, 6, (pa + size) & 0xFFFF); 1084 /* setting loop == sample len */ 1085 apu_set_register(chip, apu, 7, size); 1086 1087 /* clear effects/env.. */ 1088 apu_set_register(chip, apu, 8, 0x0000); 1089 /* set amp now to 0xd0 (?), low byte is 'amplitude dest'? */ 1090 apu_set_register(chip, apu, 9, 0xD000); 1091 1092 /* clear routing stuff */ 1093 apu_set_register(chip, apu, 11, 0x0000); 1094 /* dma on, no envelopes, filter to all 1s) */ 1095 apu_set_register(chip, apu, 0, 0x400F); 1096 1097 if (es->fmt & ESS_FMT_16BIT) 1098 es->apu_mode[channel] = ESM_APU_16BITLINEAR; 1099 else 1100 es->apu_mode[channel] = ESM_APU_8BITLINEAR; 1101 1102 if (es->fmt & ESS_FMT_STEREO) { 1103 /* set panning: left or right */ 1104 /* Check: different panning. On my Canyon 3D Chipset the 1105 Channels are swapped. I don't know, about the output 1106 to the SPDif Link. Perhaps you have to change this 1107 and not the APU Regs 4-5. */ 1108 apu_set_register(chip, apu, 10, 1109 0x8F00 | (channel ? 0 : 0x10)); 1110 es->apu_mode[channel] += 1; /* stereo */ 1111 } else 1112 apu_set_register(chip, apu, 10, 0x8F08); 1113 } 1114 1115 spin_lock_irqsave(&chip->reg_lock, flags); 1116 /* clear WP interrupts */ 1117 outw(1, chip->io_port + 0x04); 1118 /* enable WP ints */ 1119 outw(inw(chip->io_port + ESM_PORT_HOST_IRQ) | ESM_HIRQ_DSIE, chip->io_port + ESM_PORT_HOST_IRQ); 1120 spin_unlock_irqrestore(&chip->reg_lock, flags); 1121 1122 freq = runtime->rate; 1123 /* set frequency */ 1124 if (freq > 48000) 1125 freq = 48000; 1126 if (freq < 4000) 1127 freq = 4000; 1128 1129 /* hmmm.. */ 1130 if (!(es->fmt & ESS_FMT_16BIT) && !(es->fmt & ESS_FMT_STEREO)) 1131 freq >>= 1; 1132 1133 freq = snd_es1968_compute_rate(chip, freq); 1134 1135 /* Load the frequency, turn on 6dB */ 1136 snd_es1968_apu_set_freq(chip, es->apu[0], freq); 1137 snd_es1968_apu_set_freq(chip, es->apu[1], freq); 1138 } 1139 1140 1141 static void init_capture_apu(es1968_t *chip, esschan_t *es, int channel, 1142 unsigned int pa, unsigned int bsize, 1143 int mode, int route) 1144 { 1145 int i, apu = es->apu[channel]; 1146 1147 es->apu_mode[channel] = mode; 1148 1149 /* set the wavecache control reg */ 1150 snd_es1968_program_wavecache(chip, es, channel, pa, 1); 1151 1152 /* Offset to PCMBAR */ 1153 pa -= chip->dma.addr; 1154 pa >>= 1; /* words */ 1155 1156 /* base offset of dma calcs when reading the pointer 1157 on this left one */ 1158 es->base[channel] = pa & 0xFFFF; 1159 pa |= 0x00400000; /* bit 22 -> System RAM */ 1160 1161 /* Begin loading the APU */ 1162 for (i = 0; i < 16; i++) 1163 apu_set_register(chip, apu, i, 0x0000); 1164 1165 /* need to enable subgroups.. and we should probably 1166 have different groups for different /dev/dsps.. */ 1167 apu_set_register(chip, apu, 2, 0x8); 1168 1169 /* Load the buffer into the wave engine */ 1170 apu_set_register(chip, apu, 4, ((pa >> 16) & 0xFF) << 8); 1171 apu_set_register(chip, apu, 5, pa & 0xFFFF); 1172 apu_set_register(chip, apu, 6, (pa + bsize) & 0xFFFF); 1173 apu_set_register(chip, apu, 7, bsize); 1174 /* clear effects/env.. */ 1175 apu_set_register(chip, apu, 8, 0x00F0); 1176 /* amplitude now? sure. why not. */ 1177 apu_set_register(chip, apu, 9, 0x0000); 1178 /* set filter tune, radius, polar pan */ 1179 apu_set_register(chip, apu, 10, 0x8F08); 1180 /* route input */ 1181 apu_set_register(chip, apu, 11, route); 1182 /* dma on, no envelopes, filter to all 1s) */ 1183 apu_set_register(chip, apu, 0, 0x400F); 1184 } 1185 1186 static void snd_es1968_capture_setup(es1968_t *chip, esschan_t *es, 1187 snd_pcm_runtime_t *runtime) 1188 { 1189 int size; 1190 u32 freq; 1191 unsigned long flags; 1192 1193 size = es->dma_size >> es->wav_shift; 1194 1195 /* APU assignments: 1196 0 = mono/left SRC 1197 1 = right SRC 1198 2 = mono/left Input Mixer 1199 3 = right Input Mixer 1200 */ 1201 /* data seems to flow from the codec, through an apu into 1202 the 'mixbuf' bit of page, then through the SRC apu 1203 and out to the real 'buffer'. ok. sure. */ 1204 1205 /* input mixer (left/mono) */ 1206 /* parallel in crap, see maestro reg 0xC [8-11] */ 1207 init_capture_apu(chip, es, 2, 1208 es->mixbuf->buf.addr, ESM_MIXBUF_SIZE/4, /* in words */ 1209 ESM_APU_INPUTMIXER, 0x14); 1210 /* SRC (left/mono); get input from inputing apu */ 1211 init_capture_apu(chip, es, 0, es->memory->buf.addr, size, 1212 ESM_APU_SRCONVERTOR, es->apu[2]); 1213 if (es->fmt & ESS_FMT_STEREO) { 1214 /* input mixer (right) */ 1215 init_capture_apu(chip, es, 3, 1216 es->mixbuf->buf.addr + ESM_MIXBUF_SIZE/2, 1217 ESM_MIXBUF_SIZE/4, /* in words */ 1218 ESM_APU_INPUTMIXER, 0x15); 1219 /* SRC (right) */ 1220 init_capture_apu(chip, es, 1, 1221 es->memory->buf.addr + size*2, size, 1222 ESM_APU_SRCONVERTOR, es->apu[3]); 1223 } 1224 1225 freq = runtime->rate; 1226 /* Sample Rate conversion APUs don't like 0x10000 for their rate */ 1227 if (freq > 47999) 1228 freq = 47999; 1229 if (freq < 4000) 1230 freq = 4000; 1231 1232 freq = snd_es1968_compute_rate(chip, freq); 1233 1234 /* Load the frequency, turn on 6dB */ 1235 snd_es1968_apu_set_freq(chip, es->apu[0], freq); 1236 snd_es1968_apu_set_freq(chip, es->apu[1], freq); 1237 1238 /* fix mixer rate at 48khz. and its _must_ be 0x10000. */ 1239 freq = 0x10000; 1240 snd_es1968_apu_set_freq(chip, es->apu[2], freq); 1241 snd_es1968_apu_set_freq(chip, es->apu[3], freq); 1242 1243 spin_lock_irqsave(&chip->reg_lock, flags); 1244 /* clear WP interrupts */ 1245 outw(1, chip->io_port + 0x04); 1246 /* enable WP ints */ 1247 outw(inw(chip->io_port + ESM_PORT_HOST_IRQ) | ESM_HIRQ_DSIE, chip->io_port + ESM_PORT_HOST_IRQ); 1248 spin_unlock_irqrestore(&chip->reg_lock, flags); 1249 } 1250 1251 /******************* 1252 * ALSA Interface * 1253 *******************/ 1254 1255 static int snd_es1968_pcm_prepare(snd_pcm_substream_t *substream) 1256 { 1257 es1968_t *chip = snd_pcm_substream_chip(substream); 1258 snd_pcm_runtime_t *runtime = substream->runtime; 1259 esschan_t *es = runtime->private_data; 1260 1261 es->dma_size = snd_pcm_lib_buffer_bytes(substream); 1262 es->frag_size = snd_pcm_lib_period_bytes(substream); 1263 1264 es->wav_shift = 1; /* maestro handles always 16bit */ 1265 es->fmt = 0; 1266 if (snd_pcm_format_width(runtime->format) == 16) 1267 es->fmt |= ESS_FMT_16BIT; 1268 if (runtime->channels > 1) { 1269 es->fmt |= ESS_FMT_STEREO; 1270 if (es->fmt & ESS_FMT_16BIT) /* 8bit is already word shifted */ 1271 es->wav_shift++; 1272 } 1273 es->bob_freq = snd_es1968_calc_bob_rate(chip, es, runtime); 1274 1275 switch (es->mode) { 1276 case ESM_MODE_PLAY: 1277 snd_es1968_playback_setup(chip, es, runtime); 1278 break; 1279 case ESM_MODE_CAPTURE: 1280 snd_es1968_capture_setup(chip, es, runtime); 1281 break; 1282 } 1283 1284 return 0; 1285 } 1286 1287 static int snd_es1968_pcm_trigger(snd_pcm_substream_t *substream, int cmd) 1288 { 1289 es1968_t *chip = snd_pcm_substream_chip(substream); 1290 esschan_t *es = substream->runtime->private_data; 1291 1292 spin_lock(&chip->substream_lock); 1293 switch (cmd) { 1294 case SNDRV_PCM_TRIGGER_START: 1295 case SNDRV_PCM_TRIGGER_RESUME: 1296 if (es->running) 1297 break; 1298 snd_es1968_bob_inc(chip, es->bob_freq); 1299 es->count = 0; 1300 es->hwptr = 0; 1301 snd_es1968_pcm_start(chip, es); 1302 es->running = 1; 1303 break; 1304 case SNDRV_PCM_TRIGGER_STOP: 1305 case SNDRV_PCM_TRIGGER_SUSPEND: 1306 if (! es->running) 1307 break; 1308 snd_es1968_pcm_stop(chip, es); 1309 es->running = 0; 1310 snd_es1968_bob_dec(chip); 1311 break; 1312 } 1313 spin_unlock(&chip->substream_lock); 1314 return 0; 1315 } 1316 1317 static snd_pcm_uframes_t snd_es1968_pcm_pointer(snd_pcm_substream_t *substream) 1318 { 1319 es1968_t *chip = snd_pcm_substream_chip(substream); 1320 esschan_t *es = substream->runtime->private_data; 1321 unsigned int ptr; 1322 1323 ptr = snd_es1968_get_dma_ptr(chip, es) << es->wav_shift; 1324 1325 return bytes_to_frames(substream->runtime, ptr % es->dma_size); 1326 } 1327 1328 static snd_pcm_hardware_t snd_es1968_playback = { 1329 .info = (SNDRV_PCM_INFO_MMAP | 1330 SNDRV_PCM_INFO_MMAP_VALID | 1331 SNDRV_PCM_INFO_INTERLEAVED | 1332 SNDRV_PCM_INFO_BLOCK_TRANSFER | 1333 /*SNDRV_PCM_INFO_PAUSE |*/ 1334 SNDRV_PCM_INFO_RESUME), 1335 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE, 1336 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, 1337 .rate_min = 4000, 1338 .rate_max = 48000, 1339 .channels_min = 1, 1340 .channels_max = 2, 1341 .buffer_bytes_max = 65536, 1342 .period_bytes_min = 256, 1343 .period_bytes_max = 65536, 1344 .periods_min = 1, 1345 .periods_max = 1024, 1346 .fifo_size = 0, 1347 }; 1348 1349 static snd_pcm_hardware_t snd_es1968_capture = { 1350 .info = (SNDRV_PCM_INFO_NONINTERLEAVED | 1351 SNDRV_PCM_INFO_MMAP | 1352 SNDRV_PCM_INFO_MMAP_VALID | 1353 SNDRV_PCM_INFO_BLOCK_TRANSFER | 1354 /*SNDRV_PCM_INFO_PAUSE |*/ 1355 SNDRV_PCM_INFO_RESUME), 1356 .formats = /*SNDRV_PCM_FMTBIT_U8 |*/ SNDRV_PCM_FMTBIT_S16_LE, 1357 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, 1358 .rate_min = 4000, 1359 .rate_max = 48000, 1360 .channels_min = 1, 1361 .channels_max = 2, 1362 .buffer_bytes_max = 65536, 1363 .period_bytes_min = 256, 1364 .period_bytes_max = 65536, 1365 .periods_min = 1, 1366 .periods_max = 1024, 1367 .fifo_size = 0, 1368 }; 1369 1370 /* ************************* 1371 * DMA memory management * 1372 *************************/ 1373 1374 /* Because the Maestro can only take addresses relative to the PCM base address 1375 register :( */ 1376 1377 static int calc_available_memory_size(es1968_t *chip) 1378 { 1379 struct list_head *p; 1380 int max_size = 0; 1381 1382 down(&chip->memory_mutex); 1383 list_for_each(p, &chip->buf_list) { 1384 esm_memory_t *buf = list_entry(p, esm_memory_t, list); 1385 if (buf->empty && buf->buf.bytes > max_size) 1386 max_size = buf->buf.bytes; 1387 } 1388 up(&chip->memory_mutex); 1389 if (max_size >= 128*1024) 1390 max_size = 127*1024; 1391 return max_size; 1392 } 1393 1394 /* allocate a new memory chunk with the specified size */ 1395 static esm_memory_t *snd_es1968_new_memory(es1968_t *chip, int size) 1396 { 1397 esm_memory_t *buf; 1398 struct list_head *p; 1399 1400 size = ((size + ESM_MEM_ALIGN - 1) / ESM_MEM_ALIGN) * ESM_MEM_ALIGN; 1401 down(&chip->memory_mutex); 1402 list_for_each(p, &chip->buf_list) { 1403 buf = list_entry(p, esm_memory_t, list); 1404 if (buf->empty && buf->buf.bytes >= size) 1405 goto __found; 1406 } 1407 up(&chip->memory_mutex); 1408 return NULL; 1409 1410 __found: 1411 if (buf->buf.bytes > size) { 1412 esm_memory_t *chunk = kmalloc(sizeof(*chunk), GFP_KERNEL); 1413 if (chunk == NULL) { 1414 up(&chip->memory_mutex); 1415 return NULL; 1416 } 1417 chunk->buf = buf->buf; 1418 chunk->buf.bytes -= size; 1419 chunk->buf.area += size; 1420 chunk->buf.addr += size; 1421 chunk->empty = 1; 1422 buf->buf.bytes = size; 1423 list_add(&chunk->list, &buf->list); 1424 } 1425 buf->empty = 0; 1426 up(&chip->memory_mutex); 1427 return buf; 1428 } 1429 1430 /* free a memory chunk */ 1431 static void snd_es1968_free_memory(es1968_t *chip, esm_memory_t *buf) 1432 { 1433 esm_memory_t *chunk; 1434 1435 down(&chip->memory_mutex); 1436 buf->empty = 1; 1437 if (buf->list.prev != &chip->buf_list) { 1438 chunk = list_entry(buf->list.prev, esm_memory_t, list); 1439 if (chunk->empty) { 1440 chunk->buf.bytes += buf->buf.bytes; 1441 list_del(&buf->list); 1442 kfree(buf); 1443 buf = chunk; 1444 } 1445 } 1446 if (buf->list.next != &chip->buf_list) { 1447 chunk = list_entry(buf->list.next, esm_memory_t, list); 1448 if (chunk->empty) { 1449 buf->buf.bytes += chunk->buf.bytes; 1450 list_del(&chunk->list); 1451 kfree(chunk); 1452 } 1453 } 1454 up(&chip->memory_mutex); 1455 } 1456 1457 static void snd_es1968_free_dmabuf(es1968_t *chip) 1458 { 1459 struct list_head *p; 1460 1461 if (! chip->dma.area) 1462 return; 1463 snd_dma_reserve_buf(&chip->dma, snd_dma_pci_buf_id(chip->pci)); 1464 while ((p = chip->buf_list.next) != &chip->buf_list) { 1465 esm_memory_t *chunk = list_entry(p, esm_memory_t, list); 1466 list_del(p); 1467 kfree(chunk); 1468 } 1469 } 1470 1471 static int __devinit 1472 snd_es1968_init_dmabuf(es1968_t *chip) 1473 { 1474 int err; 1475 esm_memory_t *chunk; 1476 1477 chip->dma.dev.type = SNDRV_DMA_TYPE_DEV; 1478 chip->dma.dev.dev = snd_dma_pci_data(chip->pci); 1479 if (! snd_dma_get_reserved_buf(&chip->dma, snd_dma_pci_buf_id(chip->pci))) { 1480 err = snd_dma_alloc_pages_fallback(SNDRV_DMA_TYPE_DEV, 1481 snd_dma_pci_data(chip->pci), 1482 chip->total_bufsize, &chip->dma); 1483 if (err < 0 || ! chip->dma.area) { 1484 snd_printk("es1968: can't allocate dma pages for size %d\n", 1485 chip->total_bufsize); 1486 return -ENOMEM; 1487 } 1488 if ((chip->dma.addr + chip->dma.bytes - 1) & ~((1 << 28) - 1)) { 1489 snd_dma_free_pages(&chip->dma); 1490 snd_printk("es1968: DMA buffer beyond 256MB.\n"); 1491 return -ENOMEM; 1492 } 1493 } 1494 1495 INIT_LIST_HEAD(&chip->buf_list); 1496 /* allocate an empty chunk */ 1497 chunk = kmalloc(sizeof(*chunk), GFP_KERNEL); 1498 if (chunk == NULL) { 1499 snd_es1968_free_dmabuf(chip); 1500 return -ENOMEM; 1501 } 1502 memset(chip->dma.area, 0, ESM_MEM_ALIGN); 1503 chunk->buf = chip->dma; 1504 chunk->buf.area += ESM_MEM_ALIGN; 1505 chunk->buf.addr += ESM_MEM_ALIGN; 1506 chunk->buf.bytes -= ESM_MEM_ALIGN; 1507 chunk->empty = 1; 1508 list_add(&chunk->list, &chip->buf_list); 1509 1510 return 0; 1511 } 1512 1513 /* setup the dma_areas */ 1514 /* buffer is extracted from the pre-allocated memory chunk */ 1515 static int snd_es1968_hw_params(snd_pcm_substream_t *substream, 1516 snd_pcm_hw_params_t *hw_params) 1517 { 1518 es1968_t *chip = snd_pcm_substream_chip(substream); 1519 snd_pcm_runtime_t *runtime = substream->runtime; 1520 esschan_t *chan = runtime->private_data; 1521 int size = params_buffer_bytes(hw_params); 1522 1523 if (chan->memory) { 1524 if (chan->memory->buf.bytes >= size) { 1525 runtime->dma_bytes = size; 1526 return 0; 1527 } 1528 snd_es1968_free_memory(chip, chan->memory); 1529 } 1530 chan->memory = snd_es1968_new_memory(chip, size); 1531 if (chan->memory == NULL) { 1532 // snd_printd("cannot allocate dma buffer: size = %d\n", size); 1533 return -ENOMEM; 1534 } 1535 snd_pcm_set_runtime_buffer(substream, &chan->memory->buf); 1536 return 1; /* area was changed */ 1537 } 1538 1539 /* remove dma areas if allocated */ 1540 static int snd_es1968_hw_free(snd_pcm_substream_t * substream) 1541 { 1542 es1968_t *chip = snd_pcm_substream_chip(substream); 1543 snd_pcm_runtime_t *runtime = substream->runtime; 1544 esschan_t *chan; 1545 1546 if (runtime->private_data == NULL) 1547 return 0; 1548 chan = runtime->private_data; 1549 if (chan->memory) { 1550 snd_es1968_free_memory(chip, chan->memory); 1551 chan->memory = NULL; 1552 } 1553 return 0; 1554 } 1555 1556 1557 /* 1558 * allocate APU pair 1559 */ 1560 static int snd_es1968_alloc_apu_pair(es1968_t *chip, int type) 1561 { 1562 int apu; 1563 1564 for (apu = 0; apu < NR_APUS; apu += 2) { 1565 if (chip->apu[apu] == ESM_APU_FREE && 1566 chip->apu[apu + 1] == ESM_APU_FREE) { 1567 chip->apu[apu] = chip->apu[apu + 1] = type; 1568 return apu; 1569 } 1570 } 1571 return -EBUSY; 1572 } 1573 1574 /* 1575 * release APU pair 1576 */ 1577 static void snd_es1968_free_apu_pair(es1968_t *chip, int apu) 1578 { 1579 chip->apu[apu] = chip->apu[apu + 1] = ESM_APU_FREE; 1580 } 1581 1582 1583 /****************** 1584 * PCM open/close * 1585 ******************/ 1586 1587 static int snd_es1968_playback_open(snd_pcm_substream_t *substream) 1588 { 1589 es1968_t *chip = snd_pcm_substream_chip(substream); 1590 snd_pcm_runtime_t *runtime = substream->runtime; 1591 esschan_t *es; 1592 int apu1; 1593 1594 /* search 2 APUs */ 1595 apu1 = snd_es1968_alloc_apu_pair(chip, ESM_APU_PCM_PLAY); 1596 if (apu1 < 0) 1597 return apu1; 1598 1599 es = kcalloc(1, sizeof(*es), GFP_KERNEL); 1600 if (!es) { 1601 snd_es1968_free_apu_pair(chip, apu1); 1602 return -ENOMEM; 1603 } 1604 1605 es->apu[0] = apu1; 1606 es->apu[1] = apu1 + 1; 1607 es->apu_mode[0] = 0; 1608 es->apu_mode[1] = 0; 1609 es->running = 0; 1610 es->substream = substream; 1611 es->mode = ESM_MODE_PLAY; 1612 1613 runtime->private_data = es; 1614 runtime->hw = snd_es1968_playback; 1615 runtime->hw.buffer_bytes_max = runtime->hw.period_bytes_max = 1616 calc_available_memory_size(chip); 1617 #if 0 1618 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 1619 1024); 1620 #endif 1621 spin_lock_irq(&chip->substream_lock); 1622 list_add(&es->list, &chip->substream_list); 1623 spin_unlock_irq(&chip->substream_lock); 1624 1625 return 0; 1626 } 1627 1628 static int snd_es1968_capture_open(snd_pcm_substream_t *substream) 1629 { 1630 snd_pcm_runtime_t *runtime = substream->runtime; 1631 es1968_t *chip = snd_pcm_substream_chip(substream); 1632 esschan_t *es; 1633 int apu1, apu2; 1634 1635 apu1 = snd_es1968_alloc_apu_pair(chip, ESM_APU_PCM_CAPTURE); 1636 if (apu1 < 0) 1637 return apu1; 1638 apu2 = snd_es1968_alloc_apu_pair(chip, ESM_APU_PCM_RATECONV); 1639 if (apu2 < 0) { 1640 snd_es1968_free_apu_pair(chip, apu1); 1641 return apu2; 1642 } 1643 1644 es = kcalloc(1, sizeof(*es), GFP_KERNEL); 1645 if (!es) { 1646 snd_es1968_free_apu_pair(chip, apu1); 1647 snd_es1968_free_apu_pair(chip, apu2); 1648 return -ENOMEM; 1649 } 1650 1651 es->apu[0] = apu1; 1652 es->apu[1] = apu1 + 1; 1653 es->apu[2] = apu2; 1654 es->apu[3] = apu2 + 1; 1655 es->apu_mode[0] = 0; 1656 es->apu_mode[1] = 0; 1657 es->apu_mode[2] = 0; 1658 es->apu_mode[3] = 0; 1659 es->running = 0; 1660 es->substream = substream; 1661 es->mode = ESM_MODE_CAPTURE; 1662 1663 /* get mixbuffer */ 1664 if ((es->mixbuf = snd_es1968_new_memory(chip, ESM_MIXBUF_SIZE)) == NULL) { 1665 snd_es1968_free_apu_pair(chip, apu1); 1666 snd_es1968_free_apu_pair(chip, apu2); 1667 kfree(es); 1668 return -ENOMEM; 1669 } 1670 memset(es->mixbuf->buf.area, 0, ESM_MIXBUF_SIZE); 1671 1672 runtime->private_data = es; 1673 runtime->hw = snd_es1968_capture; 1674 runtime->hw.buffer_bytes_max = runtime->hw.period_bytes_max = 1675 calc_available_memory_size(chip) - 1024; /* keep MIXBUF size */ 1676 #if 0 1677 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 1678 1024); 1679 #endif 1680 spin_lock_irq(&chip->substream_lock); 1681 list_add(&es->list, &chip->substream_list); 1682 spin_unlock_irq(&chip->substream_lock); 1683 1684 return 0; 1685 } 1686 1687 static int snd_es1968_playback_close(snd_pcm_substream_t * substream) 1688 { 1689 es1968_t *chip = snd_pcm_substream_chip(substream); 1690 esschan_t *es; 1691 1692 if (substream->runtime->private_data == NULL) 1693 return 0; 1694 es = substream->runtime->private_data; 1695 spin_lock_irq(&chip->substream_lock); 1696 list_del(&es->list); 1697 spin_unlock_irq(&chip->substream_lock); 1698 snd_es1968_free_apu_pair(chip, es->apu[0]); 1699 kfree(es); 1700 1701 return 0; 1702 } 1703 1704 static int snd_es1968_capture_close(snd_pcm_substream_t * substream) 1705 { 1706 es1968_t *chip = snd_pcm_substream_chip(substream); 1707 esschan_t *es; 1708 1709 if (substream->runtime->private_data == NULL) 1710 return 0; 1711 es = substream->runtime->private_data; 1712 spin_lock_irq(&chip->substream_lock); 1713 list_del(&es->list); 1714 spin_unlock_irq(&chip->substream_lock); 1715 snd_es1968_free_memory(chip, es->mixbuf); 1716 snd_es1968_free_apu_pair(chip, es->apu[0]); 1717 snd_es1968_free_apu_pair(chip, es->apu[2]); 1718 kfree(es); 1719 1720 return 0; 1721 } 1722 1723 static snd_pcm_ops_t snd_es1968_playback_ops = { 1724 .open = snd_es1968_playback_open, 1725 .close = snd_es1968_playback_close, 1726 .ioctl = snd_pcm_lib_ioctl, 1727 .hw_params = snd_es1968_hw_params, 1728 .hw_free = snd_es1968_hw_free, 1729 .prepare = snd_es1968_pcm_prepare, 1730 .trigger = snd_es1968_pcm_trigger, 1731 .pointer = snd_es1968_pcm_pointer, 1732 }; 1733 1734 static snd_pcm_ops_t snd_es1968_capture_ops = { 1735 .open = snd_es1968_capture_open, 1736 .close = snd_es1968_capture_close, 1737 .ioctl = snd_pcm_lib_ioctl, 1738 .hw_params = snd_es1968_hw_params, 1739 .hw_free = snd_es1968_hw_free, 1740 .prepare = snd_es1968_pcm_prepare, 1741 .trigger = snd_es1968_pcm_trigger, 1742 .pointer = snd_es1968_pcm_pointer, 1743 }; 1744 1745 1746 /* 1747 * measure clock 1748 */ 1749 #define CLOCK_MEASURE_BUFSIZE 16768 /* enough large for a single shot */ 1750 1751 static void __devinit es1968_measure_clock(es1968_t *chip) 1752 { 1753 int i, apu; 1754 unsigned int pa, offset, t; 1755 esm_memory_t *memory; 1756 struct timeval start_time, stop_time; 1757 1758 if (chip->clock == 0) 1759 chip->clock = 48000; /* default clock value */ 1760 1761 /* search 2 APUs (although one apu is enough) */ 1762 if ((apu = snd_es1968_alloc_apu_pair(chip, ESM_APU_PCM_PLAY)) < 0) { 1763 snd_printk("Hmm, cannot find empty APU pair!?\n"); 1764 return; 1765 } 1766 if ((memory = snd_es1968_new_memory(chip, CLOCK_MEASURE_BUFSIZE)) == NULL) { 1767 snd_printk("cannot allocate dma buffer - using default clock %d\n", chip->clock); 1768 snd_es1968_free_apu_pair(chip, apu); 1769 return; 1770 } 1771 1772 memset(memory->buf.area, 0, CLOCK_MEASURE_BUFSIZE); 1773 1774 wave_set_register(chip, apu << 3, (memory->buf.addr - 0x10) & 0xfff8); 1775 1776 pa = (unsigned int)((memory->buf.addr - chip->dma.addr) >> 1); 1777 pa |= 0x00400000; /* System RAM (Bit 22) */ 1778 1779 /* initialize apu */ 1780 for (i = 0; i < 16; i++) 1781 apu_set_register(chip, apu, i, 0x0000); 1782 1783 apu_set_register(chip, apu, 0, 0x400f); 1784 apu_set_register(chip, apu, 4, ((pa >> 16) & 0xff) << 8); 1785 apu_set_register(chip, apu, 5, pa & 0xffff); 1786 apu_set_register(chip, apu, 6, (pa + CLOCK_MEASURE_BUFSIZE/2) & 0xffff); 1787 apu_set_register(chip, apu, 7, CLOCK_MEASURE_BUFSIZE/2); 1788 apu_set_register(chip, apu, 8, 0x0000); 1789 apu_set_register(chip, apu, 9, 0xD000); 1790 apu_set_register(chip, apu, 10, 0x8F08); 1791 apu_set_register(chip, apu, 11, 0x0000); 1792 spin_lock_irq(&chip->reg_lock); 1793 outw(1, chip->io_port + 0x04); /* clear WP interrupts */ 1794 outw(inw(chip->io_port + ESM_PORT_HOST_IRQ) | ESM_HIRQ_DSIE, chip->io_port + ESM_PORT_HOST_IRQ); /* enable WP ints */ 1795 spin_unlock_irq(&chip->reg_lock); 1796 1797 snd_es1968_apu_set_freq(chip, apu, ((unsigned int)48000 << 16) / chip->clock); /* 48000 Hz */ 1798 1799 chip->in_measurement = 1; 1800 chip->measure_apu = apu; 1801 spin_lock_irq(&chip->reg_lock); 1802 snd_es1968_bob_inc(chip, ESM_BOB_FREQ); 1803 __apu_set_register(chip, apu, 5, pa & 0xffff); 1804 snd_es1968_trigger_apu(chip, apu, ESM_APU_16BITLINEAR); 1805 do_gettimeofday(&start_time); 1806 spin_unlock_irq(&chip->reg_lock); 1807 msleep(50); 1808 spin_lock_irq(&chip->reg_lock); 1809 offset = __apu_get_register(chip, apu, 5); 1810 do_gettimeofday(&stop_time); 1811 snd_es1968_trigger_apu(chip, apu, 0); /* stop */ 1812 snd_es1968_bob_dec(chip); 1813 chip->in_measurement = 0; 1814 spin_unlock_irq(&chip->reg_lock); 1815 1816 /* check the current position */ 1817 offset -= (pa & 0xffff); 1818 offset &= 0xfffe; 1819 offset += chip->measure_count * (CLOCK_MEASURE_BUFSIZE/2); 1820 1821 t = stop_time.tv_sec - start_time.tv_sec; 1822 t *= 1000000; 1823 if (stop_time.tv_usec < start_time.tv_usec) 1824 t -= start_time.tv_usec - stop_time.tv_usec; 1825 else 1826 t += stop_time.tv_usec - start_time.tv_usec; 1827 if (t == 0) { 1828 snd_printk("?? calculation error..\n"); 1829 } else { 1830 offset *= 1000; 1831 offset = (offset / t) * 1000 + ((offset % t) * 1000) / t; 1832 if (offset < 47500 || offset > 48500) { 1833 if (offset >= 40000 && offset <= 50000) 1834 chip->clock = (chip->clock * offset) / 48000; 1835 } 1836 printk(KERN_INFO "es1968: clocking to %d\n", chip->clock); 1837 } 1838 snd_es1968_free_memory(chip, memory); 1839 snd_es1968_free_apu_pair(chip, apu); 1840 } 1841 1842 1843 /* 1844 */ 1845 1846 static void snd_es1968_pcm_free(snd_pcm_t *pcm) 1847 { 1848 es1968_t *esm = pcm->private_data; 1849 snd_es1968_free_dmabuf(esm); 1850 esm->pcm = NULL; 1851 } 1852 1853 static int __devinit 1854 snd_es1968_pcm(es1968_t *chip, int device) 1855 { 1856 snd_pcm_t *pcm; 1857 int err; 1858 1859 /* get DMA buffer */ 1860 if ((err = snd_es1968_init_dmabuf(chip)) < 0) 1861 return err; 1862 1863 /* set PCMBAR */ 1864 wave_set_register(chip, 0x01FC, chip->dma.addr >> 12); 1865 wave_set_register(chip, 0x01FD, chip->dma.addr >> 12); 1866 wave_set_register(chip, 0x01FE, chip->dma.addr >> 12); 1867 wave_set_register(chip, 0x01FF, chip->dma.addr >> 12); 1868 1869 if ((err = snd_pcm_new(chip->card, "ESS Maestro", device, 1870 chip->playback_streams, 1871 chip->capture_streams, &pcm)) < 0) 1872 return err; 1873 1874 pcm->private_data = chip; 1875 pcm->private_free = snd_es1968_pcm_free; 1876 1877 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_es1968_playback_ops); 1878 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_es1968_capture_ops); 1879 1880 pcm->info_flags = 0; 1881 1882 strcpy(pcm->name, "ESS Maestro"); 1883 1884 chip->pcm = pcm; 1885 1886 return 0; 1887 } 1888 1889 /* 1890 * update pointer 1891 */ 1892 static void snd_es1968_update_pcm(es1968_t *chip, esschan_t *es) 1893 { 1894 unsigned int hwptr; 1895 unsigned int diff; 1896 snd_pcm_substream_t *subs = es->substream; 1897 1898 if (subs == NULL || !es->running) 1899 return; 1900 1901 hwptr = snd_es1968_get_dma_ptr(chip, es) << es->wav_shift; 1902 hwptr %= es->dma_size; 1903 1904 diff = (es->dma_size + hwptr - es->hwptr) % es->dma_size; 1905 1906 es->hwptr = hwptr; 1907 es->count += diff; 1908 1909 if (es->count > es->frag_size) { 1910 spin_unlock(&chip->substream_lock); 1911 snd_pcm_period_elapsed(subs); 1912 spin_lock(&chip->substream_lock); 1913 es->count %= es->frag_size; 1914 } 1915 } 1916 1917 /* 1918 */ 1919 static void es1968_update_hw_volume(unsigned long private_data) 1920 { 1921 es1968_t *chip = (es1968_t *) private_data; 1922 int x, val; 1923 unsigned long flags; 1924 1925 /* Figure out which volume control button was pushed, 1926 based on differences from the default register 1927 values. */ 1928 x = inb(chip->io_port + 0x1c); 1929 /* Reset the volume control registers. */ 1930 outb(0x88, chip->io_port + 0x1c); 1931 outb(0x88, chip->io_port + 0x1d); 1932 outb(0x88, chip->io_port + 0x1e); 1933 outb(0x88, chip->io_port + 0x1f); 1934 1935 if (chip->in_suspend) 1936 return; 1937 1938 if (! chip->master_switch || ! chip->master_volume) 1939 return; 1940 1941 /* FIXME: we can't call snd_ac97_* functions since here is in tasklet. */ 1942 spin_lock_irqsave(&chip->ac97_lock, flags); 1943 val = chip->ac97->regs[AC97_MASTER]; 1944 if (x & 1) { 1945 /* mute */ 1946 val ^= 0x8000; 1947 chip->ac97->regs[AC97_MASTER] = val; 1948 outw(val, chip->io_port + ESM_AC97_DATA); 1949 outb(AC97_MASTER, chip->io_port + ESM_AC97_INDEX); 1950 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE, 1951 &chip->master_switch->id); 1952 } else { 1953 val &= 0x7fff; 1954 if (((x>>1) & 7) > 4) { 1955 /* volume up */ 1956 if ((val & 0xff) > 0) 1957 val--; 1958 if ((val & 0xff00) > 0) 1959 val -= 0x0100; 1960 } else { 1961 /* volume down */ 1962 if ((val & 0xff) < 0x1f) 1963 val++; 1964 if ((val & 0xff00) < 0x1f00) 1965 val += 0x0100; 1966 } 1967 chip->ac97->regs[AC97_MASTER] = val; 1968 outw(val, chip->io_port + ESM_AC97_DATA); 1969 outb(AC97_MASTER, chip->io_port + ESM_AC97_INDEX); 1970 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE, 1971 &chip->master_volume->id); 1972 } 1973 spin_unlock_irqrestore(&chip->ac97_lock, flags); 1974 } 1975 1976 /* 1977 * interrupt handler 1978 */ 1979 static irqreturn_t snd_es1968_interrupt(int irq, void *dev_id, struct pt_regs *regs) 1980 { 1981 es1968_t *chip = dev_id; 1982 u32 event; 1983 1984 if (!(event = inb(chip->io_port + 0x1A))) 1985 return IRQ_NONE; 1986 1987 outw(inw(chip->io_port + 4) & 1, chip->io_port + 4); 1988 1989 if (event & ESM_HWVOL_IRQ) 1990 tasklet_hi_schedule(&chip->hwvol_tq); /* we'll do this later */ 1991 1992 /* else ack 'em all, i imagine */ 1993 outb(0xFF, chip->io_port + 0x1A); 1994 1995 if ((event & ESM_MPU401_IRQ) && chip->rmidi) { 1996 snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data, regs); 1997 } 1998 1999 if (event & ESM_SOUND_IRQ) { 2000 struct list_head *p; 2001 spin_lock(&chip->substream_lock); 2002 list_for_each(p, &chip->substream_list) { 2003 esschan_t *es = list_entry(p, esschan_t, list); 2004 if (es->running) 2005 snd_es1968_update_pcm(chip, es); 2006 } 2007 spin_unlock(&chip->substream_lock); 2008 if (chip->in_measurement) { 2009 unsigned int curp = __apu_get_register(chip, chip->measure_apu, 5); 2010 if (curp < chip->measure_lastpos) 2011 chip->measure_count++; 2012 chip->measure_lastpos = curp; 2013 } 2014 } 2015 2016 return IRQ_HANDLED; 2017 } 2018 2019 /* 2020 * Mixer stuff 2021 */ 2022 2023 static int __devinit 2024 snd_es1968_mixer(es1968_t *chip) 2025 { 2026 ac97_bus_t *pbus; 2027 ac97_template_t ac97; 2028 snd_ctl_elem_id_t id; 2029 int err; 2030 static ac97_bus_ops_t ops = { 2031 .write = snd_es1968_ac97_write, 2032 .read = snd_es1968_ac97_read, 2033 }; 2034 2035 if ((err = snd_ac97_bus(chip->card, 0, &ops, NULL, &pbus)) < 0) 2036 return err; 2037 pbus->no_vra = 1; /* ES1968 doesn't need VRA */ 2038 2039 memset(&ac97, 0, sizeof(ac97)); 2040 ac97.private_data = chip; 2041 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97)) < 0) 2042 return err; 2043 2044 /* attach master switch / volumes for h/w volume control */ 2045 memset(&id, 0, sizeof(id)); 2046 id.iface = SNDRV_CTL_ELEM_IFACE_MIXER; 2047 strcpy(id.name, "Master Playback Switch"); 2048 chip->master_switch = snd_ctl_find_id(chip->card, &id); 2049 memset(&id, 0, sizeof(id)); 2050 id.iface = SNDRV_CTL_ELEM_IFACE_MIXER; 2051 strcpy(id.name, "Master Playback Volume"); 2052 chip->master_volume = snd_ctl_find_id(chip->card, &id); 2053 2054 return 0; 2055 } 2056 2057 /* 2058 * reset ac97 codec 2059 */ 2060 2061 static void snd_es1968_ac97_reset(es1968_t *chip) 2062 { 2063 unsigned long ioaddr = chip->io_port; 2064 2065 unsigned short save_ringbus_a; 2066 unsigned short save_68; 2067 unsigned short w; 2068 unsigned int vend; 2069 2070 /* save configuration */ 2071 save_ringbus_a = inw(ioaddr + 0x36); 2072 2073 //outw(inw(ioaddr + 0x38) & 0xfffc, ioaddr + 0x38); /* clear second codec id? */ 2074 /* set command/status address i/o to 1st codec */ 2075 outw(inw(ioaddr + 0x3a) & 0xfffc, ioaddr + 0x3a); 2076 outw(inw(ioaddr + 0x3c) & 0xfffc, ioaddr + 0x3c); 2077 2078 /* disable ac link */ 2079 outw(0x0000, ioaddr + 0x36); 2080 save_68 = inw(ioaddr + 0x68); 2081 pci_read_config_word(chip->pci, 0x58, &w); /* something magical with gpio and bus arb. */ 2082 pci_read_config_dword(chip->pci, PCI_SUBSYSTEM_VENDOR_ID, &vend); 2083 if (w & 1) 2084 save_68 |= 0x10; 2085 outw(0xfffe, ioaddr + 0x64); /* unmask gpio 0 */ 2086 outw(0x0001, ioaddr + 0x68); /* gpio write */ 2087 outw(0x0000, ioaddr + 0x60); /* write 0 to gpio 0 */ 2088 udelay(20); 2089 outw(0x0001, ioaddr + 0x60); /* write 1 to gpio 1 */ 2090 msleep(20); 2091 2092 outw(save_68 | 0x1, ioaddr + 0x68); /* now restore .. */ 2093 outw((inw(ioaddr + 0x38) & 0xfffc) | 0x1, ioaddr + 0x38); 2094 outw((inw(ioaddr + 0x3a) & 0xfffc) | 0x1, ioaddr + 0x3a); 2095 outw((inw(ioaddr + 0x3c) & 0xfffc) | 0x1, ioaddr + 0x3c); 2096 2097 /* now the second codec */ 2098 /* disable ac link */ 2099 outw(0x0000, ioaddr + 0x36); 2100 outw(0xfff7, ioaddr + 0x64); /* unmask gpio 3 */ 2101 save_68 = inw(ioaddr + 0x68); 2102 outw(0x0009, ioaddr + 0x68); /* gpio write 0 & 3 ?? */ 2103 outw(0x0001, ioaddr + 0x60); /* write 1 to gpio */ 2104 udelay(20); 2105 outw(0x0009, ioaddr + 0x60); /* write 9 to gpio */ 2106 msleep(500); 2107 //outw(inw(ioaddr + 0x38) & 0xfffc, ioaddr + 0x38); 2108 outw(inw(ioaddr + 0x3a) & 0xfffc, ioaddr + 0x3a); 2109 outw(inw(ioaddr + 0x3c) & 0xfffc, ioaddr + 0x3c); 2110 2111 #if 0 /* the loop here needs to be much better if we want it.. */ 2112 snd_printk("trying software reset\n"); 2113 /* try and do a software reset */ 2114 outb(0x80 | 0x7c, ioaddr + 0x30); 2115 for (w = 0;; w++) { 2116 if ((inw(ioaddr + 0x30) & 1) == 0) { 2117 if (inb(ioaddr + 0x32) != 0) 2118 break; 2119 2120 outb(0x80 | 0x7d, ioaddr + 0x30); 2121 if (((inw(ioaddr + 0x30) & 1) == 0) 2122 && (inb(ioaddr + 0x32) != 0)) 2123 break; 2124 outb(0x80 | 0x7f, ioaddr + 0x30); 2125 if (((inw(ioaddr + 0x30) & 1) == 0) 2126 && (inb(ioaddr + 0x32) != 0)) 2127 break; 2128 } 2129 2130 if (w > 10000) { 2131 outb(inb(ioaddr + 0x37) | 0x08, ioaddr + 0x37); /* do a software reset */ 2132 msleep(500); /* oh my.. */ 2133 outb(inb(ioaddr + 0x37) & ~0x08, 2134 ioaddr + 0x37); 2135 udelay(1); 2136 outw(0x80, ioaddr + 0x30); 2137 for (w = 0; w < 10000; w++) { 2138 if ((inw(ioaddr + 0x30) & 1) == 0) 2139 break; 2140 } 2141 } 2142 } 2143 #endif 2144 if (vend == NEC_VERSA_SUBID1 || vend == NEC_VERSA_SUBID2) { 2145 /* turn on external amp? */ 2146 outw(0xf9ff, ioaddr + 0x64); 2147 outw(inw(ioaddr + 0x68) | 0x600, ioaddr + 0x68); 2148 outw(0x0209, ioaddr + 0x60); 2149 } 2150 2151 /* restore.. */ 2152 outw(save_ringbus_a, ioaddr + 0x36); 2153 2154 /* Turn on the 978 docking chip. 2155 First frob the "master output enable" bit, 2156 then set most of the playback volume control registers to max. */ 2157 outb(inb(ioaddr+0xc0)|(1<<5), ioaddr+0xc0); 2158 outb(0xff, ioaddr+0xc3); 2159 outb(0xff, ioaddr+0xc4); 2160 outb(0xff, ioaddr+0xc6); 2161 outb(0xff, ioaddr+0xc8); 2162 outb(0x3f, ioaddr+0xcf); 2163 outb(0x3f, ioaddr+0xd0); 2164 } 2165 2166 static void snd_es1968_reset(es1968_t *chip) 2167 { 2168 /* Reset */ 2169 outw(ESM_RESET_MAESTRO | ESM_RESET_DIRECTSOUND, 2170 chip->io_port + ESM_PORT_HOST_IRQ); 2171 udelay(10); 2172 outw(0x0000, chip->io_port + ESM_PORT_HOST_IRQ); 2173 udelay(10); 2174 } 2175 2176 /* 2177 * power management 2178 */ 2179 static void snd_es1968_set_acpi(es1968_t *chip, int state) 2180 { 2181 u16 active_mask = acpi_state_mask[state]; 2182 2183 pci_set_power_state(chip->pci, state); 2184 /* make sure the units we care about are on 2185 XXX we might want to do this before state flipping? */ 2186 pci_write_config_word(chip->pci, 0x54, ~ active_mask); 2187 pci_write_config_word(chip->pci, 0x56, ~ active_mask); 2188 } 2189 2190 2191 /* 2192 * initialize maestro chip 2193 */ 2194 static void snd_es1968_chip_init(es1968_t *chip) 2195 { 2196 struct pci_dev *pci = chip->pci; 2197 int i; 2198 unsigned long iobase = chip->io_port; 2199 u16 w; 2200 u32 n; 2201 2202 /* We used to muck around with pci config space that 2203 * we had no business messing with. We don't know enough 2204 * about the machine to know which DMA mode is appropriate, 2205 * etc. We were guessing wrong on some machines and making 2206 * them unhappy. We now trust in the BIOS to do things right, 2207 * which almost certainly means a new host of problems will 2208 * arise with broken BIOS implementations. screw 'em. 2209 * We're already intolerant of machines that don't assign 2210 * IRQs. 2211 */ 2212 2213 /* do config work at full power */ 2214 snd_es1968_set_acpi(chip, ACPI_D0); 2215 2216 /* Config Reg A */ 2217 pci_read_config_word(pci, ESM_CONFIG_A, &w); 2218 2219 /* Use TDMA for now. TDMA works on all boards, so while its 2220 * not the most efficient its the simplest. */ 2221 w &= ~DMA_CLEAR; /* Clear DMA bits */ 2222 w |= DMA_TDMA; /* TDMA on */ 2223 w &= ~(PIC_SNOOP1 | PIC_SNOOP2); /* Clear Pic Snoop Mode Bits */ 2224 w &= ~SAFEGUARD; /* Safeguard off */ 2225 w |= POST_WRITE; /* Posted write */ 2226 w |= ISA_TIMING; /* ISA timing on */ 2227 /* XXX huh? claims to be reserved.. */ 2228 w &= ~SWAP_LR; /* swap left/right 2229 seems to only have effect on SB 2230 Emulation */ 2231 w &= ~SUBTR_DECODE; /* Subtractive decode off */ 2232 2233 pci_write_config_word(pci, ESM_CONFIG_A, w); 2234 2235 /* Config Reg B */ 2236 2237 pci_read_config_word(pci, ESM_CONFIG_B, &w); 2238 2239 w &= ~(1 << 15); /* Turn off internal clock multiplier */ 2240 /* XXX how do we know which to use? */ 2241 w &= ~(1 << 14); /* External clock */ 2242 2243 w &= ~SPDIF_CONFB; /* disable S/PDIF output */ 2244 w |= HWV_CONFB; /* HWV on */ 2245 w |= DEBOUNCE; /* Debounce off: easier to push the HW buttons */ 2246 w &= ~GPIO_CONFB; /* GPIO 4:5 */ 2247 w |= CHI_CONFB; /* Disconnect from the CHI. Enabling this made a dell 7500 work. */ 2248 w &= ~IDMA_CONFB; /* IDMA off (undocumented) */ 2249 w &= ~MIDI_FIX; /* MIDI fix off (undoc) */ 2250 w &= ~(1 << 1); /* reserved, always write 0 */ 2251 w &= ~IRQ_TO_ISA; /* IRQ to ISA off (undoc) */ 2252 2253 pci_write_config_word(pci, ESM_CONFIG_B, w); 2254 2255 /* DDMA off */ 2256 2257 pci_read_config_word(pci, ESM_DDMA, &w); 2258 w &= ~(1 << 0); 2259 pci_write_config_word(pci, ESM_DDMA, w); 2260 2261 /* 2262 * Legacy mode 2263 */ 2264 2265 pci_read_config_word(pci, ESM_LEGACY_AUDIO_CONTROL, &w); 2266 2267 w &= ~ESS_ENABLE_AUDIO; /* Disable Legacy Audio */ 2268 w &= ~ESS_ENABLE_SERIAL_IRQ; /* Disable SIRQ */ 2269 w &= ~(0x1f); /* disable mpu irq/io, game port, fm, SB */ 2270 2271 pci_write_config_word(pci, ESM_LEGACY_AUDIO_CONTROL, w); 2272 2273 /* Set up 978 docking control chip. */ 2274 pci_read_config_word(pci, 0x58, &w); 2275 w|=1<<2; /* Enable 978. */ 2276 w|=1<<3; /* Turn on 978 hardware volume control. */ 2277 w&=~(1<<11); /* Turn on 978 mixer volume control. */ 2278 pci_write_config_word(pci, 0x58, w); 2279 2280 /* Sound Reset */ 2281 2282 snd_es1968_reset(chip); 2283 2284 /* 2285 * Ring Bus Setup 2286 */ 2287 2288 /* setup usual 0x34 stuff.. 0x36 may be chip specific */ 2289 outw(0xC090, iobase + ESM_RING_BUS_DEST); /* direct sound, stereo */ 2290 udelay(20); 2291 outw(0x3000, iobase + ESM_RING_BUS_CONTR_A); /* enable ringbus/serial */ 2292 udelay(20); 2293 2294 /* 2295 * Reset the CODEC 2296 */ 2297 2298 snd_es1968_ac97_reset(chip); 2299 2300 /* Ring Bus Control B */ 2301 2302 n = inl(iobase + ESM_RING_BUS_CONTR_B); 2303 n &= ~RINGB_EN_SPDIF; /* SPDIF off */ 2304 //w |= RINGB_EN_2CODEC; /* enable 2nd codec */ 2305 outl(n, iobase + ESM_RING_BUS_CONTR_B); 2306 2307 /* Set hardware volume control registers to midpoints. 2308 We can tell which button was pushed based on how they change. */ 2309 outb(0x88, iobase+0x1c); 2310 outb(0x88, iobase+0x1d); 2311 outb(0x88, iobase+0x1e); 2312 outb(0x88, iobase+0x1f); 2313 2314 /* it appears some maestros (dell 7500) only work if these are set, 2315 regardless of wether we use the assp or not. */ 2316 2317 outb(0, iobase + ASSP_CONTROL_B); 2318 outb(3, iobase + ASSP_CONTROL_A); /* M: Reserved bits... */ 2319 outb(0, iobase + ASSP_CONTROL_C); /* M: Disable ASSP, ASSP IRQ's and FM Port */ 2320 2321 /* 2322 * set up wavecache 2323 */ 2324 for (i = 0; i < 16; i++) { 2325 /* Write 0 into the buffer area 0x1E0->1EF */ 2326 outw(0x01E0 + i, iobase + WC_INDEX); 2327 outw(0x0000, iobase + WC_DATA); 2328 2329 /* The 1.10 test program seem to write 0 into the buffer area 2330 * 0x1D0-0x1DF too.*/ 2331 outw(0x01D0 + i, iobase + WC_INDEX); 2332 outw(0x0000, iobase + WC_DATA); 2333 } 2334 wave_set_register(chip, IDR7_WAVE_ROMRAM, 2335 (wave_get_register(chip, IDR7_WAVE_ROMRAM) & 0xFF00)); 2336 wave_set_register(chip, IDR7_WAVE_ROMRAM, 2337 wave_get_register(chip, IDR7_WAVE_ROMRAM) | 0x100); 2338 wave_set_register(chip, IDR7_WAVE_ROMRAM, 2339 wave_get_register(chip, IDR7_WAVE_ROMRAM) & ~0x200); 2340 wave_set_register(chip, IDR7_WAVE_ROMRAM, 2341 wave_get_register(chip, IDR7_WAVE_ROMRAM) | ~0x400); 2342 2343 2344 maestro_write(chip, IDR2_CRAM_DATA, 0x0000); 2345 /* Now back to the DirectSound stuff */ 2346 /* audio serial configuration.. ? */ 2347 maestro_write(chip, 0x08, 0xB004); 2348 maestro_write(chip, 0x09, 0x001B); 2349 maestro_write(chip, 0x0A, 0x8000); 2350 maestro_write(chip, 0x0B, 0x3F37); 2351 maestro_write(chip, 0x0C, 0x0098); 2352 2353 /* parallel in, has something to do with recording :) */ 2354 maestro_write(chip, 0x0C, 2355 (maestro_read(chip, 0x0C) & ~0xF000) | 0x8000); 2356 /* parallel out */ 2357 maestro_write(chip, 0x0C, 2358 (maestro_read(chip, 0x0C) & ~0x0F00) | 0x0500); 2359 2360 maestro_write(chip, 0x0D, 0x7632); 2361 2362 /* Wave cache control on - test off, sg off, 2363 enable, enable extra chans 1Mb */ 2364 2365 w = inw(iobase + WC_CONTROL); 2366 2367 w &= ~0xFA00; /* Seems to be reserved? I don't know */ 2368 w |= 0xA000; /* reserved... I don't know */ 2369 w &= ~0x0200; /* Channels 56,57,58,59 as Extra Play,Rec Channel enable 2370 Seems to crash the Computer if enabled... */ 2371 w |= 0x0100; /* Wave Cache Operation Enabled */ 2372 w |= 0x0080; /* Channels 60/61 as Placback/Record enabled */ 2373 w &= ~0x0060; /* Clear Wavtable Size */ 2374 w |= 0x0020; /* Wavetable Size : 1MB */ 2375 /* Bit 4 is reserved */ 2376 w &= ~0x000C; /* DMA Stuff? I don't understand what the datasheet means */ 2377 /* Bit 1 is reserved */ 2378 w &= ~0x0001; /* Test Mode off */ 2379 2380 outw(w, iobase + WC_CONTROL); 2381 2382 /* Now clear the APU control ram */ 2383 for (i = 0; i < NR_APUS; i++) { 2384 for (w = 0; w < NR_APU_REGS; w++) 2385 apu_set_register(chip, i, w, 0); 2386 2387 } 2388 } 2389 2390 /* Enable IRQ's */ 2391 static void snd_es1968_start_irq(es1968_t *chip) 2392 { 2393 unsigned short w; 2394 w = ESM_HIRQ_DSIE | ESM_HIRQ_HW_VOLUME; 2395 if (chip->rmidi) 2396 w |= ESM_HIRQ_MPU401; 2397 outw(w, chip->io_port + ESM_PORT_HOST_IRQ); 2398 } 2399 2400 #ifdef CONFIG_PM 2401 /* 2402 * PM support 2403 */ 2404 static int es1968_suspend(snd_card_t *card, pm_message_t state) 2405 { 2406 es1968_t *chip = card->pm_private_data; 2407 2408 if (! chip->do_pm) 2409 return 0; 2410 2411 chip->in_suspend = 1; 2412 snd_pcm_suspend_all(chip->pcm); 2413 snd_ac97_suspend(chip->ac97); 2414 snd_es1968_bob_stop(chip); 2415 snd_es1968_set_acpi(chip, ACPI_D3); 2416 pci_disable_device(chip->pci); 2417 return 0; 2418 } 2419 2420 static int es1968_resume(snd_card_t *card) 2421 { 2422 es1968_t *chip = card->pm_private_data; 2423 struct list_head *p; 2424 2425 if (! chip->do_pm) 2426 return 0; 2427 2428 /* restore all our config */ 2429 pci_enable_device(chip->pci); 2430 pci_set_master(chip->pci); 2431 snd_es1968_chip_init(chip); 2432 2433 /* need to restore the base pointers.. */ 2434 if (chip->dma.addr) { 2435 /* set PCMBAR */ 2436 wave_set_register(chip, 0x01FC, chip->dma.addr >> 12); 2437 } 2438 2439 snd_es1968_start_irq(chip); 2440 2441 /* restore ac97 state */ 2442 snd_ac97_resume(chip->ac97); 2443 2444 list_for_each(p, &chip->substream_list) { 2445 esschan_t *es = list_entry(p, esschan_t, list); 2446 switch (es->mode) { 2447 case ESM_MODE_PLAY: 2448 snd_es1968_playback_setup(chip, es, es->substream->runtime); 2449 break; 2450 case ESM_MODE_CAPTURE: 2451 snd_es1968_capture_setup(chip, es, es->substream->runtime); 2452 break; 2453 } 2454 } 2455 2456 /* start timer again */ 2457 if (chip->bobclient) 2458 snd_es1968_bob_start(chip); 2459 2460 chip->in_suspend = 0; 2461 return 0; 2462 } 2463 #endif /* CONFIG_PM */ 2464 2465 #ifdef SUPPORT_JOYSTICK 2466 #define JOYSTICK_ADDR 0x200 2467 static int __devinit snd_es1968_create_gameport(es1968_t *chip, int dev) 2468 { 2469 struct gameport *gp; 2470 struct resource *r; 2471 u16 val; 2472 2473 if (!joystick[dev]) 2474 return -ENODEV; 2475 2476 r = request_region(JOYSTICK_ADDR, 8, "ES1968 gameport"); 2477 if (!r) 2478 return -EBUSY; 2479 2480 chip->gameport = gp = gameport_allocate_port(); 2481 if (!gp) { 2482 printk(KERN_ERR "es1968: cannot allocate memory for gameport\n"); 2483 release_resource(r); 2484 kfree_nocheck(r); 2485 return -ENOMEM; 2486 } 2487 2488 pci_read_config_word(chip->pci, ESM_LEGACY_AUDIO_CONTROL, &val); 2489 pci_write_config_word(chip->pci, ESM_LEGACY_AUDIO_CONTROL, val | 0x04); 2490 2491 gameport_set_name(gp, "ES1968 Gameport"); 2492 gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci)); 2493 gameport_set_dev_parent(gp, &chip->pci->dev); 2494 gp->io = JOYSTICK_ADDR; 2495 gameport_set_port_data(gp, r); 2496 2497 gameport_register_port(gp); 2498 2499 return 0; 2500 } 2501 2502 static void snd_es1968_free_gameport(es1968_t *chip) 2503 { 2504 if (chip->gameport) { 2505 struct resource *r = gameport_get_port_data(chip->gameport); 2506 2507 gameport_unregister_port(chip->gameport); 2508 chip->gameport = NULL; 2509 2510 release_resource(r); 2511 kfree_nocheck(r); 2512 } 2513 } 2514 #else 2515 static inline int snd_es1968_create_gameport(es1968_t *chip, int dev) { return -ENOSYS; } 2516 static inline void snd_es1968_free_gameport(es1968_t *chip) { } 2517 #endif 2518 2519 static int snd_es1968_free(es1968_t *chip) 2520 { 2521 if (chip->io_port) { 2522 synchronize_irq(chip->irq); 2523 outw(1, chip->io_port + 0x04); /* clear WP interrupts */ 2524 outw(0, chip->io_port + ESM_PORT_HOST_IRQ); /* disable IRQ */ 2525 } 2526 2527 if (chip->irq >= 0) 2528 free_irq(chip->irq, (void *)chip); 2529 snd_es1968_free_gameport(chip); 2530 snd_es1968_set_acpi(chip, ACPI_D3); 2531 chip->master_switch = NULL; 2532 chip->master_volume = NULL; 2533 pci_release_regions(chip->pci); 2534 pci_disable_device(chip->pci); 2535 kfree(chip); 2536 return 0; 2537 } 2538 2539 static int snd_es1968_dev_free(snd_device_t *device) 2540 { 2541 es1968_t *chip = device->device_data; 2542 return snd_es1968_free(chip); 2543 } 2544 2545 struct ess_device_list { 2546 unsigned short type; /* chip type */ 2547 unsigned short vendor; /* subsystem vendor id */ 2548 }; 2549 2550 static struct ess_device_list pm_whitelist[] __devinitdata = { 2551 { TYPE_MAESTRO2E, 0x0e11 }, /* Compaq Armada */ 2552 { TYPE_MAESTRO2E, 0x1028 }, 2553 { TYPE_MAESTRO2E, 0x103c }, 2554 { TYPE_MAESTRO2E, 0x1179 }, 2555 { TYPE_MAESTRO2E, 0x14c0 }, /* HP omnibook 4150 */ 2556 { TYPE_MAESTRO2E, 0x1558 }, 2557 }; 2558 2559 static struct ess_device_list mpu_blacklist[] __devinitdata = { 2560 { TYPE_MAESTRO2, 0x125d }, 2561 }; 2562 2563 static int __devinit snd_es1968_create(snd_card_t * card, 2564 struct pci_dev *pci, 2565 int total_bufsize, 2566 int play_streams, 2567 int capt_streams, 2568 int chip_type, 2569 int do_pm, 2570 es1968_t **chip_ret) 2571 { 2572 static snd_device_ops_t ops = { 2573 .dev_free = snd_es1968_dev_free, 2574 }; 2575 es1968_t *chip; 2576 int i, err; 2577 2578 *chip_ret = NULL; 2579 2580 /* enable PCI device */ 2581 if ((err = pci_enable_device(pci)) < 0) 2582 return err; 2583 /* check, if we can restrict PCI DMA transfers to 28 bits */ 2584 if (pci_set_dma_mask(pci, 0x0fffffff) < 0 || 2585 pci_set_consistent_dma_mask(pci, 0x0fffffff) < 0) { 2586 snd_printk("architecture does not support 28bit PCI busmaster DMA\n"); 2587 pci_disable_device(pci); 2588 return -ENXIO; 2589 } 2590 2591 chip = kcalloc(1, sizeof(*chip), GFP_KERNEL); 2592 if (! chip) { 2593 pci_disable_device(pci); 2594 return -ENOMEM; 2595 } 2596 2597 /* Set Vars */ 2598 chip->type = chip_type; 2599 spin_lock_init(&chip->reg_lock); 2600 spin_lock_init(&chip->substream_lock); 2601 INIT_LIST_HEAD(&chip->buf_list); 2602 INIT_LIST_HEAD(&chip->substream_list); 2603 spin_lock_init(&chip->ac97_lock); 2604 init_MUTEX(&chip->memory_mutex); 2605 tasklet_init(&chip->hwvol_tq, es1968_update_hw_volume, (unsigned long)chip); 2606 chip->card = card; 2607 chip->pci = pci; 2608 chip->irq = -1; 2609 chip->total_bufsize = total_bufsize; /* in bytes */ 2610 chip->playback_streams = play_streams; 2611 chip->capture_streams = capt_streams; 2612 2613 if ((err = pci_request_regions(pci, "ESS Maestro")) < 0) { 2614 kfree(chip); 2615 pci_disable_device(pci); 2616 return err; 2617 } 2618 chip->io_port = pci_resource_start(pci, 0); 2619 if (request_irq(pci->irq, snd_es1968_interrupt, SA_INTERRUPT|SA_SHIRQ, 2620 "ESS Maestro", (void*)chip)) { 2621 snd_printk("unable to grab IRQ %d\n", pci->irq); 2622 snd_es1968_free(chip); 2623 return -EBUSY; 2624 } 2625 chip->irq = pci->irq; 2626 2627 /* Clear Maestro_map */ 2628 for (i = 0; i < 32; i++) 2629 chip->maestro_map[i] = 0; 2630 2631 /* Clear Apu Map */ 2632 for (i = 0; i < NR_APUS; i++) 2633 chip->apu[i] = ESM_APU_FREE; 2634 2635 /* just to be sure */ 2636 pci_set_master(pci); 2637 2638 if (do_pm > 1) { 2639 /* disable power-management if not on the whitelist */ 2640 unsigned short vend; 2641 pci_read_config_word(chip->pci, PCI_SUBSYSTEM_VENDOR_ID, &vend); 2642 for (i = 0; i < (int)ARRAY_SIZE(pm_whitelist); i++) { 2643 if (chip->type == pm_whitelist[i].type && 2644 vend == pm_whitelist[i].vendor) { 2645 do_pm = 1; 2646 break; 2647 } 2648 } 2649 if (do_pm > 1) { 2650 /* not matched; disabling pm */ 2651 printk(KERN_INFO "es1968: not attempting power management.\n"); 2652 do_pm = 0; 2653 } 2654 } 2655 chip->do_pm = do_pm; 2656 2657 snd_es1968_chip_init(chip); 2658 2659 if (chip->do_pm) 2660 snd_card_set_pm_callback(card, es1968_suspend, es1968_resume, chip); 2661 2662 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) { 2663 snd_es1968_free(chip); 2664 return err; 2665 } 2666 2667 snd_card_set_dev(card, &pci->dev); 2668 2669 *chip_ret = chip; 2670 2671 return 0; 2672 } 2673 2674 2675 /* 2676 */ 2677 static int __devinit snd_es1968_probe(struct pci_dev *pci, 2678 const struct pci_device_id *pci_id) 2679 { 2680 static int dev; 2681 snd_card_t *card; 2682 es1968_t *chip; 2683 unsigned int i; 2684 int err; 2685 2686 if (dev >= SNDRV_CARDS) 2687 return -ENODEV; 2688 if (!enable[dev]) { 2689 dev++; 2690 return -ENOENT; 2691 } 2692 2693 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0); 2694 if (!card) 2695 return -ENOMEM; 2696 2697 if (total_bufsize[dev] < 128) 2698 total_bufsize[dev] = 128; 2699 if (total_bufsize[dev] > 4096) 2700 total_bufsize[dev] = 4096; 2701 if ((err = snd_es1968_create(card, pci, 2702 total_bufsize[dev] * 1024, /* in bytes */ 2703 pcm_substreams_p[dev], 2704 pcm_substreams_c[dev], 2705 pci_id->driver_data, 2706 use_pm[dev], 2707 &chip)) < 0) { 2708 snd_card_free(card); 2709 return err; 2710 } 2711 2712 switch (chip->type) { 2713 case TYPE_MAESTRO2E: 2714 strcpy(card->driver, "ES1978"); 2715 strcpy(card->shortname, "ESS ES1978 (Maestro 2E)"); 2716 break; 2717 case TYPE_MAESTRO2: 2718 strcpy(card->driver, "ES1968"); 2719 strcpy(card->shortname, "ESS ES1968 (Maestro 2)"); 2720 break; 2721 case TYPE_MAESTRO: 2722 strcpy(card->driver, "ESM1"); 2723 strcpy(card->shortname, "ESS Maestro 1"); 2724 break; 2725 } 2726 2727 if ((err = snd_es1968_pcm(chip, 0)) < 0) { 2728 snd_card_free(card); 2729 return err; 2730 } 2731 2732 if ((err = snd_es1968_mixer(chip)) < 0) { 2733 snd_card_free(card); 2734 return err; 2735 } 2736 2737 if (enable_mpu[dev] == 2) { 2738 /* check the black list */ 2739 unsigned short vend; 2740 pci_read_config_word(chip->pci, PCI_SUBSYSTEM_VENDOR_ID, &vend); 2741 for (i = 0; i < ARRAY_SIZE(mpu_blacklist); i++) { 2742 if (chip->type == mpu_blacklist[i].type && 2743 vend == mpu_blacklist[i].vendor) { 2744 enable_mpu[dev] = 0; 2745 break; 2746 } 2747 } 2748 } 2749 if (enable_mpu[dev]) { 2750 if ((err = snd_mpu401_uart_new(card, 0, MPU401_HW_MPU401, 2751 chip->io_port + ESM_MPU401_PORT, 1, 2752 chip->irq, 0, &chip->rmidi)) < 0) { 2753 printk(KERN_WARNING "es1968: skipping MPU-401 MIDI support..\n"); 2754 } 2755 } 2756 2757 snd_es1968_create_gameport(chip, dev); 2758 2759 snd_es1968_start_irq(chip); 2760 2761 chip->clock = clock[dev]; 2762 if (! chip->clock) 2763 es1968_measure_clock(chip); 2764 2765 sprintf(card->longname, "%s at 0x%lx, irq %i", 2766 card->shortname, chip->io_port, chip->irq); 2767 2768 if ((err = snd_card_register(card)) < 0) { 2769 snd_card_free(card); 2770 return err; 2771 } 2772 pci_set_drvdata(pci, card); 2773 dev++; 2774 return 0; 2775 } 2776 2777 static void __devexit snd_es1968_remove(struct pci_dev *pci) 2778 { 2779 snd_card_free(pci_get_drvdata(pci)); 2780 pci_set_drvdata(pci, NULL); 2781 } 2782 2783 static struct pci_driver driver = { 2784 .name = "ES1968 (ESS Maestro)", 2785 .id_table = snd_es1968_ids, 2786 .probe = snd_es1968_probe, 2787 .remove = __devexit_p(snd_es1968_remove), 2788 SND_PCI_PM_CALLBACKS 2789 }; 2790 2791 static int __init alsa_card_es1968_init(void) 2792 { 2793 return pci_register_driver(&driver); 2794 } 2795 2796 static void __exit alsa_card_es1968_exit(void) 2797 { 2798 pci_unregister_driver(&driver); 2799 } 2800 2801 module_init(alsa_card_es1968_init) 2802 module_exit(alsa_card_es1968_exit) 2803