1 /* 2 * Driver for Ensoniq ES1370/ES1371 AudioPCI soundcard 3 * Copyright (c) by Jaroslav Kysela <perex@suse.cz>, 4 * Thomas Sailer <sailer@ife.ee.ethz.ch> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 19 * 20 */ 21 22 /* Power-Management-Code ( CONFIG_PM ) 23 * for ens1371 only ( FIXME ) 24 * derived from cs4281.c, atiixp.c and via82xx.c 25 * using http://www.alsa-project.org/~iwai/writing-an-alsa-driver/c1540.htm 26 * by Kurt J. Bosch 27 */ 28 29 #include <sound/driver.h> 30 #include <asm/io.h> 31 #include <linux/delay.h> 32 #include <linux/interrupt.h> 33 #include <linux/init.h> 34 #include <linux/pci.h> 35 #include <linux/slab.h> 36 #include <linux/gameport.h> 37 #include <linux/moduleparam.h> 38 #include <linux/mutex.h> 39 40 #include <sound/core.h> 41 #include <sound/control.h> 42 #include <sound/pcm.h> 43 #include <sound/rawmidi.h> 44 #ifdef CHIP1371 45 #include <sound/ac97_codec.h> 46 #else 47 #include <sound/ak4531_codec.h> 48 #endif 49 #include <sound/initval.h> 50 #include <sound/asoundef.h> 51 52 #ifndef CHIP1371 53 #undef CHIP1370 54 #define CHIP1370 55 #endif 56 57 #ifdef CHIP1370 58 #define DRIVER_NAME "ENS1370" 59 #else 60 #define DRIVER_NAME "ENS1371" 61 #endif 62 63 64 MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>, Thomas Sailer <sailer@ife.ee.ethz.ch>"); 65 MODULE_LICENSE("GPL"); 66 #ifdef CHIP1370 67 MODULE_DESCRIPTION("Ensoniq AudioPCI ES1370"); 68 MODULE_SUPPORTED_DEVICE("{{Ensoniq,AudioPCI-97 ES1370}," 69 "{Creative Labs,SB PCI64/128 (ES1370)}}"); 70 #endif 71 #ifdef CHIP1371 72 MODULE_DESCRIPTION("Ensoniq/Creative AudioPCI ES1371+"); 73 MODULE_SUPPORTED_DEVICE("{{Ensoniq,AudioPCI ES1371/73}," 74 "{Ensoniq,AudioPCI ES1373}," 75 "{Creative Labs,Ectiva EV1938}," 76 "{Creative Labs,SB PCI64/128 (ES1371/73)}," 77 "{Creative Labs,Vibra PCI128}," 78 "{Ectiva,EV1938}}"); 79 #endif 80 81 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE)) 82 #define SUPPORT_JOYSTICK 83 #endif 84 85 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ 86 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ 87 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable switches */ 88 #ifdef SUPPORT_JOYSTICK 89 #ifdef CHIP1371 90 static int joystick_port[SNDRV_CARDS]; 91 #else 92 static int joystick[SNDRV_CARDS]; 93 #endif 94 #endif 95 #ifdef CHIP1371 96 static int spdif[SNDRV_CARDS]; 97 static int lineio[SNDRV_CARDS]; 98 #endif 99 100 module_param_array(index, int, NULL, 0444); 101 MODULE_PARM_DESC(index, "Index value for Ensoniq AudioPCI soundcard."); 102 module_param_array(id, charp, NULL, 0444); 103 MODULE_PARM_DESC(id, "ID string for Ensoniq AudioPCI soundcard."); 104 module_param_array(enable, bool, NULL, 0444); 105 MODULE_PARM_DESC(enable, "Enable Ensoniq AudioPCI soundcard."); 106 #ifdef SUPPORT_JOYSTICK 107 #ifdef CHIP1371 108 module_param_array(joystick_port, int, NULL, 0444); 109 MODULE_PARM_DESC(joystick_port, "Joystick port address."); 110 #else 111 module_param_array(joystick, bool, NULL, 0444); 112 MODULE_PARM_DESC(joystick, "Enable joystick."); 113 #endif 114 #endif /* SUPPORT_JOYSTICK */ 115 #ifdef CHIP1371 116 module_param_array(spdif, int, NULL, 0444); 117 MODULE_PARM_DESC(spdif, "S/PDIF output (-1 = none, 0 = auto, 1 = force)."); 118 module_param_array(lineio, int, NULL, 0444); 119 MODULE_PARM_DESC(lineio, "Line In to Rear Out (0 = auto, 1 = force)."); 120 #endif 121 122 /* ES1371 chip ID */ 123 /* This is a little confusing because all ES1371 compatible chips have the 124 same DEVICE_ID, the only thing differentiating them is the REV_ID field. 125 This is only significant if you want to enable features on the later parts. 126 Yes, I know it's stupid and why didn't we use the sub IDs? 127 */ 128 #define ES1371REV_ES1373_A 0x04 129 #define ES1371REV_ES1373_B 0x06 130 #define ES1371REV_CT5880_A 0x07 131 #define CT5880REV_CT5880_C 0x02 132 #define CT5880REV_CT5880_D 0x03 /* ??? -jk */ 133 #define CT5880REV_CT5880_E 0x04 /* mw */ 134 #define ES1371REV_ES1371_B 0x09 135 #define EV1938REV_EV1938_A 0x00 136 #define ES1371REV_ES1373_8 0x08 137 138 /* 139 * Direct registers 140 */ 141 142 #define ES_REG(ensoniq, x) ((ensoniq)->port + ES_REG_##x) 143 144 #define ES_REG_CONTROL 0x00 /* R/W: Interrupt/Chip select control register */ 145 #define ES_1370_ADC_STOP (1<<31) /* disable capture buffer transfers */ 146 #define ES_1370_XCTL1 (1<<30) /* general purpose output bit */ 147 #define ES_1373_BYPASS_P1 (1<<31) /* bypass SRC for PB1 */ 148 #define ES_1373_BYPASS_P2 (1<<30) /* bypass SRC for PB2 */ 149 #define ES_1373_BYPASS_R (1<<29) /* bypass SRC for REC */ 150 #define ES_1373_TEST_BIT (1<<28) /* should be set to 0 for normal operation */ 151 #define ES_1373_RECEN_B (1<<27) /* mix record with playback for I2S/SPDIF out */ 152 #define ES_1373_SPDIF_THRU (1<<26) /* 0 = SPDIF thru mode, 1 = SPDIF == dig out */ 153 #define ES_1371_JOY_ASEL(o) (((o)&0x03)<<24)/* joystick port mapping */ 154 #define ES_1371_JOY_ASELM (0x03<<24) /* mask for above */ 155 #define ES_1371_JOY_ASELI(i) (((i)>>24)&0x03) 156 #define ES_1371_GPIO_IN(i) (((i)>>20)&0x0f)/* GPIO in [3:0] pins - R/O */ 157 #define ES_1370_PCLKDIVO(o) (((o)&0x1fff)<<16)/* clock divide ratio for DAC2 */ 158 #define ES_1370_PCLKDIVM ((0x1fff)<<16) /* mask for above */ 159 #define ES_1370_PCLKDIVI(i) (((i)>>16)&0x1fff)/* clock divide ratio for DAC2 */ 160 #define ES_1371_GPIO_OUT(o) (((o)&0x0f)<<16)/* GPIO out [3:0] pins - W/R */ 161 #define ES_1371_GPIO_OUTM (0x0f<<16) /* mask for above */ 162 #define ES_MSFMTSEL (1<<15) /* MPEG serial data format; 0 = SONY, 1 = I2S */ 163 #define ES_1370_M_SBB (1<<14) /* clock source for DAC - 0 = clock generator; 1 = MPEG clocks */ 164 #define ES_1371_SYNC_RES (1<<14) /* Warm AC97 reset */ 165 #define ES_1370_WTSRSEL(o) (((o)&0x03)<<12)/* fixed frequency clock for DAC1 */ 166 #define ES_1370_WTSRSELM (0x03<<12) /* mask for above */ 167 #define ES_1371_ADC_STOP (1<<13) /* disable CCB transfer capture information */ 168 #define ES_1371_PWR_INTRM (1<<12) /* power level change interrupts enable */ 169 #define ES_1370_DAC_SYNC (1<<11) /* DAC's are synchronous */ 170 #define ES_1371_M_CB (1<<11) /* capture clock source; 0 = AC'97 ADC; 1 = I2S */ 171 #define ES_CCB_INTRM (1<<10) /* CCB voice interrupts enable */ 172 #define ES_1370_M_CB (1<<9) /* capture clock source; 0 = ADC; 1 = MPEG */ 173 #define ES_1370_XCTL0 (1<<8) /* generap purpose output bit */ 174 #define ES_1371_PDLEV(o) (((o)&0x03)<<8) /* current power down level */ 175 #define ES_1371_PDLEVM (0x03<<8) /* mask for above */ 176 #define ES_BREQ (1<<7) /* memory bus request enable */ 177 #define ES_DAC1_EN (1<<6) /* DAC1 playback channel enable */ 178 #define ES_DAC2_EN (1<<5) /* DAC2 playback channel enable */ 179 #define ES_ADC_EN (1<<4) /* ADC capture channel enable */ 180 #define ES_UART_EN (1<<3) /* UART enable */ 181 #define ES_JYSTK_EN (1<<2) /* Joystick module enable */ 182 #define ES_1370_CDC_EN (1<<1) /* Codec interface enable */ 183 #define ES_1371_XTALCKDIS (1<<1) /* Xtal clock disable */ 184 #define ES_1370_SERR_DISABLE (1<<0) /* PCI serr signal disable */ 185 #define ES_1371_PCICLKDIS (1<<0) /* PCI clock disable */ 186 #define ES_REG_STATUS 0x04 /* R/O: Interrupt/Chip select status register */ 187 #define ES_INTR (1<<31) /* Interrupt is pending */ 188 #define ES_1371_ST_AC97_RST (1<<29) /* CT5880 AC'97 Reset bit */ 189 #define ES_1373_REAR_BIT27 (1<<27) /* rear bits: 000 - front, 010 - mirror, 101 - separate */ 190 #define ES_1373_REAR_BIT26 (1<<26) 191 #define ES_1373_REAR_BIT24 (1<<24) 192 #define ES_1373_GPIO_INT_EN(o)(((o)&0x0f)<<20)/* GPIO [3:0] pins - interrupt enable */ 193 #define ES_1373_SPDIF_EN (1<<18) /* SPDIF enable */ 194 #define ES_1373_SPDIF_TEST (1<<17) /* SPDIF test */ 195 #define ES_1371_TEST (1<<16) /* test ASIC */ 196 #define ES_1373_GPIO_INT(i) (((i)&0x0f)>>12)/* GPIO [3:0] pins - interrupt pending */ 197 #define ES_1370_CSTAT (1<<10) /* CODEC is busy or register write in progress */ 198 #define ES_1370_CBUSY (1<<9) /* CODEC is busy */ 199 #define ES_1370_CWRIP (1<<8) /* CODEC register write in progress */ 200 #define ES_1371_SYNC_ERR (1<<8) /* CODEC synchronization error occurred */ 201 #define ES_1371_VC(i) (((i)>>6)&0x03) /* voice code from CCB module */ 202 #define ES_1370_VC(i) (((i)>>5)&0x03) /* voice code from CCB module */ 203 #define ES_1371_MPWR (1<<5) /* power level interrupt pending */ 204 #define ES_MCCB (1<<4) /* CCB interrupt pending */ 205 #define ES_UART (1<<3) /* UART interrupt pending */ 206 #define ES_DAC1 (1<<2) /* DAC1 channel interrupt pending */ 207 #define ES_DAC2 (1<<1) /* DAC2 channel interrupt pending */ 208 #define ES_ADC (1<<0) /* ADC channel interrupt pending */ 209 #define ES_REG_UART_DATA 0x08 /* R/W: UART data register */ 210 #define ES_REG_UART_STATUS 0x09 /* R/O: UART status register */ 211 #define ES_RXINT (1<<7) /* RX interrupt occurred */ 212 #define ES_TXINT (1<<2) /* TX interrupt occurred */ 213 #define ES_TXRDY (1<<1) /* transmitter ready */ 214 #define ES_RXRDY (1<<0) /* receiver ready */ 215 #define ES_REG_UART_CONTROL 0x09 /* W/O: UART control register */ 216 #define ES_RXINTEN (1<<7) /* RX interrupt enable */ 217 #define ES_TXINTENO(o) (((o)&0x03)<<5) /* TX interrupt enable */ 218 #define ES_TXINTENM (0x03<<5) /* mask for above */ 219 #define ES_TXINTENI(i) (((i)>>5)&0x03) 220 #define ES_CNTRL(o) (((o)&0x03)<<0) /* control */ 221 #define ES_CNTRLM (0x03<<0) /* mask for above */ 222 #define ES_REG_UART_RES 0x0a /* R/W: UART reserver register */ 223 #define ES_TEST_MODE (1<<0) /* test mode enabled */ 224 #define ES_REG_MEM_PAGE 0x0c /* R/W: Memory page register */ 225 #define ES_MEM_PAGEO(o) (((o)&0x0f)<<0) /* memory page select - out */ 226 #define ES_MEM_PAGEM (0x0f<<0) /* mask for above */ 227 #define ES_MEM_PAGEI(i) (((i)>>0)&0x0f) /* memory page select - in */ 228 #define ES_REG_1370_CODEC 0x10 /* W/O: Codec write register address */ 229 #define ES_1370_CODEC_WRITE(a,d) ((((a)&0xff)<<8)|(((d)&0xff)<<0)) 230 #define ES_REG_1371_CODEC 0x14 /* W/R: Codec Read/Write register address */ 231 #define ES_1371_CODEC_RDY (1<<31) /* codec ready */ 232 #define ES_1371_CODEC_WIP (1<<30) /* codec register access in progress */ 233 #define ES_1371_CODEC_PIRD (1<<23) /* codec read/write select register */ 234 #define ES_1371_CODEC_WRITE(a,d) ((((a)&0x7f)<<16)|(((d)&0xffff)<<0)) 235 #define ES_1371_CODEC_READS(a) ((((a)&0x7f)<<16)|ES_1371_CODEC_PIRD) 236 #define ES_1371_CODEC_READ(i) (((i)>>0)&0xffff) 237 238 #define ES_REG_1371_SMPRATE 0x10 /* W/R: Codec rate converter interface register */ 239 #define ES_1371_SRC_RAM_ADDRO(o) (((o)&0x7f)<<25)/* address of the sample rate converter */ 240 #define ES_1371_SRC_RAM_ADDRM (0x7f<<25) /* mask for above */ 241 #define ES_1371_SRC_RAM_ADDRI(i) (((i)>>25)&0x7f)/* address of the sample rate converter */ 242 #define ES_1371_SRC_RAM_WE (1<<24) /* R/W: read/write control for sample rate converter */ 243 #define ES_1371_SRC_RAM_BUSY (1<<23) /* R/O: sample rate memory is busy */ 244 #define ES_1371_SRC_DISABLE (1<<22) /* sample rate converter disable */ 245 #define ES_1371_DIS_P1 (1<<21) /* playback channel 1 accumulator update disable */ 246 #define ES_1371_DIS_P2 (1<<20) /* playback channel 1 accumulator update disable */ 247 #define ES_1371_DIS_R1 (1<<19) /* capture channel accumulator update disable */ 248 #define ES_1371_SRC_RAM_DATAO(o) (((o)&0xffff)<<0)/* current value of the sample rate converter */ 249 #define ES_1371_SRC_RAM_DATAM (0xffff<<0) /* mask for above */ 250 #define ES_1371_SRC_RAM_DATAI(i) (((i)>>0)&0xffff)/* current value of the sample rate converter */ 251 252 #define ES_REG_1371_LEGACY 0x18 /* W/R: Legacy control/status register */ 253 #define ES_1371_JFAST (1<<31) /* fast joystick timing */ 254 #define ES_1371_HIB (1<<30) /* host interrupt blocking enable */ 255 #define ES_1371_VSB (1<<29) /* SB; 0 = addr 0x220xH, 1 = 0x22FxH */ 256 #define ES_1371_VMPUO(o) (((o)&0x03)<<27)/* base register address; 0 = 0x320xH; 1 = 0x330xH; 2 = 0x340xH; 3 = 0x350xH */ 257 #define ES_1371_VMPUM (0x03<<27) /* mask for above */ 258 #define ES_1371_VMPUI(i) (((i)>>27)&0x03)/* base register address */ 259 #define ES_1371_VCDCO(o) (((o)&0x03)<<25)/* CODEC; 0 = 0x530xH; 1 = undefined; 2 = 0xe80xH; 3 = 0xF40xH */ 260 #define ES_1371_VCDCM (0x03<<25) /* mask for above */ 261 #define ES_1371_VCDCI(i) (((i)>>25)&0x03)/* CODEC address */ 262 #define ES_1371_FIRQ (1<<24) /* force an interrupt */ 263 #define ES_1371_SDMACAP (1<<23) /* enable event capture for slave DMA controller */ 264 #define ES_1371_SPICAP (1<<22) /* enable event capture for slave IRQ controller */ 265 #define ES_1371_MDMACAP (1<<21) /* enable event capture for master DMA controller */ 266 #define ES_1371_MPICAP (1<<20) /* enable event capture for master IRQ controller */ 267 #define ES_1371_ADCAP (1<<19) /* enable event capture for ADLIB register; 0x388xH */ 268 #define ES_1371_SVCAP (1<<18) /* enable event capture for SB registers */ 269 #define ES_1371_CDCCAP (1<<17) /* enable event capture for CODEC registers */ 270 #define ES_1371_BACAP (1<<16) /* enable event capture for SoundScape base address */ 271 #define ES_1371_EXI(i) (((i)>>8)&0x07) /* event number */ 272 #define ES_1371_AI(i) (((i)>>3)&0x1f) /* event significant I/O address */ 273 #define ES_1371_WR (1<<2) /* event capture; 0 = read; 1 = write */ 274 #define ES_1371_LEGINT (1<<0) /* interrupt for legacy events; 0 = interrupt did occur */ 275 276 #define ES_REG_CHANNEL_STATUS 0x1c /* R/W: first 32-bits from S/PDIF channel status block, es1373 */ 277 278 #define ES_REG_SERIAL 0x20 /* R/W: Serial interface control register */ 279 #define ES_1371_DAC_TEST (1<<22) /* DAC test mode enable */ 280 #define ES_P2_END_INCO(o) (((o)&0x07)<<19)/* binary offset value to increment / loop end */ 281 #define ES_P2_END_INCM (0x07<<19) /* mask for above */ 282 #define ES_P2_END_INCI(i) (((i)>>16)&0x07)/* binary offset value to increment / loop end */ 283 #define ES_P2_ST_INCO(o) (((o)&0x07)<<16)/* binary offset value to increment / start */ 284 #define ES_P2_ST_INCM (0x07<<16) /* mask for above */ 285 #define ES_P2_ST_INCI(i) (((i)<<16)&0x07)/* binary offset value to increment / start */ 286 #define ES_R1_LOOP_SEL (1<<15) /* ADC; 0 - loop mode; 1 = stop mode */ 287 #define ES_P2_LOOP_SEL (1<<14) /* DAC2; 0 - loop mode; 1 = stop mode */ 288 #define ES_P1_LOOP_SEL (1<<13) /* DAC1; 0 - loop mode; 1 = stop mode */ 289 #define ES_P2_PAUSE (1<<12) /* DAC2; 0 - play mode; 1 = pause mode */ 290 #define ES_P1_PAUSE (1<<11) /* DAC1; 0 - play mode; 1 = pause mode */ 291 #define ES_R1_INT_EN (1<<10) /* ADC interrupt enable */ 292 #define ES_P2_INT_EN (1<<9) /* DAC2 interrupt enable */ 293 #define ES_P1_INT_EN (1<<8) /* DAC1 interrupt enable */ 294 #define ES_P1_SCT_RLD (1<<7) /* force sample counter reload for DAC1 */ 295 #define ES_P2_DAC_SEN (1<<6) /* when stop mode: 0 - DAC2 play back zeros; 1 = DAC2 play back last sample */ 296 #define ES_R1_MODEO(o) (((o)&0x03)<<4) /* ADC mode; 0 = 8-bit mono; 1 = 8-bit stereo; 2 = 16-bit mono; 3 = 16-bit stereo */ 297 #define ES_R1_MODEM (0x03<<4) /* mask for above */ 298 #define ES_R1_MODEI(i) (((i)>>4)&0x03) 299 #define ES_P2_MODEO(o) (((o)&0x03)<<2) /* DAC2 mode; -- '' -- */ 300 #define ES_P2_MODEM (0x03<<2) /* mask for above */ 301 #define ES_P2_MODEI(i) (((i)>>2)&0x03) 302 #define ES_P1_MODEO(o) (((o)&0x03)<<0) /* DAC1 mode; -- '' -- */ 303 #define ES_P1_MODEM (0x03<<0) /* mask for above */ 304 #define ES_P1_MODEI(i) (((i)>>0)&0x03) 305 306 #define ES_REG_DAC1_COUNT 0x24 /* R/W: DAC1 sample count register */ 307 #define ES_REG_DAC2_COUNT 0x28 /* R/W: DAC2 sample count register */ 308 #define ES_REG_ADC_COUNT 0x2c /* R/W: ADC sample count register */ 309 #define ES_REG_CURR_COUNT(i) (((i)>>16)&0xffff) 310 #define ES_REG_COUNTO(o) (((o)&0xffff)<<0) 311 #define ES_REG_COUNTM (0xffff<<0) 312 #define ES_REG_COUNTI(i) (((i)>>0)&0xffff) 313 314 #define ES_REG_DAC1_FRAME 0x30 /* R/W: PAGE 0x0c; DAC1 frame address */ 315 #define ES_REG_DAC1_SIZE 0x34 /* R/W: PAGE 0x0c; DAC1 frame size */ 316 #define ES_REG_DAC2_FRAME 0x38 /* R/W: PAGE 0x0c; DAC2 frame address */ 317 #define ES_REG_DAC2_SIZE 0x3c /* R/W: PAGE 0x0c; DAC2 frame size */ 318 #define ES_REG_ADC_FRAME 0x30 /* R/W: PAGE 0x0d; ADC frame address */ 319 #define ES_REG_ADC_SIZE 0x34 /* R/W: PAGE 0x0d; ADC frame size */ 320 #define ES_REG_FCURR_COUNTO(o) (((o)&0xffff)<<16) 321 #define ES_REG_FCURR_COUNTM (0xffff<<16) 322 #define ES_REG_FCURR_COUNTI(i) (((i)>>14)&0x3fffc) 323 #define ES_REG_FSIZEO(o) (((o)&0xffff)<<0) 324 #define ES_REG_FSIZEM (0xffff<<0) 325 #define ES_REG_FSIZEI(i) (((i)>>0)&0xffff) 326 #define ES_REG_PHANTOM_FRAME 0x38 /* R/W: PAGE 0x0d: phantom frame address */ 327 #define ES_REG_PHANTOM_COUNT 0x3c /* R/W: PAGE 0x0d: phantom frame count */ 328 329 #define ES_REG_UART_FIFO 0x30 /* R/W: PAGE 0x0e; UART FIFO register */ 330 #define ES_REG_UF_VALID (1<<8) 331 #define ES_REG_UF_BYTEO(o) (((o)&0xff)<<0) 332 #define ES_REG_UF_BYTEM (0xff<<0) 333 #define ES_REG_UF_BYTEI(i) (((i)>>0)&0xff) 334 335 336 /* 337 * Pages 338 */ 339 340 #define ES_PAGE_DAC 0x0c 341 #define ES_PAGE_ADC 0x0d 342 #define ES_PAGE_UART 0x0e 343 #define ES_PAGE_UART1 0x0f 344 345 /* 346 * Sample rate converter addresses 347 */ 348 349 #define ES_SMPREG_DAC1 0x70 350 #define ES_SMPREG_DAC2 0x74 351 #define ES_SMPREG_ADC 0x78 352 #define ES_SMPREG_VOL_ADC 0x6c 353 #define ES_SMPREG_VOL_DAC1 0x7c 354 #define ES_SMPREG_VOL_DAC2 0x7e 355 #define ES_SMPREG_TRUNC_N 0x00 356 #define ES_SMPREG_INT_REGS 0x01 357 #define ES_SMPREG_ACCUM_FRAC 0x02 358 #define ES_SMPREG_VFREQ_FRAC 0x03 359 360 /* 361 * Some contants 362 */ 363 364 #define ES_1370_SRCLOCK 1411200 365 #define ES_1370_SRTODIV(x) (ES_1370_SRCLOCK/(x)-2) 366 367 /* 368 * Open modes 369 */ 370 371 #define ES_MODE_PLAY1 0x0001 372 #define ES_MODE_PLAY2 0x0002 373 #define ES_MODE_CAPTURE 0x0004 374 375 #define ES_MODE_OUTPUT 0x0001 /* for MIDI */ 376 #define ES_MODE_INPUT 0x0002 /* for MIDI */ 377 378 /* 379 380 */ 381 382 struct ensoniq { 383 spinlock_t reg_lock; 384 struct mutex src_mutex; 385 386 int irq; 387 388 unsigned long playback1size; 389 unsigned long playback2size; 390 unsigned long capture3size; 391 392 unsigned long port; 393 unsigned int mode; 394 unsigned int uartm; /* UART mode */ 395 396 unsigned int ctrl; /* control register */ 397 unsigned int sctrl; /* serial control register */ 398 unsigned int cssr; /* control status register */ 399 unsigned int uartc; /* uart control register */ 400 unsigned int rev; /* chip revision */ 401 402 union { 403 #ifdef CHIP1371 404 struct { 405 struct snd_ac97 *ac97; 406 } es1371; 407 #else 408 struct { 409 int pclkdiv_lock; 410 struct snd_ak4531 *ak4531; 411 } es1370; 412 #endif 413 } u; 414 415 struct pci_dev *pci; 416 struct snd_card *card; 417 struct snd_pcm *pcm1; /* DAC1/ADC PCM */ 418 struct snd_pcm *pcm2; /* DAC2 PCM */ 419 struct snd_pcm_substream *playback1_substream; 420 struct snd_pcm_substream *playback2_substream; 421 struct snd_pcm_substream *capture_substream; 422 unsigned int p1_dma_size; 423 unsigned int p2_dma_size; 424 unsigned int c_dma_size; 425 unsigned int p1_period_size; 426 unsigned int p2_period_size; 427 unsigned int c_period_size; 428 struct snd_rawmidi *rmidi; 429 struct snd_rawmidi_substream *midi_input; 430 struct snd_rawmidi_substream *midi_output; 431 432 unsigned int spdif; 433 unsigned int spdif_default; 434 unsigned int spdif_stream; 435 436 #ifdef CHIP1370 437 struct snd_dma_buffer dma_bug; 438 #endif 439 440 #ifdef SUPPORT_JOYSTICK 441 struct gameport *gameport; 442 #endif 443 }; 444 445 static irqreturn_t snd_audiopci_interrupt(int irq, void *dev_id); 446 447 static struct pci_device_id snd_audiopci_ids[] = { 448 #ifdef CHIP1370 449 { 0x1274, 0x5000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* ES1370 */ 450 #endif 451 #ifdef CHIP1371 452 { 0x1274, 0x1371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* ES1371 */ 453 { 0x1274, 0x5880, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* ES1373 - CT5880 */ 454 { 0x1102, 0x8938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* Ectiva EV1938 */ 455 #endif 456 { 0, } 457 }; 458 459 MODULE_DEVICE_TABLE(pci, snd_audiopci_ids); 460 461 /* 462 * constants 463 */ 464 465 #define POLL_COUNT 0xa000 466 467 #ifdef CHIP1370 468 static unsigned int snd_es1370_fixed_rates[] = 469 {5512, 11025, 22050, 44100}; 470 static struct snd_pcm_hw_constraint_list snd_es1370_hw_constraints_rates = { 471 .count = 4, 472 .list = snd_es1370_fixed_rates, 473 .mask = 0, 474 }; 475 static struct snd_ratnum es1370_clock = { 476 .num = ES_1370_SRCLOCK, 477 .den_min = 29, 478 .den_max = 353, 479 .den_step = 1, 480 }; 481 static struct snd_pcm_hw_constraint_ratnums snd_es1370_hw_constraints_clock = { 482 .nrats = 1, 483 .rats = &es1370_clock, 484 }; 485 #else 486 static struct snd_ratden es1371_dac_clock = { 487 .num_min = 3000 * (1 << 15), 488 .num_max = 48000 * (1 << 15), 489 .num_step = 3000, 490 .den = 1 << 15, 491 }; 492 static struct snd_pcm_hw_constraint_ratdens snd_es1371_hw_constraints_dac_clock = { 493 .nrats = 1, 494 .rats = &es1371_dac_clock, 495 }; 496 static struct snd_ratnum es1371_adc_clock = { 497 .num = 48000 << 15, 498 .den_min = 32768, 499 .den_max = 393216, 500 .den_step = 1, 501 }; 502 static struct snd_pcm_hw_constraint_ratnums snd_es1371_hw_constraints_adc_clock = { 503 .nrats = 1, 504 .rats = &es1371_adc_clock, 505 }; 506 #endif 507 static const unsigned int snd_ensoniq_sample_shift[] = 508 {0, 1, 1, 2}; 509 510 /* 511 * common I/O routines 512 */ 513 514 #ifdef CHIP1371 515 516 static unsigned int snd_es1371_wait_src_ready(struct ensoniq * ensoniq) 517 { 518 unsigned int t, r = 0; 519 520 for (t = 0; t < POLL_COUNT; t++) { 521 r = inl(ES_REG(ensoniq, 1371_SMPRATE)); 522 if ((r & ES_1371_SRC_RAM_BUSY) == 0) 523 return r; 524 cond_resched(); 525 } 526 snd_printk(KERN_ERR "wait source ready timeout 0x%lx [0x%x]\n", 527 ES_REG(ensoniq, 1371_SMPRATE), r); 528 return 0; 529 } 530 531 static unsigned int snd_es1371_src_read(struct ensoniq * ensoniq, unsigned short reg) 532 { 533 unsigned int temp, i, orig, r; 534 535 /* wait for ready */ 536 temp = orig = snd_es1371_wait_src_ready(ensoniq); 537 538 /* expose the SRC state bits */ 539 r = temp & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 | 540 ES_1371_DIS_P2 | ES_1371_DIS_R1); 541 r |= ES_1371_SRC_RAM_ADDRO(reg) | 0x10000; 542 outl(r, ES_REG(ensoniq, 1371_SMPRATE)); 543 544 /* now, wait for busy and the correct time to read */ 545 temp = snd_es1371_wait_src_ready(ensoniq); 546 547 if ((temp & 0x00870000) != 0x00010000) { 548 /* wait for the right state */ 549 for (i = 0; i < POLL_COUNT; i++) { 550 temp = inl(ES_REG(ensoniq, 1371_SMPRATE)); 551 if ((temp & 0x00870000) == 0x00010000) 552 break; 553 } 554 } 555 556 /* hide the state bits */ 557 r = orig & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 | 558 ES_1371_DIS_P2 | ES_1371_DIS_R1); 559 r |= ES_1371_SRC_RAM_ADDRO(reg); 560 outl(r, ES_REG(ensoniq, 1371_SMPRATE)); 561 562 return temp; 563 } 564 565 static void snd_es1371_src_write(struct ensoniq * ensoniq, 566 unsigned short reg, unsigned short data) 567 { 568 unsigned int r; 569 570 r = snd_es1371_wait_src_ready(ensoniq) & 571 (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 | 572 ES_1371_DIS_P2 | ES_1371_DIS_R1); 573 r |= ES_1371_SRC_RAM_ADDRO(reg) | ES_1371_SRC_RAM_DATAO(data); 574 outl(r | ES_1371_SRC_RAM_WE, ES_REG(ensoniq, 1371_SMPRATE)); 575 } 576 577 #endif /* CHIP1371 */ 578 579 #ifdef CHIP1370 580 581 static void snd_es1370_codec_write(struct snd_ak4531 *ak4531, 582 unsigned short reg, unsigned short val) 583 { 584 struct ensoniq *ensoniq = ak4531->private_data; 585 unsigned long end_time = jiffies + HZ / 10; 586 587 #if 0 588 printk("CODEC WRITE: reg = 0x%x, val = 0x%x (0x%x), creg = 0x%x\n", 589 reg, val, ES_1370_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1370_CODEC)); 590 #endif 591 do { 592 if (!(inl(ES_REG(ensoniq, STATUS)) & ES_1370_CSTAT)) { 593 outw(ES_1370_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1370_CODEC)); 594 return; 595 } 596 schedule_timeout_uninterruptible(1); 597 } while (time_after(end_time, jiffies)); 598 snd_printk(KERN_ERR "codec write timeout, status = 0x%x\n", 599 inl(ES_REG(ensoniq, STATUS))); 600 } 601 602 #endif /* CHIP1370 */ 603 604 #ifdef CHIP1371 605 606 static void snd_es1371_codec_write(struct snd_ac97 *ac97, 607 unsigned short reg, unsigned short val) 608 { 609 struct ensoniq *ensoniq = ac97->private_data; 610 unsigned int t, x; 611 612 mutex_lock(&ensoniq->src_mutex); 613 for (t = 0; t < POLL_COUNT; t++) { 614 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) { 615 /* save the current state for latter */ 616 x = snd_es1371_wait_src_ready(ensoniq); 617 outl((x & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 | 618 ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 0x00010000, 619 ES_REG(ensoniq, 1371_SMPRATE)); 620 /* wait for not busy (state 0) first to avoid 621 transition states */ 622 for (t = 0; t < POLL_COUNT; t++) { 623 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) == 624 0x00000000) 625 break; 626 } 627 /* wait for a SAFE time to write addr/data and then do it, dammit */ 628 for (t = 0; t < POLL_COUNT; t++) { 629 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) == 630 0x00010000) 631 break; 632 } 633 outl(ES_1371_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1371_CODEC)); 634 /* restore SRC reg */ 635 snd_es1371_wait_src_ready(ensoniq); 636 outl(x, ES_REG(ensoniq, 1371_SMPRATE)); 637 mutex_unlock(&ensoniq->src_mutex); 638 return; 639 } 640 } 641 mutex_unlock(&ensoniq->src_mutex); 642 snd_printk(KERN_ERR "codec write timeout at 0x%lx [0x%x]\n", 643 ES_REG(ensoniq, 1371_CODEC), inl(ES_REG(ensoniq, 1371_CODEC))); 644 } 645 646 static unsigned short snd_es1371_codec_read(struct snd_ac97 *ac97, 647 unsigned short reg) 648 { 649 struct ensoniq *ensoniq = ac97->private_data; 650 unsigned int t, x, fail = 0; 651 652 __again: 653 mutex_lock(&ensoniq->src_mutex); 654 for (t = 0; t < POLL_COUNT; t++) { 655 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) { 656 /* save the current state for latter */ 657 x = snd_es1371_wait_src_ready(ensoniq); 658 outl((x & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 | 659 ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 0x00010000, 660 ES_REG(ensoniq, 1371_SMPRATE)); 661 /* wait for not busy (state 0) first to avoid 662 transition states */ 663 for (t = 0; t < POLL_COUNT; t++) { 664 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) == 665 0x00000000) 666 break; 667 } 668 /* wait for a SAFE time to write addr/data and then do it, dammit */ 669 for (t = 0; t < POLL_COUNT; t++) { 670 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) == 671 0x00010000) 672 break; 673 } 674 outl(ES_1371_CODEC_READS(reg), ES_REG(ensoniq, 1371_CODEC)); 675 /* restore SRC reg */ 676 snd_es1371_wait_src_ready(ensoniq); 677 outl(x, ES_REG(ensoniq, 1371_SMPRATE)); 678 /* wait for WIP again */ 679 for (t = 0; t < POLL_COUNT; t++) { 680 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) 681 break; 682 } 683 /* now wait for the stinkin' data (RDY) */ 684 for (t = 0; t < POLL_COUNT; t++) { 685 if ((x = inl(ES_REG(ensoniq, 1371_CODEC))) & ES_1371_CODEC_RDY) { 686 mutex_unlock(&ensoniq->src_mutex); 687 return ES_1371_CODEC_READ(x); 688 } 689 } 690 mutex_unlock(&ensoniq->src_mutex); 691 if (++fail > 10) { 692 snd_printk(KERN_ERR "codec read timeout (final) " 693 "at 0x%lx, reg = 0x%x [0x%x]\n", 694 ES_REG(ensoniq, 1371_CODEC), reg, 695 inl(ES_REG(ensoniq, 1371_CODEC))); 696 return 0; 697 } 698 goto __again; 699 } 700 } 701 mutex_unlock(&ensoniq->src_mutex); 702 snd_printk(KERN_ERR "es1371: codec read timeout at 0x%lx [0x%x]\n", 703 ES_REG(ensoniq, 1371_CODEC), inl(ES_REG(ensoniq, 1371_CODEC))); 704 return 0; 705 } 706 707 static void snd_es1371_codec_wait(struct snd_ac97 *ac97) 708 { 709 msleep(750); 710 snd_es1371_codec_read(ac97, AC97_RESET); 711 snd_es1371_codec_read(ac97, AC97_VENDOR_ID1); 712 snd_es1371_codec_read(ac97, AC97_VENDOR_ID2); 713 msleep(50); 714 } 715 716 static void snd_es1371_adc_rate(struct ensoniq * ensoniq, unsigned int rate) 717 { 718 unsigned int n, truncm, freq, result; 719 720 mutex_lock(&ensoniq->src_mutex); 721 n = rate / 3000; 722 if ((1 << n) & ((1 << 15) | (1 << 13) | (1 << 11) | (1 << 9))) 723 n--; 724 truncm = (21 * n - 1) | 1; 725 freq = ((48000UL << 15) / rate) * n; 726 result = (48000UL << 15) / (freq / n); 727 if (rate >= 24000) { 728 if (truncm > 239) 729 truncm = 239; 730 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N, 731 (((239 - truncm) >> 1) << 9) | (n << 4)); 732 } else { 733 if (truncm > 119) 734 truncm = 119; 735 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N, 736 0x8000 | (((119 - truncm) >> 1) << 9) | (n << 4)); 737 } 738 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_INT_REGS, 739 (snd_es1371_src_read(ensoniq, ES_SMPREG_ADC + 740 ES_SMPREG_INT_REGS) & 0x00ff) | 741 ((freq >> 5) & 0xfc00)); 742 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff); 743 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC, n << 8); 744 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC + 1, n << 8); 745 mutex_unlock(&ensoniq->src_mutex); 746 } 747 748 static void snd_es1371_dac1_rate(struct ensoniq * ensoniq, unsigned int rate) 749 { 750 unsigned int freq, r; 751 752 mutex_lock(&ensoniq->src_mutex); 753 freq = ((rate << 15) + 1500) / 3000; 754 r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE | 755 ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 756 ES_1371_DIS_P1; 757 outl(r, ES_REG(ensoniq, 1371_SMPRATE)); 758 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS, 759 (snd_es1371_src_read(ensoniq, ES_SMPREG_DAC1 + 760 ES_SMPREG_INT_REGS) & 0x00ff) | 761 ((freq >> 5) & 0xfc00)); 762 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff); 763 r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE | 764 ES_1371_DIS_P2 | ES_1371_DIS_R1)); 765 outl(r, ES_REG(ensoniq, 1371_SMPRATE)); 766 mutex_unlock(&ensoniq->src_mutex); 767 } 768 769 static void snd_es1371_dac2_rate(struct ensoniq * ensoniq, unsigned int rate) 770 { 771 unsigned int freq, r; 772 773 mutex_lock(&ensoniq->src_mutex); 774 freq = ((rate << 15) + 1500) / 3000; 775 r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE | 776 ES_1371_DIS_P1 | ES_1371_DIS_R1)) | 777 ES_1371_DIS_P2; 778 outl(r, ES_REG(ensoniq, 1371_SMPRATE)); 779 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS, 780 (snd_es1371_src_read(ensoniq, ES_SMPREG_DAC2 + 781 ES_SMPREG_INT_REGS) & 0x00ff) | 782 ((freq >> 5) & 0xfc00)); 783 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_VFREQ_FRAC, 784 freq & 0x7fff); 785 r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE | 786 ES_1371_DIS_P1 | ES_1371_DIS_R1)); 787 outl(r, ES_REG(ensoniq, 1371_SMPRATE)); 788 mutex_unlock(&ensoniq->src_mutex); 789 } 790 791 #endif /* CHIP1371 */ 792 793 static int snd_ensoniq_trigger(struct snd_pcm_substream *substream, int cmd) 794 { 795 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); 796 switch (cmd) { 797 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 798 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 799 { 800 unsigned int what = 0; 801 struct list_head *pos; 802 struct snd_pcm_substream *s; 803 snd_pcm_group_for_each(pos, substream) { 804 s = snd_pcm_group_substream_entry(pos); 805 if (s == ensoniq->playback1_substream) { 806 what |= ES_P1_PAUSE; 807 snd_pcm_trigger_done(s, substream); 808 } else if (s == ensoniq->playback2_substream) { 809 what |= ES_P2_PAUSE; 810 snd_pcm_trigger_done(s, substream); 811 } else if (s == ensoniq->capture_substream) 812 return -EINVAL; 813 } 814 spin_lock(&ensoniq->reg_lock); 815 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH) 816 ensoniq->sctrl |= what; 817 else 818 ensoniq->sctrl &= ~what; 819 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL)); 820 spin_unlock(&ensoniq->reg_lock); 821 break; 822 } 823 case SNDRV_PCM_TRIGGER_START: 824 case SNDRV_PCM_TRIGGER_STOP: 825 { 826 unsigned int what = 0; 827 struct list_head *pos; 828 struct snd_pcm_substream *s; 829 snd_pcm_group_for_each(pos, substream) { 830 s = snd_pcm_group_substream_entry(pos); 831 if (s == ensoniq->playback1_substream) { 832 what |= ES_DAC1_EN; 833 snd_pcm_trigger_done(s, substream); 834 } else if (s == ensoniq->playback2_substream) { 835 what |= ES_DAC2_EN; 836 snd_pcm_trigger_done(s, substream); 837 } else if (s == ensoniq->capture_substream) { 838 what |= ES_ADC_EN; 839 snd_pcm_trigger_done(s, substream); 840 } 841 } 842 spin_lock(&ensoniq->reg_lock); 843 if (cmd == SNDRV_PCM_TRIGGER_START) 844 ensoniq->ctrl |= what; 845 else 846 ensoniq->ctrl &= ~what; 847 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 848 spin_unlock(&ensoniq->reg_lock); 849 break; 850 } 851 default: 852 return -EINVAL; 853 } 854 return 0; 855 } 856 857 /* 858 * PCM part 859 */ 860 861 static int snd_ensoniq_hw_params(struct snd_pcm_substream *substream, 862 struct snd_pcm_hw_params *hw_params) 863 { 864 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params)); 865 } 866 867 static int snd_ensoniq_hw_free(struct snd_pcm_substream *substream) 868 { 869 return snd_pcm_lib_free_pages(substream); 870 } 871 872 static int snd_ensoniq_playback1_prepare(struct snd_pcm_substream *substream) 873 { 874 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); 875 struct snd_pcm_runtime *runtime = substream->runtime; 876 unsigned int mode = 0; 877 878 ensoniq->p1_dma_size = snd_pcm_lib_buffer_bytes(substream); 879 ensoniq->p1_period_size = snd_pcm_lib_period_bytes(substream); 880 if (snd_pcm_format_width(runtime->format) == 16) 881 mode |= 0x02; 882 if (runtime->channels > 1) 883 mode |= 0x01; 884 spin_lock_irq(&ensoniq->reg_lock); 885 ensoniq->ctrl &= ~ES_DAC1_EN; 886 #ifdef CHIP1371 887 /* 48k doesn't need SRC (it breaks AC3-passthru) */ 888 if (runtime->rate == 48000) 889 ensoniq->ctrl |= ES_1373_BYPASS_P1; 890 else 891 ensoniq->ctrl &= ~ES_1373_BYPASS_P1; 892 #endif 893 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 894 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE)); 895 outl(runtime->dma_addr, ES_REG(ensoniq, DAC1_FRAME)); 896 outl((ensoniq->p1_dma_size >> 2) - 1, ES_REG(ensoniq, DAC1_SIZE)); 897 ensoniq->sctrl &= ~(ES_P1_LOOP_SEL | ES_P1_PAUSE | ES_P1_SCT_RLD | ES_P1_MODEM); 898 ensoniq->sctrl |= ES_P1_INT_EN | ES_P1_MODEO(mode); 899 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL)); 900 outl((ensoniq->p1_period_size >> snd_ensoniq_sample_shift[mode]) - 1, 901 ES_REG(ensoniq, DAC1_COUNT)); 902 #ifdef CHIP1370 903 ensoniq->ctrl &= ~ES_1370_WTSRSELM; 904 switch (runtime->rate) { 905 case 5512: ensoniq->ctrl |= ES_1370_WTSRSEL(0); break; 906 case 11025: ensoniq->ctrl |= ES_1370_WTSRSEL(1); break; 907 case 22050: ensoniq->ctrl |= ES_1370_WTSRSEL(2); break; 908 case 44100: ensoniq->ctrl |= ES_1370_WTSRSEL(3); break; 909 default: snd_BUG(); 910 } 911 #endif 912 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 913 spin_unlock_irq(&ensoniq->reg_lock); 914 #ifndef CHIP1370 915 snd_es1371_dac1_rate(ensoniq, runtime->rate); 916 #endif 917 return 0; 918 } 919 920 static int snd_ensoniq_playback2_prepare(struct snd_pcm_substream *substream) 921 { 922 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); 923 struct snd_pcm_runtime *runtime = substream->runtime; 924 unsigned int mode = 0; 925 926 ensoniq->p2_dma_size = snd_pcm_lib_buffer_bytes(substream); 927 ensoniq->p2_period_size = snd_pcm_lib_period_bytes(substream); 928 if (snd_pcm_format_width(runtime->format) == 16) 929 mode |= 0x02; 930 if (runtime->channels > 1) 931 mode |= 0x01; 932 spin_lock_irq(&ensoniq->reg_lock); 933 ensoniq->ctrl &= ~ES_DAC2_EN; 934 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 935 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE)); 936 outl(runtime->dma_addr, ES_REG(ensoniq, DAC2_FRAME)); 937 outl((ensoniq->p2_dma_size >> 2) - 1, ES_REG(ensoniq, DAC2_SIZE)); 938 ensoniq->sctrl &= ~(ES_P2_LOOP_SEL | ES_P2_PAUSE | ES_P2_DAC_SEN | 939 ES_P2_END_INCM | ES_P2_ST_INCM | ES_P2_MODEM); 940 ensoniq->sctrl |= ES_P2_INT_EN | ES_P2_MODEO(mode) | 941 ES_P2_END_INCO(mode & 2 ? 2 : 1) | ES_P2_ST_INCO(0); 942 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL)); 943 outl((ensoniq->p2_period_size >> snd_ensoniq_sample_shift[mode]) - 1, 944 ES_REG(ensoniq, DAC2_COUNT)); 945 #ifdef CHIP1370 946 if (!(ensoniq->u.es1370.pclkdiv_lock & ES_MODE_CAPTURE)) { 947 ensoniq->ctrl &= ~ES_1370_PCLKDIVM; 948 ensoniq->ctrl |= ES_1370_PCLKDIVO(ES_1370_SRTODIV(runtime->rate)); 949 ensoniq->u.es1370.pclkdiv_lock |= ES_MODE_PLAY2; 950 } 951 #endif 952 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 953 spin_unlock_irq(&ensoniq->reg_lock); 954 #ifndef CHIP1370 955 snd_es1371_dac2_rate(ensoniq, runtime->rate); 956 #endif 957 return 0; 958 } 959 960 static int snd_ensoniq_capture_prepare(struct snd_pcm_substream *substream) 961 { 962 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); 963 struct snd_pcm_runtime *runtime = substream->runtime; 964 unsigned int mode = 0; 965 966 ensoniq->c_dma_size = snd_pcm_lib_buffer_bytes(substream); 967 ensoniq->c_period_size = snd_pcm_lib_period_bytes(substream); 968 if (snd_pcm_format_width(runtime->format) == 16) 969 mode |= 0x02; 970 if (runtime->channels > 1) 971 mode |= 0x01; 972 spin_lock_irq(&ensoniq->reg_lock); 973 ensoniq->ctrl &= ~ES_ADC_EN; 974 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 975 outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE)); 976 outl(runtime->dma_addr, ES_REG(ensoniq, ADC_FRAME)); 977 outl((ensoniq->c_dma_size >> 2) - 1, ES_REG(ensoniq, ADC_SIZE)); 978 ensoniq->sctrl &= ~(ES_R1_LOOP_SEL | ES_R1_MODEM); 979 ensoniq->sctrl |= ES_R1_INT_EN | ES_R1_MODEO(mode); 980 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL)); 981 outl((ensoniq->c_period_size >> snd_ensoniq_sample_shift[mode]) - 1, 982 ES_REG(ensoniq, ADC_COUNT)); 983 #ifdef CHIP1370 984 if (!(ensoniq->u.es1370.pclkdiv_lock & ES_MODE_PLAY2)) { 985 ensoniq->ctrl &= ~ES_1370_PCLKDIVM; 986 ensoniq->ctrl |= ES_1370_PCLKDIVO(ES_1370_SRTODIV(runtime->rate)); 987 ensoniq->u.es1370.pclkdiv_lock |= ES_MODE_CAPTURE; 988 } 989 #endif 990 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 991 spin_unlock_irq(&ensoniq->reg_lock); 992 #ifndef CHIP1370 993 snd_es1371_adc_rate(ensoniq, runtime->rate); 994 #endif 995 return 0; 996 } 997 998 static snd_pcm_uframes_t snd_ensoniq_playback1_pointer(struct snd_pcm_substream *substream) 999 { 1000 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); 1001 size_t ptr; 1002 1003 spin_lock(&ensoniq->reg_lock); 1004 if (inl(ES_REG(ensoniq, CONTROL)) & ES_DAC1_EN) { 1005 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE)); 1006 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, DAC1_SIZE))); 1007 ptr = bytes_to_frames(substream->runtime, ptr); 1008 } else { 1009 ptr = 0; 1010 } 1011 spin_unlock(&ensoniq->reg_lock); 1012 return ptr; 1013 } 1014 1015 static snd_pcm_uframes_t snd_ensoniq_playback2_pointer(struct snd_pcm_substream *substream) 1016 { 1017 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); 1018 size_t ptr; 1019 1020 spin_lock(&ensoniq->reg_lock); 1021 if (inl(ES_REG(ensoniq, CONTROL)) & ES_DAC2_EN) { 1022 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE)); 1023 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, DAC2_SIZE))); 1024 ptr = bytes_to_frames(substream->runtime, ptr); 1025 } else { 1026 ptr = 0; 1027 } 1028 spin_unlock(&ensoniq->reg_lock); 1029 return ptr; 1030 } 1031 1032 static snd_pcm_uframes_t snd_ensoniq_capture_pointer(struct snd_pcm_substream *substream) 1033 { 1034 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); 1035 size_t ptr; 1036 1037 spin_lock(&ensoniq->reg_lock); 1038 if (inl(ES_REG(ensoniq, CONTROL)) & ES_ADC_EN) { 1039 outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE)); 1040 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, ADC_SIZE))); 1041 ptr = bytes_to_frames(substream->runtime, ptr); 1042 } else { 1043 ptr = 0; 1044 } 1045 spin_unlock(&ensoniq->reg_lock); 1046 return ptr; 1047 } 1048 1049 static struct snd_pcm_hardware snd_ensoniq_playback1 = 1050 { 1051 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 1052 SNDRV_PCM_INFO_BLOCK_TRANSFER | 1053 SNDRV_PCM_INFO_MMAP_VALID | 1054 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START), 1055 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE, 1056 .rates = 1057 #ifndef CHIP1370 1058 SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, 1059 #else 1060 (SNDRV_PCM_RATE_KNOT | /* 5512Hz rate */ 1061 SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_22050 | 1062 SNDRV_PCM_RATE_44100), 1063 #endif 1064 .rate_min = 4000, 1065 .rate_max = 48000, 1066 .channels_min = 1, 1067 .channels_max = 2, 1068 .buffer_bytes_max = (128*1024), 1069 .period_bytes_min = 64, 1070 .period_bytes_max = (128*1024), 1071 .periods_min = 1, 1072 .periods_max = 1024, 1073 .fifo_size = 0, 1074 }; 1075 1076 static struct snd_pcm_hardware snd_ensoniq_playback2 = 1077 { 1078 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 1079 SNDRV_PCM_INFO_BLOCK_TRANSFER | 1080 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_PAUSE | 1081 SNDRV_PCM_INFO_SYNC_START), 1082 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE, 1083 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, 1084 .rate_min = 4000, 1085 .rate_max = 48000, 1086 .channels_min = 1, 1087 .channels_max = 2, 1088 .buffer_bytes_max = (128*1024), 1089 .period_bytes_min = 64, 1090 .period_bytes_max = (128*1024), 1091 .periods_min = 1, 1092 .periods_max = 1024, 1093 .fifo_size = 0, 1094 }; 1095 1096 static struct snd_pcm_hardware snd_ensoniq_capture = 1097 { 1098 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 1099 SNDRV_PCM_INFO_BLOCK_TRANSFER | 1100 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_SYNC_START), 1101 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE, 1102 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, 1103 .rate_min = 4000, 1104 .rate_max = 48000, 1105 .channels_min = 1, 1106 .channels_max = 2, 1107 .buffer_bytes_max = (128*1024), 1108 .period_bytes_min = 64, 1109 .period_bytes_max = (128*1024), 1110 .periods_min = 1, 1111 .periods_max = 1024, 1112 .fifo_size = 0, 1113 }; 1114 1115 static int snd_ensoniq_playback1_open(struct snd_pcm_substream *substream) 1116 { 1117 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); 1118 struct snd_pcm_runtime *runtime = substream->runtime; 1119 1120 ensoniq->mode |= ES_MODE_PLAY1; 1121 ensoniq->playback1_substream = substream; 1122 runtime->hw = snd_ensoniq_playback1; 1123 snd_pcm_set_sync(substream); 1124 spin_lock_irq(&ensoniq->reg_lock); 1125 if (ensoniq->spdif && ensoniq->playback2_substream == NULL) 1126 ensoniq->spdif_stream = ensoniq->spdif_default; 1127 spin_unlock_irq(&ensoniq->reg_lock); 1128 #ifdef CHIP1370 1129 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 1130 &snd_es1370_hw_constraints_rates); 1131 #else 1132 snd_pcm_hw_constraint_ratdens(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 1133 &snd_es1371_hw_constraints_dac_clock); 1134 #endif 1135 return 0; 1136 } 1137 1138 static int snd_ensoniq_playback2_open(struct snd_pcm_substream *substream) 1139 { 1140 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); 1141 struct snd_pcm_runtime *runtime = substream->runtime; 1142 1143 ensoniq->mode |= ES_MODE_PLAY2; 1144 ensoniq->playback2_substream = substream; 1145 runtime->hw = snd_ensoniq_playback2; 1146 snd_pcm_set_sync(substream); 1147 spin_lock_irq(&ensoniq->reg_lock); 1148 if (ensoniq->spdif && ensoniq->playback1_substream == NULL) 1149 ensoniq->spdif_stream = ensoniq->spdif_default; 1150 spin_unlock_irq(&ensoniq->reg_lock); 1151 #ifdef CHIP1370 1152 snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 1153 &snd_es1370_hw_constraints_clock); 1154 #else 1155 snd_pcm_hw_constraint_ratdens(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 1156 &snd_es1371_hw_constraints_dac_clock); 1157 #endif 1158 return 0; 1159 } 1160 1161 static int snd_ensoniq_capture_open(struct snd_pcm_substream *substream) 1162 { 1163 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); 1164 struct snd_pcm_runtime *runtime = substream->runtime; 1165 1166 ensoniq->mode |= ES_MODE_CAPTURE; 1167 ensoniq->capture_substream = substream; 1168 runtime->hw = snd_ensoniq_capture; 1169 snd_pcm_set_sync(substream); 1170 #ifdef CHIP1370 1171 snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 1172 &snd_es1370_hw_constraints_clock); 1173 #else 1174 snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 1175 &snd_es1371_hw_constraints_adc_clock); 1176 #endif 1177 return 0; 1178 } 1179 1180 static int snd_ensoniq_playback1_close(struct snd_pcm_substream *substream) 1181 { 1182 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); 1183 1184 ensoniq->playback1_substream = NULL; 1185 ensoniq->mode &= ~ES_MODE_PLAY1; 1186 return 0; 1187 } 1188 1189 static int snd_ensoniq_playback2_close(struct snd_pcm_substream *substream) 1190 { 1191 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); 1192 1193 ensoniq->playback2_substream = NULL; 1194 spin_lock_irq(&ensoniq->reg_lock); 1195 #ifdef CHIP1370 1196 ensoniq->u.es1370.pclkdiv_lock &= ~ES_MODE_PLAY2; 1197 #endif 1198 ensoniq->mode &= ~ES_MODE_PLAY2; 1199 spin_unlock_irq(&ensoniq->reg_lock); 1200 return 0; 1201 } 1202 1203 static int snd_ensoniq_capture_close(struct snd_pcm_substream *substream) 1204 { 1205 struct ensoniq *ensoniq = snd_pcm_substream_chip(substream); 1206 1207 ensoniq->capture_substream = NULL; 1208 spin_lock_irq(&ensoniq->reg_lock); 1209 #ifdef CHIP1370 1210 ensoniq->u.es1370.pclkdiv_lock &= ~ES_MODE_CAPTURE; 1211 #endif 1212 ensoniq->mode &= ~ES_MODE_CAPTURE; 1213 spin_unlock_irq(&ensoniq->reg_lock); 1214 return 0; 1215 } 1216 1217 static struct snd_pcm_ops snd_ensoniq_playback1_ops = { 1218 .open = snd_ensoniq_playback1_open, 1219 .close = snd_ensoniq_playback1_close, 1220 .ioctl = snd_pcm_lib_ioctl, 1221 .hw_params = snd_ensoniq_hw_params, 1222 .hw_free = snd_ensoniq_hw_free, 1223 .prepare = snd_ensoniq_playback1_prepare, 1224 .trigger = snd_ensoniq_trigger, 1225 .pointer = snd_ensoniq_playback1_pointer, 1226 }; 1227 1228 static struct snd_pcm_ops snd_ensoniq_playback2_ops = { 1229 .open = snd_ensoniq_playback2_open, 1230 .close = snd_ensoniq_playback2_close, 1231 .ioctl = snd_pcm_lib_ioctl, 1232 .hw_params = snd_ensoniq_hw_params, 1233 .hw_free = snd_ensoniq_hw_free, 1234 .prepare = snd_ensoniq_playback2_prepare, 1235 .trigger = snd_ensoniq_trigger, 1236 .pointer = snd_ensoniq_playback2_pointer, 1237 }; 1238 1239 static struct snd_pcm_ops snd_ensoniq_capture_ops = { 1240 .open = snd_ensoniq_capture_open, 1241 .close = snd_ensoniq_capture_close, 1242 .ioctl = snd_pcm_lib_ioctl, 1243 .hw_params = snd_ensoniq_hw_params, 1244 .hw_free = snd_ensoniq_hw_free, 1245 .prepare = snd_ensoniq_capture_prepare, 1246 .trigger = snd_ensoniq_trigger, 1247 .pointer = snd_ensoniq_capture_pointer, 1248 }; 1249 1250 static int __devinit snd_ensoniq_pcm(struct ensoniq * ensoniq, int device, 1251 struct snd_pcm ** rpcm) 1252 { 1253 struct snd_pcm *pcm; 1254 int err; 1255 1256 if (rpcm) 1257 *rpcm = NULL; 1258 #ifdef CHIP1370 1259 err = snd_pcm_new(ensoniq->card, "ES1370/1", device, 1, 1, &pcm); 1260 #else 1261 err = snd_pcm_new(ensoniq->card, "ES1371/1", device, 1, 1, &pcm); 1262 #endif 1263 if (err < 0) 1264 return err; 1265 1266 #ifdef CHIP1370 1267 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback2_ops); 1268 #else 1269 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback1_ops); 1270 #endif 1271 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ensoniq_capture_ops); 1272 1273 pcm->private_data = ensoniq; 1274 pcm->info_flags = 0; 1275 #ifdef CHIP1370 1276 strcpy(pcm->name, "ES1370 DAC2/ADC"); 1277 #else 1278 strcpy(pcm->name, "ES1371 DAC2/ADC"); 1279 #endif 1280 ensoniq->pcm1 = pcm; 1281 1282 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 1283 snd_dma_pci_data(ensoniq->pci), 64*1024, 128*1024); 1284 1285 if (rpcm) 1286 *rpcm = pcm; 1287 return 0; 1288 } 1289 1290 static int __devinit snd_ensoniq_pcm2(struct ensoniq * ensoniq, int device, 1291 struct snd_pcm ** rpcm) 1292 { 1293 struct snd_pcm *pcm; 1294 int err; 1295 1296 if (rpcm) 1297 *rpcm = NULL; 1298 #ifdef CHIP1370 1299 err = snd_pcm_new(ensoniq->card, "ES1370/2", device, 1, 0, &pcm); 1300 #else 1301 err = snd_pcm_new(ensoniq->card, "ES1371/2", device, 1, 0, &pcm); 1302 #endif 1303 if (err < 0) 1304 return err; 1305 1306 #ifdef CHIP1370 1307 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback1_ops); 1308 #else 1309 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback2_ops); 1310 #endif 1311 pcm->private_data = ensoniq; 1312 pcm->info_flags = 0; 1313 #ifdef CHIP1370 1314 strcpy(pcm->name, "ES1370 DAC1"); 1315 #else 1316 strcpy(pcm->name, "ES1371 DAC1"); 1317 #endif 1318 ensoniq->pcm2 = pcm; 1319 1320 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 1321 snd_dma_pci_data(ensoniq->pci), 64*1024, 128*1024); 1322 1323 if (rpcm) 1324 *rpcm = pcm; 1325 return 0; 1326 } 1327 1328 /* 1329 * Mixer section 1330 */ 1331 1332 /* 1333 * ENS1371 mixer (including SPDIF interface) 1334 */ 1335 #ifdef CHIP1371 1336 static int snd_ens1373_spdif_info(struct snd_kcontrol *kcontrol, 1337 struct snd_ctl_elem_info *uinfo) 1338 { 1339 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 1340 uinfo->count = 1; 1341 return 0; 1342 } 1343 1344 static int snd_ens1373_spdif_default_get(struct snd_kcontrol *kcontrol, 1345 struct snd_ctl_elem_value *ucontrol) 1346 { 1347 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); 1348 spin_lock_irq(&ensoniq->reg_lock); 1349 ucontrol->value.iec958.status[0] = (ensoniq->spdif_default >> 0) & 0xff; 1350 ucontrol->value.iec958.status[1] = (ensoniq->spdif_default >> 8) & 0xff; 1351 ucontrol->value.iec958.status[2] = (ensoniq->spdif_default >> 16) & 0xff; 1352 ucontrol->value.iec958.status[3] = (ensoniq->spdif_default >> 24) & 0xff; 1353 spin_unlock_irq(&ensoniq->reg_lock); 1354 return 0; 1355 } 1356 1357 static int snd_ens1373_spdif_default_put(struct snd_kcontrol *kcontrol, 1358 struct snd_ctl_elem_value *ucontrol) 1359 { 1360 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); 1361 unsigned int val; 1362 int change; 1363 1364 val = ((u32)ucontrol->value.iec958.status[0] << 0) | 1365 ((u32)ucontrol->value.iec958.status[1] << 8) | 1366 ((u32)ucontrol->value.iec958.status[2] << 16) | 1367 ((u32)ucontrol->value.iec958.status[3] << 24); 1368 spin_lock_irq(&ensoniq->reg_lock); 1369 change = ensoniq->spdif_default != val; 1370 ensoniq->spdif_default = val; 1371 if (change && ensoniq->playback1_substream == NULL && 1372 ensoniq->playback2_substream == NULL) 1373 outl(val, ES_REG(ensoniq, CHANNEL_STATUS)); 1374 spin_unlock_irq(&ensoniq->reg_lock); 1375 return change; 1376 } 1377 1378 static int snd_ens1373_spdif_mask_get(struct snd_kcontrol *kcontrol, 1379 struct snd_ctl_elem_value *ucontrol) 1380 { 1381 ucontrol->value.iec958.status[0] = 0xff; 1382 ucontrol->value.iec958.status[1] = 0xff; 1383 ucontrol->value.iec958.status[2] = 0xff; 1384 ucontrol->value.iec958.status[3] = 0xff; 1385 return 0; 1386 } 1387 1388 static int snd_ens1373_spdif_stream_get(struct snd_kcontrol *kcontrol, 1389 struct snd_ctl_elem_value *ucontrol) 1390 { 1391 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); 1392 spin_lock_irq(&ensoniq->reg_lock); 1393 ucontrol->value.iec958.status[0] = (ensoniq->spdif_stream >> 0) & 0xff; 1394 ucontrol->value.iec958.status[1] = (ensoniq->spdif_stream >> 8) & 0xff; 1395 ucontrol->value.iec958.status[2] = (ensoniq->spdif_stream >> 16) & 0xff; 1396 ucontrol->value.iec958.status[3] = (ensoniq->spdif_stream >> 24) & 0xff; 1397 spin_unlock_irq(&ensoniq->reg_lock); 1398 return 0; 1399 } 1400 1401 static int snd_ens1373_spdif_stream_put(struct snd_kcontrol *kcontrol, 1402 struct snd_ctl_elem_value *ucontrol) 1403 { 1404 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); 1405 unsigned int val; 1406 int change; 1407 1408 val = ((u32)ucontrol->value.iec958.status[0] << 0) | 1409 ((u32)ucontrol->value.iec958.status[1] << 8) | 1410 ((u32)ucontrol->value.iec958.status[2] << 16) | 1411 ((u32)ucontrol->value.iec958.status[3] << 24); 1412 spin_lock_irq(&ensoniq->reg_lock); 1413 change = ensoniq->spdif_stream != val; 1414 ensoniq->spdif_stream = val; 1415 if (change && (ensoniq->playback1_substream != NULL || 1416 ensoniq->playback2_substream != NULL)) 1417 outl(val, ES_REG(ensoniq, CHANNEL_STATUS)); 1418 spin_unlock_irq(&ensoniq->reg_lock); 1419 return change; 1420 } 1421 1422 #define ES1371_SPDIF(xname) \ 1423 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .info = snd_es1371_spdif_info, \ 1424 .get = snd_es1371_spdif_get, .put = snd_es1371_spdif_put } 1425 1426 static int snd_es1371_spdif_info(struct snd_kcontrol *kcontrol, 1427 struct snd_ctl_elem_info *uinfo) 1428 { 1429 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 1430 uinfo->count = 1; 1431 uinfo->value.integer.min = 0; 1432 uinfo->value.integer.max = 1; 1433 return 0; 1434 } 1435 1436 static int snd_es1371_spdif_get(struct snd_kcontrol *kcontrol, 1437 struct snd_ctl_elem_value *ucontrol) 1438 { 1439 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); 1440 1441 spin_lock_irq(&ensoniq->reg_lock); 1442 ucontrol->value.integer.value[0] = ensoniq->ctrl & ES_1373_SPDIF_THRU ? 1 : 0; 1443 spin_unlock_irq(&ensoniq->reg_lock); 1444 return 0; 1445 } 1446 1447 static int snd_es1371_spdif_put(struct snd_kcontrol *kcontrol, 1448 struct snd_ctl_elem_value *ucontrol) 1449 { 1450 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); 1451 unsigned int nval1, nval2; 1452 int change; 1453 1454 nval1 = ucontrol->value.integer.value[0] ? ES_1373_SPDIF_THRU : 0; 1455 nval2 = ucontrol->value.integer.value[0] ? ES_1373_SPDIF_EN : 0; 1456 spin_lock_irq(&ensoniq->reg_lock); 1457 change = (ensoniq->ctrl & ES_1373_SPDIF_THRU) != nval1; 1458 ensoniq->ctrl &= ~ES_1373_SPDIF_THRU; 1459 ensoniq->ctrl |= nval1; 1460 ensoniq->cssr &= ~ES_1373_SPDIF_EN; 1461 ensoniq->cssr |= nval2; 1462 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 1463 outl(ensoniq->cssr, ES_REG(ensoniq, STATUS)); 1464 spin_unlock_irq(&ensoniq->reg_lock); 1465 return change; 1466 } 1467 1468 1469 /* spdif controls */ 1470 static struct snd_kcontrol_new snd_es1371_mixer_spdif[] __devinitdata = { 1471 ES1371_SPDIF(SNDRV_CTL_NAME_IEC958("",PLAYBACK,SWITCH)), 1472 { 1473 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1474 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT), 1475 .info = snd_ens1373_spdif_info, 1476 .get = snd_ens1373_spdif_default_get, 1477 .put = snd_ens1373_spdif_default_put, 1478 }, 1479 { 1480 .access = SNDRV_CTL_ELEM_ACCESS_READ, 1481 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1482 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK), 1483 .info = snd_ens1373_spdif_info, 1484 .get = snd_ens1373_spdif_mask_get 1485 }, 1486 { 1487 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1488 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM), 1489 .info = snd_ens1373_spdif_info, 1490 .get = snd_ens1373_spdif_stream_get, 1491 .put = snd_ens1373_spdif_stream_put 1492 }, 1493 }; 1494 1495 1496 static int snd_es1373_rear_info(struct snd_kcontrol *kcontrol, 1497 struct snd_ctl_elem_info *uinfo) 1498 { 1499 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 1500 uinfo->count = 1; 1501 uinfo->value.integer.min = 0; 1502 uinfo->value.integer.max = 1; 1503 return 0; 1504 } 1505 1506 static int snd_es1373_rear_get(struct snd_kcontrol *kcontrol, 1507 struct snd_ctl_elem_value *ucontrol) 1508 { 1509 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); 1510 int val = 0; 1511 1512 spin_lock_irq(&ensoniq->reg_lock); 1513 if ((ensoniq->cssr & (ES_1373_REAR_BIT27|ES_1373_REAR_BIT26| 1514 ES_1373_REAR_BIT24)) == ES_1373_REAR_BIT26) 1515 val = 1; 1516 ucontrol->value.integer.value[0] = val; 1517 spin_unlock_irq(&ensoniq->reg_lock); 1518 return 0; 1519 } 1520 1521 static int snd_es1373_rear_put(struct snd_kcontrol *kcontrol, 1522 struct snd_ctl_elem_value *ucontrol) 1523 { 1524 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); 1525 unsigned int nval1; 1526 int change; 1527 1528 nval1 = ucontrol->value.integer.value[0] ? 1529 ES_1373_REAR_BIT26 : (ES_1373_REAR_BIT27|ES_1373_REAR_BIT24); 1530 spin_lock_irq(&ensoniq->reg_lock); 1531 change = (ensoniq->cssr & (ES_1373_REAR_BIT27| 1532 ES_1373_REAR_BIT26|ES_1373_REAR_BIT24)) != nval1; 1533 ensoniq->cssr &= ~(ES_1373_REAR_BIT27|ES_1373_REAR_BIT26|ES_1373_REAR_BIT24); 1534 ensoniq->cssr |= nval1; 1535 outl(ensoniq->cssr, ES_REG(ensoniq, STATUS)); 1536 spin_unlock_irq(&ensoniq->reg_lock); 1537 return change; 1538 } 1539 1540 static struct snd_kcontrol_new snd_ens1373_rear __devinitdata = 1541 { 1542 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 1543 .name = "AC97 2ch->4ch Copy Switch", 1544 .info = snd_es1373_rear_info, 1545 .get = snd_es1373_rear_get, 1546 .put = snd_es1373_rear_put, 1547 }; 1548 1549 static int snd_es1373_line_info(struct snd_kcontrol *kcontrol, 1550 struct snd_ctl_elem_info *uinfo) 1551 { 1552 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 1553 uinfo->count = 1; 1554 uinfo->value.integer.min = 0; 1555 uinfo->value.integer.max = 1; 1556 return 0; 1557 } 1558 1559 static int snd_es1373_line_get(struct snd_kcontrol *kcontrol, 1560 struct snd_ctl_elem_value *ucontrol) 1561 { 1562 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); 1563 int val = 0; 1564 1565 spin_lock_irq(&ensoniq->reg_lock); 1566 if ((ensoniq->ctrl & ES_1371_GPIO_OUTM) >= 4) 1567 val = 1; 1568 ucontrol->value.integer.value[0] = val; 1569 spin_unlock_irq(&ensoniq->reg_lock); 1570 return 0; 1571 } 1572 1573 static int snd_es1373_line_put(struct snd_kcontrol *kcontrol, 1574 struct snd_ctl_elem_value *ucontrol) 1575 { 1576 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); 1577 int changed; 1578 unsigned int ctrl; 1579 1580 spin_lock_irq(&ensoniq->reg_lock); 1581 ctrl = ensoniq->ctrl; 1582 if (ucontrol->value.integer.value[0]) 1583 ensoniq->ctrl |= ES_1371_GPIO_OUT(4); /* switch line-in -> rear out */ 1584 else 1585 ensoniq->ctrl &= ~ES_1371_GPIO_OUT(4); 1586 changed = (ctrl != ensoniq->ctrl); 1587 if (changed) 1588 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 1589 spin_unlock_irq(&ensoniq->reg_lock); 1590 return changed; 1591 } 1592 1593 static struct snd_kcontrol_new snd_ens1373_line __devinitdata = 1594 { 1595 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 1596 .name = "Line In->Rear Out Switch", 1597 .info = snd_es1373_line_info, 1598 .get = snd_es1373_line_get, 1599 .put = snd_es1373_line_put, 1600 }; 1601 1602 static void snd_ensoniq_mixer_free_ac97(struct snd_ac97 *ac97) 1603 { 1604 struct ensoniq *ensoniq = ac97->private_data; 1605 ensoniq->u.es1371.ac97 = NULL; 1606 } 1607 1608 struct es1371_quirk { 1609 unsigned short vid; /* vendor ID */ 1610 unsigned short did; /* device ID */ 1611 unsigned char rev; /* revision */ 1612 }; 1613 1614 static int __devinit es1371_quirk_lookup(struct ensoniq *ensoniq, 1615 struct es1371_quirk *list) 1616 { 1617 while (list->vid != (unsigned short)PCI_ANY_ID) { 1618 if (ensoniq->pci->vendor == list->vid && 1619 ensoniq->pci->device == list->did && 1620 ensoniq->rev == list->rev) 1621 return 1; 1622 list++; 1623 } 1624 return 0; 1625 } 1626 1627 static struct es1371_quirk es1371_spdif_present[] __devinitdata = { 1628 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_C }, 1629 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_D }, 1630 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_E }, 1631 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_CT5880_A }, 1632 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_ES1373_8 }, 1633 { .vid = PCI_ANY_ID, .did = PCI_ANY_ID } 1634 }; 1635 1636 static struct snd_pci_quirk ens1373_line_quirk[] __devinitdata = { 1637 SND_PCI_QUIRK_ID(0x1274, 0x2000), /* GA-7DXR */ 1638 SND_PCI_QUIRK_ID(0x1458, 0xa000), /* GA-8IEXP */ 1639 { } /* end */ 1640 }; 1641 1642 static int __devinit snd_ensoniq_1371_mixer(struct ensoniq *ensoniq, 1643 int has_spdif, int has_line) 1644 { 1645 struct snd_card *card = ensoniq->card; 1646 struct snd_ac97_bus *pbus; 1647 struct snd_ac97_template ac97; 1648 int err; 1649 static struct snd_ac97_bus_ops ops = { 1650 .write = snd_es1371_codec_write, 1651 .read = snd_es1371_codec_read, 1652 .wait = snd_es1371_codec_wait, 1653 }; 1654 1655 if ((err = snd_ac97_bus(card, 0, &ops, NULL, &pbus)) < 0) 1656 return err; 1657 1658 memset(&ac97, 0, sizeof(ac97)); 1659 ac97.private_data = ensoniq; 1660 ac97.private_free = snd_ensoniq_mixer_free_ac97; 1661 ac97.scaps = AC97_SCAP_AUDIO; 1662 if ((err = snd_ac97_mixer(pbus, &ac97, &ensoniq->u.es1371.ac97)) < 0) 1663 return err; 1664 if (has_spdif > 0 || 1665 (!has_spdif && es1371_quirk_lookup(ensoniq, es1371_spdif_present))) { 1666 struct snd_kcontrol *kctl; 1667 int i, index = 0; 1668 1669 ensoniq->spdif_default = ensoniq->spdif_stream = 1670 SNDRV_PCM_DEFAULT_CON_SPDIF; 1671 outl(ensoniq->spdif_default, ES_REG(ensoniq, CHANNEL_STATUS)); 1672 1673 if (ensoniq->u.es1371.ac97->ext_id & AC97_EI_SPDIF) 1674 index++; 1675 1676 for (i = 0; i < ARRAY_SIZE(snd_es1371_mixer_spdif); i++) { 1677 kctl = snd_ctl_new1(&snd_es1371_mixer_spdif[i], ensoniq); 1678 if (!kctl) 1679 return -ENOMEM; 1680 kctl->id.index = index; 1681 err = snd_ctl_add(card, kctl); 1682 if (err < 0) 1683 return err; 1684 } 1685 } 1686 if (ensoniq->u.es1371.ac97->ext_id & AC97_EI_SDAC) { 1687 /* mirror rear to front speakers */ 1688 ensoniq->cssr &= ~(ES_1373_REAR_BIT27|ES_1373_REAR_BIT24); 1689 ensoniq->cssr |= ES_1373_REAR_BIT26; 1690 err = snd_ctl_add(card, snd_ctl_new1(&snd_ens1373_rear, ensoniq)); 1691 if (err < 0) 1692 return err; 1693 } 1694 if (has_line > 0 || 1695 snd_pci_quirk_lookup(ensoniq->pci, ens1373_line_quirk)) { 1696 err = snd_ctl_add(card, snd_ctl_new1(&snd_ens1373_line, 1697 ensoniq)); 1698 if (err < 0) 1699 return err; 1700 } 1701 1702 return 0; 1703 } 1704 1705 #endif /* CHIP1371 */ 1706 1707 /* generic control callbacks for ens1370 */ 1708 #ifdef CHIP1370 1709 #define ENSONIQ_CONTROL(xname, mask) \ 1710 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, .name = xname, .info = snd_ensoniq_control_info, \ 1711 .get = snd_ensoniq_control_get, .put = snd_ensoniq_control_put, \ 1712 .private_value = mask } 1713 1714 static int snd_ensoniq_control_info(struct snd_kcontrol *kcontrol, 1715 struct snd_ctl_elem_info *uinfo) 1716 { 1717 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 1718 uinfo->count = 1; 1719 uinfo->value.integer.min = 0; 1720 uinfo->value.integer.max = 1; 1721 return 0; 1722 } 1723 1724 static int snd_ensoniq_control_get(struct snd_kcontrol *kcontrol, 1725 struct snd_ctl_elem_value *ucontrol) 1726 { 1727 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); 1728 int mask = kcontrol->private_value; 1729 1730 spin_lock_irq(&ensoniq->reg_lock); 1731 ucontrol->value.integer.value[0] = ensoniq->ctrl & mask ? 1 : 0; 1732 spin_unlock_irq(&ensoniq->reg_lock); 1733 return 0; 1734 } 1735 1736 static int snd_ensoniq_control_put(struct snd_kcontrol *kcontrol, 1737 struct snd_ctl_elem_value *ucontrol) 1738 { 1739 struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol); 1740 int mask = kcontrol->private_value; 1741 unsigned int nval; 1742 int change; 1743 1744 nval = ucontrol->value.integer.value[0] ? mask : 0; 1745 spin_lock_irq(&ensoniq->reg_lock); 1746 change = (ensoniq->ctrl & mask) != nval; 1747 ensoniq->ctrl &= ~mask; 1748 ensoniq->ctrl |= nval; 1749 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 1750 spin_unlock_irq(&ensoniq->reg_lock); 1751 return change; 1752 } 1753 1754 /* 1755 * ENS1370 mixer 1756 */ 1757 1758 static struct snd_kcontrol_new snd_es1370_controls[2] __devinitdata = { 1759 ENSONIQ_CONTROL("PCM 0 Output also on Line-In Jack", ES_1370_XCTL0), 1760 ENSONIQ_CONTROL("Mic +5V bias", ES_1370_XCTL1) 1761 }; 1762 1763 #define ES1370_CONTROLS ARRAY_SIZE(snd_es1370_controls) 1764 1765 static void snd_ensoniq_mixer_free_ak4531(struct snd_ak4531 *ak4531) 1766 { 1767 struct ensoniq *ensoniq = ak4531->private_data; 1768 ensoniq->u.es1370.ak4531 = NULL; 1769 } 1770 1771 static int __devinit snd_ensoniq_1370_mixer(struct ensoniq * ensoniq) 1772 { 1773 struct snd_card *card = ensoniq->card; 1774 struct snd_ak4531 ak4531; 1775 unsigned int idx; 1776 int err; 1777 1778 /* try reset AK4531 */ 1779 outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x02), ES_REG(ensoniq, 1370_CODEC)); 1780 inw(ES_REG(ensoniq, 1370_CODEC)); 1781 udelay(100); 1782 outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x03), ES_REG(ensoniq, 1370_CODEC)); 1783 inw(ES_REG(ensoniq, 1370_CODEC)); 1784 udelay(100); 1785 1786 memset(&ak4531, 0, sizeof(ak4531)); 1787 ak4531.write = snd_es1370_codec_write; 1788 ak4531.private_data = ensoniq; 1789 ak4531.private_free = snd_ensoniq_mixer_free_ak4531; 1790 if ((err = snd_ak4531_mixer(card, &ak4531, &ensoniq->u.es1370.ak4531)) < 0) 1791 return err; 1792 for (idx = 0; idx < ES1370_CONTROLS; idx++) { 1793 err = snd_ctl_add(card, snd_ctl_new1(&snd_es1370_controls[idx], ensoniq)); 1794 if (err < 0) 1795 return err; 1796 } 1797 return 0; 1798 } 1799 1800 #endif /* CHIP1370 */ 1801 1802 #ifdef SUPPORT_JOYSTICK 1803 1804 #ifdef CHIP1371 1805 static int __devinit snd_ensoniq_get_joystick_port(int dev) 1806 { 1807 switch (joystick_port[dev]) { 1808 case 0: /* disabled */ 1809 case 1: /* auto-detect */ 1810 case 0x200: 1811 case 0x208: 1812 case 0x210: 1813 case 0x218: 1814 return joystick_port[dev]; 1815 1816 default: 1817 printk(KERN_ERR "ens1371: invalid joystick port %#x", joystick_port[dev]); 1818 return 0; 1819 } 1820 } 1821 #else 1822 static inline int snd_ensoniq_get_joystick_port(int dev) 1823 { 1824 return joystick[dev] ? 0x200 : 0; 1825 } 1826 #endif 1827 1828 static int __devinit snd_ensoniq_create_gameport(struct ensoniq *ensoniq, int dev) 1829 { 1830 struct gameport *gp; 1831 int io_port; 1832 1833 io_port = snd_ensoniq_get_joystick_port(dev); 1834 1835 switch (io_port) { 1836 case 0: 1837 return -ENOSYS; 1838 1839 case 1: /* auto_detect */ 1840 for (io_port = 0x200; io_port <= 0x218; io_port += 8) 1841 if (request_region(io_port, 8, "ens137x: gameport")) 1842 break; 1843 if (io_port > 0x218) { 1844 printk(KERN_WARNING "ens137x: no gameport ports available\n"); 1845 return -EBUSY; 1846 } 1847 break; 1848 1849 default: 1850 if (!request_region(io_port, 8, "ens137x: gameport")) { 1851 printk(KERN_WARNING "ens137x: gameport io port 0x%#x in use\n", 1852 io_port); 1853 return -EBUSY; 1854 } 1855 break; 1856 } 1857 1858 ensoniq->gameport = gp = gameport_allocate_port(); 1859 if (!gp) { 1860 printk(KERN_ERR "ens137x: cannot allocate memory for gameport\n"); 1861 release_region(io_port, 8); 1862 return -ENOMEM; 1863 } 1864 1865 gameport_set_name(gp, "ES137x"); 1866 gameport_set_phys(gp, "pci%s/gameport0", pci_name(ensoniq->pci)); 1867 gameport_set_dev_parent(gp, &ensoniq->pci->dev); 1868 gp->io = io_port; 1869 1870 ensoniq->ctrl |= ES_JYSTK_EN; 1871 #ifdef CHIP1371 1872 ensoniq->ctrl &= ~ES_1371_JOY_ASELM; 1873 ensoniq->ctrl |= ES_1371_JOY_ASEL((io_port - 0x200) / 8); 1874 #endif 1875 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 1876 1877 gameport_register_port(ensoniq->gameport); 1878 1879 return 0; 1880 } 1881 1882 static void snd_ensoniq_free_gameport(struct ensoniq *ensoniq) 1883 { 1884 if (ensoniq->gameport) { 1885 int port = ensoniq->gameport->io; 1886 1887 gameport_unregister_port(ensoniq->gameport); 1888 ensoniq->gameport = NULL; 1889 ensoniq->ctrl &= ~ES_JYSTK_EN; 1890 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 1891 release_region(port, 8); 1892 } 1893 } 1894 #else 1895 static inline int snd_ensoniq_create_gameport(struct ensoniq *ensoniq, long port) { return -ENOSYS; } 1896 static inline void snd_ensoniq_free_gameport(struct ensoniq *ensoniq) { } 1897 #endif /* SUPPORT_JOYSTICK */ 1898 1899 /* 1900 1901 */ 1902 1903 static void snd_ensoniq_proc_read(struct snd_info_entry *entry, 1904 struct snd_info_buffer *buffer) 1905 { 1906 struct ensoniq *ensoniq = entry->private_data; 1907 1908 #ifdef CHIP1370 1909 snd_iprintf(buffer, "Ensoniq AudioPCI ES1370\n\n"); 1910 #else 1911 snd_iprintf(buffer, "Ensoniq AudioPCI ES1371\n\n"); 1912 #endif 1913 snd_iprintf(buffer, "Joystick enable : %s\n", 1914 ensoniq->ctrl & ES_JYSTK_EN ? "on" : "off"); 1915 #ifdef CHIP1370 1916 snd_iprintf(buffer, "MIC +5V bias : %s\n", 1917 ensoniq->ctrl & ES_1370_XCTL1 ? "on" : "off"); 1918 snd_iprintf(buffer, "Line In to AOUT : %s\n", 1919 ensoniq->ctrl & ES_1370_XCTL0 ? "on" : "off"); 1920 #else 1921 snd_iprintf(buffer, "Joystick port : 0x%x\n", 1922 (ES_1371_JOY_ASELI(ensoniq->ctrl) * 8) + 0x200); 1923 #endif 1924 } 1925 1926 static void __devinit snd_ensoniq_proc_init(struct ensoniq * ensoniq) 1927 { 1928 struct snd_info_entry *entry; 1929 1930 if (! snd_card_proc_new(ensoniq->card, "audiopci", &entry)) 1931 snd_info_set_text_ops(entry, ensoniq, snd_ensoniq_proc_read); 1932 } 1933 1934 /* 1935 1936 */ 1937 1938 static int snd_ensoniq_free(struct ensoniq *ensoniq) 1939 { 1940 snd_ensoniq_free_gameport(ensoniq); 1941 if (ensoniq->irq < 0) 1942 goto __hw_end; 1943 #ifdef CHIP1370 1944 outl(ES_1370_SERR_DISABLE, ES_REG(ensoniq, CONTROL)); /* switch everything off */ 1945 outl(0, ES_REG(ensoniq, SERIAL)); /* clear serial interface */ 1946 #else 1947 outl(0, ES_REG(ensoniq, CONTROL)); /* switch everything off */ 1948 outl(0, ES_REG(ensoniq, SERIAL)); /* clear serial interface */ 1949 #endif 1950 synchronize_irq(ensoniq->irq); 1951 pci_set_power_state(ensoniq->pci, 3); 1952 __hw_end: 1953 #ifdef CHIP1370 1954 if (ensoniq->dma_bug.area) 1955 snd_dma_free_pages(&ensoniq->dma_bug); 1956 #endif 1957 if (ensoniq->irq >= 0) 1958 free_irq(ensoniq->irq, ensoniq); 1959 pci_release_regions(ensoniq->pci); 1960 pci_disable_device(ensoniq->pci); 1961 kfree(ensoniq); 1962 return 0; 1963 } 1964 1965 static int snd_ensoniq_dev_free(struct snd_device *device) 1966 { 1967 struct ensoniq *ensoniq = device->device_data; 1968 return snd_ensoniq_free(ensoniq); 1969 } 1970 1971 #ifdef CHIP1371 1972 static struct snd_pci_quirk es1371_amplifier_hack[] __devinitdata = { 1973 SND_PCI_QUIRK_ID(0x107b, 0x2150), /* Gateway Solo 2150 */ 1974 SND_PCI_QUIRK_ID(0x13bd, 0x100c), /* EV1938 on Mebius PC-MJ100V */ 1975 SND_PCI_QUIRK_ID(0x1102, 0x5938), /* Targa Xtender300 */ 1976 SND_PCI_QUIRK_ID(0x1102, 0x8938), /* IPC Topnote G notebook */ 1977 { } /* end */ 1978 }; 1979 1980 static struct es1371_quirk es1371_ac97_reset_hack[] = { 1981 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_C }, 1982 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_D }, 1983 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_E }, 1984 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_CT5880_A }, 1985 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_ES1373_8 }, 1986 { .vid = PCI_ANY_ID, .did = PCI_ANY_ID } 1987 }; 1988 #endif 1989 1990 static void snd_ensoniq_chip_init(struct ensoniq *ensoniq) 1991 { 1992 #ifdef CHIP1371 1993 int idx; 1994 #endif 1995 /* this code was part of snd_ensoniq_create before intruduction 1996 * of suspend/resume 1997 */ 1998 #ifdef CHIP1370 1999 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 2000 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL)); 2001 outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE)); 2002 outl(ensoniq->dma_bug.addr, ES_REG(ensoniq, PHANTOM_FRAME)); 2003 outl(0, ES_REG(ensoniq, PHANTOM_COUNT)); 2004 #else 2005 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 2006 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL)); 2007 outl(0, ES_REG(ensoniq, 1371_LEGACY)); 2008 if (es1371_quirk_lookup(ensoniq, es1371_ac97_reset_hack)) { 2009 outl(ensoniq->cssr, ES_REG(ensoniq, STATUS)); 2010 /* need to delay around 20ms(bleech) to give 2011 some CODECs enough time to wakeup */ 2012 msleep(20); 2013 } 2014 /* AC'97 warm reset to start the bitclk */ 2015 outl(ensoniq->ctrl | ES_1371_SYNC_RES, ES_REG(ensoniq, CONTROL)); 2016 inl(ES_REG(ensoniq, CONTROL)); 2017 udelay(20); 2018 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 2019 /* Init the sample rate converter */ 2020 snd_es1371_wait_src_ready(ensoniq); 2021 outl(ES_1371_SRC_DISABLE, ES_REG(ensoniq, 1371_SMPRATE)); 2022 for (idx = 0; idx < 0x80; idx++) 2023 snd_es1371_src_write(ensoniq, idx, 0); 2024 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_TRUNC_N, 16 << 4); 2025 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS, 16 << 10); 2026 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_TRUNC_N, 16 << 4); 2027 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS, 16 << 10); 2028 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC, 1 << 12); 2029 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC + 1, 1 << 12); 2030 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC1, 1 << 12); 2031 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC1 + 1, 1 << 12); 2032 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC2, 1 << 12); 2033 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC2 + 1, 1 << 12); 2034 snd_es1371_adc_rate(ensoniq, 22050); 2035 snd_es1371_dac1_rate(ensoniq, 22050); 2036 snd_es1371_dac2_rate(ensoniq, 22050); 2037 /* WARNING: 2038 * enabling the sample rate converter without properly programming 2039 * its parameters causes the chip to lock up (the SRC busy bit will 2040 * be stuck high, and I've found no way to rectify this other than 2041 * power cycle) - Thomas Sailer 2042 */ 2043 snd_es1371_wait_src_ready(ensoniq); 2044 outl(0, ES_REG(ensoniq, 1371_SMPRATE)); 2045 /* try reset codec directly */ 2046 outl(ES_1371_CODEC_WRITE(0, 0), ES_REG(ensoniq, 1371_CODEC)); 2047 #endif 2048 outb(ensoniq->uartc = 0x00, ES_REG(ensoniq, UART_CONTROL)); 2049 outb(0x00, ES_REG(ensoniq, UART_RES)); 2050 outl(ensoniq->cssr, ES_REG(ensoniq, STATUS)); 2051 synchronize_irq(ensoniq->irq); 2052 } 2053 2054 #ifdef CONFIG_PM 2055 static int snd_ensoniq_suspend(struct pci_dev *pci, pm_message_t state) 2056 { 2057 struct snd_card *card = pci_get_drvdata(pci); 2058 struct ensoniq *ensoniq = card->private_data; 2059 2060 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 2061 2062 snd_pcm_suspend_all(ensoniq->pcm1); 2063 snd_pcm_suspend_all(ensoniq->pcm2); 2064 2065 #ifdef CHIP1371 2066 snd_ac97_suspend(ensoniq->u.es1371.ac97); 2067 #else 2068 /* try to reset AK4531 */ 2069 outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x02), ES_REG(ensoniq, 1370_CODEC)); 2070 inw(ES_REG(ensoniq, 1370_CODEC)); 2071 udelay(100); 2072 outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x03), ES_REG(ensoniq, 1370_CODEC)); 2073 inw(ES_REG(ensoniq, 1370_CODEC)); 2074 udelay(100); 2075 snd_ak4531_suspend(ensoniq->u.es1370.ak4531); 2076 #endif 2077 2078 pci_disable_device(pci); 2079 pci_save_state(pci); 2080 pci_set_power_state(pci, pci_choose_state(pci, state)); 2081 return 0; 2082 } 2083 2084 static int snd_ensoniq_resume(struct pci_dev *pci) 2085 { 2086 struct snd_card *card = pci_get_drvdata(pci); 2087 struct ensoniq *ensoniq = card->private_data; 2088 2089 pci_set_power_state(pci, PCI_D0); 2090 pci_restore_state(pci); 2091 if (pci_enable_device(pci) < 0) { 2092 printk(KERN_ERR DRIVER_NAME ": pci_enable_device failed, " 2093 "disabling device\n"); 2094 snd_card_disconnect(card); 2095 return -EIO; 2096 } 2097 pci_set_master(pci); 2098 2099 snd_ensoniq_chip_init(ensoniq); 2100 2101 #ifdef CHIP1371 2102 snd_ac97_resume(ensoniq->u.es1371.ac97); 2103 #else 2104 snd_ak4531_resume(ensoniq->u.es1370.ak4531); 2105 #endif 2106 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 2107 return 0; 2108 } 2109 #endif /* CONFIG_PM */ 2110 2111 2112 static int __devinit snd_ensoniq_create(struct snd_card *card, 2113 struct pci_dev *pci, 2114 struct ensoniq ** rensoniq) 2115 { 2116 struct ensoniq *ensoniq; 2117 unsigned char cmdb; 2118 int err; 2119 static struct snd_device_ops ops = { 2120 .dev_free = snd_ensoniq_dev_free, 2121 }; 2122 2123 *rensoniq = NULL; 2124 if ((err = pci_enable_device(pci)) < 0) 2125 return err; 2126 ensoniq = kzalloc(sizeof(*ensoniq), GFP_KERNEL); 2127 if (ensoniq == NULL) { 2128 pci_disable_device(pci); 2129 return -ENOMEM; 2130 } 2131 spin_lock_init(&ensoniq->reg_lock); 2132 mutex_init(&ensoniq->src_mutex); 2133 ensoniq->card = card; 2134 ensoniq->pci = pci; 2135 ensoniq->irq = -1; 2136 if ((err = pci_request_regions(pci, "Ensoniq AudioPCI")) < 0) { 2137 kfree(ensoniq); 2138 pci_disable_device(pci); 2139 return err; 2140 } 2141 ensoniq->port = pci_resource_start(pci, 0); 2142 if (request_irq(pci->irq, snd_audiopci_interrupt, IRQF_SHARED, 2143 "Ensoniq AudioPCI", ensoniq)) { 2144 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq); 2145 snd_ensoniq_free(ensoniq); 2146 return -EBUSY; 2147 } 2148 ensoniq->irq = pci->irq; 2149 #ifdef CHIP1370 2150 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci), 2151 16, &ensoniq->dma_bug) < 0) { 2152 snd_printk(KERN_ERR "unable to allocate space for phantom area - dma_bug\n"); 2153 snd_ensoniq_free(ensoniq); 2154 return -EBUSY; 2155 } 2156 #endif 2157 pci_set_master(pci); 2158 pci_read_config_byte(pci, PCI_REVISION_ID, &cmdb); 2159 ensoniq->rev = cmdb; 2160 #ifdef CHIP1370 2161 #if 0 2162 ensoniq->ctrl = ES_1370_CDC_EN | ES_1370_SERR_DISABLE | 2163 ES_1370_PCLKDIVO(ES_1370_SRTODIV(8000)); 2164 #else /* get microphone working */ 2165 ensoniq->ctrl = ES_1370_CDC_EN | ES_1370_PCLKDIVO(ES_1370_SRTODIV(8000)); 2166 #endif 2167 ensoniq->sctrl = 0; 2168 #else 2169 ensoniq->ctrl = 0; 2170 ensoniq->sctrl = 0; 2171 ensoniq->cssr = 0; 2172 if (snd_pci_quirk_lookup(pci, es1371_amplifier_hack)) 2173 ensoniq->ctrl |= ES_1371_GPIO_OUT(1); /* turn amplifier on */ 2174 2175 if (es1371_quirk_lookup(ensoniq, es1371_ac97_reset_hack)) 2176 ensoniq->cssr |= ES_1371_ST_AC97_RST; 2177 #endif 2178 2179 snd_ensoniq_chip_init(ensoniq); 2180 2181 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, ensoniq, &ops)) < 0) { 2182 snd_ensoniq_free(ensoniq); 2183 return err; 2184 } 2185 2186 snd_ensoniq_proc_init(ensoniq); 2187 2188 snd_card_set_dev(card, &pci->dev); 2189 2190 *rensoniq = ensoniq; 2191 return 0; 2192 } 2193 2194 /* 2195 * MIDI section 2196 */ 2197 2198 static void snd_ensoniq_midi_interrupt(struct ensoniq * ensoniq) 2199 { 2200 struct snd_rawmidi *rmidi = ensoniq->rmidi; 2201 unsigned char status, mask, byte; 2202 2203 if (rmidi == NULL) 2204 return; 2205 /* do Rx at first */ 2206 spin_lock(&ensoniq->reg_lock); 2207 mask = ensoniq->uartm & ES_MODE_INPUT ? ES_RXRDY : 0; 2208 while (mask) { 2209 status = inb(ES_REG(ensoniq, UART_STATUS)); 2210 if ((status & mask) == 0) 2211 break; 2212 byte = inb(ES_REG(ensoniq, UART_DATA)); 2213 snd_rawmidi_receive(ensoniq->midi_input, &byte, 1); 2214 } 2215 spin_unlock(&ensoniq->reg_lock); 2216 2217 /* do Tx at second */ 2218 spin_lock(&ensoniq->reg_lock); 2219 mask = ensoniq->uartm & ES_MODE_OUTPUT ? ES_TXRDY : 0; 2220 while (mask) { 2221 status = inb(ES_REG(ensoniq, UART_STATUS)); 2222 if ((status & mask) == 0) 2223 break; 2224 if (snd_rawmidi_transmit(ensoniq->midi_output, &byte, 1) != 1) { 2225 ensoniq->uartc &= ~ES_TXINTENM; 2226 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL)); 2227 mask &= ~ES_TXRDY; 2228 } else { 2229 outb(byte, ES_REG(ensoniq, UART_DATA)); 2230 } 2231 } 2232 spin_unlock(&ensoniq->reg_lock); 2233 } 2234 2235 static int snd_ensoniq_midi_input_open(struct snd_rawmidi_substream *substream) 2236 { 2237 struct ensoniq *ensoniq = substream->rmidi->private_data; 2238 2239 spin_lock_irq(&ensoniq->reg_lock); 2240 ensoniq->uartm |= ES_MODE_INPUT; 2241 ensoniq->midi_input = substream; 2242 if (!(ensoniq->uartm & ES_MODE_OUTPUT)) { 2243 outb(ES_CNTRL(3), ES_REG(ensoniq, UART_CONTROL)); 2244 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL)); 2245 outl(ensoniq->ctrl |= ES_UART_EN, ES_REG(ensoniq, CONTROL)); 2246 } 2247 spin_unlock_irq(&ensoniq->reg_lock); 2248 return 0; 2249 } 2250 2251 static int snd_ensoniq_midi_input_close(struct snd_rawmidi_substream *substream) 2252 { 2253 struct ensoniq *ensoniq = substream->rmidi->private_data; 2254 2255 spin_lock_irq(&ensoniq->reg_lock); 2256 if (!(ensoniq->uartm & ES_MODE_OUTPUT)) { 2257 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL)); 2258 outl(ensoniq->ctrl &= ~ES_UART_EN, ES_REG(ensoniq, CONTROL)); 2259 } else { 2260 outb(ensoniq->uartc &= ~ES_RXINTEN, ES_REG(ensoniq, UART_CONTROL)); 2261 } 2262 ensoniq->midi_input = NULL; 2263 ensoniq->uartm &= ~ES_MODE_INPUT; 2264 spin_unlock_irq(&ensoniq->reg_lock); 2265 return 0; 2266 } 2267 2268 static int snd_ensoniq_midi_output_open(struct snd_rawmidi_substream *substream) 2269 { 2270 struct ensoniq *ensoniq = substream->rmidi->private_data; 2271 2272 spin_lock_irq(&ensoniq->reg_lock); 2273 ensoniq->uartm |= ES_MODE_OUTPUT; 2274 ensoniq->midi_output = substream; 2275 if (!(ensoniq->uartm & ES_MODE_INPUT)) { 2276 outb(ES_CNTRL(3), ES_REG(ensoniq, UART_CONTROL)); 2277 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL)); 2278 outl(ensoniq->ctrl |= ES_UART_EN, ES_REG(ensoniq, CONTROL)); 2279 } 2280 spin_unlock_irq(&ensoniq->reg_lock); 2281 return 0; 2282 } 2283 2284 static int snd_ensoniq_midi_output_close(struct snd_rawmidi_substream *substream) 2285 { 2286 struct ensoniq *ensoniq = substream->rmidi->private_data; 2287 2288 spin_lock_irq(&ensoniq->reg_lock); 2289 if (!(ensoniq->uartm & ES_MODE_INPUT)) { 2290 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL)); 2291 outl(ensoniq->ctrl &= ~ES_UART_EN, ES_REG(ensoniq, CONTROL)); 2292 } else { 2293 outb(ensoniq->uartc &= ~ES_TXINTENM, ES_REG(ensoniq, UART_CONTROL)); 2294 } 2295 ensoniq->midi_output = NULL; 2296 ensoniq->uartm &= ~ES_MODE_OUTPUT; 2297 spin_unlock_irq(&ensoniq->reg_lock); 2298 return 0; 2299 } 2300 2301 static void snd_ensoniq_midi_input_trigger(struct snd_rawmidi_substream *substream, int up) 2302 { 2303 unsigned long flags; 2304 struct ensoniq *ensoniq = substream->rmidi->private_data; 2305 int idx; 2306 2307 spin_lock_irqsave(&ensoniq->reg_lock, flags); 2308 if (up) { 2309 if ((ensoniq->uartc & ES_RXINTEN) == 0) { 2310 /* empty input FIFO */ 2311 for (idx = 0; idx < 32; idx++) 2312 inb(ES_REG(ensoniq, UART_DATA)); 2313 ensoniq->uartc |= ES_RXINTEN; 2314 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL)); 2315 } 2316 } else { 2317 if (ensoniq->uartc & ES_RXINTEN) { 2318 ensoniq->uartc &= ~ES_RXINTEN; 2319 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL)); 2320 } 2321 } 2322 spin_unlock_irqrestore(&ensoniq->reg_lock, flags); 2323 } 2324 2325 static void snd_ensoniq_midi_output_trigger(struct snd_rawmidi_substream *substream, int up) 2326 { 2327 unsigned long flags; 2328 struct ensoniq *ensoniq = substream->rmidi->private_data; 2329 unsigned char byte; 2330 2331 spin_lock_irqsave(&ensoniq->reg_lock, flags); 2332 if (up) { 2333 if (ES_TXINTENI(ensoniq->uartc) == 0) { 2334 ensoniq->uartc |= ES_TXINTENO(1); 2335 /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */ 2336 while (ES_TXINTENI(ensoniq->uartc) == 1 && 2337 (inb(ES_REG(ensoniq, UART_STATUS)) & ES_TXRDY)) { 2338 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) { 2339 ensoniq->uartc &= ~ES_TXINTENM; 2340 } else { 2341 outb(byte, ES_REG(ensoniq, UART_DATA)); 2342 } 2343 } 2344 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL)); 2345 } 2346 } else { 2347 if (ES_TXINTENI(ensoniq->uartc) == 1) { 2348 ensoniq->uartc &= ~ES_TXINTENM; 2349 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL)); 2350 } 2351 } 2352 spin_unlock_irqrestore(&ensoniq->reg_lock, flags); 2353 } 2354 2355 static struct snd_rawmidi_ops snd_ensoniq_midi_output = 2356 { 2357 .open = snd_ensoniq_midi_output_open, 2358 .close = snd_ensoniq_midi_output_close, 2359 .trigger = snd_ensoniq_midi_output_trigger, 2360 }; 2361 2362 static struct snd_rawmidi_ops snd_ensoniq_midi_input = 2363 { 2364 .open = snd_ensoniq_midi_input_open, 2365 .close = snd_ensoniq_midi_input_close, 2366 .trigger = snd_ensoniq_midi_input_trigger, 2367 }; 2368 2369 static int __devinit snd_ensoniq_midi(struct ensoniq * ensoniq, int device, 2370 struct snd_rawmidi **rrawmidi) 2371 { 2372 struct snd_rawmidi *rmidi; 2373 int err; 2374 2375 if (rrawmidi) 2376 *rrawmidi = NULL; 2377 if ((err = snd_rawmidi_new(ensoniq->card, "ES1370/1", device, 1, 1, &rmidi)) < 0) 2378 return err; 2379 #ifdef CHIP1370 2380 strcpy(rmidi->name, "ES1370"); 2381 #else 2382 strcpy(rmidi->name, "ES1371"); 2383 #endif 2384 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_ensoniq_midi_output); 2385 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_ensoniq_midi_input); 2386 rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | 2387 SNDRV_RAWMIDI_INFO_DUPLEX; 2388 rmidi->private_data = ensoniq; 2389 ensoniq->rmidi = rmidi; 2390 if (rrawmidi) 2391 *rrawmidi = rmidi; 2392 return 0; 2393 } 2394 2395 /* 2396 * Interrupt handler 2397 */ 2398 2399 static irqreturn_t snd_audiopci_interrupt(int irq, void *dev_id) 2400 { 2401 struct ensoniq *ensoniq = dev_id; 2402 unsigned int status, sctrl; 2403 2404 if (ensoniq == NULL) 2405 return IRQ_NONE; 2406 2407 status = inl(ES_REG(ensoniq, STATUS)); 2408 if (!(status & ES_INTR)) 2409 return IRQ_NONE; 2410 2411 spin_lock(&ensoniq->reg_lock); 2412 sctrl = ensoniq->sctrl; 2413 if (status & ES_DAC1) 2414 sctrl &= ~ES_P1_INT_EN; 2415 if (status & ES_DAC2) 2416 sctrl &= ~ES_P2_INT_EN; 2417 if (status & ES_ADC) 2418 sctrl &= ~ES_R1_INT_EN; 2419 outl(sctrl, ES_REG(ensoniq, SERIAL)); 2420 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL)); 2421 spin_unlock(&ensoniq->reg_lock); 2422 2423 if (status & ES_UART) 2424 snd_ensoniq_midi_interrupt(ensoniq); 2425 if ((status & ES_DAC2) && ensoniq->playback2_substream) 2426 snd_pcm_period_elapsed(ensoniq->playback2_substream); 2427 if ((status & ES_ADC) && ensoniq->capture_substream) 2428 snd_pcm_period_elapsed(ensoniq->capture_substream); 2429 if ((status & ES_DAC1) && ensoniq->playback1_substream) 2430 snd_pcm_period_elapsed(ensoniq->playback1_substream); 2431 return IRQ_HANDLED; 2432 } 2433 2434 static int __devinit snd_audiopci_probe(struct pci_dev *pci, 2435 const struct pci_device_id *pci_id) 2436 { 2437 static int dev; 2438 struct snd_card *card; 2439 struct ensoniq *ensoniq; 2440 int err, pcm_devs[2]; 2441 2442 if (dev >= SNDRV_CARDS) 2443 return -ENODEV; 2444 if (!enable[dev]) { 2445 dev++; 2446 return -ENOENT; 2447 } 2448 2449 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0); 2450 if (card == NULL) 2451 return -ENOMEM; 2452 2453 if ((err = snd_ensoniq_create(card, pci, &ensoniq)) < 0) { 2454 snd_card_free(card); 2455 return err; 2456 } 2457 card->private_data = ensoniq; 2458 2459 pcm_devs[0] = 0; pcm_devs[1] = 1; 2460 #ifdef CHIP1370 2461 if ((err = snd_ensoniq_1370_mixer(ensoniq)) < 0) { 2462 snd_card_free(card); 2463 return err; 2464 } 2465 #endif 2466 #ifdef CHIP1371 2467 if ((err = snd_ensoniq_1371_mixer(ensoniq, spdif[dev], lineio[dev])) < 0) { 2468 snd_card_free(card); 2469 return err; 2470 } 2471 #endif 2472 if ((err = snd_ensoniq_pcm(ensoniq, 0, NULL)) < 0) { 2473 snd_card_free(card); 2474 return err; 2475 } 2476 if ((err = snd_ensoniq_pcm2(ensoniq, 1, NULL)) < 0) { 2477 snd_card_free(card); 2478 return err; 2479 } 2480 if ((err = snd_ensoniq_midi(ensoniq, 0, NULL)) < 0) { 2481 snd_card_free(card); 2482 return err; 2483 } 2484 2485 snd_ensoniq_create_gameport(ensoniq, dev); 2486 2487 strcpy(card->driver, DRIVER_NAME); 2488 2489 strcpy(card->shortname, "Ensoniq AudioPCI"); 2490 sprintf(card->longname, "%s %s at 0x%lx, irq %i", 2491 card->shortname, 2492 card->driver, 2493 ensoniq->port, 2494 ensoniq->irq); 2495 2496 if ((err = snd_card_register(card)) < 0) { 2497 snd_card_free(card); 2498 return err; 2499 } 2500 2501 pci_set_drvdata(pci, card); 2502 dev++; 2503 return 0; 2504 } 2505 2506 static void __devexit snd_audiopci_remove(struct pci_dev *pci) 2507 { 2508 snd_card_free(pci_get_drvdata(pci)); 2509 pci_set_drvdata(pci, NULL); 2510 } 2511 2512 static struct pci_driver driver = { 2513 .name = DRIVER_NAME, 2514 .id_table = snd_audiopci_ids, 2515 .probe = snd_audiopci_probe, 2516 .remove = __devexit_p(snd_audiopci_remove), 2517 #ifdef CONFIG_PM 2518 .suspend = snd_ensoniq_suspend, 2519 .resume = snd_ensoniq_resume, 2520 #endif 2521 }; 2522 2523 static int __init alsa_card_ens137x_init(void) 2524 { 2525 return pci_register_driver(&driver); 2526 } 2527 2528 static void __exit alsa_card_ens137x_exit(void) 2529 { 2530 pci_unregister_driver(&driver); 2531 } 2532 2533 module_init(alsa_card_ens137x_init) 2534 module_exit(alsa_card_ens137x_exit) 2535