1 /* 2 * Driver for Ensoniq ES1370/ES1371 AudioPCI soundcard 3 * Copyright (c) by Jaroslav Kysela <perex@suse.cz>, 4 * Thomas Sailer <sailer@ife.ee.ethz.ch> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 19 * 20 */ 21 22 #include <sound/driver.h> 23 #include <asm/io.h> 24 #include <linux/delay.h> 25 #include <linux/interrupt.h> 26 #include <linux/init.h> 27 #include <linux/pci.h> 28 #include <linux/slab.h> 29 #include <linux/gameport.h> 30 #include <linux/moduleparam.h> 31 #include <sound/core.h> 32 #include <sound/control.h> 33 #include <sound/pcm.h> 34 #include <sound/rawmidi.h> 35 #ifdef CHIP1371 36 #include <sound/ac97_codec.h> 37 #else 38 #include <sound/ak4531_codec.h> 39 #endif 40 #include <sound/initval.h> 41 #include <sound/asoundef.h> 42 43 #ifndef CHIP1371 44 #undef CHIP1370 45 #define CHIP1370 46 #endif 47 48 #ifdef CHIP1370 49 #define DRIVER_NAME "ENS1370" 50 #else 51 #define DRIVER_NAME "ENS1371" 52 #endif 53 54 55 MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>, Thomas Sailer <sailer@ife.ee.ethz.ch>"); 56 MODULE_LICENSE("GPL"); 57 #ifdef CHIP1370 58 MODULE_DESCRIPTION("Ensoniq AudioPCI ES1370"); 59 MODULE_SUPPORTED_DEVICE("{{Ensoniq,AudioPCI-97 ES1370}," 60 "{Creative Labs,SB PCI64/128 (ES1370)}}"); 61 #endif 62 #ifdef CHIP1371 63 MODULE_DESCRIPTION("Ensoniq/Creative AudioPCI ES1371+"); 64 MODULE_SUPPORTED_DEVICE("{{Ensoniq,AudioPCI ES1371/73}," 65 "{Ensoniq,AudioPCI ES1373}," 66 "{Creative Labs,Ectiva EV1938}," 67 "{Creative Labs,SB PCI64/128 (ES1371/73)}," 68 "{Creative Labs,Vibra PCI128}," 69 "{Ectiva,EV1938}}"); 70 #endif 71 72 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE)) 73 #define SUPPORT_JOYSTICK 74 #endif 75 76 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ 77 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ 78 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable switches */ 79 #ifdef SUPPORT_JOYSTICK 80 #ifdef CHIP1371 81 static int joystick_port[SNDRV_CARDS]; 82 #else 83 static int joystick[SNDRV_CARDS]; 84 #endif 85 #endif 86 87 module_param_array(index, int, NULL, 0444); 88 MODULE_PARM_DESC(index, "Index value for Ensoniq AudioPCI soundcard."); 89 module_param_array(id, charp, NULL, 0444); 90 MODULE_PARM_DESC(id, "ID string for Ensoniq AudioPCI soundcard."); 91 module_param_array(enable, bool, NULL, 0444); 92 MODULE_PARM_DESC(enable, "Enable Ensoniq AudioPCI soundcard."); 93 #ifdef SUPPORT_JOYSTICK 94 #ifdef CHIP1371 95 module_param_array(joystick_port, int, NULL, 0444); 96 MODULE_PARM_DESC(joystick_port, "Joystick port address."); 97 #else 98 module_param_array(joystick, bool, NULL, 0444); 99 MODULE_PARM_DESC(joystick, "Enable joystick."); 100 #endif 101 #endif /* SUPPORT_JOYSTICK */ 102 103 #ifndef PCI_DEVICE_ID_ENSONIQ_CT5880 104 #define PCI_DEVICE_ID_ENSONIQ_CT5880 0x5880 105 #endif 106 #ifndef PCI_DEVICE_ID_ENSONIQ_ES1371 107 #define PCI_DEVICE_ID_ENSONIQ_ES1371 0x1371 108 #endif 109 110 /* ES1371 chip ID */ 111 /* This is a little confusing because all ES1371 compatible chips have the 112 same DEVICE_ID, the only thing differentiating them is the REV_ID field. 113 This is only significant if you want to enable features on the later parts. 114 Yes, I know it's stupid and why didn't we use the sub IDs? 115 */ 116 #define ES1371REV_ES1373_A 0x04 117 #define ES1371REV_ES1373_B 0x06 118 #define ES1371REV_CT5880_A 0x07 119 #define CT5880REV_CT5880_C 0x02 120 #define CT5880REV_CT5880_D 0x03 /* ??? -jk */ 121 #define CT5880REV_CT5880_E 0x04 /* mw */ 122 #define ES1371REV_ES1371_B 0x09 123 #define EV1938REV_EV1938_A 0x00 124 #define ES1371REV_ES1373_8 0x08 125 126 /* 127 * Direct registers 128 */ 129 130 #define ES_REG(ensoniq, x) ((ensoniq)->port + ES_REG_##x) 131 132 #define ES_REG_CONTROL 0x00 /* R/W: Interrupt/Chip select control register */ 133 #define ES_1370_ADC_STOP (1<<31) /* disable capture buffer transfers */ 134 #define ES_1370_XCTL1 (1<<30) /* general purpose output bit */ 135 #define ES_1373_BYPASS_P1 (1<<31) /* bypass SRC for PB1 */ 136 #define ES_1373_BYPASS_P2 (1<<30) /* bypass SRC for PB2 */ 137 #define ES_1373_BYPASS_R (1<<29) /* bypass SRC for REC */ 138 #define ES_1373_TEST_BIT (1<<28) /* should be set to 0 for normal operation */ 139 #define ES_1373_RECEN_B (1<<27) /* mix record with playback for I2S/SPDIF out */ 140 #define ES_1373_SPDIF_THRU (1<<26) /* 0 = SPDIF thru mode, 1 = SPDIF == dig out */ 141 #define ES_1371_JOY_ASEL(o) (((o)&0x03)<<24)/* joystick port mapping */ 142 #define ES_1371_JOY_ASELM (0x03<<24) /* mask for above */ 143 #define ES_1371_JOY_ASELI(i) (((i)>>24)&0x03) 144 #define ES_1371_GPIO_IN(i) (((i)>>20)&0x0f)/* GPIO in [3:0] pins - R/O */ 145 #define ES_1370_PCLKDIVO(o) (((o)&0x1fff)<<16)/* clock divide ratio for DAC2 */ 146 #define ES_1370_PCLKDIVM ((0x1fff)<<16) /* mask for above */ 147 #define ES_1370_PCLKDIVI(i) (((i)>>16)&0x1fff)/* clock divide ratio for DAC2 */ 148 #define ES_1371_GPIO_OUT(o) (((o)&0x0f)<<16)/* GPIO out [3:0] pins - W/R */ 149 #define ES_1371_GPIO_OUTM (0x0f<<16) /* mask for above */ 150 #define ES_MSFMTSEL (1<<15) /* MPEG serial data format; 0 = SONY, 1 = I2S */ 151 #define ES_1370_M_SBB (1<<14) /* clock source for DAC - 0 = clock generator; 1 = MPEG clocks */ 152 #define ES_1371_SYNC_RES (1<<14) /* Warm AC97 reset */ 153 #define ES_1370_WTSRSEL(o) (((o)&0x03)<<12)/* fixed frequency clock for DAC1 */ 154 #define ES_1370_WTSRSELM (0x03<<12) /* mask for above */ 155 #define ES_1371_ADC_STOP (1<<13) /* disable CCB transfer capture information */ 156 #define ES_1371_PWR_INTRM (1<<12) /* power level change interrupts enable */ 157 #define ES_1370_DAC_SYNC (1<<11) /* DAC's are synchronous */ 158 #define ES_1371_M_CB (1<<11) /* capture clock source; 0 = AC'97 ADC; 1 = I2S */ 159 #define ES_CCB_INTRM (1<<10) /* CCB voice interrupts enable */ 160 #define ES_1370_M_CB (1<<9) /* capture clock source; 0 = ADC; 1 = MPEG */ 161 #define ES_1370_XCTL0 (1<<8) /* generap purpose output bit */ 162 #define ES_1371_PDLEV(o) (((o)&0x03)<<8) /* current power down level */ 163 #define ES_1371_PDLEVM (0x03<<8) /* mask for above */ 164 #define ES_BREQ (1<<7) /* memory bus request enable */ 165 #define ES_DAC1_EN (1<<6) /* DAC1 playback channel enable */ 166 #define ES_DAC2_EN (1<<5) /* DAC2 playback channel enable */ 167 #define ES_ADC_EN (1<<4) /* ADC capture channel enable */ 168 #define ES_UART_EN (1<<3) /* UART enable */ 169 #define ES_JYSTK_EN (1<<2) /* Joystick module enable */ 170 #define ES_1370_CDC_EN (1<<1) /* Codec interface enable */ 171 #define ES_1371_XTALCKDIS (1<<1) /* Xtal clock disable */ 172 #define ES_1370_SERR_DISABLE (1<<0) /* PCI serr signal disable */ 173 #define ES_1371_PCICLKDIS (1<<0) /* PCI clock disable */ 174 #define ES_REG_STATUS 0x04 /* R/O: Interrupt/Chip select status register */ 175 #define ES_INTR (1<<31) /* Interrupt is pending */ 176 #define ES_1371_ST_AC97_RST (1<<29) /* CT5880 AC'97 Reset bit */ 177 #define ES_1373_REAR_BIT27 (1<<27) /* rear bits: 000 - front, 010 - mirror, 101 - separate */ 178 #define ES_1373_REAR_BIT26 (1<<26) 179 #define ES_1373_REAR_BIT24 (1<<24) 180 #define ES_1373_GPIO_INT_EN(o)(((o)&0x0f)<<20)/* GPIO [3:0] pins - interrupt enable */ 181 #define ES_1373_SPDIF_EN (1<<18) /* SPDIF enable */ 182 #define ES_1373_SPDIF_TEST (1<<17) /* SPDIF test */ 183 #define ES_1371_TEST (1<<16) /* test ASIC */ 184 #define ES_1373_GPIO_INT(i) (((i)&0x0f)>>12)/* GPIO [3:0] pins - interrupt pending */ 185 #define ES_1370_CSTAT (1<<10) /* CODEC is busy or register write in progress */ 186 #define ES_1370_CBUSY (1<<9) /* CODEC is busy */ 187 #define ES_1370_CWRIP (1<<8) /* CODEC register write in progress */ 188 #define ES_1371_SYNC_ERR (1<<8) /* CODEC synchronization error occurred */ 189 #define ES_1371_VC(i) (((i)>>6)&0x03) /* voice code from CCB module */ 190 #define ES_1370_VC(i) (((i)>>5)&0x03) /* voice code from CCB module */ 191 #define ES_1371_MPWR (1<<5) /* power level interrupt pending */ 192 #define ES_MCCB (1<<4) /* CCB interrupt pending */ 193 #define ES_UART (1<<3) /* UART interrupt pending */ 194 #define ES_DAC1 (1<<2) /* DAC1 channel interrupt pending */ 195 #define ES_DAC2 (1<<1) /* DAC2 channel interrupt pending */ 196 #define ES_ADC (1<<0) /* ADC channel interrupt pending */ 197 #define ES_REG_UART_DATA 0x08 /* R/W: UART data register */ 198 #define ES_REG_UART_STATUS 0x09 /* R/O: UART status register */ 199 #define ES_RXINT (1<<7) /* RX interrupt occurred */ 200 #define ES_TXINT (1<<2) /* TX interrupt occurred */ 201 #define ES_TXRDY (1<<1) /* transmitter ready */ 202 #define ES_RXRDY (1<<0) /* receiver ready */ 203 #define ES_REG_UART_CONTROL 0x09 /* W/O: UART control register */ 204 #define ES_RXINTEN (1<<7) /* RX interrupt enable */ 205 #define ES_TXINTENO(o) (((o)&0x03)<<5) /* TX interrupt enable */ 206 #define ES_TXINTENM (0x03<<5) /* mask for above */ 207 #define ES_TXINTENI(i) (((i)>>5)&0x03) 208 #define ES_CNTRL(o) (((o)&0x03)<<0) /* control */ 209 #define ES_CNTRLM (0x03<<0) /* mask for above */ 210 #define ES_REG_UART_RES 0x0a /* R/W: UART reserver register */ 211 #define ES_TEST_MODE (1<<0) /* test mode enabled */ 212 #define ES_REG_MEM_PAGE 0x0c /* R/W: Memory page register */ 213 #define ES_MEM_PAGEO(o) (((o)&0x0f)<<0) /* memory page select - out */ 214 #define ES_MEM_PAGEM (0x0f<<0) /* mask for above */ 215 #define ES_MEM_PAGEI(i) (((i)>>0)&0x0f) /* memory page select - in */ 216 #define ES_REG_1370_CODEC 0x10 /* W/O: Codec write register address */ 217 #define ES_1370_CODEC_WRITE(a,d) ((((a)&0xff)<<8)|(((d)&0xff)<<0)) 218 #define ES_REG_1371_CODEC 0x14 /* W/R: Codec Read/Write register address */ 219 #define ES_1371_CODEC_RDY (1<<31) /* codec ready */ 220 #define ES_1371_CODEC_WIP (1<<30) /* codec register access in progress */ 221 #define ES_1371_CODEC_PIRD (1<<23) /* codec read/write select register */ 222 #define ES_1371_CODEC_WRITE(a,d) ((((a)&0x7f)<<16)|(((d)&0xffff)<<0)) 223 #define ES_1371_CODEC_READS(a) ((((a)&0x7f)<<16)|ES_1371_CODEC_PIRD) 224 #define ES_1371_CODEC_READ(i) (((i)>>0)&0xffff) 225 226 #define ES_REG_1371_SMPRATE 0x10 /* W/R: Codec rate converter interface register */ 227 #define ES_1371_SRC_RAM_ADDRO(o) (((o)&0x7f)<<25)/* address of the sample rate converter */ 228 #define ES_1371_SRC_RAM_ADDRM (0x7f<<25) /* mask for above */ 229 #define ES_1371_SRC_RAM_ADDRI(i) (((i)>>25)&0x7f)/* address of the sample rate converter */ 230 #define ES_1371_SRC_RAM_WE (1<<24) /* R/W: read/write control for sample rate converter */ 231 #define ES_1371_SRC_RAM_BUSY (1<<23) /* R/O: sample rate memory is busy */ 232 #define ES_1371_SRC_DISABLE (1<<22) /* sample rate converter disable */ 233 #define ES_1371_DIS_P1 (1<<21) /* playback channel 1 accumulator update disable */ 234 #define ES_1371_DIS_P2 (1<<20) /* playback channel 1 accumulator update disable */ 235 #define ES_1371_DIS_R1 (1<<19) /* capture channel accumulator update disable */ 236 #define ES_1371_SRC_RAM_DATAO(o) (((o)&0xffff)<<0)/* current value of the sample rate converter */ 237 #define ES_1371_SRC_RAM_DATAM (0xffff<<0) /* mask for above */ 238 #define ES_1371_SRC_RAM_DATAI(i) (((i)>>0)&0xffff)/* current value of the sample rate converter */ 239 240 #define ES_REG_1371_LEGACY 0x18 /* W/R: Legacy control/status register */ 241 #define ES_1371_JFAST (1<<31) /* fast joystick timing */ 242 #define ES_1371_HIB (1<<30) /* host interrupt blocking enable */ 243 #define ES_1371_VSB (1<<29) /* SB; 0 = addr 0x220xH, 1 = 0x22FxH */ 244 #define ES_1371_VMPUO(o) (((o)&0x03)<<27)/* base register address; 0 = 0x320xH; 1 = 0x330xH; 2 = 0x340xH; 3 = 0x350xH */ 245 #define ES_1371_VMPUM (0x03<<27) /* mask for above */ 246 #define ES_1371_VMPUI(i) (((i)>>27)&0x03)/* base register address */ 247 #define ES_1371_VCDCO(o) (((o)&0x03)<<25)/* CODEC; 0 = 0x530xH; 1 = undefined; 2 = 0xe80xH; 3 = 0xF40xH */ 248 #define ES_1371_VCDCM (0x03<<25) /* mask for above */ 249 #define ES_1371_VCDCI(i) (((i)>>25)&0x03)/* CODEC address */ 250 #define ES_1371_FIRQ (1<<24) /* force an interrupt */ 251 #define ES_1371_SDMACAP (1<<23) /* enable event capture for slave DMA controller */ 252 #define ES_1371_SPICAP (1<<22) /* enable event capture for slave IRQ controller */ 253 #define ES_1371_MDMACAP (1<<21) /* enable event capture for master DMA controller */ 254 #define ES_1371_MPICAP (1<<20) /* enable event capture for master IRQ controller */ 255 #define ES_1371_ADCAP (1<<19) /* enable event capture for ADLIB register; 0x388xH */ 256 #define ES_1371_SVCAP (1<<18) /* enable event capture for SB registers */ 257 #define ES_1371_CDCCAP (1<<17) /* enable event capture for CODEC registers */ 258 #define ES_1371_BACAP (1<<16) /* enable event capture for SoundScape base address */ 259 #define ES_1371_EXI(i) (((i)>>8)&0x07) /* event number */ 260 #define ES_1371_AI(i) (((i)>>3)&0x1f) /* event significant I/O address */ 261 #define ES_1371_WR (1<<2) /* event capture; 0 = read; 1 = write */ 262 #define ES_1371_LEGINT (1<<0) /* interrupt for legacy events; 0 = interrupt did occur */ 263 264 #define ES_REG_CHANNEL_STATUS 0x1c /* R/W: first 32-bits from S/PDIF channel status block, es1373 */ 265 266 #define ES_REG_SERIAL 0x20 /* R/W: Serial interface control register */ 267 #define ES_1371_DAC_TEST (1<<22) /* DAC test mode enable */ 268 #define ES_P2_END_INCO(o) (((o)&0x07)<<19)/* binary offset value to increment / loop end */ 269 #define ES_P2_END_INCM (0x07<<19) /* mask for above */ 270 #define ES_P2_END_INCI(i) (((i)>>16)&0x07)/* binary offset value to increment / loop end */ 271 #define ES_P2_ST_INCO(o) (((o)&0x07)<<16)/* binary offset value to increment / start */ 272 #define ES_P2_ST_INCM (0x07<<16) /* mask for above */ 273 #define ES_P2_ST_INCI(i) (((i)<<16)&0x07)/* binary offset value to increment / start */ 274 #define ES_R1_LOOP_SEL (1<<15) /* ADC; 0 - loop mode; 1 = stop mode */ 275 #define ES_P2_LOOP_SEL (1<<14) /* DAC2; 0 - loop mode; 1 = stop mode */ 276 #define ES_P1_LOOP_SEL (1<<13) /* DAC1; 0 - loop mode; 1 = stop mode */ 277 #define ES_P2_PAUSE (1<<12) /* DAC2; 0 - play mode; 1 = pause mode */ 278 #define ES_P1_PAUSE (1<<11) /* DAC1; 0 - play mode; 1 = pause mode */ 279 #define ES_R1_INT_EN (1<<10) /* ADC interrupt enable */ 280 #define ES_P2_INT_EN (1<<9) /* DAC2 interrupt enable */ 281 #define ES_P1_INT_EN (1<<8) /* DAC1 interrupt enable */ 282 #define ES_P1_SCT_RLD (1<<7) /* force sample counter reload for DAC1 */ 283 #define ES_P2_DAC_SEN (1<<6) /* when stop mode: 0 - DAC2 play back zeros; 1 = DAC2 play back last sample */ 284 #define ES_R1_MODEO(o) (((o)&0x03)<<4) /* ADC mode; 0 = 8-bit mono; 1 = 8-bit stereo; 2 = 16-bit mono; 3 = 16-bit stereo */ 285 #define ES_R1_MODEM (0x03<<4) /* mask for above */ 286 #define ES_R1_MODEI(i) (((i)>>4)&0x03) 287 #define ES_P2_MODEO(o) (((o)&0x03)<<2) /* DAC2 mode; -- '' -- */ 288 #define ES_P2_MODEM (0x03<<2) /* mask for above */ 289 #define ES_P2_MODEI(i) (((i)>>2)&0x03) 290 #define ES_P1_MODEO(o) (((o)&0x03)<<0) /* DAC1 mode; -- '' -- */ 291 #define ES_P1_MODEM (0x03<<0) /* mask for above */ 292 #define ES_P1_MODEI(i) (((i)>>0)&0x03) 293 294 #define ES_REG_DAC1_COUNT 0x24 /* R/W: DAC1 sample count register */ 295 #define ES_REG_DAC2_COUNT 0x28 /* R/W: DAC2 sample count register */ 296 #define ES_REG_ADC_COUNT 0x2c /* R/W: ADC sample count register */ 297 #define ES_REG_CURR_COUNT(i) (((i)>>16)&0xffff) 298 #define ES_REG_COUNTO(o) (((o)&0xffff)<<0) 299 #define ES_REG_COUNTM (0xffff<<0) 300 #define ES_REG_COUNTI(i) (((i)>>0)&0xffff) 301 302 #define ES_REG_DAC1_FRAME 0x30 /* R/W: PAGE 0x0c; DAC1 frame address */ 303 #define ES_REG_DAC1_SIZE 0x34 /* R/W: PAGE 0x0c; DAC1 frame size */ 304 #define ES_REG_DAC2_FRAME 0x38 /* R/W: PAGE 0x0c; DAC2 frame address */ 305 #define ES_REG_DAC2_SIZE 0x3c /* R/W: PAGE 0x0c; DAC2 frame size */ 306 #define ES_REG_ADC_FRAME 0x30 /* R/W: PAGE 0x0d; ADC frame address */ 307 #define ES_REG_ADC_SIZE 0x34 /* R/W: PAGE 0x0d; ADC frame size */ 308 #define ES_REG_FCURR_COUNTO(o) (((o)&0xffff)<<16) 309 #define ES_REG_FCURR_COUNTM (0xffff<<16) 310 #define ES_REG_FCURR_COUNTI(i) (((i)>>14)&0x3fffc) 311 #define ES_REG_FSIZEO(o) (((o)&0xffff)<<0) 312 #define ES_REG_FSIZEM (0xffff<<0) 313 #define ES_REG_FSIZEI(i) (((i)>>0)&0xffff) 314 #define ES_REG_PHANTOM_FRAME 0x38 /* R/W: PAGE 0x0d: phantom frame address */ 315 #define ES_REG_PHANTOM_COUNT 0x3c /* R/W: PAGE 0x0d: phantom frame count */ 316 317 #define ES_REG_UART_FIFO 0x30 /* R/W: PAGE 0x0e; UART FIFO register */ 318 #define ES_REG_UF_VALID (1<<8) 319 #define ES_REG_UF_BYTEO(o) (((o)&0xff)<<0) 320 #define ES_REG_UF_BYTEM (0xff<<0) 321 #define ES_REG_UF_BYTEI(i) (((i)>>0)&0xff) 322 323 324 /* 325 * Pages 326 */ 327 328 #define ES_PAGE_DAC 0x0c 329 #define ES_PAGE_ADC 0x0d 330 #define ES_PAGE_UART 0x0e 331 #define ES_PAGE_UART1 0x0f 332 333 /* 334 * Sample rate converter addresses 335 */ 336 337 #define ES_SMPREG_DAC1 0x70 338 #define ES_SMPREG_DAC2 0x74 339 #define ES_SMPREG_ADC 0x78 340 #define ES_SMPREG_VOL_ADC 0x6c 341 #define ES_SMPREG_VOL_DAC1 0x7c 342 #define ES_SMPREG_VOL_DAC2 0x7e 343 #define ES_SMPREG_TRUNC_N 0x00 344 #define ES_SMPREG_INT_REGS 0x01 345 #define ES_SMPREG_ACCUM_FRAC 0x02 346 #define ES_SMPREG_VFREQ_FRAC 0x03 347 348 /* 349 * Some contants 350 */ 351 352 #define ES_1370_SRCLOCK 1411200 353 #define ES_1370_SRTODIV(x) (ES_1370_SRCLOCK/(x)-2) 354 355 /* 356 * Open modes 357 */ 358 359 #define ES_MODE_PLAY1 0x0001 360 #define ES_MODE_PLAY2 0x0002 361 #define ES_MODE_CAPTURE 0x0004 362 363 #define ES_MODE_OUTPUT 0x0001 /* for MIDI */ 364 #define ES_MODE_INPUT 0x0002 /* for MIDI */ 365 366 /* 367 368 */ 369 370 typedef struct _snd_ensoniq ensoniq_t; 371 372 struct _snd_ensoniq { 373 spinlock_t reg_lock; 374 struct semaphore src_mutex; 375 376 int irq; 377 378 unsigned long playback1size; 379 unsigned long playback2size; 380 unsigned long capture3size; 381 382 unsigned long port; 383 unsigned int mode; 384 unsigned int uartm; /* UART mode */ 385 386 unsigned int ctrl; /* control register */ 387 unsigned int sctrl; /* serial control register */ 388 unsigned int cssr; /* control status register */ 389 unsigned int uartc; /* uart control register */ 390 unsigned int rev; /* chip revision */ 391 392 union { 393 #ifdef CHIP1371 394 struct { 395 ac97_t *ac97; 396 } es1371; 397 #else 398 struct { 399 int pclkdiv_lock; 400 ak4531_t *ak4531; 401 } es1370; 402 #endif 403 } u; 404 405 struct pci_dev *pci; 406 unsigned short subsystem_vendor_id; 407 unsigned short subsystem_device_id; 408 snd_card_t *card; 409 snd_pcm_t *pcm1; /* DAC1/ADC PCM */ 410 snd_pcm_t *pcm2; /* DAC2 PCM */ 411 snd_pcm_substream_t *playback1_substream; 412 snd_pcm_substream_t *playback2_substream; 413 snd_pcm_substream_t *capture_substream; 414 unsigned int p1_dma_size; 415 unsigned int p2_dma_size; 416 unsigned int c_dma_size; 417 unsigned int p1_period_size; 418 unsigned int p2_period_size; 419 unsigned int c_period_size; 420 snd_rawmidi_t *rmidi; 421 snd_rawmidi_substream_t *midi_input; 422 snd_rawmidi_substream_t *midi_output; 423 424 unsigned int spdif; 425 unsigned int spdif_default; 426 unsigned int spdif_stream; 427 428 #ifdef CHIP1370 429 struct snd_dma_buffer dma_bug; 430 #endif 431 432 #ifdef SUPPORT_JOYSTICK 433 struct gameport *gameport; 434 #endif 435 }; 436 437 static irqreturn_t snd_audiopci_interrupt(int irq, void *dev_id, struct pt_regs *regs); 438 439 static struct pci_device_id snd_audiopci_ids[] = { 440 #ifdef CHIP1370 441 { 0x1274, 0x5000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* ES1370 */ 442 #endif 443 #ifdef CHIP1371 444 { 0x1274, 0x1371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* ES1371 */ 445 { 0x1274, 0x5880, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* ES1373 - CT5880 */ 446 { 0x1102, 0x8938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* Ectiva EV1938 */ 447 #endif 448 { 0, } 449 }; 450 451 MODULE_DEVICE_TABLE(pci, snd_audiopci_ids); 452 453 /* 454 * constants 455 */ 456 457 #define POLL_COUNT 0xa000 458 459 #ifdef CHIP1370 460 static unsigned int snd_es1370_fixed_rates[] = 461 {5512, 11025, 22050, 44100}; 462 static snd_pcm_hw_constraint_list_t snd_es1370_hw_constraints_rates = { 463 .count = 4, 464 .list = snd_es1370_fixed_rates, 465 .mask = 0, 466 }; 467 static ratnum_t es1370_clock = { 468 .num = ES_1370_SRCLOCK, 469 .den_min = 29, 470 .den_max = 353, 471 .den_step = 1, 472 }; 473 static snd_pcm_hw_constraint_ratnums_t snd_es1370_hw_constraints_clock = { 474 .nrats = 1, 475 .rats = &es1370_clock, 476 }; 477 #else 478 static ratden_t es1371_dac_clock = { 479 .num_min = 3000 * (1 << 15), 480 .num_max = 48000 * (1 << 15), 481 .num_step = 3000, 482 .den = 1 << 15, 483 }; 484 static snd_pcm_hw_constraint_ratdens_t snd_es1371_hw_constraints_dac_clock = { 485 .nrats = 1, 486 .rats = &es1371_dac_clock, 487 }; 488 static ratnum_t es1371_adc_clock = { 489 .num = 48000 << 15, 490 .den_min = 32768, 491 .den_max = 393216, 492 .den_step = 1, 493 }; 494 static snd_pcm_hw_constraint_ratnums_t snd_es1371_hw_constraints_adc_clock = { 495 .nrats = 1, 496 .rats = &es1371_adc_clock, 497 }; 498 #endif 499 static const unsigned int snd_ensoniq_sample_shift[] = 500 {0, 1, 1, 2}; 501 502 /* 503 * common I/O routines 504 */ 505 506 #ifdef CHIP1371 507 508 static unsigned int snd_es1371_wait_src_ready(ensoniq_t * ensoniq) 509 { 510 unsigned int t, r = 0; 511 512 for (t = 0; t < POLL_COUNT; t++) { 513 r = inl(ES_REG(ensoniq, 1371_SMPRATE)); 514 if ((r & ES_1371_SRC_RAM_BUSY) == 0) 515 return r; 516 cond_resched(); 517 } 518 snd_printk("wait source ready timeout 0x%lx [0x%x]\n", ES_REG(ensoniq, 1371_SMPRATE), r); 519 return 0; 520 } 521 522 static unsigned int snd_es1371_src_read(ensoniq_t * ensoniq, unsigned short reg) 523 { 524 unsigned int temp, i, orig, r; 525 526 /* wait for ready */ 527 temp = orig = snd_es1371_wait_src_ready(ensoniq); 528 529 /* expose the SRC state bits */ 530 r = temp & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 | 531 ES_1371_DIS_P2 | ES_1371_DIS_R1); 532 r |= ES_1371_SRC_RAM_ADDRO(reg) | 0x10000; 533 outl(r, ES_REG(ensoniq, 1371_SMPRATE)); 534 535 /* now, wait for busy and the correct time to read */ 536 temp = snd_es1371_wait_src_ready(ensoniq); 537 538 if ((temp & 0x00870000) != 0x00010000) { 539 /* wait for the right state */ 540 for (i = 0; i < POLL_COUNT; i++) { 541 temp = inl(ES_REG(ensoniq, 1371_SMPRATE)); 542 if ((temp & 0x00870000) == 0x00010000) 543 break; 544 } 545 } 546 547 /* hide the state bits */ 548 r = orig & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 | 549 ES_1371_DIS_P2 | ES_1371_DIS_R1); 550 r |= ES_1371_SRC_RAM_ADDRO(reg); 551 outl(r, ES_REG(ensoniq, 1371_SMPRATE)); 552 553 return temp; 554 } 555 556 static void snd_es1371_src_write(ensoniq_t * ensoniq, 557 unsigned short reg, unsigned short data) 558 { 559 unsigned int r; 560 561 r = snd_es1371_wait_src_ready(ensoniq) & 562 (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 | 563 ES_1371_DIS_P2 | ES_1371_DIS_R1); 564 r |= ES_1371_SRC_RAM_ADDRO(reg) | ES_1371_SRC_RAM_DATAO(data); 565 outl(r | ES_1371_SRC_RAM_WE, ES_REG(ensoniq, 1371_SMPRATE)); 566 } 567 568 #endif /* CHIP1371 */ 569 570 #ifdef CHIP1370 571 572 static void snd_es1370_codec_write(ak4531_t *ak4531, 573 unsigned short reg, unsigned short val) 574 { 575 ensoniq_t *ensoniq = ak4531->private_data; 576 unsigned long end_time = jiffies + HZ / 10; 577 578 #if 0 579 printk("CODEC WRITE: reg = 0x%x, val = 0x%x (0x%x), creg = 0x%x\n", reg, val, ES_1370_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1370_CODEC)); 580 #endif 581 do { 582 if (!(inl(ES_REG(ensoniq, STATUS)) & ES_1370_CSTAT)) { 583 outw(ES_1370_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1370_CODEC)); 584 return; 585 } 586 set_current_state(TASK_UNINTERRUPTIBLE); 587 schedule_timeout(1); 588 } while (time_after(end_time, jiffies)); 589 snd_printk("codec write timeout, status = 0x%x\n", inl(ES_REG(ensoniq, STATUS))); 590 } 591 592 #endif /* CHIP1370 */ 593 594 #ifdef CHIP1371 595 596 static void snd_es1371_codec_write(ac97_t *ac97, 597 unsigned short reg, unsigned short val) 598 { 599 ensoniq_t *ensoniq = ac97->private_data; 600 unsigned int t, x; 601 602 down(&ensoniq->src_mutex); 603 for (t = 0; t < POLL_COUNT; t++) { 604 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) { 605 /* save the current state for latter */ 606 x = snd_es1371_wait_src_ready(ensoniq); 607 outl((x & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 | 608 ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 0x00010000, 609 ES_REG(ensoniq, 1371_SMPRATE)); 610 /* wait for not busy (state 0) first to avoid 611 transition states */ 612 for (t = 0; t < POLL_COUNT; t++) { 613 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) == 0x00000000) 614 break; 615 } 616 /* wait for a SAFE time to write addr/data and then do it, dammit */ 617 for (t = 0; t < POLL_COUNT; t++) { 618 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) == 0x00010000) 619 break; 620 } 621 outl(ES_1371_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1371_CODEC)); 622 /* restore SRC reg */ 623 snd_es1371_wait_src_ready(ensoniq); 624 outl(x, ES_REG(ensoniq, 1371_SMPRATE)); 625 up(&ensoniq->src_mutex); 626 return; 627 } 628 } 629 up(&ensoniq->src_mutex); 630 snd_printk("codec write timeout at 0x%lx [0x%x]\n", ES_REG(ensoniq, 1371_CODEC), inl(ES_REG(ensoniq, 1371_CODEC))); 631 } 632 633 static unsigned short snd_es1371_codec_read(ac97_t *ac97, 634 unsigned short reg) 635 { 636 ensoniq_t *ensoniq = ac97->private_data; 637 unsigned int t, x, fail = 0; 638 639 __again: 640 down(&ensoniq->src_mutex); 641 for (t = 0; t < POLL_COUNT; t++) { 642 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) { 643 /* save the current state for latter */ 644 x = snd_es1371_wait_src_ready(ensoniq); 645 outl((x & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 | 646 ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 0x00010000, 647 ES_REG(ensoniq, 1371_SMPRATE)); 648 /* wait for not busy (state 0) first to avoid 649 transition states */ 650 for (t = 0; t < POLL_COUNT; t++) { 651 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) == 0x00000000) 652 break; 653 } 654 /* wait for a SAFE time to write addr/data and then do it, dammit */ 655 for (t = 0; t < POLL_COUNT; t++) { 656 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) == 0x00010000) 657 break; 658 } 659 outl(ES_1371_CODEC_READS(reg), ES_REG(ensoniq, 1371_CODEC)); 660 /* restore SRC reg */ 661 snd_es1371_wait_src_ready(ensoniq); 662 outl(x, ES_REG(ensoniq, 1371_SMPRATE)); 663 /* wait for WIP again */ 664 for (t = 0; t < POLL_COUNT; t++) { 665 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) 666 break; 667 } 668 /* now wait for the stinkin' data (RDY) */ 669 for (t = 0; t < POLL_COUNT; t++) { 670 if ((x = inl(ES_REG(ensoniq, 1371_CODEC))) & ES_1371_CODEC_RDY) { 671 up(&ensoniq->src_mutex); 672 return ES_1371_CODEC_READ(x); 673 } 674 } 675 up(&ensoniq->src_mutex); 676 if (++fail > 10) { 677 snd_printk("codec read timeout (final) at 0x%lx, reg = 0x%x [0x%x]\n", ES_REG(ensoniq, 1371_CODEC), reg, inl(ES_REG(ensoniq, 1371_CODEC))); 678 return 0; 679 } 680 goto __again; 681 } 682 } 683 up(&ensoniq->src_mutex); 684 snd_printk("es1371: codec read timeout at 0x%lx [0x%x]\n", ES_REG(ensoniq, 1371_CODEC), inl(ES_REG(ensoniq, 1371_CODEC))); 685 return 0; 686 } 687 688 static void snd_es1371_codec_wait(ac97_t *ac97) 689 { 690 msleep(750); 691 snd_es1371_codec_read(ac97, AC97_RESET); 692 snd_es1371_codec_read(ac97, AC97_VENDOR_ID1); 693 snd_es1371_codec_read(ac97, AC97_VENDOR_ID2); 694 msleep(50); 695 } 696 697 static void snd_es1371_adc_rate(ensoniq_t * ensoniq, unsigned int rate) 698 { 699 unsigned int n, truncm, freq, result; 700 701 down(&ensoniq->src_mutex); 702 n = rate / 3000; 703 if ((1 << n) & ((1 << 15) | (1 << 13) | (1 << 11) | (1 << 9))) 704 n--; 705 truncm = (21 * n - 1) | 1; 706 freq = ((48000UL << 15) / rate) * n; 707 result = (48000UL << 15) / (freq / n); 708 if (rate >= 24000) { 709 if (truncm > 239) 710 truncm = 239; 711 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N, 712 (((239 - truncm) >> 1) << 9) | (n << 4)); 713 } else { 714 if (truncm > 119) 715 truncm = 119; 716 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N, 717 0x8000 | (((119 - truncm) >> 1) << 9) | (n << 4)); 718 } 719 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_INT_REGS, 720 (snd_es1371_src_read(ensoniq, ES_SMPREG_ADC + ES_SMPREG_INT_REGS) & 0x00ff) | 721 ((freq >> 5) & 0xfc00)); 722 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff); 723 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC, n << 8); 724 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC + 1, n << 8); 725 up(&ensoniq->src_mutex); 726 } 727 728 static void snd_es1371_dac1_rate(ensoniq_t * ensoniq, unsigned int rate) 729 { 730 unsigned int freq, r; 731 732 down(&ensoniq->src_mutex); 733 freq = ((rate << 15) + 1500) / 3000; 734 r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE | ES_1371_DIS_P2 | ES_1371_DIS_R1)) | ES_1371_DIS_P1; 735 outl(r, ES_REG(ensoniq, 1371_SMPRATE)); 736 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS, 737 (snd_es1371_src_read(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS) & 0x00ff) | 738 ((freq >> 5) & 0xfc00)); 739 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff); 740 r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE | ES_1371_DIS_P2 | ES_1371_DIS_R1)); 741 outl(r, ES_REG(ensoniq, 1371_SMPRATE)); 742 up(&ensoniq->src_mutex); 743 } 744 745 static void snd_es1371_dac2_rate(ensoniq_t * ensoniq, unsigned int rate) 746 { 747 unsigned int freq, r; 748 749 down(&ensoniq->src_mutex); 750 freq = ((rate << 15) + 1500) / 3000; 751 r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 | ES_1371_DIS_R1)) | ES_1371_DIS_P2; 752 outl(r, ES_REG(ensoniq, 1371_SMPRATE)); 753 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS, 754 (snd_es1371_src_read(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS) & 0x00ff) | 755 ((freq >> 5) & 0xfc00)); 756 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff); 757 r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 | ES_1371_DIS_R1)); 758 outl(r, ES_REG(ensoniq, 1371_SMPRATE)); 759 up(&ensoniq->src_mutex); 760 } 761 762 #endif /* CHIP1371 */ 763 764 static int snd_ensoniq_trigger(snd_pcm_substream_t *substream, int cmd) 765 { 766 ensoniq_t *ensoniq = snd_pcm_substream_chip(substream); 767 switch (cmd) { 768 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 769 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 770 { 771 unsigned int what = 0; 772 struct list_head *pos; 773 snd_pcm_substream_t *s; 774 snd_pcm_group_for_each(pos, substream) { 775 s = snd_pcm_group_substream_entry(pos); 776 if (s == ensoniq->playback1_substream) { 777 what |= ES_P1_PAUSE; 778 snd_pcm_trigger_done(s, substream); 779 } else if (s == ensoniq->playback2_substream) { 780 what |= ES_P2_PAUSE; 781 snd_pcm_trigger_done(s, substream); 782 } else if (s == ensoniq->capture_substream) 783 return -EINVAL; 784 } 785 spin_lock(&ensoniq->reg_lock); 786 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH) 787 ensoniq->sctrl |= what; 788 else 789 ensoniq->sctrl &= ~what; 790 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL)); 791 spin_unlock(&ensoniq->reg_lock); 792 break; 793 } 794 case SNDRV_PCM_TRIGGER_START: 795 case SNDRV_PCM_TRIGGER_STOP: 796 { 797 unsigned int what = 0; 798 struct list_head *pos; 799 snd_pcm_substream_t *s; 800 snd_pcm_group_for_each(pos, substream) { 801 s = snd_pcm_group_substream_entry(pos); 802 if (s == ensoniq->playback1_substream) { 803 what |= ES_DAC1_EN; 804 snd_pcm_trigger_done(s, substream); 805 } else if (s == ensoniq->playback2_substream) { 806 what |= ES_DAC2_EN; 807 snd_pcm_trigger_done(s, substream); 808 } else if (s == ensoniq->capture_substream) { 809 what |= ES_ADC_EN; 810 snd_pcm_trigger_done(s, substream); 811 } 812 } 813 spin_lock(&ensoniq->reg_lock); 814 if (cmd == SNDRV_PCM_TRIGGER_START) 815 ensoniq->ctrl |= what; 816 else 817 ensoniq->ctrl &= ~what; 818 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 819 spin_unlock(&ensoniq->reg_lock); 820 break; 821 } 822 default: 823 return -EINVAL; 824 } 825 return 0; 826 } 827 828 /* 829 * PCM part 830 */ 831 832 static int snd_ensoniq_hw_params(snd_pcm_substream_t * substream, 833 snd_pcm_hw_params_t * hw_params) 834 { 835 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params)); 836 } 837 838 static int snd_ensoniq_hw_free(snd_pcm_substream_t * substream) 839 { 840 return snd_pcm_lib_free_pages(substream); 841 } 842 843 static int snd_ensoniq_playback1_prepare(snd_pcm_substream_t * substream) 844 { 845 ensoniq_t *ensoniq = snd_pcm_substream_chip(substream); 846 snd_pcm_runtime_t *runtime = substream->runtime; 847 unsigned int mode = 0; 848 849 ensoniq->p1_dma_size = snd_pcm_lib_buffer_bytes(substream); 850 ensoniq->p1_period_size = snd_pcm_lib_period_bytes(substream); 851 if (snd_pcm_format_width(runtime->format) == 16) 852 mode |= 0x02; 853 if (runtime->channels > 1) 854 mode |= 0x01; 855 spin_lock_irq(&ensoniq->reg_lock); 856 ensoniq->ctrl &= ~ES_DAC1_EN; 857 #ifdef CHIP1371 858 /* 48k doesn't need SRC (it breaks AC3-passthru) */ 859 if (runtime->rate == 48000) 860 ensoniq->ctrl |= ES_1373_BYPASS_P1; 861 else 862 ensoniq->ctrl &= ~ES_1373_BYPASS_P1; 863 #endif 864 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 865 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE)); 866 outl(runtime->dma_addr, ES_REG(ensoniq, DAC1_FRAME)); 867 outl((ensoniq->p1_dma_size >> 2) - 1, ES_REG(ensoniq, DAC1_SIZE)); 868 ensoniq->sctrl &= ~(ES_P1_LOOP_SEL | ES_P1_PAUSE | ES_P1_SCT_RLD | ES_P1_MODEM); 869 ensoniq->sctrl |= ES_P1_INT_EN | ES_P1_MODEO(mode); 870 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL)); 871 outl((ensoniq->p1_period_size >> snd_ensoniq_sample_shift[mode]) - 1, ES_REG(ensoniq, DAC1_COUNT)); 872 #ifdef CHIP1370 873 ensoniq->ctrl &= ~ES_1370_WTSRSELM; 874 switch (runtime->rate) { 875 case 5512: ensoniq->ctrl |= ES_1370_WTSRSEL(0); break; 876 case 11025: ensoniq->ctrl |= ES_1370_WTSRSEL(1); break; 877 case 22050: ensoniq->ctrl |= ES_1370_WTSRSEL(2); break; 878 case 44100: ensoniq->ctrl |= ES_1370_WTSRSEL(3); break; 879 default: snd_BUG(); 880 } 881 #endif 882 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 883 spin_unlock_irq(&ensoniq->reg_lock); 884 #ifndef CHIP1370 885 snd_es1371_dac1_rate(ensoniq, runtime->rate); 886 #endif 887 return 0; 888 } 889 890 static int snd_ensoniq_playback2_prepare(snd_pcm_substream_t * substream) 891 { 892 ensoniq_t *ensoniq = snd_pcm_substream_chip(substream); 893 snd_pcm_runtime_t *runtime = substream->runtime; 894 unsigned int mode = 0; 895 896 ensoniq->p2_dma_size = snd_pcm_lib_buffer_bytes(substream); 897 ensoniq->p2_period_size = snd_pcm_lib_period_bytes(substream); 898 if (snd_pcm_format_width(runtime->format) == 16) 899 mode |= 0x02; 900 if (runtime->channels > 1) 901 mode |= 0x01; 902 spin_lock_irq(&ensoniq->reg_lock); 903 ensoniq->ctrl &= ~ES_DAC2_EN; 904 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 905 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE)); 906 outl(runtime->dma_addr, ES_REG(ensoniq, DAC2_FRAME)); 907 outl((ensoniq->p2_dma_size >> 2) - 1, ES_REG(ensoniq, DAC2_SIZE)); 908 ensoniq->sctrl &= ~(ES_P2_LOOP_SEL | ES_P2_PAUSE | ES_P2_DAC_SEN | 909 ES_P2_END_INCM | ES_P2_ST_INCM | ES_P2_MODEM); 910 ensoniq->sctrl |= ES_P2_INT_EN | ES_P2_MODEO(mode) | 911 ES_P2_END_INCO(mode & 2 ? 2 : 1) | ES_P2_ST_INCO(0); 912 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL)); 913 outl((ensoniq->p2_period_size >> snd_ensoniq_sample_shift[mode]) - 1, ES_REG(ensoniq, DAC2_COUNT)); 914 #ifdef CHIP1370 915 if (!(ensoniq->u.es1370.pclkdiv_lock & ES_MODE_CAPTURE)) { 916 ensoniq->ctrl &= ~ES_1370_PCLKDIVM; 917 ensoniq->ctrl |= ES_1370_PCLKDIVO(ES_1370_SRTODIV(runtime->rate)); 918 ensoniq->u.es1370.pclkdiv_lock |= ES_MODE_PLAY2; 919 } 920 #endif 921 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 922 spin_unlock_irq(&ensoniq->reg_lock); 923 #ifndef CHIP1370 924 snd_es1371_dac2_rate(ensoniq, runtime->rate); 925 #endif 926 return 0; 927 } 928 929 static int snd_ensoniq_capture_prepare(snd_pcm_substream_t * substream) 930 { 931 ensoniq_t *ensoniq = snd_pcm_substream_chip(substream); 932 snd_pcm_runtime_t *runtime = substream->runtime; 933 unsigned int mode = 0; 934 935 ensoniq->c_dma_size = snd_pcm_lib_buffer_bytes(substream); 936 ensoniq->c_period_size = snd_pcm_lib_period_bytes(substream); 937 if (snd_pcm_format_width(runtime->format) == 16) 938 mode |= 0x02; 939 if (runtime->channels > 1) 940 mode |= 0x01; 941 spin_lock_irq(&ensoniq->reg_lock); 942 ensoniq->ctrl &= ~ES_ADC_EN; 943 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 944 outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE)); 945 outl(runtime->dma_addr, ES_REG(ensoniq, ADC_FRAME)); 946 outl((ensoniq->c_dma_size >> 2) - 1, ES_REG(ensoniq, ADC_SIZE)); 947 ensoniq->sctrl &= ~(ES_R1_LOOP_SEL | ES_R1_MODEM); 948 ensoniq->sctrl |= ES_R1_INT_EN | ES_R1_MODEO(mode); 949 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL)); 950 outl((ensoniq->c_period_size >> snd_ensoniq_sample_shift[mode]) - 1, ES_REG(ensoniq, ADC_COUNT)); 951 #ifdef CHIP1370 952 if (!(ensoniq->u.es1370.pclkdiv_lock & ES_MODE_PLAY2)) { 953 ensoniq->ctrl &= ~ES_1370_PCLKDIVM; 954 ensoniq->ctrl |= ES_1370_PCLKDIVO(ES_1370_SRTODIV(runtime->rate)); 955 ensoniq->u.es1370.pclkdiv_lock |= ES_MODE_CAPTURE; 956 } 957 #endif 958 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 959 spin_unlock_irq(&ensoniq->reg_lock); 960 #ifndef CHIP1370 961 snd_es1371_adc_rate(ensoniq, runtime->rate); 962 #endif 963 return 0; 964 } 965 966 static snd_pcm_uframes_t snd_ensoniq_playback1_pointer(snd_pcm_substream_t * substream) 967 { 968 ensoniq_t *ensoniq = snd_pcm_substream_chip(substream); 969 size_t ptr; 970 971 spin_lock(&ensoniq->reg_lock); 972 if (inl(ES_REG(ensoniq, CONTROL)) & ES_DAC1_EN) { 973 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE)); 974 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, DAC1_SIZE))); 975 ptr = bytes_to_frames(substream->runtime, ptr); 976 } else { 977 ptr = 0; 978 } 979 spin_unlock(&ensoniq->reg_lock); 980 return ptr; 981 } 982 983 static snd_pcm_uframes_t snd_ensoniq_playback2_pointer(snd_pcm_substream_t * substream) 984 { 985 ensoniq_t *ensoniq = snd_pcm_substream_chip(substream); 986 size_t ptr; 987 988 spin_lock(&ensoniq->reg_lock); 989 if (inl(ES_REG(ensoniq, CONTROL)) & ES_DAC2_EN) { 990 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE)); 991 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, DAC2_SIZE))); 992 ptr = bytes_to_frames(substream->runtime, ptr); 993 } else { 994 ptr = 0; 995 } 996 spin_unlock(&ensoniq->reg_lock); 997 return ptr; 998 } 999 1000 static snd_pcm_uframes_t snd_ensoniq_capture_pointer(snd_pcm_substream_t * substream) 1001 { 1002 ensoniq_t *ensoniq = snd_pcm_substream_chip(substream); 1003 size_t ptr; 1004 1005 spin_lock(&ensoniq->reg_lock); 1006 if (inl(ES_REG(ensoniq, CONTROL)) & ES_ADC_EN) { 1007 outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE)); 1008 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, ADC_SIZE))); 1009 ptr = bytes_to_frames(substream->runtime, ptr); 1010 } else { 1011 ptr = 0; 1012 } 1013 spin_unlock(&ensoniq->reg_lock); 1014 return ptr; 1015 } 1016 1017 static snd_pcm_hardware_t snd_ensoniq_playback1 = 1018 { 1019 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 1020 SNDRV_PCM_INFO_BLOCK_TRANSFER | 1021 SNDRV_PCM_INFO_MMAP_VALID | 1022 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START), 1023 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE, 1024 .rates = 1025 #ifndef CHIP1370 1026 SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, 1027 #else 1028 (SNDRV_PCM_RATE_KNOT | /* 5512Hz rate */ 1029 SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_22050 | 1030 SNDRV_PCM_RATE_44100), 1031 #endif 1032 .rate_min = 4000, 1033 .rate_max = 48000, 1034 .channels_min = 1, 1035 .channels_max = 2, 1036 .buffer_bytes_max = (128*1024), 1037 .period_bytes_min = 64, 1038 .period_bytes_max = (128*1024), 1039 .periods_min = 1, 1040 .periods_max = 1024, 1041 .fifo_size = 0, 1042 }; 1043 1044 static snd_pcm_hardware_t snd_ensoniq_playback2 = 1045 { 1046 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 1047 SNDRV_PCM_INFO_BLOCK_TRANSFER | 1048 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_PAUSE | 1049 SNDRV_PCM_INFO_SYNC_START), 1050 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE, 1051 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, 1052 .rate_min = 4000, 1053 .rate_max = 48000, 1054 .channels_min = 1, 1055 .channels_max = 2, 1056 .buffer_bytes_max = (128*1024), 1057 .period_bytes_min = 64, 1058 .period_bytes_max = (128*1024), 1059 .periods_min = 1, 1060 .periods_max = 1024, 1061 .fifo_size = 0, 1062 }; 1063 1064 static snd_pcm_hardware_t snd_ensoniq_capture = 1065 { 1066 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 1067 SNDRV_PCM_INFO_BLOCK_TRANSFER | 1068 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_SYNC_START), 1069 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE, 1070 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, 1071 .rate_min = 4000, 1072 .rate_max = 48000, 1073 .channels_min = 1, 1074 .channels_max = 2, 1075 .buffer_bytes_max = (128*1024), 1076 .period_bytes_min = 64, 1077 .period_bytes_max = (128*1024), 1078 .periods_min = 1, 1079 .periods_max = 1024, 1080 .fifo_size = 0, 1081 }; 1082 1083 static int snd_ensoniq_playback1_open(snd_pcm_substream_t * substream) 1084 { 1085 ensoniq_t *ensoniq = snd_pcm_substream_chip(substream); 1086 snd_pcm_runtime_t *runtime = substream->runtime; 1087 1088 ensoniq->mode |= ES_MODE_PLAY1; 1089 ensoniq->playback1_substream = substream; 1090 runtime->hw = snd_ensoniq_playback1; 1091 snd_pcm_set_sync(substream); 1092 spin_lock_irq(&ensoniq->reg_lock); 1093 if (ensoniq->spdif && ensoniq->playback2_substream == NULL) 1094 ensoniq->spdif_stream = ensoniq->spdif_default; 1095 spin_unlock_irq(&ensoniq->reg_lock); 1096 #ifdef CHIP1370 1097 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 1098 &snd_es1370_hw_constraints_rates); 1099 #else 1100 snd_pcm_hw_constraint_ratdens(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 1101 &snd_es1371_hw_constraints_dac_clock); 1102 #endif 1103 return 0; 1104 } 1105 1106 static int snd_ensoniq_playback2_open(snd_pcm_substream_t * substream) 1107 { 1108 ensoniq_t *ensoniq = snd_pcm_substream_chip(substream); 1109 snd_pcm_runtime_t *runtime = substream->runtime; 1110 1111 ensoniq->mode |= ES_MODE_PLAY2; 1112 ensoniq->playback2_substream = substream; 1113 runtime->hw = snd_ensoniq_playback2; 1114 snd_pcm_set_sync(substream); 1115 spin_lock_irq(&ensoniq->reg_lock); 1116 if (ensoniq->spdif && ensoniq->playback1_substream == NULL) 1117 ensoniq->spdif_stream = ensoniq->spdif_default; 1118 spin_unlock_irq(&ensoniq->reg_lock); 1119 #ifdef CHIP1370 1120 snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 1121 &snd_es1370_hw_constraints_clock); 1122 #else 1123 snd_pcm_hw_constraint_ratdens(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 1124 &snd_es1371_hw_constraints_dac_clock); 1125 #endif 1126 return 0; 1127 } 1128 1129 static int snd_ensoniq_capture_open(snd_pcm_substream_t * substream) 1130 { 1131 ensoniq_t *ensoniq = snd_pcm_substream_chip(substream); 1132 snd_pcm_runtime_t *runtime = substream->runtime; 1133 1134 ensoniq->mode |= ES_MODE_CAPTURE; 1135 ensoniq->capture_substream = substream; 1136 runtime->hw = snd_ensoniq_capture; 1137 snd_pcm_set_sync(substream); 1138 #ifdef CHIP1370 1139 snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 1140 &snd_es1370_hw_constraints_clock); 1141 #else 1142 snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 1143 &snd_es1371_hw_constraints_adc_clock); 1144 #endif 1145 return 0; 1146 } 1147 1148 static int snd_ensoniq_playback1_close(snd_pcm_substream_t * substream) 1149 { 1150 ensoniq_t *ensoniq = snd_pcm_substream_chip(substream); 1151 1152 ensoniq->playback1_substream = NULL; 1153 ensoniq->mode &= ~ES_MODE_PLAY1; 1154 return 0; 1155 } 1156 1157 static int snd_ensoniq_playback2_close(snd_pcm_substream_t * substream) 1158 { 1159 ensoniq_t *ensoniq = snd_pcm_substream_chip(substream); 1160 1161 ensoniq->playback2_substream = NULL; 1162 spin_lock_irq(&ensoniq->reg_lock); 1163 #ifdef CHIP1370 1164 ensoniq->u.es1370.pclkdiv_lock &= ~ES_MODE_PLAY2; 1165 #endif 1166 ensoniq->mode &= ~ES_MODE_PLAY2; 1167 spin_unlock_irq(&ensoniq->reg_lock); 1168 return 0; 1169 } 1170 1171 static int snd_ensoniq_capture_close(snd_pcm_substream_t * substream) 1172 { 1173 ensoniq_t *ensoniq = snd_pcm_substream_chip(substream); 1174 1175 ensoniq->capture_substream = NULL; 1176 spin_lock_irq(&ensoniq->reg_lock); 1177 #ifdef CHIP1370 1178 ensoniq->u.es1370.pclkdiv_lock &= ~ES_MODE_CAPTURE; 1179 #endif 1180 ensoniq->mode &= ~ES_MODE_CAPTURE; 1181 spin_unlock_irq(&ensoniq->reg_lock); 1182 return 0; 1183 } 1184 1185 static snd_pcm_ops_t snd_ensoniq_playback1_ops = { 1186 .open = snd_ensoniq_playback1_open, 1187 .close = snd_ensoniq_playback1_close, 1188 .ioctl = snd_pcm_lib_ioctl, 1189 .hw_params = snd_ensoniq_hw_params, 1190 .hw_free = snd_ensoniq_hw_free, 1191 .prepare = snd_ensoniq_playback1_prepare, 1192 .trigger = snd_ensoniq_trigger, 1193 .pointer = snd_ensoniq_playback1_pointer, 1194 }; 1195 1196 static snd_pcm_ops_t snd_ensoniq_playback2_ops = { 1197 .open = snd_ensoniq_playback2_open, 1198 .close = snd_ensoniq_playback2_close, 1199 .ioctl = snd_pcm_lib_ioctl, 1200 .hw_params = snd_ensoniq_hw_params, 1201 .hw_free = snd_ensoniq_hw_free, 1202 .prepare = snd_ensoniq_playback2_prepare, 1203 .trigger = snd_ensoniq_trigger, 1204 .pointer = snd_ensoniq_playback2_pointer, 1205 }; 1206 1207 static snd_pcm_ops_t snd_ensoniq_capture_ops = { 1208 .open = snd_ensoniq_capture_open, 1209 .close = snd_ensoniq_capture_close, 1210 .ioctl = snd_pcm_lib_ioctl, 1211 .hw_params = snd_ensoniq_hw_params, 1212 .hw_free = snd_ensoniq_hw_free, 1213 .prepare = snd_ensoniq_capture_prepare, 1214 .trigger = snd_ensoniq_trigger, 1215 .pointer = snd_ensoniq_capture_pointer, 1216 }; 1217 1218 static void snd_ensoniq_pcm_free(snd_pcm_t *pcm) 1219 { 1220 ensoniq_t *ensoniq = pcm->private_data; 1221 ensoniq->pcm1 = NULL; 1222 snd_pcm_lib_preallocate_free_for_all(pcm); 1223 } 1224 1225 static int __devinit snd_ensoniq_pcm(ensoniq_t * ensoniq, int device, snd_pcm_t ** rpcm) 1226 { 1227 snd_pcm_t *pcm; 1228 int err; 1229 1230 if (rpcm) 1231 *rpcm = NULL; 1232 #ifdef CHIP1370 1233 err = snd_pcm_new(ensoniq->card, "ES1370/1", device, 1, 1, &pcm); 1234 #else 1235 err = snd_pcm_new(ensoniq->card, "ES1371/1", device, 1, 1, &pcm); 1236 #endif 1237 if (err < 0) 1238 return err; 1239 1240 #ifdef CHIP1370 1241 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback2_ops); 1242 #else 1243 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback1_ops); 1244 #endif 1245 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ensoniq_capture_ops); 1246 1247 pcm->private_data = ensoniq; 1248 pcm->private_free = snd_ensoniq_pcm_free; 1249 pcm->info_flags = 0; 1250 #ifdef CHIP1370 1251 strcpy(pcm->name, "ES1370 DAC2/ADC"); 1252 #else 1253 strcpy(pcm->name, "ES1371 DAC2/ADC"); 1254 #endif 1255 ensoniq->pcm1 = pcm; 1256 1257 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 1258 snd_dma_pci_data(ensoniq->pci), 64*1024, 128*1024); 1259 1260 if (rpcm) 1261 *rpcm = pcm; 1262 return 0; 1263 } 1264 1265 static void snd_ensoniq_pcm_free2(snd_pcm_t *pcm) 1266 { 1267 ensoniq_t *ensoniq = pcm->private_data; 1268 ensoniq->pcm2 = NULL; 1269 snd_pcm_lib_preallocate_free_for_all(pcm); 1270 } 1271 1272 static int __devinit snd_ensoniq_pcm2(ensoniq_t * ensoniq, int device, snd_pcm_t ** rpcm) 1273 { 1274 snd_pcm_t *pcm; 1275 int err; 1276 1277 if (rpcm) 1278 *rpcm = NULL; 1279 #ifdef CHIP1370 1280 err = snd_pcm_new(ensoniq->card, "ES1370/2", device, 1, 0, &pcm); 1281 #else 1282 err = snd_pcm_new(ensoniq->card, "ES1371/2", device, 1, 0, &pcm); 1283 #endif 1284 if (err < 0) 1285 return err; 1286 1287 #ifdef CHIP1370 1288 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback1_ops); 1289 #else 1290 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback2_ops); 1291 #endif 1292 pcm->private_data = ensoniq; 1293 pcm->private_free = snd_ensoniq_pcm_free2; 1294 pcm->info_flags = 0; 1295 #ifdef CHIP1370 1296 strcpy(pcm->name, "ES1370 DAC1"); 1297 #else 1298 strcpy(pcm->name, "ES1371 DAC1"); 1299 #endif 1300 ensoniq->pcm2 = pcm; 1301 1302 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 1303 snd_dma_pci_data(ensoniq->pci), 64*1024, 128*1024); 1304 1305 if (rpcm) 1306 *rpcm = pcm; 1307 return 0; 1308 } 1309 1310 /* 1311 * Mixer section 1312 */ 1313 1314 /* 1315 * ENS1371 mixer (including SPDIF interface) 1316 */ 1317 #ifdef CHIP1371 1318 static int snd_ens1373_spdif_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t * uinfo) 1319 { 1320 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 1321 uinfo->count = 1; 1322 return 0; 1323 } 1324 1325 static int snd_ens1373_spdif_default_get(snd_kcontrol_t * kcontrol, 1326 snd_ctl_elem_value_t * ucontrol) 1327 { 1328 ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol); 1329 spin_lock_irq(&ensoniq->reg_lock); 1330 ucontrol->value.iec958.status[0] = (ensoniq->spdif_default >> 0) & 0xff; 1331 ucontrol->value.iec958.status[1] = (ensoniq->spdif_default >> 8) & 0xff; 1332 ucontrol->value.iec958.status[2] = (ensoniq->spdif_default >> 16) & 0xff; 1333 ucontrol->value.iec958.status[3] = (ensoniq->spdif_default >> 24) & 0xff; 1334 spin_unlock_irq(&ensoniq->reg_lock); 1335 return 0; 1336 } 1337 1338 static int snd_ens1373_spdif_default_put(snd_kcontrol_t * kcontrol, 1339 snd_ctl_elem_value_t * ucontrol) 1340 { 1341 ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol); 1342 unsigned int val; 1343 int change; 1344 1345 val = ((u32)ucontrol->value.iec958.status[0] << 0) | 1346 ((u32)ucontrol->value.iec958.status[1] << 8) | 1347 ((u32)ucontrol->value.iec958.status[2] << 16) | 1348 ((u32)ucontrol->value.iec958.status[3] << 24); 1349 spin_lock_irq(&ensoniq->reg_lock); 1350 change = ensoniq->spdif_default != val; 1351 ensoniq->spdif_default = val; 1352 if (change && ensoniq->playback1_substream == NULL && ensoniq->playback2_substream == NULL) 1353 outl(val, ES_REG(ensoniq, CHANNEL_STATUS)); 1354 spin_unlock_irq(&ensoniq->reg_lock); 1355 return change; 1356 } 1357 1358 static int snd_ens1373_spdif_mask_get(snd_kcontrol_t * kcontrol, 1359 snd_ctl_elem_value_t * ucontrol) 1360 { 1361 ucontrol->value.iec958.status[0] = 0xff; 1362 ucontrol->value.iec958.status[1] = 0xff; 1363 ucontrol->value.iec958.status[2] = 0xff; 1364 ucontrol->value.iec958.status[3] = 0xff; 1365 return 0; 1366 } 1367 1368 static int snd_ens1373_spdif_stream_get(snd_kcontrol_t * kcontrol, 1369 snd_ctl_elem_value_t * ucontrol) 1370 { 1371 ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol); 1372 spin_lock_irq(&ensoniq->reg_lock); 1373 ucontrol->value.iec958.status[0] = (ensoniq->spdif_stream >> 0) & 0xff; 1374 ucontrol->value.iec958.status[1] = (ensoniq->spdif_stream >> 8) & 0xff; 1375 ucontrol->value.iec958.status[2] = (ensoniq->spdif_stream >> 16) & 0xff; 1376 ucontrol->value.iec958.status[3] = (ensoniq->spdif_stream >> 24) & 0xff; 1377 spin_unlock_irq(&ensoniq->reg_lock); 1378 return 0; 1379 } 1380 1381 static int snd_ens1373_spdif_stream_put(snd_kcontrol_t * kcontrol, 1382 snd_ctl_elem_value_t * ucontrol) 1383 { 1384 ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol); 1385 unsigned int val; 1386 int change; 1387 1388 val = ((u32)ucontrol->value.iec958.status[0] << 0) | 1389 ((u32)ucontrol->value.iec958.status[1] << 8) | 1390 ((u32)ucontrol->value.iec958.status[2] << 16) | 1391 ((u32)ucontrol->value.iec958.status[3] << 24); 1392 spin_lock_irq(&ensoniq->reg_lock); 1393 change = ensoniq->spdif_stream != val; 1394 ensoniq->spdif_stream = val; 1395 if (change && (ensoniq->playback1_substream != NULL || ensoniq->playback2_substream != NULL)) 1396 outl(val, ES_REG(ensoniq, CHANNEL_STATUS)); 1397 spin_unlock_irq(&ensoniq->reg_lock); 1398 return change; 1399 } 1400 1401 #define ES1371_SPDIF(xname) \ 1402 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .info = snd_es1371_spdif_info, \ 1403 .get = snd_es1371_spdif_get, .put = snd_es1371_spdif_put } 1404 1405 static int snd_es1371_spdif_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo) 1406 { 1407 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 1408 uinfo->count = 1; 1409 uinfo->value.integer.min = 0; 1410 uinfo->value.integer.max = 1; 1411 return 0; 1412 } 1413 1414 static int snd_es1371_spdif_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) 1415 { 1416 ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol); 1417 1418 spin_lock_irq(&ensoniq->reg_lock); 1419 ucontrol->value.integer.value[0] = ensoniq->ctrl & ES_1373_SPDIF_THRU ? 1 : 0; 1420 spin_unlock_irq(&ensoniq->reg_lock); 1421 return 0; 1422 } 1423 1424 static int snd_es1371_spdif_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) 1425 { 1426 ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol); 1427 unsigned int nval1, nval2; 1428 int change; 1429 1430 nval1 = ucontrol->value.integer.value[0] ? ES_1373_SPDIF_THRU : 0; 1431 nval2 = ucontrol->value.integer.value[0] ? ES_1373_SPDIF_EN : 0; 1432 spin_lock_irq(&ensoniq->reg_lock); 1433 change = (ensoniq->ctrl & ES_1373_SPDIF_THRU) != nval1; 1434 ensoniq->ctrl &= ~ES_1373_SPDIF_THRU; 1435 ensoniq->ctrl |= nval1; 1436 ensoniq->cssr &= ~ES_1373_SPDIF_EN; 1437 ensoniq->cssr |= nval2; 1438 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 1439 outl(ensoniq->cssr, ES_REG(ensoniq, STATUS)); 1440 spin_unlock_irq(&ensoniq->reg_lock); 1441 return change; 1442 } 1443 1444 1445 /* spdif controls */ 1446 static snd_kcontrol_new_t snd_es1371_mixer_spdif[] __devinitdata = { 1447 ES1371_SPDIF(SNDRV_CTL_NAME_IEC958("",PLAYBACK,SWITCH)), 1448 { 1449 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1450 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT), 1451 .info = snd_ens1373_spdif_info, 1452 .get = snd_ens1373_spdif_default_get, 1453 .put = snd_ens1373_spdif_default_put, 1454 }, 1455 { 1456 .access = SNDRV_CTL_ELEM_ACCESS_READ, 1457 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1458 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK), 1459 .info = snd_ens1373_spdif_info, 1460 .get = snd_ens1373_spdif_mask_get 1461 }, 1462 { 1463 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1464 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM), 1465 .info = snd_ens1373_spdif_info, 1466 .get = snd_ens1373_spdif_stream_get, 1467 .put = snd_ens1373_spdif_stream_put 1468 }, 1469 }; 1470 1471 1472 static int snd_es1373_rear_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo) 1473 { 1474 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 1475 uinfo->count = 1; 1476 uinfo->value.integer.min = 0; 1477 uinfo->value.integer.max = 1; 1478 return 0; 1479 } 1480 1481 static int snd_es1373_rear_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) 1482 { 1483 ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol); 1484 int val = 0; 1485 1486 spin_lock_irq(&ensoniq->reg_lock); 1487 if ((ensoniq->cssr & (ES_1373_REAR_BIT27|ES_1373_REAR_BIT26|ES_1373_REAR_BIT24)) == ES_1373_REAR_BIT26) 1488 val = 1; 1489 ucontrol->value.integer.value[0] = val; 1490 spin_unlock_irq(&ensoniq->reg_lock); 1491 return 0; 1492 } 1493 1494 static int snd_es1373_rear_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) 1495 { 1496 ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol); 1497 unsigned int nval1; 1498 int change; 1499 1500 nval1 = ucontrol->value.integer.value[0] ? ES_1373_REAR_BIT26 : (ES_1373_REAR_BIT27|ES_1373_REAR_BIT24); 1501 spin_lock_irq(&ensoniq->reg_lock); 1502 change = (ensoniq->cssr & (ES_1373_REAR_BIT27|ES_1373_REAR_BIT26|ES_1373_REAR_BIT24)) != nval1; 1503 ensoniq->cssr &= ~(ES_1373_REAR_BIT27|ES_1373_REAR_BIT26|ES_1373_REAR_BIT24); 1504 ensoniq->cssr |= nval1; 1505 outl(ensoniq->cssr, ES_REG(ensoniq, STATUS)); 1506 spin_unlock_irq(&ensoniq->reg_lock); 1507 return change; 1508 } 1509 1510 static snd_kcontrol_new_t snd_ens1373_rear __devinitdata = 1511 { 1512 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 1513 .name = "AC97 2ch->4ch Copy Switch", 1514 .info = snd_es1373_rear_info, 1515 .get = snd_es1373_rear_get, 1516 .put = snd_es1373_rear_put, 1517 }; 1518 1519 static int snd_es1373_line_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo) 1520 { 1521 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 1522 uinfo->count = 1; 1523 uinfo->value.integer.min = 0; 1524 uinfo->value.integer.max = 1; 1525 return 0; 1526 } 1527 1528 static int snd_es1373_line_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) 1529 { 1530 ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol); 1531 int val = 0; 1532 1533 spin_lock_irq(&ensoniq->reg_lock); 1534 if ((ensoniq->ctrl & ES_1371_GPIO_OUTM) >= 4) 1535 val = 1; 1536 ucontrol->value.integer.value[0] = val; 1537 spin_unlock_irq(&ensoniq->reg_lock); 1538 return 0; 1539 } 1540 1541 static int snd_es1373_line_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) 1542 { 1543 ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol); 1544 int changed; 1545 unsigned int ctrl; 1546 1547 spin_lock_irq(&ensoniq->reg_lock); 1548 ctrl = ensoniq->ctrl; 1549 if (ucontrol->value.integer.value[0]) 1550 ensoniq->ctrl |= ES_1371_GPIO_OUT(4); /* switch line-in -> rear out */ 1551 else 1552 ensoniq->ctrl &= ~ES_1371_GPIO_OUT(4); 1553 changed = (ctrl != ensoniq->ctrl); 1554 if (changed) 1555 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 1556 spin_unlock_irq(&ensoniq->reg_lock); 1557 return changed; 1558 } 1559 1560 static snd_kcontrol_new_t snd_ens1373_line __devinitdata = 1561 { 1562 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 1563 .name = "Line In->Rear Out Switch", 1564 .info = snd_es1373_line_info, 1565 .get = snd_es1373_line_get, 1566 .put = snd_es1373_line_put, 1567 }; 1568 1569 static void snd_ensoniq_mixer_free_ac97(ac97_t *ac97) 1570 { 1571 ensoniq_t *ensoniq = ac97->private_data; 1572 ensoniq->u.es1371.ac97 = NULL; 1573 } 1574 1575 static struct { 1576 unsigned short vid; /* vendor ID */ 1577 unsigned short did; /* device ID */ 1578 unsigned char rev; /* revision */ 1579 } es1371_spdif_present[] __devinitdata = { 1580 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_C }, 1581 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_D }, 1582 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_E }, 1583 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_CT5880_A }, 1584 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_ES1373_8 }, 1585 { .vid = PCI_ANY_ID, .did = PCI_ANY_ID } 1586 }; 1587 1588 static int snd_ensoniq_1371_mixer(ensoniq_t * ensoniq) 1589 { 1590 snd_card_t *card = ensoniq->card; 1591 ac97_bus_t *pbus; 1592 ac97_template_t ac97; 1593 int err, idx; 1594 static ac97_bus_ops_t ops = { 1595 .write = snd_es1371_codec_write, 1596 .read = snd_es1371_codec_read, 1597 .wait = snd_es1371_codec_wait, 1598 }; 1599 1600 if ((err = snd_ac97_bus(card, 0, &ops, NULL, &pbus)) < 0) 1601 return err; 1602 1603 memset(&ac97, 0, sizeof(ac97)); 1604 ac97.private_data = ensoniq; 1605 ac97.private_free = snd_ensoniq_mixer_free_ac97; 1606 ac97.scaps = AC97_SCAP_AUDIO; 1607 if ((err = snd_ac97_mixer(pbus, &ac97, &ensoniq->u.es1371.ac97)) < 0) 1608 return err; 1609 for (idx = 0; es1371_spdif_present[idx].vid != (unsigned short)PCI_ANY_ID; idx++) 1610 if (ensoniq->pci->vendor == es1371_spdif_present[idx].vid && 1611 ensoniq->pci->device == es1371_spdif_present[idx].did && 1612 ensoniq->rev == es1371_spdif_present[idx].rev) { 1613 snd_kcontrol_t *kctl; 1614 int i, index = 0; 1615 1616 ensoniq->spdif_default = ensoniq->spdif_stream = SNDRV_PCM_DEFAULT_CON_SPDIF; 1617 outl(ensoniq->spdif_default, ES_REG(ensoniq, CHANNEL_STATUS)); 1618 1619 if (ensoniq->u.es1371.ac97->ext_id & AC97_EI_SPDIF) 1620 index++; 1621 1622 for (i = 0; i < (int)ARRAY_SIZE(snd_es1371_mixer_spdif); i++) { 1623 kctl = snd_ctl_new1(&snd_es1371_mixer_spdif[i], ensoniq); 1624 if (! kctl) 1625 return -ENOMEM; 1626 kctl->id.index = index; 1627 if ((err = snd_ctl_add(card, kctl)) < 0) 1628 return err; 1629 } 1630 break; 1631 } 1632 if (ensoniq->u.es1371.ac97->ext_id & AC97_EI_SDAC) { 1633 /* mirror rear to front speakers */ 1634 ensoniq->cssr &= ~(ES_1373_REAR_BIT27|ES_1373_REAR_BIT24); 1635 ensoniq->cssr |= ES_1373_REAR_BIT26; 1636 err = snd_ctl_add(card, snd_ctl_new1(&snd_ens1373_rear, ensoniq)); 1637 if (err < 0) 1638 return err; 1639 } 1640 if (((ensoniq->subsystem_vendor_id == 0x1274) && 1641 (ensoniq->subsystem_device_id == 0x2000)) || /* GA-7DXR */ 1642 ((ensoniq->subsystem_vendor_id == 0x1458) && 1643 (ensoniq->subsystem_device_id == 0xa000))) { /* GA-8IEXP */ 1644 err = snd_ctl_add(card, snd_ctl_new1(&snd_ens1373_line, ensoniq)); 1645 if (err < 0) 1646 return err; 1647 } 1648 1649 return 0; 1650 } 1651 1652 #endif /* CHIP1371 */ 1653 1654 /* generic control callbacks for ens1370 */ 1655 #ifdef CHIP1370 1656 #define ENSONIQ_CONTROL(xname, mask) \ 1657 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, .name = xname, .info = snd_ensoniq_control_info, \ 1658 .get = snd_ensoniq_control_get, .put = snd_ensoniq_control_put, \ 1659 .private_value = mask } 1660 1661 static int snd_ensoniq_control_info(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo) 1662 { 1663 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 1664 uinfo->count = 1; 1665 uinfo->value.integer.min = 0; 1666 uinfo->value.integer.max = 1; 1667 return 0; 1668 } 1669 1670 static int snd_ensoniq_control_get(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) 1671 { 1672 ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol); 1673 int mask = kcontrol->private_value; 1674 1675 spin_lock_irq(&ensoniq->reg_lock); 1676 ucontrol->value.integer.value[0] = ensoniq->ctrl & mask ? 1 : 0; 1677 spin_unlock_irq(&ensoniq->reg_lock); 1678 return 0; 1679 } 1680 1681 static int snd_ensoniq_control_put(snd_kcontrol_t * kcontrol, snd_ctl_elem_value_t * ucontrol) 1682 { 1683 ensoniq_t *ensoniq = snd_kcontrol_chip(kcontrol); 1684 int mask = kcontrol->private_value; 1685 unsigned int nval; 1686 int change; 1687 1688 nval = ucontrol->value.integer.value[0] ? mask : 0; 1689 spin_lock_irq(&ensoniq->reg_lock); 1690 change = (ensoniq->ctrl & mask) != nval; 1691 ensoniq->ctrl &= ~mask; 1692 ensoniq->ctrl |= nval; 1693 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 1694 spin_unlock_irq(&ensoniq->reg_lock); 1695 return change; 1696 } 1697 1698 /* 1699 * ENS1370 mixer 1700 */ 1701 1702 static snd_kcontrol_new_t snd_es1370_controls[2] __devinitdata = { 1703 ENSONIQ_CONTROL("PCM 0 Output also on Line-In Jack", ES_1370_XCTL0), 1704 ENSONIQ_CONTROL("Mic +5V bias", ES_1370_XCTL1) 1705 }; 1706 1707 #define ES1370_CONTROLS ARRAY_SIZE(snd_es1370_controls) 1708 1709 static void snd_ensoniq_mixer_free_ak4531(ak4531_t *ak4531) 1710 { 1711 ensoniq_t *ensoniq = ak4531->private_data; 1712 ensoniq->u.es1370.ak4531 = NULL; 1713 } 1714 1715 static int __devinit snd_ensoniq_1370_mixer(ensoniq_t * ensoniq) 1716 { 1717 snd_card_t *card = ensoniq->card; 1718 ak4531_t ak4531; 1719 unsigned int idx; 1720 int err; 1721 1722 /* try reset AK4531 */ 1723 outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x02), ES_REG(ensoniq, 1370_CODEC)); 1724 inw(ES_REG(ensoniq, 1370_CODEC)); 1725 udelay(100); 1726 outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x03), ES_REG(ensoniq, 1370_CODEC)); 1727 inw(ES_REG(ensoniq, 1370_CODEC)); 1728 udelay(100); 1729 1730 memset(&ak4531, 0, sizeof(ak4531)); 1731 ak4531.write = snd_es1370_codec_write; 1732 ak4531.private_data = ensoniq; 1733 ak4531.private_free = snd_ensoniq_mixer_free_ak4531; 1734 if ((err = snd_ak4531_mixer(card, &ak4531, &ensoniq->u.es1370.ak4531)) < 0) 1735 return err; 1736 for (idx = 0; idx < ES1370_CONTROLS; idx++) { 1737 err = snd_ctl_add(card, snd_ctl_new1(&snd_es1370_controls[idx], ensoniq)); 1738 if (err < 0) 1739 return err; 1740 } 1741 return 0; 1742 } 1743 1744 #endif /* CHIP1370 */ 1745 1746 #ifdef SUPPORT_JOYSTICK 1747 1748 #ifdef CHIP1371 1749 static int __devinit snd_ensoniq_get_joystick_port(int dev) 1750 { 1751 switch (joystick_port[dev]) { 1752 case 0: /* disabled */ 1753 case 1: /* auto-detect */ 1754 case 0x200: 1755 case 0x208: 1756 case 0x210: 1757 case 0x218: 1758 return joystick_port[dev]; 1759 1760 default: 1761 printk(KERN_ERR "ens1371: invalid joystick port %#x", joystick_port[dev]); 1762 return 0; 1763 } 1764 } 1765 #else 1766 static inline int snd_ensoniq_get_joystick_port(int dev) 1767 { 1768 return joystick[dev] ? 0x200 : 0; 1769 } 1770 #endif 1771 1772 static int __devinit snd_ensoniq_create_gameport(ensoniq_t *ensoniq, int dev) 1773 { 1774 struct gameport *gp; 1775 int io_port; 1776 1777 io_port = snd_ensoniq_get_joystick_port(dev); 1778 1779 switch (io_port) { 1780 case 0: 1781 return -ENOSYS; 1782 1783 case 1: /* auto_detect */ 1784 for (io_port = 0x200; io_port <= 0x218; io_port += 8) 1785 if (request_region(io_port, 8, "ens137x: gameport")) 1786 break; 1787 if (io_port > 0x218) { 1788 printk(KERN_WARNING "ens137x: no gameport ports available\n"); 1789 return -EBUSY; 1790 } 1791 break; 1792 1793 default: 1794 if (!request_region(io_port, 8, "ens137x: gameport")) { 1795 printk(KERN_WARNING "ens137x: gameport io port 0x%#x in use\n", io_port); 1796 return -EBUSY; 1797 } 1798 break; 1799 } 1800 1801 ensoniq->gameport = gp = gameport_allocate_port(); 1802 if (!gp) { 1803 printk(KERN_ERR "ens137x: cannot allocate memory for gameport\n"); 1804 release_region(io_port, 8); 1805 return -ENOMEM; 1806 } 1807 1808 gameport_set_name(gp, "ES137x"); 1809 gameport_set_phys(gp, "pci%s/gameport0", pci_name(ensoniq->pci)); 1810 gameport_set_dev_parent(gp, &ensoniq->pci->dev); 1811 gp->io = io_port; 1812 1813 ensoniq->ctrl |= ES_JYSTK_EN; 1814 #ifdef CHIP1371 1815 ensoniq->ctrl &= ~ES_1371_JOY_ASELM; 1816 ensoniq->ctrl |= ES_1371_JOY_ASEL((io_port - 0x200) / 8); 1817 #endif 1818 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 1819 1820 gameport_register_port(ensoniq->gameport); 1821 1822 return 0; 1823 } 1824 1825 static void snd_ensoniq_free_gameport(ensoniq_t *ensoniq) 1826 { 1827 if (ensoniq->gameport) { 1828 int port = ensoniq->gameport->io; 1829 1830 gameport_unregister_port(ensoniq->gameport); 1831 ensoniq->gameport = NULL; 1832 ensoniq->ctrl &= ~ES_JYSTK_EN; 1833 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 1834 release_region(port, 8); 1835 } 1836 } 1837 #else 1838 static inline int snd_ensoniq_create_gameport(ensoniq_t *ensoniq, long port) { return -ENOSYS; } 1839 static inline void snd_ensoniq_free_gameport(ensoniq_t *ensoniq) { } 1840 #endif /* SUPPORT_JOYSTICK */ 1841 1842 /* 1843 1844 */ 1845 1846 static void snd_ensoniq_proc_read(snd_info_entry_t *entry, 1847 snd_info_buffer_t * buffer) 1848 { 1849 ensoniq_t *ensoniq = entry->private_data; 1850 1851 #ifdef CHIP1370 1852 snd_iprintf(buffer, "Ensoniq AudioPCI ES1370\n\n"); 1853 #else 1854 snd_iprintf(buffer, "Ensoniq AudioPCI ES1371\n\n"); 1855 #endif 1856 snd_iprintf(buffer, "Joystick enable : %s\n", ensoniq->ctrl & ES_JYSTK_EN ? "on" : "off"); 1857 #ifdef CHIP1370 1858 snd_iprintf(buffer, "MIC +5V bias : %s\n", ensoniq->ctrl & ES_1370_XCTL1 ? "on" : "off"); 1859 snd_iprintf(buffer, "Line In to AOUT : %s\n", ensoniq->ctrl & ES_1370_XCTL0 ? "on" : "off"); 1860 #else 1861 snd_iprintf(buffer, "Joystick port : 0x%x\n", (ES_1371_JOY_ASELI(ensoniq->ctrl) * 8) + 0x200); 1862 #endif 1863 } 1864 1865 static void __devinit snd_ensoniq_proc_init(ensoniq_t * ensoniq) 1866 { 1867 snd_info_entry_t *entry; 1868 1869 if (! snd_card_proc_new(ensoniq->card, "audiopci", &entry)) 1870 snd_info_set_text_ops(entry, ensoniq, 1024, snd_ensoniq_proc_read); 1871 } 1872 1873 /* 1874 1875 */ 1876 1877 static int snd_ensoniq_free(ensoniq_t *ensoniq) 1878 { 1879 snd_ensoniq_free_gameport(ensoniq); 1880 if (ensoniq->irq < 0) 1881 goto __hw_end; 1882 #ifdef CHIP1370 1883 outl(ES_1370_SERR_DISABLE, ES_REG(ensoniq, CONTROL)); /* switch everything off */ 1884 outl(0, ES_REG(ensoniq, SERIAL)); /* clear serial interface */ 1885 #else 1886 outl(0, ES_REG(ensoniq, CONTROL)); /* switch everything off */ 1887 outl(0, ES_REG(ensoniq, SERIAL)); /* clear serial interface */ 1888 #endif 1889 synchronize_irq(ensoniq->irq); 1890 pci_set_power_state(ensoniq->pci, 3); 1891 __hw_end: 1892 #ifdef CHIP1370 1893 if (ensoniq->dma_bug.area) 1894 snd_dma_free_pages(&ensoniq->dma_bug); 1895 #endif 1896 if (ensoniq->irq >= 0) 1897 free_irq(ensoniq->irq, (void *)ensoniq); 1898 pci_release_regions(ensoniq->pci); 1899 pci_disable_device(ensoniq->pci); 1900 kfree(ensoniq); 1901 return 0; 1902 } 1903 1904 static int snd_ensoniq_dev_free(snd_device_t *device) 1905 { 1906 ensoniq_t *ensoniq = device->device_data; 1907 return snd_ensoniq_free(ensoniq); 1908 } 1909 1910 #ifdef CHIP1371 1911 static struct { 1912 unsigned short svid; /* subsystem vendor ID */ 1913 unsigned short sdid; /* subsystem device ID */ 1914 } es1371_amplifier_hack[] = { 1915 { .svid = 0x107b, .sdid = 0x2150 }, /* Gateway Solo 2150 */ 1916 { .svid = 0x13bd, .sdid = 0x100c }, /* EV1938 on Mebius PC-MJ100V */ 1917 { .svid = 0x1102, .sdid = 0x5938 }, /* Targa Xtender300 */ 1918 { .svid = 0x1102, .sdid = 0x8938 }, /* IPC Topnote G notebook */ 1919 { .svid = PCI_ANY_ID, .sdid = PCI_ANY_ID } 1920 }; 1921 static struct { 1922 unsigned short vid; /* vendor ID */ 1923 unsigned short did; /* device ID */ 1924 unsigned char rev; /* revision */ 1925 } es1371_ac97_reset_hack[] = { 1926 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_C }, 1927 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_D }, 1928 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_E }, 1929 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_CT5880_A }, 1930 { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_ES1373_8 }, 1931 { .vid = PCI_ANY_ID, .did = PCI_ANY_ID } 1932 }; 1933 #endif 1934 1935 static int __devinit snd_ensoniq_create(snd_card_t * card, 1936 struct pci_dev *pci, 1937 ensoniq_t ** rensoniq) 1938 { 1939 ensoniq_t *ensoniq; 1940 unsigned short cmdw; 1941 unsigned char cmdb; 1942 #ifdef CHIP1371 1943 int idx; 1944 #endif 1945 int err; 1946 static snd_device_ops_t ops = { 1947 .dev_free = snd_ensoniq_dev_free, 1948 }; 1949 1950 *rensoniq = NULL; 1951 if ((err = pci_enable_device(pci)) < 0) 1952 return err; 1953 ensoniq = kcalloc(1, sizeof(*ensoniq), GFP_KERNEL); 1954 if (ensoniq == NULL) { 1955 pci_disable_device(pci); 1956 return -ENOMEM; 1957 } 1958 spin_lock_init(&ensoniq->reg_lock); 1959 init_MUTEX(&ensoniq->src_mutex); 1960 ensoniq->card = card; 1961 ensoniq->pci = pci; 1962 ensoniq->irq = -1; 1963 if ((err = pci_request_regions(pci, "Ensoniq AudioPCI")) < 0) { 1964 kfree(ensoniq); 1965 pci_disable_device(pci); 1966 return err; 1967 } 1968 ensoniq->port = pci_resource_start(pci, 0); 1969 if (request_irq(pci->irq, snd_audiopci_interrupt, SA_INTERRUPT|SA_SHIRQ, "Ensoniq AudioPCI", (void *)ensoniq)) { 1970 snd_printk("unable to grab IRQ %d\n", pci->irq); 1971 snd_ensoniq_free(ensoniq); 1972 return -EBUSY; 1973 } 1974 ensoniq->irq = pci->irq; 1975 #ifdef CHIP1370 1976 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci), 1977 16, &ensoniq->dma_bug) < 0) { 1978 snd_printk("unable to allocate space for phantom area - dma_bug\n"); 1979 snd_ensoniq_free(ensoniq); 1980 return -EBUSY; 1981 } 1982 #endif 1983 pci_set_master(pci); 1984 pci_read_config_byte(pci, PCI_REVISION_ID, &cmdb); 1985 ensoniq->rev = cmdb; 1986 pci_read_config_word(pci, PCI_SUBSYSTEM_VENDOR_ID, &cmdw); 1987 ensoniq->subsystem_vendor_id = cmdw; 1988 pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &cmdw); 1989 ensoniq->subsystem_device_id = cmdw; 1990 #ifdef CHIP1370 1991 #if 0 1992 ensoniq->ctrl = ES_1370_CDC_EN | ES_1370_SERR_DISABLE | ES_1370_PCLKDIVO(ES_1370_SRTODIV(8000)); 1993 #else /* get microphone working */ 1994 ensoniq->ctrl = ES_1370_CDC_EN | ES_1370_PCLKDIVO(ES_1370_SRTODIV(8000)); 1995 #endif 1996 ensoniq->sctrl = 0; 1997 /* initialize the chips */ 1998 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 1999 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL)); 2000 outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE)); 2001 outl(ensoniq->dma_bug.addr, ES_REG(ensoniq, PHANTOM_FRAME)); 2002 outl(0, ES_REG(ensoniq, PHANTOM_COUNT)); 2003 #else 2004 ensoniq->ctrl = 0; 2005 ensoniq->sctrl = 0; 2006 ensoniq->cssr = 0; 2007 for (idx = 0; es1371_amplifier_hack[idx].svid != (unsigned short)PCI_ANY_ID; idx++) 2008 if (ensoniq->subsystem_vendor_id == es1371_amplifier_hack[idx].svid && 2009 ensoniq->subsystem_device_id == es1371_amplifier_hack[idx].sdid) { 2010 ensoniq->ctrl |= ES_1371_GPIO_OUT(1); /* turn amplifier on */ 2011 break; 2012 } 2013 /* initialize the chips */ 2014 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 2015 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL)); 2016 outl(0, ES_REG(ensoniq, 1371_LEGACY)); 2017 for (idx = 0; es1371_ac97_reset_hack[idx].vid != (unsigned short)PCI_ANY_ID; idx++) 2018 if (pci->vendor == es1371_ac97_reset_hack[idx].vid && 2019 pci->device == es1371_ac97_reset_hack[idx].did && 2020 ensoniq->rev == es1371_ac97_reset_hack[idx].rev) { 2021 ensoniq->cssr |= ES_1371_ST_AC97_RST; 2022 outl(ensoniq->cssr, ES_REG(ensoniq, STATUS)); 2023 /* need to delay around 20ms(bleech) to give 2024 some CODECs enough time to wakeup */ 2025 msleep(20); 2026 break; 2027 } 2028 /* AC'97 warm reset to start the bitclk */ 2029 outl(ensoniq->ctrl | ES_1371_SYNC_RES, ES_REG(ensoniq, CONTROL)); 2030 inl(ES_REG(ensoniq, CONTROL)); 2031 udelay(20); 2032 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); 2033 /* Init the sample rate converter */ 2034 snd_es1371_wait_src_ready(ensoniq); 2035 outl(ES_1371_SRC_DISABLE, ES_REG(ensoniq, 1371_SMPRATE)); 2036 for (idx = 0; idx < 0x80; idx++) 2037 snd_es1371_src_write(ensoniq, idx, 0); 2038 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_TRUNC_N, 16 << 4); 2039 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS, 16 << 10); 2040 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_TRUNC_N, 16 << 4); 2041 snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS, 16 << 10); 2042 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC, 1 << 12); 2043 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC + 1, 1 << 12); 2044 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC1, 1 << 12); 2045 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC1 + 1, 1 << 12); 2046 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC2, 1 << 12); 2047 snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC2 + 1, 1 << 12); 2048 snd_es1371_adc_rate(ensoniq, 22050); 2049 snd_es1371_dac1_rate(ensoniq, 22050); 2050 snd_es1371_dac2_rate(ensoniq, 22050); 2051 /* WARNING: 2052 * enabling the sample rate converter without properly programming 2053 * its parameters causes the chip to lock up (the SRC busy bit will 2054 * be stuck high, and I've found no way to rectify this other than 2055 * power cycle) - Thomas Sailer 2056 */ 2057 snd_es1371_wait_src_ready(ensoniq); 2058 outl(0, ES_REG(ensoniq, 1371_SMPRATE)); 2059 /* try reset codec directly */ 2060 outl(ES_1371_CODEC_WRITE(0, 0), ES_REG(ensoniq, 1371_CODEC)); 2061 #endif 2062 outb(ensoniq->uartc = 0x00, ES_REG(ensoniq, UART_CONTROL)); 2063 outb(0x00, ES_REG(ensoniq, UART_RES)); 2064 outl(ensoniq->cssr, ES_REG(ensoniq, STATUS)); 2065 synchronize_irq(ensoniq->irq); 2066 2067 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, ensoniq, &ops)) < 0) { 2068 snd_ensoniq_free(ensoniq); 2069 return err; 2070 } 2071 2072 snd_ensoniq_proc_init(ensoniq); 2073 2074 snd_card_set_dev(card, &pci->dev); 2075 2076 *rensoniq = ensoniq; 2077 return 0; 2078 } 2079 2080 /* 2081 * MIDI section 2082 */ 2083 2084 static void snd_ensoniq_midi_interrupt(ensoniq_t * ensoniq) 2085 { 2086 snd_rawmidi_t * rmidi = ensoniq->rmidi; 2087 unsigned char status, mask, byte; 2088 2089 if (rmidi == NULL) 2090 return; 2091 /* do Rx at first */ 2092 spin_lock(&ensoniq->reg_lock); 2093 mask = ensoniq->uartm & ES_MODE_INPUT ? ES_RXRDY : 0; 2094 while (mask) { 2095 status = inb(ES_REG(ensoniq, UART_STATUS)); 2096 if ((status & mask) == 0) 2097 break; 2098 byte = inb(ES_REG(ensoniq, UART_DATA)); 2099 snd_rawmidi_receive(ensoniq->midi_input, &byte, 1); 2100 } 2101 spin_unlock(&ensoniq->reg_lock); 2102 2103 /* do Tx at second */ 2104 spin_lock(&ensoniq->reg_lock); 2105 mask = ensoniq->uartm & ES_MODE_OUTPUT ? ES_TXRDY : 0; 2106 while (mask) { 2107 status = inb(ES_REG(ensoniq, UART_STATUS)); 2108 if ((status & mask) == 0) 2109 break; 2110 if (snd_rawmidi_transmit(ensoniq->midi_output, &byte, 1) != 1) { 2111 ensoniq->uartc &= ~ES_TXINTENM; 2112 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL)); 2113 mask &= ~ES_TXRDY; 2114 } else { 2115 outb(byte, ES_REG(ensoniq, UART_DATA)); 2116 } 2117 } 2118 spin_unlock(&ensoniq->reg_lock); 2119 } 2120 2121 static int snd_ensoniq_midi_input_open(snd_rawmidi_substream_t * substream) 2122 { 2123 ensoniq_t *ensoniq = substream->rmidi->private_data; 2124 2125 spin_lock_irq(&ensoniq->reg_lock); 2126 ensoniq->uartm |= ES_MODE_INPUT; 2127 ensoniq->midi_input = substream; 2128 if (!(ensoniq->uartm & ES_MODE_OUTPUT)) { 2129 outb(ES_CNTRL(3), ES_REG(ensoniq, UART_CONTROL)); 2130 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL)); 2131 outl(ensoniq->ctrl |= ES_UART_EN, ES_REG(ensoniq, CONTROL)); 2132 } 2133 spin_unlock_irq(&ensoniq->reg_lock); 2134 return 0; 2135 } 2136 2137 static int snd_ensoniq_midi_input_close(snd_rawmidi_substream_t * substream) 2138 { 2139 ensoniq_t *ensoniq = substream->rmidi->private_data; 2140 2141 spin_lock_irq(&ensoniq->reg_lock); 2142 if (!(ensoniq->uartm & ES_MODE_OUTPUT)) { 2143 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL)); 2144 outl(ensoniq->ctrl &= ~ES_UART_EN, ES_REG(ensoniq, CONTROL)); 2145 } else { 2146 outb(ensoniq->uartc &= ~ES_RXINTEN, ES_REG(ensoniq, UART_CONTROL)); 2147 } 2148 ensoniq->midi_input = NULL; 2149 ensoniq->uartm &= ~ES_MODE_INPUT; 2150 spin_unlock_irq(&ensoniq->reg_lock); 2151 return 0; 2152 } 2153 2154 static int snd_ensoniq_midi_output_open(snd_rawmidi_substream_t * substream) 2155 { 2156 ensoniq_t *ensoniq = substream->rmidi->private_data; 2157 2158 spin_lock_irq(&ensoniq->reg_lock); 2159 ensoniq->uartm |= ES_MODE_OUTPUT; 2160 ensoniq->midi_output = substream; 2161 if (!(ensoniq->uartm & ES_MODE_INPUT)) { 2162 outb(ES_CNTRL(3), ES_REG(ensoniq, UART_CONTROL)); 2163 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL)); 2164 outl(ensoniq->ctrl |= ES_UART_EN, ES_REG(ensoniq, CONTROL)); 2165 } 2166 spin_unlock_irq(&ensoniq->reg_lock); 2167 return 0; 2168 } 2169 2170 static int snd_ensoniq_midi_output_close(snd_rawmidi_substream_t * substream) 2171 { 2172 ensoniq_t *ensoniq = substream->rmidi->private_data; 2173 2174 spin_lock_irq(&ensoniq->reg_lock); 2175 if (!(ensoniq->uartm & ES_MODE_INPUT)) { 2176 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL)); 2177 outl(ensoniq->ctrl &= ~ES_UART_EN, ES_REG(ensoniq, CONTROL)); 2178 } else { 2179 outb(ensoniq->uartc &= ~ES_TXINTENM, ES_REG(ensoniq, UART_CONTROL)); 2180 } 2181 ensoniq->midi_output = NULL; 2182 ensoniq->uartm &= ~ES_MODE_OUTPUT; 2183 spin_unlock_irq(&ensoniq->reg_lock); 2184 return 0; 2185 } 2186 2187 static void snd_ensoniq_midi_input_trigger(snd_rawmidi_substream_t * substream, int up) 2188 { 2189 unsigned long flags; 2190 ensoniq_t *ensoniq = substream->rmidi->private_data; 2191 int idx; 2192 2193 spin_lock_irqsave(&ensoniq->reg_lock, flags); 2194 if (up) { 2195 if ((ensoniq->uartc & ES_RXINTEN) == 0) { 2196 /* empty input FIFO */ 2197 for (idx = 0; idx < 32; idx++) 2198 inb(ES_REG(ensoniq, UART_DATA)); 2199 ensoniq->uartc |= ES_RXINTEN; 2200 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL)); 2201 } 2202 } else { 2203 if (ensoniq->uartc & ES_RXINTEN) { 2204 ensoniq->uartc &= ~ES_RXINTEN; 2205 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL)); 2206 } 2207 } 2208 spin_unlock_irqrestore(&ensoniq->reg_lock, flags); 2209 } 2210 2211 static void snd_ensoniq_midi_output_trigger(snd_rawmidi_substream_t * substream, int up) 2212 { 2213 unsigned long flags; 2214 ensoniq_t *ensoniq = substream->rmidi->private_data; 2215 unsigned char byte; 2216 2217 spin_lock_irqsave(&ensoniq->reg_lock, flags); 2218 if (up) { 2219 if (ES_TXINTENI(ensoniq->uartc) == 0) { 2220 ensoniq->uartc |= ES_TXINTENO(1); 2221 /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */ 2222 while (ES_TXINTENI(ensoniq->uartc) == 1 && 2223 (inb(ES_REG(ensoniq, UART_STATUS)) & ES_TXRDY)) { 2224 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) { 2225 ensoniq->uartc &= ~ES_TXINTENM; 2226 } else { 2227 outb(byte, ES_REG(ensoniq, UART_DATA)); 2228 } 2229 } 2230 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL)); 2231 } 2232 } else { 2233 if (ES_TXINTENI(ensoniq->uartc) == 1) { 2234 ensoniq->uartc &= ~ES_TXINTENM; 2235 outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL)); 2236 } 2237 } 2238 spin_unlock_irqrestore(&ensoniq->reg_lock, flags); 2239 } 2240 2241 static snd_rawmidi_ops_t snd_ensoniq_midi_output = 2242 { 2243 .open = snd_ensoniq_midi_output_open, 2244 .close = snd_ensoniq_midi_output_close, 2245 .trigger = snd_ensoniq_midi_output_trigger, 2246 }; 2247 2248 static snd_rawmidi_ops_t snd_ensoniq_midi_input = 2249 { 2250 .open = snd_ensoniq_midi_input_open, 2251 .close = snd_ensoniq_midi_input_close, 2252 .trigger = snd_ensoniq_midi_input_trigger, 2253 }; 2254 2255 static int __devinit snd_ensoniq_midi(ensoniq_t * ensoniq, int device, snd_rawmidi_t **rrawmidi) 2256 { 2257 snd_rawmidi_t *rmidi; 2258 int err; 2259 2260 if (rrawmidi) 2261 *rrawmidi = NULL; 2262 if ((err = snd_rawmidi_new(ensoniq->card, "ES1370/1", device, 1, 1, &rmidi)) < 0) 2263 return err; 2264 #ifdef CHIP1370 2265 strcpy(rmidi->name, "ES1370"); 2266 #else 2267 strcpy(rmidi->name, "ES1371"); 2268 #endif 2269 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_ensoniq_midi_output); 2270 snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_ensoniq_midi_input); 2271 rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | SNDRV_RAWMIDI_INFO_DUPLEX; 2272 rmidi->private_data = ensoniq; 2273 ensoniq->rmidi = rmidi; 2274 if (rrawmidi) 2275 *rrawmidi = rmidi; 2276 return 0; 2277 } 2278 2279 /* 2280 * Interrupt handler 2281 */ 2282 2283 static irqreturn_t snd_audiopci_interrupt(int irq, void *dev_id, struct pt_regs *regs) 2284 { 2285 ensoniq_t *ensoniq = dev_id; 2286 unsigned int status, sctrl; 2287 2288 if (ensoniq == NULL) 2289 return IRQ_NONE; 2290 2291 status = inl(ES_REG(ensoniq, STATUS)); 2292 if (!(status & ES_INTR)) 2293 return IRQ_NONE; 2294 2295 spin_lock(&ensoniq->reg_lock); 2296 sctrl = ensoniq->sctrl; 2297 if (status & ES_DAC1) 2298 sctrl &= ~ES_P1_INT_EN; 2299 if (status & ES_DAC2) 2300 sctrl &= ~ES_P2_INT_EN; 2301 if (status & ES_ADC) 2302 sctrl &= ~ES_R1_INT_EN; 2303 outl(sctrl, ES_REG(ensoniq, SERIAL)); 2304 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL)); 2305 spin_unlock(&ensoniq->reg_lock); 2306 2307 if (status & ES_UART) 2308 snd_ensoniq_midi_interrupt(ensoniq); 2309 if ((status & ES_DAC2) && ensoniq->playback2_substream) 2310 snd_pcm_period_elapsed(ensoniq->playback2_substream); 2311 if ((status & ES_ADC) && ensoniq->capture_substream) 2312 snd_pcm_period_elapsed(ensoniq->capture_substream); 2313 if ((status & ES_DAC1) && ensoniq->playback1_substream) 2314 snd_pcm_period_elapsed(ensoniq->playback1_substream); 2315 return IRQ_HANDLED; 2316 } 2317 2318 static int __devinit snd_audiopci_probe(struct pci_dev *pci, 2319 const struct pci_device_id *pci_id) 2320 { 2321 static int dev; 2322 snd_card_t *card; 2323 ensoniq_t *ensoniq; 2324 int err, pcm_devs[2]; 2325 2326 if (dev >= SNDRV_CARDS) 2327 return -ENODEV; 2328 if (!enable[dev]) { 2329 dev++; 2330 return -ENOENT; 2331 } 2332 2333 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0); 2334 if (card == NULL) 2335 return -ENOMEM; 2336 2337 if ((err = snd_ensoniq_create(card, pci, &ensoniq)) < 0) { 2338 snd_card_free(card); 2339 return err; 2340 } 2341 2342 pcm_devs[0] = 0; pcm_devs[1] = 1; 2343 #ifdef CHIP1370 2344 if ((err = snd_ensoniq_1370_mixer(ensoniq)) < 0) { 2345 snd_card_free(card); 2346 return err; 2347 } 2348 #endif 2349 #ifdef CHIP1371 2350 if ((err = snd_ensoniq_1371_mixer(ensoniq)) < 0) { 2351 snd_card_free(card); 2352 return err; 2353 } 2354 #endif 2355 if ((err = snd_ensoniq_pcm(ensoniq, 0, NULL)) < 0) { 2356 snd_card_free(card); 2357 return err; 2358 } 2359 if ((err = snd_ensoniq_pcm2(ensoniq, 1, NULL)) < 0) { 2360 snd_card_free(card); 2361 return err; 2362 } 2363 if ((err = snd_ensoniq_midi(ensoniq, 0, NULL)) < 0) { 2364 snd_card_free(card); 2365 return err; 2366 } 2367 2368 snd_ensoniq_create_gameport(ensoniq, dev); 2369 2370 strcpy(card->driver, DRIVER_NAME); 2371 2372 strcpy(card->shortname, "Ensoniq AudioPCI"); 2373 sprintf(card->longname, "%s %s at 0x%lx, irq %i", 2374 card->shortname, 2375 card->driver, 2376 ensoniq->port, 2377 ensoniq->irq); 2378 2379 if ((err = snd_card_register(card)) < 0) { 2380 snd_card_free(card); 2381 return err; 2382 } 2383 2384 pci_set_drvdata(pci, card); 2385 dev++; 2386 return 0; 2387 } 2388 2389 static void __devexit snd_audiopci_remove(struct pci_dev *pci) 2390 { 2391 snd_card_free(pci_get_drvdata(pci)); 2392 pci_set_drvdata(pci, NULL); 2393 } 2394 2395 static struct pci_driver driver = { 2396 .name = DRIVER_NAME, 2397 .id_table = snd_audiopci_ids, 2398 .probe = snd_audiopci_probe, 2399 .remove = __devexit_p(snd_audiopci_remove), 2400 }; 2401 2402 static int __init alsa_card_ens137x_init(void) 2403 { 2404 return pci_register_driver(&driver); 2405 } 2406 2407 static void __exit alsa_card_ens137x_exit(void) 2408 { 2409 pci_unregister_driver(&driver); 2410 } 2411 2412 module_init(alsa_card_ens137x_init) 2413 module_exit(alsa_card_ens137x_exit) 2414