1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (c) by Jaroslav Kysela <perex@perex.cz> 4 * Creative Labs, Inc. 5 * Routines for control of EMU10K1 chips 6 * 7 * BUGS: 8 * -- 9 * 10 * TODO: 11 * -- 12 */ 13 14 #include <linux/time.h> 15 #include <sound/core.h> 16 #include <sound/emu10k1.h> 17 #include <linux/delay.h> 18 #include <linux/export.h> 19 #include "p17v.h" 20 21 static inline bool check_ptr_reg(struct snd_emu10k1 *emu, unsigned int reg) 22 { 23 if (snd_BUG_ON(!emu)) 24 return false; 25 if (snd_BUG_ON(reg & (emu->audigy ? (0xffff0000 & ~A_PTR_ADDRESS_MASK) 26 : (0xffff0000 & ~PTR_ADDRESS_MASK)))) 27 return false; 28 if (snd_BUG_ON(reg & 0x0000ffff & ~PTR_CHANNELNUM_MASK)) 29 return false; 30 return true; 31 } 32 33 unsigned int snd_emu10k1_ptr_read(struct snd_emu10k1 * emu, unsigned int reg, unsigned int chn) 34 { 35 unsigned long flags; 36 unsigned int regptr, val; 37 unsigned int mask; 38 39 regptr = (reg << 16) | chn; 40 if (!check_ptr_reg(emu, regptr)) 41 return 0; 42 43 spin_lock_irqsave(&emu->emu_lock, flags); 44 outl(regptr, emu->port + PTR); 45 val = inl(emu->port + DATA); 46 spin_unlock_irqrestore(&emu->emu_lock, flags); 47 48 if (reg & 0xff000000) { 49 unsigned char size, offset; 50 51 size = (reg >> 24) & 0x3f; 52 offset = (reg >> 16) & 0x1f; 53 mask = (1 << size) - 1; 54 55 return (val >> offset) & mask; 56 } else { 57 return val; 58 } 59 } 60 61 EXPORT_SYMBOL(snd_emu10k1_ptr_read); 62 63 void snd_emu10k1_ptr_write(struct snd_emu10k1 *emu, unsigned int reg, unsigned int chn, unsigned int data) 64 { 65 unsigned int regptr; 66 unsigned long flags; 67 unsigned int mask; 68 69 regptr = (reg << 16) | chn; 70 if (!check_ptr_reg(emu, regptr)) 71 return; 72 73 if (reg & 0xff000000) { 74 unsigned char size, offset; 75 76 size = (reg >> 24) & 0x3f; 77 offset = (reg >> 16) & 0x1f; 78 mask = (1 << size) - 1; 79 if (snd_BUG_ON(data & ~mask)) 80 return; 81 mask <<= offset; 82 data <<= offset; 83 84 spin_lock_irqsave(&emu->emu_lock, flags); 85 outl(regptr, emu->port + PTR); 86 data |= inl(emu->port + DATA) & ~mask; 87 } else { 88 spin_lock_irqsave(&emu->emu_lock, flags); 89 outl(regptr, emu->port + PTR); 90 } 91 outl(data, emu->port + DATA); 92 spin_unlock_irqrestore(&emu->emu_lock, flags); 93 } 94 95 EXPORT_SYMBOL(snd_emu10k1_ptr_write); 96 97 void snd_emu10k1_ptr_write_multiple(struct snd_emu10k1 *emu, unsigned int chn, ...) 98 { 99 va_list va; 100 u32 addr_mask; 101 unsigned long flags; 102 103 if (snd_BUG_ON(!emu)) 104 return; 105 if (snd_BUG_ON(chn & ~PTR_CHANNELNUM_MASK)) 106 return; 107 addr_mask = ~((emu->audigy ? A_PTR_ADDRESS_MASK : PTR_ADDRESS_MASK) >> 16); 108 109 va_start(va, chn); 110 spin_lock_irqsave(&emu->emu_lock, flags); 111 for (;;) { 112 u32 data; 113 u32 reg = va_arg(va, u32); 114 if (reg == REGLIST_END) 115 break; 116 data = va_arg(va, u32); 117 if (snd_BUG_ON(reg & addr_mask)) // Only raw registers supported here 118 continue; 119 outl((reg << 16) | chn, emu->port + PTR); 120 outl(data, emu->port + DATA); 121 } 122 spin_unlock_irqrestore(&emu->emu_lock, flags); 123 va_end(va); 124 } 125 126 EXPORT_SYMBOL(snd_emu10k1_ptr_write_multiple); 127 128 unsigned int snd_emu10k1_ptr20_read(struct snd_emu10k1 * emu, 129 unsigned int reg, 130 unsigned int chn) 131 { 132 unsigned long flags; 133 unsigned int regptr, val; 134 135 regptr = (reg << 16) | chn; 136 137 spin_lock_irqsave(&emu->emu_lock, flags); 138 outl(regptr, emu->port + PTR2); 139 val = inl(emu->port + DATA2); 140 spin_unlock_irqrestore(&emu->emu_lock, flags); 141 return val; 142 } 143 144 void snd_emu10k1_ptr20_write(struct snd_emu10k1 *emu, 145 unsigned int reg, 146 unsigned int chn, 147 unsigned int data) 148 { 149 unsigned int regptr; 150 unsigned long flags; 151 152 regptr = (reg << 16) | chn; 153 154 spin_lock_irqsave(&emu->emu_lock, flags); 155 outl(regptr, emu->port + PTR2); 156 outl(data, emu->port + DATA2); 157 spin_unlock_irqrestore(&emu->emu_lock, flags); 158 } 159 160 int snd_emu10k1_spi_write(struct snd_emu10k1 * emu, 161 unsigned int data) 162 { 163 unsigned int reset, set; 164 unsigned int reg, tmp; 165 int n, result; 166 int err = 0; 167 168 /* This function is not re-entrant, so protect against it. */ 169 spin_lock(&emu->spi_lock); 170 if (emu->card_capabilities->ca0108_chip) 171 reg = P17V_SPI; 172 else { 173 /* For other chip types the SPI register 174 * is currently unknown. */ 175 err = 1; 176 goto spi_write_exit; 177 } 178 if (data > 0xffff) { 179 /* Only 16bit values allowed */ 180 err = 1; 181 goto spi_write_exit; 182 } 183 184 tmp = snd_emu10k1_ptr20_read(emu, reg, 0); 185 reset = (tmp & ~0x3ffff) | 0x20000; /* Set xxx20000 */ 186 set = reset | 0x10000; /* Set xxx1xxxx */ 187 snd_emu10k1_ptr20_write(emu, reg, 0, reset | data); 188 tmp = snd_emu10k1_ptr20_read(emu, reg, 0); /* write post */ 189 snd_emu10k1_ptr20_write(emu, reg, 0, set | data); 190 result = 1; 191 /* Wait for status bit to return to 0 */ 192 for (n = 0; n < 100; n++) { 193 udelay(10); 194 tmp = snd_emu10k1_ptr20_read(emu, reg, 0); 195 if (!(tmp & 0x10000)) { 196 result = 0; 197 break; 198 } 199 } 200 if (result) { 201 /* Timed out */ 202 err = 1; 203 goto spi_write_exit; 204 } 205 snd_emu10k1_ptr20_write(emu, reg, 0, reset | data); 206 tmp = snd_emu10k1_ptr20_read(emu, reg, 0); /* Write post */ 207 err = 0; 208 spi_write_exit: 209 spin_unlock(&emu->spi_lock); 210 return err; 211 } 212 213 /* The ADC does not support i2c read, so only write is implemented */ 214 int snd_emu10k1_i2c_write(struct snd_emu10k1 *emu, 215 u32 reg, 216 u32 value) 217 { 218 u32 tmp; 219 int timeout = 0; 220 int status; 221 int retry; 222 int err = 0; 223 224 if ((reg > 0x7f) || (value > 0x1ff)) { 225 dev_err(emu->card->dev, "i2c_write: invalid values.\n"); 226 return -EINVAL; 227 } 228 229 /* This function is not re-entrant, so protect against it. */ 230 spin_lock(&emu->i2c_lock); 231 232 tmp = reg << 25 | value << 16; 233 234 /* This controls the I2C connected to the WM8775 ADC Codec */ 235 snd_emu10k1_ptr20_write(emu, P17V_I2C_1, 0, tmp); 236 tmp = snd_emu10k1_ptr20_read(emu, P17V_I2C_1, 0); /* write post */ 237 238 for (retry = 0; retry < 10; retry++) { 239 /* Send the data to i2c */ 240 tmp = 0; 241 tmp = tmp | (I2C_A_ADC_LAST|I2C_A_ADC_START|I2C_A_ADC_ADD); 242 snd_emu10k1_ptr20_write(emu, P17V_I2C_ADDR, 0, tmp); 243 244 /* Wait till the transaction ends */ 245 while (1) { 246 mdelay(1); 247 status = snd_emu10k1_ptr20_read(emu, P17V_I2C_ADDR, 0); 248 timeout++; 249 if ((status & I2C_A_ADC_START) == 0) 250 break; 251 252 if (timeout > 1000) { 253 dev_warn(emu->card->dev, 254 "emu10k1:I2C:timeout status=0x%x\n", 255 status); 256 break; 257 } 258 } 259 //Read back and see if the transaction is successful 260 if ((status & I2C_A_ADC_ABORT) == 0) 261 break; 262 } 263 264 if (retry == 10) { 265 dev_err(emu->card->dev, "Writing to ADC failed!\n"); 266 dev_err(emu->card->dev, "status=0x%x, reg=%d, value=%d\n", 267 status, reg, value); 268 /* dump_stack(); */ 269 err = -EINVAL; 270 } 271 272 spin_unlock(&emu->i2c_lock); 273 return err; 274 } 275 276 static void snd_emu1010_fpga_write_locked(struct snd_emu10k1 *emu, u32 reg, u32 value) 277 { 278 if (snd_BUG_ON(reg > 0x3f)) 279 return; 280 reg += 0x40; /* 0x40 upwards are registers. */ 281 if (snd_BUG_ON(value > 0x3f)) /* 0 to 0x3f are values */ 282 return; 283 outw(reg, emu->port + A_GPIO); 284 udelay(10); 285 outw(reg | 0x80, emu->port + A_GPIO); /* High bit clocks the value into the fpga. */ 286 udelay(10); 287 outw(value, emu->port + A_GPIO); 288 udelay(10); 289 outw(value | 0x80 , emu->port + A_GPIO); /* High bit clocks the value into the fpga. */ 290 } 291 292 void snd_emu1010_fpga_write(struct snd_emu10k1 *emu, u32 reg, u32 value) 293 { 294 unsigned long flags; 295 296 spin_lock_irqsave(&emu->emu_lock, flags); 297 snd_emu1010_fpga_write_locked(emu, reg, value); 298 spin_unlock_irqrestore(&emu->emu_lock, flags); 299 } 300 301 void snd_emu1010_fpga_read(struct snd_emu10k1 *emu, u32 reg, u32 *value) 302 { 303 // The higest input pin is used as the designated interrupt trigger, 304 // so it needs to be masked out. 305 u32 mask = emu->card_capabilities->ca0108_chip ? 0x1f : 0x7f; 306 unsigned long flags; 307 if (snd_BUG_ON(reg > 0x3f)) 308 return; 309 reg += 0x40; /* 0x40 upwards are registers. */ 310 spin_lock_irqsave(&emu->emu_lock, flags); 311 outw(reg, emu->port + A_GPIO); 312 udelay(10); 313 outw(reg | 0x80, emu->port + A_GPIO); /* High bit clocks the value into the fpga. */ 314 udelay(10); 315 *value = ((inw(emu->port + A_GPIO) >> 8) & mask); 316 spin_unlock_irqrestore(&emu->emu_lock, flags); 317 } 318 319 /* Each Destination has one and only one Source, 320 * but one Source can feed any number of Destinations simultaneously. 321 */ 322 void snd_emu1010_fpga_link_dst_src_write(struct snd_emu10k1 *emu, u32 dst, u32 src) 323 { 324 unsigned long flags; 325 326 if (snd_BUG_ON(dst & ~0x71f)) 327 return; 328 if (snd_BUG_ON(src & ~0x71f)) 329 return; 330 spin_lock_irqsave(&emu->emu_lock, flags); 331 snd_emu1010_fpga_write_locked(emu, EMU_HANA_DESTHI, dst >> 8); 332 snd_emu1010_fpga_write_locked(emu, EMU_HANA_DESTLO, dst & 0x1f); 333 snd_emu1010_fpga_write_locked(emu, EMU_HANA_SRCHI, src >> 8); 334 snd_emu1010_fpga_write_locked(emu, EMU_HANA_SRCLO, src & 0x1f); 335 spin_unlock_irqrestore(&emu->emu_lock, flags); 336 } 337 338 void snd_emu10k1_intr_enable(struct snd_emu10k1 *emu, unsigned int intrenb) 339 { 340 unsigned long flags; 341 unsigned int enable; 342 343 spin_lock_irqsave(&emu->emu_lock, flags); 344 enable = inl(emu->port + INTE) | intrenb; 345 outl(enable, emu->port + INTE); 346 spin_unlock_irqrestore(&emu->emu_lock, flags); 347 } 348 349 void snd_emu10k1_intr_disable(struct snd_emu10k1 *emu, unsigned int intrenb) 350 { 351 unsigned long flags; 352 unsigned int enable; 353 354 spin_lock_irqsave(&emu->emu_lock, flags); 355 enable = inl(emu->port + INTE) & ~intrenb; 356 outl(enable, emu->port + INTE); 357 spin_unlock_irqrestore(&emu->emu_lock, flags); 358 } 359 360 void snd_emu10k1_voice_intr_enable(struct snd_emu10k1 *emu, unsigned int voicenum) 361 { 362 unsigned long flags; 363 unsigned int val; 364 365 spin_lock_irqsave(&emu->emu_lock, flags); 366 if (voicenum >= 32) { 367 outl(CLIEH << 16, emu->port + PTR); 368 val = inl(emu->port + DATA); 369 val |= 1 << (voicenum - 32); 370 } else { 371 outl(CLIEL << 16, emu->port + PTR); 372 val = inl(emu->port + DATA); 373 val |= 1 << voicenum; 374 } 375 outl(val, emu->port + DATA); 376 spin_unlock_irqrestore(&emu->emu_lock, flags); 377 } 378 379 void snd_emu10k1_voice_intr_disable(struct snd_emu10k1 *emu, unsigned int voicenum) 380 { 381 unsigned long flags; 382 unsigned int val; 383 384 spin_lock_irqsave(&emu->emu_lock, flags); 385 if (voicenum >= 32) { 386 outl(CLIEH << 16, emu->port + PTR); 387 val = inl(emu->port + DATA); 388 val &= ~(1 << (voicenum - 32)); 389 } else { 390 outl(CLIEL << 16, emu->port + PTR); 391 val = inl(emu->port + DATA); 392 val &= ~(1 << voicenum); 393 } 394 outl(val, emu->port + DATA); 395 spin_unlock_irqrestore(&emu->emu_lock, flags); 396 } 397 398 void snd_emu10k1_voice_intr_ack(struct snd_emu10k1 *emu, unsigned int voicenum) 399 { 400 unsigned long flags; 401 402 spin_lock_irqsave(&emu->emu_lock, flags); 403 if (voicenum >= 32) { 404 outl(CLIPH << 16, emu->port + PTR); 405 voicenum = 1 << (voicenum - 32); 406 } else { 407 outl(CLIPL << 16, emu->port + PTR); 408 voicenum = 1 << voicenum; 409 } 410 outl(voicenum, emu->port + DATA); 411 spin_unlock_irqrestore(&emu->emu_lock, flags); 412 } 413 414 void snd_emu10k1_voice_half_loop_intr_enable(struct snd_emu10k1 *emu, unsigned int voicenum) 415 { 416 unsigned long flags; 417 unsigned int val; 418 419 spin_lock_irqsave(&emu->emu_lock, flags); 420 if (voicenum >= 32) { 421 outl(HLIEH << 16, emu->port + PTR); 422 val = inl(emu->port + DATA); 423 val |= 1 << (voicenum - 32); 424 } else { 425 outl(HLIEL << 16, emu->port + PTR); 426 val = inl(emu->port + DATA); 427 val |= 1 << voicenum; 428 } 429 outl(val, emu->port + DATA); 430 spin_unlock_irqrestore(&emu->emu_lock, flags); 431 } 432 433 void snd_emu10k1_voice_half_loop_intr_disable(struct snd_emu10k1 *emu, unsigned int voicenum) 434 { 435 unsigned long flags; 436 unsigned int val; 437 438 spin_lock_irqsave(&emu->emu_lock, flags); 439 if (voicenum >= 32) { 440 outl(HLIEH << 16, emu->port + PTR); 441 val = inl(emu->port + DATA); 442 val &= ~(1 << (voicenum - 32)); 443 } else { 444 outl(HLIEL << 16, emu->port + PTR); 445 val = inl(emu->port + DATA); 446 val &= ~(1 << voicenum); 447 } 448 outl(val, emu->port + DATA); 449 spin_unlock_irqrestore(&emu->emu_lock, flags); 450 } 451 452 void snd_emu10k1_voice_half_loop_intr_ack(struct snd_emu10k1 *emu, unsigned int voicenum) 453 { 454 unsigned long flags; 455 456 spin_lock_irqsave(&emu->emu_lock, flags); 457 if (voicenum >= 32) { 458 outl(HLIPH << 16, emu->port + PTR); 459 voicenum = 1 << (voicenum - 32); 460 } else { 461 outl(HLIPL << 16, emu->port + PTR); 462 voicenum = 1 << voicenum; 463 } 464 outl(voicenum, emu->port + DATA); 465 spin_unlock_irqrestore(&emu->emu_lock, flags); 466 } 467 468 #if 0 469 void snd_emu10k1_voice_set_loop_stop(struct snd_emu10k1 *emu, unsigned int voicenum) 470 { 471 unsigned long flags; 472 unsigned int sol; 473 474 spin_lock_irqsave(&emu->emu_lock, flags); 475 if (voicenum >= 32) { 476 outl(SOLEH << 16, emu->port + PTR); 477 sol = inl(emu->port + DATA); 478 sol |= 1 << (voicenum - 32); 479 } else { 480 outl(SOLEL << 16, emu->port + PTR); 481 sol = inl(emu->port + DATA); 482 sol |= 1 << voicenum; 483 } 484 outl(sol, emu->port + DATA); 485 spin_unlock_irqrestore(&emu->emu_lock, flags); 486 } 487 488 void snd_emu10k1_voice_clear_loop_stop(struct snd_emu10k1 *emu, unsigned int voicenum) 489 { 490 unsigned long flags; 491 unsigned int sol; 492 493 spin_lock_irqsave(&emu->emu_lock, flags); 494 if (voicenum >= 32) { 495 outl(SOLEH << 16, emu->port + PTR); 496 sol = inl(emu->port + DATA); 497 sol &= ~(1 << (voicenum - 32)); 498 } else { 499 outl(SOLEL << 16, emu->port + PTR); 500 sol = inl(emu->port + DATA); 501 sol &= ~(1 << voicenum); 502 } 503 outl(sol, emu->port + DATA); 504 spin_unlock_irqrestore(&emu->emu_lock, flags); 505 } 506 #endif 507 508 void snd_emu10k1_voice_set_loop_stop_multiple(struct snd_emu10k1 *emu, u64 voices) 509 { 510 unsigned long flags; 511 512 spin_lock_irqsave(&emu->emu_lock, flags); 513 outl(SOLEL << 16, emu->port + PTR); 514 outl(inl(emu->port + DATA) | (u32)voices, emu->port + DATA); 515 outl(SOLEH << 16, emu->port + PTR); 516 outl(inl(emu->port + DATA) | (u32)(voices >> 32), emu->port + DATA); 517 spin_unlock_irqrestore(&emu->emu_lock, flags); 518 } 519 520 void snd_emu10k1_voice_clear_loop_stop_multiple(struct snd_emu10k1 *emu, u64 voices) 521 { 522 unsigned long flags; 523 524 spin_lock_irqsave(&emu->emu_lock, flags); 525 outl(SOLEL << 16, emu->port + PTR); 526 outl(inl(emu->port + DATA) & (u32)~voices, emu->port + DATA); 527 outl(SOLEH << 16, emu->port + PTR); 528 outl(inl(emu->port + DATA) & (u32)(~voices >> 32), emu->port + DATA); 529 spin_unlock_irqrestore(&emu->emu_lock, flags); 530 } 531 532 int snd_emu10k1_voice_clear_loop_stop_multiple_atomic(struct snd_emu10k1 *emu, u64 voices) 533 { 534 unsigned long flags; 535 u32 soll, solh; 536 int ret = -EIO; 537 538 spin_lock_irqsave(&emu->emu_lock, flags); 539 540 outl(SOLEL << 16, emu->port + PTR); 541 soll = inl(emu->port + DATA); 542 outl(SOLEH << 16, emu->port + PTR); 543 solh = inl(emu->port + DATA); 544 545 soll &= (u32)~voices; 546 solh &= (u32)(~voices >> 32); 547 548 for (int tries = 0; tries < 1000; tries++) { 549 const u32 quart = 1U << (REG_SIZE(WC_CURRENTCHANNEL) - 2); 550 // First we wait for the third quarter of the sample cycle ... 551 u32 wc = inl(emu->port + WC); 552 u32 cc = REG_VAL_GET(WC_CURRENTCHANNEL, wc); 553 if (cc >= quart * 2 && cc < quart * 3) { 554 // ... and release the low voices, while the high ones are serviced. 555 outl(SOLEL << 16, emu->port + PTR); 556 outl(soll, emu->port + DATA); 557 // Then we wait for the first quarter of the next sample cycle ... 558 for (; tries < 1000; tries++) { 559 cc = REG_VAL_GET(WC_CURRENTCHANNEL, inl(emu->port + WC)); 560 if (cc < quart) 561 goto good; 562 // We will block for 10+ us with interrupts disabled. This is 563 // not nice at all, but necessary for reasonable reliability. 564 udelay(1); 565 } 566 break; 567 good: 568 // ... and release the high voices, while the low ones are serviced. 569 outl(SOLEH << 16, emu->port + PTR); 570 outl(solh, emu->port + DATA); 571 // Finally we verify that nothing interfered in fact. 572 if (REG_VAL_GET(WC_SAMPLECOUNTER, inl(emu->port + WC)) == 573 ((REG_VAL_GET(WC_SAMPLECOUNTER, wc) + 1) & REG_MASK0(WC_SAMPLECOUNTER))) { 574 ret = 0; 575 } else { 576 ret = -EAGAIN; 577 } 578 break; 579 } 580 // Don't block for too long 581 spin_unlock_irqrestore(&emu->emu_lock, flags); 582 udelay(1); 583 spin_lock_irqsave(&emu->emu_lock, flags); 584 } 585 586 spin_unlock_irqrestore(&emu->emu_lock, flags); 587 return ret; 588 } 589 590 void snd_emu10k1_wait(struct snd_emu10k1 *emu, unsigned int wait) 591 { 592 volatile unsigned count; 593 unsigned int newtime = 0, curtime; 594 595 curtime = inl(emu->port + WC) >> 6; 596 while (wait-- > 0) { 597 count = 0; 598 while (count++ < 16384) { 599 newtime = inl(emu->port + WC) >> 6; 600 if (newtime != curtime) 601 break; 602 } 603 if (count > 16384) 604 break; 605 curtime = newtime; 606 } 607 } 608 609 unsigned short snd_emu10k1_ac97_read(struct snd_ac97 *ac97, unsigned short reg) 610 { 611 struct snd_emu10k1 *emu = ac97->private_data; 612 unsigned long flags; 613 unsigned short val; 614 615 spin_lock_irqsave(&emu->emu_lock, flags); 616 outb(reg, emu->port + AC97ADDRESS); 617 val = inw(emu->port + AC97DATA); 618 spin_unlock_irqrestore(&emu->emu_lock, flags); 619 return val; 620 } 621 622 void snd_emu10k1_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short data) 623 { 624 struct snd_emu10k1 *emu = ac97->private_data; 625 unsigned long flags; 626 627 spin_lock_irqsave(&emu->emu_lock, flags); 628 outb(reg, emu->port + AC97ADDRESS); 629 outw(data, emu->port + AC97DATA); 630 spin_unlock_irqrestore(&emu->emu_lock, flags); 631 } 632