1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (c) by Jaroslav Kysela <perex@perex.cz> 4 * Creative Labs, Inc. 5 * Routines for effect processor FX8010 6 * 7 * Copyright (c) by James Courtier-Dutton <James@superbug.co.uk> 8 * Added EMU 1010 support. 9 * 10 * BUGS: 11 * -- 12 * 13 * TODO: 14 * -- 15 */ 16 17 #include <linux/pci.h> 18 #include <linux/capability.h> 19 #include <linux/delay.h> 20 #include <linux/slab.h> 21 #include <linux/vmalloc.h> 22 #include <linux/init.h> 23 #include <linux/mutex.h> 24 #include <linux/moduleparam.h> 25 #include <linux/nospec.h> 26 27 #include <sound/core.h> 28 #include <sound/tlv.h> 29 #include <sound/emu10k1.h> 30 31 #if 0 /* for testing purposes - digital out -> capture */ 32 #define EMU10K1_CAPTURE_DIGITAL_OUT 33 #endif 34 #if 0 /* for testing purposes - set S/PDIF to AC3 output */ 35 #define EMU10K1_SET_AC3_IEC958 36 #endif 37 #if 0 /* for testing purposes - feed the front signal to Center/LFE outputs */ 38 #define EMU10K1_CENTER_LFE_FROM_FRONT 39 #endif 40 41 static bool high_res_gpr_volume; 42 module_param(high_res_gpr_volume, bool, 0444); 43 MODULE_PARM_DESC(high_res_gpr_volume, "GPR mixer controls use 31-bit range."); 44 45 /* 46 * Tables 47 */ 48 49 // Playback channel labels; corresponds with the public FXBUS_* defines. 50 // Unlike the tables below, this is not determined by the hardware. 51 const char * const snd_emu10k1_fxbus[32] = { 52 /* 0x00 */ "PCM Left", 53 /* 0x01 */ "PCM Right", 54 /* 0x02 */ "PCM Rear Left", 55 /* 0x03 */ "PCM Rear Right", 56 /* 0x04 */ "MIDI Left", 57 /* 0x05 */ "MIDI Right", 58 /* 0x06 */ "PCM Center", 59 /* 0x07 */ "PCM LFE", 60 /* 0x08 */ "PCM Front Left", 61 /* 0x09 */ "PCM Front Right", 62 /* 0x0a */ NULL, 63 /* 0x0b */ NULL, 64 /* 0x0c */ "MIDI Reverb", 65 /* 0x0d */ "MIDI Chorus", 66 /* 0x0e */ "PCM Side Left", 67 /* 0x0f */ "PCM Side Right", 68 /* 0x10 */ NULL, 69 /* 0x11 */ NULL, 70 /* 0x12 */ NULL, 71 /* 0x13 */ NULL, 72 /* 0x14 */ "Passthrough Left", 73 /* 0x15 */ "Passthrough Right", 74 /* 0x16 */ NULL, 75 /* 0x17 */ NULL, 76 /* 0x18 */ NULL, 77 /* 0x19 */ NULL, 78 /* 0x1a */ NULL, 79 /* 0x1b */ NULL, 80 /* 0x1c */ NULL, 81 /* 0x1d */ NULL, 82 /* 0x1e */ NULL, 83 /* 0x1f */ NULL 84 }; 85 86 // Physical inputs; corresponds with the public EXTIN_* defines. 87 const char * const snd_emu10k1_sblive_ins[16] = { 88 /* 0x00 */ "AC97 Left", 89 /* 0x01 */ "AC97 Right", 90 /* 0x02 */ "TTL IEC958 Left", 91 /* 0x03 */ "TTL IEC958 Right", 92 /* 0x04 */ "Zoom Video Left", 93 /* 0x05 */ "Zoom Video Right", 94 /* 0x06 */ "Optical IEC958 Left", 95 /* 0x07 */ "Optical IEC958 Right", 96 /* 0x08 */ "Line/Mic 1 Left", 97 /* 0x09 */ "Line/Mic 1 Right", 98 /* 0x0a */ "Coaxial IEC958 Left", 99 /* 0x0b */ "Coaxial IEC958 Right", 100 /* 0x0c */ "Line/Mic 2 Left", 101 /* 0x0d */ "Line/Mic 2 Right", 102 /* 0x0e */ NULL, 103 /* 0x0f */ NULL 104 }; 105 106 // Physical inputs; corresponds with the public A_EXTIN_* defines. 107 const char * const snd_emu10k1_audigy_ins[16] = { 108 /* 0x00 */ "AC97 Left", 109 /* 0x01 */ "AC97 Right", 110 /* 0x02 */ "Audigy CD Left", 111 /* 0x03 */ "Audigy CD Right", 112 /* 0x04 */ "Optical IEC958 Left", 113 /* 0x05 */ "Optical IEC958 Right", 114 /* 0x06 */ NULL, 115 /* 0x07 */ NULL, 116 /* 0x08 */ "Line/Mic 2 Left", 117 /* 0x09 */ "Line/Mic 2 Right", 118 /* 0x0a */ "SPDIF Left", 119 /* 0x0b */ "SPDIF Right", 120 /* 0x0c */ "Aux2 Left", 121 /* 0x0d */ "Aux2 Right", 122 /* 0x0e */ NULL, 123 /* 0x0f */ NULL 124 }; 125 126 // Physical outputs; corresponds with the public EXTOUT_* defines. 127 const char * const snd_emu10k1_sblive_outs[32] = { 128 /* 0x00 */ "AC97 Left", 129 /* 0x01 */ "AC97 Right", 130 /* 0x02 */ "Optical IEC958 Left", 131 /* 0x03 */ "Optical IEC958 Right", 132 /* 0x04 */ "Center", 133 /* 0x05 */ "LFE", 134 /* 0x06 */ "Headphone Left", 135 /* 0x07 */ "Headphone Right", 136 /* 0x08 */ "Surround Left", 137 /* 0x09 */ "Surround Right", 138 /* 0x0a */ "PCM Capture Left", 139 /* 0x0b */ "PCM Capture Right", 140 /* 0x0c */ "MIC Capture", 141 /* 0x0d */ "AC97 Surround Left", 142 /* 0x0e */ "AC97 Surround Right", 143 /* 0x0f */ NULL, 144 // This is actually the FXBUS2 range; SB Live! 5.1 only. 145 /* 0x10 */ NULL, 146 /* 0x11 */ "Analog Center", 147 /* 0x12 */ "Analog LFE", 148 /* 0x13 */ NULL, 149 /* 0x14 */ NULL, 150 /* 0x15 */ NULL, 151 /* 0x16 */ NULL, 152 /* 0x17 */ NULL, 153 /* 0x18 */ NULL, 154 /* 0x19 */ NULL, 155 /* 0x1a */ NULL, 156 /* 0x1b */ NULL, 157 /* 0x1c */ NULL, 158 /* 0x1d */ NULL, 159 /* 0x1e */ NULL, 160 /* 0x1f */ NULL, 161 }; 162 163 // Physical outputs; corresponds with the public A_EXTOUT_* defines. 164 const char * const snd_emu10k1_audigy_outs[32] = { 165 /* 0x00 */ "Digital Front Left", 166 /* 0x01 */ "Digital Front Right", 167 /* 0x02 */ "Digital Center", 168 /* 0x03 */ "Digital LEF", 169 /* 0x04 */ "Headphone Left", 170 /* 0x05 */ "Headphone Right", 171 /* 0x06 */ "Digital Rear Left", 172 /* 0x07 */ "Digital Rear Right", 173 /* 0x08 */ "Front Left", 174 /* 0x09 */ "Front Right", 175 /* 0x0a */ "Center", 176 /* 0x0b */ "LFE", 177 /* 0x0c */ NULL, 178 /* 0x0d */ NULL, 179 /* 0x0e */ "Rear Left", 180 /* 0x0f */ "Rear Right", 181 /* 0x10 */ "AC97 Front Left", 182 /* 0x11 */ "AC97 Front Right", 183 /* 0x12 */ "ADC Capture Left", 184 /* 0x13 */ "ADC Capture Right", 185 /* 0x14 */ NULL, 186 /* 0x15 */ NULL, 187 /* 0x16 */ NULL, 188 /* 0x17 */ NULL, 189 /* 0x18 */ NULL, 190 /* 0x19 */ NULL, 191 /* 0x1a */ NULL, 192 /* 0x1b */ NULL, 193 /* 0x1c */ NULL, 194 /* 0x1d */ NULL, 195 /* 0x1e */ NULL, 196 /* 0x1f */ NULL, 197 }; 198 199 // On the SB Live! 5.1, FXBUS2[1] and FXBUS2[2] are occupied by EXTOUT_ACENTER 200 // and EXTOUT_ALFE, so we can't connect inputs to them for multitrack recording. 201 // 202 // Since only 14 of the 16 EXTINs are used, this is not a big problem. 203 // We route AC97 to FX capture 14 and 15, SPDIF_CD to FX capture 0 and 3, 204 // and the rest of the EXTINs to the corresponding FX capture channel. 205 // Multitrack recorders will still see the center/LFE output signal 206 // on the second and third "input" channel. 207 const s8 snd_emu10k1_sblive51_fxbus2_map[16] = { 208 2, -1, -1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 0, 1 209 }; 210 211 static const u32 bass_table[41][5] = { 212 { 0x3e4f844f, 0x84ed4cc3, 0x3cc69927, 0x7b03553a, 0xc4da8486 }, 213 { 0x3e69a17a, 0x84c280fb, 0x3cd77cd4, 0x7b2f2a6f, 0xc4b08d1d }, 214 { 0x3e82ff42, 0x849991d5, 0x3ce7466b, 0x7b5917c6, 0xc48863ee }, 215 { 0x3e9bab3c, 0x847267f0, 0x3cf5ffe8, 0x7b813560, 0xc461f22c }, 216 { 0x3eb3b275, 0x844ced29, 0x3d03b295, 0x7ba79a1c, 0xc43d223b }, 217 { 0x3ecb2174, 0x84290c8b, 0x3d106714, 0x7bcc5ba3, 0xc419dfa5 }, 218 { 0x3ee2044b, 0x8406b244, 0x3d1c2561, 0x7bef8e77, 0xc3f8170f }, 219 { 0x3ef86698, 0x83e5cb96, 0x3d26f4d8, 0x7c114600, 0xc3d7b625 }, 220 { 0x3f0e5390, 0x83c646c9, 0x3d30dc39, 0x7c319498, 0xc3b8ab97 }, 221 { 0x3f23d60b, 0x83a81321, 0x3d39e1af, 0x7c508b9c, 0xc39ae704 }, 222 { 0x3f38f884, 0x838b20d2, 0x3d420ad2, 0x7c6e3b75, 0xc37e58f1 }, 223 { 0x3f4dc52c, 0x836f60ef, 0x3d495cab, 0x7c8ab3a6, 0xc362f2be }, 224 { 0x3f6245e8, 0x8354c565, 0x3d4fdbb8, 0x7ca602d6, 0xc348a69b }, 225 { 0x3f76845f, 0x833b40ec, 0x3d558bf0, 0x7cc036df, 0xc32f677c }, 226 { 0x3f8a8a03, 0x8322c6fb, 0x3d5a70c4, 0x7cd95cd7, 0xc317290b }, 227 { 0x3f9e6014, 0x830b4bc3, 0x3d5e8d25, 0x7cf1811a, 0xc2ffdfa5 }, 228 { 0x3fb20fae, 0x82f4c420, 0x3d61e37f, 0x7d08af56, 0xc2e9804a }, 229 { 0x3fc5a1cc, 0x82df2592, 0x3d6475c3, 0x7d1ef294, 0xc2d40096 }, 230 { 0x3fd91f55, 0x82ca6632, 0x3d664564, 0x7d345541, 0xc2bf56b9 }, 231 { 0x3fec9120, 0x82b67cac, 0x3d675356, 0x7d48e138, 0xc2ab796e }, 232 { 0x40000000, 0x82a36037, 0x3d67a012, 0x7d5c9fc9, 0xc2985fee }, 233 { 0x401374c7, 0x8291088a, 0x3d672b93, 0x7d6f99c3, 0xc28601f2 }, 234 { 0x4026f857, 0x827f6dd7, 0x3d65f559, 0x7d81d77c, 0xc27457a3 }, 235 { 0x403a939f, 0x826e88c5, 0x3d63fc63, 0x7d9360d4, 0xc2635996 }, 236 { 0x404e4faf, 0x825e5266, 0x3d613f32, 0x7da43d42, 0xc25300c6 }, 237 { 0x406235ba, 0x824ec434, 0x3d5dbbc3, 0x7db473d7, 0xc243468e }, 238 { 0x40764f1f, 0x823fd80c, 0x3d596f8f, 0x7dc40b44, 0xc23424a2 }, 239 { 0x408aa576, 0x82318824, 0x3d545787, 0x7dd309e2, 0xc2259509 }, 240 { 0x409f4296, 0x8223cf0b, 0x3d4e7012, 0x7de175b5, 0xc2179218 }, 241 { 0x40b430a0, 0x8216a7a1, 0x3d47b505, 0x7def5475, 0xc20a1670 }, 242 { 0x40c97a0a, 0x820a0d12, 0x3d4021a1, 0x7dfcab8d, 0xc1fd1cf5 }, 243 { 0x40df29a6, 0x81fdfad6, 0x3d37b08d, 0x7e098028, 0xc1f0a0ca }, 244 { 0x40f54ab1, 0x81f26ca9, 0x3d2e5bd1, 0x7e15d72b, 0xc1e49d52 }, 245 { 0x410be8da, 0x81e75e89, 0x3d241cce, 0x7e21b544, 0xc1d90e24 }, 246 { 0x41231051, 0x81dcccb3, 0x3d18ec37, 0x7e2d1ee6, 0xc1cdef10 }, 247 { 0x413acdd0, 0x81d2b39e, 0x3d0cc20a, 0x7e38184e, 0xc1c33c13 }, 248 { 0x41532ea7, 0x81c90ffb, 0x3cff9585, 0x7e42a58b, 0xc1b8f15a }, 249 { 0x416c40cd, 0x81bfdeb2, 0x3cf15d21, 0x7e4cca7c, 0xc1af0b3f }, 250 { 0x418612ea, 0x81b71cdc, 0x3ce20e85, 0x7e568ad3, 0xc1a58640 }, 251 { 0x41a0b465, 0x81aec7c5, 0x3cd19e7c, 0x7e5fea1e, 0xc19c5f03 }, 252 { 0x41bc3573, 0x81a6dcea, 0x3cc000e9, 0x7e68ebc2, 0xc1939250 } 253 }; 254 255 static const u32 treble_table[41][5] = { 256 { 0x0125cba9, 0xfed5debd, 0x00599b6c, 0x0d2506da, 0xfa85b354 }, 257 { 0x0142f67e, 0xfeb03163, 0x0066cd0f, 0x0d14c69d, 0xfa914473 }, 258 { 0x016328bd, 0xfe860158, 0x0075b7f2, 0x0d03eb27, 0xfa9d32d2 }, 259 { 0x0186b438, 0xfe56c982, 0x00869234, 0x0cf27048, 0xfaa97fca }, 260 { 0x01adf358, 0xfe21f5fe, 0x00999842, 0x0ce051c2, 0xfab62ca5 }, 261 { 0x01d949fa, 0xfde6e287, 0x00af0d8d, 0x0ccd8b4a, 0xfac33aa7 }, 262 { 0x02092669, 0xfda4d8bf, 0x00c73d4c, 0x0cba1884, 0xfad0ab07 }, 263 { 0x023e0268, 0xfd5b0e4a, 0x00e27b54, 0x0ca5f509, 0xfade7ef2 }, 264 { 0x0278645c, 0xfd08a2b0, 0x01012509, 0x0c911c63, 0xfaecb788 }, 265 { 0x02b8e091, 0xfcac9d1a, 0x0123a262, 0x0c7b8a14, 0xfafb55df }, 266 { 0x03001a9a, 0xfc45e9ce, 0x014a6709, 0x0c65398f, 0xfb0a5aff }, 267 { 0x034ec6d7, 0xfbd3576b, 0x0175f397, 0x0c4e2643, 0xfb19c7e4 }, 268 { 0x03a5ac15, 0xfb5393ee, 0x01a6d6ed, 0x0c364b94, 0xfb299d7c }, 269 { 0x0405a562, 0xfac52968, 0x01ddafae, 0x0c1da4e2, 0xfb39dca5 }, 270 { 0x046fa3fe, 0xfa267a66, 0x021b2ddd, 0x0c042d8d, 0xfb4a8631 }, 271 { 0x04e4b17f, 0xf975be0f, 0x0260149f, 0x0be9e0f2, 0xfb5b9ae0 }, 272 { 0x0565f220, 0xf8b0fbe5, 0x02ad3c29, 0x0bceba73, 0xfb6d1b60 }, 273 { 0x05f4a745, 0xf7d60722, 0x030393d4, 0x0bb2b578, 0xfb7f084d }, 274 { 0x06923236, 0xf6e279bd, 0x03642465, 0x0b95cd75, 0xfb916233 }, 275 { 0x07401713, 0xf5d3aef9, 0x03d01283, 0x0b77fded, 0xfba42984 }, 276 { 0x08000000, 0xf4a6bd88, 0x0448a161, 0x0b594278, 0xfbb75e9f }, 277 { 0x08d3c097, 0xf3587131, 0x04cf35a4, 0x0b3996c9, 0xfbcb01cb }, 278 { 0x09bd59a2, 0xf1e543f9, 0x05655880, 0x0b18f6b2, 0xfbdf1333 }, 279 { 0x0abefd0f, 0xf04956ca, 0x060cbb12, 0x0af75e2c, 0xfbf392e8 }, 280 { 0x0bdb123e, 0xee806984, 0x06c739fe, 0x0ad4c962, 0xfc0880dd }, 281 { 0x0d143a94, 0xec85d287, 0x0796e150, 0x0ab134b0, 0xfc1ddce5 }, 282 { 0x0e6d5664, 0xea547598, 0x087df0a0, 0x0a8c9cb6, 0xfc33a6ad }, 283 { 0x0fe98a2a, 0xe7e6ba35, 0x097edf83, 0x0a66fe5b, 0xfc49ddc2 }, 284 { 0x118c4421, 0xe536813a, 0x0a9c6248, 0x0a4056d7, 0xfc608185 }, 285 { 0x1359422e, 0xe23d19eb, 0x0bd96efb, 0x0a18a3bf, 0xfc77912c }, 286 { 0x1554982b, 0xdef33645, 0x0d3942bd, 0x09efe312, 0xfc8f0bc1 }, 287 { 0x1782b68a, 0xdb50deb1, 0x0ebf676d, 0x09c6133f, 0xfca6f019 }, 288 { 0x19e8715d, 0xd74d64fd, 0x106fb999, 0x099b3337, 0xfcbf3cd6 }, 289 { 0x1c8b07b8, 0xd2df56ab, 0x124e6ec8, 0x096f4274, 0xfcd7f060 }, 290 { 0x1f702b6d, 0xcdfc6e92, 0x14601c10, 0x0942410b, 0xfcf108e5 }, 291 { 0x229e0933, 0xc89985cd, 0x16a9bcfa, 0x09142fb5, 0xfd0a8451 }, 292 { 0x261b5118, 0xc2aa8409, 0x1930bab6, 0x08e50fdc, 0xfd24604d }, 293 { 0x29ef3f5d, 0xbc224f28, 0x1bfaf396, 0x08b4e3aa, 0xfd3e9a3b }, 294 { 0x2e21a59b, 0xb4f2ba46, 0x1f0ec2d6, 0x0883ae15, 0xfd592f33 }, 295 { 0x32baf44b, 0xad0c7429, 0x227308a3, 0x085172eb, 0xfd741bfd }, 296 { 0x37c4448b, 0xa45ef51d, 0x262f3267, 0x081e36dc, 0xfd8f5d14 } 297 }; 298 299 /* dB gain = (float) 20 * log10( float(db_table_value) / 0x8000000 ) */ 300 static const u32 db_table[101] = { 301 0x00000000, 0x01571f82, 0x01674b41, 0x01783a1b, 0x0189f540, 302 0x019c8651, 0x01aff763, 0x01c45306, 0x01d9a446, 0x01eff6b8, 303 0x0207567a, 0x021fd03d, 0x0239714c, 0x02544792, 0x027061a1, 304 0x028dcebb, 0x02ac9edc, 0x02cce2bf, 0x02eeabe8, 0x03120cb0, 305 0x0337184e, 0x035de2df, 0x03868173, 0x03b10a18, 0x03dd93e9, 306 0x040c3713, 0x043d0cea, 0x04702ff3, 0x04a5bbf2, 0x04ddcdfb, 307 0x0518847f, 0x0555ff62, 0x05966005, 0x05d9c95d, 0x06206005, 308 0x066a4a52, 0x06b7b067, 0x0708bc4c, 0x075d9a01, 0x07b6779d, 309 0x08138561, 0x0874f5d5, 0x08dafde1, 0x0945d4ed, 0x09b5b4fd, 310 0x0a2adad1, 0x0aa58605, 0x0b25f936, 0x0bac7a24, 0x0c3951d8, 311 0x0ccccccc, 0x0d673b17, 0x0e08f093, 0x0eb24510, 0x0f639481, 312 0x101d3f2d, 0x10dfa9e6, 0x11ab3e3f, 0x12806ac3, 0x135fa333, 313 0x144960c5, 0x153e2266, 0x163e6cfe, 0x174acbb7, 0x1863d04d, 314 0x198a1357, 0x1abe349f, 0x1c00db77, 0x1d52b712, 0x1eb47ee6, 315 0x2026f30f, 0x21aadcb6, 0x23410e7e, 0x24ea64f9, 0x26a7c71d, 316 0x287a26c4, 0x2a62812c, 0x2c61df84, 0x2e795779, 0x30aa0bcf, 317 0x32f52cfe, 0x355bf9d8, 0x37dfc033, 0x3a81dda4, 0x3d43c038, 318 0x4026e73c, 0x432ce40f, 0x46575af8, 0x49a8040f, 0x4d20ac2a, 319 0x50c335d3, 0x54919a57, 0x588dead1, 0x5cba514a, 0x611911ea, 320 0x65ac8c2f, 0x6a773c39, 0x6f7bbc23, 0x74bcc56c, 0x7a3d3272, 321 0x7fffffff, 322 }; 323 324 /* EMU10k1/EMU10k2 DSP control db gain */ 325 static const DECLARE_TLV_DB_SCALE(snd_emu10k1_db_scale1, -4000, 40, 1); 326 static const DECLARE_TLV_DB_LINEAR(snd_emu10k1_db_linear, TLV_DB_GAIN_MUTE, 0); 327 328 /* EMU10K1 bass/treble db gain */ 329 static const DECLARE_TLV_DB_SCALE(snd_emu10k1_bass_treble_db_scale, -1200, 60, 0); 330 331 static const u32 onoff_table[2] = { 332 0x00000000, 0x00000001 333 }; 334 335 /* 336 * controls 337 */ 338 339 static int snd_emu10k1_gpr_ctl_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 340 { 341 struct snd_emu10k1_fx8010_ctl *ctl = 342 (struct snd_emu10k1_fx8010_ctl *) kcontrol->private_value; 343 344 if (ctl->min == 0 && ctl->max == 1) 345 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 346 else 347 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 348 uinfo->count = ctl->vcount; 349 uinfo->value.integer.min = ctl->min; 350 uinfo->value.integer.max = ctl->max; 351 return 0; 352 } 353 354 static int snd_emu10k1_gpr_ctl_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 355 { 356 struct snd_emu10k1_fx8010_ctl *ctl = 357 (struct snd_emu10k1_fx8010_ctl *) kcontrol->private_value; 358 unsigned int i; 359 360 for (i = 0; i < ctl->vcount; i++) 361 ucontrol->value.integer.value[i] = ctl->value[i]; 362 return 0; 363 } 364 365 static int snd_emu10k1_gpr_ctl_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 366 { 367 struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol); 368 struct snd_emu10k1_fx8010_ctl *ctl = 369 (struct snd_emu10k1_fx8010_ctl *) kcontrol->private_value; 370 int nval, val; 371 unsigned int i, j; 372 int change = 0; 373 374 for (i = 0; i < ctl->vcount; i++) { 375 nval = ucontrol->value.integer.value[i]; 376 if (nval < ctl->min) 377 nval = ctl->min; 378 if (nval > ctl->max) 379 nval = ctl->max; 380 if (nval != ctl->value[i]) 381 change = 1; 382 val = ctl->value[i] = nval; 383 switch (ctl->translation) { 384 case EMU10K1_GPR_TRANSLATION_NONE: 385 snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[i], 0, val); 386 break; 387 case EMU10K1_GPR_TRANSLATION_NEGATE: 388 snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[i], 0, ~val); 389 break; 390 case EMU10K1_GPR_TRANSLATION_TABLE100: 391 snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[i], 0, db_table[val]); 392 break; 393 case EMU10K1_GPR_TRANSLATION_NEG_TABLE100: 394 snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[i], 0, 395 val == 100 ? 0x80000000 : -(int)db_table[val]); 396 break; 397 case EMU10K1_GPR_TRANSLATION_BASS: 398 if ((ctl->count % 5) != 0 || (ctl->count / 5) != ctl->vcount) { 399 change = -EIO; 400 goto __error; 401 } 402 for (j = 0; j < 5; j++) 403 snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[j * ctl->vcount + i], 0, bass_table[val][j]); 404 break; 405 case EMU10K1_GPR_TRANSLATION_TREBLE: 406 if ((ctl->count % 5) != 0 || (ctl->count / 5) != ctl->vcount) { 407 change = -EIO; 408 goto __error; 409 } 410 for (j = 0; j < 5; j++) 411 snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[j * ctl->vcount + i], 0, treble_table[val][j]); 412 break; 413 case EMU10K1_GPR_TRANSLATION_ONOFF: 414 snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[i], 0, onoff_table[val]); 415 break; 416 } 417 } 418 __error: 419 return change; 420 } 421 422 /* 423 * Interrupt handler 424 */ 425 426 static void snd_emu10k1_fx8010_interrupt(struct snd_emu10k1 *emu) 427 { 428 struct snd_emu10k1_fx8010_irq *irq, *nirq; 429 430 irq = emu->fx8010.irq_handlers; 431 while (irq) { 432 nirq = irq->next; /* irq ptr can be removed from list */ 433 if (snd_emu10k1_ptr_read(emu, emu->gpr_base + irq->gpr_running, 0) & 0xffff0000) { 434 if (irq->handler) 435 irq->handler(emu, irq->private_data); 436 snd_emu10k1_ptr_write(emu, emu->gpr_base + irq->gpr_running, 0, 1); 437 } 438 irq = nirq; 439 } 440 } 441 442 int snd_emu10k1_fx8010_register_irq_handler(struct snd_emu10k1 *emu, 443 snd_fx8010_irq_handler_t *handler, 444 unsigned char gpr_running, 445 void *private_data, 446 struct snd_emu10k1_fx8010_irq *irq) 447 { 448 unsigned long flags; 449 450 irq->handler = handler; 451 irq->gpr_running = gpr_running; 452 irq->private_data = private_data; 453 irq->next = NULL; 454 spin_lock_irqsave(&emu->fx8010.irq_lock, flags); 455 if (emu->fx8010.irq_handlers == NULL) { 456 emu->fx8010.irq_handlers = irq; 457 emu->dsp_interrupt = snd_emu10k1_fx8010_interrupt; 458 snd_emu10k1_intr_enable(emu, INTE_FXDSPENABLE); 459 } else { 460 irq->next = emu->fx8010.irq_handlers; 461 emu->fx8010.irq_handlers = irq; 462 } 463 spin_unlock_irqrestore(&emu->fx8010.irq_lock, flags); 464 return 0; 465 } 466 467 int snd_emu10k1_fx8010_unregister_irq_handler(struct snd_emu10k1 *emu, 468 struct snd_emu10k1_fx8010_irq *irq) 469 { 470 struct snd_emu10k1_fx8010_irq *tmp; 471 unsigned long flags; 472 473 spin_lock_irqsave(&emu->fx8010.irq_lock, flags); 474 tmp = emu->fx8010.irq_handlers; 475 if (tmp == irq) { 476 emu->fx8010.irq_handlers = tmp->next; 477 if (emu->fx8010.irq_handlers == NULL) { 478 snd_emu10k1_intr_disable(emu, INTE_FXDSPENABLE); 479 emu->dsp_interrupt = NULL; 480 } 481 } else { 482 while (tmp && tmp->next != irq) 483 tmp = tmp->next; 484 if (tmp) 485 tmp->next = tmp->next->next; 486 } 487 spin_unlock_irqrestore(&emu->fx8010.irq_lock, flags); 488 return 0; 489 } 490 491 /************************************************************************* 492 * EMU10K1 effect manager 493 *************************************************************************/ 494 495 static void snd_emu10k1_write_op(struct snd_emu10k1_fx8010_code *icode, 496 unsigned int *ptr, 497 u32 op, u32 r, u32 a, u32 x, u32 y) 498 { 499 u_int32_t *code; 500 if (snd_BUG_ON(*ptr >= 512)) 501 return; 502 code = icode->code + (*ptr) * 2; 503 set_bit(*ptr, icode->code_valid); 504 code[0] = ((x & 0x3ff) << 10) | (y & 0x3ff); 505 code[1] = ((op & 0x0f) << 20) | ((r & 0x3ff) << 10) | (a & 0x3ff); 506 (*ptr)++; 507 } 508 509 #define OP(icode, ptr, op, r, a, x, y) \ 510 snd_emu10k1_write_op(icode, ptr, op, r, a, x, y) 511 512 static void snd_emu10k1_audigy_write_op(struct snd_emu10k1_fx8010_code *icode, 513 unsigned int *ptr, 514 u32 op, u32 r, u32 a, u32 x, u32 y) 515 { 516 u_int32_t *code; 517 if (snd_BUG_ON(*ptr >= 1024)) 518 return; 519 code = icode->code + (*ptr) * 2; 520 set_bit(*ptr, icode->code_valid); 521 code[0] = ((x & 0x7ff) << 12) | (y & 0x7ff); 522 code[1] = ((op & 0x0f) << 24) | ((r & 0x7ff) << 12) | (a & 0x7ff); 523 (*ptr)++; 524 } 525 526 #define A_OP(icode, ptr, op, r, a, x, y) \ 527 snd_emu10k1_audigy_write_op(icode, ptr, op, r, a, x, y) 528 529 static void snd_emu10k1_efx_write(struct snd_emu10k1 *emu, unsigned int pc, unsigned int data) 530 { 531 pc += emu->audigy ? A_MICROCODEBASE : MICROCODEBASE; 532 snd_emu10k1_ptr_write(emu, pc, 0, data); 533 } 534 535 unsigned int snd_emu10k1_efx_read(struct snd_emu10k1 *emu, unsigned int pc) 536 { 537 pc += emu->audigy ? A_MICROCODEBASE : MICROCODEBASE; 538 return snd_emu10k1_ptr_read(emu, pc, 0); 539 } 540 541 static int snd_emu10k1_gpr_poke(struct snd_emu10k1 *emu, 542 struct snd_emu10k1_fx8010_code *icode, 543 bool in_kernel) 544 { 545 int gpr; 546 u32 val; 547 548 for (gpr = 0; gpr < (emu->audigy ? 0x200 : 0x100); gpr++) { 549 if (!test_bit(gpr, icode->gpr_valid)) 550 continue; 551 if (in_kernel) 552 val = icode->gpr_map[gpr]; 553 else if (get_user(val, (__user u32 *)&icode->gpr_map[gpr])) 554 return -EFAULT; 555 snd_emu10k1_ptr_write(emu, emu->gpr_base + gpr, 0, val); 556 } 557 return 0; 558 } 559 560 static int snd_emu10k1_gpr_peek(struct snd_emu10k1 *emu, 561 struct snd_emu10k1_fx8010_code *icode) 562 { 563 int gpr; 564 u32 val; 565 566 for (gpr = 0; gpr < (emu->audigy ? 0x200 : 0x100); gpr++) { 567 set_bit(gpr, icode->gpr_valid); 568 val = snd_emu10k1_ptr_read(emu, emu->gpr_base + gpr, 0); 569 if (put_user(val, (__user u32 *)&icode->gpr_map[gpr])) 570 return -EFAULT; 571 } 572 return 0; 573 } 574 575 static int snd_emu10k1_tram_poke(struct snd_emu10k1 *emu, 576 struct snd_emu10k1_fx8010_code *icode, 577 bool in_kernel) 578 { 579 int tram; 580 u32 addr, val; 581 582 for (tram = 0; tram < (emu->audigy ? 0x100 : 0xa0); tram++) { 583 if (!test_bit(tram, icode->tram_valid)) 584 continue; 585 if (in_kernel) { 586 val = icode->tram_data_map[tram]; 587 addr = icode->tram_addr_map[tram]; 588 } else { 589 if (get_user(val, (__user __u32 *)&icode->tram_data_map[tram]) || 590 get_user(addr, (__user __u32 *)&icode->tram_addr_map[tram])) 591 return -EFAULT; 592 } 593 snd_emu10k1_ptr_write(emu, TANKMEMDATAREGBASE + tram, 0, val); 594 if (!emu->audigy) { 595 snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + tram, 0, addr); 596 } else { 597 snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + tram, 0, addr << 12); 598 snd_emu10k1_ptr_write(emu, A_TANKMEMCTLREGBASE + tram, 0, addr >> 20); 599 } 600 } 601 return 0; 602 } 603 604 static int snd_emu10k1_tram_peek(struct snd_emu10k1 *emu, 605 struct snd_emu10k1_fx8010_code *icode) 606 { 607 int tram; 608 u32 val, addr; 609 610 memset(icode->tram_valid, 0, sizeof(icode->tram_valid)); 611 for (tram = 0; tram < (emu->audigy ? 0x100 : 0xa0); tram++) { 612 set_bit(tram, icode->tram_valid); 613 val = snd_emu10k1_ptr_read(emu, TANKMEMDATAREGBASE + tram, 0); 614 if (!emu->audigy) { 615 addr = snd_emu10k1_ptr_read(emu, TANKMEMADDRREGBASE + tram, 0); 616 } else { 617 addr = snd_emu10k1_ptr_read(emu, TANKMEMADDRREGBASE + tram, 0) >> 12; 618 addr |= snd_emu10k1_ptr_read(emu, A_TANKMEMCTLREGBASE + tram, 0) << 20; 619 } 620 if (put_user(val, (__user u32 *)&icode->tram_data_map[tram]) || 621 put_user(addr, (__user u32 *)&icode->tram_addr_map[tram])) 622 return -EFAULT; 623 } 624 return 0; 625 } 626 627 static int snd_emu10k1_code_poke(struct snd_emu10k1 *emu, 628 struct snd_emu10k1_fx8010_code *icode, 629 bool in_kernel) 630 { 631 u32 pc, lo, hi; 632 633 for (pc = 0; pc < (emu->audigy ? 2*1024 : 2*512); pc += 2) { 634 if (!test_bit(pc / 2, icode->code_valid)) 635 continue; 636 if (in_kernel) { 637 lo = icode->code[pc + 0]; 638 hi = icode->code[pc + 1]; 639 } else { 640 if (get_user(lo, (__user u32 *)&icode->code[pc + 0]) || 641 get_user(hi, (__user u32 *)&icode->code[pc + 1])) 642 return -EFAULT; 643 } 644 snd_emu10k1_efx_write(emu, pc + 0, lo); 645 snd_emu10k1_efx_write(emu, pc + 1, hi); 646 } 647 return 0; 648 } 649 650 static int snd_emu10k1_code_peek(struct snd_emu10k1 *emu, 651 struct snd_emu10k1_fx8010_code *icode) 652 { 653 u32 pc; 654 655 memset(icode->code_valid, 0, sizeof(icode->code_valid)); 656 for (pc = 0; pc < (emu->audigy ? 2*1024 : 2*512); pc += 2) { 657 set_bit(pc / 2, icode->code_valid); 658 if (put_user(snd_emu10k1_efx_read(emu, pc + 0), 659 (__user u32 *)&icode->code[pc + 0])) 660 return -EFAULT; 661 if (put_user(snd_emu10k1_efx_read(emu, pc + 1), 662 (__user u32 *)&icode->code[pc + 1])) 663 return -EFAULT; 664 } 665 return 0; 666 } 667 668 static struct snd_emu10k1_fx8010_ctl * 669 snd_emu10k1_look_for_ctl(struct snd_emu10k1 *emu, 670 struct emu10k1_ctl_elem_id *_id) 671 { 672 struct snd_ctl_elem_id *id = (struct snd_ctl_elem_id *)_id; 673 struct snd_emu10k1_fx8010_ctl *ctl; 674 struct snd_kcontrol *kcontrol; 675 676 list_for_each_entry(ctl, &emu->fx8010.gpr_ctl, list) { 677 kcontrol = ctl->kcontrol; 678 if (kcontrol->id.iface == id->iface && 679 kcontrol->id.index == id->index && 680 !strcmp(kcontrol->id.name, id->name)) 681 return ctl; 682 } 683 return NULL; 684 } 685 686 #define MAX_TLV_SIZE 256 687 688 static unsigned int *copy_tlv(const unsigned int __user *_tlv, bool in_kernel) 689 { 690 unsigned int data[2]; 691 unsigned int *tlv; 692 693 if (!_tlv) 694 return NULL; 695 if (in_kernel) 696 memcpy(data, (__force void *)_tlv, sizeof(data)); 697 else if (copy_from_user(data, _tlv, sizeof(data))) 698 return NULL; 699 if (data[1] >= MAX_TLV_SIZE) 700 return NULL; 701 tlv = kmalloc(data[1] + sizeof(data), GFP_KERNEL); 702 if (!tlv) 703 return NULL; 704 memcpy(tlv, data, sizeof(data)); 705 if (in_kernel) { 706 memcpy(tlv + 2, (__force void *)(_tlv + 2), data[1]); 707 } else if (copy_from_user(tlv + 2, _tlv + 2, data[1])) { 708 kfree(tlv); 709 return NULL; 710 } 711 return tlv; 712 } 713 714 static int copy_gctl(struct snd_emu10k1 *emu, 715 struct snd_emu10k1_fx8010_control_gpr *dst, 716 struct snd_emu10k1_fx8010_control_gpr *src, 717 int idx, bool in_kernel) 718 { 719 struct snd_emu10k1_fx8010_control_gpr __user *_src; 720 struct snd_emu10k1_fx8010_control_old_gpr *octl; 721 struct snd_emu10k1_fx8010_control_old_gpr __user *_octl; 722 723 _src = (struct snd_emu10k1_fx8010_control_gpr __user *)src; 724 if (emu->support_tlv) { 725 if (in_kernel) 726 *dst = src[idx]; 727 else if (copy_from_user(dst, &_src[idx], sizeof(*src))) 728 return -EFAULT; 729 return 0; 730 } 731 732 octl = (struct snd_emu10k1_fx8010_control_old_gpr *)src; 733 _octl = (struct snd_emu10k1_fx8010_control_old_gpr __user *)octl; 734 if (in_kernel) 735 memcpy(dst, &octl[idx], sizeof(*octl)); 736 else if (copy_from_user(dst, &_octl[idx], sizeof(*octl))) 737 return -EFAULT; 738 dst->tlv = NULL; 739 return 0; 740 } 741 742 static int copy_gctl_to_user(struct snd_emu10k1 *emu, 743 struct snd_emu10k1_fx8010_control_gpr *dst, 744 struct snd_emu10k1_fx8010_control_gpr *src, 745 int idx) 746 { 747 struct snd_emu10k1_fx8010_control_gpr __user *_dst; 748 struct snd_emu10k1_fx8010_control_old_gpr __user *octl; 749 750 _dst = (struct snd_emu10k1_fx8010_control_gpr __user *)dst; 751 if (emu->support_tlv) 752 return copy_to_user(&_dst[idx], src, sizeof(*src)); 753 754 octl = (struct snd_emu10k1_fx8010_control_old_gpr __user *)dst; 755 return copy_to_user(&octl[idx], src, sizeof(*octl)); 756 } 757 758 static int copy_ctl_elem_id(const struct emu10k1_ctl_elem_id *list, int i, 759 struct emu10k1_ctl_elem_id *ret, bool in_kernel) 760 { 761 struct emu10k1_ctl_elem_id __user *_id = 762 (struct emu10k1_ctl_elem_id __user *)&list[i]; 763 764 if (in_kernel) 765 *ret = list[i]; 766 else if (copy_from_user(ret, _id, sizeof(*ret))) 767 return -EFAULT; 768 return 0; 769 } 770 771 static int snd_emu10k1_verify_controls(struct snd_emu10k1 *emu, 772 struct snd_emu10k1_fx8010_code *icode, 773 bool in_kernel) 774 { 775 unsigned int i; 776 struct emu10k1_ctl_elem_id id; 777 struct snd_emu10k1_fx8010_control_gpr *gctl; 778 struct snd_ctl_elem_id *gctl_id; 779 int err; 780 781 for (i = 0; i < icode->gpr_del_control_count; i++) { 782 err = copy_ctl_elem_id(icode->gpr_del_controls, i, &id, 783 in_kernel); 784 if (err < 0) 785 return err; 786 if (snd_emu10k1_look_for_ctl(emu, &id) == NULL) 787 return -ENOENT; 788 } 789 gctl = kmalloc(sizeof(*gctl), GFP_KERNEL); 790 if (! gctl) 791 return -ENOMEM; 792 err = 0; 793 for (i = 0; i < icode->gpr_add_control_count; i++) { 794 if (copy_gctl(emu, gctl, icode->gpr_add_controls, i, 795 in_kernel)) { 796 err = -EFAULT; 797 goto __error; 798 } 799 if (snd_emu10k1_look_for_ctl(emu, &gctl->id)) 800 continue; 801 gctl_id = (struct snd_ctl_elem_id *)&gctl->id; 802 down_read(&emu->card->controls_rwsem); 803 if (snd_ctl_find_id(emu->card, gctl_id)) { 804 up_read(&emu->card->controls_rwsem); 805 err = -EEXIST; 806 goto __error; 807 } 808 up_read(&emu->card->controls_rwsem); 809 if (gctl_id->iface != SNDRV_CTL_ELEM_IFACE_MIXER && 810 gctl_id->iface != SNDRV_CTL_ELEM_IFACE_PCM) { 811 err = -EINVAL; 812 goto __error; 813 } 814 switch (gctl->translation) { 815 case EMU10K1_GPR_TRANSLATION_NONE: 816 case EMU10K1_GPR_TRANSLATION_NEGATE: 817 break; 818 case EMU10K1_GPR_TRANSLATION_TABLE100: 819 case EMU10K1_GPR_TRANSLATION_NEG_TABLE100: 820 if (gctl->min != 0 || gctl->max != 100) { 821 err = -EINVAL; 822 goto __error; 823 } 824 break; 825 case EMU10K1_GPR_TRANSLATION_BASS: 826 case EMU10K1_GPR_TRANSLATION_TREBLE: 827 if (gctl->min != 0 || gctl->max != 40) { 828 err = -EINVAL; 829 goto __error; 830 } 831 break; 832 case EMU10K1_GPR_TRANSLATION_ONOFF: 833 if (gctl->min != 0 || gctl->max != 1) { 834 err = -EINVAL; 835 goto __error; 836 } 837 break; 838 default: 839 err = -EINVAL; 840 goto __error; 841 } 842 } 843 for (i = 0; i < icode->gpr_list_control_count; i++) { 844 /* FIXME: we need to check the WRITE access */ 845 if (copy_gctl(emu, gctl, icode->gpr_list_controls, i, 846 in_kernel)) { 847 err = -EFAULT; 848 goto __error; 849 } 850 } 851 __error: 852 kfree(gctl); 853 return err; 854 } 855 856 static void snd_emu10k1_ctl_private_free(struct snd_kcontrol *kctl) 857 { 858 struct snd_emu10k1_fx8010_ctl *ctl; 859 860 ctl = (struct snd_emu10k1_fx8010_ctl *) kctl->private_value; 861 kctl->private_value = 0; 862 list_del(&ctl->list); 863 kfree(ctl); 864 kfree(kctl->tlv.p); 865 } 866 867 static int snd_emu10k1_add_controls(struct snd_emu10k1 *emu, 868 struct snd_emu10k1_fx8010_code *icode, 869 bool in_kernel) 870 { 871 unsigned int i, j; 872 struct snd_emu10k1_fx8010_control_gpr *gctl; 873 struct snd_ctl_elem_id *gctl_id; 874 struct snd_emu10k1_fx8010_ctl *ctl, *nctl; 875 struct snd_kcontrol_new knew; 876 struct snd_kcontrol *kctl; 877 struct snd_ctl_elem_value *val; 878 int err = 0; 879 880 val = kmalloc(sizeof(*val), GFP_KERNEL); 881 gctl = kmalloc(sizeof(*gctl), GFP_KERNEL); 882 nctl = kmalloc(sizeof(*nctl), GFP_KERNEL); 883 if (!val || !gctl || !nctl) { 884 err = -ENOMEM; 885 goto __error; 886 } 887 888 for (i = 0; i < icode->gpr_add_control_count; i++) { 889 if (copy_gctl(emu, gctl, icode->gpr_add_controls, i, 890 in_kernel)) { 891 err = -EFAULT; 892 goto __error; 893 } 894 gctl_id = (struct snd_ctl_elem_id *)&gctl->id; 895 if (gctl_id->iface != SNDRV_CTL_ELEM_IFACE_MIXER && 896 gctl_id->iface != SNDRV_CTL_ELEM_IFACE_PCM) { 897 err = -EINVAL; 898 goto __error; 899 } 900 if (!*gctl_id->name) { 901 err = -EINVAL; 902 goto __error; 903 } 904 ctl = snd_emu10k1_look_for_ctl(emu, &gctl->id); 905 memset(&knew, 0, sizeof(knew)); 906 knew.iface = gctl_id->iface; 907 knew.name = gctl_id->name; 908 knew.index = gctl_id->index; 909 knew.device = gctl_id->device; 910 knew.subdevice = gctl_id->subdevice; 911 knew.info = snd_emu10k1_gpr_ctl_info; 912 knew.tlv.p = copy_tlv((const unsigned int __user *)gctl->tlv, in_kernel); 913 if (knew.tlv.p) 914 knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE | 915 SNDRV_CTL_ELEM_ACCESS_TLV_READ; 916 knew.get = snd_emu10k1_gpr_ctl_get; 917 knew.put = snd_emu10k1_gpr_ctl_put; 918 memset(nctl, 0, sizeof(*nctl)); 919 nctl->vcount = gctl->vcount; 920 nctl->count = gctl->count; 921 for (j = 0; j < 32; j++) { 922 nctl->gpr[j] = gctl->gpr[j]; 923 nctl->value[j] = ~gctl->value[j]; /* inverted, we want to write new value in gpr_ctl_put() */ 924 val->value.integer.value[j] = gctl->value[j]; 925 } 926 nctl->min = gctl->min; 927 nctl->max = gctl->max; 928 nctl->translation = gctl->translation; 929 if (ctl == NULL) { 930 ctl = kmalloc(sizeof(*ctl), GFP_KERNEL); 931 if (ctl == NULL) { 932 err = -ENOMEM; 933 kfree(knew.tlv.p); 934 goto __error; 935 } 936 knew.private_value = (unsigned long)ctl; 937 *ctl = *nctl; 938 kctl = snd_ctl_new1(&knew, emu); 939 err = snd_ctl_add(emu->card, kctl); 940 if (err < 0) { 941 kfree(ctl); 942 kfree(knew.tlv.p); 943 goto __error; 944 } 945 kctl->private_free = snd_emu10k1_ctl_private_free; 946 ctl->kcontrol = kctl; 947 list_add_tail(&ctl->list, &emu->fx8010.gpr_ctl); 948 } else { 949 /* overwrite */ 950 nctl->list = ctl->list; 951 nctl->kcontrol = ctl->kcontrol; 952 *ctl = *nctl; 953 snd_ctl_notify(emu->card, SNDRV_CTL_EVENT_MASK_VALUE | 954 SNDRV_CTL_EVENT_MASK_INFO, &ctl->kcontrol->id); 955 } 956 snd_emu10k1_gpr_ctl_put(ctl->kcontrol, val); 957 } 958 __error: 959 kfree(nctl); 960 kfree(gctl); 961 kfree(val); 962 return err; 963 } 964 965 static int snd_emu10k1_del_controls(struct snd_emu10k1 *emu, 966 struct snd_emu10k1_fx8010_code *icode, 967 bool in_kernel) 968 { 969 unsigned int i; 970 struct emu10k1_ctl_elem_id id; 971 struct snd_emu10k1_fx8010_ctl *ctl; 972 struct snd_card *card = emu->card; 973 int err; 974 975 for (i = 0; i < icode->gpr_del_control_count; i++) { 976 err = copy_ctl_elem_id(icode->gpr_del_controls, i, &id, 977 in_kernel); 978 if (err < 0) 979 return err; 980 down_write(&card->controls_rwsem); 981 ctl = snd_emu10k1_look_for_ctl(emu, &id); 982 if (ctl) 983 snd_ctl_remove(card, ctl->kcontrol); 984 up_write(&card->controls_rwsem); 985 } 986 return 0; 987 } 988 989 static int snd_emu10k1_list_controls(struct snd_emu10k1 *emu, 990 struct snd_emu10k1_fx8010_code *icode) 991 { 992 unsigned int i = 0, j; 993 unsigned int total = 0; 994 struct snd_emu10k1_fx8010_control_gpr *gctl; 995 struct snd_emu10k1_fx8010_ctl *ctl; 996 struct snd_ctl_elem_id *id; 997 998 gctl = kmalloc(sizeof(*gctl), GFP_KERNEL); 999 if (! gctl) 1000 return -ENOMEM; 1001 1002 list_for_each_entry(ctl, &emu->fx8010.gpr_ctl, list) { 1003 total++; 1004 if (icode->gpr_list_controls && 1005 i < icode->gpr_list_control_count) { 1006 memset(gctl, 0, sizeof(*gctl)); 1007 id = &ctl->kcontrol->id; 1008 gctl->id.iface = (__force int)id->iface; 1009 strscpy(gctl->id.name, id->name, sizeof(gctl->id.name)); 1010 gctl->id.index = id->index; 1011 gctl->id.device = id->device; 1012 gctl->id.subdevice = id->subdevice; 1013 gctl->vcount = ctl->vcount; 1014 gctl->count = ctl->count; 1015 for (j = 0; j < 32; j++) { 1016 gctl->gpr[j] = ctl->gpr[j]; 1017 gctl->value[j] = ctl->value[j]; 1018 } 1019 gctl->min = ctl->min; 1020 gctl->max = ctl->max; 1021 gctl->translation = ctl->translation; 1022 if (copy_gctl_to_user(emu, icode->gpr_list_controls, 1023 gctl, i)) { 1024 kfree(gctl); 1025 return -EFAULT; 1026 } 1027 i++; 1028 } 1029 } 1030 icode->gpr_list_control_total = total; 1031 kfree(gctl); 1032 return 0; 1033 } 1034 1035 static int snd_emu10k1_icode_poke(struct snd_emu10k1 *emu, 1036 struct snd_emu10k1_fx8010_code *icode, 1037 bool in_kernel) 1038 { 1039 int err = 0; 1040 1041 mutex_lock(&emu->fx8010.lock); 1042 err = snd_emu10k1_verify_controls(emu, icode, in_kernel); 1043 if (err < 0) 1044 goto __error; 1045 strscpy(emu->fx8010.name, icode->name, sizeof(emu->fx8010.name)); 1046 /* stop FX processor - this may be dangerous, but it's better to miss 1047 some samples than generate wrong ones - [jk] */ 1048 if (emu->audigy) 1049 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg | A_DBG_SINGLE_STEP); 1050 else 1051 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg | EMU10K1_DBG_SINGLE_STEP); 1052 /* ok, do the main job */ 1053 err = snd_emu10k1_del_controls(emu, icode, in_kernel); 1054 if (err < 0) 1055 goto __error; 1056 err = snd_emu10k1_gpr_poke(emu, icode, in_kernel); 1057 if (err < 0) 1058 goto __error; 1059 err = snd_emu10k1_tram_poke(emu, icode, in_kernel); 1060 if (err < 0) 1061 goto __error; 1062 err = snd_emu10k1_code_poke(emu, icode, in_kernel); 1063 if (err < 0) 1064 goto __error; 1065 err = snd_emu10k1_add_controls(emu, icode, in_kernel); 1066 if (err < 0) 1067 goto __error; 1068 /* start FX processor when the DSP code is updated */ 1069 if (emu->audigy) 1070 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg); 1071 else 1072 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg); 1073 __error: 1074 mutex_unlock(&emu->fx8010.lock); 1075 return err; 1076 } 1077 1078 static int snd_emu10k1_icode_peek(struct snd_emu10k1 *emu, 1079 struct snd_emu10k1_fx8010_code *icode) 1080 { 1081 int err; 1082 1083 mutex_lock(&emu->fx8010.lock); 1084 strscpy(icode->name, emu->fx8010.name, sizeof(icode->name)); 1085 /* ok, do the main job */ 1086 err = snd_emu10k1_gpr_peek(emu, icode); 1087 if (err >= 0) 1088 err = snd_emu10k1_tram_peek(emu, icode); 1089 if (err >= 0) 1090 err = snd_emu10k1_code_peek(emu, icode); 1091 if (err >= 0) 1092 err = snd_emu10k1_list_controls(emu, icode); 1093 mutex_unlock(&emu->fx8010.lock); 1094 return err; 1095 } 1096 1097 static int snd_emu10k1_ipcm_poke(struct snd_emu10k1 *emu, 1098 struct snd_emu10k1_fx8010_pcm_rec *ipcm) 1099 { 1100 unsigned int i; 1101 int err = 0; 1102 struct snd_emu10k1_fx8010_pcm *pcm; 1103 1104 if (ipcm->substream >= EMU10K1_FX8010_PCM_COUNT) 1105 return -EINVAL; 1106 ipcm->substream = array_index_nospec(ipcm->substream, 1107 EMU10K1_FX8010_PCM_COUNT); 1108 if (ipcm->channels > 32) 1109 return -EINVAL; 1110 pcm = &emu->fx8010.pcm[ipcm->substream]; 1111 mutex_lock(&emu->fx8010.lock); 1112 spin_lock_irq(&emu->reg_lock); 1113 if (pcm->opened) { 1114 err = -EBUSY; 1115 goto __error; 1116 } 1117 if (ipcm->channels == 0) { /* remove */ 1118 pcm->valid = 0; 1119 } else { 1120 /* FIXME: we need to add universal code to the PCM transfer routine */ 1121 if (ipcm->channels != 2) { 1122 err = -EINVAL; 1123 goto __error; 1124 } 1125 pcm->valid = 1; 1126 pcm->opened = 0; 1127 pcm->channels = ipcm->channels; 1128 pcm->tram_start = ipcm->tram_start; 1129 pcm->buffer_size = ipcm->buffer_size; 1130 pcm->gpr_size = ipcm->gpr_size; 1131 pcm->gpr_count = ipcm->gpr_count; 1132 pcm->gpr_tmpcount = ipcm->gpr_tmpcount; 1133 pcm->gpr_ptr = ipcm->gpr_ptr; 1134 pcm->gpr_trigger = ipcm->gpr_trigger; 1135 pcm->gpr_running = ipcm->gpr_running; 1136 for (i = 0; i < pcm->channels; i++) 1137 pcm->etram[i] = ipcm->etram[i]; 1138 } 1139 __error: 1140 spin_unlock_irq(&emu->reg_lock); 1141 mutex_unlock(&emu->fx8010.lock); 1142 return err; 1143 } 1144 1145 static int snd_emu10k1_ipcm_peek(struct snd_emu10k1 *emu, 1146 struct snd_emu10k1_fx8010_pcm_rec *ipcm) 1147 { 1148 unsigned int i; 1149 int err = 0; 1150 struct snd_emu10k1_fx8010_pcm *pcm; 1151 1152 if (ipcm->substream >= EMU10K1_FX8010_PCM_COUNT) 1153 return -EINVAL; 1154 ipcm->substream = array_index_nospec(ipcm->substream, 1155 EMU10K1_FX8010_PCM_COUNT); 1156 pcm = &emu->fx8010.pcm[ipcm->substream]; 1157 mutex_lock(&emu->fx8010.lock); 1158 spin_lock_irq(&emu->reg_lock); 1159 ipcm->channels = pcm->channels; 1160 ipcm->tram_start = pcm->tram_start; 1161 ipcm->buffer_size = pcm->buffer_size; 1162 ipcm->gpr_size = pcm->gpr_size; 1163 ipcm->gpr_ptr = pcm->gpr_ptr; 1164 ipcm->gpr_count = pcm->gpr_count; 1165 ipcm->gpr_tmpcount = pcm->gpr_tmpcount; 1166 ipcm->gpr_trigger = pcm->gpr_trigger; 1167 ipcm->gpr_running = pcm->gpr_running; 1168 for (i = 0; i < pcm->channels; i++) 1169 ipcm->etram[i] = pcm->etram[i]; 1170 ipcm->res1 = ipcm->res2 = 0; 1171 ipcm->pad = 0; 1172 spin_unlock_irq(&emu->reg_lock); 1173 mutex_unlock(&emu->fx8010.lock); 1174 return err; 1175 } 1176 1177 #define SND_EMU10K1_GPR_CONTROLS 44 1178 #define SND_EMU10K1_INPUTS 12 1179 #define SND_EMU10K1_PLAYBACK_CHANNELS 8 1180 #define SND_EMU10K1_CAPTURE_CHANNELS 4 1181 1182 #define HR_VAL(v) ((v) * 0x80000000LL / 100 - 1) 1183 1184 static void 1185 snd_emu10k1_init_mono_control2(struct snd_emu10k1_fx8010_control_gpr *ctl, 1186 const char *name, int gpr, int defval, int defval_hr) 1187 { 1188 ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER; 1189 strcpy(ctl->id.name, name); 1190 ctl->vcount = ctl->count = 1; 1191 if (high_res_gpr_volume) { 1192 ctl->min = -1; 1193 ctl->max = 0x7fffffff; 1194 ctl->tlv = snd_emu10k1_db_linear; 1195 ctl->translation = EMU10K1_GPR_TRANSLATION_NEGATE; 1196 defval = defval_hr; 1197 } else { 1198 ctl->min = 0; 1199 ctl->max = 100; 1200 ctl->tlv = snd_emu10k1_db_scale1; 1201 ctl->translation = EMU10K1_GPR_TRANSLATION_NEG_TABLE100; 1202 } 1203 ctl->gpr[0] = gpr + 0; ctl->value[0] = defval; 1204 } 1205 #define snd_emu10k1_init_mono_control(ctl, name, gpr, defval) \ 1206 snd_emu10k1_init_mono_control2(ctl, name, gpr, defval, HR_VAL(defval)) 1207 1208 static void 1209 snd_emu10k1_init_stereo_control2(struct snd_emu10k1_fx8010_control_gpr *ctl, 1210 const char *name, int gpr, int defval, int defval_hr) 1211 { 1212 ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER; 1213 strcpy(ctl->id.name, name); 1214 ctl->vcount = ctl->count = 2; 1215 if (high_res_gpr_volume) { 1216 ctl->min = -1; 1217 ctl->max = 0x7fffffff; 1218 ctl->tlv = snd_emu10k1_db_linear; 1219 ctl->translation = EMU10K1_GPR_TRANSLATION_NEGATE; 1220 defval = defval_hr; 1221 } else { 1222 ctl->min = 0; 1223 ctl->max = 100; 1224 ctl->tlv = snd_emu10k1_db_scale1; 1225 ctl->translation = EMU10K1_GPR_TRANSLATION_NEG_TABLE100; 1226 } 1227 ctl->gpr[0] = gpr + 0; ctl->value[0] = defval; 1228 ctl->gpr[1] = gpr + 1; ctl->value[1] = defval; 1229 } 1230 #define snd_emu10k1_init_stereo_control(ctl, name, gpr, defval) \ 1231 snd_emu10k1_init_stereo_control2(ctl, name, gpr, defval, HR_VAL(defval)) 1232 1233 static void 1234 snd_emu10k1_init_mono_onoff_control(struct snd_emu10k1_fx8010_control_gpr *ctl, 1235 const char *name, int gpr, int defval) 1236 { 1237 ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER; 1238 strcpy(ctl->id.name, name); 1239 ctl->vcount = ctl->count = 1; 1240 ctl->gpr[0] = gpr + 0; ctl->value[0] = defval; 1241 ctl->min = 0; 1242 ctl->max = 1; 1243 ctl->translation = EMU10K1_GPR_TRANSLATION_ONOFF; 1244 } 1245 1246 static void 1247 snd_emu10k1_init_stereo_onoff_control(struct snd_emu10k1_fx8010_control_gpr *ctl, 1248 const char *name, int gpr, int defval) 1249 { 1250 ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER; 1251 strcpy(ctl->id.name, name); 1252 ctl->vcount = ctl->count = 2; 1253 ctl->gpr[0] = gpr + 0; ctl->value[0] = defval; 1254 ctl->gpr[1] = gpr + 1; ctl->value[1] = defval; 1255 ctl->min = 0; 1256 ctl->max = 1; 1257 ctl->translation = EMU10K1_GPR_TRANSLATION_ONOFF; 1258 } 1259 1260 /* 1261 * Used for emu1010 - conversion from 32-bit capture inputs from the FPGA 1262 * to 2 x 16-bit registers in Audigy - their values are read via DMA. 1263 * Conversion is performed by Audigy DSP instructions of FX8010. 1264 */ 1265 static void snd_emu10k1_audigy_dsp_convert_32_to_2x16( 1266 struct snd_emu10k1_fx8010_code *icode, 1267 u32 *ptr, int tmp, int bit_shifter16, 1268 int reg_in, int reg_out) 1269 { 1270 // This leaves the low word in place, which is fine, 1271 // as the low bits are completely ignored subsequently. 1272 // reg_out[1] = reg_in 1273 A_OP(icode, ptr, iACC3, reg_out + 1, reg_in, A_C_00000000, A_C_00000000); 1274 // It is fine to read reg_in multiple times. 1275 // tmp = reg_in << 15 1276 A_OP(icode, ptr, iMACINT1, A_GPR(tmp), A_C_00000000, reg_in, A_GPR(bit_shifter16)); 1277 // Left-shift once more. This is a separate step, as the 1278 // signed multiplication would clobber the MSB. 1279 // reg_out[0] = tmp + ((tmp << 31) >> 31) 1280 A_OP(icode, ptr, iMAC3, reg_out, A_GPR(tmp), A_GPR(tmp), A_C_80000000); 1281 } 1282 1283 #define ENUM_GPR(name, size) name, name ## _dummy = name + (size) - 1 1284 1285 /* 1286 * initial DSP configuration for Audigy 1287 */ 1288 1289 static int _snd_emu10k1_audigy_init_efx(struct snd_emu10k1 *emu) 1290 { 1291 int err, z, nctl; 1292 enum { 1293 ENUM_GPR(playback, SND_EMU10K1_PLAYBACK_CHANNELS), 1294 ENUM_GPR(stereo_mix, 2), 1295 ENUM_GPR(capture, 2), 1296 ENUM_GPR(bit_shifter16, 1), 1297 // The fixed allocation of these breaks the pattern, but why not. 1298 // Splitting these into left/right is questionable, as it will break 1299 // down for center/lfe. But it works for stereo/quadro, so whatever. 1300 ENUM_GPR(bass_gpr, 2 * 5), // two sides, five coefficients 1301 ENUM_GPR(treble_gpr, 2 * 5), 1302 ENUM_GPR(bass_tmp, SND_EMU10K1_PLAYBACK_CHANNELS * 4), // four delay stages 1303 ENUM_GPR(treble_tmp, SND_EMU10K1_PLAYBACK_CHANNELS * 4), 1304 ENUM_GPR(tmp, 3), 1305 num_static_gprs 1306 }; 1307 int gpr = num_static_gprs; 1308 u32 ptr, ptr_skip; 1309 struct snd_emu10k1_fx8010_code *icode = NULL; 1310 struct snd_emu10k1_fx8010_control_gpr *controls = NULL, *ctl; 1311 u32 *gpr_map; 1312 1313 err = -ENOMEM; 1314 icode = kzalloc(sizeof(*icode), GFP_KERNEL); 1315 if (!icode) 1316 return err; 1317 1318 icode->gpr_map = kcalloc(512 + 256 + 256 + 2 * 1024, 1319 sizeof(u_int32_t), GFP_KERNEL); 1320 if (!icode->gpr_map) 1321 goto __err_gpr; 1322 controls = kcalloc(SND_EMU10K1_GPR_CONTROLS, 1323 sizeof(*controls), GFP_KERNEL); 1324 if (!controls) 1325 goto __err_ctrls; 1326 1327 gpr_map = icode->gpr_map; 1328 1329 icode->tram_data_map = icode->gpr_map + 512; 1330 icode->tram_addr_map = icode->tram_data_map + 256; 1331 icode->code = icode->tram_addr_map + 256; 1332 1333 /* clear free GPRs */ 1334 memset(icode->gpr_valid, 0xff, 512 / 8); 1335 1336 /* clear TRAM data & address lines */ 1337 memset(icode->tram_valid, 0xff, 256 / 8); 1338 1339 strcpy(icode->name, "Audigy DSP code for ALSA"); 1340 ptr = 0; 1341 nctl = 0; 1342 gpr_map[bit_shifter16] = 0x00008000; 1343 1344 #if 1 1345 /* PCM front Playback Volume (independent from stereo mix) 1346 * playback = -gpr * FXBUS_PCM_LEFT_FRONT >> 31 1347 * where gpr contains negated attenuation from corresponding mixer control 1348 * (snd_emu10k1_init_stereo_control) 1349 */ 1350 A_OP(icode, &ptr, iMAC1, A_GPR(playback), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT_FRONT)); 1351 A_OP(icode, &ptr, iMAC1, A_GPR(playback+1), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT_FRONT)); 1352 snd_emu10k1_init_stereo_control(&controls[nctl++], "PCM Front Playback Volume", gpr, 100); 1353 gpr += 2; 1354 1355 /* PCM Surround Playback (independent from stereo mix) */ 1356 A_OP(icode, &ptr, iMAC1, A_GPR(playback+2), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT_REAR)); 1357 A_OP(icode, &ptr, iMAC1, A_GPR(playback+3), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT_REAR)); 1358 snd_emu10k1_init_stereo_control(&controls[nctl++], "PCM Surround Playback Volume", gpr, 100); 1359 gpr += 2; 1360 1361 /* PCM Side Playback (independent from stereo mix) */ 1362 if (emu->card_capabilities->spk71) { 1363 A_OP(icode, &ptr, iMAC1, A_GPR(playback+6), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT_SIDE)); 1364 A_OP(icode, &ptr, iMAC1, A_GPR(playback+7), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT_SIDE)); 1365 snd_emu10k1_init_stereo_control(&controls[nctl++], "PCM Side Playback Volume", gpr, 100); 1366 gpr += 2; 1367 } 1368 1369 /* PCM Center Playback (independent from stereo mix) */ 1370 A_OP(icode, &ptr, iMAC1, A_GPR(playback+4), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_CENTER)); 1371 snd_emu10k1_init_mono_control(&controls[nctl++], "PCM Center Playback Volume", gpr, 100); 1372 gpr++; 1373 1374 /* PCM LFE Playback (independent from stereo mix) */ 1375 A_OP(icode, &ptr, iMAC1, A_GPR(playback+5), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LFE)); 1376 snd_emu10k1_init_mono_control(&controls[nctl++], "PCM LFE Playback Volume", gpr, 100); 1377 gpr++; 1378 1379 /* 1380 * Stereo Mix 1381 */ 1382 /* Wave (PCM) Playback Volume (will be renamed later) */ 1383 A_OP(icode, &ptr, iMAC1, A_GPR(stereo_mix), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT)); 1384 A_OP(icode, &ptr, iMAC1, A_GPR(stereo_mix+1), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT)); 1385 snd_emu10k1_init_stereo_control(&controls[nctl++], "Wave Playback Volume", gpr, 100); 1386 gpr += 2; 1387 1388 /* Synth Playback */ 1389 A_OP(icode, &ptr, iMAC1, A_GPR(stereo_mix+0), A_GPR(stereo_mix+0), A_GPR(gpr), A_FXBUS(FXBUS_MIDI_LEFT)); 1390 A_OP(icode, &ptr, iMAC1, A_GPR(stereo_mix+1), A_GPR(stereo_mix+1), A_GPR(gpr+1), A_FXBUS(FXBUS_MIDI_RIGHT)); 1391 snd_emu10k1_init_stereo_control(&controls[nctl++], "Synth Playback Volume", gpr, 100); 1392 gpr += 2; 1393 1394 /* Wave (PCM) Capture */ 1395 A_OP(icode, &ptr, iMAC1, A_GPR(capture+0), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT)); 1396 A_OP(icode, &ptr, iMAC1, A_GPR(capture+1), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT)); 1397 snd_emu10k1_init_stereo_control(&controls[nctl++], "PCM Capture Volume", gpr, 0); 1398 gpr += 2; 1399 1400 /* Synth Capture */ 1401 A_OP(icode, &ptr, iMAC1, A_GPR(capture+0), A_GPR(capture+0), A_GPR(gpr), A_FXBUS(FXBUS_MIDI_LEFT)); 1402 A_OP(icode, &ptr, iMAC1, A_GPR(capture+1), A_GPR(capture+1), A_GPR(gpr+1), A_FXBUS(FXBUS_MIDI_RIGHT)); 1403 snd_emu10k1_init_stereo_control(&controls[nctl++], "Synth Capture Volume", gpr, 0); 1404 gpr += 2; 1405 1406 // We need to double the volume, as we configure the voices for half volume, 1407 // which is necessary for bit-identical reproduction. 1408 { static_assert(stereo_mix == playback + SND_EMU10K1_PLAYBACK_CHANNELS); } 1409 for (z = 0; z < SND_EMU10K1_PLAYBACK_CHANNELS + 2; z++) 1410 A_OP(icode, &ptr, iACC3, A_GPR(playback + z), A_GPR(playback + z), A_GPR(playback + z), A_C_00000000); 1411 1412 /* 1413 * inputs 1414 */ 1415 #define A_ADD_VOLUME_IN(var,vol,input) \ 1416 A_OP(icode, &ptr, iMAC1, A_GPR(var), A_GPR(var), A_GPR(vol), A_EXTIN(input)) 1417 1418 if (emu->card_capabilities->emu_model) { 1419 /* EMU1010 DSP 0 and DSP 1 Capture */ 1420 // The 24 MSB hold the actual value. We implicitly discard the 16 LSB. 1421 if (emu->card_capabilities->ca0108_chip) { 1422 // For unclear reasons, the EMU32IN cannot be the Y operand! 1423 A_OP(icode, &ptr, iMAC1, A_GPR(capture+0), A_GPR(capture+0), A3_EMU32IN(0x0), A_GPR(gpr)); 1424 // A3_EMU32IN(0) is delayed by one sample, so all other A3_EMU32IN channels 1425 // need to be delayed as well; we use an auxiliary register for that. 1426 A_OP(icode, &ptr, iMAC1, A_GPR(capture+1), A_GPR(capture+1), A_GPR(gpr+2), A_GPR(gpr+1)); 1427 A_OP(icode, &ptr, iACC3, A_GPR(gpr+2), A3_EMU32IN(0x1), A_C_00000000, A_C_00000000); 1428 } else { 1429 A_OP(icode, &ptr, iMAC1, A_GPR(capture+0), A_GPR(capture+0), A_P16VIN(0x0), A_GPR(gpr)); 1430 // A_P16VIN(0) is delayed by one sample, so all other A_P16VIN channels 1431 // need to be delayed as well; we use an auxiliary register for that. 1432 A_OP(icode, &ptr, iMAC1, A_GPR(capture+1), A_GPR(capture+1), A_GPR(gpr+2), A_GPR(gpr+1)); 1433 A_OP(icode, &ptr, iACC3, A_GPR(gpr+2), A_P16VIN(0x1), A_C_00000000, A_C_00000000); 1434 } 1435 snd_emu10k1_init_stereo_control(&controls[nctl++], "EMU Capture Volume", gpr, 0); 1436 gpr_map[gpr + 2] = 0x00000000; 1437 gpr += 3; 1438 } else { 1439 if (emu->card_capabilities->ac97_chip) { 1440 /* AC'97 Playback Volume - used only for mic (renamed later) */ 1441 A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_AC97_L); 1442 A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_AC97_R); 1443 snd_emu10k1_init_stereo_control(&controls[nctl++], "AMic Playback Volume", gpr, 0); 1444 gpr += 2; 1445 /* AC'97 Capture Volume - used only for mic */ 1446 A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_AC97_L); 1447 A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_AC97_R); 1448 snd_emu10k1_init_stereo_control(&controls[nctl++], "Mic Capture Volume", gpr, 0); 1449 gpr += 2; 1450 1451 /* mic capture buffer */ 1452 A_OP(icode, &ptr, iINTERP, A_EXTOUT(A_EXTOUT_MIC_CAP), A_EXTIN(A_EXTIN_AC97_L), A_C_40000000, A_EXTIN(A_EXTIN_AC97_R)); 1453 } 1454 1455 /* Audigy CD Playback Volume */ 1456 A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_SPDIF_CD_L); 1457 A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_SPDIF_CD_R); 1458 snd_emu10k1_init_stereo_control(&controls[nctl++], 1459 emu->card_capabilities->ac97_chip ? "Audigy CD Playback Volume" : "CD Playback Volume", 1460 gpr, 0); 1461 gpr += 2; 1462 /* Audigy CD Capture Volume */ 1463 A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_SPDIF_CD_L); 1464 A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_SPDIF_CD_R); 1465 snd_emu10k1_init_stereo_control(&controls[nctl++], 1466 emu->card_capabilities->ac97_chip ? "Audigy CD Capture Volume" : "CD Capture Volume", 1467 gpr, 0); 1468 gpr += 2; 1469 1470 /* Optical SPDIF Playback Volume */ 1471 A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_OPT_SPDIF_L); 1472 A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_OPT_SPDIF_R); 1473 snd_emu10k1_init_stereo_control(&controls[nctl++], SNDRV_CTL_NAME_IEC958("Optical ",PLAYBACK,VOLUME), gpr, 0); 1474 gpr += 2; 1475 /* Optical SPDIF Capture Volume */ 1476 A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_OPT_SPDIF_L); 1477 A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_OPT_SPDIF_R); 1478 snd_emu10k1_init_stereo_control(&controls[nctl++], SNDRV_CTL_NAME_IEC958("Optical ",CAPTURE,VOLUME), gpr, 0); 1479 gpr += 2; 1480 1481 /* Line2 Playback Volume */ 1482 A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_LINE2_L); 1483 A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_LINE2_R); 1484 snd_emu10k1_init_stereo_control(&controls[nctl++], 1485 emu->card_capabilities->ac97_chip ? "Line2 Playback Volume" : "Line Playback Volume", 1486 gpr, 0); 1487 gpr += 2; 1488 /* Line2 Capture Volume */ 1489 A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_LINE2_L); 1490 A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_LINE2_R); 1491 snd_emu10k1_init_stereo_control(&controls[nctl++], 1492 emu->card_capabilities->ac97_chip ? "Line2 Capture Volume" : "Line Capture Volume", 1493 gpr, 0); 1494 gpr += 2; 1495 1496 /* Philips ADC Playback Volume */ 1497 A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_ADC_L); 1498 A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_ADC_R); 1499 snd_emu10k1_init_stereo_control(&controls[nctl++], "Analog Mix Playback Volume", gpr, 0); 1500 gpr += 2; 1501 /* Philips ADC Capture Volume */ 1502 A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_ADC_L); 1503 A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_ADC_R); 1504 snd_emu10k1_init_stereo_control(&controls[nctl++], "Analog Mix Capture Volume", gpr, 0); 1505 gpr += 2; 1506 1507 /* Aux2 Playback Volume */ 1508 A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_AUX2_L); 1509 A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_AUX2_R); 1510 snd_emu10k1_init_stereo_control(&controls[nctl++], 1511 emu->card_capabilities->ac97_chip ? "Aux2 Playback Volume" : "Aux Playback Volume", 1512 gpr, 0); 1513 gpr += 2; 1514 /* Aux2 Capture Volume */ 1515 A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_AUX2_L); 1516 A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_AUX2_R); 1517 snd_emu10k1_init_stereo_control(&controls[nctl++], 1518 emu->card_capabilities->ac97_chip ? "Aux2 Capture Volume" : "Aux Capture Volume", 1519 gpr, 0); 1520 gpr += 2; 1521 } 1522 1523 /* Stereo Mix Front Playback Volume */ 1524 A_OP(icode, &ptr, iMAC1, A_GPR(playback), A_GPR(playback), A_GPR(gpr), A_GPR(stereo_mix)); 1525 A_OP(icode, &ptr, iMAC1, A_GPR(playback+1), A_GPR(playback+1), A_GPR(gpr+1), A_GPR(stereo_mix+1)); 1526 snd_emu10k1_init_stereo_control(&controls[nctl++], "Front Playback Volume", gpr, 100); 1527 gpr += 2; 1528 1529 /* Stereo Mix Surround Playback */ 1530 A_OP(icode, &ptr, iMAC1, A_GPR(playback+2), A_GPR(playback+2), A_GPR(gpr), A_GPR(stereo_mix)); 1531 A_OP(icode, &ptr, iMAC1, A_GPR(playback+3), A_GPR(playback+3), A_GPR(gpr+1), A_GPR(stereo_mix+1)); 1532 snd_emu10k1_init_stereo_control(&controls[nctl++], "Surround Playback Volume", gpr, 0); 1533 gpr += 2; 1534 1535 /* Stereo Mix Center Playback */ 1536 /* Center = sub = Left/2 + Right/2 */ 1537 A_OP(icode, &ptr, iINTERP, A_GPR(tmp), A_GPR(stereo_mix), A_C_40000000, A_GPR(stereo_mix+1)); 1538 A_OP(icode, &ptr, iMAC1, A_GPR(playback+4), A_GPR(playback+4), A_GPR(gpr), A_GPR(tmp)); 1539 snd_emu10k1_init_mono_control(&controls[nctl++], "Center Playback Volume", gpr, 0); 1540 gpr++; 1541 1542 /* Stereo Mix LFE Playback */ 1543 A_OP(icode, &ptr, iMAC1, A_GPR(playback+5), A_GPR(playback+5), A_GPR(gpr), A_GPR(tmp)); 1544 snd_emu10k1_init_mono_control(&controls[nctl++], "LFE Playback Volume", gpr, 0); 1545 gpr++; 1546 1547 if (emu->card_capabilities->spk71) { 1548 /* Stereo Mix Side Playback */ 1549 A_OP(icode, &ptr, iMAC1, A_GPR(playback+6), A_GPR(playback+6), A_GPR(gpr), A_GPR(stereo_mix)); 1550 A_OP(icode, &ptr, iMAC1, A_GPR(playback+7), A_GPR(playback+7), A_GPR(gpr+1), A_GPR(stereo_mix+1)); 1551 snd_emu10k1_init_stereo_control(&controls[nctl++], "Side Playback Volume", gpr, 0); 1552 gpr += 2; 1553 } 1554 1555 /* 1556 * outputs 1557 */ 1558 #define A_PUT_OUTPUT(out,src) A_OP(icode, &ptr, iACC3, A_EXTOUT(out), A_C_00000000, A_C_00000000, A_GPR(src)) 1559 #define A_PUT_STEREO_OUTPUT(out1,out2,src) \ 1560 {A_PUT_OUTPUT(out1,src); A_PUT_OUTPUT(out2,src+1);} 1561 1562 #define _A_SWITCH(icode, ptr, dst, src, sw) \ 1563 A_OP((icode), ptr, iMACINT0, dst, A_C_00000000, src, sw); 1564 #define A_SWITCH(icode, ptr, dst, src, sw) \ 1565 _A_SWITCH(icode, ptr, A_GPR(dst), A_GPR(src), A_GPR(sw)) 1566 #define _A_SWITCH_NEG(icode, ptr, dst, src) \ 1567 A_OP((icode), ptr, iANDXOR, dst, src, A_C_00000001, A_C_00000001); 1568 #define A_SWITCH_NEG(icode, ptr, dst, src) \ 1569 _A_SWITCH_NEG(icode, ptr, A_GPR(dst), A_GPR(src)) 1570 1571 1572 /* 1573 * Process tone control 1574 */ 1575 ctl = &controls[nctl + 0]; 1576 ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER; 1577 strcpy(ctl->id.name, "Tone Control - Bass"); 1578 ctl->vcount = 2; 1579 ctl->count = 10; 1580 ctl->min = 0; 1581 ctl->max = 40; 1582 ctl->value[0] = ctl->value[1] = 20; 1583 ctl->translation = EMU10K1_GPR_TRANSLATION_BASS; 1584 ctl = &controls[nctl + 1]; 1585 ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER; 1586 strcpy(ctl->id.name, "Tone Control - Treble"); 1587 ctl->vcount = 2; 1588 ctl->count = 10; 1589 ctl->min = 0; 1590 ctl->max = 40; 1591 ctl->value[0] = ctl->value[1] = 20; 1592 ctl->translation = EMU10K1_GPR_TRANSLATION_TREBLE; 1593 for (z = 0; z < 5; z++) { 1594 int j; 1595 for (j = 0; j < 2; j++) { 1596 controls[nctl + 0].gpr[z * 2 + j] = bass_gpr + z * 2 + j; 1597 controls[nctl + 1].gpr[z * 2 + j] = treble_gpr + z * 2 + j; 1598 } 1599 } 1600 nctl += 2; 1601 1602 A_OP(icode, &ptr, iACC3, A_C_00000000, A_GPR(gpr), A_C_00000000, A_C_00000000); 1603 snd_emu10k1_init_mono_onoff_control(controls + nctl++, "Tone Control - Switch", gpr, 0); 1604 gpr++; 1605 A_OP(icode, &ptr, iSKIP, A_GPR_COND, A_GPR_COND, A_CC_REG_ZERO, A_GPR(gpr)); 1606 ptr_skip = ptr; 1607 for (z = 0; z < 4; z++) { /* front/rear/center-lfe/side */ 1608 int j, k, l, d; 1609 for (j = 0; j < 2; j++) { /* left/right */ 1610 k = bass_tmp + (z * 8) + (j * 4); 1611 l = treble_tmp + (z * 8) + (j * 4); 1612 d = playback + z * 2 + j; 1613 1614 A_OP(icode, &ptr, iMAC0, A_C_00000000, A_C_00000000, A_GPR(d), A_GPR(bass_gpr + 0 + j)); 1615 A_OP(icode, &ptr, iMACMV, A_GPR(k+1), A_GPR(k), A_GPR(k+1), A_GPR(bass_gpr + 4 + j)); 1616 A_OP(icode, &ptr, iMACMV, A_GPR(k), A_GPR(d), A_GPR(k), A_GPR(bass_gpr + 2 + j)); 1617 A_OP(icode, &ptr, iMACMV, A_GPR(k+3), A_GPR(k+2), A_GPR(k+3), A_GPR(bass_gpr + 8 + j)); 1618 A_OP(icode, &ptr, iMAC0, A_GPR(k+2), A_GPR_ACCU, A_GPR(k+2), A_GPR(bass_gpr + 6 + j)); 1619 A_OP(icode, &ptr, iACC3, A_GPR(k+2), A_GPR(k+2), A_GPR(k+2), A_C_00000000); 1620 1621 A_OP(icode, &ptr, iMAC0, A_C_00000000, A_C_00000000, A_GPR(k+2), A_GPR(treble_gpr + 0 + j)); 1622 A_OP(icode, &ptr, iMACMV, A_GPR(l+1), A_GPR(l), A_GPR(l+1), A_GPR(treble_gpr + 4 + j)); 1623 A_OP(icode, &ptr, iMACMV, A_GPR(l), A_GPR(k+2), A_GPR(l), A_GPR(treble_gpr + 2 + j)); 1624 A_OP(icode, &ptr, iMACMV, A_GPR(l+3), A_GPR(l+2), A_GPR(l+3), A_GPR(treble_gpr + 8 + j)); 1625 A_OP(icode, &ptr, iMAC0, A_GPR(l+2), A_GPR_ACCU, A_GPR(l+2), A_GPR(treble_gpr + 6 + j)); 1626 A_OP(icode, &ptr, iMACINT0, A_GPR(l+2), A_C_00000000, A_GPR(l+2), A_C_00000010); 1627 1628 A_OP(icode, &ptr, iACC3, A_GPR(d), A_GPR(l+2), A_C_00000000, A_C_00000000); 1629 1630 if (z == 2) /* center */ 1631 break; 1632 } 1633 } 1634 gpr_map[gpr++] = ptr - ptr_skip; 1635 1636 /* Master volume (will be renamed later) */ 1637 for (z = 0; z < 8; z++) 1638 A_OP(icode, &ptr, iMAC1, A_GPR(playback+z), A_C_00000000, A_GPR(gpr), A_GPR(playback+z)); 1639 snd_emu10k1_init_mono_control(&controls[nctl++], "Wave Master Playback Volume", gpr, 0); 1640 gpr++; 1641 1642 if (emu->card_capabilities->emu_model) { 1643 /* EMU1010 Outputs from PCM Front, Rear, Center, LFE, Side */ 1644 dev_info(emu->card->dev, "EMU outputs on\n"); 1645 for (z = 0; z < 8; z++) { 1646 if (emu->card_capabilities->ca0108_chip) { 1647 A_OP(icode, &ptr, iACC3, A3_EMU32OUT(z), A_GPR(playback + z), A_C_00000000, A_C_00000000); 1648 } else { 1649 A_OP(icode, &ptr, iACC3, A_EMU32OUTL(z), A_GPR(playback + z), A_C_00000000, A_C_00000000); 1650 } 1651 } 1652 } else { 1653 /* analog speakers */ 1654 A_PUT_STEREO_OUTPUT(A_EXTOUT_AFRONT_L, A_EXTOUT_AFRONT_R, playback); 1655 A_PUT_STEREO_OUTPUT(A_EXTOUT_AREAR_L, A_EXTOUT_AREAR_R, playback+2); 1656 A_PUT_OUTPUT(A_EXTOUT_ACENTER, playback+4); 1657 A_PUT_OUTPUT(A_EXTOUT_ALFE, playback+5); 1658 if (emu->card_capabilities->spk71) 1659 A_PUT_STEREO_OUTPUT(A_EXTOUT_ASIDE_L, A_EXTOUT_ASIDE_R, playback+6); 1660 1661 /* headphone */ 1662 A_PUT_STEREO_OUTPUT(A_EXTOUT_HEADPHONE_L, A_EXTOUT_HEADPHONE_R, playback); 1663 1664 /* IEC958 Optical Raw Playback Switch */ 1665 gpr_map[gpr++] = 0; 1666 gpr_map[gpr++] = 0x1008; 1667 gpr_map[gpr++] = 0xffff0000; 1668 for (z = 0; z < 2; z++) { 1669 A_OP(icode, &ptr, iMAC0, A_GPR(tmp + 2), A_FXBUS(FXBUS_PT_LEFT + z), A_C_00000000, A_C_00000000); 1670 A_OP(icode, &ptr, iSKIP, A_GPR_COND, A_GPR_COND, A_GPR(gpr - 2), A_C_00000001); 1671 A_OP(icode, &ptr, iACC3, A_GPR(tmp + 2), A_C_00000000, A_C_00010000, A_GPR(tmp + 2)); 1672 A_OP(icode, &ptr, iANDXOR, A_GPR(tmp + 2), A_GPR(tmp + 2), A_GPR(gpr - 1), A_C_00000000); 1673 A_SWITCH(icode, &ptr, tmp + 0, tmp + 2, gpr + z); 1674 A_SWITCH_NEG(icode, &ptr, tmp + 1, gpr + z); 1675 A_SWITCH(icode, &ptr, tmp + 1, playback + z, tmp + 1); 1676 if ((z==1) && (emu->card_capabilities->spdif_bug)) { 1677 /* Due to a SPDIF output bug on some Audigy cards, this code delays the Right channel by 1 sample */ 1678 dev_info(emu->card->dev, 1679 "Installing spdif_bug patch: %s\n", 1680 emu->card_capabilities->name); 1681 A_OP(icode, &ptr, iACC3, A_EXTOUT(A_EXTOUT_FRONT_L + z), A_GPR(gpr - 3), A_C_00000000, A_C_00000000); 1682 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 3), A_GPR(tmp + 0), A_GPR(tmp + 1), A_C_00000000); 1683 } else { 1684 A_OP(icode, &ptr, iACC3, A_EXTOUT(A_EXTOUT_FRONT_L + z), A_GPR(tmp + 0), A_GPR(tmp + 1), A_C_00000000); 1685 } 1686 } 1687 snd_emu10k1_init_stereo_onoff_control(controls + nctl++, SNDRV_CTL_NAME_IEC958("Optical Raw ",PLAYBACK,SWITCH), gpr, 0); 1688 gpr += 2; 1689 1690 A_PUT_STEREO_OUTPUT(A_EXTOUT_REAR_L, A_EXTOUT_REAR_R, playback+2); 1691 A_PUT_OUTPUT(A_EXTOUT_CENTER, playback+4); 1692 A_PUT_OUTPUT(A_EXTOUT_LFE, playback+5); 1693 } 1694 1695 /* ADC buffer */ 1696 #ifdef EMU10K1_CAPTURE_DIGITAL_OUT 1697 A_PUT_STEREO_OUTPUT(A_EXTOUT_ADC_CAP_L, A_EXTOUT_ADC_CAP_R, playback); 1698 #else 1699 A_PUT_OUTPUT(A_EXTOUT_ADC_CAP_L, capture); 1700 A_PUT_OUTPUT(A_EXTOUT_ADC_CAP_R, capture+1); 1701 #endif 1702 1703 if (emu->card_capabilities->emu_model) { 1704 /* Capture 16 channels of S32_LE sound. */ 1705 if (emu->card_capabilities->ca0108_chip) { 1706 dev_info(emu->card->dev, "EMU2 inputs on\n"); 1707 /* Note that the Tina[2] DSPs have 16 more EMU32 inputs which we don't use. */ 1708 1709 snd_emu10k1_audigy_dsp_convert_32_to_2x16( 1710 icode, &ptr, tmp, bit_shifter16, A3_EMU32IN(0), A_FXBUS2(0)); 1711 // A3_EMU32IN(0) is delayed by one sample, so all other A3_EMU32IN channels 1712 // need to be delayed as well; we use an auxiliary register for that. 1713 for (z = 1; z < 0x10; z++) { 1714 snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, 1715 bit_shifter16, 1716 A_GPR(gpr), 1717 A_FXBUS2(z*2) ); 1718 A_OP(icode, &ptr, iACC3, A_GPR(gpr), A3_EMU32IN(z), A_C_00000000, A_C_00000000); 1719 gpr_map[gpr++] = 0x00000000; 1720 } 1721 } else { 1722 dev_info(emu->card->dev, "EMU inputs on\n"); 1723 /* Note that the Alice2 DSPs have 6 I2S inputs which we don't use. */ 1724 1725 /* 1726 dev_dbg(emu->card->dev, "emufx.c: gpr=0x%x, tmp=0x%x\n", 1727 gpr, tmp); 1728 */ 1729 snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_P16VIN(0x0), A_FXBUS2(0) ); 1730 /* A_P16VIN(0) is delayed by one sample, so all other A_P16VIN channels 1731 * will need to also be delayed; we use an auxiliary register for that. */ 1732 for (z = 1; z < 0x10; z++) { 1733 snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr), A_FXBUS2(z * 2) ); 1734 A_OP(icode, &ptr, iACC3, A_GPR(gpr), A_P16VIN(z), A_C_00000000, A_C_00000000); 1735 gpr_map[gpr++] = 0x00000000; 1736 } 1737 } 1738 1739 #if 0 1740 for (z = 4; z < 8; z++) { 1741 A_OP(icode, &ptr, iACC3, A_FXBUS2(z), A_C_00000000, A_C_00000000, A_C_00000000); 1742 } 1743 for (z = 0xc; z < 0x10; z++) { 1744 A_OP(icode, &ptr, iACC3, A_FXBUS2(z), A_C_00000000, A_C_00000000, A_C_00000000); 1745 } 1746 #endif 1747 } else { 1748 /* EFX capture - capture the 16 EXTINs */ 1749 /* Capture 16 channels of S16_LE sound */ 1750 for (z = 0; z < 16; z++) { 1751 A_OP(icode, &ptr, iACC3, A_FXBUS2(z), A_C_00000000, A_C_00000000, A_EXTIN(z)); 1752 } 1753 } 1754 1755 #endif /* JCD test */ 1756 /* 1757 * ok, set up done.. 1758 */ 1759 1760 if (gpr > 512) { 1761 snd_BUG(); 1762 err = -EIO; 1763 goto __err; 1764 } 1765 1766 /* clear remaining instruction memory */ 1767 while (ptr < 0x400) 1768 A_OP(icode, &ptr, 0x0f, 0xc0, 0xc0, 0xcf, 0xc0); 1769 1770 icode->gpr_add_control_count = nctl; 1771 icode->gpr_add_controls = controls; 1772 emu->support_tlv = 1; /* support TLV */ 1773 err = snd_emu10k1_icode_poke(emu, icode, true); 1774 emu->support_tlv = 0; /* clear again */ 1775 1776 __err: 1777 kfree(controls); 1778 __err_ctrls: 1779 kfree(icode->gpr_map); 1780 __err_gpr: 1781 kfree(icode); 1782 return err; 1783 } 1784 1785 1786 /* 1787 * initial DSP configuration for Emu10k1 1788 */ 1789 1790 /* Volumes are in the [-2^31, 0] range, zero being mute. */ 1791 static void _volume(struct snd_emu10k1_fx8010_code *icode, u32 *ptr, u32 dst, u32 src, u32 vol) 1792 { 1793 OP(icode, ptr, iMAC1, dst, C_00000000, src, vol); 1794 } 1795 static void _volume_add(struct snd_emu10k1_fx8010_code *icode, u32 *ptr, u32 dst, u32 src, u32 vol) 1796 { 1797 OP(icode, ptr, iMAC1, dst, dst, src, vol); 1798 } 1799 1800 #define VOLUME(icode, ptr, dst, src, vol) \ 1801 _volume(icode, ptr, GPR(dst), GPR(src), GPR(vol)) 1802 #define VOLUME_IN(icode, ptr, dst, src, vol) \ 1803 _volume(icode, ptr, GPR(dst), EXTIN(src), GPR(vol)) 1804 #define VOLUME_ADD(icode, ptr, dst, src, vol) \ 1805 _volume_add(icode, ptr, GPR(dst), GPR(src), GPR(vol)) 1806 #define VOLUME_ADDIN(icode, ptr, dst, src, vol) \ 1807 _volume_add(icode, ptr, GPR(dst), EXTIN(src), GPR(vol)) 1808 #define VOLUME_OUT(icode, ptr, dst, src, vol) \ 1809 _volume(icode, ptr, EXTOUT(dst), GPR(src), GPR(vol)) 1810 #define _SWITCH(icode, ptr, dst, src, sw) \ 1811 OP((icode), ptr, iMACINT0, dst, C_00000000, src, sw); 1812 #define SWITCH(icode, ptr, dst, src, sw) \ 1813 _SWITCH(icode, ptr, GPR(dst), GPR(src), GPR(sw)) 1814 #define SWITCH_IN(icode, ptr, dst, src, sw) \ 1815 _SWITCH(icode, ptr, GPR(dst), EXTIN(src), GPR(sw)) 1816 #define _SWITCH_NEG(icode, ptr, dst, src) \ 1817 OP((icode), ptr, iANDXOR, dst, src, C_00000001, C_00000001); 1818 #define SWITCH_NEG(icode, ptr, dst, src) \ 1819 _SWITCH_NEG(icode, ptr, GPR(dst), GPR(src)) 1820 1821 1822 static int _snd_emu10k1_init_efx(struct snd_emu10k1 *emu) 1823 { 1824 int err, i, z, gpr, tmp, playback, capture; 1825 u32 ptr, ptr_skip; 1826 struct snd_emu10k1_fx8010_code *icode; 1827 struct snd_emu10k1_fx8010_pcm_rec *ipcm = NULL; 1828 struct snd_emu10k1_fx8010_control_gpr *controls = NULL, *ctl; 1829 u32 *gpr_map; 1830 1831 err = -ENOMEM; 1832 icode = kzalloc(sizeof(*icode), GFP_KERNEL); 1833 if (!icode) 1834 return err; 1835 1836 icode->gpr_map = kcalloc(256 + 160 + 160 + 2 * 512, 1837 sizeof(u_int32_t), GFP_KERNEL); 1838 if (!icode->gpr_map) 1839 goto __err_gpr; 1840 1841 controls = kcalloc(SND_EMU10K1_GPR_CONTROLS, 1842 sizeof(struct snd_emu10k1_fx8010_control_gpr), 1843 GFP_KERNEL); 1844 if (!controls) 1845 goto __err_ctrls; 1846 1847 ipcm = kzalloc(sizeof(*ipcm), GFP_KERNEL); 1848 if (!ipcm) 1849 goto __err_ipcm; 1850 1851 gpr_map = icode->gpr_map; 1852 1853 icode->tram_data_map = icode->gpr_map + 256; 1854 icode->tram_addr_map = icode->tram_data_map + 160; 1855 icode->code = icode->tram_addr_map + 160; 1856 1857 /* clear free GPRs */ 1858 memset(icode->gpr_valid, 0xff, 256 / 8); 1859 1860 /* clear TRAM data & address lines */ 1861 memset(icode->tram_valid, 0xff, 160 / 8); 1862 1863 strcpy(icode->name, "SB Live! FX8010 code for ALSA v1.2 by Jaroslav Kysela"); 1864 ptr = 0; i = 0; 1865 /* we have 12 inputs */ 1866 playback = SND_EMU10K1_INPUTS; 1867 /* we have 6 playback channels and tone control doubles */ 1868 capture = playback + SND_EMU10K1_PLAYBACK_CHANNELS; 1869 gpr = capture + SND_EMU10K1_CAPTURE_CHANNELS; 1870 tmp = 0x88; /* we need 4 temporary GPR */ 1871 /* from 0x8c to 0xff is the area for tone control */ 1872 1873 /* 1874 * Process FX Buses 1875 */ 1876 OP(icode, &ptr, iMACINT0, GPR(0), C_00000000, FXBUS(FXBUS_PCM_LEFT), C_00000008); 1877 OP(icode, &ptr, iMACINT0, GPR(1), C_00000000, FXBUS(FXBUS_PCM_RIGHT), C_00000008); 1878 OP(icode, &ptr, iMACINT0, GPR(2), C_00000000, FXBUS(FXBUS_MIDI_LEFT), C_00000008); 1879 OP(icode, &ptr, iMACINT0, GPR(3), C_00000000, FXBUS(FXBUS_MIDI_RIGHT), C_00000008); 1880 OP(icode, &ptr, iMACINT0, GPR(4), C_00000000, FXBUS(FXBUS_PCM_LEFT_REAR), C_00000008); 1881 OP(icode, &ptr, iMACINT0, GPR(5), C_00000000, FXBUS(FXBUS_PCM_RIGHT_REAR), C_00000008); 1882 OP(icode, &ptr, iMACINT0, GPR(6), C_00000000, FXBUS(FXBUS_PCM_CENTER), C_00000008); 1883 OP(icode, &ptr, iMACINT0, GPR(7), C_00000000, FXBUS(FXBUS_PCM_LFE), C_00000008); 1884 OP(icode, &ptr, iMACINT0, GPR(8), C_00000000, C_00000000, C_00000000); /* S/PDIF left */ 1885 OP(icode, &ptr, iMACINT0, GPR(9), C_00000000, C_00000000, C_00000000); /* S/PDIF right */ 1886 OP(icode, &ptr, iMACINT0, GPR(10), C_00000000, FXBUS(FXBUS_PCM_LEFT_FRONT), C_00000008); 1887 OP(icode, &ptr, iMACINT0, GPR(11), C_00000000, FXBUS(FXBUS_PCM_RIGHT_FRONT), C_00000008); 1888 1889 /* Raw S/PDIF PCM */ 1890 ipcm->substream = 0; 1891 ipcm->channels = 2; 1892 ipcm->tram_start = 0; 1893 ipcm->buffer_size = (64 * 1024) / 2; 1894 ipcm->gpr_size = gpr++; 1895 ipcm->gpr_ptr = gpr++; 1896 ipcm->gpr_count = gpr++; 1897 ipcm->gpr_tmpcount = gpr++; 1898 ipcm->gpr_trigger = gpr++; 1899 ipcm->gpr_running = gpr++; 1900 ipcm->etram[0] = 0; 1901 ipcm->etram[1] = 1; 1902 1903 gpr_map[gpr + 0] = 0xfffff000; 1904 gpr_map[gpr + 1] = 0xffff0000; 1905 gpr_map[gpr + 2] = 0x70000000; 1906 gpr_map[gpr + 3] = 0x00000007; 1907 gpr_map[gpr + 4] = 0x001f << 11; 1908 gpr_map[gpr + 5] = 0x001c << 11; 1909 gpr_map[gpr + 6] = (0x22 - 0x01) - 1; /* skip at 01 to 22 */ 1910 gpr_map[gpr + 7] = (0x22 - 0x06) - 1; /* skip at 06 to 22 */ 1911 gpr_map[gpr + 8] = 0x2000000 + (2<<11); 1912 gpr_map[gpr + 9] = 0x4000000 + (2<<11); 1913 gpr_map[gpr + 10] = 1<<11; 1914 gpr_map[gpr + 11] = (0x24 - 0x0a) - 1; /* skip at 0a to 24 */ 1915 gpr_map[gpr + 12] = 0; 1916 1917 /* if the trigger flag is not set, skip */ 1918 /* 00: */ OP(icode, &ptr, iMAC0, C_00000000, GPR(ipcm->gpr_trigger), C_00000000, C_00000000); 1919 /* 01: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_ZERO, GPR(gpr + 6)); 1920 /* if the running flag is set, we're running */ 1921 /* 02: */ OP(icode, &ptr, iMAC0, C_00000000, GPR(ipcm->gpr_running), C_00000000, C_00000000); 1922 /* 03: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, C_00000004); 1923 /* wait until ((GPR_DBAC>>11) & 0x1f) == 0x1c) */ 1924 /* 04: */ OP(icode, &ptr, iANDXOR, GPR(tmp + 0), GPR_DBAC, GPR(gpr + 4), C_00000000); 1925 /* 05: */ OP(icode, &ptr, iMACINT0, C_00000000, GPR(tmp + 0), C_ffffffff, GPR(gpr + 5)); 1926 /* 06: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, GPR(gpr + 7)); 1927 /* 07: */ OP(icode, &ptr, iACC3, GPR(gpr + 12), C_00000010, C_00000001, C_00000000); 1928 1929 /* 08: */ OP(icode, &ptr, iANDXOR, GPR(ipcm->gpr_running), GPR(ipcm->gpr_running), C_00000000, C_00000001); 1930 /* 09: */ OP(icode, &ptr, iACC3, GPR(gpr + 12), GPR(gpr + 12), C_ffffffff, C_00000000); 1931 /* 0a: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, GPR(gpr + 11)); 1932 /* 0b: */ OP(icode, &ptr, iACC3, GPR(gpr + 12), C_00000001, C_00000000, C_00000000); 1933 1934 /* 0c: */ OP(icode, &ptr, iANDXOR, GPR(tmp + 0), ETRAM_DATA(ipcm->etram[0]), GPR(gpr + 0), C_00000000); 1935 /* 0d: */ OP(icode, &ptr, iLOG, GPR(tmp + 0), GPR(tmp + 0), GPR(gpr + 3), C_00000000); 1936 /* 0e: */ OP(icode, &ptr, iANDXOR, GPR(8), GPR(tmp + 0), GPR(gpr + 1), GPR(gpr + 2)); 1937 /* 0f: */ OP(icode, &ptr, iSKIP, C_00000000, GPR_COND, CC_REG_MINUS, C_00000001); 1938 /* 10: */ OP(icode, &ptr, iANDXOR, GPR(8), GPR(8), GPR(gpr + 1), GPR(gpr + 2)); 1939 1940 /* 11: */ OP(icode, &ptr, iANDXOR, GPR(tmp + 0), ETRAM_DATA(ipcm->etram[1]), GPR(gpr + 0), C_00000000); 1941 /* 12: */ OP(icode, &ptr, iLOG, GPR(tmp + 0), GPR(tmp + 0), GPR(gpr + 3), C_00000000); 1942 /* 13: */ OP(icode, &ptr, iANDXOR, GPR(9), GPR(tmp + 0), GPR(gpr + 1), GPR(gpr + 2)); 1943 /* 14: */ OP(icode, &ptr, iSKIP, C_00000000, GPR_COND, CC_REG_MINUS, C_00000001); 1944 /* 15: */ OP(icode, &ptr, iANDXOR, GPR(9), GPR(9), GPR(gpr + 1), GPR(gpr + 2)); 1945 1946 /* 16: */ OP(icode, &ptr, iACC3, GPR(tmp + 0), GPR(ipcm->gpr_ptr), C_00000001, C_00000000); 1947 /* 17: */ OP(icode, &ptr, iMACINT0, C_00000000, GPR(tmp + 0), C_ffffffff, GPR(ipcm->gpr_size)); 1948 /* 18: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_MINUS, C_00000001); 1949 /* 19: */ OP(icode, &ptr, iACC3, GPR(tmp + 0), C_00000000, C_00000000, C_00000000); 1950 /* 1a: */ OP(icode, &ptr, iACC3, GPR(ipcm->gpr_ptr), GPR(tmp + 0), C_00000000, C_00000000); 1951 1952 /* 1b: */ OP(icode, &ptr, iACC3, GPR(ipcm->gpr_tmpcount), GPR(ipcm->gpr_tmpcount), C_ffffffff, C_00000000); 1953 /* 1c: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, C_00000002); 1954 /* 1d: */ OP(icode, &ptr, iACC3, GPR(ipcm->gpr_tmpcount), GPR(ipcm->gpr_count), C_00000000, C_00000000); 1955 /* 1e: */ OP(icode, &ptr, iACC3, GPR_IRQ, C_80000000, C_00000000, C_00000000); 1956 /* 1f: */ OP(icode, &ptr, iANDXOR, GPR(ipcm->gpr_running), GPR(ipcm->gpr_running), C_00000001, C_00010000); 1957 1958 /* 20: */ OP(icode, &ptr, iANDXOR, GPR(ipcm->gpr_running), GPR(ipcm->gpr_running), C_00010000, C_00000001); 1959 /* 21: */ OP(icode, &ptr, iSKIP, C_00000000, C_7fffffff, C_7fffffff, C_00000002); 1960 1961 /* 22: */ OP(icode, &ptr, iMACINT1, ETRAM_ADDR(ipcm->etram[0]), GPR(gpr + 8), GPR_DBAC, C_ffffffff); 1962 /* 23: */ OP(icode, &ptr, iMACINT1, ETRAM_ADDR(ipcm->etram[1]), GPR(gpr + 9), GPR_DBAC, C_ffffffff); 1963 1964 /* 24: */ 1965 gpr += 13; 1966 1967 /* Wave Playback Volume */ 1968 for (z = 0; z < 2; z++) 1969 VOLUME(icode, &ptr, playback + z, z, gpr + z); 1970 snd_emu10k1_init_stereo_control(controls + i++, "Wave Playback Volume", gpr, 100); 1971 gpr += 2; 1972 1973 /* Wave Surround Playback Volume */ 1974 for (z = 0; z < 2; z++) 1975 VOLUME(icode, &ptr, playback + 2 + z, z, gpr + z); 1976 snd_emu10k1_init_stereo_control(controls + i++, "Wave Surround Playback Volume", gpr, 0); 1977 gpr += 2; 1978 1979 /* Wave Center/LFE Playback Volume */ 1980 OP(icode, &ptr, iACC3, GPR(tmp + 0), FXBUS(FXBUS_PCM_LEFT), FXBUS(FXBUS_PCM_RIGHT), C_00000000); 1981 OP(icode, &ptr, iMACINT0, GPR(tmp + 0), C_00000000, GPR(tmp + 0), C_00000004); 1982 VOLUME(icode, &ptr, playback + 4, tmp + 0, gpr); 1983 snd_emu10k1_init_mono_control(controls + i++, "Wave Center Playback Volume", gpr++, 0); 1984 VOLUME(icode, &ptr, playback + 5, tmp + 0, gpr); 1985 snd_emu10k1_init_mono_control(controls + i++, "Wave LFE Playback Volume", gpr++, 0); 1986 1987 /* Wave Capture Volume + Switch */ 1988 for (z = 0; z < 2; z++) { 1989 SWITCH(icode, &ptr, tmp + 0, z, gpr + 2 + z); 1990 VOLUME(icode, &ptr, capture + z, tmp + 0, gpr + z); 1991 } 1992 snd_emu10k1_init_stereo_control(controls + i++, "Wave Capture Volume", gpr, 0); 1993 snd_emu10k1_init_stereo_onoff_control(controls + i++, "Wave Capture Switch", gpr + 2, 0); 1994 gpr += 4; 1995 1996 /* Synth Playback Volume */ 1997 for (z = 0; z < 2; z++) 1998 VOLUME_ADD(icode, &ptr, playback + z, 2 + z, gpr + z); 1999 snd_emu10k1_init_stereo_control(controls + i++, "Synth Playback Volume", gpr, 100); 2000 gpr += 2; 2001 2002 /* Synth Capture Volume + Switch */ 2003 for (z = 0; z < 2; z++) { 2004 SWITCH(icode, &ptr, tmp + 0, 2 + z, gpr + 2 + z); 2005 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z); 2006 } 2007 snd_emu10k1_init_stereo_control(controls + i++, "Synth Capture Volume", gpr, 0); 2008 snd_emu10k1_init_stereo_onoff_control(controls + i++, "Synth Capture Switch", gpr + 2, 0); 2009 gpr += 4; 2010 2011 /* Surround Digital Playback Volume (renamed later without Digital) */ 2012 for (z = 0; z < 2; z++) 2013 VOLUME_ADD(icode, &ptr, playback + 2 + z, 4 + z, gpr + z); 2014 snd_emu10k1_init_stereo_control(controls + i++, "Surround Digital Playback Volume", gpr, 100); 2015 gpr += 2; 2016 2017 /* Surround Capture Volume + Switch */ 2018 for (z = 0; z < 2; z++) { 2019 SWITCH(icode, &ptr, tmp + 0, 4 + z, gpr + 2 + z); 2020 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z); 2021 } 2022 snd_emu10k1_init_stereo_control(controls + i++, "Surround Capture Volume", gpr, 0); 2023 snd_emu10k1_init_stereo_onoff_control(controls + i++, "Surround Capture Switch", gpr + 2, 0); 2024 gpr += 4; 2025 2026 /* Center Playback Volume (renamed later without Digital) */ 2027 VOLUME_ADD(icode, &ptr, playback + 4, 6, gpr); 2028 snd_emu10k1_init_mono_control(controls + i++, "Center Digital Playback Volume", gpr++, 100); 2029 2030 /* LFE Playback Volume + Switch (renamed later without Digital) */ 2031 VOLUME_ADD(icode, &ptr, playback + 5, 7, gpr); 2032 snd_emu10k1_init_mono_control(controls + i++, "LFE Digital Playback Volume", gpr++, 100); 2033 2034 /* Front Playback Volume */ 2035 for (z = 0; z < 2; z++) 2036 VOLUME_ADD(icode, &ptr, playback + z, 10 + z, gpr + z); 2037 snd_emu10k1_init_stereo_control(controls + i++, "Front Playback Volume", gpr, 100); 2038 gpr += 2; 2039 2040 /* Front Capture Volume + Switch */ 2041 for (z = 0; z < 2; z++) { 2042 SWITCH(icode, &ptr, tmp + 0, 10 + z, gpr + 2); 2043 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z); 2044 } 2045 snd_emu10k1_init_stereo_control(controls + i++, "Front Capture Volume", gpr, 0); 2046 snd_emu10k1_init_mono_onoff_control(controls + i++, "Front Capture Switch", gpr + 2, 0); 2047 gpr += 3; 2048 2049 /* 2050 * Process inputs 2051 */ 2052 2053 if (emu->fx8010.extin_mask & ((1<<EXTIN_AC97_L)|(1<<EXTIN_AC97_R))) { 2054 /* AC'97 Playback Volume */ 2055 VOLUME_ADDIN(icode, &ptr, playback + 0, EXTIN_AC97_L, gpr); gpr++; 2056 VOLUME_ADDIN(icode, &ptr, playback + 1, EXTIN_AC97_R, gpr); gpr++; 2057 snd_emu10k1_init_stereo_control(controls + i++, "AC97 Playback Volume", gpr-2, 0); 2058 /* AC'97 Capture Volume */ 2059 VOLUME_ADDIN(icode, &ptr, capture + 0, EXTIN_AC97_L, gpr); gpr++; 2060 VOLUME_ADDIN(icode, &ptr, capture + 1, EXTIN_AC97_R, gpr); gpr++; 2061 snd_emu10k1_init_stereo_control(controls + i++, "AC97 Capture Volume", gpr-2, 100); 2062 } 2063 2064 if (emu->fx8010.extin_mask & ((1<<EXTIN_SPDIF_CD_L)|(1<<EXTIN_SPDIF_CD_R))) { 2065 /* IEC958 TTL Playback Volume */ 2066 for (z = 0; z < 2; z++) 2067 VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_SPDIF_CD_L + z, gpr + z); 2068 snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("TTL ",PLAYBACK,VOLUME), gpr, 0); 2069 gpr += 2; 2070 2071 /* IEC958 TTL Capture Volume + Switch */ 2072 for (z = 0; z < 2; z++) { 2073 SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_SPDIF_CD_L + z, gpr + 2 + z); 2074 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z); 2075 } 2076 snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("TTL ",CAPTURE,VOLUME), gpr, 0); 2077 snd_emu10k1_init_stereo_onoff_control(controls + i++, SNDRV_CTL_NAME_IEC958("TTL ",CAPTURE,SWITCH), gpr + 2, 0); 2078 gpr += 4; 2079 } 2080 2081 if (emu->fx8010.extin_mask & ((1<<EXTIN_ZOOM_L)|(1<<EXTIN_ZOOM_R))) { 2082 /* Zoom Video Playback Volume */ 2083 for (z = 0; z < 2; z++) 2084 VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_ZOOM_L + z, gpr + z); 2085 snd_emu10k1_init_stereo_control(controls + i++, "Zoom Video Playback Volume", gpr, 0); 2086 gpr += 2; 2087 2088 /* Zoom Video Capture Volume + Switch */ 2089 for (z = 0; z < 2; z++) { 2090 SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_ZOOM_L + z, gpr + 2 + z); 2091 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z); 2092 } 2093 snd_emu10k1_init_stereo_control(controls + i++, "Zoom Video Capture Volume", gpr, 0); 2094 snd_emu10k1_init_stereo_onoff_control(controls + i++, "Zoom Video Capture Switch", gpr + 2, 0); 2095 gpr += 4; 2096 } 2097 2098 if (emu->fx8010.extin_mask & ((1<<EXTIN_TOSLINK_L)|(1<<EXTIN_TOSLINK_R))) { 2099 /* IEC958 Optical Playback Volume */ 2100 for (z = 0; z < 2; z++) 2101 VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_TOSLINK_L + z, gpr + z); 2102 snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("LiveDrive ",PLAYBACK,VOLUME), gpr, 0); 2103 gpr += 2; 2104 2105 /* IEC958 Optical Capture Volume */ 2106 for (z = 0; z < 2; z++) { 2107 SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_TOSLINK_L + z, gpr + 2 + z); 2108 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z); 2109 } 2110 snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("LiveDrive ",CAPTURE,VOLUME), gpr, 0); 2111 snd_emu10k1_init_stereo_onoff_control(controls + i++, SNDRV_CTL_NAME_IEC958("LiveDrive ",CAPTURE,SWITCH), gpr + 2, 0); 2112 gpr += 4; 2113 } 2114 2115 if (emu->fx8010.extin_mask & ((1<<EXTIN_LINE1_L)|(1<<EXTIN_LINE1_R))) { 2116 /* Line LiveDrive Playback Volume */ 2117 for (z = 0; z < 2; z++) 2118 VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_LINE1_L + z, gpr + z); 2119 snd_emu10k1_init_stereo_control(controls + i++, "Line LiveDrive Playback Volume", gpr, 0); 2120 gpr += 2; 2121 2122 /* Line LiveDrive Capture Volume + Switch */ 2123 for (z = 0; z < 2; z++) { 2124 SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_LINE1_L + z, gpr + 2 + z); 2125 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z); 2126 } 2127 snd_emu10k1_init_stereo_control(controls + i++, "Line LiveDrive Capture Volume", gpr, 0); 2128 snd_emu10k1_init_stereo_onoff_control(controls + i++, "Line LiveDrive Capture Switch", gpr + 2, 0); 2129 gpr += 4; 2130 } 2131 2132 if (emu->fx8010.extin_mask & ((1<<EXTIN_COAX_SPDIF_L)|(1<<EXTIN_COAX_SPDIF_R))) { 2133 /* IEC958 Coax Playback Volume */ 2134 for (z = 0; z < 2; z++) 2135 VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_COAX_SPDIF_L + z, gpr + z); 2136 snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("Coaxial ",PLAYBACK,VOLUME), gpr, 0); 2137 gpr += 2; 2138 2139 /* IEC958 Coax Capture Volume + Switch */ 2140 for (z = 0; z < 2; z++) { 2141 SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_COAX_SPDIF_L + z, gpr + 2 + z); 2142 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z); 2143 } 2144 snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("Coaxial ",CAPTURE,VOLUME), gpr, 0); 2145 snd_emu10k1_init_stereo_onoff_control(controls + i++, SNDRV_CTL_NAME_IEC958("Coaxial ",CAPTURE,SWITCH), gpr + 2, 0); 2146 gpr += 4; 2147 } 2148 2149 if (emu->fx8010.extin_mask & ((1<<EXTIN_LINE2_L)|(1<<EXTIN_LINE2_R))) { 2150 /* Line LiveDrive Playback Volume */ 2151 for (z = 0; z < 2; z++) 2152 VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_LINE2_L + z, gpr + z); 2153 snd_emu10k1_init_stereo_control(controls + i++, "Line2 LiveDrive Playback Volume", gpr, 0); 2154 controls[i-1].id.index = 1; 2155 gpr += 2; 2156 2157 /* Line LiveDrive Capture Volume */ 2158 for (z = 0; z < 2; z++) { 2159 SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_LINE2_L + z, gpr + 2 + z); 2160 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z); 2161 } 2162 snd_emu10k1_init_stereo_control(controls + i++, "Line2 LiveDrive Capture Volume", gpr, 0); 2163 controls[i-1].id.index = 1; 2164 snd_emu10k1_init_stereo_onoff_control(controls + i++, "Line2 LiveDrive Capture Switch", gpr + 2, 0); 2165 controls[i-1].id.index = 1; 2166 gpr += 4; 2167 } 2168 2169 /* 2170 * Process tone control 2171 */ 2172 ctl = &controls[i + 0]; 2173 ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER; 2174 strcpy(ctl->id.name, "Tone Control - Bass"); 2175 ctl->vcount = 2; 2176 ctl->count = 10; 2177 ctl->min = 0; 2178 ctl->max = 40; 2179 ctl->value[0] = ctl->value[1] = 20; 2180 ctl->tlv = snd_emu10k1_bass_treble_db_scale; 2181 ctl->translation = EMU10K1_GPR_TRANSLATION_BASS; 2182 ctl = &controls[i + 1]; 2183 ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER; 2184 strcpy(ctl->id.name, "Tone Control - Treble"); 2185 ctl->vcount = 2; 2186 ctl->count = 10; 2187 ctl->min = 0; 2188 ctl->max = 40; 2189 ctl->value[0] = ctl->value[1] = 20; 2190 ctl->tlv = snd_emu10k1_bass_treble_db_scale; 2191 ctl->translation = EMU10K1_GPR_TRANSLATION_TREBLE; 2192 2193 #define BASS_GPR 0x8c 2194 #define TREBLE_GPR 0x96 2195 2196 for (z = 0; z < 5; z++) { 2197 int j; 2198 for (j = 0; j < 2; j++) { 2199 controls[i + 0].gpr[z * 2 + j] = BASS_GPR + z * 2 + j; 2200 controls[i + 1].gpr[z * 2 + j] = TREBLE_GPR + z * 2 + j; 2201 } 2202 } 2203 i += 2; 2204 2205 OP(icode, &ptr, iACC3, C_00000000, GPR(gpr), C_00000000, C_00000000); 2206 snd_emu10k1_init_mono_onoff_control(controls + i++, "Tone Control - Switch", gpr, 0); 2207 gpr++; 2208 OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_ZERO, GPR(gpr)); 2209 ptr_skip = ptr; 2210 for (z = 0; z < 3; z++) { /* front/rear/center-lfe */ 2211 int j, k, l, d; 2212 for (j = 0; j < 2; j++) { /* left/right */ 2213 k = 0xa0 + (z * 8) + (j * 4); 2214 l = 0xd0 + (z * 8) + (j * 4); 2215 d = playback + z * 2 + j; 2216 2217 OP(icode, &ptr, iMAC0, C_00000000, C_00000000, GPR(d), GPR(BASS_GPR + 0 + j)); 2218 OP(icode, &ptr, iMACMV, GPR(k+1), GPR(k), GPR(k+1), GPR(BASS_GPR + 4 + j)); 2219 OP(icode, &ptr, iMACMV, GPR(k), GPR(d), GPR(k), GPR(BASS_GPR + 2 + j)); 2220 OP(icode, &ptr, iMACMV, GPR(k+3), GPR(k+2), GPR(k+3), GPR(BASS_GPR + 8 + j)); 2221 OP(icode, &ptr, iMAC0, GPR(k+2), GPR_ACCU, GPR(k+2), GPR(BASS_GPR + 6 + j)); 2222 OP(icode, &ptr, iACC3, GPR(k+2), GPR(k+2), GPR(k+2), C_00000000); 2223 2224 OP(icode, &ptr, iMAC0, C_00000000, C_00000000, GPR(k+2), GPR(TREBLE_GPR + 0 + j)); 2225 OP(icode, &ptr, iMACMV, GPR(l+1), GPR(l), GPR(l+1), GPR(TREBLE_GPR + 4 + j)); 2226 OP(icode, &ptr, iMACMV, GPR(l), GPR(k+2), GPR(l), GPR(TREBLE_GPR + 2 + j)); 2227 OP(icode, &ptr, iMACMV, GPR(l+3), GPR(l+2), GPR(l+3), GPR(TREBLE_GPR + 8 + j)); 2228 OP(icode, &ptr, iMAC0, GPR(l+2), GPR_ACCU, GPR(l+2), GPR(TREBLE_GPR + 6 + j)); 2229 OP(icode, &ptr, iMACINT0, GPR(l+2), C_00000000, GPR(l+2), C_00000010); 2230 2231 OP(icode, &ptr, iACC3, GPR(d), GPR(l+2), C_00000000, C_00000000); 2232 2233 if (z == 2) /* center */ 2234 break; 2235 } 2236 } 2237 gpr_map[gpr++] = ptr - ptr_skip; 2238 2239 #undef BASS_GPR 2240 #undef TREBLE_GPR 2241 2242 /* 2243 * Process outputs 2244 */ 2245 if (emu->fx8010.extout_mask & ((1<<EXTOUT_AC97_L)|(1<<EXTOUT_AC97_R))) { 2246 /* AC'97 Playback Volume */ 2247 2248 for (z = 0; z < 2; z++) 2249 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_L + z), GPR(playback + z), C_00000000, C_00000000); 2250 } 2251 2252 if (emu->fx8010.extout_mask & ((1<<EXTOUT_TOSLINK_L)|(1<<EXTOUT_TOSLINK_R))) { 2253 /* IEC958 Optical Raw Playback Switch */ 2254 2255 for (z = 0; z < 2; z++) { 2256 SWITCH(icode, &ptr, tmp + 0, 8 + z, gpr + z); 2257 SWITCH_NEG(icode, &ptr, tmp + 1, gpr + z); 2258 SWITCH(icode, &ptr, tmp + 1, playback + z, tmp + 1); 2259 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_TOSLINK_L + z), GPR(tmp + 0), GPR(tmp + 1), C_00000000); 2260 #ifdef EMU10K1_CAPTURE_DIGITAL_OUT 2261 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ADC_CAP_L + z), GPR(tmp + 0), GPR(tmp + 1), C_00000000); 2262 #endif 2263 } 2264 2265 snd_emu10k1_init_stereo_onoff_control(controls + i++, SNDRV_CTL_NAME_IEC958("Optical Raw ",PLAYBACK,SWITCH), gpr, 0); 2266 gpr += 2; 2267 } 2268 2269 if (emu->fx8010.extout_mask & ((1<<EXTOUT_HEADPHONE_L)|(1<<EXTOUT_HEADPHONE_R))) { 2270 /* Headphone Playback Volume */ 2271 2272 for (z = 0; z < 2; z++) { 2273 SWITCH(icode, &ptr, tmp + 0, playback + 4 + z, gpr + 2 + z); 2274 SWITCH_NEG(icode, &ptr, tmp + 1, gpr + 2 + z); 2275 SWITCH(icode, &ptr, tmp + 1, playback + z, tmp + 1); 2276 OP(icode, &ptr, iACC3, GPR(tmp + 0), GPR(tmp + 0), GPR(tmp + 1), C_00000000); 2277 VOLUME_OUT(icode, &ptr, EXTOUT_HEADPHONE_L + z, tmp + 0, gpr + z); 2278 } 2279 2280 snd_emu10k1_init_stereo_control(controls + i++, "Headphone Playback Volume", gpr + 0, 0); 2281 controls[i-1].id.index = 1; /* AC'97 can have also Headphone control */ 2282 snd_emu10k1_init_mono_onoff_control(controls + i++, "Headphone Center Playback Switch", gpr + 2, 0); 2283 controls[i-1].id.index = 1; 2284 snd_emu10k1_init_mono_onoff_control(controls + i++, "Headphone LFE Playback Switch", gpr + 3, 0); 2285 controls[i-1].id.index = 1; 2286 2287 gpr += 4; 2288 } 2289 2290 if (emu->fx8010.extout_mask & ((1<<EXTOUT_REAR_L)|(1<<EXTOUT_REAR_R))) 2291 for (z = 0; z < 2; z++) 2292 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_REAR_L + z), GPR(playback + 2 + z), C_00000000, C_00000000); 2293 2294 if (emu->fx8010.extout_mask & ((1<<EXTOUT_AC97_REAR_L)|(1<<EXTOUT_AC97_REAR_R))) 2295 for (z = 0; z < 2; z++) 2296 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_REAR_L + z), GPR(playback + 2 + z), C_00000000, C_00000000); 2297 2298 if (emu->fx8010.extout_mask & (1<<EXTOUT_AC97_CENTER)) { 2299 #ifndef EMU10K1_CENTER_LFE_FROM_FRONT 2300 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_CENTER), GPR(playback + 4), C_00000000, C_00000000); 2301 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ACENTER), GPR(playback + 4), C_00000000, C_00000000); 2302 #else 2303 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_CENTER), GPR(playback + 0), C_00000000, C_00000000); 2304 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ACENTER), GPR(playback + 0), C_00000000, C_00000000); 2305 #endif 2306 } 2307 2308 if (emu->fx8010.extout_mask & (1<<EXTOUT_AC97_LFE)) { 2309 #ifndef EMU10K1_CENTER_LFE_FROM_FRONT 2310 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_LFE), GPR(playback + 5), C_00000000, C_00000000); 2311 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ALFE), GPR(playback + 5), C_00000000, C_00000000); 2312 #else 2313 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_LFE), GPR(playback + 1), C_00000000, C_00000000); 2314 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ALFE), GPR(playback + 1), C_00000000, C_00000000); 2315 #endif 2316 } 2317 2318 #ifndef EMU10K1_CAPTURE_DIGITAL_OUT 2319 for (z = 0; z < 2; z++) 2320 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ADC_CAP_L + z), GPR(capture + z), C_00000000, C_00000000); 2321 #endif 2322 2323 if (emu->fx8010.extout_mask & (1<<EXTOUT_MIC_CAP)) 2324 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_MIC_CAP), GPR(capture + 2), C_00000000, C_00000000); 2325 2326 /* EFX capture - capture the 16 EXTINS */ 2327 if (emu->card_capabilities->sblive51) { 2328 for (z = 0; z < 16; z++) { 2329 s8 c = snd_emu10k1_sblive51_fxbus2_map[z]; 2330 if (c != -1) 2331 OP(icode, &ptr, iACC3, FXBUS2(z), C_00000000, C_00000000, EXTIN(c)); 2332 } 2333 } else { 2334 for (z = 0; z < 16; z++) 2335 OP(icode, &ptr, iACC3, FXBUS2(z), C_00000000, C_00000000, EXTIN(z)); 2336 } 2337 2338 2339 if (gpr > tmp) { 2340 snd_BUG(); 2341 err = -EIO; 2342 goto __err; 2343 } 2344 if (i > SND_EMU10K1_GPR_CONTROLS) { 2345 snd_BUG(); 2346 err = -EIO; 2347 goto __err; 2348 } 2349 2350 /* clear remaining instruction memory */ 2351 while (ptr < 0x200) 2352 OP(icode, &ptr, iACC3, C_00000000, C_00000000, C_00000000, C_00000000); 2353 2354 err = snd_emu10k1_fx8010_tram_setup(emu, ipcm->buffer_size); 2355 if (err < 0) 2356 goto __err; 2357 icode->gpr_add_control_count = i; 2358 icode->gpr_add_controls = controls; 2359 emu->support_tlv = 1; /* support TLV */ 2360 err = snd_emu10k1_icode_poke(emu, icode, true); 2361 emu->support_tlv = 0; /* clear again */ 2362 if (err >= 0) 2363 err = snd_emu10k1_ipcm_poke(emu, ipcm); 2364 __err: 2365 kfree(ipcm); 2366 __err_ipcm: 2367 kfree(controls); 2368 __err_ctrls: 2369 kfree(icode->gpr_map); 2370 __err_gpr: 2371 kfree(icode); 2372 return err; 2373 } 2374 2375 int snd_emu10k1_init_efx(struct snd_emu10k1 *emu) 2376 { 2377 spin_lock_init(&emu->fx8010.irq_lock); 2378 INIT_LIST_HEAD(&emu->fx8010.gpr_ctl); 2379 if (emu->audigy) 2380 return _snd_emu10k1_audigy_init_efx(emu); 2381 else 2382 return _snd_emu10k1_init_efx(emu); 2383 } 2384 2385 void snd_emu10k1_free_efx(struct snd_emu10k1 *emu) 2386 { 2387 /* stop processor */ 2388 if (emu->audigy) 2389 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg = A_DBG_SINGLE_STEP); 2390 else 2391 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg = EMU10K1_DBG_SINGLE_STEP); 2392 } 2393 2394 #if 0 /* FIXME: who use them? */ 2395 int snd_emu10k1_fx8010_tone_control_activate(struct snd_emu10k1 *emu, int output) 2396 { 2397 if (output < 0 || output >= 6) 2398 return -EINVAL; 2399 snd_emu10k1_ptr_write(emu, emu->gpr_base + 0x94 + output, 0, 1); 2400 return 0; 2401 } 2402 2403 int snd_emu10k1_fx8010_tone_control_deactivate(struct snd_emu10k1 *emu, int output) 2404 { 2405 if (output < 0 || output >= 6) 2406 return -EINVAL; 2407 snd_emu10k1_ptr_write(emu, emu->gpr_base + 0x94 + output, 0, 0); 2408 return 0; 2409 } 2410 #endif 2411 2412 int snd_emu10k1_fx8010_tram_setup(struct snd_emu10k1 *emu, u32 size) 2413 { 2414 u8 size_reg = 0; 2415 2416 /* size is in samples */ 2417 if (size != 0) { 2418 size = (size - 1) >> 13; 2419 2420 while (size) { 2421 size >>= 1; 2422 size_reg++; 2423 } 2424 size = 0x2000 << size_reg; 2425 } 2426 if ((emu->fx8010.etram_pages.bytes / 2) == size) 2427 return 0; 2428 spin_lock_irq(&emu->emu_lock); 2429 outl(HCFG_LOCKTANKCACHE_MASK | inl(emu->port + HCFG), emu->port + HCFG); 2430 spin_unlock_irq(&emu->emu_lock); 2431 snd_emu10k1_ptr_write(emu, TCB, 0, 0); 2432 snd_emu10k1_ptr_write(emu, TCBS, 0, TCBS_BUFFSIZE_16K); 2433 if (emu->fx8010.etram_pages.area != NULL) { 2434 snd_dma_free_pages(&emu->fx8010.etram_pages); 2435 emu->fx8010.etram_pages.area = NULL; 2436 emu->fx8010.etram_pages.bytes = 0; 2437 } 2438 2439 if (size > 0) { 2440 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &emu->pci->dev, 2441 size * 2, &emu->fx8010.etram_pages) < 0) 2442 return -ENOMEM; 2443 memset(emu->fx8010.etram_pages.area, 0, size * 2); 2444 snd_emu10k1_ptr_write(emu, TCB, 0, emu->fx8010.etram_pages.addr); 2445 snd_emu10k1_ptr_write(emu, TCBS, 0, size_reg); 2446 spin_lock_irq(&emu->emu_lock); 2447 outl(inl(emu->port + HCFG) & ~HCFG_LOCKTANKCACHE_MASK, emu->port + HCFG); 2448 spin_unlock_irq(&emu->emu_lock); 2449 } 2450 2451 return 0; 2452 } 2453 2454 static int snd_emu10k1_fx8010_open(struct snd_hwdep * hw, struct file *file) 2455 { 2456 return 0; 2457 } 2458 2459 static void copy_string(char *dst, const char *src, const char *null, int idx) 2460 { 2461 if (src == NULL) 2462 sprintf(dst, "%s %02X", null, idx); 2463 else 2464 strcpy(dst, src); 2465 } 2466 2467 static void snd_emu10k1_fx8010_info(struct snd_emu10k1 *emu, 2468 struct snd_emu10k1_fx8010_info *info) 2469 { 2470 const char * const *fxbus, * const *extin, * const *extout; 2471 unsigned short extin_mask, extout_mask; 2472 int res; 2473 2474 info->internal_tram_size = emu->fx8010.itram_size; 2475 info->external_tram_size = emu->fx8010.etram_pages.bytes / 2; 2476 fxbus = snd_emu10k1_fxbus; 2477 extin = emu->audigy ? snd_emu10k1_audigy_ins : snd_emu10k1_sblive_ins; 2478 extout = emu->audigy ? snd_emu10k1_audigy_outs : snd_emu10k1_sblive_outs; 2479 extin_mask = emu->audigy ? ~0 : emu->fx8010.extin_mask; 2480 extout_mask = emu->audigy ? ~0 : emu->fx8010.extout_mask; 2481 for (res = 0; res < 16; res++, fxbus++, extin++, extout++) { 2482 copy_string(info->fxbus_names[res], *fxbus, "FXBUS", res); 2483 copy_string(info->extin_names[res], extin_mask & (1 << res) ? *extin : NULL, "Unused", res); 2484 copy_string(info->extout_names[res], extout_mask & (1 << res) ? *extout : NULL, "Unused", res); 2485 } 2486 for (res = 16; res < 32; res++, extout++) 2487 copy_string(info->extout_names[res], extout_mask & (1 << res) ? *extout : NULL, "Unused", res); 2488 info->gpr_controls = emu->fx8010.gpr_count; 2489 } 2490 2491 static int snd_emu10k1_fx8010_ioctl(struct snd_hwdep * hw, struct file *file, unsigned int cmd, unsigned long arg) 2492 { 2493 struct snd_emu10k1 *emu = hw->private_data; 2494 struct snd_emu10k1_fx8010_info *info; 2495 struct snd_emu10k1_fx8010_code *icode; 2496 struct snd_emu10k1_fx8010_pcm_rec *ipcm; 2497 unsigned int addr; 2498 void __user *argp = (void __user *)arg; 2499 int res; 2500 2501 switch (cmd) { 2502 case SNDRV_EMU10K1_IOCTL_PVERSION: 2503 emu->support_tlv = 1; 2504 return put_user(SNDRV_EMU10K1_VERSION, (int __user *)argp); 2505 case SNDRV_EMU10K1_IOCTL_INFO: 2506 info = kzalloc(sizeof(*info), GFP_KERNEL); 2507 if (!info) 2508 return -ENOMEM; 2509 snd_emu10k1_fx8010_info(emu, info); 2510 if (copy_to_user(argp, info, sizeof(*info))) { 2511 kfree(info); 2512 return -EFAULT; 2513 } 2514 kfree(info); 2515 return 0; 2516 case SNDRV_EMU10K1_IOCTL_CODE_POKE: 2517 if (!capable(CAP_SYS_ADMIN)) 2518 return -EPERM; 2519 2520 icode = memdup_user(argp, sizeof(*icode)); 2521 if (IS_ERR(icode)) 2522 return PTR_ERR(icode); 2523 res = snd_emu10k1_icode_poke(emu, icode, false); 2524 kfree(icode); 2525 return res; 2526 case SNDRV_EMU10K1_IOCTL_CODE_PEEK: 2527 icode = memdup_user(argp, sizeof(*icode)); 2528 if (IS_ERR(icode)) 2529 return PTR_ERR(icode); 2530 res = snd_emu10k1_icode_peek(emu, icode); 2531 if (res == 0 && copy_to_user(argp, icode, sizeof(*icode))) { 2532 kfree(icode); 2533 return -EFAULT; 2534 } 2535 kfree(icode); 2536 return res; 2537 case SNDRV_EMU10K1_IOCTL_PCM_POKE: 2538 ipcm = memdup_user(argp, sizeof(*ipcm)); 2539 if (IS_ERR(ipcm)) 2540 return PTR_ERR(ipcm); 2541 res = snd_emu10k1_ipcm_poke(emu, ipcm); 2542 kfree(ipcm); 2543 return res; 2544 case SNDRV_EMU10K1_IOCTL_PCM_PEEK: 2545 ipcm = memdup_user(argp, sizeof(*ipcm)); 2546 if (IS_ERR(ipcm)) 2547 return PTR_ERR(ipcm); 2548 res = snd_emu10k1_ipcm_peek(emu, ipcm); 2549 if (res == 0 && copy_to_user(argp, ipcm, sizeof(*ipcm))) { 2550 kfree(ipcm); 2551 return -EFAULT; 2552 } 2553 kfree(ipcm); 2554 return res; 2555 case SNDRV_EMU10K1_IOCTL_TRAM_SETUP: 2556 if (!capable(CAP_SYS_ADMIN)) 2557 return -EPERM; 2558 if (get_user(addr, (unsigned int __user *)argp)) 2559 return -EFAULT; 2560 mutex_lock(&emu->fx8010.lock); 2561 res = snd_emu10k1_fx8010_tram_setup(emu, addr); 2562 mutex_unlock(&emu->fx8010.lock); 2563 return res; 2564 case SNDRV_EMU10K1_IOCTL_STOP: 2565 if (!capable(CAP_SYS_ADMIN)) 2566 return -EPERM; 2567 if (emu->audigy) 2568 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg |= A_DBG_SINGLE_STEP); 2569 else 2570 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg |= EMU10K1_DBG_SINGLE_STEP); 2571 return 0; 2572 case SNDRV_EMU10K1_IOCTL_CONTINUE: 2573 if (!capable(CAP_SYS_ADMIN)) 2574 return -EPERM; 2575 if (emu->audigy) 2576 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg = 0); 2577 else 2578 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg = 0); 2579 return 0; 2580 case SNDRV_EMU10K1_IOCTL_ZERO_TRAM_COUNTER: 2581 if (!capable(CAP_SYS_ADMIN)) 2582 return -EPERM; 2583 if (emu->audigy) 2584 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg | A_DBG_ZC); 2585 else 2586 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg | EMU10K1_DBG_ZC); 2587 udelay(10); 2588 if (emu->audigy) 2589 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg); 2590 else 2591 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg); 2592 return 0; 2593 case SNDRV_EMU10K1_IOCTL_SINGLE_STEP: 2594 if (!capable(CAP_SYS_ADMIN)) 2595 return -EPERM; 2596 if (get_user(addr, (unsigned int __user *)argp)) 2597 return -EFAULT; 2598 if (emu->audigy) { 2599 if (addr > A_DBG_STEP_ADDR) 2600 return -EINVAL; 2601 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg |= A_DBG_SINGLE_STEP); 2602 udelay(10); 2603 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg | A_DBG_STEP | addr); 2604 } else { 2605 if (addr > EMU10K1_DBG_SINGLE_STEP_ADDR) 2606 return -EINVAL; 2607 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg |= EMU10K1_DBG_SINGLE_STEP); 2608 udelay(10); 2609 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg | EMU10K1_DBG_STEP | addr); 2610 } 2611 return 0; 2612 case SNDRV_EMU10K1_IOCTL_DBG_READ: 2613 if (emu->audigy) 2614 addr = snd_emu10k1_ptr_read(emu, A_DBG, 0); 2615 else 2616 addr = snd_emu10k1_ptr_read(emu, DBG, 0); 2617 if (put_user(addr, (unsigned int __user *)argp)) 2618 return -EFAULT; 2619 return 0; 2620 } 2621 return -ENOTTY; 2622 } 2623 2624 static int snd_emu10k1_fx8010_release(struct snd_hwdep * hw, struct file *file) 2625 { 2626 return 0; 2627 } 2628 2629 int snd_emu10k1_fx8010_new(struct snd_emu10k1 *emu, int device) 2630 { 2631 struct snd_hwdep *hw; 2632 int err; 2633 2634 err = snd_hwdep_new(emu->card, "FX8010", device, &hw); 2635 if (err < 0) 2636 return err; 2637 strcpy(hw->name, "EMU10K1 (FX8010)"); 2638 hw->iface = SNDRV_HWDEP_IFACE_EMU10K1; 2639 hw->ops.open = snd_emu10k1_fx8010_open; 2640 hw->ops.ioctl = snd_emu10k1_fx8010_ioctl; 2641 hw->ops.release = snd_emu10k1_fx8010_release; 2642 hw->private_data = emu; 2643 return 0; 2644 } 2645 2646 #ifdef CONFIG_PM_SLEEP 2647 int snd_emu10k1_efx_alloc_pm_buffer(struct snd_emu10k1 *emu) 2648 { 2649 int len; 2650 2651 len = emu->audigy ? 0x200 : 0x100; 2652 emu->saved_gpr = kmalloc_array(len, 4, GFP_KERNEL); 2653 if (! emu->saved_gpr) 2654 return -ENOMEM; 2655 len = emu->audigy ? 0x100 : 0xa0; 2656 emu->tram_val_saved = kmalloc_array(len, 4, GFP_KERNEL); 2657 emu->tram_addr_saved = kmalloc_array(len, 4, GFP_KERNEL); 2658 if (! emu->tram_val_saved || ! emu->tram_addr_saved) 2659 return -ENOMEM; 2660 len = emu->audigy ? 2 * 1024 : 2 * 512; 2661 emu->saved_icode = vmalloc(array_size(len, 4)); 2662 if (! emu->saved_icode) 2663 return -ENOMEM; 2664 return 0; 2665 } 2666 2667 void snd_emu10k1_efx_free_pm_buffer(struct snd_emu10k1 *emu) 2668 { 2669 kfree(emu->saved_gpr); 2670 kfree(emu->tram_val_saved); 2671 kfree(emu->tram_addr_saved); 2672 vfree(emu->saved_icode); 2673 } 2674 2675 /* 2676 * save/restore GPR, TRAM and codes 2677 */ 2678 void snd_emu10k1_efx_suspend(struct snd_emu10k1 *emu) 2679 { 2680 int i, len; 2681 2682 len = emu->audigy ? 0x200 : 0x100; 2683 for (i = 0; i < len; i++) 2684 emu->saved_gpr[i] = snd_emu10k1_ptr_read(emu, emu->gpr_base + i, 0); 2685 2686 len = emu->audigy ? 0x100 : 0xa0; 2687 for (i = 0; i < len; i++) { 2688 emu->tram_val_saved[i] = snd_emu10k1_ptr_read(emu, TANKMEMDATAREGBASE + i, 0); 2689 emu->tram_addr_saved[i] = snd_emu10k1_ptr_read(emu, TANKMEMADDRREGBASE + i, 0); 2690 if (emu->audigy) { 2691 emu->tram_addr_saved[i] >>= 12; 2692 emu->tram_addr_saved[i] |= 2693 snd_emu10k1_ptr_read(emu, A_TANKMEMCTLREGBASE + i, 0) << 20; 2694 } 2695 } 2696 2697 len = emu->audigy ? 2 * 1024 : 2 * 512; 2698 for (i = 0; i < len; i++) 2699 emu->saved_icode[i] = snd_emu10k1_efx_read(emu, i); 2700 } 2701 2702 void snd_emu10k1_efx_resume(struct snd_emu10k1 *emu) 2703 { 2704 int i, len; 2705 2706 /* set up TRAM */ 2707 if (emu->fx8010.etram_pages.bytes > 0) { 2708 unsigned size, size_reg = 0; 2709 size = emu->fx8010.etram_pages.bytes / 2; 2710 size = (size - 1) >> 13; 2711 while (size) { 2712 size >>= 1; 2713 size_reg++; 2714 } 2715 outl(HCFG_LOCKTANKCACHE_MASK | inl(emu->port + HCFG), emu->port + HCFG); 2716 snd_emu10k1_ptr_write(emu, TCB, 0, emu->fx8010.etram_pages.addr); 2717 snd_emu10k1_ptr_write(emu, TCBS, 0, size_reg); 2718 outl(inl(emu->port + HCFG) & ~HCFG_LOCKTANKCACHE_MASK, emu->port + HCFG); 2719 } 2720 2721 if (emu->audigy) 2722 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg | A_DBG_SINGLE_STEP); 2723 else 2724 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg | EMU10K1_DBG_SINGLE_STEP); 2725 2726 len = emu->audigy ? 0x200 : 0x100; 2727 for (i = 0; i < len; i++) 2728 snd_emu10k1_ptr_write(emu, emu->gpr_base + i, 0, emu->saved_gpr[i]); 2729 2730 len = emu->audigy ? 0x100 : 0xa0; 2731 for (i = 0; i < len; i++) { 2732 snd_emu10k1_ptr_write(emu, TANKMEMDATAREGBASE + i, 0, 2733 emu->tram_val_saved[i]); 2734 if (! emu->audigy) 2735 snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + i, 0, 2736 emu->tram_addr_saved[i]); 2737 else { 2738 snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + i, 0, 2739 emu->tram_addr_saved[i] << 12); 2740 snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + i, 0, 2741 emu->tram_addr_saved[i] >> 20); 2742 } 2743 } 2744 2745 len = emu->audigy ? 2 * 1024 : 2 * 512; 2746 for (i = 0; i < len; i++) 2747 snd_emu10k1_efx_write(emu, i, emu->saved_icode[i]); 2748 2749 /* start FX processor when the DSP code is updated */ 2750 if (emu->audigy) 2751 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg); 2752 else 2753 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg); 2754 } 2755 #endif 2756