1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (c) by Jaroslav Kysela <perex@perex.cz> 4 * Creative Labs, Inc. 5 * Routines for effect processor FX8010 6 * 7 * Copyright (c) by James Courtier-Dutton <James@superbug.co.uk> 8 * Added EMU 1010 support. 9 * 10 * BUGS: 11 * -- 12 * 13 * TODO: 14 * -- 15 */ 16 17 #include <linux/pci.h> 18 #include <linux/capability.h> 19 #include <linux/delay.h> 20 #include <linux/slab.h> 21 #include <linux/vmalloc.h> 22 #include <linux/init.h> 23 #include <linux/mutex.h> 24 #include <linux/moduleparam.h> 25 #include <linux/nospec.h> 26 27 #include <sound/core.h> 28 #include <sound/tlv.h> 29 #include <sound/emu10k1.h> 30 31 #if 0 /* for testing purposes - digital out -> capture */ 32 #define EMU10K1_CAPTURE_DIGITAL_OUT 33 #endif 34 #if 0 /* for testing purposes - set S/PDIF to AC3 output */ 35 #define EMU10K1_SET_AC3_IEC958 36 #endif 37 #if 0 /* for testing purposes - feed the front signal to Center/LFE outputs */ 38 #define EMU10K1_CENTER_LFE_FROM_FRONT 39 #endif 40 41 static bool high_res_gpr_volume; 42 module_param(high_res_gpr_volume, bool, 0444); 43 MODULE_PARM_DESC(high_res_gpr_volume, "GPR mixer controls use 31-bit range."); 44 45 /* 46 * Tables 47 */ 48 49 static const char * const fxbuses[16] = { 50 /* 0x00 */ "PCM Left", 51 /* 0x01 */ "PCM Right", 52 /* 0x02 */ "PCM Surround Left", 53 /* 0x03 */ "PCM Surround Right", 54 /* 0x04 */ "MIDI Left", 55 /* 0x05 */ "MIDI Right", 56 /* 0x06 */ "Center", 57 /* 0x07 */ "LFE", 58 /* 0x08 */ NULL, 59 /* 0x09 */ NULL, 60 /* 0x0a */ NULL, 61 /* 0x0b */ NULL, 62 /* 0x0c */ "MIDI Reverb", 63 /* 0x0d */ "MIDI Chorus", 64 /* 0x0e */ NULL, 65 /* 0x0f */ NULL 66 }; 67 68 static const char * const creative_ins[16] = { 69 /* 0x00 */ "AC97 Left", 70 /* 0x01 */ "AC97 Right", 71 /* 0x02 */ "TTL IEC958 Left", 72 /* 0x03 */ "TTL IEC958 Right", 73 /* 0x04 */ "Zoom Video Left", 74 /* 0x05 */ "Zoom Video Right", 75 /* 0x06 */ "Optical IEC958 Left", 76 /* 0x07 */ "Optical IEC958 Right", 77 /* 0x08 */ "Line/Mic 1 Left", 78 /* 0x09 */ "Line/Mic 1 Right", 79 /* 0x0a */ "Coaxial IEC958 Left", 80 /* 0x0b */ "Coaxial IEC958 Right", 81 /* 0x0c */ "Line/Mic 2 Left", 82 /* 0x0d */ "Line/Mic 2 Right", 83 /* 0x0e */ NULL, 84 /* 0x0f */ NULL 85 }; 86 87 static const char * const audigy_ins[16] = { 88 /* 0x00 */ "AC97 Left", 89 /* 0x01 */ "AC97 Right", 90 /* 0x02 */ "Audigy CD Left", 91 /* 0x03 */ "Audigy CD Right", 92 /* 0x04 */ "Optical IEC958 Left", 93 /* 0x05 */ "Optical IEC958 Right", 94 /* 0x06 */ NULL, 95 /* 0x07 */ NULL, 96 /* 0x08 */ "Line/Mic 2 Left", 97 /* 0x09 */ "Line/Mic 2 Right", 98 /* 0x0a */ "SPDIF Left", 99 /* 0x0b */ "SPDIF Right", 100 /* 0x0c */ "Aux2 Left", 101 /* 0x0d */ "Aux2 Right", 102 /* 0x0e */ NULL, 103 /* 0x0f */ NULL 104 }; 105 106 static const char * const creative_outs[32] = { 107 /* 0x00 */ "AC97 Left", 108 /* 0x01 */ "AC97 Right", 109 /* 0x02 */ "Optical IEC958 Left", 110 /* 0x03 */ "Optical IEC958 Right", 111 /* 0x04 */ "Center", 112 /* 0x05 */ "LFE", 113 /* 0x06 */ "Headphone Left", 114 /* 0x07 */ "Headphone Right", 115 /* 0x08 */ "Surround Left", 116 /* 0x09 */ "Surround Right", 117 /* 0x0a */ "PCM Capture Left", 118 /* 0x0b */ "PCM Capture Right", 119 /* 0x0c */ "MIC Capture", 120 /* 0x0d */ "AC97 Surround Left", 121 /* 0x0e */ "AC97 Surround Right", 122 /* 0x0f */ NULL, 123 /* 0x10 */ NULL, 124 /* 0x11 */ "Analog Center", 125 /* 0x12 */ "Analog LFE", 126 /* 0x13 */ NULL, 127 /* 0x14 */ NULL, 128 /* 0x15 */ NULL, 129 /* 0x16 */ NULL, 130 /* 0x17 */ NULL, 131 /* 0x18 */ NULL, 132 /* 0x19 */ NULL, 133 /* 0x1a */ NULL, 134 /* 0x1b */ NULL, 135 /* 0x1c */ NULL, 136 /* 0x1d */ NULL, 137 /* 0x1e */ NULL, 138 /* 0x1f */ NULL, 139 }; 140 141 static const char * const audigy_outs[32] = { 142 /* 0x00 */ "Digital Front Left", 143 /* 0x01 */ "Digital Front Right", 144 /* 0x02 */ "Digital Center", 145 /* 0x03 */ "Digital LEF", 146 /* 0x04 */ "Headphone Left", 147 /* 0x05 */ "Headphone Right", 148 /* 0x06 */ "Digital Rear Left", 149 /* 0x07 */ "Digital Rear Right", 150 /* 0x08 */ "Front Left", 151 /* 0x09 */ "Front Right", 152 /* 0x0a */ "Center", 153 /* 0x0b */ "LFE", 154 /* 0x0c */ NULL, 155 /* 0x0d */ NULL, 156 /* 0x0e */ "Rear Left", 157 /* 0x0f */ "Rear Right", 158 /* 0x10 */ "AC97 Front Left", 159 /* 0x11 */ "AC97 Front Right", 160 /* 0x12 */ "ADC Capture Left", 161 /* 0x13 */ "ADC Capture Right", 162 /* 0x14 */ NULL, 163 /* 0x15 */ NULL, 164 /* 0x16 */ NULL, 165 /* 0x17 */ NULL, 166 /* 0x18 */ NULL, 167 /* 0x19 */ NULL, 168 /* 0x1a */ NULL, 169 /* 0x1b */ NULL, 170 /* 0x1c */ NULL, 171 /* 0x1d */ NULL, 172 /* 0x1e */ NULL, 173 /* 0x1f */ NULL, 174 }; 175 176 static const u32 bass_table[41][5] = { 177 { 0x3e4f844f, 0x84ed4cc3, 0x3cc69927, 0x7b03553a, 0xc4da8486 }, 178 { 0x3e69a17a, 0x84c280fb, 0x3cd77cd4, 0x7b2f2a6f, 0xc4b08d1d }, 179 { 0x3e82ff42, 0x849991d5, 0x3ce7466b, 0x7b5917c6, 0xc48863ee }, 180 { 0x3e9bab3c, 0x847267f0, 0x3cf5ffe8, 0x7b813560, 0xc461f22c }, 181 { 0x3eb3b275, 0x844ced29, 0x3d03b295, 0x7ba79a1c, 0xc43d223b }, 182 { 0x3ecb2174, 0x84290c8b, 0x3d106714, 0x7bcc5ba3, 0xc419dfa5 }, 183 { 0x3ee2044b, 0x8406b244, 0x3d1c2561, 0x7bef8e77, 0xc3f8170f }, 184 { 0x3ef86698, 0x83e5cb96, 0x3d26f4d8, 0x7c114600, 0xc3d7b625 }, 185 { 0x3f0e5390, 0x83c646c9, 0x3d30dc39, 0x7c319498, 0xc3b8ab97 }, 186 { 0x3f23d60b, 0x83a81321, 0x3d39e1af, 0x7c508b9c, 0xc39ae704 }, 187 { 0x3f38f884, 0x838b20d2, 0x3d420ad2, 0x7c6e3b75, 0xc37e58f1 }, 188 { 0x3f4dc52c, 0x836f60ef, 0x3d495cab, 0x7c8ab3a6, 0xc362f2be }, 189 { 0x3f6245e8, 0x8354c565, 0x3d4fdbb8, 0x7ca602d6, 0xc348a69b }, 190 { 0x3f76845f, 0x833b40ec, 0x3d558bf0, 0x7cc036df, 0xc32f677c }, 191 { 0x3f8a8a03, 0x8322c6fb, 0x3d5a70c4, 0x7cd95cd7, 0xc317290b }, 192 { 0x3f9e6014, 0x830b4bc3, 0x3d5e8d25, 0x7cf1811a, 0xc2ffdfa5 }, 193 { 0x3fb20fae, 0x82f4c420, 0x3d61e37f, 0x7d08af56, 0xc2e9804a }, 194 { 0x3fc5a1cc, 0x82df2592, 0x3d6475c3, 0x7d1ef294, 0xc2d40096 }, 195 { 0x3fd91f55, 0x82ca6632, 0x3d664564, 0x7d345541, 0xc2bf56b9 }, 196 { 0x3fec9120, 0x82b67cac, 0x3d675356, 0x7d48e138, 0xc2ab796e }, 197 { 0x40000000, 0x82a36037, 0x3d67a012, 0x7d5c9fc9, 0xc2985fee }, 198 { 0x401374c7, 0x8291088a, 0x3d672b93, 0x7d6f99c3, 0xc28601f2 }, 199 { 0x4026f857, 0x827f6dd7, 0x3d65f559, 0x7d81d77c, 0xc27457a3 }, 200 { 0x403a939f, 0x826e88c5, 0x3d63fc63, 0x7d9360d4, 0xc2635996 }, 201 { 0x404e4faf, 0x825e5266, 0x3d613f32, 0x7da43d42, 0xc25300c6 }, 202 { 0x406235ba, 0x824ec434, 0x3d5dbbc3, 0x7db473d7, 0xc243468e }, 203 { 0x40764f1f, 0x823fd80c, 0x3d596f8f, 0x7dc40b44, 0xc23424a2 }, 204 { 0x408aa576, 0x82318824, 0x3d545787, 0x7dd309e2, 0xc2259509 }, 205 { 0x409f4296, 0x8223cf0b, 0x3d4e7012, 0x7de175b5, 0xc2179218 }, 206 { 0x40b430a0, 0x8216a7a1, 0x3d47b505, 0x7def5475, 0xc20a1670 }, 207 { 0x40c97a0a, 0x820a0d12, 0x3d4021a1, 0x7dfcab8d, 0xc1fd1cf5 }, 208 { 0x40df29a6, 0x81fdfad6, 0x3d37b08d, 0x7e098028, 0xc1f0a0ca }, 209 { 0x40f54ab1, 0x81f26ca9, 0x3d2e5bd1, 0x7e15d72b, 0xc1e49d52 }, 210 { 0x410be8da, 0x81e75e89, 0x3d241cce, 0x7e21b544, 0xc1d90e24 }, 211 { 0x41231051, 0x81dcccb3, 0x3d18ec37, 0x7e2d1ee6, 0xc1cdef10 }, 212 { 0x413acdd0, 0x81d2b39e, 0x3d0cc20a, 0x7e38184e, 0xc1c33c13 }, 213 { 0x41532ea7, 0x81c90ffb, 0x3cff9585, 0x7e42a58b, 0xc1b8f15a }, 214 { 0x416c40cd, 0x81bfdeb2, 0x3cf15d21, 0x7e4cca7c, 0xc1af0b3f }, 215 { 0x418612ea, 0x81b71cdc, 0x3ce20e85, 0x7e568ad3, 0xc1a58640 }, 216 { 0x41a0b465, 0x81aec7c5, 0x3cd19e7c, 0x7e5fea1e, 0xc19c5f03 }, 217 { 0x41bc3573, 0x81a6dcea, 0x3cc000e9, 0x7e68ebc2, 0xc1939250 } 218 }; 219 220 static const u32 treble_table[41][5] = { 221 { 0x0125cba9, 0xfed5debd, 0x00599b6c, 0x0d2506da, 0xfa85b354 }, 222 { 0x0142f67e, 0xfeb03163, 0x0066cd0f, 0x0d14c69d, 0xfa914473 }, 223 { 0x016328bd, 0xfe860158, 0x0075b7f2, 0x0d03eb27, 0xfa9d32d2 }, 224 { 0x0186b438, 0xfe56c982, 0x00869234, 0x0cf27048, 0xfaa97fca }, 225 { 0x01adf358, 0xfe21f5fe, 0x00999842, 0x0ce051c2, 0xfab62ca5 }, 226 { 0x01d949fa, 0xfde6e287, 0x00af0d8d, 0x0ccd8b4a, 0xfac33aa7 }, 227 { 0x02092669, 0xfda4d8bf, 0x00c73d4c, 0x0cba1884, 0xfad0ab07 }, 228 { 0x023e0268, 0xfd5b0e4a, 0x00e27b54, 0x0ca5f509, 0xfade7ef2 }, 229 { 0x0278645c, 0xfd08a2b0, 0x01012509, 0x0c911c63, 0xfaecb788 }, 230 { 0x02b8e091, 0xfcac9d1a, 0x0123a262, 0x0c7b8a14, 0xfafb55df }, 231 { 0x03001a9a, 0xfc45e9ce, 0x014a6709, 0x0c65398f, 0xfb0a5aff }, 232 { 0x034ec6d7, 0xfbd3576b, 0x0175f397, 0x0c4e2643, 0xfb19c7e4 }, 233 { 0x03a5ac15, 0xfb5393ee, 0x01a6d6ed, 0x0c364b94, 0xfb299d7c }, 234 { 0x0405a562, 0xfac52968, 0x01ddafae, 0x0c1da4e2, 0xfb39dca5 }, 235 { 0x046fa3fe, 0xfa267a66, 0x021b2ddd, 0x0c042d8d, 0xfb4a8631 }, 236 { 0x04e4b17f, 0xf975be0f, 0x0260149f, 0x0be9e0f2, 0xfb5b9ae0 }, 237 { 0x0565f220, 0xf8b0fbe5, 0x02ad3c29, 0x0bceba73, 0xfb6d1b60 }, 238 { 0x05f4a745, 0xf7d60722, 0x030393d4, 0x0bb2b578, 0xfb7f084d }, 239 { 0x06923236, 0xf6e279bd, 0x03642465, 0x0b95cd75, 0xfb916233 }, 240 { 0x07401713, 0xf5d3aef9, 0x03d01283, 0x0b77fded, 0xfba42984 }, 241 { 0x08000000, 0xf4a6bd88, 0x0448a161, 0x0b594278, 0xfbb75e9f }, 242 { 0x08d3c097, 0xf3587131, 0x04cf35a4, 0x0b3996c9, 0xfbcb01cb }, 243 { 0x09bd59a2, 0xf1e543f9, 0x05655880, 0x0b18f6b2, 0xfbdf1333 }, 244 { 0x0abefd0f, 0xf04956ca, 0x060cbb12, 0x0af75e2c, 0xfbf392e8 }, 245 { 0x0bdb123e, 0xee806984, 0x06c739fe, 0x0ad4c962, 0xfc0880dd }, 246 { 0x0d143a94, 0xec85d287, 0x0796e150, 0x0ab134b0, 0xfc1ddce5 }, 247 { 0x0e6d5664, 0xea547598, 0x087df0a0, 0x0a8c9cb6, 0xfc33a6ad }, 248 { 0x0fe98a2a, 0xe7e6ba35, 0x097edf83, 0x0a66fe5b, 0xfc49ddc2 }, 249 { 0x118c4421, 0xe536813a, 0x0a9c6248, 0x0a4056d7, 0xfc608185 }, 250 { 0x1359422e, 0xe23d19eb, 0x0bd96efb, 0x0a18a3bf, 0xfc77912c }, 251 { 0x1554982b, 0xdef33645, 0x0d3942bd, 0x09efe312, 0xfc8f0bc1 }, 252 { 0x1782b68a, 0xdb50deb1, 0x0ebf676d, 0x09c6133f, 0xfca6f019 }, 253 { 0x19e8715d, 0xd74d64fd, 0x106fb999, 0x099b3337, 0xfcbf3cd6 }, 254 { 0x1c8b07b8, 0xd2df56ab, 0x124e6ec8, 0x096f4274, 0xfcd7f060 }, 255 { 0x1f702b6d, 0xcdfc6e92, 0x14601c10, 0x0942410b, 0xfcf108e5 }, 256 { 0x229e0933, 0xc89985cd, 0x16a9bcfa, 0x09142fb5, 0xfd0a8451 }, 257 { 0x261b5118, 0xc2aa8409, 0x1930bab6, 0x08e50fdc, 0xfd24604d }, 258 { 0x29ef3f5d, 0xbc224f28, 0x1bfaf396, 0x08b4e3aa, 0xfd3e9a3b }, 259 { 0x2e21a59b, 0xb4f2ba46, 0x1f0ec2d6, 0x0883ae15, 0xfd592f33 }, 260 { 0x32baf44b, 0xad0c7429, 0x227308a3, 0x085172eb, 0xfd741bfd }, 261 { 0x37c4448b, 0xa45ef51d, 0x262f3267, 0x081e36dc, 0xfd8f5d14 } 262 }; 263 264 /* dB gain = (float) 20 * log10( float(db_table_value) / 0x8000000 ) */ 265 static const u32 db_table[101] = { 266 0x00000000, 0x01571f82, 0x01674b41, 0x01783a1b, 0x0189f540, 267 0x019c8651, 0x01aff763, 0x01c45306, 0x01d9a446, 0x01eff6b8, 268 0x0207567a, 0x021fd03d, 0x0239714c, 0x02544792, 0x027061a1, 269 0x028dcebb, 0x02ac9edc, 0x02cce2bf, 0x02eeabe8, 0x03120cb0, 270 0x0337184e, 0x035de2df, 0x03868173, 0x03b10a18, 0x03dd93e9, 271 0x040c3713, 0x043d0cea, 0x04702ff3, 0x04a5bbf2, 0x04ddcdfb, 272 0x0518847f, 0x0555ff62, 0x05966005, 0x05d9c95d, 0x06206005, 273 0x066a4a52, 0x06b7b067, 0x0708bc4c, 0x075d9a01, 0x07b6779d, 274 0x08138561, 0x0874f5d5, 0x08dafde1, 0x0945d4ed, 0x09b5b4fd, 275 0x0a2adad1, 0x0aa58605, 0x0b25f936, 0x0bac7a24, 0x0c3951d8, 276 0x0ccccccc, 0x0d673b17, 0x0e08f093, 0x0eb24510, 0x0f639481, 277 0x101d3f2d, 0x10dfa9e6, 0x11ab3e3f, 0x12806ac3, 0x135fa333, 278 0x144960c5, 0x153e2266, 0x163e6cfe, 0x174acbb7, 0x1863d04d, 279 0x198a1357, 0x1abe349f, 0x1c00db77, 0x1d52b712, 0x1eb47ee6, 280 0x2026f30f, 0x21aadcb6, 0x23410e7e, 0x24ea64f9, 0x26a7c71d, 281 0x287a26c4, 0x2a62812c, 0x2c61df84, 0x2e795779, 0x30aa0bcf, 282 0x32f52cfe, 0x355bf9d8, 0x37dfc033, 0x3a81dda4, 0x3d43c038, 283 0x4026e73c, 0x432ce40f, 0x46575af8, 0x49a8040f, 0x4d20ac2a, 284 0x50c335d3, 0x54919a57, 0x588dead1, 0x5cba514a, 0x611911ea, 285 0x65ac8c2f, 0x6a773c39, 0x6f7bbc23, 0x74bcc56c, 0x7a3d3272, 286 0x7fffffff, 287 }; 288 289 /* EMU10k1/EMU10k2 DSP control db gain */ 290 static const DECLARE_TLV_DB_SCALE(snd_emu10k1_db_scale1, -4000, 40, 1); 291 static const DECLARE_TLV_DB_LINEAR(snd_emu10k1_db_linear, TLV_DB_GAIN_MUTE, 0); 292 293 /* EMU10K1 bass/treble db gain */ 294 static const DECLARE_TLV_DB_SCALE(snd_emu10k1_bass_treble_db_scale, -1200, 60, 0); 295 296 static const u32 onoff_table[2] = { 297 0x00000000, 0x00000001 298 }; 299 300 /* 301 * controls 302 */ 303 304 static int snd_emu10k1_gpr_ctl_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 305 { 306 struct snd_emu10k1_fx8010_ctl *ctl = 307 (struct snd_emu10k1_fx8010_ctl *) kcontrol->private_value; 308 309 if (ctl->min == 0 && ctl->max == 1) 310 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 311 else 312 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 313 uinfo->count = ctl->vcount; 314 uinfo->value.integer.min = ctl->min; 315 uinfo->value.integer.max = ctl->max; 316 return 0; 317 } 318 319 static int snd_emu10k1_gpr_ctl_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 320 { 321 struct snd_emu10k1_fx8010_ctl *ctl = 322 (struct snd_emu10k1_fx8010_ctl *) kcontrol->private_value; 323 unsigned int i; 324 325 for (i = 0; i < ctl->vcount; i++) 326 ucontrol->value.integer.value[i] = ctl->value[i]; 327 return 0; 328 } 329 330 static int snd_emu10k1_gpr_ctl_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 331 { 332 struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol); 333 struct snd_emu10k1_fx8010_ctl *ctl = 334 (struct snd_emu10k1_fx8010_ctl *) kcontrol->private_value; 335 int nval, val; 336 unsigned int i, j; 337 int change = 0; 338 339 for (i = 0; i < ctl->vcount; i++) { 340 nval = ucontrol->value.integer.value[i]; 341 if (nval < ctl->min) 342 nval = ctl->min; 343 if (nval > ctl->max) 344 nval = ctl->max; 345 if (nval != ctl->value[i]) 346 change = 1; 347 val = ctl->value[i] = nval; 348 switch (ctl->translation) { 349 case EMU10K1_GPR_TRANSLATION_NONE: 350 snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[i], 0, val); 351 break; 352 case EMU10K1_GPR_TRANSLATION_NEGATE: 353 snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[i], 0, ~val); 354 break; 355 case EMU10K1_GPR_TRANSLATION_TABLE100: 356 snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[i], 0, db_table[val]); 357 break; 358 case EMU10K1_GPR_TRANSLATION_NEG_TABLE100: 359 snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[i], 0, 360 val == 100 ? 0x80000000 : -(int)db_table[val]); 361 break; 362 case EMU10K1_GPR_TRANSLATION_BASS: 363 if ((ctl->count % 5) != 0 || (ctl->count / 5) != ctl->vcount) { 364 change = -EIO; 365 goto __error; 366 } 367 for (j = 0; j < 5; j++) 368 snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[j * ctl->vcount + i], 0, bass_table[val][j]); 369 break; 370 case EMU10K1_GPR_TRANSLATION_TREBLE: 371 if ((ctl->count % 5) != 0 || (ctl->count / 5) != ctl->vcount) { 372 change = -EIO; 373 goto __error; 374 } 375 for (j = 0; j < 5; j++) 376 snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[j * ctl->vcount + i], 0, treble_table[val][j]); 377 break; 378 case EMU10K1_GPR_TRANSLATION_ONOFF: 379 snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[i], 0, onoff_table[val]); 380 break; 381 } 382 } 383 __error: 384 return change; 385 } 386 387 /* 388 * Interrupt handler 389 */ 390 391 static void snd_emu10k1_fx8010_interrupt(struct snd_emu10k1 *emu) 392 { 393 struct snd_emu10k1_fx8010_irq *irq, *nirq; 394 395 irq = emu->fx8010.irq_handlers; 396 while (irq) { 397 nirq = irq->next; /* irq ptr can be removed from list */ 398 if (snd_emu10k1_ptr_read(emu, emu->gpr_base + irq->gpr_running, 0) & 0xffff0000) { 399 if (irq->handler) 400 irq->handler(emu, irq->private_data); 401 snd_emu10k1_ptr_write(emu, emu->gpr_base + irq->gpr_running, 0, 1); 402 } 403 irq = nirq; 404 } 405 } 406 407 int snd_emu10k1_fx8010_register_irq_handler(struct snd_emu10k1 *emu, 408 snd_fx8010_irq_handler_t *handler, 409 unsigned char gpr_running, 410 void *private_data, 411 struct snd_emu10k1_fx8010_irq *irq) 412 { 413 unsigned long flags; 414 415 irq->handler = handler; 416 irq->gpr_running = gpr_running; 417 irq->private_data = private_data; 418 irq->next = NULL; 419 spin_lock_irqsave(&emu->fx8010.irq_lock, flags); 420 if (emu->fx8010.irq_handlers == NULL) { 421 emu->fx8010.irq_handlers = irq; 422 emu->dsp_interrupt = snd_emu10k1_fx8010_interrupt; 423 snd_emu10k1_intr_enable(emu, INTE_FXDSPENABLE); 424 } else { 425 irq->next = emu->fx8010.irq_handlers; 426 emu->fx8010.irq_handlers = irq; 427 } 428 spin_unlock_irqrestore(&emu->fx8010.irq_lock, flags); 429 return 0; 430 } 431 432 int snd_emu10k1_fx8010_unregister_irq_handler(struct snd_emu10k1 *emu, 433 struct snd_emu10k1_fx8010_irq *irq) 434 { 435 struct snd_emu10k1_fx8010_irq *tmp; 436 unsigned long flags; 437 438 spin_lock_irqsave(&emu->fx8010.irq_lock, flags); 439 tmp = emu->fx8010.irq_handlers; 440 if (tmp == irq) { 441 emu->fx8010.irq_handlers = tmp->next; 442 if (emu->fx8010.irq_handlers == NULL) { 443 snd_emu10k1_intr_disable(emu, INTE_FXDSPENABLE); 444 emu->dsp_interrupt = NULL; 445 } 446 } else { 447 while (tmp && tmp->next != irq) 448 tmp = tmp->next; 449 if (tmp) 450 tmp->next = tmp->next->next; 451 } 452 spin_unlock_irqrestore(&emu->fx8010.irq_lock, flags); 453 return 0; 454 } 455 456 /************************************************************************* 457 * EMU10K1 effect manager 458 *************************************************************************/ 459 460 static void snd_emu10k1_write_op(struct snd_emu10k1_fx8010_code *icode, 461 unsigned int *ptr, 462 u32 op, u32 r, u32 a, u32 x, u32 y) 463 { 464 u_int32_t *code; 465 if (snd_BUG_ON(*ptr >= 512)) 466 return; 467 code = icode->code + (*ptr) * 2; 468 set_bit(*ptr, icode->code_valid); 469 code[0] = ((x & 0x3ff) << 10) | (y & 0x3ff); 470 code[1] = ((op & 0x0f) << 20) | ((r & 0x3ff) << 10) | (a & 0x3ff); 471 (*ptr)++; 472 } 473 474 #define OP(icode, ptr, op, r, a, x, y) \ 475 snd_emu10k1_write_op(icode, ptr, op, r, a, x, y) 476 477 static void snd_emu10k1_audigy_write_op(struct snd_emu10k1_fx8010_code *icode, 478 unsigned int *ptr, 479 u32 op, u32 r, u32 a, u32 x, u32 y) 480 { 481 u_int32_t *code; 482 if (snd_BUG_ON(*ptr >= 1024)) 483 return; 484 code = icode->code + (*ptr) * 2; 485 set_bit(*ptr, icode->code_valid); 486 code[0] = ((x & 0x7ff) << 12) | (y & 0x7ff); 487 code[1] = ((op & 0x0f) << 24) | ((r & 0x7ff) << 12) | (a & 0x7ff); 488 (*ptr)++; 489 } 490 491 #define A_OP(icode, ptr, op, r, a, x, y) \ 492 snd_emu10k1_audigy_write_op(icode, ptr, op, r, a, x, y) 493 494 static void snd_emu10k1_efx_write(struct snd_emu10k1 *emu, unsigned int pc, unsigned int data) 495 { 496 pc += emu->audigy ? A_MICROCODEBASE : MICROCODEBASE; 497 snd_emu10k1_ptr_write(emu, pc, 0, data); 498 } 499 500 unsigned int snd_emu10k1_efx_read(struct snd_emu10k1 *emu, unsigned int pc) 501 { 502 pc += emu->audigy ? A_MICROCODEBASE : MICROCODEBASE; 503 return snd_emu10k1_ptr_read(emu, pc, 0); 504 } 505 506 static int snd_emu10k1_gpr_poke(struct snd_emu10k1 *emu, 507 struct snd_emu10k1_fx8010_code *icode, 508 bool in_kernel) 509 { 510 int gpr; 511 u32 val; 512 513 for (gpr = 0; gpr < (emu->audigy ? 0x200 : 0x100); gpr++) { 514 if (!test_bit(gpr, icode->gpr_valid)) 515 continue; 516 if (in_kernel) 517 val = icode->gpr_map[gpr]; 518 else if (get_user(val, (__user u32 *)&icode->gpr_map[gpr])) 519 return -EFAULT; 520 snd_emu10k1_ptr_write(emu, emu->gpr_base + gpr, 0, val); 521 } 522 return 0; 523 } 524 525 static int snd_emu10k1_gpr_peek(struct snd_emu10k1 *emu, 526 struct snd_emu10k1_fx8010_code *icode) 527 { 528 int gpr; 529 u32 val; 530 531 for (gpr = 0; gpr < (emu->audigy ? 0x200 : 0x100); gpr++) { 532 set_bit(gpr, icode->gpr_valid); 533 val = snd_emu10k1_ptr_read(emu, emu->gpr_base + gpr, 0); 534 if (put_user(val, (__user u32 *)&icode->gpr_map[gpr])) 535 return -EFAULT; 536 } 537 return 0; 538 } 539 540 static int snd_emu10k1_tram_poke(struct snd_emu10k1 *emu, 541 struct snd_emu10k1_fx8010_code *icode, 542 bool in_kernel) 543 { 544 int tram; 545 u32 addr, val; 546 547 for (tram = 0; tram < (emu->audigy ? 0x100 : 0xa0); tram++) { 548 if (!test_bit(tram, icode->tram_valid)) 549 continue; 550 if (in_kernel) { 551 val = icode->tram_data_map[tram]; 552 addr = icode->tram_addr_map[tram]; 553 } else { 554 if (get_user(val, (__user __u32 *)&icode->tram_data_map[tram]) || 555 get_user(addr, (__user __u32 *)&icode->tram_addr_map[tram])) 556 return -EFAULT; 557 } 558 snd_emu10k1_ptr_write(emu, TANKMEMDATAREGBASE + tram, 0, val); 559 if (!emu->audigy) { 560 snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + tram, 0, addr); 561 } else { 562 snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + tram, 0, addr << 12); 563 snd_emu10k1_ptr_write(emu, A_TANKMEMCTLREGBASE + tram, 0, addr >> 20); 564 } 565 } 566 return 0; 567 } 568 569 static int snd_emu10k1_tram_peek(struct snd_emu10k1 *emu, 570 struct snd_emu10k1_fx8010_code *icode) 571 { 572 int tram; 573 u32 val, addr; 574 575 memset(icode->tram_valid, 0, sizeof(icode->tram_valid)); 576 for (tram = 0; tram < (emu->audigy ? 0x100 : 0xa0); tram++) { 577 set_bit(tram, icode->tram_valid); 578 val = snd_emu10k1_ptr_read(emu, TANKMEMDATAREGBASE + tram, 0); 579 if (!emu->audigy) { 580 addr = snd_emu10k1_ptr_read(emu, TANKMEMADDRREGBASE + tram, 0); 581 } else { 582 addr = snd_emu10k1_ptr_read(emu, TANKMEMADDRREGBASE + tram, 0) >> 12; 583 addr |= snd_emu10k1_ptr_read(emu, A_TANKMEMCTLREGBASE + tram, 0) << 20; 584 } 585 if (put_user(val, (__user u32 *)&icode->tram_data_map[tram]) || 586 put_user(addr, (__user u32 *)&icode->tram_addr_map[tram])) 587 return -EFAULT; 588 } 589 return 0; 590 } 591 592 static int snd_emu10k1_code_poke(struct snd_emu10k1 *emu, 593 struct snd_emu10k1_fx8010_code *icode, 594 bool in_kernel) 595 { 596 u32 pc, lo, hi; 597 598 for (pc = 0; pc < (emu->audigy ? 2*1024 : 2*512); pc += 2) { 599 if (!test_bit(pc / 2, icode->code_valid)) 600 continue; 601 if (in_kernel) { 602 lo = icode->code[pc + 0]; 603 hi = icode->code[pc + 1]; 604 } else { 605 if (get_user(lo, (__user u32 *)&icode->code[pc + 0]) || 606 get_user(hi, (__user u32 *)&icode->code[pc + 1])) 607 return -EFAULT; 608 } 609 snd_emu10k1_efx_write(emu, pc + 0, lo); 610 snd_emu10k1_efx_write(emu, pc + 1, hi); 611 } 612 return 0; 613 } 614 615 static int snd_emu10k1_code_peek(struct snd_emu10k1 *emu, 616 struct snd_emu10k1_fx8010_code *icode) 617 { 618 u32 pc; 619 620 memset(icode->code_valid, 0, sizeof(icode->code_valid)); 621 for (pc = 0; pc < (emu->audigy ? 2*1024 : 2*512); pc += 2) { 622 set_bit(pc / 2, icode->code_valid); 623 if (put_user(snd_emu10k1_efx_read(emu, pc + 0), 624 (__user u32 *)&icode->code[pc + 0])) 625 return -EFAULT; 626 if (put_user(snd_emu10k1_efx_read(emu, pc + 1), 627 (__user u32 *)&icode->code[pc + 1])) 628 return -EFAULT; 629 } 630 return 0; 631 } 632 633 static struct snd_emu10k1_fx8010_ctl * 634 snd_emu10k1_look_for_ctl(struct snd_emu10k1 *emu, 635 struct emu10k1_ctl_elem_id *_id) 636 { 637 struct snd_ctl_elem_id *id = (struct snd_ctl_elem_id *)_id; 638 struct snd_emu10k1_fx8010_ctl *ctl; 639 struct snd_kcontrol *kcontrol; 640 641 list_for_each_entry(ctl, &emu->fx8010.gpr_ctl, list) { 642 kcontrol = ctl->kcontrol; 643 if (kcontrol->id.iface == id->iface && 644 kcontrol->id.index == id->index && 645 !strcmp(kcontrol->id.name, id->name)) 646 return ctl; 647 } 648 return NULL; 649 } 650 651 #define MAX_TLV_SIZE 256 652 653 static unsigned int *copy_tlv(const unsigned int __user *_tlv, bool in_kernel) 654 { 655 unsigned int data[2]; 656 unsigned int *tlv; 657 658 if (!_tlv) 659 return NULL; 660 if (in_kernel) 661 memcpy(data, (__force void *)_tlv, sizeof(data)); 662 else if (copy_from_user(data, _tlv, sizeof(data))) 663 return NULL; 664 if (data[1] >= MAX_TLV_SIZE) 665 return NULL; 666 tlv = kmalloc(data[1] + sizeof(data), GFP_KERNEL); 667 if (!tlv) 668 return NULL; 669 memcpy(tlv, data, sizeof(data)); 670 if (in_kernel) { 671 memcpy(tlv + 2, (__force void *)(_tlv + 2), data[1]); 672 } else if (copy_from_user(tlv + 2, _tlv + 2, data[1])) { 673 kfree(tlv); 674 return NULL; 675 } 676 return tlv; 677 } 678 679 static int copy_gctl(struct snd_emu10k1 *emu, 680 struct snd_emu10k1_fx8010_control_gpr *dst, 681 struct snd_emu10k1_fx8010_control_gpr *src, 682 int idx, bool in_kernel) 683 { 684 struct snd_emu10k1_fx8010_control_gpr __user *_src; 685 struct snd_emu10k1_fx8010_control_old_gpr *octl; 686 struct snd_emu10k1_fx8010_control_old_gpr __user *_octl; 687 688 _src = (struct snd_emu10k1_fx8010_control_gpr __user *)src; 689 if (emu->support_tlv) { 690 if (in_kernel) 691 *dst = src[idx]; 692 else if (copy_from_user(dst, &_src[idx], sizeof(*src))) 693 return -EFAULT; 694 return 0; 695 } 696 697 octl = (struct snd_emu10k1_fx8010_control_old_gpr *)src; 698 _octl = (struct snd_emu10k1_fx8010_control_old_gpr __user *)octl; 699 if (in_kernel) 700 memcpy(dst, &octl[idx], sizeof(*octl)); 701 else if (copy_from_user(dst, &_octl[idx], sizeof(*octl))) 702 return -EFAULT; 703 dst->tlv = NULL; 704 return 0; 705 } 706 707 static int copy_gctl_to_user(struct snd_emu10k1 *emu, 708 struct snd_emu10k1_fx8010_control_gpr *dst, 709 struct snd_emu10k1_fx8010_control_gpr *src, 710 int idx) 711 { 712 struct snd_emu10k1_fx8010_control_gpr __user *_dst; 713 struct snd_emu10k1_fx8010_control_old_gpr __user *octl; 714 715 _dst = (struct snd_emu10k1_fx8010_control_gpr __user *)dst; 716 if (emu->support_tlv) 717 return copy_to_user(&_dst[idx], src, sizeof(*src)); 718 719 octl = (struct snd_emu10k1_fx8010_control_old_gpr __user *)dst; 720 return copy_to_user(&octl[idx], src, sizeof(*octl)); 721 } 722 723 static int copy_ctl_elem_id(const struct emu10k1_ctl_elem_id *list, int i, 724 struct emu10k1_ctl_elem_id *ret, bool in_kernel) 725 { 726 struct emu10k1_ctl_elem_id __user *_id = 727 (struct emu10k1_ctl_elem_id __user *)&list[i]; 728 729 if (in_kernel) 730 *ret = list[i]; 731 else if (copy_from_user(ret, _id, sizeof(*ret))) 732 return -EFAULT; 733 return 0; 734 } 735 736 static int snd_emu10k1_verify_controls(struct snd_emu10k1 *emu, 737 struct snd_emu10k1_fx8010_code *icode, 738 bool in_kernel) 739 { 740 unsigned int i; 741 struct emu10k1_ctl_elem_id id; 742 struct snd_emu10k1_fx8010_control_gpr *gctl; 743 struct snd_ctl_elem_id *gctl_id; 744 int err; 745 746 for (i = 0; i < icode->gpr_del_control_count; i++) { 747 err = copy_ctl_elem_id(icode->gpr_del_controls, i, &id, 748 in_kernel); 749 if (err < 0) 750 return err; 751 if (snd_emu10k1_look_for_ctl(emu, &id) == NULL) 752 return -ENOENT; 753 } 754 gctl = kmalloc(sizeof(*gctl), GFP_KERNEL); 755 if (! gctl) 756 return -ENOMEM; 757 err = 0; 758 for (i = 0; i < icode->gpr_add_control_count; i++) { 759 if (copy_gctl(emu, gctl, icode->gpr_add_controls, i, 760 in_kernel)) { 761 err = -EFAULT; 762 goto __error; 763 } 764 if (snd_emu10k1_look_for_ctl(emu, &gctl->id)) 765 continue; 766 gctl_id = (struct snd_ctl_elem_id *)&gctl->id; 767 down_read(&emu->card->controls_rwsem); 768 if (snd_ctl_find_id(emu->card, gctl_id)) { 769 up_read(&emu->card->controls_rwsem); 770 err = -EEXIST; 771 goto __error; 772 } 773 up_read(&emu->card->controls_rwsem); 774 if (gctl_id->iface != SNDRV_CTL_ELEM_IFACE_MIXER && 775 gctl_id->iface != SNDRV_CTL_ELEM_IFACE_PCM) { 776 err = -EINVAL; 777 goto __error; 778 } 779 switch (gctl->translation) { 780 case EMU10K1_GPR_TRANSLATION_NONE: 781 case EMU10K1_GPR_TRANSLATION_NEGATE: 782 break; 783 case EMU10K1_GPR_TRANSLATION_TABLE100: 784 case EMU10K1_GPR_TRANSLATION_NEG_TABLE100: 785 if (gctl->min != 0 || gctl->max != 100) { 786 err = -EINVAL; 787 goto __error; 788 } 789 break; 790 case EMU10K1_GPR_TRANSLATION_BASS: 791 case EMU10K1_GPR_TRANSLATION_TREBLE: 792 if (gctl->min != 0 || gctl->max != 40) { 793 err = -EINVAL; 794 goto __error; 795 } 796 break; 797 case EMU10K1_GPR_TRANSLATION_ONOFF: 798 if (gctl->min != 0 || gctl->max != 1) { 799 err = -EINVAL; 800 goto __error; 801 } 802 break; 803 default: 804 err = -EINVAL; 805 goto __error; 806 } 807 } 808 for (i = 0; i < icode->gpr_list_control_count; i++) { 809 /* FIXME: we need to check the WRITE access */ 810 if (copy_gctl(emu, gctl, icode->gpr_list_controls, i, 811 in_kernel)) { 812 err = -EFAULT; 813 goto __error; 814 } 815 } 816 __error: 817 kfree(gctl); 818 return err; 819 } 820 821 static void snd_emu10k1_ctl_private_free(struct snd_kcontrol *kctl) 822 { 823 struct snd_emu10k1_fx8010_ctl *ctl; 824 825 ctl = (struct snd_emu10k1_fx8010_ctl *) kctl->private_value; 826 kctl->private_value = 0; 827 list_del(&ctl->list); 828 kfree(ctl); 829 kfree(kctl->tlv.p); 830 } 831 832 static int snd_emu10k1_add_controls(struct snd_emu10k1 *emu, 833 struct snd_emu10k1_fx8010_code *icode, 834 bool in_kernel) 835 { 836 unsigned int i, j; 837 struct snd_emu10k1_fx8010_control_gpr *gctl; 838 struct snd_ctl_elem_id *gctl_id; 839 struct snd_emu10k1_fx8010_ctl *ctl, *nctl; 840 struct snd_kcontrol_new knew; 841 struct snd_kcontrol *kctl; 842 struct snd_ctl_elem_value *val; 843 int err = 0; 844 845 val = kmalloc(sizeof(*val), GFP_KERNEL); 846 gctl = kmalloc(sizeof(*gctl), GFP_KERNEL); 847 nctl = kmalloc(sizeof(*nctl), GFP_KERNEL); 848 if (!val || !gctl || !nctl) { 849 err = -ENOMEM; 850 goto __error; 851 } 852 853 for (i = 0; i < icode->gpr_add_control_count; i++) { 854 if (copy_gctl(emu, gctl, icode->gpr_add_controls, i, 855 in_kernel)) { 856 err = -EFAULT; 857 goto __error; 858 } 859 gctl_id = (struct snd_ctl_elem_id *)&gctl->id; 860 if (gctl_id->iface != SNDRV_CTL_ELEM_IFACE_MIXER && 861 gctl_id->iface != SNDRV_CTL_ELEM_IFACE_PCM) { 862 err = -EINVAL; 863 goto __error; 864 } 865 if (!*gctl_id->name) { 866 err = -EINVAL; 867 goto __error; 868 } 869 ctl = snd_emu10k1_look_for_ctl(emu, &gctl->id); 870 memset(&knew, 0, sizeof(knew)); 871 knew.iface = gctl_id->iface; 872 knew.name = gctl_id->name; 873 knew.index = gctl_id->index; 874 knew.device = gctl_id->device; 875 knew.subdevice = gctl_id->subdevice; 876 knew.info = snd_emu10k1_gpr_ctl_info; 877 knew.tlv.p = copy_tlv((const unsigned int __user *)gctl->tlv, in_kernel); 878 if (knew.tlv.p) 879 knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE | 880 SNDRV_CTL_ELEM_ACCESS_TLV_READ; 881 knew.get = snd_emu10k1_gpr_ctl_get; 882 knew.put = snd_emu10k1_gpr_ctl_put; 883 memset(nctl, 0, sizeof(*nctl)); 884 nctl->vcount = gctl->vcount; 885 nctl->count = gctl->count; 886 for (j = 0; j < 32; j++) { 887 nctl->gpr[j] = gctl->gpr[j]; 888 nctl->value[j] = ~gctl->value[j]; /* inverted, we want to write new value in gpr_ctl_put() */ 889 val->value.integer.value[j] = gctl->value[j]; 890 } 891 nctl->min = gctl->min; 892 nctl->max = gctl->max; 893 nctl->translation = gctl->translation; 894 if (ctl == NULL) { 895 ctl = kmalloc(sizeof(*ctl), GFP_KERNEL); 896 if (ctl == NULL) { 897 err = -ENOMEM; 898 kfree(knew.tlv.p); 899 goto __error; 900 } 901 knew.private_value = (unsigned long)ctl; 902 *ctl = *nctl; 903 kctl = snd_ctl_new1(&knew, emu); 904 err = snd_ctl_add(emu->card, kctl); 905 if (err < 0) { 906 kfree(ctl); 907 kfree(knew.tlv.p); 908 goto __error; 909 } 910 kctl->private_free = snd_emu10k1_ctl_private_free; 911 ctl->kcontrol = kctl; 912 list_add_tail(&ctl->list, &emu->fx8010.gpr_ctl); 913 } else { 914 /* overwrite */ 915 nctl->list = ctl->list; 916 nctl->kcontrol = ctl->kcontrol; 917 *ctl = *nctl; 918 snd_ctl_notify(emu->card, SNDRV_CTL_EVENT_MASK_VALUE | 919 SNDRV_CTL_EVENT_MASK_INFO, &ctl->kcontrol->id); 920 } 921 snd_emu10k1_gpr_ctl_put(ctl->kcontrol, val); 922 } 923 __error: 924 kfree(nctl); 925 kfree(gctl); 926 kfree(val); 927 return err; 928 } 929 930 static int snd_emu10k1_del_controls(struct snd_emu10k1 *emu, 931 struct snd_emu10k1_fx8010_code *icode, 932 bool in_kernel) 933 { 934 unsigned int i; 935 struct emu10k1_ctl_elem_id id; 936 struct snd_emu10k1_fx8010_ctl *ctl; 937 struct snd_card *card = emu->card; 938 int err; 939 940 for (i = 0; i < icode->gpr_del_control_count; i++) { 941 err = copy_ctl_elem_id(icode->gpr_del_controls, i, &id, 942 in_kernel); 943 if (err < 0) 944 return err; 945 down_write(&card->controls_rwsem); 946 ctl = snd_emu10k1_look_for_ctl(emu, &id); 947 if (ctl) 948 snd_ctl_remove(card, ctl->kcontrol); 949 up_write(&card->controls_rwsem); 950 } 951 return 0; 952 } 953 954 static int snd_emu10k1_list_controls(struct snd_emu10k1 *emu, 955 struct snd_emu10k1_fx8010_code *icode) 956 { 957 unsigned int i = 0, j; 958 unsigned int total = 0; 959 struct snd_emu10k1_fx8010_control_gpr *gctl; 960 struct snd_emu10k1_fx8010_ctl *ctl; 961 struct snd_ctl_elem_id *id; 962 963 gctl = kmalloc(sizeof(*gctl), GFP_KERNEL); 964 if (! gctl) 965 return -ENOMEM; 966 967 list_for_each_entry(ctl, &emu->fx8010.gpr_ctl, list) { 968 total++; 969 if (icode->gpr_list_controls && 970 i < icode->gpr_list_control_count) { 971 memset(gctl, 0, sizeof(*gctl)); 972 id = &ctl->kcontrol->id; 973 gctl->id.iface = (__force int)id->iface; 974 strscpy(gctl->id.name, id->name, sizeof(gctl->id.name)); 975 gctl->id.index = id->index; 976 gctl->id.device = id->device; 977 gctl->id.subdevice = id->subdevice; 978 gctl->vcount = ctl->vcount; 979 gctl->count = ctl->count; 980 for (j = 0; j < 32; j++) { 981 gctl->gpr[j] = ctl->gpr[j]; 982 gctl->value[j] = ctl->value[j]; 983 } 984 gctl->min = ctl->min; 985 gctl->max = ctl->max; 986 gctl->translation = ctl->translation; 987 if (copy_gctl_to_user(emu, icode->gpr_list_controls, 988 gctl, i)) { 989 kfree(gctl); 990 return -EFAULT; 991 } 992 i++; 993 } 994 } 995 icode->gpr_list_control_total = total; 996 kfree(gctl); 997 return 0; 998 } 999 1000 static int snd_emu10k1_icode_poke(struct snd_emu10k1 *emu, 1001 struct snd_emu10k1_fx8010_code *icode, 1002 bool in_kernel) 1003 { 1004 int err = 0; 1005 1006 mutex_lock(&emu->fx8010.lock); 1007 err = snd_emu10k1_verify_controls(emu, icode, in_kernel); 1008 if (err < 0) 1009 goto __error; 1010 strscpy(emu->fx8010.name, icode->name, sizeof(emu->fx8010.name)); 1011 /* stop FX processor - this may be dangerous, but it's better to miss 1012 some samples than generate wrong ones - [jk] */ 1013 if (emu->audigy) 1014 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg | A_DBG_SINGLE_STEP); 1015 else 1016 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg | EMU10K1_DBG_SINGLE_STEP); 1017 /* ok, do the main job */ 1018 err = snd_emu10k1_del_controls(emu, icode, in_kernel); 1019 if (err < 0) 1020 goto __error; 1021 err = snd_emu10k1_gpr_poke(emu, icode, in_kernel); 1022 if (err < 0) 1023 goto __error; 1024 err = snd_emu10k1_tram_poke(emu, icode, in_kernel); 1025 if (err < 0) 1026 goto __error; 1027 err = snd_emu10k1_code_poke(emu, icode, in_kernel); 1028 if (err < 0) 1029 goto __error; 1030 err = snd_emu10k1_add_controls(emu, icode, in_kernel); 1031 if (err < 0) 1032 goto __error; 1033 /* start FX processor when the DSP code is updated */ 1034 if (emu->audigy) 1035 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg); 1036 else 1037 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg); 1038 __error: 1039 mutex_unlock(&emu->fx8010.lock); 1040 return err; 1041 } 1042 1043 static int snd_emu10k1_icode_peek(struct snd_emu10k1 *emu, 1044 struct snd_emu10k1_fx8010_code *icode) 1045 { 1046 int err; 1047 1048 mutex_lock(&emu->fx8010.lock); 1049 strscpy(icode->name, emu->fx8010.name, sizeof(icode->name)); 1050 /* ok, do the main job */ 1051 err = snd_emu10k1_gpr_peek(emu, icode); 1052 if (err >= 0) 1053 err = snd_emu10k1_tram_peek(emu, icode); 1054 if (err >= 0) 1055 err = snd_emu10k1_code_peek(emu, icode); 1056 if (err >= 0) 1057 err = snd_emu10k1_list_controls(emu, icode); 1058 mutex_unlock(&emu->fx8010.lock); 1059 return err; 1060 } 1061 1062 static int snd_emu10k1_ipcm_poke(struct snd_emu10k1 *emu, 1063 struct snd_emu10k1_fx8010_pcm_rec *ipcm) 1064 { 1065 unsigned int i; 1066 int err = 0; 1067 struct snd_emu10k1_fx8010_pcm *pcm; 1068 1069 if (ipcm->substream >= EMU10K1_FX8010_PCM_COUNT) 1070 return -EINVAL; 1071 ipcm->substream = array_index_nospec(ipcm->substream, 1072 EMU10K1_FX8010_PCM_COUNT); 1073 if (ipcm->channels > 32) 1074 return -EINVAL; 1075 pcm = &emu->fx8010.pcm[ipcm->substream]; 1076 mutex_lock(&emu->fx8010.lock); 1077 spin_lock_irq(&emu->reg_lock); 1078 if (pcm->opened) { 1079 err = -EBUSY; 1080 goto __error; 1081 } 1082 if (ipcm->channels == 0) { /* remove */ 1083 pcm->valid = 0; 1084 } else { 1085 /* FIXME: we need to add universal code to the PCM transfer routine */ 1086 if (ipcm->channels != 2) { 1087 err = -EINVAL; 1088 goto __error; 1089 } 1090 pcm->valid = 1; 1091 pcm->opened = 0; 1092 pcm->channels = ipcm->channels; 1093 pcm->tram_start = ipcm->tram_start; 1094 pcm->buffer_size = ipcm->buffer_size; 1095 pcm->gpr_size = ipcm->gpr_size; 1096 pcm->gpr_count = ipcm->gpr_count; 1097 pcm->gpr_tmpcount = ipcm->gpr_tmpcount; 1098 pcm->gpr_ptr = ipcm->gpr_ptr; 1099 pcm->gpr_trigger = ipcm->gpr_trigger; 1100 pcm->gpr_running = ipcm->gpr_running; 1101 for (i = 0; i < pcm->channels; i++) 1102 pcm->etram[i] = ipcm->etram[i]; 1103 } 1104 __error: 1105 spin_unlock_irq(&emu->reg_lock); 1106 mutex_unlock(&emu->fx8010.lock); 1107 return err; 1108 } 1109 1110 static int snd_emu10k1_ipcm_peek(struct snd_emu10k1 *emu, 1111 struct snd_emu10k1_fx8010_pcm_rec *ipcm) 1112 { 1113 unsigned int i; 1114 int err = 0; 1115 struct snd_emu10k1_fx8010_pcm *pcm; 1116 1117 if (ipcm->substream >= EMU10K1_FX8010_PCM_COUNT) 1118 return -EINVAL; 1119 ipcm->substream = array_index_nospec(ipcm->substream, 1120 EMU10K1_FX8010_PCM_COUNT); 1121 pcm = &emu->fx8010.pcm[ipcm->substream]; 1122 mutex_lock(&emu->fx8010.lock); 1123 spin_lock_irq(&emu->reg_lock); 1124 ipcm->channels = pcm->channels; 1125 ipcm->tram_start = pcm->tram_start; 1126 ipcm->buffer_size = pcm->buffer_size; 1127 ipcm->gpr_size = pcm->gpr_size; 1128 ipcm->gpr_ptr = pcm->gpr_ptr; 1129 ipcm->gpr_count = pcm->gpr_count; 1130 ipcm->gpr_tmpcount = pcm->gpr_tmpcount; 1131 ipcm->gpr_trigger = pcm->gpr_trigger; 1132 ipcm->gpr_running = pcm->gpr_running; 1133 for (i = 0; i < pcm->channels; i++) 1134 ipcm->etram[i] = pcm->etram[i]; 1135 ipcm->res1 = ipcm->res2 = 0; 1136 ipcm->pad = 0; 1137 spin_unlock_irq(&emu->reg_lock); 1138 mutex_unlock(&emu->fx8010.lock); 1139 return err; 1140 } 1141 1142 #define SND_EMU10K1_GPR_CONTROLS 44 1143 #define SND_EMU10K1_INPUTS 12 1144 #define SND_EMU10K1_PLAYBACK_CHANNELS 8 1145 #define SND_EMU10K1_CAPTURE_CHANNELS 4 1146 1147 #define HR_VAL(v) ((v) * 0x80000000LL / 100 - 1) 1148 1149 static void 1150 snd_emu10k1_init_mono_control2(struct snd_emu10k1_fx8010_control_gpr *ctl, 1151 const char *name, int gpr, int defval, int defval_hr) 1152 { 1153 ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER; 1154 strcpy(ctl->id.name, name); 1155 ctl->vcount = ctl->count = 1; 1156 if (high_res_gpr_volume) { 1157 ctl->min = -1; 1158 ctl->max = 0x7fffffff; 1159 ctl->tlv = snd_emu10k1_db_linear; 1160 ctl->translation = EMU10K1_GPR_TRANSLATION_NEGATE; 1161 defval = defval_hr; 1162 } else { 1163 ctl->min = 0; 1164 ctl->max = 100; 1165 ctl->tlv = snd_emu10k1_db_scale1; 1166 ctl->translation = EMU10K1_GPR_TRANSLATION_NEG_TABLE100; 1167 } 1168 ctl->gpr[0] = gpr + 0; ctl->value[0] = defval; 1169 } 1170 #define snd_emu10k1_init_mono_control(ctl, name, gpr, defval) \ 1171 snd_emu10k1_init_mono_control2(ctl, name, gpr, defval, HR_VAL(defval)) 1172 1173 static void 1174 snd_emu10k1_init_stereo_control2(struct snd_emu10k1_fx8010_control_gpr *ctl, 1175 const char *name, int gpr, int defval, int defval_hr) 1176 { 1177 ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER; 1178 strcpy(ctl->id.name, name); 1179 ctl->vcount = ctl->count = 2; 1180 if (high_res_gpr_volume) { 1181 ctl->min = -1; 1182 ctl->max = 0x7fffffff; 1183 ctl->tlv = snd_emu10k1_db_linear; 1184 ctl->translation = EMU10K1_GPR_TRANSLATION_NEGATE; 1185 defval = defval_hr; 1186 } else { 1187 ctl->min = 0; 1188 ctl->max = 100; 1189 ctl->tlv = snd_emu10k1_db_scale1; 1190 ctl->translation = EMU10K1_GPR_TRANSLATION_NEG_TABLE100; 1191 } 1192 ctl->gpr[0] = gpr + 0; ctl->value[0] = defval; 1193 ctl->gpr[1] = gpr + 1; ctl->value[1] = defval; 1194 } 1195 #define snd_emu10k1_init_stereo_control(ctl, name, gpr, defval) \ 1196 snd_emu10k1_init_stereo_control2(ctl, name, gpr, defval, HR_VAL(defval)) 1197 1198 static void 1199 snd_emu10k1_init_mono_onoff_control(struct snd_emu10k1_fx8010_control_gpr *ctl, 1200 const char *name, int gpr, int defval) 1201 { 1202 ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER; 1203 strcpy(ctl->id.name, name); 1204 ctl->vcount = ctl->count = 1; 1205 ctl->gpr[0] = gpr + 0; ctl->value[0] = defval; 1206 ctl->min = 0; 1207 ctl->max = 1; 1208 ctl->translation = EMU10K1_GPR_TRANSLATION_ONOFF; 1209 } 1210 1211 static void 1212 snd_emu10k1_init_stereo_onoff_control(struct snd_emu10k1_fx8010_control_gpr *ctl, 1213 const char *name, int gpr, int defval) 1214 { 1215 ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER; 1216 strcpy(ctl->id.name, name); 1217 ctl->vcount = ctl->count = 2; 1218 ctl->gpr[0] = gpr + 0; ctl->value[0] = defval; 1219 ctl->gpr[1] = gpr + 1; ctl->value[1] = defval; 1220 ctl->min = 0; 1221 ctl->max = 1; 1222 ctl->translation = EMU10K1_GPR_TRANSLATION_ONOFF; 1223 } 1224 1225 /* 1226 * Used for emu1010 - conversion from 32-bit capture inputs from the FPGA 1227 * to 2 x 16-bit registers in Audigy - their values are read via DMA. 1228 * Conversion is performed by Audigy DSP instructions of FX8010. 1229 */ 1230 static void snd_emu10k1_audigy_dsp_convert_32_to_2x16( 1231 struct snd_emu10k1_fx8010_code *icode, 1232 u32 *ptr, int tmp, int bit_shifter16, 1233 int reg_in, int reg_out) 1234 { 1235 // This leaves the low word in place, which is fine, 1236 // as the low bits are completely ignored subsequently. 1237 // reg_out[1] = reg_in 1238 A_OP(icode, ptr, iACC3, reg_out + 1, reg_in, A_C_00000000, A_C_00000000); 1239 // It is fine to read reg_in multiple times. 1240 // tmp = reg_in << 15 1241 A_OP(icode, ptr, iMACINT1, A_GPR(tmp), A_C_00000000, reg_in, A_GPR(bit_shifter16)); 1242 // Left-shift once more. This is a separate step, as the 1243 // signed multiplication would clobber the MSB. 1244 // reg_out[0] = tmp + ((tmp << 31) >> 31) 1245 A_OP(icode, ptr, iMAC3, reg_out, A_GPR(tmp), A_GPR(tmp), A_C_80000000); 1246 } 1247 1248 #define ENUM_GPR(name, size) name, name ## _dummy = name + (size) - 1 1249 1250 /* 1251 * initial DSP configuration for Audigy 1252 */ 1253 1254 static int _snd_emu10k1_audigy_init_efx(struct snd_emu10k1 *emu) 1255 { 1256 int err, z, nctl; 1257 enum { 1258 ENUM_GPR(playback, SND_EMU10K1_PLAYBACK_CHANNELS), 1259 ENUM_GPR(stereo_mix, 2), 1260 ENUM_GPR(capture, 2), 1261 ENUM_GPR(bit_shifter16, 1), 1262 // The fixed allocation of these breaks the pattern, but why not. 1263 // Splitting these into left/right is questionable, as it will break 1264 // down for center/lfe. But it works for stereo/quadro, so whatever. 1265 ENUM_GPR(bass_gpr, 2 * 5), // two sides, five coefficients 1266 ENUM_GPR(treble_gpr, 2 * 5), 1267 ENUM_GPR(bass_tmp, SND_EMU10K1_PLAYBACK_CHANNELS * 4), // four delay stages 1268 ENUM_GPR(treble_tmp, SND_EMU10K1_PLAYBACK_CHANNELS * 4), 1269 ENUM_GPR(tmp, 3), 1270 num_static_gprs 1271 }; 1272 int gpr = num_static_gprs; 1273 u32 ptr, ptr_skip; 1274 struct snd_emu10k1_fx8010_code *icode = NULL; 1275 struct snd_emu10k1_fx8010_control_gpr *controls = NULL, *ctl; 1276 u32 *gpr_map; 1277 1278 err = -ENOMEM; 1279 icode = kzalloc(sizeof(*icode), GFP_KERNEL); 1280 if (!icode) 1281 return err; 1282 1283 icode->gpr_map = kcalloc(512 + 256 + 256 + 2 * 1024, 1284 sizeof(u_int32_t), GFP_KERNEL); 1285 if (!icode->gpr_map) 1286 goto __err_gpr; 1287 controls = kcalloc(SND_EMU10K1_GPR_CONTROLS, 1288 sizeof(*controls), GFP_KERNEL); 1289 if (!controls) 1290 goto __err_ctrls; 1291 1292 gpr_map = icode->gpr_map; 1293 1294 icode->tram_data_map = icode->gpr_map + 512; 1295 icode->tram_addr_map = icode->tram_data_map + 256; 1296 icode->code = icode->tram_addr_map + 256; 1297 1298 /* clear free GPRs */ 1299 memset(icode->gpr_valid, 0xff, 512 / 8); 1300 1301 /* clear TRAM data & address lines */ 1302 memset(icode->tram_valid, 0xff, 256 / 8); 1303 1304 strcpy(icode->name, "Audigy DSP code for ALSA"); 1305 ptr = 0; 1306 nctl = 0; 1307 gpr_map[bit_shifter16] = 0x00008000; 1308 1309 #if 1 1310 /* PCM front Playback Volume (independent from stereo mix) 1311 * playback = -gpr * FXBUS_PCM_LEFT_FRONT >> 31 1312 * where gpr contains negated attenuation from corresponding mixer control 1313 * (snd_emu10k1_init_stereo_control) 1314 */ 1315 A_OP(icode, &ptr, iMAC1, A_GPR(playback), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT_FRONT)); 1316 A_OP(icode, &ptr, iMAC1, A_GPR(playback+1), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT_FRONT)); 1317 snd_emu10k1_init_stereo_control(&controls[nctl++], "PCM Front Playback Volume", gpr, 100); 1318 gpr += 2; 1319 1320 /* PCM Surround Playback (independent from stereo mix) */ 1321 A_OP(icode, &ptr, iMAC1, A_GPR(playback+2), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT_REAR)); 1322 A_OP(icode, &ptr, iMAC1, A_GPR(playback+3), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT_REAR)); 1323 snd_emu10k1_init_stereo_control(&controls[nctl++], "PCM Surround Playback Volume", gpr, 100); 1324 gpr += 2; 1325 1326 /* PCM Side Playback (independent from stereo mix) */ 1327 if (emu->card_capabilities->spk71) { 1328 A_OP(icode, &ptr, iMAC1, A_GPR(playback+6), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT_SIDE)); 1329 A_OP(icode, &ptr, iMAC1, A_GPR(playback+7), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT_SIDE)); 1330 snd_emu10k1_init_stereo_control(&controls[nctl++], "PCM Side Playback Volume", gpr, 100); 1331 gpr += 2; 1332 } 1333 1334 /* PCM Center Playback (independent from stereo mix) */ 1335 A_OP(icode, &ptr, iMAC1, A_GPR(playback+4), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_CENTER)); 1336 snd_emu10k1_init_mono_control(&controls[nctl++], "PCM Center Playback Volume", gpr, 100); 1337 gpr++; 1338 1339 /* PCM LFE Playback (independent from stereo mix) */ 1340 A_OP(icode, &ptr, iMAC1, A_GPR(playback+5), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LFE)); 1341 snd_emu10k1_init_mono_control(&controls[nctl++], "PCM LFE Playback Volume", gpr, 100); 1342 gpr++; 1343 1344 /* 1345 * Stereo Mix 1346 */ 1347 /* Wave (PCM) Playback Volume (will be renamed later) */ 1348 A_OP(icode, &ptr, iMAC1, A_GPR(stereo_mix), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT)); 1349 A_OP(icode, &ptr, iMAC1, A_GPR(stereo_mix+1), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT)); 1350 snd_emu10k1_init_stereo_control(&controls[nctl++], "Wave Playback Volume", gpr, 100); 1351 gpr += 2; 1352 1353 /* Synth Playback */ 1354 A_OP(icode, &ptr, iMAC1, A_GPR(stereo_mix+0), A_GPR(stereo_mix+0), A_GPR(gpr), A_FXBUS(FXBUS_MIDI_LEFT)); 1355 A_OP(icode, &ptr, iMAC1, A_GPR(stereo_mix+1), A_GPR(stereo_mix+1), A_GPR(gpr+1), A_FXBUS(FXBUS_MIDI_RIGHT)); 1356 snd_emu10k1_init_stereo_control(&controls[nctl++], "Synth Playback Volume", gpr, 100); 1357 gpr += 2; 1358 1359 /* Wave (PCM) Capture */ 1360 A_OP(icode, &ptr, iMAC1, A_GPR(capture+0), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT)); 1361 A_OP(icode, &ptr, iMAC1, A_GPR(capture+1), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT)); 1362 snd_emu10k1_init_stereo_control(&controls[nctl++], "PCM Capture Volume", gpr, 0); 1363 gpr += 2; 1364 1365 /* Synth Capture */ 1366 A_OP(icode, &ptr, iMAC1, A_GPR(capture+0), A_GPR(capture+0), A_GPR(gpr), A_FXBUS(FXBUS_MIDI_LEFT)); 1367 A_OP(icode, &ptr, iMAC1, A_GPR(capture+1), A_GPR(capture+1), A_GPR(gpr+1), A_FXBUS(FXBUS_MIDI_RIGHT)); 1368 snd_emu10k1_init_stereo_control(&controls[nctl++], "Synth Capture Volume", gpr, 0); 1369 gpr += 2; 1370 1371 // We need to double the volume, as we configure the voices for half volume, 1372 // which is necessary for bit-identical reproduction. 1373 { static_assert(stereo_mix == playback + SND_EMU10K1_PLAYBACK_CHANNELS); } 1374 for (z = 0; z < SND_EMU10K1_PLAYBACK_CHANNELS + 2; z++) 1375 A_OP(icode, &ptr, iACC3, A_GPR(playback + z), A_GPR(playback + z), A_GPR(playback + z), A_C_00000000); 1376 1377 /* 1378 * inputs 1379 */ 1380 #define A_ADD_VOLUME_IN(var,vol,input) \ 1381 A_OP(icode, &ptr, iMAC1, A_GPR(var), A_GPR(var), A_GPR(vol), A_EXTIN(input)) 1382 1383 if (emu->card_capabilities->emu_model) { 1384 /* EMU1010 DSP 0 and DSP 1 Capture */ 1385 // The 24 MSB hold the actual value. We implicitly discard the 16 LSB. 1386 if (emu->card_capabilities->ca0108_chip) { 1387 // For unclear reasons, the EMU32IN cannot be the Y operand! 1388 A_OP(icode, &ptr, iMAC1, A_GPR(capture+0), A_GPR(capture+0), A3_EMU32IN(0x0), A_GPR(gpr)); 1389 // A3_EMU32IN(0) is delayed by one sample, so all other A3_EMU32IN channels 1390 // need to be delayed as well; we use an auxiliary register for that. 1391 A_OP(icode, &ptr, iMAC1, A_GPR(capture+1), A_GPR(capture+1), A_GPR(gpr+2), A_GPR(gpr+1)); 1392 A_OP(icode, &ptr, iACC3, A_GPR(gpr+2), A3_EMU32IN(0x1), A_C_00000000, A_C_00000000); 1393 } else { 1394 A_OP(icode, &ptr, iMAC1, A_GPR(capture+0), A_GPR(capture+0), A_P16VIN(0x0), A_GPR(gpr)); 1395 // A_P16VIN(0) is delayed by one sample, so all other A_P16VIN channels 1396 // need to be delayed as well; we use an auxiliary register for that. 1397 A_OP(icode, &ptr, iMAC1, A_GPR(capture+1), A_GPR(capture+1), A_GPR(gpr+2), A_GPR(gpr+1)); 1398 A_OP(icode, &ptr, iACC3, A_GPR(gpr+2), A_P16VIN(0x1), A_C_00000000, A_C_00000000); 1399 } 1400 snd_emu10k1_init_stereo_control(&controls[nctl++], "EMU Capture Volume", gpr, 0); 1401 gpr_map[gpr + 2] = 0x00000000; 1402 gpr += 3; 1403 } else { 1404 if (emu->card_capabilities->ac97_chip) { 1405 /* AC'97 Playback Volume - used only for mic (renamed later) */ 1406 A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_AC97_L); 1407 A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_AC97_R); 1408 snd_emu10k1_init_stereo_control(&controls[nctl++], "AMic Playback Volume", gpr, 0); 1409 gpr += 2; 1410 /* AC'97 Capture Volume - used only for mic */ 1411 A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_AC97_L); 1412 A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_AC97_R); 1413 snd_emu10k1_init_stereo_control(&controls[nctl++], "Mic Capture Volume", gpr, 0); 1414 gpr += 2; 1415 1416 /* mic capture buffer */ 1417 A_OP(icode, &ptr, iINTERP, A_EXTOUT(A_EXTOUT_MIC_CAP), A_EXTIN(A_EXTIN_AC97_L), A_C_40000000, A_EXTIN(A_EXTIN_AC97_R)); 1418 } 1419 1420 /* Audigy CD Playback Volume */ 1421 A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_SPDIF_CD_L); 1422 A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_SPDIF_CD_R); 1423 snd_emu10k1_init_stereo_control(&controls[nctl++], 1424 emu->card_capabilities->ac97_chip ? "Audigy CD Playback Volume" : "CD Playback Volume", 1425 gpr, 0); 1426 gpr += 2; 1427 /* Audigy CD Capture Volume */ 1428 A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_SPDIF_CD_L); 1429 A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_SPDIF_CD_R); 1430 snd_emu10k1_init_stereo_control(&controls[nctl++], 1431 emu->card_capabilities->ac97_chip ? "Audigy CD Capture Volume" : "CD Capture Volume", 1432 gpr, 0); 1433 gpr += 2; 1434 1435 /* Optical SPDIF Playback Volume */ 1436 A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_OPT_SPDIF_L); 1437 A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_OPT_SPDIF_R); 1438 snd_emu10k1_init_stereo_control(&controls[nctl++], SNDRV_CTL_NAME_IEC958("Optical ",PLAYBACK,VOLUME), gpr, 0); 1439 gpr += 2; 1440 /* Optical SPDIF Capture Volume */ 1441 A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_OPT_SPDIF_L); 1442 A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_OPT_SPDIF_R); 1443 snd_emu10k1_init_stereo_control(&controls[nctl++], SNDRV_CTL_NAME_IEC958("Optical ",CAPTURE,VOLUME), gpr, 0); 1444 gpr += 2; 1445 1446 /* Line2 Playback Volume */ 1447 A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_LINE2_L); 1448 A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_LINE2_R); 1449 snd_emu10k1_init_stereo_control(&controls[nctl++], 1450 emu->card_capabilities->ac97_chip ? "Line2 Playback Volume" : "Line Playback Volume", 1451 gpr, 0); 1452 gpr += 2; 1453 /* Line2 Capture Volume */ 1454 A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_LINE2_L); 1455 A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_LINE2_R); 1456 snd_emu10k1_init_stereo_control(&controls[nctl++], 1457 emu->card_capabilities->ac97_chip ? "Line2 Capture Volume" : "Line Capture Volume", 1458 gpr, 0); 1459 gpr += 2; 1460 1461 /* Philips ADC Playback Volume */ 1462 A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_ADC_L); 1463 A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_ADC_R); 1464 snd_emu10k1_init_stereo_control(&controls[nctl++], "Analog Mix Playback Volume", gpr, 0); 1465 gpr += 2; 1466 /* Philips ADC Capture Volume */ 1467 A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_ADC_L); 1468 A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_ADC_R); 1469 snd_emu10k1_init_stereo_control(&controls[nctl++], "Analog Mix Capture Volume", gpr, 0); 1470 gpr += 2; 1471 1472 /* Aux2 Playback Volume */ 1473 A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_AUX2_L); 1474 A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_AUX2_R); 1475 snd_emu10k1_init_stereo_control(&controls[nctl++], 1476 emu->card_capabilities->ac97_chip ? "Aux2 Playback Volume" : "Aux Playback Volume", 1477 gpr, 0); 1478 gpr += 2; 1479 /* Aux2 Capture Volume */ 1480 A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_AUX2_L); 1481 A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_AUX2_R); 1482 snd_emu10k1_init_stereo_control(&controls[nctl++], 1483 emu->card_capabilities->ac97_chip ? "Aux2 Capture Volume" : "Aux Capture Volume", 1484 gpr, 0); 1485 gpr += 2; 1486 } 1487 1488 /* Stereo Mix Front Playback Volume */ 1489 A_OP(icode, &ptr, iMAC1, A_GPR(playback), A_GPR(playback), A_GPR(gpr), A_GPR(stereo_mix)); 1490 A_OP(icode, &ptr, iMAC1, A_GPR(playback+1), A_GPR(playback+1), A_GPR(gpr+1), A_GPR(stereo_mix+1)); 1491 snd_emu10k1_init_stereo_control(&controls[nctl++], "Front Playback Volume", gpr, 100); 1492 gpr += 2; 1493 1494 /* Stereo Mix Surround Playback */ 1495 A_OP(icode, &ptr, iMAC1, A_GPR(playback+2), A_GPR(playback+2), A_GPR(gpr), A_GPR(stereo_mix)); 1496 A_OP(icode, &ptr, iMAC1, A_GPR(playback+3), A_GPR(playback+3), A_GPR(gpr+1), A_GPR(stereo_mix+1)); 1497 snd_emu10k1_init_stereo_control(&controls[nctl++], "Surround Playback Volume", gpr, 0); 1498 gpr += 2; 1499 1500 /* Stereo Mix Center Playback */ 1501 /* Center = sub = Left/2 + Right/2 */ 1502 A_OP(icode, &ptr, iINTERP, A_GPR(tmp), A_GPR(stereo_mix), A_C_40000000, A_GPR(stereo_mix+1)); 1503 A_OP(icode, &ptr, iMAC1, A_GPR(playback+4), A_GPR(playback+4), A_GPR(gpr), A_GPR(tmp)); 1504 snd_emu10k1_init_mono_control(&controls[nctl++], "Center Playback Volume", gpr, 0); 1505 gpr++; 1506 1507 /* Stereo Mix LFE Playback */ 1508 A_OP(icode, &ptr, iMAC1, A_GPR(playback+5), A_GPR(playback+5), A_GPR(gpr), A_GPR(tmp)); 1509 snd_emu10k1_init_mono_control(&controls[nctl++], "LFE Playback Volume", gpr, 0); 1510 gpr++; 1511 1512 if (emu->card_capabilities->spk71) { 1513 /* Stereo Mix Side Playback */ 1514 A_OP(icode, &ptr, iMAC1, A_GPR(playback+6), A_GPR(playback+6), A_GPR(gpr), A_GPR(stereo_mix)); 1515 A_OP(icode, &ptr, iMAC1, A_GPR(playback+7), A_GPR(playback+7), A_GPR(gpr+1), A_GPR(stereo_mix+1)); 1516 snd_emu10k1_init_stereo_control(&controls[nctl++], "Side Playback Volume", gpr, 0); 1517 gpr += 2; 1518 } 1519 1520 /* 1521 * outputs 1522 */ 1523 #define A_PUT_OUTPUT(out,src) A_OP(icode, &ptr, iACC3, A_EXTOUT(out), A_C_00000000, A_C_00000000, A_GPR(src)) 1524 #define A_PUT_STEREO_OUTPUT(out1,out2,src) \ 1525 {A_PUT_OUTPUT(out1,src); A_PUT_OUTPUT(out2,src+1);} 1526 1527 #define _A_SWITCH(icode, ptr, dst, src, sw) \ 1528 A_OP((icode), ptr, iMACINT0, dst, A_C_00000000, src, sw); 1529 #define A_SWITCH(icode, ptr, dst, src, sw) \ 1530 _A_SWITCH(icode, ptr, A_GPR(dst), A_GPR(src), A_GPR(sw)) 1531 #define _A_SWITCH_NEG(icode, ptr, dst, src) \ 1532 A_OP((icode), ptr, iANDXOR, dst, src, A_C_00000001, A_C_00000001); 1533 #define A_SWITCH_NEG(icode, ptr, dst, src) \ 1534 _A_SWITCH_NEG(icode, ptr, A_GPR(dst), A_GPR(src)) 1535 1536 1537 /* 1538 * Process tone control 1539 */ 1540 ctl = &controls[nctl + 0]; 1541 ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER; 1542 strcpy(ctl->id.name, "Tone Control - Bass"); 1543 ctl->vcount = 2; 1544 ctl->count = 10; 1545 ctl->min = 0; 1546 ctl->max = 40; 1547 ctl->value[0] = ctl->value[1] = 20; 1548 ctl->translation = EMU10K1_GPR_TRANSLATION_BASS; 1549 ctl = &controls[nctl + 1]; 1550 ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER; 1551 strcpy(ctl->id.name, "Tone Control - Treble"); 1552 ctl->vcount = 2; 1553 ctl->count = 10; 1554 ctl->min = 0; 1555 ctl->max = 40; 1556 ctl->value[0] = ctl->value[1] = 20; 1557 ctl->translation = EMU10K1_GPR_TRANSLATION_TREBLE; 1558 for (z = 0; z < 5; z++) { 1559 int j; 1560 for (j = 0; j < 2; j++) { 1561 controls[nctl + 0].gpr[z * 2 + j] = bass_gpr + z * 2 + j; 1562 controls[nctl + 1].gpr[z * 2 + j] = treble_gpr + z * 2 + j; 1563 } 1564 } 1565 nctl += 2; 1566 1567 A_OP(icode, &ptr, iACC3, A_C_00000000, A_GPR(gpr), A_C_00000000, A_C_00000000); 1568 snd_emu10k1_init_mono_onoff_control(controls + nctl++, "Tone Control - Switch", gpr, 0); 1569 gpr++; 1570 A_OP(icode, &ptr, iSKIP, A_GPR_COND, A_GPR_COND, A_CC_REG_ZERO, A_GPR(gpr)); 1571 ptr_skip = ptr; 1572 for (z = 0; z < 4; z++) { /* front/rear/center-lfe/side */ 1573 int j, k, l, d; 1574 for (j = 0; j < 2; j++) { /* left/right */ 1575 k = bass_tmp + (z * 8) + (j * 4); 1576 l = treble_tmp + (z * 8) + (j * 4); 1577 d = playback + z * 2 + j; 1578 1579 A_OP(icode, &ptr, iMAC0, A_C_00000000, A_C_00000000, A_GPR(d), A_GPR(bass_gpr + 0 + j)); 1580 A_OP(icode, &ptr, iMACMV, A_GPR(k+1), A_GPR(k), A_GPR(k+1), A_GPR(bass_gpr + 4 + j)); 1581 A_OP(icode, &ptr, iMACMV, A_GPR(k), A_GPR(d), A_GPR(k), A_GPR(bass_gpr + 2 + j)); 1582 A_OP(icode, &ptr, iMACMV, A_GPR(k+3), A_GPR(k+2), A_GPR(k+3), A_GPR(bass_gpr + 8 + j)); 1583 A_OP(icode, &ptr, iMAC0, A_GPR(k+2), A_GPR_ACCU, A_GPR(k+2), A_GPR(bass_gpr + 6 + j)); 1584 A_OP(icode, &ptr, iACC3, A_GPR(k+2), A_GPR(k+2), A_GPR(k+2), A_C_00000000); 1585 1586 A_OP(icode, &ptr, iMAC0, A_C_00000000, A_C_00000000, A_GPR(k+2), A_GPR(treble_gpr + 0 + j)); 1587 A_OP(icode, &ptr, iMACMV, A_GPR(l+1), A_GPR(l), A_GPR(l+1), A_GPR(treble_gpr + 4 + j)); 1588 A_OP(icode, &ptr, iMACMV, A_GPR(l), A_GPR(k+2), A_GPR(l), A_GPR(treble_gpr + 2 + j)); 1589 A_OP(icode, &ptr, iMACMV, A_GPR(l+3), A_GPR(l+2), A_GPR(l+3), A_GPR(treble_gpr + 8 + j)); 1590 A_OP(icode, &ptr, iMAC0, A_GPR(l+2), A_GPR_ACCU, A_GPR(l+2), A_GPR(treble_gpr + 6 + j)); 1591 A_OP(icode, &ptr, iMACINT0, A_GPR(l+2), A_C_00000000, A_GPR(l+2), A_C_00000010); 1592 1593 A_OP(icode, &ptr, iACC3, A_GPR(d), A_GPR(l+2), A_C_00000000, A_C_00000000); 1594 1595 if (z == 2) /* center */ 1596 break; 1597 } 1598 } 1599 gpr_map[gpr++] = ptr - ptr_skip; 1600 1601 /* Master volume (will be renamed later) */ 1602 for (z = 0; z < 8; z++) 1603 A_OP(icode, &ptr, iMAC1, A_GPR(playback+z), A_C_00000000, A_GPR(gpr), A_GPR(playback+z)); 1604 snd_emu10k1_init_mono_control(&controls[nctl++], "Wave Master Playback Volume", gpr, 0); 1605 gpr++; 1606 1607 if (emu->card_capabilities->emu_model) { 1608 /* EMU1010 Outputs from PCM Front, Rear, Center, LFE, Side */ 1609 dev_info(emu->card->dev, "EMU outputs on\n"); 1610 for (z = 0; z < 8; z++) { 1611 if (emu->card_capabilities->ca0108_chip) { 1612 A_OP(icode, &ptr, iACC3, A3_EMU32OUT(z), A_GPR(playback + z), A_C_00000000, A_C_00000000); 1613 } else { 1614 A_OP(icode, &ptr, iACC3, A_EMU32OUTL(z), A_GPR(playback + z), A_C_00000000, A_C_00000000); 1615 } 1616 } 1617 } else { 1618 /* analog speakers */ 1619 A_PUT_STEREO_OUTPUT(A_EXTOUT_AFRONT_L, A_EXTOUT_AFRONT_R, playback); 1620 A_PUT_STEREO_OUTPUT(A_EXTOUT_AREAR_L, A_EXTOUT_AREAR_R, playback+2); 1621 A_PUT_OUTPUT(A_EXTOUT_ACENTER, playback+4); 1622 A_PUT_OUTPUT(A_EXTOUT_ALFE, playback+5); 1623 if (emu->card_capabilities->spk71) 1624 A_PUT_STEREO_OUTPUT(A_EXTOUT_ASIDE_L, A_EXTOUT_ASIDE_R, playback+6); 1625 1626 /* headphone */ 1627 A_PUT_STEREO_OUTPUT(A_EXTOUT_HEADPHONE_L, A_EXTOUT_HEADPHONE_R, playback); 1628 1629 /* IEC958 Optical Raw Playback Switch */ 1630 gpr_map[gpr++] = 0; 1631 gpr_map[gpr++] = 0x1008; 1632 gpr_map[gpr++] = 0xffff0000; 1633 for (z = 0; z < 2; z++) { 1634 A_OP(icode, &ptr, iMAC0, A_GPR(tmp + 2), A_FXBUS(FXBUS_PT_LEFT + z), A_C_00000000, A_C_00000000); 1635 A_OP(icode, &ptr, iSKIP, A_GPR_COND, A_GPR_COND, A_GPR(gpr - 2), A_C_00000001); 1636 A_OP(icode, &ptr, iACC3, A_GPR(tmp + 2), A_C_00000000, A_C_00010000, A_GPR(tmp + 2)); 1637 A_OP(icode, &ptr, iANDXOR, A_GPR(tmp + 2), A_GPR(tmp + 2), A_GPR(gpr - 1), A_C_00000000); 1638 A_SWITCH(icode, &ptr, tmp + 0, tmp + 2, gpr + z); 1639 A_SWITCH_NEG(icode, &ptr, tmp + 1, gpr + z); 1640 A_SWITCH(icode, &ptr, tmp + 1, playback + z, tmp + 1); 1641 if ((z==1) && (emu->card_capabilities->spdif_bug)) { 1642 /* Due to a SPDIF output bug on some Audigy cards, this code delays the Right channel by 1 sample */ 1643 dev_info(emu->card->dev, 1644 "Installing spdif_bug patch: %s\n", 1645 emu->card_capabilities->name); 1646 A_OP(icode, &ptr, iACC3, A_EXTOUT(A_EXTOUT_FRONT_L + z), A_GPR(gpr - 3), A_C_00000000, A_C_00000000); 1647 A_OP(icode, &ptr, iACC3, A_GPR(gpr - 3), A_GPR(tmp + 0), A_GPR(tmp + 1), A_C_00000000); 1648 } else { 1649 A_OP(icode, &ptr, iACC3, A_EXTOUT(A_EXTOUT_FRONT_L + z), A_GPR(tmp + 0), A_GPR(tmp + 1), A_C_00000000); 1650 } 1651 } 1652 snd_emu10k1_init_stereo_onoff_control(controls + nctl++, SNDRV_CTL_NAME_IEC958("Optical Raw ",PLAYBACK,SWITCH), gpr, 0); 1653 gpr += 2; 1654 1655 A_PUT_STEREO_OUTPUT(A_EXTOUT_REAR_L, A_EXTOUT_REAR_R, playback+2); 1656 A_PUT_OUTPUT(A_EXTOUT_CENTER, playback+4); 1657 A_PUT_OUTPUT(A_EXTOUT_LFE, playback+5); 1658 } 1659 1660 /* ADC buffer */ 1661 #ifdef EMU10K1_CAPTURE_DIGITAL_OUT 1662 A_PUT_STEREO_OUTPUT(A_EXTOUT_ADC_CAP_L, A_EXTOUT_ADC_CAP_R, playback); 1663 #else 1664 A_PUT_OUTPUT(A_EXTOUT_ADC_CAP_L, capture); 1665 A_PUT_OUTPUT(A_EXTOUT_ADC_CAP_R, capture+1); 1666 #endif 1667 1668 if (emu->card_capabilities->emu_model) { 1669 /* Capture 16 channels of S32_LE sound. */ 1670 if (emu->card_capabilities->ca0108_chip) { 1671 dev_info(emu->card->dev, "EMU2 inputs on\n"); 1672 /* Note that the Tina[2] DSPs have 16 more EMU32 inputs which we don't use. */ 1673 1674 snd_emu10k1_audigy_dsp_convert_32_to_2x16( 1675 icode, &ptr, tmp, bit_shifter16, A3_EMU32IN(0), A_FXBUS2(0)); 1676 // A3_EMU32IN(0) is delayed by one sample, so all other A3_EMU32IN channels 1677 // need to be delayed as well; we use an auxiliary register for that. 1678 for (z = 1; z < 0x10; z++) { 1679 snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, 1680 bit_shifter16, 1681 A_GPR(gpr), 1682 A_FXBUS2(z*2) ); 1683 A_OP(icode, &ptr, iACC3, A_GPR(gpr), A3_EMU32IN(z), A_C_00000000, A_C_00000000); 1684 gpr_map[gpr++] = 0x00000000; 1685 } 1686 } else { 1687 dev_info(emu->card->dev, "EMU inputs on\n"); 1688 /* Note that the Alice2 DSPs have 6 I2S inputs which we don't use. */ 1689 1690 /* 1691 dev_dbg(emu->card->dev, "emufx.c: gpr=0x%x, tmp=0x%x\n", 1692 gpr, tmp); 1693 */ 1694 snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_P16VIN(0x0), A_FXBUS2(0) ); 1695 /* A_P16VIN(0) is delayed by one sample, so all other A_P16VIN channels 1696 * will need to also be delayed; we use an auxiliary register for that. */ 1697 for (z = 1; z < 0x10; z++) { 1698 snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr), A_FXBUS2(z * 2) ); 1699 A_OP(icode, &ptr, iACC3, A_GPR(gpr), A_P16VIN(z), A_C_00000000, A_C_00000000); 1700 gpr_map[gpr++] = 0x00000000; 1701 } 1702 } 1703 1704 #if 0 1705 for (z = 4; z < 8; z++) { 1706 A_OP(icode, &ptr, iACC3, A_FXBUS2(z), A_C_00000000, A_C_00000000, A_C_00000000); 1707 } 1708 for (z = 0xc; z < 0x10; z++) { 1709 A_OP(icode, &ptr, iACC3, A_FXBUS2(z), A_C_00000000, A_C_00000000, A_C_00000000); 1710 } 1711 #endif 1712 } else { 1713 /* EFX capture - capture the 16 EXTINs */ 1714 /* Capture 16 channels of S16_LE sound */ 1715 for (z = 0; z < 16; z++) { 1716 A_OP(icode, &ptr, iACC3, A_FXBUS2(z), A_C_00000000, A_C_00000000, A_EXTIN(z)); 1717 } 1718 } 1719 1720 #endif /* JCD test */ 1721 /* 1722 * ok, set up done.. 1723 */ 1724 1725 if (gpr > 512) { 1726 snd_BUG(); 1727 err = -EIO; 1728 goto __err; 1729 } 1730 1731 /* clear remaining instruction memory */ 1732 while (ptr < 0x400) 1733 A_OP(icode, &ptr, 0x0f, 0xc0, 0xc0, 0xcf, 0xc0); 1734 1735 icode->gpr_add_control_count = nctl; 1736 icode->gpr_add_controls = controls; 1737 emu->support_tlv = 1; /* support TLV */ 1738 err = snd_emu10k1_icode_poke(emu, icode, true); 1739 emu->support_tlv = 0; /* clear again */ 1740 1741 __err: 1742 kfree(controls); 1743 __err_ctrls: 1744 kfree(icode->gpr_map); 1745 __err_gpr: 1746 kfree(icode); 1747 return err; 1748 } 1749 1750 1751 /* 1752 * initial DSP configuration for Emu10k1 1753 */ 1754 1755 /* Volumes are in the [-2^31, 0] range, zero being mute. */ 1756 static void _volume(struct snd_emu10k1_fx8010_code *icode, u32 *ptr, u32 dst, u32 src, u32 vol) 1757 { 1758 OP(icode, ptr, iMAC1, dst, C_00000000, src, vol); 1759 } 1760 static void _volume_add(struct snd_emu10k1_fx8010_code *icode, u32 *ptr, u32 dst, u32 src, u32 vol) 1761 { 1762 OP(icode, ptr, iMAC1, dst, dst, src, vol); 1763 } 1764 1765 #define VOLUME(icode, ptr, dst, src, vol) \ 1766 _volume(icode, ptr, GPR(dst), GPR(src), GPR(vol)) 1767 #define VOLUME_IN(icode, ptr, dst, src, vol) \ 1768 _volume(icode, ptr, GPR(dst), EXTIN(src), GPR(vol)) 1769 #define VOLUME_ADD(icode, ptr, dst, src, vol) \ 1770 _volume_add(icode, ptr, GPR(dst), GPR(src), GPR(vol)) 1771 #define VOLUME_ADDIN(icode, ptr, dst, src, vol) \ 1772 _volume_add(icode, ptr, GPR(dst), EXTIN(src), GPR(vol)) 1773 #define VOLUME_OUT(icode, ptr, dst, src, vol) \ 1774 _volume(icode, ptr, EXTOUT(dst), GPR(src), GPR(vol)) 1775 #define _SWITCH(icode, ptr, dst, src, sw) \ 1776 OP((icode), ptr, iMACINT0, dst, C_00000000, src, sw); 1777 #define SWITCH(icode, ptr, dst, src, sw) \ 1778 _SWITCH(icode, ptr, GPR(dst), GPR(src), GPR(sw)) 1779 #define SWITCH_IN(icode, ptr, dst, src, sw) \ 1780 _SWITCH(icode, ptr, GPR(dst), EXTIN(src), GPR(sw)) 1781 #define _SWITCH_NEG(icode, ptr, dst, src) \ 1782 OP((icode), ptr, iANDXOR, dst, src, C_00000001, C_00000001); 1783 #define SWITCH_NEG(icode, ptr, dst, src) \ 1784 _SWITCH_NEG(icode, ptr, GPR(dst), GPR(src)) 1785 1786 1787 static int _snd_emu10k1_init_efx(struct snd_emu10k1 *emu) 1788 { 1789 int err, i, z, gpr, tmp, playback, capture; 1790 u32 ptr, ptr_skip; 1791 struct snd_emu10k1_fx8010_code *icode; 1792 struct snd_emu10k1_fx8010_pcm_rec *ipcm = NULL; 1793 struct snd_emu10k1_fx8010_control_gpr *controls = NULL, *ctl; 1794 u32 *gpr_map; 1795 1796 err = -ENOMEM; 1797 icode = kzalloc(sizeof(*icode), GFP_KERNEL); 1798 if (!icode) 1799 return err; 1800 1801 icode->gpr_map = kcalloc(256 + 160 + 160 + 2 * 512, 1802 sizeof(u_int32_t), GFP_KERNEL); 1803 if (!icode->gpr_map) 1804 goto __err_gpr; 1805 1806 controls = kcalloc(SND_EMU10K1_GPR_CONTROLS, 1807 sizeof(struct snd_emu10k1_fx8010_control_gpr), 1808 GFP_KERNEL); 1809 if (!controls) 1810 goto __err_ctrls; 1811 1812 ipcm = kzalloc(sizeof(*ipcm), GFP_KERNEL); 1813 if (!ipcm) 1814 goto __err_ipcm; 1815 1816 gpr_map = icode->gpr_map; 1817 1818 icode->tram_data_map = icode->gpr_map + 256; 1819 icode->tram_addr_map = icode->tram_data_map + 160; 1820 icode->code = icode->tram_addr_map + 160; 1821 1822 /* clear free GPRs */ 1823 memset(icode->gpr_valid, 0xff, 256 / 8); 1824 1825 /* clear TRAM data & address lines */ 1826 memset(icode->tram_valid, 0xff, 160 / 8); 1827 1828 strcpy(icode->name, "SB Live! FX8010 code for ALSA v1.2 by Jaroslav Kysela"); 1829 ptr = 0; i = 0; 1830 /* we have 12 inputs */ 1831 playback = SND_EMU10K1_INPUTS; 1832 /* we have 6 playback channels and tone control doubles */ 1833 capture = playback + SND_EMU10K1_PLAYBACK_CHANNELS; 1834 gpr = capture + SND_EMU10K1_CAPTURE_CHANNELS; 1835 tmp = 0x88; /* we need 4 temporary GPR */ 1836 /* from 0x8c to 0xff is the area for tone control */ 1837 1838 /* 1839 * Process FX Buses 1840 */ 1841 OP(icode, &ptr, iMACINT0, GPR(0), C_00000000, FXBUS(FXBUS_PCM_LEFT), C_00000008); 1842 OP(icode, &ptr, iMACINT0, GPR(1), C_00000000, FXBUS(FXBUS_PCM_RIGHT), C_00000008); 1843 OP(icode, &ptr, iMACINT0, GPR(2), C_00000000, FXBUS(FXBUS_MIDI_LEFT), C_00000008); 1844 OP(icode, &ptr, iMACINT0, GPR(3), C_00000000, FXBUS(FXBUS_MIDI_RIGHT), C_00000008); 1845 OP(icode, &ptr, iMACINT0, GPR(4), C_00000000, FXBUS(FXBUS_PCM_LEFT_REAR), C_00000008); 1846 OP(icode, &ptr, iMACINT0, GPR(5), C_00000000, FXBUS(FXBUS_PCM_RIGHT_REAR), C_00000008); 1847 OP(icode, &ptr, iMACINT0, GPR(6), C_00000000, FXBUS(FXBUS_PCM_CENTER), C_00000008); 1848 OP(icode, &ptr, iMACINT0, GPR(7), C_00000000, FXBUS(FXBUS_PCM_LFE), C_00000008); 1849 OP(icode, &ptr, iMACINT0, GPR(8), C_00000000, C_00000000, C_00000000); /* S/PDIF left */ 1850 OP(icode, &ptr, iMACINT0, GPR(9), C_00000000, C_00000000, C_00000000); /* S/PDIF right */ 1851 OP(icode, &ptr, iMACINT0, GPR(10), C_00000000, FXBUS(FXBUS_PCM_LEFT_FRONT), C_00000008); 1852 OP(icode, &ptr, iMACINT0, GPR(11), C_00000000, FXBUS(FXBUS_PCM_RIGHT_FRONT), C_00000008); 1853 1854 /* Raw S/PDIF PCM */ 1855 ipcm->substream = 0; 1856 ipcm->channels = 2; 1857 ipcm->tram_start = 0; 1858 ipcm->buffer_size = (64 * 1024) / 2; 1859 ipcm->gpr_size = gpr++; 1860 ipcm->gpr_ptr = gpr++; 1861 ipcm->gpr_count = gpr++; 1862 ipcm->gpr_tmpcount = gpr++; 1863 ipcm->gpr_trigger = gpr++; 1864 ipcm->gpr_running = gpr++; 1865 ipcm->etram[0] = 0; 1866 ipcm->etram[1] = 1; 1867 1868 gpr_map[gpr + 0] = 0xfffff000; 1869 gpr_map[gpr + 1] = 0xffff0000; 1870 gpr_map[gpr + 2] = 0x70000000; 1871 gpr_map[gpr + 3] = 0x00000007; 1872 gpr_map[gpr + 4] = 0x001f << 11; 1873 gpr_map[gpr + 5] = 0x001c << 11; 1874 gpr_map[gpr + 6] = (0x22 - 0x01) - 1; /* skip at 01 to 22 */ 1875 gpr_map[gpr + 7] = (0x22 - 0x06) - 1; /* skip at 06 to 22 */ 1876 gpr_map[gpr + 8] = 0x2000000 + (2<<11); 1877 gpr_map[gpr + 9] = 0x4000000 + (2<<11); 1878 gpr_map[gpr + 10] = 1<<11; 1879 gpr_map[gpr + 11] = (0x24 - 0x0a) - 1; /* skip at 0a to 24 */ 1880 gpr_map[gpr + 12] = 0; 1881 1882 /* if the trigger flag is not set, skip */ 1883 /* 00: */ OP(icode, &ptr, iMAC0, C_00000000, GPR(ipcm->gpr_trigger), C_00000000, C_00000000); 1884 /* 01: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_ZERO, GPR(gpr + 6)); 1885 /* if the running flag is set, we're running */ 1886 /* 02: */ OP(icode, &ptr, iMAC0, C_00000000, GPR(ipcm->gpr_running), C_00000000, C_00000000); 1887 /* 03: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, C_00000004); 1888 /* wait until ((GPR_DBAC>>11) & 0x1f) == 0x1c) */ 1889 /* 04: */ OP(icode, &ptr, iANDXOR, GPR(tmp + 0), GPR_DBAC, GPR(gpr + 4), C_00000000); 1890 /* 05: */ OP(icode, &ptr, iMACINT0, C_00000000, GPR(tmp + 0), C_ffffffff, GPR(gpr + 5)); 1891 /* 06: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, GPR(gpr + 7)); 1892 /* 07: */ OP(icode, &ptr, iACC3, GPR(gpr + 12), C_00000010, C_00000001, C_00000000); 1893 1894 /* 08: */ OP(icode, &ptr, iANDXOR, GPR(ipcm->gpr_running), GPR(ipcm->gpr_running), C_00000000, C_00000001); 1895 /* 09: */ OP(icode, &ptr, iACC3, GPR(gpr + 12), GPR(gpr + 12), C_ffffffff, C_00000000); 1896 /* 0a: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, GPR(gpr + 11)); 1897 /* 0b: */ OP(icode, &ptr, iACC3, GPR(gpr + 12), C_00000001, C_00000000, C_00000000); 1898 1899 /* 0c: */ OP(icode, &ptr, iANDXOR, GPR(tmp + 0), ETRAM_DATA(ipcm->etram[0]), GPR(gpr + 0), C_00000000); 1900 /* 0d: */ OP(icode, &ptr, iLOG, GPR(tmp + 0), GPR(tmp + 0), GPR(gpr + 3), C_00000000); 1901 /* 0e: */ OP(icode, &ptr, iANDXOR, GPR(8), GPR(tmp + 0), GPR(gpr + 1), GPR(gpr + 2)); 1902 /* 0f: */ OP(icode, &ptr, iSKIP, C_00000000, GPR_COND, CC_REG_MINUS, C_00000001); 1903 /* 10: */ OP(icode, &ptr, iANDXOR, GPR(8), GPR(8), GPR(gpr + 1), GPR(gpr + 2)); 1904 1905 /* 11: */ OP(icode, &ptr, iANDXOR, GPR(tmp + 0), ETRAM_DATA(ipcm->etram[1]), GPR(gpr + 0), C_00000000); 1906 /* 12: */ OP(icode, &ptr, iLOG, GPR(tmp + 0), GPR(tmp + 0), GPR(gpr + 3), C_00000000); 1907 /* 13: */ OP(icode, &ptr, iANDXOR, GPR(9), GPR(tmp + 0), GPR(gpr + 1), GPR(gpr + 2)); 1908 /* 14: */ OP(icode, &ptr, iSKIP, C_00000000, GPR_COND, CC_REG_MINUS, C_00000001); 1909 /* 15: */ OP(icode, &ptr, iANDXOR, GPR(9), GPR(9), GPR(gpr + 1), GPR(gpr + 2)); 1910 1911 /* 16: */ OP(icode, &ptr, iACC3, GPR(tmp + 0), GPR(ipcm->gpr_ptr), C_00000001, C_00000000); 1912 /* 17: */ OP(icode, &ptr, iMACINT0, C_00000000, GPR(tmp + 0), C_ffffffff, GPR(ipcm->gpr_size)); 1913 /* 18: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_MINUS, C_00000001); 1914 /* 19: */ OP(icode, &ptr, iACC3, GPR(tmp + 0), C_00000000, C_00000000, C_00000000); 1915 /* 1a: */ OP(icode, &ptr, iACC3, GPR(ipcm->gpr_ptr), GPR(tmp + 0), C_00000000, C_00000000); 1916 1917 /* 1b: */ OP(icode, &ptr, iACC3, GPR(ipcm->gpr_tmpcount), GPR(ipcm->gpr_tmpcount), C_ffffffff, C_00000000); 1918 /* 1c: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, C_00000002); 1919 /* 1d: */ OP(icode, &ptr, iACC3, GPR(ipcm->gpr_tmpcount), GPR(ipcm->gpr_count), C_00000000, C_00000000); 1920 /* 1e: */ OP(icode, &ptr, iACC3, GPR_IRQ, C_80000000, C_00000000, C_00000000); 1921 /* 1f: */ OP(icode, &ptr, iANDXOR, GPR(ipcm->gpr_running), GPR(ipcm->gpr_running), C_00000001, C_00010000); 1922 1923 /* 20: */ OP(icode, &ptr, iANDXOR, GPR(ipcm->gpr_running), GPR(ipcm->gpr_running), C_00010000, C_00000001); 1924 /* 21: */ OP(icode, &ptr, iSKIP, C_00000000, C_7fffffff, C_7fffffff, C_00000002); 1925 1926 /* 22: */ OP(icode, &ptr, iMACINT1, ETRAM_ADDR(ipcm->etram[0]), GPR(gpr + 8), GPR_DBAC, C_ffffffff); 1927 /* 23: */ OP(icode, &ptr, iMACINT1, ETRAM_ADDR(ipcm->etram[1]), GPR(gpr + 9), GPR_DBAC, C_ffffffff); 1928 1929 /* 24: */ 1930 gpr += 13; 1931 1932 /* Wave Playback Volume */ 1933 for (z = 0; z < 2; z++) 1934 VOLUME(icode, &ptr, playback + z, z, gpr + z); 1935 snd_emu10k1_init_stereo_control(controls + i++, "Wave Playback Volume", gpr, 100); 1936 gpr += 2; 1937 1938 /* Wave Surround Playback Volume */ 1939 for (z = 0; z < 2; z++) 1940 VOLUME(icode, &ptr, playback + 2 + z, z, gpr + z); 1941 snd_emu10k1_init_stereo_control(controls + i++, "Wave Surround Playback Volume", gpr, 0); 1942 gpr += 2; 1943 1944 /* Wave Center/LFE Playback Volume */ 1945 OP(icode, &ptr, iACC3, GPR(tmp + 0), FXBUS(FXBUS_PCM_LEFT), FXBUS(FXBUS_PCM_RIGHT), C_00000000); 1946 OP(icode, &ptr, iMACINT0, GPR(tmp + 0), C_00000000, GPR(tmp + 0), C_00000004); 1947 VOLUME(icode, &ptr, playback + 4, tmp + 0, gpr); 1948 snd_emu10k1_init_mono_control(controls + i++, "Wave Center Playback Volume", gpr++, 0); 1949 VOLUME(icode, &ptr, playback + 5, tmp + 0, gpr); 1950 snd_emu10k1_init_mono_control(controls + i++, "Wave LFE Playback Volume", gpr++, 0); 1951 1952 /* Wave Capture Volume + Switch */ 1953 for (z = 0; z < 2; z++) { 1954 SWITCH(icode, &ptr, tmp + 0, z, gpr + 2 + z); 1955 VOLUME(icode, &ptr, capture + z, tmp + 0, gpr + z); 1956 } 1957 snd_emu10k1_init_stereo_control(controls + i++, "Wave Capture Volume", gpr, 0); 1958 snd_emu10k1_init_stereo_onoff_control(controls + i++, "Wave Capture Switch", gpr + 2, 0); 1959 gpr += 4; 1960 1961 /* Synth Playback Volume */ 1962 for (z = 0; z < 2; z++) 1963 VOLUME_ADD(icode, &ptr, playback + z, 2 + z, gpr + z); 1964 snd_emu10k1_init_stereo_control(controls + i++, "Synth Playback Volume", gpr, 100); 1965 gpr += 2; 1966 1967 /* Synth Capture Volume + Switch */ 1968 for (z = 0; z < 2; z++) { 1969 SWITCH(icode, &ptr, tmp + 0, 2 + z, gpr + 2 + z); 1970 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z); 1971 } 1972 snd_emu10k1_init_stereo_control(controls + i++, "Synth Capture Volume", gpr, 0); 1973 snd_emu10k1_init_stereo_onoff_control(controls + i++, "Synth Capture Switch", gpr + 2, 0); 1974 gpr += 4; 1975 1976 /* Surround Digital Playback Volume (renamed later without Digital) */ 1977 for (z = 0; z < 2; z++) 1978 VOLUME_ADD(icode, &ptr, playback + 2 + z, 4 + z, gpr + z); 1979 snd_emu10k1_init_stereo_control(controls + i++, "Surround Digital Playback Volume", gpr, 100); 1980 gpr += 2; 1981 1982 /* Surround Capture Volume + Switch */ 1983 for (z = 0; z < 2; z++) { 1984 SWITCH(icode, &ptr, tmp + 0, 4 + z, gpr + 2 + z); 1985 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z); 1986 } 1987 snd_emu10k1_init_stereo_control(controls + i++, "Surround Capture Volume", gpr, 0); 1988 snd_emu10k1_init_stereo_onoff_control(controls + i++, "Surround Capture Switch", gpr + 2, 0); 1989 gpr += 4; 1990 1991 /* Center Playback Volume (renamed later without Digital) */ 1992 VOLUME_ADD(icode, &ptr, playback + 4, 6, gpr); 1993 snd_emu10k1_init_mono_control(controls + i++, "Center Digital Playback Volume", gpr++, 100); 1994 1995 /* LFE Playback Volume + Switch (renamed later without Digital) */ 1996 VOLUME_ADD(icode, &ptr, playback + 5, 7, gpr); 1997 snd_emu10k1_init_mono_control(controls + i++, "LFE Digital Playback Volume", gpr++, 100); 1998 1999 /* Front Playback Volume */ 2000 for (z = 0; z < 2; z++) 2001 VOLUME_ADD(icode, &ptr, playback + z, 10 + z, gpr + z); 2002 snd_emu10k1_init_stereo_control(controls + i++, "Front Playback Volume", gpr, 100); 2003 gpr += 2; 2004 2005 /* Front Capture Volume + Switch */ 2006 for (z = 0; z < 2; z++) { 2007 SWITCH(icode, &ptr, tmp + 0, 10 + z, gpr + 2); 2008 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z); 2009 } 2010 snd_emu10k1_init_stereo_control(controls + i++, "Front Capture Volume", gpr, 0); 2011 snd_emu10k1_init_mono_onoff_control(controls + i++, "Front Capture Switch", gpr + 2, 0); 2012 gpr += 3; 2013 2014 /* 2015 * Process inputs 2016 */ 2017 2018 if (emu->fx8010.extin_mask & ((1<<EXTIN_AC97_L)|(1<<EXTIN_AC97_R))) { 2019 /* AC'97 Playback Volume */ 2020 VOLUME_ADDIN(icode, &ptr, playback + 0, EXTIN_AC97_L, gpr); gpr++; 2021 VOLUME_ADDIN(icode, &ptr, playback + 1, EXTIN_AC97_R, gpr); gpr++; 2022 snd_emu10k1_init_stereo_control(controls + i++, "AC97 Playback Volume", gpr-2, 0); 2023 /* AC'97 Capture Volume */ 2024 VOLUME_ADDIN(icode, &ptr, capture + 0, EXTIN_AC97_L, gpr); gpr++; 2025 VOLUME_ADDIN(icode, &ptr, capture + 1, EXTIN_AC97_R, gpr); gpr++; 2026 snd_emu10k1_init_stereo_control(controls + i++, "AC97 Capture Volume", gpr-2, 100); 2027 } 2028 2029 if (emu->fx8010.extin_mask & ((1<<EXTIN_SPDIF_CD_L)|(1<<EXTIN_SPDIF_CD_R))) { 2030 /* IEC958 TTL Playback Volume */ 2031 for (z = 0; z < 2; z++) 2032 VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_SPDIF_CD_L + z, gpr + z); 2033 snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("TTL ",PLAYBACK,VOLUME), gpr, 0); 2034 gpr += 2; 2035 2036 /* IEC958 TTL Capture Volume + Switch */ 2037 for (z = 0; z < 2; z++) { 2038 SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_SPDIF_CD_L + z, gpr + 2 + z); 2039 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z); 2040 } 2041 snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("TTL ",CAPTURE,VOLUME), gpr, 0); 2042 snd_emu10k1_init_stereo_onoff_control(controls + i++, SNDRV_CTL_NAME_IEC958("TTL ",CAPTURE,SWITCH), gpr + 2, 0); 2043 gpr += 4; 2044 } 2045 2046 if (emu->fx8010.extin_mask & ((1<<EXTIN_ZOOM_L)|(1<<EXTIN_ZOOM_R))) { 2047 /* Zoom Video Playback Volume */ 2048 for (z = 0; z < 2; z++) 2049 VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_ZOOM_L + z, gpr + z); 2050 snd_emu10k1_init_stereo_control(controls + i++, "Zoom Video Playback Volume", gpr, 0); 2051 gpr += 2; 2052 2053 /* Zoom Video Capture Volume + Switch */ 2054 for (z = 0; z < 2; z++) { 2055 SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_ZOOM_L + z, gpr + 2 + z); 2056 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z); 2057 } 2058 snd_emu10k1_init_stereo_control(controls + i++, "Zoom Video Capture Volume", gpr, 0); 2059 snd_emu10k1_init_stereo_onoff_control(controls + i++, "Zoom Video Capture Switch", gpr + 2, 0); 2060 gpr += 4; 2061 } 2062 2063 if (emu->fx8010.extin_mask & ((1<<EXTIN_TOSLINK_L)|(1<<EXTIN_TOSLINK_R))) { 2064 /* IEC958 Optical Playback Volume */ 2065 for (z = 0; z < 2; z++) 2066 VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_TOSLINK_L + z, gpr + z); 2067 snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("LiveDrive ",PLAYBACK,VOLUME), gpr, 0); 2068 gpr += 2; 2069 2070 /* IEC958 Optical Capture Volume */ 2071 for (z = 0; z < 2; z++) { 2072 SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_TOSLINK_L + z, gpr + 2 + z); 2073 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z); 2074 } 2075 snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("LiveDrive ",CAPTURE,VOLUME), gpr, 0); 2076 snd_emu10k1_init_stereo_onoff_control(controls + i++, SNDRV_CTL_NAME_IEC958("LiveDrive ",CAPTURE,SWITCH), gpr + 2, 0); 2077 gpr += 4; 2078 } 2079 2080 if (emu->fx8010.extin_mask & ((1<<EXTIN_LINE1_L)|(1<<EXTIN_LINE1_R))) { 2081 /* Line LiveDrive Playback Volume */ 2082 for (z = 0; z < 2; z++) 2083 VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_LINE1_L + z, gpr + z); 2084 snd_emu10k1_init_stereo_control(controls + i++, "Line LiveDrive Playback Volume", gpr, 0); 2085 gpr += 2; 2086 2087 /* Line LiveDrive Capture Volume + Switch */ 2088 for (z = 0; z < 2; z++) { 2089 SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_LINE1_L + z, gpr + 2 + z); 2090 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z); 2091 } 2092 snd_emu10k1_init_stereo_control(controls + i++, "Line LiveDrive Capture Volume", gpr, 0); 2093 snd_emu10k1_init_stereo_onoff_control(controls + i++, "Line LiveDrive Capture Switch", gpr + 2, 0); 2094 gpr += 4; 2095 } 2096 2097 if (emu->fx8010.extin_mask & ((1<<EXTIN_COAX_SPDIF_L)|(1<<EXTIN_COAX_SPDIF_R))) { 2098 /* IEC958 Coax Playback Volume */ 2099 for (z = 0; z < 2; z++) 2100 VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_COAX_SPDIF_L + z, gpr + z); 2101 snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("Coaxial ",PLAYBACK,VOLUME), gpr, 0); 2102 gpr += 2; 2103 2104 /* IEC958 Coax Capture Volume + Switch */ 2105 for (z = 0; z < 2; z++) { 2106 SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_COAX_SPDIF_L + z, gpr + 2 + z); 2107 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z); 2108 } 2109 snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("Coaxial ",CAPTURE,VOLUME), gpr, 0); 2110 snd_emu10k1_init_stereo_onoff_control(controls + i++, SNDRV_CTL_NAME_IEC958("Coaxial ",CAPTURE,SWITCH), gpr + 2, 0); 2111 gpr += 4; 2112 } 2113 2114 if (emu->fx8010.extin_mask & ((1<<EXTIN_LINE2_L)|(1<<EXTIN_LINE2_R))) { 2115 /* Line LiveDrive Playback Volume */ 2116 for (z = 0; z < 2; z++) 2117 VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_LINE2_L + z, gpr + z); 2118 snd_emu10k1_init_stereo_control(controls + i++, "Line2 LiveDrive Playback Volume", gpr, 0); 2119 controls[i-1].id.index = 1; 2120 gpr += 2; 2121 2122 /* Line LiveDrive Capture Volume */ 2123 for (z = 0; z < 2; z++) { 2124 SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_LINE2_L + z, gpr + 2 + z); 2125 VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z); 2126 } 2127 snd_emu10k1_init_stereo_control(controls + i++, "Line2 LiveDrive Capture Volume", gpr, 0); 2128 controls[i-1].id.index = 1; 2129 snd_emu10k1_init_stereo_onoff_control(controls + i++, "Line2 LiveDrive Capture Switch", gpr + 2, 0); 2130 controls[i-1].id.index = 1; 2131 gpr += 4; 2132 } 2133 2134 /* 2135 * Process tone control 2136 */ 2137 ctl = &controls[i + 0]; 2138 ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER; 2139 strcpy(ctl->id.name, "Tone Control - Bass"); 2140 ctl->vcount = 2; 2141 ctl->count = 10; 2142 ctl->min = 0; 2143 ctl->max = 40; 2144 ctl->value[0] = ctl->value[1] = 20; 2145 ctl->tlv = snd_emu10k1_bass_treble_db_scale; 2146 ctl->translation = EMU10K1_GPR_TRANSLATION_BASS; 2147 ctl = &controls[i + 1]; 2148 ctl->id.iface = (__force int)SNDRV_CTL_ELEM_IFACE_MIXER; 2149 strcpy(ctl->id.name, "Tone Control - Treble"); 2150 ctl->vcount = 2; 2151 ctl->count = 10; 2152 ctl->min = 0; 2153 ctl->max = 40; 2154 ctl->value[0] = ctl->value[1] = 20; 2155 ctl->tlv = snd_emu10k1_bass_treble_db_scale; 2156 ctl->translation = EMU10K1_GPR_TRANSLATION_TREBLE; 2157 2158 #define BASS_GPR 0x8c 2159 #define TREBLE_GPR 0x96 2160 2161 for (z = 0; z < 5; z++) { 2162 int j; 2163 for (j = 0; j < 2; j++) { 2164 controls[i + 0].gpr[z * 2 + j] = BASS_GPR + z * 2 + j; 2165 controls[i + 1].gpr[z * 2 + j] = TREBLE_GPR + z * 2 + j; 2166 } 2167 } 2168 i += 2; 2169 2170 OP(icode, &ptr, iACC3, C_00000000, GPR(gpr), C_00000000, C_00000000); 2171 snd_emu10k1_init_mono_onoff_control(controls + i++, "Tone Control - Switch", gpr, 0); 2172 gpr++; 2173 OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_ZERO, GPR(gpr)); 2174 ptr_skip = ptr; 2175 for (z = 0; z < 3; z++) { /* front/rear/center-lfe */ 2176 int j, k, l, d; 2177 for (j = 0; j < 2; j++) { /* left/right */ 2178 k = 0xa0 + (z * 8) + (j * 4); 2179 l = 0xd0 + (z * 8) + (j * 4); 2180 d = playback + z * 2 + j; 2181 2182 OP(icode, &ptr, iMAC0, C_00000000, C_00000000, GPR(d), GPR(BASS_GPR + 0 + j)); 2183 OP(icode, &ptr, iMACMV, GPR(k+1), GPR(k), GPR(k+1), GPR(BASS_GPR + 4 + j)); 2184 OP(icode, &ptr, iMACMV, GPR(k), GPR(d), GPR(k), GPR(BASS_GPR + 2 + j)); 2185 OP(icode, &ptr, iMACMV, GPR(k+3), GPR(k+2), GPR(k+3), GPR(BASS_GPR + 8 + j)); 2186 OP(icode, &ptr, iMAC0, GPR(k+2), GPR_ACCU, GPR(k+2), GPR(BASS_GPR + 6 + j)); 2187 OP(icode, &ptr, iACC3, GPR(k+2), GPR(k+2), GPR(k+2), C_00000000); 2188 2189 OP(icode, &ptr, iMAC0, C_00000000, C_00000000, GPR(k+2), GPR(TREBLE_GPR + 0 + j)); 2190 OP(icode, &ptr, iMACMV, GPR(l+1), GPR(l), GPR(l+1), GPR(TREBLE_GPR + 4 + j)); 2191 OP(icode, &ptr, iMACMV, GPR(l), GPR(k+2), GPR(l), GPR(TREBLE_GPR + 2 + j)); 2192 OP(icode, &ptr, iMACMV, GPR(l+3), GPR(l+2), GPR(l+3), GPR(TREBLE_GPR + 8 + j)); 2193 OP(icode, &ptr, iMAC0, GPR(l+2), GPR_ACCU, GPR(l+2), GPR(TREBLE_GPR + 6 + j)); 2194 OP(icode, &ptr, iMACINT0, GPR(l+2), C_00000000, GPR(l+2), C_00000010); 2195 2196 OP(icode, &ptr, iACC3, GPR(d), GPR(l+2), C_00000000, C_00000000); 2197 2198 if (z == 2) /* center */ 2199 break; 2200 } 2201 } 2202 gpr_map[gpr++] = ptr - ptr_skip; 2203 2204 #undef BASS_GPR 2205 #undef TREBLE_GPR 2206 2207 /* 2208 * Process outputs 2209 */ 2210 if (emu->fx8010.extout_mask & ((1<<EXTOUT_AC97_L)|(1<<EXTOUT_AC97_R))) { 2211 /* AC'97 Playback Volume */ 2212 2213 for (z = 0; z < 2; z++) 2214 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_L + z), GPR(playback + z), C_00000000, C_00000000); 2215 } 2216 2217 if (emu->fx8010.extout_mask & ((1<<EXTOUT_TOSLINK_L)|(1<<EXTOUT_TOSLINK_R))) { 2218 /* IEC958 Optical Raw Playback Switch */ 2219 2220 for (z = 0; z < 2; z++) { 2221 SWITCH(icode, &ptr, tmp + 0, 8 + z, gpr + z); 2222 SWITCH_NEG(icode, &ptr, tmp + 1, gpr + z); 2223 SWITCH(icode, &ptr, tmp + 1, playback + z, tmp + 1); 2224 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_TOSLINK_L + z), GPR(tmp + 0), GPR(tmp + 1), C_00000000); 2225 #ifdef EMU10K1_CAPTURE_DIGITAL_OUT 2226 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ADC_CAP_L + z), GPR(tmp + 0), GPR(tmp + 1), C_00000000); 2227 #endif 2228 } 2229 2230 snd_emu10k1_init_stereo_onoff_control(controls + i++, SNDRV_CTL_NAME_IEC958("Optical Raw ",PLAYBACK,SWITCH), gpr, 0); 2231 gpr += 2; 2232 } 2233 2234 if (emu->fx8010.extout_mask & ((1<<EXTOUT_HEADPHONE_L)|(1<<EXTOUT_HEADPHONE_R))) { 2235 /* Headphone Playback Volume */ 2236 2237 for (z = 0; z < 2; z++) { 2238 SWITCH(icode, &ptr, tmp + 0, playback + 4 + z, gpr + 2 + z); 2239 SWITCH_NEG(icode, &ptr, tmp + 1, gpr + 2 + z); 2240 SWITCH(icode, &ptr, tmp + 1, playback + z, tmp + 1); 2241 OP(icode, &ptr, iACC3, GPR(tmp + 0), GPR(tmp + 0), GPR(tmp + 1), C_00000000); 2242 VOLUME_OUT(icode, &ptr, EXTOUT_HEADPHONE_L + z, tmp + 0, gpr + z); 2243 } 2244 2245 snd_emu10k1_init_stereo_control(controls + i++, "Headphone Playback Volume", gpr + 0, 0); 2246 controls[i-1].id.index = 1; /* AC'97 can have also Headphone control */ 2247 snd_emu10k1_init_mono_onoff_control(controls + i++, "Headphone Center Playback Switch", gpr + 2, 0); 2248 controls[i-1].id.index = 1; 2249 snd_emu10k1_init_mono_onoff_control(controls + i++, "Headphone LFE Playback Switch", gpr + 3, 0); 2250 controls[i-1].id.index = 1; 2251 2252 gpr += 4; 2253 } 2254 2255 if (emu->fx8010.extout_mask & ((1<<EXTOUT_REAR_L)|(1<<EXTOUT_REAR_R))) 2256 for (z = 0; z < 2; z++) 2257 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_REAR_L + z), GPR(playback + 2 + z), C_00000000, C_00000000); 2258 2259 if (emu->fx8010.extout_mask & ((1<<EXTOUT_AC97_REAR_L)|(1<<EXTOUT_AC97_REAR_R))) 2260 for (z = 0; z < 2; z++) 2261 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_REAR_L + z), GPR(playback + 2 + z), C_00000000, C_00000000); 2262 2263 if (emu->fx8010.extout_mask & (1<<EXTOUT_AC97_CENTER)) { 2264 #ifndef EMU10K1_CENTER_LFE_FROM_FRONT 2265 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_CENTER), GPR(playback + 4), C_00000000, C_00000000); 2266 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ACENTER), GPR(playback + 4), C_00000000, C_00000000); 2267 #else 2268 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_CENTER), GPR(playback + 0), C_00000000, C_00000000); 2269 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ACENTER), GPR(playback + 0), C_00000000, C_00000000); 2270 #endif 2271 } 2272 2273 if (emu->fx8010.extout_mask & (1<<EXTOUT_AC97_LFE)) { 2274 #ifndef EMU10K1_CENTER_LFE_FROM_FRONT 2275 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_LFE), GPR(playback + 5), C_00000000, C_00000000); 2276 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ALFE), GPR(playback + 5), C_00000000, C_00000000); 2277 #else 2278 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_LFE), GPR(playback + 1), C_00000000, C_00000000); 2279 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ALFE), GPR(playback + 1), C_00000000, C_00000000); 2280 #endif 2281 } 2282 2283 #ifndef EMU10K1_CAPTURE_DIGITAL_OUT 2284 for (z = 0; z < 2; z++) 2285 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ADC_CAP_L + z), GPR(capture + z), C_00000000, C_00000000); 2286 #endif 2287 2288 if (emu->fx8010.extout_mask & (1<<EXTOUT_MIC_CAP)) 2289 OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_MIC_CAP), GPR(capture + 2), C_00000000, C_00000000); 2290 2291 /* EFX capture - capture the 16 EXTINS */ 2292 if (emu->card_capabilities->sblive51) { 2293 /* On the Live! 5.1, FXBUS2(1) and FXBUS(2) are shared with EXTOUT_ACENTER 2294 * and EXTOUT_ALFE, so we can't connect inputs to them for multitrack recording. 2295 * 2296 * Since only 14 of the 16 EXTINs are used, this is not a big problem. 2297 * We route AC97L and R to FX capture 14 and 15, SPDIF CD in to FX capture 2298 * 0 and 3, then the rest of the EXTINs to the corresponding FX capture 2299 * channel. Multitrack recorders will still see the center/lfe output signal 2300 * on the second and third channels. 2301 */ 2302 OP(icode, &ptr, iACC3, FXBUS2(14), C_00000000, C_00000000, EXTIN(0)); 2303 OP(icode, &ptr, iACC3, FXBUS2(15), C_00000000, C_00000000, EXTIN(1)); 2304 OP(icode, &ptr, iACC3, FXBUS2(0), C_00000000, C_00000000, EXTIN(2)); 2305 OP(icode, &ptr, iACC3, FXBUS2(3), C_00000000, C_00000000, EXTIN(3)); 2306 for (z = 4; z < 14; z++) 2307 OP(icode, &ptr, iACC3, FXBUS2(z), C_00000000, C_00000000, EXTIN(z)); 2308 } else { 2309 for (z = 0; z < 16; z++) 2310 OP(icode, &ptr, iACC3, FXBUS2(z), C_00000000, C_00000000, EXTIN(z)); 2311 } 2312 2313 2314 if (gpr > tmp) { 2315 snd_BUG(); 2316 err = -EIO; 2317 goto __err; 2318 } 2319 if (i > SND_EMU10K1_GPR_CONTROLS) { 2320 snd_BUG(); 2321 err = -EIO; 2322 goto __err; 2323 } 2324 2325 /* clear remaining instruction memory */ 2326 while (ptr < 0x200) 2327 OP(icode, &ptr, iACC3, C_00000000, C_00000000, C_00000000, C_00000000); 2328 2329 err = snd_emu10k1_fx8010_tram_setup(emu, ipcm->buffer_size); 2330 if (err < 0) 2331 goto __err; 2332 icode->gpr_add_control_count = i; 2333 icode->gpr_add_controls = controls; 2334 emu->support_tlv = 1; /* support TLV */ 2335 err = snd_emu10k1_icode_poke(emu, icode, true); 2336 emu->support_tlv = 0; /* clear again */ 2337 if (err >= 0) 2338 err = snd_emu10k1_ipcm_poke(emu, ipcm); 2339 __err: 2340 kfree(ipcm); 2341 __err_ipcm: 2342 kfree(controls); 2343 __err_ctrls: 2344 kfree(icode->gpr_map); 2345 __err_gpr: 2346 kfree(icode); 2347 return err; 2348 } 2349 2350 int snd_emu10k1_init_efx(struct snd_emu10k1 *emu) 2351 { 2352 spin_lock_init(&emu->fx8010.irq_lock); 2353 INIT_LIST_HEAD(&emu->fx8010.gpr_ctl); 2354 if (emu->audigy) 2355 return _snd_emu10k1_audigy_init_efx(emu); 2356 else 2357 return _snd_emu10k1_init_efx(emu); 2358 } 2359 2360 void snd_emu10k1_free_efx(struct snd_emu10k1 *emu) 2361 { 2362 /* stop processor */ 2363 if (emu->audigy) 2364 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg = A_DBG_SINGLE_STEP); 2365 else 2366 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg = EMU10K1_DBG_SINGLE_STEP); 2367 } 2368 2369 #if 0 /* FIXME: who use them? */ 2370 int snd_emu10k1_fx8010_tone_control_activate(struct snd_emu10k1 *emu, int output) 2371 { 2372 if (output < 0 || output >= 6) 2373 return -EINVAL; 2374 snd_emu10k1_ptr_write(emu, emu->gpr_base + 0x94 + output, 0, 1); 2375 return 0; 2376 } 2377 2378 int snd_emu10k1_fx8010_tone_control_deactivate(struct snd_emu10k1 *emu, int output) 2379 { 2380 if (output < 0 || output >= 6) 2381 return -EINVAL; 2382 snd_emu10k1_ptr_write(emu, emu->gpr_base + 0x94 + output, 0, 0); 2383 return 0; 2384 } 2385 #endif 2386 2387 int snd_emu10k1_fx8010_tram_setup(struct snd_emu10k1 *emu, u32 size) 2388 { 2389 u8 size_reg = 0; 2390 2391 /* size is in samples */ 2392 if (size != 0) { 2393 size = (size - 1) >> 13; 2394 2395 while (size) { 2396 size >>= 1; 2397 size_reg++; 2398 } 2399 size = 0x2000 << size_reg; 2400 } 2401 if ((emu->fx8010.etram_pages.bytes / 2) == size) 2402 return 0; 2403 spin_lock_irq(&emu->emu_lock); 2404 outl(HCFG_LOCKTANKCACHE_MASK | inl(emu->port + HCFG), emu->port + HCFG); 2405 spin_unlock_irq(&emu->emu_lock); 2406 snd_emu10k1_ptr_write(emu, TCB, 0, 0); 2407 snd_emu10k1_ptr_write(emu, TCBS, 0, TCBS_BUFFSIZE_16K); 2408 if (emu->fx8010.etram_pages.area != NULL) { 2409 snd_dma_free_pages(&emu->fx8010.etram_pages); 2410 emu->fx8010.etram_pages.area = NULL; 2411 emu->fx8010.etram_pages.bytes = 0; 2412 } 2413 2414 if (size > 0) { 2415 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &emu->pci->dev, 2416 size * 2, &emu->fx8010.etram_pages) < 0) 2417 return -ENOMEM; 2418 memset(emu->fx8010.etram_pages.area, 0, size * 2); 2419 snd_emu10k1_ptr_write(emu, TCB, 0, emu->fx8010.etram_pages.addr); 2420 snd_emu10k1_ptr_write(emu, TCBS, 0, size_reg); 2421 spin_lock_irq(&emu->emu_lock); 2422 outl(inl(emu->port + HCFG) & ~HCFG_LOCKTANKCACHE_MASK, emu->port + HCFG); 2423 spin_unlock_irq(&emu->emu_lock); 2424 } 2425 2426 return 0; 2427 } 2428 2429 static int snd_emu10k1_fx8010_open(struct snd_hwdep * hw, struct file *file) 2430 { 2431 return 0; 2432 } 2433 2434 static void copy_string(char *dst, const char *src, const char *null, int idx) 2435 { 2436 if (src == NULL) 2437 sprintf(dst, "%s %02X", null, idx); 2438 else 2439 strcpy(dst, src); 2440 } 2441 2442 static void snd_emu10k1_fx8010_info(struct snd_emu10k1 *emu, 2443 struct snd_emu10k1_fx8010_info *info) 2444 { 2445 const char * const *fxbus, * const *extin, * const *extout; 2446 unsigned short extin_mask, extout_mask; 2447 int res; 2448 2449 info->internal_tram_size = emu->fx8010.itram_size; 2450 info->external_tram_size = emu->fx8010.etram_pages.bytes / 2; 2451 fxbus = fxbuses; 2452 extin = emu->audigy ? audigy_ins : creative_ins; 2453 extout = emu->audigy ? audigy_outs : creative_outs; 2454 extin_mask = emu->audigy ? ~0 : emu->fx8010.extin_mask; 2455 extout_mask = emu->audigy ? ~0 : emu->fx8010.extout_mask; 2456 for (res = 0; res < 16; res++, fxbus++, extin++, extout++) { 2457 copy_string(info->fxbus_names[res], *fxbus, "FXBUS", res); 2458 copy_string(info->extin_names[res], extin_mask & (1 << res) ? *extin : NULL, "Unused", res); 2459 copy_string(info->extout_names[res], extout_mask & (1 << res) ? *extout : NULL, "Unused", res); 2460 } 2461 for (res = 16; res < 32; res++, extout++) 2462 copy_string(info->extout_names[res], extout_mask & (1 << res) ? *extout : NULL, "Unused", res); 2463 info->gpr_controls = emu->fx8010.gpr_count; 2464 } 2465 2466 static int snd_emu10k1_fx8010_ioctl(struct snd_hwdep * hw, struct file *file, unsigned int cmd, unsigned long arg) 2467 { 2468 struct snd_emu10k1 *emu = hw->private_data; 2469 struct snd_emu10k1_fx8010_info *info; 2470 struct snd_emu10k1_fx8010_code *icode; 2471 struct snd_emu10k1_fx8010_pcm_rec *ipcm; 2472 unsigned int addr; 2473 void __user *argp = (void __user *)arg; 2474 int res; 2475 2476 switch (cmd) { 2477 case SNDRV_EMU10K1_IOCTL_PVERSION: 2478 emu->support_tlv = 1; 2479 return put_user(SNDRV_EMU10K1_VERSION, (int __user *)argp); 2480 case SNDRV_EMU10K1_IOCTL_INFO: 2481 info = kzalloc(sizeof(*info), GFP_KERNEL); 2482 if (!info) 2483 return -ENOMEM; 2484 snd_emu10k1_fx8010_info(emu, info); 2485 if (copy_to_user(argp, info, sizeof(*info))) { 2486 kfree(info); 2487 return -EFAULT; 2488 } 2489 kfree(info); 2490 return 0; 2491 case SNDRV_EMU10K1_IOCTL_CODE_POKE: 2492 if (!capable(CAP_SYS_ADMIN)) 2493 return -EPERM; 2494 2495 icode = memdup_user(argp, sizeof(*icode)); 2496 if (IS_ERR(icode)) 2497 return PTR_ERR(icode); 2498 res = snd_emu10k1_icode_poke(emu, icode, false); 2499 kfree(icode); 2500 return res; 2501 case SNDRV_EMU10K1_IOCTL_CODE_PEEK: 2502 icode = memdup_user(argp, sizeof(*icode)); 2503 if (IS_ERR(icode)) 2504 return PTR_ERR(icode); 2505 res = snd_emu10k1_icode_peek(emu, icode); 2506 if (res == 0 && copy_to_user(argp, icode, sizeof(*icode))) { 2507 kfree(icode); 2508 return -EFAULT; 2509 } 2510 kfree(icode); 2511 return res; 2512 case SNDRV_EMU10K1_IOCTL_PCM_POKE: 2513 ipcm = memdup_user(argp, sizeof(*ipcm)); 2514 if (IS_ERR(ipcm)) 2515 return PTR_ERR(ipcm); 2516 res = snd_emu10k1_ipcm_poke(emu, ipcm); 2517 kfree(ipcm); 2518 return res; 2519 case SNDRV_EMU10K1_IOCTL_PCM_PEEK: 2520 ipcm = memdup_user(argp, sizeof(*ipcm)); 2521 if (IS_ERR(ipcm)) 2522 return PTR_ERR(ipcm); 2523 res = snd_emu10k1_ipcm_peek(emu, ipcm); 2524 if (res == 0 && copy_to_user(argp, ipcm, sizeof(*ipcm))) { 2525 kfree(ipcm); 2526 return -EFAULT; 2527 } 2528 kfree(ipcm); 2529 return res; 2530 case SNDRV_EMU10K1_IOCTL_TRAM_SETUP: 2531 if (!capable(CAP_SYS_ADMIN)) 2532 return -EPERM; 2533 if (get_user(addr, (unsigned int __user *)argp)) 2534 return -EFAULT; 2535 mutex_lock(&emu->fx8010.lock); 2536 res = snd_emu10k1_fx8010_tram_setup(emu, addr); 2537 mutex_unlock(&emu->fx8010.lock); 2538 return res; 2539 case SNDRV_EMU10K1_IOCTL_STOP: 2540 if (!capable(CAP_SYS_ADMIN)) 2541 return -EPERM; 2542 if (emu->audigy) 2543 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg |= A_DBG_SINGLE_STEP); 2544 else 2545 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg |= EMU10K1_DBG_SINGLE_STEP); 2546 return 0; 2547 case SNDRV_EMU10K1_IOCTL_CONTINUE: 2548 if (!capable(CAP_SYS_ADMIN)) 2549 return -EPERM; 2550 if (emu->audigy) 2551 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg = 0); 2552 else 2553 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg = 0); 2554 return 0; 2555 case SNDRV_EMU10K1_IOCTL_ZERO_TRAM_COUNTER: 2556 if (!capable(CAP_SYS_ADMIN)) 2557 return -EPERM; 2558 if (emu->audigy) 2559 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg | A_DBG_ZC); 2560 else 2561 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg | EMU10K1_DBG_ZC); 2562 udelay(10); 2563 if (emu->audigy) 2564 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg); 2565 else 2566 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg); 2567 return 0; 2568 case SNDRV_EMU10K1_IOCTL_SINGLE_STEP: 2569 if (!capable(CAP_SYS_ADMIN)) 2570 return -EPERM; 2571 if (get_user(addr, (unsigned int __user *)argp)) 2572 return -EFAULT; 2573 if (emu->audigy) { 2574 if (addr > A_DBG_STEP_ADDR) 2575 return -EINVAL; 2576 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg |= A_DBG_SINGLE_STEP); 2577 udelay(10); 2578 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg | A_DBG_STEP | addr); 2579 } else { 2580 if (addr > EMU10K1_DBG_SINGLE_STEP_ADDR) 2581 return -EINVAL; 2582 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg |= EMU10K1_DBG_SINGLE_STEP); 2583 udelay(10); 2584 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg | EMU10K1_DBG_STEP | addr); 2585 } 2586 return 0; 2587 case SNDRV_EMU10K1_IOCTL_DBG_READ: 2588 if (emu->audigy) 2589 addr = snd_emu10k1_ptr_read(emu, A_DBG, 0); 2590 else 2591 addr = snd_emu10k1_ptr_read(emu, DBG, 0); 2592 if (put_user(addr, (unsigned int __user *)argp)) 2593 return -EFAULT; 2594 return 0; 2595 } 2596 return -ENOTTY; 2597 } 2598 2599 static int snd_emu10k1_fx8010_release(struct snd_hwdep * hw, struct file *file) 2600 { 2601 return 0; 2602 } 2603 2604 int snd_emu10k1_fx8010_new(struct snd_emu10k1 *emu, int device) 2605 { 2606 struct snd_hwdep *hw; 2607 int err; 2608 2609 err = snd_hwdep_new(emu->card, "FX8010", device, &hw); 2610 if (err < 0) 2611 return err; 2612 strcpy(hw->name, "EMU10K1 (FX8010)"); 2613 hw->iface = SNDRV_HWDEP_IFACE_EMU10K1; 2614 hw->ops.open = snd_emu10k1_fx8010_open; 2615 hw->ops.ioctl = snd_emu10k1_fx8010_ioctl; 2616 hw->ops.release = snd_emu10k1_fx8010_release; 2617 hw->private_data = emu; 2618 return 0; 2619 } 2620 2621 #ifdef CONFIG_PM_SLEEP 2622 int snd_emu10k1_efx_alloc_pm_buffer(struct snd_emu10k1 *emu) 2623 { 2624 int len; 2625 2626 len = emu->audigy ? 0x200 : 0x100; 2627 emu->saved_gpr = kmalloc_array(len, 4, GFP_KERNEL); 2628 if (! emu->saved_gpr) 2629 return -ENOMEM; 2630 len = emu->audigy ? 0x100 : 0xa0; 2631 emu->tram_val_saved = kmalloc_array(len, 4, GFP_KERNEL); 2632 emu->tram_addr_saved = kmalloc_array(len, 4, GFP_KERNEL); 2633 if (! emu->tram_val_saved || ! emu->tram_addr_saved) 2634 return -ENOMEM; 2635 len = emu->audigy ? 2 * 1024 : 2 * 512; 2636 emu->saved_icode = vmalloc(array_size(len, 4)); 2637 if (! emu->saved_icode) 2638 return -ENOMEM; 2639 return 0; 2640 } 2641 2642 void snd_emu10k1_efx_free_pm_buffer(struct snd_emu10k1 *emu) 2643 { 2644 kfree(emu->saved_gpr); 2645 kfree(emu->tram_val_saved); 2646 kfree(emu->tram_addr_saved); 2647 vfree(emu->saved_icode); 2648 } 2649 2650 /* 2651 * save/restore GPR, TRAM and codes 2652 */ 2653 void snd_emu10k1_efx_suspend(struct snd_emu10k1 *emu) 2654 { 2655 int i, len; 2656 2657 len = emu->audigy ? 0x200 : 0x100; 2658 for (i = 0; i < len; i++) 2659 emu->saved_gpr[i] = snd_emu10k1_ptr_read(emu, emu->gpr_base + i, 0); 2660 2661 len = emu->audigy ? 0x100 : 0xa0; 2662 for (i = 0; i < len; i++) { 2663 emu->tram_val_saved[i] = snd_emu10k1_ptr_read(emu, TANKMEMDATAREGBASE + i, 0); 2664 emu->tram_addr_saved[i] = snd_emu10k1_ptr_read(emu, TANKMEMADDRREGBASE + i, 0); 2665 if (emu->audigy) { 2666 emu->tram_addr_saved[i] >>= 12; 2667 emu->tram_addr_saved[i] |= 2668 snd_emu10k1_ptr_read(emu, A_TANKMEMCTLREGBASE + i, 0) << 20; 2669 } 2670 } 2671 2672 len = emu->audigy ? 2 * 1024 : 2 * 512; 2673 for (i = 0; i < len; i++) 2674 emu->saved_icode[i] = snd_emu10k1_efx_read(emu, i); 2675 } 2676 2677 void snd_emu10k1_efx_resume(struct snd_emu10k1 *emu) 2678 { 2679 int i, len; 2680 2681 /* set up TRAM */ 2682 if (emu->fx8010.etram_pages.bytes > 0) { 2683 unsigned size, size_reg = 0; 2684 size = emu->fx8010.etram_pages.bytes / 2; 2685 size = (size - 1) >> 13; 2686 while (size) { 2687 size >>= 1; 2688 size_reg++; 2689 } 2690 outl(HCFG_LOCKTANKCACHE_MASK | inl(emu->port + HCFG), emu->port + HCFG); 2691 snd_emu10k1_ptr_write(emu, TCB, 0, emu->fx8010.etram_pages.addr); 2692 snd_emu10k1_ptr_write(emu, TCBS, 0, size_reg); 2693 outl(inl(emu->port + HCFG) & ~HCFG_LOCKTANKCACHE_MASK, emu->port + HCFG); 2694 } 2695 2696 if (emu->audigy) 2697 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg | A_DBG_SINGLE_STEP); 2698 else 2699 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg | EMU10K1_DBG_SINGLE_STEP); 2700 2701 len = emu->audigy ? 0x200 : 0x100; 2702 for (i = 0; i < len; i++) 2703 snd_emu10k1_ptr_write(emu, emu->gpr_base + i, 0, emu->saved_gpr[i]); 2704 2705 len = emu->audigy ? 0x100 : 0xa0; 2706 for (i = 0; i < len; i++) { 2707 snd_emu10k1_ptr_write(emu, TANKMEMDATAREGBASE + i, 0, 2708 emu->tram_val_saved[i]); 2709 if (! emu->audigy) 2710 snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + i, 0, 2711 emu->tram_addr_saved[i]); 2712 else { 2713 snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + i, 0, 2714 emu->tram_addr_saved[i] << 12); 2715 snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + i, 0, 2716 emu->tram_addr_saved[i] >> 20); 2717 } 2718 } 2719 2720 len = emu->audigy ? 2 * 1024 : 2 * 512; 2721 for (i = 0; i < len; i++) 2722 snd_emu10k1_efx_write(emu, i, emu->saved_icode[i]); 2723 2724 /* start FX processor when the DSP code is updated */ 2725 if (emu->audigy) 2726 snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg); 2727 else 2728 snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg); 2729 } 2730 #endif 2731