1 // SPDX-License-Identifier: GPL-2.0-only 2 /**************************************************************************** 3 4 Copyright Echo Digital Audio Corporation (c) 1998 - 2004 5 All rights reserved 6 www.echoaudio.com 7 8 This file is part of Echo Digital Audio's generic driver library. 9 ************************************************************************* 10 11 Translation from C++ and adaptation for use in ALSA-Driver 12 were made by Giuliano Pochini <pochini@shiny.it> 13 14 ****************************************************************************/ 15 16 17 static int write_control_reg(struct echoaudio *chip, u32 value, char force); 18 static int set_input_clock(struct echoaudio *chip, u16 clock); 19 static int set_professional_spdif(struct echoaudio *chip, char prof); 20 static int set_digital_mode(struct echoaudio *chip, u8 mode); 21 static int load_asic_generic(struct echoaudio *chip, u32 cmd, short asic); 22 static int check_asic_status(struct echoaudio *chip); 23 24 25 static int init_hw(struct echoaudio *chip, u16 device_id, u16 subdevice_id) 26 { 27 int err; 28 29 if (snd_BUG_ON((subdevice_id & 0xfff0) != MONA)) 30 return -ENODEV; 31 32 err = init_dsp_comm_page(chip); 33 if (err) { 34 dev_err(chip->card->dev, 35 "init_hw - could not initialize DSP comm page\n"); 36 return err; 37 } 38 39 chip->device_id = device_id; 40 chip->subdevice_id = subdevice_id; 41 chip->bad_board = true; 42 chip->input_clock_types = 43 ECHO_CLOCK_BIT_INTERNAL | ECHO_CLOCK_BIT_SPDIF | 44 ECHO_CLOCK_BIT_WORD | ECHO_CLOCK_BIT_ADAT; 45 chip->digital_modes = 46 ECHOCAPS_HAS_DIGITAL_MODE_SPDIF_RCA | 47 ECHOCAPS_HAS_DIGITAL_MODE_SPDIF_OPTICAL | 48 ECHOCAPS_HAS_DIGITAL_MODE_ADAT; 49 50 /* Mona comes in both '301 and '361 flavors */ 51 if (chip->device_id == DEVICE_ID_56361) 52 chip->dsp_code_to_load = FW_MONA_361_DSP; 53 else 54 chip->dsp_code_to_load = FW_MONA_301_DSP; 55 56 err = load_firmware(chip); 57 if (err < 0) 58 return err; 59 chip->bad_board = false; 60 61 return err; 62 } 63 64 65 66 static int set_mixer_defaults(struct echoaudio *chip) 67 { 68 chip->digital_mode = DIGITAL_MODE_SPDIF_RCA; 69 chip->professional_spdif = false; 70 chip->digital_in_automute = true; 71 return init_line_levels(chip); 72 } 73 74 75 76 static u32 detect_input_clocks(const struct echoaudio *chip) 77 { 78 u32 clocks_from_dsp, clock_bits; 79 80 /* Map the DSP clock detect bits to the generic driver clock 81 detect bits */ 82 clocks_from_dsp = le32_to_cpu(chip->comm_page->status_clocks); 83 84 clock_bits = ECHO_CLOCK_BIT_INTERNAL; 85 86 if (clocks_from_dsp & GML_CLOCK_DETECT_BIT_SPDIF) 87 clock_bits |= ECHO_CLOCK_BIT_SPDIF; 88 89 if (clocks_from_dsp & GML_CLOCK_DETECT_BIT_ADAT) 90 clock_bits |= ECHO_CLOCK_BIT_ADAT; 91 92 if (clocks_from_dsp & GML_CLOCK_DETECT_BIT_WORD) 93 clock_bits |= ECHO_CLOCK_BIT_WORD; 94 95 return clock_bits; 96 } 97 98 99 100 /* Mona has an ASIC on the PCI card and another ASIC in the external box; 101 both need to be loaded. */ 102 static int load_asic(struct echoaudio *chip) 103 { 104 u32 control_reg; 105 int err; 106 short asic; 107 108 if (chip->asic_loaded) 109 return 0; 110 111 mdelay(10); 112 113 if (chip->device_id == DEVICE_ID_56361) 114 asic = FW_MONA_361_1_ASIC48; 115 else 116 asic = FW_MONA_301_1_ASIC48; 117 118 err = load_asic_generic(chip, DSP_FNC_LOAD_MONA_PCI_CARD_ASIC, asic); 119 if (err < 0) 120 return err; 121 122 chip->asic_code = asic; 123 mdelay(10); 124 125 /* Do the external one */ 126 err = load_asic_generic(chip, DSP_FNC_LOAD_MONA_EXTERNAL_ASIC, 127 FW_MONA_2_ASIC); 128 if (err < 0) 129 return err; 130 131 mdelay(10); 132 err = check_asic_status(chip); 133 134 /* Set up the control register if the load succeeded - 135 48 kHz, internal clock, S/PDIF RCA mode */ 136 if (!err) { 137 control_reg = GML_CONVERTER_ENABLE | GML_48KHZ; 138 err = write_control_reg(chip, control_reg, true); 139 } 140 141 return err; 142 } 143 144 145 146 /* Depending on what digital mode you want, Mona needs different ASICs 147 loaded. This function checks the ASIC needed for the new mode and sees 148 if it matches the one already loaded. */ 149 static int switch_asic(struct echoaudio *chip, char double_speed) 150 { 151 int err; 152 short asic; 153 154 /* Check the clock detect bits to see if this is 155 a single-speed clock or a double-speed clock; load 156 a new ASIC if necessary. */ 157 if (chip->device_id == DEVICE_ID_56361) { 158 if (double_speed) 159 asic = FW_MONA_361_1_ASIC96; 160 else 161 asic = FW_MONA_361_1_ASIC48; 162 } else { 163 if (double_speed) 164 asic = FW_MONA_301_1_ASIC96; 165 else 166 asic = FW_MONA_301_1_ASIC48; 167 } 168 169 if (asic != chip->asic_code) { 170 /* Load the desired ASIC */ 171 err = load_asic_generic(chip, DSP_FNC_LOAD_MONA_PCI_CARD_ASIC, 172 asic); 173 if (err < 0) 174 return err; 175 chip->asic_code = asic; 176 } 177 178 return 0; 179 } 180 181 182 183 static int set_sample_rate(struct echoaudio *chip, u32 rate) 184 { 185 u32 control_reg, clock; 186 short asic; 187 char force_write; 188 189 /* Only set the clock for internal mode. */ 190 if (chip->input_clock != ECHO_CLOCK_INTERNAL) { 191 dev_dbg(chip->card->dev, 192 "Cannot set sample rate - clock not set to CLK_CLOCKININTERNAL\n"); 193 /* Save the rate anyhow */ 194 chip->comm_page->sample_rate = cpu_to_le32(rate); 195 chip->sample_rate = rate; 196 return 0; 197 } 198 199 /* Now, check to see if the required ASIC is loaded */ 200 if (rate >= 88200) { 201 if (chip->digital_mode == DIGITAL_MODE_ADAT) 202 return -EINVAL; 203 if (chip->device_id == DEVICE_ID_56361) 204 asic = FW_MONA_361_1_ASIC96; 205 else 206 asic = FW_MONA_301_1_ASIC96; 207 } else { 208 if (chip->device_id == DEVICE_ID_56361) 209 asic = FW_MONA_361_1_ASIC48; 210 else 211 asic = FW_MONA_301_1_ASIC48; 212 } 213 214 force_write = 0; 215 if (asic != chip->asic_code) { 216 int err; 217 /* Load the desired ASIC (load_asic_generic() can sleep) */ 218 spin_unlock_irq(&chip->lock); 219 err = load_asic_generic(chip, DSP_FNC_LOAD_MONA_PCI_CARD_ASIC, 220 asic); 221 spin_lock_irq(&chip->lock); 222 223 if (err < 0) 224 return err; 225 chip->asic_code = asic; 226 force_write = 1; 227 } 228 229 /* Compute the new control register value */ 230 clock = 0; 231 control_reg = le32_to_cpu(chip->comm_page->control_register); 232 control_reg &= GML_CLOCK_CLEAR_MASK; 233 control_reg &= GML_SPDIF_RATE_CLEAR_MASK; 234 235 switch (rate) { 236 case 96000: 237 clock = GML_96KHZ; 238 break; 239 case 88200: 240 clock = GML_88KHZ; 241 break; 242 case 48000: 243 clock = GML_48KHZ | GML_SPDIF_SAMPLE_RATE1; 244 break; 245 case 44100: 246 clock = GML_44KHZ; 247 /* Professional mode */ 248 if (control_reg & GML_SPDIF_PRO_MODE) 249 clock |= GML_SPDIF_SAMPLE_RATE0; 250 break; 251 case 32000: 252 clock = GML_32KHZ | GML_SPDIF_SAMPLE_RATE0 | 253 GML_SPDIF_SAMPLE_RATE1; 254 break; 255 case 22050: 256 clock = GML_22KHZ; 257 break; 258 case 16000: 259 clock = GML_16KHZ; 260 break; 261 case 11025: 262 clock = GML_11KHZ; 263 break; 264 case 8000: 265 clock = GML_8KHZ; 266 break; 267 default: 268 dev_err(chip->card->dev, 269 "set_sample_rate: %d invalid!\n", rate); 270 return -EINVAL; 271 } 272 273 control_reg |= clock; 274 275 chip->comm_page->sample_rate = cpu_to_le32(rate); /* ignored by the DSP */ 276 chip->sample_rate = rate; 277 dev_dbg(chip->card->dev, 278 "set_sample_rate: %d clock %d\n", rate, clock); 279 280 return write_control_reg(chip, control_reg, force_write); 281 } 282 283 284 285 static int set_input_clock(struct echoaudio *chip, u16 clock) 286 { 287 u32 control_reg, clocks_from_dsp; 288 int err; 289 290 /* Mask off the clock select bits */ 291 control_reg = le32_to_cpu(chip->comm_page->control_register) & 292 GML_CLOCK_CLEAR_MASK; 293 clocks_from_dsp = le32_to_cpu(chip->comm_page->status_clocks); 294 295 switch (clock) { 296 case ECHO_CLOCK_INTERNAL: 297 chip->input_clock = ECHO_CLOCK_INTERNAL; 298 return set_sample_rate(chip, chip->sample_rate); 299 case ECHO_CLOCK_SPDIF: 300 if (chip->digital_mode == DIGITAL_MODE_ADAT) 301 return -EAGAIN; 302 spin_unlock_irq(&chip->lock); 303 err = switch_asic(chip, clocks_from_dsp & 304 GML_CLOCK_DETECT_BIT_SPDIF96); 305 spin_lock_irq(&chip->lock); 306 if (err < 0) 307 return err; 308 control_reg |= GML_SPDIF_CLOCK; 309 if (clocks_from_dsp & GML_CLOCK_DETECT_BIT_SPDIF96) 310 control_reg |= GML_DOUBLE_SPEED_MODE; 311 else 312 control_reg &= ~GML_DOUBLE_SPEED_MODE; 313 break; 314 case ECHO_CLOCK_WORD: 315 spin_unlock_irq(&chip->lock); 316 err = switch_asic(chip, clocks_from_dsp & 317 GML_CLOCK_DETECT_BIT_WORD96); 318 spin_lock_irq(&chip->lock); 319 if (err < 0) 320 return err; 321 control_reg |= GML_WORD_CLOCK; 322 if (clocks_from_dsp & GML_CLOCK_DETECT_BIT_WORD96) 323 control_reg |= GML_DOUBLE_SPEED_MODE; 324 else 325 control_reg &= ~GML_DOUBLE_SPEED_MODE; 326 break; 327 case ECHO_CLOCK_ADAT: 328 dev_dbg(chip->card->dev, "Set Mona clock to ADAT\n"); 329 if (chip->digital_mode != DIGITAL_MODE_ADAT) 330 return -EAGAIN; 331 control_reg |= GML_ADAT_CLOCK; 332 control_reg &= ~GML_DOUBLE_SPEED_MODE; 333 break; 334 default: 335 dev_err(chip->card->dev, 336 "Input clock 0x%x not supported for Mona\n", clock); 337 return -EINVAL; 338 } 339 340 chip->input_clock = clock; 341 return write_control_reg(chip, control_reg, true); 342 } 343 344 345 346 static int dsp_set_digital_mode(struct echoaudio *chip, u8 mode) 347 { 348 u32 control_reg; 349 int err, incompatible_clock; 350 351 /* Set clock to "internal" if it's not compatible with the new mode */ 352 incompatible_clock = false; 353 switch (mode) { 354 case DIGITAL_MODE_SPDIF_OPTICAL: 355 case DIGITAL_MODE_SPDIF_RCA: 356 if (chip->input_clock == ECHO_CLOCK_ADAT) 357 incompatible_clock = true; 358 break; 359 case DIGITAL_MODE_ADAT: 360 if (chip->input_clock == ECHO_CLOCK_SPDIF) 361 incompatible_clock = true; 362 break; 363 default: 364 dev_err(chip->card->dev, 365 "Digital mode not supported: %d\n", mode); 366 return -EINVAL; 367 } 368 369 guard(spinlock_irq)(&chip->lock); 370 371 if (incompatible_clock) { /* Switch to 48KHz, internal */ 372 chip->sample_rate = 48000; 373 set_input_clock(chip, ECHO_CLOCK_INTERNAL); 374 } 375 376 /* Clear the current digital mode */ 377 control_reg = le32_to_cpu(chip->comm_page->control_register); 378 control_reg &= GML_DIGITAL_MODE_CLEAR_MASK; 379 380 /* Tweak the control reg */ 381 switch (mode) { 382 case DIGITAL_MODE_SPDIF_OPTICAL: 383 control_reg |= GML_SPDIF_OPTICAL_MODE; 384 break; 385 case DIGITAL_MODE_SPDIF_RCA: 386 /* GML_SPDIF_OPTICAL_MODE bit cleared */ 387 break; 388 case DIGITAL_MODE_ADAT: 389 /* If the current ASIC is the 96KHz ASIC, switch the ASIC 390 and set to 48 KHz */ 391 if (chip->asic_code == FW_MONA_361_1_ASIC96 || 392 chip->asic_code == FW_MONA_301_1_ASIC96) { 393 set_sample_rate(chip, 48000); 394 } 395 control_reg |= GML_ADAT_MODE; 396 control_reg &= ~GML_DOUBLE_SPEED_MODE; 397 break; 398 } 399 400 err = write_control_reg(chip, control_reg, false); 401 if (err < 0) 402 return err; 403 chip->digital_mode = mode; 404 405 dev_dbg(chip->card->dev, "set_digital_mode to %d\n", mode); 406 return incompatible_clock; 407 } 408